diff options
Diffstat (limited to 'include/asm-arm/arch-omap/gpmc.h')
| -rw-r--r-- | include/asm-arm/arch-omap/gpmc.h | 96 |
1 files changed, 0 insertions, 96 deletions
diff --git a/include/asm-arm/arch-omap/gpmc.h b/include/asm-arm/arch-omap/gpmc.h deleted file mode 100644 index 6a8e07ffc2d0..000000000000 --- a/include/asm-arm/arch-omap/gpmc.h +++ /dev/null | |||
| @@ -1,96 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * General-Purpose Memory Controller for OMAP2 | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005-2006 Nokia Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License version 2 as | ||
| 8 | * published by the Free Software Foundation. | ||
| 9 | */ | ||
| 10 | |||
| 11 | #ifndef __OMAP2_GPMC_H | ||
| 12 | #define __OMAP2_GPMC_H | ||
| 13 | |||
| 14 | #define GPMC_CS_CONFIG1 0x00 | ||
| 15 | #define GPMC_CS_CONFIG2 0x04 | ||
| 16 | #define GPMC_CS_CONFIG3 0x08 | ||
| 17 | #define GPMC_CS_CONFIG4 0x0c | ||
| 18 | #define GPMC_CS_CONFIG5 0x10 | ||
| 19 | #define GPMC_CS_CONFIG6 0x14 | ||
| 20 | #define GPMC_CS_CONFIG7 0x18 | ||
| 21 | #define GPMC_CS_NAND_COMMAND 0x1c | ||
| 22 | #define GPMC_CS_NAND_ADDRESS 0x20 | ||
| 23 | #define GPMC_CS_NAND_DATA 0x24 | ||
| 24 | |||
| 25 | #define GPMC_CONFIG1_WRAPBURST_SUPP (1 << 31) | ||
| 26 | #define GPMC_CONFIG1_READMULTIPLE_SUPP (1 << 30) | ||
| 27 | #define GPMC_CONFIG1_READTYPE_ASYNC (0 << 29) | ||
| 28 | #define GPMC_CONFIG1_READTYPE_SYNC (1 << 29) | ||
| 29 | #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28) | ||
| 30 | #define GPMC_CONFIG1_WRITETYPE_ASYNC (0 << 27) | ||
| 31 | #define GPMC_CONFIG1_WRITETYPE_SYNC (1 << 27) | ||
| 32 | #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) ((val & 3) << 25) | ||
| 33 | #define GPMC_CONFIG1_PAGE_LEN(val) ((val & 3) << 23) | ||
| 34 | #define GPMC_CONFIG1_WAIT_READ_MON (1 << 22) | ||
| 35 | #define GPMC_CONFIG1_WAIT_WRITE_MON (1 << 21) | ||
| 36 | #define GPMC_CONFIG1_WAIT_MON_IIME(val) ((val & 3) << 18) | ||
| 37 | #define GPMC_CONFIG1_WAIT_PIN_SEL(val) ((val & 3) << 16) | ||
| 38 | #define GPMC_CONFIG1_DEVICESIZE(val) ((val & 3) << 12) | ||
| 39 | #define GPMC_CONFIG1_DEVICESIZE_16 GPMC_CONFIG1_DEVICESIZE(1) | ||
| 40 | #define GPMC_CONFIG1_DEVICETYPE(val) ((val & 3) << 10) | ||
| 41 | #define GPMC_CONFIG1_DEVICETYPE_NOR GPMC_CONFIG1_DEVICETYPE(0) | ||
| 42 | #define GPMC_CONFIG1_DEVICETYPE_NAND GPMC_CONFIG1_DEVICETYPE(1) | ||
| 43 | #define GPMC_CONFIG1_MUXADDDATA (1 << 9) | ||
| 44 | #define GPMC_CONFIG1_TIME_PARA_GRAN (1 << 4) | ||
| 45 | #define GPMC_CONFIG1_FCLK_DIV(val) (val & 3) | ||
| 46 | #define GPMC_CONFIG1_FCLK_DIV2 (GPMC_CONFIG1_FCLK_DIV(1)) | ||
| 47 | #define GPMC_CONFIG1_FCLK_DIV3 (GPMC_CONFIG1_FCLK_DIV(2)) | ||
| 48 | #define GPMC_CONFIG1_FCLK_DIV4 (GPMC_CONFIG1_FCLK_DIV(3)) | ||
| 49 | |||
| 50 | /* | ||
| 51 | * Note that all values in this struct are in nanoseconds, while | ||
| 52 | * the register values are in gpmc_fck cycles. | ||
| 53 | */ | ||
| 54 | struct gpmc_timings { | ||
| 55 | /* Minimum clock period for synchronous mode */ | ||
| 56 | u16 sync_clk; | ||
| 57 | |||
| 58 | /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */ | ||
| 59 | u16 cs_on; /* Assertion time */ | ||
| 60 | u16 cs_rd_off; /* Read deassertion time */ | ||
| 61 | u16 cs_wr_off; /* Write deassertion time */ | ||
| 62 | |||
| 63 | /* ADV signal timings corresponding to GPMC_CONFIG3 */ | ||
| 64 | u16 adv_on; /* Assertion time */ | ||
| 65 | u16 adv_rd_off; /* Read deassertion time */ | ||
| 66 | u16 adv_wr_off; /* Write deassertion time */ | ||
| 67 | |||
| 68 | /* WE signals timings corresponding to GPMC_CONFIG4 */ | ||
| 69 | u16 we_on; /* WE assertion time */ | ||
| 70 | u16 we_off; /* WE deassertion time */ | ||
| 71 | |||
| 72 | /* OE signals timings corresponding to GPMC_CONFIG4 */ | ||
| 73 | u16 oe_on; /* OE assertion time */ | ||
| 74 | u16 oe_off; /* OE deassertion time */ | ||
| 75 | |||
| 76 | /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */ | ||
| 77 | u16 page_burst_access; /* Multiple access word delay */ | ||
| 78 | u16 access; /* Start-cycle to first data valid delay */ | ||
| 79 | u16 rd_cycle; /* Total read cycle time */ | ||
| 80 | u16 wr_cycle; /* Total write cycle time */ | ||
| 81 | }; | ||
| 82 | |||
| 83 | extern unsigned int gpmc_ns_to_ticks(unsigned int time_ns); | ||
| 84 | extern unsigned int gpmc_round_ns_to_ticks(unsigned int time_ns); | ||
| 85 | extern unsigned long gpmc_get_fclk_period(void); | ||
| 86 | |||
| 87 | extern void gpmc_cs_write_reg(int cs, int idx, u32 val); | ||
| 88 | extern u32 gpmc_cs_read_reg(int cs, int idx); | ||
| 89 | extern int gpmc_cs_calc_divider(int cs, unsigned int sync_clk); | ||
| 90 | extern int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t); | ||
| 91 | extern int gpmc_cs_request(int cs, unsigned long size, unsigned long *base); | ||
| 92 | extern void gpmc_cs_free(int cs); | ||
| 93 | extern int gpmc_cs_set_reserved(int cs, int reserved); | ||
| 94 | extern int gpmc_cs_reserved(int cs); | ||
| 95 | |||
| 96 | #endif | ||