1 files changed, 207 insertions, 54 deletions
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 04ebef5c6e95..ccbcb580a5c1 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,9 +22,109 @@
 #define __ASM_ARCH_DMA_H
 #define MAX_DMA_ADDRESS                 0xffffffff
+#define MAX_DMA_CHANNELS                0
+/* Hardware registers for omap1 */
+#define OMAP_DMA_BASE                   (0xfffed800)
+#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
+#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
+#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
+#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
+#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
+#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
+#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
+#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
+#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
+#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
+#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
+#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
+#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
+#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
+#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
+#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
+#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
+#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
+#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
+#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
+/* Hardware registers for omap2 */
+#define OMAP24XX_DMA_BASE               (L4_24XX_BASE + 0x56000)
+#define OMAP_DMA4_REVISION              (OMAP24XX_DMA_BASE + 0x00)
+#define OMAP_DMA4_GCR_REG               (OMAP24XX_DMA_BASE + 0x78)
+#define OMAP_DMA4_IRQSTATUS_L0          (OMAP24XX_DMA_BASE + 0x08)
+#define OMAP_DMA4_IRQSTATUS_L1          (OMAP24XX_DMA_BASE + 0x0c)
+#define OMAP_DMA4_IRQSTATUS_L2          (OMAP24XX_DMA_BASE + 0x10)
+#define OMAP_DMA4_IRQSTATUS_L3          (OMAP24XX_DMA_BASE + 0x14)
+#define OMAP_DMA4_IRQENABLE_L0          (OMAP24XX_DMA_BASE + 0x18)
+#define OMAP_DMA4_IRQENABLE_L1          (OMAP24XX_DMA_BASE + 0x1c)
+#define OMAP_DMA4_IRQENABLE_L2          (OMAP24XX_DMA_BASE + 0x20)
+#define OMAP_DMA4_IRQENABLE_L3          (OMAP24XX_DMA_BASE + 0x24)
+#define OMAP_DMA4_SYSSTATUS             (OMAP24XX_DMA_BASE + 0x28)
+#define OMAP_DMA4_CAPS_0                (OMAP24XX_DMA_BASE + 0x64)
+#define OMAP_DMA4_CAPS_2                (OMAP24XX_DMA_BASE + 0x6c)
+#define OMAP_DMA4_CAPS_3                (OMAP24XX_DMA_BASE + 0x70)
+#define OMAP_DMA4_CAPS_4                (OMAP24XX_DMA_BASE + 0x74)
+#ifdef CONFIG_ARCH_OMAP1
 #define OMAP_LOGICAL_DMA_CH_COUNT       17
+/* Common channel specific registers for omap1 */
+#define OMAP_DMA_CSDP_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
+#define OMAP_DMA_CCR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
+#define OMAP_DMA_CICR_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
+#define OMAP_DMA_CSR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
+#define OMAP_DMA_CEN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
+#define OMAP_DMA_CFN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
+#define OMAP_DMA_CSFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
+#define OMAP_DMA_CSEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
+#define OMAP_DMA_CSAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
+#define OMAP_DMA_CDAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
+#define OMAP_DMA_CDEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
+#define OMAP_DMA_CDFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
+#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
+#else
+#define OMAP_LOGICAL_DMA_CH_COUNT       32      /* REVISIT: Is this 32 + 2? */
+/* Common channel specific registers for omap2 */
+#define OMAP_DMA_CCR_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
+#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
+#define OMAP_DMA_CICR_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
+#define OMAP_DMA_CSR_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
+#define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
+#define OMAP_DMA_CEN_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
+#define OMAP_DMA_CFN_REG(n)             __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
+#define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
+#define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
+#define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
+#define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
+#define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
+#define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
+#endif
+/* Channel specific registers only on omap1 */
+#define OMAP1_DMA_CSSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
+#define OMAP1_DMA_CSSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
+#define OMAP1_DMA_CDSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
+#define OMAP1_DMA_CDSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
+#define OMAP1_DMA_COLOR_L_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
+#define OMAP1_DMA_CCR2_REG(n)           __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
+#define OMAP1_DMA_COLOR_U_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
+#define OMAP1_DMA_LCH_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+/* Channel specific registers only on omap2 */
+#define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
+#define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
+#define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
+#define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
+#define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
+/*----------------------------------------------------------------------------*/
+/* DMA channels for omap1 */
 #define OMAP_DMA_NO_DEVICE              0
 #define OMAP_DMA_MCSI1_TX               1
 #define OMAP_DMA_MCSI1_RX               2
@@ -85,29 +185,72 @@
 #define OMAP_DMA_MMC2_RX                55
 #define OMAP_DMA_CRYPTO_DES_OUT         56
+/* DMA channels for 24xx */
+#define OMAP24XX_DMA_NO_DEVICE          0
+#define OMAP24XX_DMA_XTI_DMA            1       /* S_DMA_0 */
+#define OMAP24XX_DMA_EXT_NDMA_REQ0      2       /* S_DMA_1 */
+#define OMAP24XX_DMA_EXT_NDMA_REQ1      3       /* S_DMA_2 */
+#define OMAP24XX_DMA_GPMC               4       /* S_DMA_3 */
+#define OMAP24XX_DMA_GFX                5       /* S_DMA_4 */
+#define OMAP24XX_DMA_DSS                6       /* S_DMA_5 */
+#define OMAP24XX_DMA_VLYNQ_TX           7       /* S_DMA_6 */
+#define OMAP24XX_DMA_CWT                8       /* S_DMA_7 */
+#define OMAP24XX_DMA_AES_TX             9       /* S_DMA_8 */
+#define OMAP24XX_DMA_AES_RX             10      /* S_DMA_9 */
+#define OMAP24XX_DMA_DES_TX             11      /* S_DMA_10 */
+#define OMAP24XX_DMA_DES_RX             12      /* S_DMA_11 */
+#define OMAP24XX_DMA_SHA1MD5_RX         13      /* S_DMA_12 */
-#define OMAP_DMA_BASE                   (0xfffed800)
+#define OMAP24XX_DMA_EAC_AC_RD          17      /* S_DMA_16 */
-#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
+#define OMAP24XX_DMA_EAC_AC_WR          18      /* S_DMA_17 */
-#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
+#define OMAP24XX_DMA_EAC_MD_UL_RD       19      /* S_DMA_18 */
-#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
+#define OMAP24XX_DMA_EAC_MD_UL_WR       20      /* S_DMA_19 */
-#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
+#define OMAP24XX_DMA_EAC_MD_DL_RD       21      /* S_DMA_20 */
-#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
+#define OMAP24XX_DMA_EAC_MD_DL_WR       22      /* S_DMA_21 */
-#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
+#define OMAP24XX_DMA_EAC_BT_UL_RD       23      /* S_DMA_22 */
-#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
+#define OMAP24XX_DMA_EAC_BT_UL_WR       24      /* S_DMA_23 */
-#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
+#define OMAP24XX_DMA_EAC_BT_DL_RD       25      /* S_DMA_24 */
-#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
+#define OMAP24XX_DMA_EAC_BT_DL_WR       26      /* S_DMA_25 */
-#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
+#define OMAP24XX_DMA_I2C1_TX            27      /* S_DMA_26 */
-#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
+#define OMAP24XX_DMA_I2C1_RX            28      /* S_DMA_27 */
-#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
+#define OMAP24XX_DMA_I2C2_TX            29      /* S_DMA_28 */
-#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
+#define OMAP24XX_DMA_I2C2_RX            30      /* S_DMA_29 */
-#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
+#define OMAP24XX_DMA_MCBSP1_TX          31      /* SDMA_30 */
-#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
+#define OMAP24XX_DMA_MCBSP1_RX          32      /* SDMA_31 */
-#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
+#define OMAP24XX_DMA_MCBSP2_TX          33      /* SDMA_32 */
-#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
+#define OMAP24XX_DMA_MCBSP2_RX          34      /* SDMA_33 */
-#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
+#define OMAP24XX_DMA_SPI1_TX0           35      /* SDMA_34 */
-#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
+#define OMAP24XX_DMA_SPI1_RX0           36      /* SDMA_35 */
-#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
+#define OMAP24XX_DMA_SPI1_TX1           37      /* SDMA_36 */
+#define OMAP24XX_DMA_SPI1_RX1           38      /* SDMA_37 */
+#define OMAP24XX_DMA_SPI1_TX2           39      /* SDMA_38 */
+#define OMAP24XX_DMA_SPI1_RX2           40      /* SDMA_39 */
+#define OMAP24XX_DMA_SPI1_TX3           41      /* SDMA_40 */
+#define OMAP24XX_DMA_SPI1_RX3           42      /* SDMA_41 */
+#define OMAP24XX_DMA_SPI2_TX0           43      /* SDMA_42 */
+#define OMAP24XX_DMA_SPI2_RX0           44      /* SDMA_43 */
+#define OMAP24XX_DMA_SPI2_TX1           45      /* SDMA_44 */
+#define OMAP24XX_DMA_SPI2_RX1           46      /* SDMA_45 */
+#define OMAP24XX_DMA_UART1_TX           49      /* SDMA_48 */
+#define OMAP24XX_DMA_UART1_RX           50      /* SDMA_49 */
+#define OMAP24XX_DMA_UART2_TX           51      /* SDMA_50 */
+#define OMAP24XX_DMA_UART2_RX           52      /* SDMA_51 */
+#define OMAP24XX_DMA_UART3_TX           53      /* SDMA_52 */
+#define OMAP24XX_DMA_UART3_RX           54      /* SDMA_53 */
+#define OMAP24XX_DMA_USB_W2FC_TX0       55      /* SDMA_54 */
+#define OMAP24XX_DMA_USB_W2FC_RX0       56      /* SDMA_55 */
+#define OMAP24XX_DMA_USB_W2FC_TX1       57      /* SDMA_56 */
+#define OMAP24XX_DMA_USB_W2FC_RX1       58      /* SDMA_57 */
+#define OMAP24XX_DMA_USB_W2FC_TX2       59      /* SDMA_58 */
+#define OMAP24XX_DMA_USB_W2FC_RX2       60      /* SDMA_59 */
+#define OMAP24XX_DMA_MMC1_TX            61      /* SDMA_60 */
+#define OMAP24XX_DMA_MMC1_RX            62      /* SDMA_61 */
+#define OMAP24XX_DMA_MS                 63      /* SDMA_62 */
+/*----------------------------------------------------------------------------*/
+/* Hardware registers for LCD DMA */
 #define OMAP1510_DMA_LCD_BASE           (0xfffedb00)
 #define OMAP1510_DMA_LCD_CTRL           (OMAP1510_DMA_LCD_BASE + 0x00)
 #define OMAP1510_DMA_LCD_TOP_F1_L       (OMAP1510_DMA_LCD_BASE + 0x02)
@@ -116,7 +259,7 @@
 #define OMAP1510_DMA_LCD_BOT_F1_U       (OMAP1510_DMA_LCD_BASE + 0x08)
 #define OMAP1610_DMA_LCD_BASE           (0xfffee300)
-#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
+#define OMAP1610_DMA_LCD_CSDP           (OMAP1610_DMA_LCD_BASE + 0xc0)
 #define OMAP1610_DMA_LCD_CCR            (OMAP1610_DMA_LCD_BASE + 0xc2)
 #define OMAP1610_DMA_LCD_CTRL           (OMAP1610_DMA_LCD_BASE + 0xc4)
 #define OMAP1610_DMA_LCD_TOP_B1_L       (OMAP1610_DMA_LCD_BASE + 0xc8)
@@ -134,37 +277,18 @@
 #define OMAP1610_DMA_LCD_LCH_CTRL       (OMAP1610_DMA_LCD_BASE + 0xea)
 #define OMAP1610_DMA_LCD_SRC_FI_B1_U    (OMAP1610_DMA_LCD_BASE + 0xf4)
+#define OMAP_DMA_TOUT_IRQ               (1 << 0)        /* Only on omap1 */
-/* Every LCh has its own set of the registers below */
-#define OMAP_DMA_CSDP(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
-#define OMAP_DMA_CCR(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
-#define OMAP_DMA_CICR(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
-#define OMAP_DMA_CSR(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
-#define OMAP_DMA_CSSA_L(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
-#define OMAP_DMA_CSSA_U(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
-#define OMAP_DMA_CDSA_L(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
-#define OMAP_DMA_CDSA_U(n)              (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
-#define OMAP_DMA_CEN(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
-#define OMAP_DMA_CFN(n)                 (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
-#define OMAP_DMA_CSFI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
-#define OMAP_DMA_CSEI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
-#define OMAP_DMA_CSAC(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
-#define OMAP_DMA_CDAC(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
-#define OMAP_DMA_CDEI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
-#define OMAP_DMA_CDFI(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
-#define OMAP_DMA_COLOR_L(n)             (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
-#define OMAP_DMA_COLOR_U(n)             (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
-#define OMAP_DMA_CCR2(n)                (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
-#define OMAP_DMA_CLNK_CTRL(n)           (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
-#define OMAP_DMA_LCH_CTRL(n)            (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
-#define OMAP_DMA_TOUT_IRQ               (1 << 0)
 #define OMAP_DMA_DROP_IRQ               (1 << 1)
 #define OMAP_DMA_HALF_IRQ               (1 << 2)
 #define OMAP_DMA_FRAME_IRQ              (1 << 3)
 #define OMAP_DMA_LAST_IRQ               (1 << 4)
 #define OMAP_DMA_BLOCK_IRQ              (1 << 5)
-#define OMAP_DMA_SYNC_IRQ               (1 << 6)
+#define OMAP1_DMA_SYNC_IRQ              (1 << 6)
+#define OMAP2_DMA_PKT_IRQ               (1 << 7)
+#define OMAP2_DMA_TRANS_ERR_IRQ         (1 << 8)
+#define OMAP2_DMA_SECURE_ERR_IRQ        (1 << 9)
+#define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
+#define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
 #define OMAP_DMA_DATA_TYPE_S8           0x00
 #define OMAP_DMA_DATA_TYPE_S16          0x01
@@ -194,6 +318,7 @@ enum {
        OMAP_LCD_DMA_B2_BOTTOM
 };
+/* REVISIT: Check if BURST_4 is really 1 (or 2) */
 enum omap_dma_burst_mode {
        OMAP_DMA_DATA_BURST_DIS = 0,
        OMAP_DMA_DATA_BURST_4,
@@ -206,6 +331,31 @@ enum omap_dma_color_mode {
        OMAP_DMA_TRANSPARENT_COPY
 };
+struct omap_dma_channel_params {
+        int data_type;          /* data type 8,16,32 */
+        int elem_count;         /* number of elements in a frame */
+        int frame_count;        /* number of frames in a element */
+        int src_port;           /* Only on OMAP1 REVISIT: Is this needed? */
+        int src_amode;          /* constant , post increment, indexed , double indexed */
+        int src_start;          /* source address : physical */
+        int src_ei;             /* source element index */
+        int src_fi;             /* source frame index */
+        int dst_port;           /* Only on OMAP1 REVISIT: Is this needed? */
+        int dst_amode;          /* constant , post increment, indexed , double indexed */
+        int dst_start;          /* source address : physical */
+        int dst_ei;             /* source element index */
+        int dst_fi;             /* source frame index */
+        int trigger;            /* trigger attached if the channel is synchronized */
+        int sync_mode;          /* sycn on element, frame , block or packet */
+        int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
+        int ie;                 /* interrupt enabled */
+};
 extern void omap_set_dma_priority(int dst_port, int priority);
 extern int omap_request_dma(int dev_id, const char *dev_name,
                            void (* callback)(int lch, u16 ch_status, void *data),
@@ -217,24 +367,30 @@ extern void omap_start_dma(int lch);
 extern void omap_stop_dma(int lch);
 extern void omap_set_dma_transfer_params(int lch, int data_type,
                                         int elem_count, int frame_count,
-                                         int sync_mode);
+                                         int sync_mode,
+                                         int dma_trigger, int src_or_dst_synch);
 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
                                    u32 color);
 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
-                                    unsigned long src_start);
+                                    unsigned long src_start,
+                                    int src_ei, int src_fi);
 extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
 extern void omap_set_dma_src_data_pack(int lch, int enable);
 extern void omap_set_dma_src_burst_mode(int lch,
                                        enum omap_dma_burst_mode burst_mode);
 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
-                                     unsigned long dest_start);
+                                     unsigned long dest_start,
+                                     int dst_ei, int dst_fi);
 extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
 extern void omap_set_dma_dest_data_pack(int lch, int enable);
 extern void omap_set_dma_dest_burst_mode(int lch,
                                         enum omap_dma_burst_mode burst_mode);
+extern void omap_set_dma_params(int lch,
+                                struct omap_dma_channel_params * params);
 extern void omap_dma_link_lch (int lch_head, int lch_queue);
 extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
@@ -244,9 +400,6 @@ extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
 extern int omap_dma_running(void);
-/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
-extern int omap_dma_in_1510_mode(void);
 /* LCD DMA functions */
 extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
                                void *data);

diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 04ebef5c6e95..ccbcb580a5c1 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h
@@ -22,9 +22,109 @@
22	#define __ASM_ARCH_DMA_H	22	#define __ASM_ARCH_DMA_H
23		23
24	#define MAX_DMA_ADDRESS 0xffffffff	24	#define MAX_DMA_ADDRESS 0xffffffff
		25	#define MAX_DMA_CHANNELS 0
		26
		27	/* Hardware registers for omap1 */
		28	#define OMAP_DMA_BASE (0xfffed800)
		29	#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)
		30	#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)
		31	#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)
		32	#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)
		33	#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)
		34	#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)
		35	#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)
		36	#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)
		37	#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)
		38	#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)
		39	#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)
		40	#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)
		41	#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)
		42	#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)
		43	#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)
		44	#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)
		45	#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)
		46	#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)
		47	#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)
		48	#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)
		49
		50	/* Hardware registers for omap2 */
		51	#define OMAP24XX_DMA_BASE (L4_24XX_BASE + 0x56000)
		52	#define OMAP_DMA4_REVISION (OMAP24XX_DMA_BASE + 0x00)
		53	#define OMAP_DMA4_GCR_REG (OMAP24XX_DMA_BASE + 0x78)
		54	#define OMAP_DMA4_IRQSTATUS_L0 (OMAP24XX_DMA_BASE + 0x08)
		55	#define OMAP_DMA4_IRQSTATUS_L1 (OMAP24XX_DMA_BASE + 0x0c)
		56	#define OMAP_DMA4_IRQSTATUS_L2 (OMAP24XX_DMA_BASE + 0x10)
		57	#define OMAP_DMA4_IRQSTATUS_L3 (OMAP24XX_DMA_BASE + 0x14)
		58	#define OMAP_DMA4_IRQENABLE_L0 (OMAP24XX_DMA_BASE + 0x18)
		59	#define OMAP_DMA4_IRQENABLE_L1 (OMAP24XX_DMA_BASE + 0x1c)
		60	#define OMAP_DMA4_IRQENABLE_L2 (OMAP24XX_DMA_BASE + 0x20)
		61	#define OMAP_DMA4_IRQENABLE_L3 (OMAP24XX_DMA_BASE + 0x24)
		62	#define OMAP_DMA4_SYSSTATUS (OMAP24XX_DMA_BASE + 0x28)
		63	#define OMAP_DMA4_CAPS_0 (OMAP24XX_DMA_BASE + 0x64)
		64	#define OMAP_DMA4_CAPS_2 (OMAP24XX_DMA_BASE + 0x6c)
		65	#define OMAP_DMA4_CAPS_3 (OMAP24XX_DMA_BASE + 0x70)
		66	#define OMAP_DMA4_CAPS_4 (OMAP24XX_DMA_BASE + 0x74)
		67
		68	#ifdef CONFIG_ARCH_OMAP1
25		69
26	#define OMAP_LOGICAL_DMA_CH_COUNT 17	70	#define OMAP_LOGICAL_DMA_CH_COUNT 17
27		71
		72	/* Common channel specific registers for omap1 */
		73	#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
		74	#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
		75	#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
		76	#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
		77	#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
		78	#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
		79	#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
		80	#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
		81	#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
		82	#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
		83	#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
		84	#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
		85	#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
		86
		87	#else
		88
		89	#define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
		90
		91	/* Common channel specific registers for omap2 */
		92	#define OMAP_DMA_CCR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x80)
		93	#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x84)
		94	#define OMAP_DMA_CICR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x88)
		95	#define OMAP_DMA_CSR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x8c)
		96	#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x90)
		97	#define OMAP_DMA_CEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x94)
		98	#define OMAP_DMA_CFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x98)
		99	#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa4)
		100	#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa8)
		101	#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xac)
		102	#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb0)
		103	#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb4)
		104	#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xb8)
		105
		106	#endif
		107
		108	/* Channel specific registers only on omap1 */
		109	#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
		110	#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
		111	#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
		112	#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
		113	#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
		114	#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
		115	#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
		116	#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
		117
		118	/* Channel specific registers only on omap2 */
		119	#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0x9c)
		120	#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xa0)
		121	#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xbc)
		122	#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc0)
		123	#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP24XX_DMA_BASE + 0x60 * (n) + 0xc4)
		124
		125	/----------------------------------------------------------------------------/
		126
		127	/* DMA channels for omap1 */
28	#define OMAP_DMA_NO_DEVICE 0	128	#define OMAP_DMA_NO_DEVICE 0
29	#define OMAP_DMA_MCSI1_TX 1	129	#define OMAP_DMA_MCSI1_TX 1
30	#define OMAP_DMA_MCSI1_RX 2	130	#define OMAP_DMA_MCSI1_RX 2
@@ -85,29 +185,72 @@
85	#define OMAP_DMA_MMC2_RX 55	185	#define OMAP_DMA_MMC2_RX 55
86	#define OMAP_DMA_CRYPTO_DES_OUT 56	186	#define OMAP_DMA_CRYPTO_DES_OUT 56
87		187
		188	/* DMA channels for 24xx */
		189	#define OMAP24XX_DMA_NO_DEVICE 0
		190	#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
		191	#define OMAP24XX_DMA_EXT_NDMA_REQ0 2 /* S_DMA_1 */
		192	#define OMAP24XX_DMA_EXT_NDMA_REQ1 3 /* S_DMA_2 */
		193	#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
		194	#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
		195	#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
		196	#define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */
		197	#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
		198	#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
		199	#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
		200	#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
		201	#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
		202	#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
88		203
89	#define OMAP_DMA_BASE (0xfffed800)	204	#define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */
90	#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)	205	#define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */
91	#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)	206	#define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
92	#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)	207	#define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
93	#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)	208	#define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
94	#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)	209	#define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
95	#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)	210	#define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
96	#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)	211	#define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
97	#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)	212	#define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
98	#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)	213	#define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
99	#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)	214	#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
100	#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)	215	#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
101	#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)	216	#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
102	#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)	217	#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
103	#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)	218	#define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */
104	#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)	219	#define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */
105	#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)	220	#define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */
106	#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)	221	#define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */
107	#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)	222	#define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */
108	#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)	223	#define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */
109	#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)	224	#define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */
		225	#define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */
		226	#define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */
		227	#define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */
		228	#define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */
		229	#define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */
		230	#define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */
		231	#define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */
		232	#define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */
		233	#define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */
110		234
		235	#define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */
		236	#define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */
		237	#define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */
		238	#define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */
		239	#define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */
		240	#define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */
		241	#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */
		242	#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */
		243	#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */
		244	#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */
		245	#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */
		246	#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */
		247	#define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */
		248	#define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */
		249	#define OMAP24XX_DMA_MS 63 /* SDMA_62 */
		250
		251	/----------------------------------------------------------------------------/
		252
		253	/* Hardware registers for LCD DMA */
111	#define OMAP1510_DMA_LCD_BASE (0xfffedb00)	254	#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
112	#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)	255	#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
113	#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)	256	#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
@@ -116,7 +259,7 @@
116	#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)	259	#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
117		260
118	#define OMAP1610_DMA_LCD_BASE (0xfffee300)	261	#define OMAP1610_DMA_LCD_BASE (0xfffee300)
119	#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)	262	#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
120	#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)	263	#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
121	#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)	264	#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
122	#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)	265	#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
@@ -134,37 +277,18 @@
134	#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)	277	#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
135	#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)	278	#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
136		279
137		280	#define OMAP_DMA_TOUT_IRQ (1 << 0) /* Only on omap1 */
138	/* Every LCh has its own set of the registers below */
139	#define OMAP_DMA_CSDP(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x00)
140	#define OMAP_DMA_CCR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x02)
141	#define OMAP_DMA_CICR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x04)
142	#define OMAP_DMA_CSR(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x06)
143	#define OMAP_DMA_CSSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x08)
144	#define OMAP_DMA_CSSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
145	#define OMAP_DMA_CDSA_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
146	#define OMAP_DMA_CDSA_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
147	#define OMAP_DMA_CEN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x10)
148	#define OMAP_DMA_CFN(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x12)
149	#define OMAP_DMA_CSFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x14)
150	#define OMAP_DMA_CSEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x16)
151	#define OMAP_DMA_CSAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x18)
152	#define OMAP_DMA_CDAC(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
153	#define OMAP_DMA_CDEI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
154	#define OMAP_DMA_CDFI(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
155	#define OMAP_DMA_COLOR_L(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x20)
156	#define OMAP_DMA_COLOR_U(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x22)
157	#define OMAP_DMA_CCR2(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x24)
158	#define OMAP_DMA_CLNK_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x28)
159	#define OMAP_DMA_LCH_CTRL(n) (OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
160
161	#define OMAP_DMA_TOUT_IRQ (1 << 0)
162	#define OMAP_DMA_DROP_IRQ (1 << 1)	281	#define OMAP_DMA_DROP_IRQ (1 << 1)
163	#define OMAP_DMA_HALF_IRQ (1 << 2)	282	#define OMAP_DMA_HALF_IRQ (1 << 2)
164	#define OMAP_DMA_FRAME_IRQ (1 << 3)	283	#define OMAP_DMA_FRAME_IRQ (1 << 3)
165	#define OMAP_DMA_LAST_IRQ (1 << 4)	284	#define OMAP_DMA_LAST_IRQ (1 << 4)
166	#define OMAP_DMA_BLOCK_IRQ (1 << 5)	285	#define OMAP_DMA_BLOCK_IRQ (1 << 5)
167	#define OMAP_DMA_SYNC_IRQ (1 << 6)	286	#define OMAP1_DMA_SYNC_IRQ (1 << 6)
		287	#define OMAP2_DMA_PKT_IRQ (1 << 7)
		288	#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
		289	#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
		290	#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
		291	#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
168		292
169	#define OMAP_DMA_DATA_TYPE_S8 0x00	293	#define OMAP_DMA_DATA_TYPE_S8 0x00
170	#define OMAP_DMA_DATA_TYPE_S16 0x01	294	#define OMAP_DMA_DATA_TYPE_S16 0x01
@@ -194,6 +318,7 @@ enum {
194	OMAP_LCD_DMA_B2_BOTTOM	318	OMAP_LCD_DMA_B2_BOTTOM
195	};	319	};
196		320
		321	/* REVISIT: Check if BURST_4 is really 1 (or 2) */
197	enum omap_dma_burst_mode {	322	enum omap_dma_burst_mode {
198	OMAP_DMA_DATA_BURST_DIS = 0,	323	OMAP_DMA_DATA_BURST_DIS = 0,
199	OMAP_DMA_DATA_BURST_4,	324	OMAP_DMA_DATA_BURST_4,
@@ -206,6 +331,31 @@ enum omap_dma_color_mode {
206	OMAP_DMA_TRANSPARENT_COPY	331	OMAP_DMA_TRANSPARENT_COPY
207	};	332	};
208		333
		334	struct omap_dma_channel_params {
		335	int data_type; /* data type 8,16,32 */
		336	int elem_count; /* number of elements in a frame */
		337	int frame_count; /* number of frames in a element */
		338
		339	int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
		340	int src_amode; /* constant , post increment, indexed , double indexed */
		341	int src_start; /* source address : physical */
		342	int src_ei; /* source element index */
		343	int src_fi; /* source frame index */
		344
		345	int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
		346	int dst_amode; /* constant , post increment, indexed , double indexed */
		347	int dst_start; /* source address : physical */
		348	int dst_ei; /* source element index */
		349	int dst_fi; /* source frame index */
		350
		351	int trigger; /* trigger attached if the channel is synchronized */
		352	int sync_mode; /* sycn on element, frame , block or packet */
		353	int src_or_dst_synch; /* source synch(1) or destination synch(0) */
		354
		355	int ie; /* interrupt enabled */
		356	};
		357
		358
209	extern void omap_set_dma_priority(int dst_port, int priority);	359	extern void omap_set_dma_priority(int dst_port, int priority);
210	extern int omap_request_dma(int dev_id, const char *dev_name,	360	extern int omap_request_dma(int dev_id, const char *dev_name,
211	void (* callback)(int lch, u16 ch_status, void *data),	361	void (* callback)(int lch, u16 ch_status, void *data),
@@ -217,24 +367,30 @@ extern void omap_start_dma(int lch);
217	extern void omap_stop_dma(int lch);	367	extern void omap_stop_dma(int lch);
218	extern void omap_set_dma_transfer_params(int lch, int data_type,	368	extern void omap_set_dma_transfer_params(int lch, int data_type,
219	int elem_count, int frame_count,	369	int elem_count, int frame_count,
220	int sync_mode);	370	int sync_mode,
		371	int dma_trigger, int src_or_dst_synch);
221	extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,	372	extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
222	u32 color);	373	u32 color);
223		374
224	extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,	375	extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
225	unsigned long src_start);	376	unsigned long src_start,
		377	int src_ei, int src_fi);
226	extern void omap_set_dma_src_index(int lch, int eidx, int fidx);	378	extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
227	extern void omap_set_dma_src_data_pack(int lch, int enable);	379	extern void omap_set_dma_src_data_pack(int lch, int enable);
228	extern void omap_set_dma_src_burst_mode(int lch,	380	extern void omap_set_dma_src_burst_mode(int lch,
229	enum omap_dma_burst_mode burst_mode);	381	enum omap_dma_burst_mode burst_mode);
230		382
231	extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,	383	extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
232	unsigned long dest_start);	384	unsigned long dest_start,
		385	int dst_ei, int dst_fi);
233	extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);	386	extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
234	extern void omap_set_dma_dest_data_pack(int lch, int enable);	387	extern void omap_set_dma_dest_data_pack(int lch, int enable);
235	extern void omap_set_dma_dest_burst_mode(int lch,	388	extern void omap_set_dma_dest_burst_mode(int lch,
236	enum omap_dma_burst_mode burst_mode);	389	enum omap_dma_burst_mode burst_mode);
237		390
		391	extern void omap_set_dma_params(int lch,
		392	struct omap_dma_channel_params * params);
		393
238	extern void omap_dma_link_lch (int lch_head, int lch_queue);	394	extern void omap_dma_link_lch (int lch_head, int lch_queue);
239	extern void omap_dma_unlink_lch (int lch_head, int lch_queue);	395	extern void omap_dma_unlink_lch (int lch_head, int lch_queue);
240		396
@@ -244,9 +400,6 @@ extern int omap_get_dma_src_addr_counter(int lch);
244	extern void omap_clear_dma(int lch);	400	extern void omap_clear_dma(int lch);
245	extern int omap_dma_running(void);	401	extern int omap_dma_running(void);
246		402
247	/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
248	extern int omap_dma_in_1510_mode(void);
249
250	/* LCD DMA functions */	403	/* LCD DMA functions */
251	extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),	404	extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
252	void *data);	405	void *data);