diff options
Diffstat (limited to 'include/asm-arm/arch-omap/dma.h')
| -rw-r--r-- | include/asm-arm/arch-omap/dma.h | 378 |
1 files changed, 226 insertions, 152 deletions
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 24acf090030d..f4dcb9587869 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h | |||
| @@ -22,108 +22,128 @@ | |||
| 22 | #define __ASM_ARCH_DMA_H | 22 | #define __ASM_ARCH_DMA_H |
| 23 | 23 | ||
| 24 | /* Hardware registers for omap1 */ | 24 | /* Hardware registers for omap1 */ |
| 25 | #define OMAP_DMA_BASE (0xfffed800) | 25 | #define OMAP1_DMA_BASE (0xfffed800) |
| 26 | #define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400) | 26 | |
| 27 | #define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404) | 27 | #define OMAP1_DMA_GCR 0x400 |
| 28 | #define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408) | 28 | #define OMAP1_DMA_GSCR 0x404 |
| 29 | #define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442) | 29 | #define OMAP1_DMA_GRST 0x408 |
| 30 | #define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444) | 30 | #define OMAP1_DMA_HW_ID 0x442 |
| 31 | #define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446) | 31 | #define OMAP1_DMA_PCH2_ID 0x444 |
| 32 | #define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448) | 32 | #define OMAP1_DMA_PCH0_ID 0x446 |
| 33 | #define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a) | 33 | #define OMAP1_DMA_PCH1_ID 0x448 |
| 34 | #define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c) | 34 | #define OMAP1_DMA_PCHG_ID 0x44a |
| 35 | #define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e) | 35 | #define OMAP1_DMA_PCHD_ID 0x44c |
| 36 | #define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450) | 36 | #define OMAP1_DMA_CAPS_0_U 0x44e |
| 37 | #define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452) | 37 | #define OMAP1_DMA_CAPS_0_L 0x450 |
| 38 | #define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454) | 38 | #define OMAP1_DMA_CAPS_1_U 0x452 |
| 39 | #define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456) | 39 | #define OMAP1_DMA_CAPS_1_L 0x454 |
| 40 | #define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458) | 40 | #define OMAP1_DMA_CAPS_2 0x456 |
| 41 | #define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a) | 41 | #define OMAP1_DMA_CAPS_3 0x458 |
| 42 | #define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460) | 42 | #define OMAP1_DMA_CAPS_4 0x45a |
| 43 | #define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480) | 43 | #define OMAP1_DMA_PCH2_SR 0x460 |
| 44 | #define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482) | 44 | #define OMAP1_DMA_PCH0_SR 0x480 |
| 45 | #define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0) | 45 | #define OMAP1_DMA_PCH1_SR 0x482 |
| 46 | 46 | #define OMAP1_DMA_PCHD_SR 0x4c0 | |
| 47 | /* Hardware registers for omap2 */ | 47 | |
| 48 | #if defined(CONFIG_ARCH_OMAP3) | 48 | /* Hardware registers for omap2 and omap3 */ |
| 49 | #define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000) | 49 | #define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000) |
| 50 | #else /* CONFIG_ARCH_OMAP2 */ | 50 | #define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000) |
| 51 | #define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000) | 51 | |
| 52 | #endif | 52 | #define OMAP_DMA4_REVISION 0x00 |
| 53 | 53 | #define OMAP_DMA4_GCR 0x78 | |
| 54 | #define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00) | 54 | #define OMAP_DMA4_IRQSTATUS_L0 0x08 |
| 55 | #define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78) | 55 | #define OMAP_DMA4_IRQSTATUS_L1 0x0c |
| 56 | #define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08) | 56 | #define OMAP_DMA4_IRQSTATUS_L2 0x10 |
| 57 | #define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c) | 57 | #define OMAP_DMA4_IRQSTATUS_L3 0x14 |
| 58 | #define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10) | 58 | #define OMAP_DMA4_IRQENABLE_L0 0x18 |
| 59 | #define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14) | 59 | #define OMAP_DMA4_IRQENABLE_L1 0x1c |
| 60 | #define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18) | 60 | #define OMAP_DMA4_IRQENABLE_L2 0x20 |
| 61 | #define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c) | 61 | #define OMAP_DMA4_IRQENABLE_L3 0x24 |
| 62 | #define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20) | 62 | #define OMAP_DMA4_SYSSTATUS 0x28 |
| 63 | #define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24) | 63 | #define OMAP_DMA4_OCP_SYSCONFIG 0x2c |
| 64 | #define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28) | 64 | #define OMAP_DMA4_CAPS_0 0x64 |
| 65 | #define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c) | 65 | #define OMAP_DMA4_CAPS_2 0x6c |
| 66 | #define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64) | 66 | #define OMAP_DMA4_CAPS_3 0x70 |
| 67 | #define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c) | 67 | #define OMAP_DMA4_CAPS_4 0x74 |
| 68 | #define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70) | 68 | |
| 69 | #define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74) | 69 | #define OMAP1_LOGICAL_DMA_CH_COUNT 17 |
| 70 | 70 | #define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ | |
| 71 | #ifdef CONFIG_ARCH_OMAP1 | ||
| 72 | |||
| 73 | #define OMAP_LOGICAL_DMA_CH_COUNT 17 | ||
| 74 | 71 | ||
| 75 | /* Common channel specific registers for omap1 */ | 72 | /* Common channel specific registers for omap1 */ |
| 76 | #define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00) | 73 | #define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00) |
| 77 | #define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02) | 74 | #define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00) |
| 78 | #define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04) | 75 | #define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02) |
| 79 | #define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06) | 76 | #define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04) |
| 80 | #define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10) | 77 | #define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06) |
| 81 | #define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12) | 78 | #define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10) |
| 82 | #define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14) | 79 | #define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12) |
| 83 | #define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16) | 80 | #define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14) |
| 84 | #define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18) | 81 | #define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16) |
| 85 | #define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a) | 82 | #define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */ |
| 86 | #define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c) | 83 | #define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18) |
| 87 | #define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e) | 84 | #define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a) |
| 88 | #define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28) | 85 | #define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c) |
| 89 | 86 | #define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e) | |
| 90 | #else | 87 | #define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28) |
| 91 | |||
| 92 | #define OMAP_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */ | ||
| 93 | 88 | ||
| 94 | /* Common channel specific registers for omap2 */ | 89 | /* Common channel specific registers for omap2 */ |
| 95 | #define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80) | 90 | #define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80) |
| 96 | #define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84) | 91 | #define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80) |
| 97 | #define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88) | 92 | #define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84) |
| 98 | #define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c) | 93 | #define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88) |
| 99 | #define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90) | 94 | #define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c) |
| 100 | #define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94) | 95 | #define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90) |
| 101 | #define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98) | 96 | #define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94) |
| 102 | #define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4) | 97 | #define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98) |
| 103 | #define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8) | 98 | #define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4) |
| 104 | #define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac) | 99 | #define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8) |
| 105 | #define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0) | 100 | #define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac) |
| 106 | #define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4) | 101 | #define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0) |
| 107 | #define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8) | 102 | #define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4) |
| 108 | 103 | #define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8) | |
| 109 | #endif | ||
| 110 | 104 | ||
| 111 | /* Channel specific registers only on omap1 */ | 105 | /* Channel specific registers only on omap1 */ |
| 112 | #define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08) | 106 | #define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08) |
| 113 | #define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a) | 107 | #define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a) |
| 114 | #define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c) | 108 | #define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c) |
| 115 | #define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e) | 109 | #define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e) |
| 116 | #define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20) | 110 | #define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20) |
| 117 | #define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24) | 111 | #define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22) |
| 118 | #define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22) | 112 | #define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24) |
| 119 | #define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a) | 113 | #define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */ |
| 114 | #define OMAP1_DMA_CCEN(n) 0 | ||
| 115 | #define OMAP1_DMA_CCFN(n) 0 | ||
| 120 | 116 | ||
| 121 | /* Channel specific registers only on omap2 */ | 117 | /* Channel specific registers only on omap2 */ |
| 122 | #define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c) | 118 | #define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c) |
| 123 | #define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0) | 119 | #define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0) |
| 124 | #define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc) | 120 | #define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc) |
| 125 | #define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0) | 121 | #define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0) |
| 126 | #define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4) | 122 | #define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4) |
| 123 | |||
| 124 | /* Dummy defines to keep multi-omap compiles happy */ | ||
| 125 | #define OMAP1_DMA_REVISION 0 | ||
| 126 | #define OMAP1_DMA_IRQSTATUS_L0 0 | ||
| 127 | #define OMAP1_DMA_IRQENABLE_L0 0 | ||
| 128 | #define OMAP1_DMA_OCP_SYSCONFIG 0 | ||
| 129 | #define OMAP_DMA4_HW_ID 0 | ||
| 130 | #define OMAP_DMA4_CAPS_0_L 0 | ||
| 131 | #define OMAP_DMA4_CAPS_0_U 0 | ||
| 132 | #define OMAP_DMA4_CAPS_1_L 0 | ||
| 133 | #define OMAP_DMA4_CAPS_1_U 0 | ||
| 134 | #define OMAP_DMA4_GSCR 0 | ||
| 135 | #define OMAP_DMA4_CPC(n) 0 | ||
| 136 | |||
| 137 | #define OMAP_DMA4_LCH_CTRL(n) 0 | ||
| 138 | #define OMAP_DMA4_COLOR_L(n) 0 | ||
| 139 | #define OMAP_DMA4_COLOR_U(n) 0 | ||
| 140 | #define OMAP_DMA4_CCR2(n) 0 | ||
| 141 | #define OMAP1_DMA_CSSA(n) 0 | ||
| 142 | #define OMAP1_DMA_CDSA(n) 0 | ||
| 143 | #define OMAP_DMA4_CSSA_L(n) 0 | ||
| 144 | #define OMAP_DMA4_CSSA_U(n) 0 | ||
| 145 | #define OMAP_DMA4_CDSA_L(n) 0 | ||
| 146 | #define OMAP_DMA4_CDSA_U(n) 0 | ||
| 127 | 147 | ||
| 128 | /*----------------------------------------------------------------------------*/ | 148 | /*----------------------------------------------------------------------------*/ |
| 129 | 149 | ||
| @@ -196,63 +216,98 @@ | |||
| 196 | #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ | 216 | #define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */ |
| 197 | #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ | 217 | #define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */ |
| 198 | #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ | 218 | #define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */ |
| 199 | #define OMAP24XX_DMA_VLYNQ_TX 7 /* S_DMA_6 */ | 219 | #define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */ |
| 220 | #define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */ | ||
| 200 | #define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ | 221 | #define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */ |
| 201 | #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ | 222 | #define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */ |
| 202 | #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ | 223 | #define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */ |
| 203 | #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ | 224 | #define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */ |
| 204 | #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ | 225 | #define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */ |
| 205 | #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ | 226 | #define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */ |
| 206 | #define OMAP24XX_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ | 227 | #define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */ |
| 207 | #define OMAP24XX_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ | 228 | #define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */ |
| 208 | #define OMAP24XX_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ | 229 | #define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */ |
| 209 | #define OMAP24XX_DMA_EAC_AC_RD 17 /* S_DMA_16 */ | 230 | #define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */ |
| 210 | #define OMAP24XX_DMA_EAC_AC_WR 18 /* S_DMA_17 */ | 231 | #define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */ |
| 211 | #define OMAP24XX_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ | 232 | #define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */ |
| 212 | #define OMAP24XX_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ | 233 | #define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */ |
| 213 | #define OMAP24XX_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ | 234 | #define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */ |
| 214 | #define OMAP24XX_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ | 235 | #define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */ |
| 215 | #define OMAP24XX_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ | 236 | #define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */ |
| 216 | #define OMAP24XX_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ | 237 | #define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */ |
| 217 | #define OMAP24XX_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ | 238 | #define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */ |
| 218 | #define OMAP24XX_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ | 239 | #define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */ |
| 240 | #define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */ | ||
| 241 | #define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */ | ||
| 242 | #define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */ | ||
| 243 | #define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */ | ||
| 244 | #define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */ | ||
| 245 | #define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */ | ||
| 246 | #define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */ | ||
| 247 | #define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */ | ||
| 248 | #define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */ | ||
| 249 | #define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */ | ||
| 250 | #define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */ | ||
| 251 | #define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */ | ||
| 252 | #define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */ | ||
| 253 | #define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */ | ||
| 254 | #define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */ | ||
| 255 | #define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */ | ||
| 219 | #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ | 256 | #define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */ |
| 220 | #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ | 257 | #define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */ |
| 221 | #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ | 258 | #define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */ |
| 222 | #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ | 259 | #define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */ |
| 223 | #define OMAP24XX_DMA_MCBSP1_TX 31 /* SDMA_30 */ | 260 | #define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */ |
| 224 | #define OMAP24XX_DMA_MCBSP1_RX 32 /* SDMA_31 */ | 261 | #define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */ |
| 225 | #define OMAP24XX_DMA_MCBSP2_TX 33 /* SDMA_32 */ | 262 | #define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */ |
| 226 | #define OMAP24XX_DMA_MCBSP2_RX 34 /* SDMA_33 */ | 263 | #define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */ |
| 227 | #define OMAP24XX_DMA_SPI1_TX0 35 /* SDMA_34 */ | 264 | #define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */ |
| 228 | #define OMAP24XX_DMA_SPI1_RX0 36 /* SDMA_35 */ | 265 | #define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */ |
| 229 | #define OMAP24XX_DMA_SPI1_TX1 37 /* SDMA_36 */ | 266 | #define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */ |
| 230 | #define OMAP24XX_DMA_SPI1_RX1 38 /* SDMA_37 */ | 267 | #define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */ |
| 231 | #define OMAP24XX_DMA_SPI1_TX2 39 /* SDMA_38 */ | 268 | #define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */ |
| 232 | #define OMAP24XX_DMA_SPI1_RX2 40 /* SDMA_39 */ | 269 | #define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */ |
| 233 | #define OMAP24XX_DMA_SPI1_TX3 41 /* SDMA_40 */ | 270 | #define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */ |
| 234 | #define OMAP24XX_DMA_SPI1_RX3 42 /* SDMA_41 */ | 271 | #define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */ |
| 235 | #define OMAP24XX_DMA_SPI2_TX0 43 /* SDMA_42 */ | 272 | #define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */ |
| 236 | #define OMAP24XX_DMA_SPI2_RX0 44 /* SDMA_43 */ | 273 | #define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */ |
| 237 | #define OMAP24XX_DMA_SPI2_TX1 45 /* SDMA_44 */ | 274 | #define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */ |
| 238 | #define OMAP24XX_DMA_SPI2_RX1 46 /* SDMA_45 */ | 275 | #define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */ |
| 239 | 276 | #define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */ | |
| 240 | #define OMAP24XX_DMA_UART1_TX 49 /* SDMA_48 */ | 277 | #define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */ |
| 241 | #define OMAP24XX_DMA_UART1_RX 50 /* SDMA_49 */ | 278 | #define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */ |
| 242 | #define OMAP24XX_DMA_UART2_TX 51 /* SDMA_50 */ | 279 | #define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */ |
| 243 | #define OMAP24XX_DMA_UART2_RX 52 /* SDMA_51 */ | 280 | #define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */ |
| 244 | #define OMAP24XX_DMA_UART3_TX 53 /* SDMA_52 */ | 281 | #define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */ |
| 245 | #define OMAP24XX_DMA_UART3_RX 54 /* SDMA_53 */ | 282 | #define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */ |
| 246 | #define OMAP24XX_DMA_USB_W2FC_TX0 55 /* SDMA_54 */ | 283 | #define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */ |
| 247 | #define OMAP24XX_DMA_USB_W2FC_RX0 56 /* SDMA_55 */ | 284 | #define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */ |
| 248 | #define OMAP24XX_DMA_USB_W2FC_TX1 57 /* SDMA_56 */ | 285 | #define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */ |
| 249 | #define OMAP24XX_DMA_USB_W2FC_RX1 58 /* SDMA_57 */ | 286 | #define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */ |
| 250 | #define OMAP24XX_DMA_USB_W2FC_TX2 59 /* SDMA_58 */ | 287 | #define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */ |
| 251 | #define OMAP24XX_DMA_USB_W2FC_RX2 60 /* SDMA_59 */ | 288 | #define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */ |
| 252 | #define OMAP24XX_DMA_MMC1_TX 61 /* SDMA_60 */ | 289 | #define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */ |
| 253 | #define OMAP24XX_DMA_MMC1_RX 62 /* SDMA_61 */ | 290 | #define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */ |
| 254 | #define OMAP24XX_DMA_MS 63 /* SDMA_62 */ | 291 | #define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */ |
| 255 | #define OMAP24XX_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ | 292 | #define OMAP24XX_DMA_MS 63 /* S_DMA_62 */ |
| 293 | #define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */ | ||
| 294 | #define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */ | ||
| 295 | #define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */ | ||
| 296 | #define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */ | ||
| 297 | #define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */ | ||
| 298 | #define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */ | ||
| 299 | #define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */ | ||
| 300 | #define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */ | ||
| 301 | #define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */ | ||
| 302 | #define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */ | ||
| 303 | #define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */ | ||
| 304 | #define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */ | ||
| 305 | #define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */ | ||
| 306 | #define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */ | ||
| 307 | #define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */ | ||
| 308 | #define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */ | ||
| 309 | #define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */ | ||
| 310 | #define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */ | ||
| 256 | 311 | ||
| 257 | /*----------------------------------------------------------------------------*/ | 312 | /*----------------------------------------------------------------------------*/ |
| 258 | 313 | ||
| @@ -358,6 +413,11 @@ enum omap_dma_burst_mode { | |||
| 358 | OMAP_DMA_DATA_BURST_16, | 413 | OMAP_DMA_DATA_BURST_16, |
| 359 | }; | 414 | }; |
| 360 | 415 | ||
| 416 | enum end_type { | ||
| 417 | OMAP_DMA_LITTLE_ENDIAN = 0, | ||
| 418 | OMAP_DMA_BIG_ENDIAN | ||
| 419 | }; | ||
| 420 | |||
| 361 | enum omap_dma_color_mode { | 421 | enum omap_dma_color_mode { |
| 362 | OMAP_DMA_COLOR_DIS = 0, | 422 | OMAP_DMA_COLOR_DIS = 0, |
| 363 | OMAP_DMA_CONSTANT_FILL, | 423 | OMAP_DMA_CONSTANT_FILL, |
| @@ -370,24 +430,34 @@ enum omap_dma_write_mode { | |||
| 370 | OMAP_DMA_WRITE_LAST_NON_POSTED | 430 | OMAP_DMA_WRITE_LAST_NON_POSTED |
| 371 | }; | 431 | }; |
| 372 | 432 | ||
| 433 | enum omap_dma_channel_mode { | ||
| 434 | OMAP_DMA_LCH_2D = 0, | ||
| 435 | OMAP_DMA_LCH_G, | ||
| 436 | OMAP_DMA_LCH_P, | ||
| 437 | OMAP_DMA_LCH_PD | ||
| 438 | }; | ||
| 439 | |||
| 373 | struct omap_dma_channel_params { | 440 | struct omap_dma_channel_params { |
| 374 | int data_type; /* data type 8,16,32 */ | 441 | int data_type; /* data type 8,16,32 */ |
| 375 | int elem_count; /* number of elements in a frame */ | 442 | int elem_count; /* number of elements in a frame */ |
| 376 | int frame_count; /* number of frames in a element */ | 443 | int frame_count; /* number of frames in a element */ |
| 377 | 444 | ||
| 378 | int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ | 445 | int src_port; /* Only on OMAP1 REVISIT: Is this needed? */ |
| 379 | int src_amode; /* constant , post increment, indexed , double indexed */ | 446 | int src_amode; /* constant, post increment, indexed, |
| 447 | double indexed */ | ||
| 380 | unsigned long src_start; /* source address : physical */ | 448 | unsigned long src_start; /* source address : physical */ |
| 381 | int src_ei; /* source element index */ | 449 | int src_ei; /* source element index */ |
| 382 | int src_fi; /* source frame index */ | 450 | int src_fi; /* source frame index */ |
| 383 | 451 | ||
| 384 | int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ | 452 | int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */ |
| 385 | int dst_amode; /* constant , post increment, indexed , double indexed */ | 453 | int dst_amode; /* constant, post increment, indexed, |
| 454 | double indexed */ | ||
| 386 | unsigned long dst_start; /* source address : physical */ | 455 | unsigned long dst_start; /* source address : physical */ |
| 387 | int dst_ei; /* source element index */ | 456 | int dst_ei; /* source element index */ |
| 388 | int dst_fi; /* source frame index */ | 457 | int dst_fi; /* source frame index */ |
| 389 | 458 | ||
| 390 | int trigger; /* trigger attached if the channel is synchronized */ | 459 | int trigger; /* trigger attached if the channel is |
| 460 | synchronized */ | ||
| 391 | int sync_mode; /* sycn on element, frame , block or packet */ | 461 | int sync_mode; /* sycn on element, frame , block or packet */ |
| 392 | int src_or_dst_synch; /* source synch(1) or destination synch(0) */ | 462 | int src_or_dst_synch; /* source synch(1) or destination synch(0) */ |
| 393 | 463 | ||
| @@ -404,8 +474,8 @@ struct omap_dma_channel_params { | |||
| 404 | 474 | ||
| 405 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); | 475 | extern void omap_set_dma_priority(int lch, int dst_port, int priority); |
| 406 | extern int omap_request_dma(int dev_id, const char *dev_name, | 476 | extern int omap_request_dma(int dev_id, const char *dev_name, |
| 407 | void (* callback)(int lch, u16 ch_status, void *data), | 477 | void (*callback)(int lch, u16 ch_status, void *data), |
| 408 | void *data, int *dma_ch); | 478 | void *data, int *dma_ch); |
| 409 | extern void omap_enable_dma_irq(int ch, u16 irq_bits); | 479 | extern void omap_enable_dma_irq(int ch, u16 irq_bits); |
| 410 | extern void omap_disable_dma_irq(int ch, u16 irq_bits); | 480 | extern void omap_disable_dma_irq(int ch, u16 irq_bits); |
| 411 | extern void omap_free_dma(int ch); | 481 | extern void omap_free_dma(int ch); |
| @@ -418,6 +488,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type, | |||
| 418 | extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, | 488 | extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, |
| 419 | u32 color); | 489 | u32 color); |
| 420 | extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); | 490 | extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode); |
| 491 | extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode); | ||
| 421 | 492 | ||
| 422 | extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, | 493 | extern void omap_set_dma_src_params(int lch, int src_port, int src_amode, |
| 423 | unsigned long src_start, | 494 | unsigned long src_start, |
| @@ -436,23 +507,26 @@ extern void omap_set_dma_dest_burst_mode(int lch, | |||
| 436 | enum omap_dma_burst_mode burst_mode); | 507 | enum omap_dma_burst_mode burst_mode); |
| 437 | 508 | ||
| 438 | extern void omap_set_dma_params(int lch, | 509 | extern void omap_set_dma_params(int lch, |
| 439 | struct omap_dma_channel_params * params); | 510 | struct omap_dma_channel_params *params); |
| 440 | 511 | ||
| 441 | extern void omap_dma_link_lch (int lch_head, int lch_queue); | 512 | extern void omap_dma_link_lch(int lch_head, int lch_queue); |
| 442 | extern void omap_dma_unlink_lch (int lch_head, int lch_queue); | 513 | extern void omap_dma_unlink_lch(int lch_head, int lch_queue); |
| 443 | 514 | ||
| 444 | extern int omap_set_dma_callback(int lch, | 515 | extern int omap_set_dma_callback(int lch, |
| 445 | void (* callback)(int lch, u16 ch_status, void *data), | 516 | void (*callback)(int lch, u16 ch_status, void *data), |
| 446 | void *data); | 517 | void *data); |
| 447 | extern dma_addr_t omap_get_dma_src_pos(int lch); | 518 | extern dma_addr_t omap_get_dma_src_pos(int lch); |
| 448 | extern dma_addr_t omap_get_dma_dst_pos(int lch); | 519 | extern dma_addr_t omap_get_dma_dst_pos(int lch); |
| 449 | extern int omap_get_dma_src_addr_counter(int lch); | ||
| 450 | extern void omap_clear_dma(int lch); | 520 | extern void omap_clear_dma(int lch); |
| 521 | extern int omap_get_dma_active_status(int lch); | ||
| 451 | extern int omap_dma_running(void); | 522 | extern int omap_dma_running(void); |
| 452 | extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, | 523 | extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth, |
| 453 | int tparams); | 524 | int tparams); |
| 454 | extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, | 525 | extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio, |
| 455 | unsigned char write_prio); | 526 | unsigned char write_prio); |
| 527 | extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype); | ||
| 528 | extern void omap_set_dma_src_endian_type(int lch, enum end_type etype); | ||
| 529 | extern int omap_get_dma_index(int lch, int *ei, int *fi); | ||
| 456 | 530 | ||
| 457 | /* Chaining APIs */ | 531 | /* Chaining APIs */ |
| 458 | #ifndef CONFIG_ARCH_OMAP1 | 532 | #ifndef CONFIG_ARCH_OMAP1 |
| @@ -478,7 +552,7 @@ extern int omap_dma_chain_status(int chain_id); | |||
| 478 | #endif | 552 | #endif |
| 479 | 553 | ||
| 480 | /* LCD DMA functions */ | 554 | /* LCD DMA functions */ |
| 481 | extern int omap_request_lcd_dma(void (* callback)(u16 status, void *data), | 555 | extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data), |
| 482 | void *data); | 556 | void *data); |
| 483 | extern void omap_free_lcd_dma(void); | 557 | extern void omap_free_lcd_dma(void); |
| 484 | extern void omap_setup_lcd_dma(void); | 558 | extern void omap_setup_lcd_dma(void); |