1 files changed, 120 insertions, 90 deletions
diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
index 46fe5a40a25e..d188100f8f45 100644
--- a/include/asm-arm/arch-omap/dma.h
+++ b/include/asm-arm/arch-omap/dma.h
@@ -22,107 +22,128 @@
 #define __ASM_ARCH_DMA_H
 /* Hardware registers for omap1 */
-#define OMAP_DMA_BASE                   (0xfffed800)
+#define OMAP1_DMA_BASE                  (0xfffed800)
-#define OMAP_DMA_GCR                    (OMAP_DMA_BASE + 0x400)
-#define OMAP_DMA_GSCR                   (OMAP_DMA_BASE + 0x404)
+#define OMAP1_DMA_GCR                   0x400
-#define OMAP_DMA_GRST                   (OMAP_DMA_BASE + 0x408)
+#define OMAP1_DMA_GSCR                  0x404
-#define OMAP_DMA_HW_ID                  (OMAP_DMA_BASE + 0x442)
+#define OMAP1_DMA_GRST                  0x408
-#define OMAP_DMA_PCH2_ID                (OMAP_DMA_BASE + 0x444)
+#define OMAP1_DMA_HW_ID                 0x442
-#define OMAP_DMA_PCH0_ID                (OMAP_DMA_BASE + 0x446)
+#define OMAP1_DMA_PCH2_ID               0x444
-#define OMAP_DMA_PCH1_ID                (OMAP_DMA_BASE + 0x448)
+#define OMAP1_DMA_PCH0_ID               0x446
-#define OMAP_DMA_PCHG_ID                (OMAP_DMA_BASE + 0x44a)
+#define OMAP1_DMA_PCH1_ID               0x448
-#define OMAP_DMA_PCHD_ID                (OMAP_DMA_BASE + 0x44c)
+#define OMAP1_DMA_PCHG_ID               0x44a
-#define OMAP_DMA_CAPS_0_U               (OMAP_DMA_BASE + 0x44e)
+#define OMAP1_DMA_PCHD_ID               0x44c
-#define OMAP_DMA_CAPS_0_L               (OMAP_DMA_BASE + 0x450)
+#define OMAP1_DMA_CAPS_0_U              0x44e
-#define OMAP_DMA_CAPS_1_U               (OMAP_DMA_BASE + 0x452)
+#define OMAP1_DMA_CAPS_0_L              0x450
-#define OMAP_DMA_CAPS_1_L               (OMAP_DMA_BASE + 0x454)
+#define OMAP1_DMA_CAPS_1_U              0x452
-#define OMAP_DMA_CAPS_2                 (OMAP_DMA_BASE + 0x456)
+#define OMAP1_DMA_CAPS_1_L              0x454
-#define OMAP_DMA_CAPS_3                 (OMAP_DMA_BASE + 0x458)
+#define OMAP1_DMA_CAPS_2                0x456
-#define OMAP_DMA_CAPS_4                 (OMAP_DMA_BASE + 0x45a)
+#define OMAP1_DMA_CAPS_3                0x458
-#define OMAP_DMA_PCH2_SR                (OMAP_DMA_BASE + 0x460)
+#define OMAP1_DMA_CAPS_4                0x45a
-#define OMAP_DMA_PCH0_SR                (OMAP_DMA_BASE + 0x480)
+#define OMAP1_DMA_PCH2_SR               0x460
-#define OMAP_DMA_PCH1_SR                (OMAP_DMA_BASE + 0x482)
+#define OMAP1_DMA_PCH0_SR               0x480
-#define OMAP_DMA_PCHD_SR                (OMAP_DMA_BASE + 0x4c0)
+#define OMAP1_DMA_PCH1_SR               0x482
+#define OMAP1_DMA_PCHD_SR               0x4c0
-/* Hardware registers for omap2 */
-#if defined(CONFIG_ARCH_OMAP3)
+/* Hardware registers for omap2 and omap3 */
-#define OMAP_DMA4_BASE                  (L4_34XX_BASE + 0x56000)
+#define OMAP24XX_DMA4_BASE              (L4_24XX_BASE + 0x56000)
-#else   /* CONFIG_ARCH_OMAP2 */
+#define OMAP34XX_DMA4_BASE              (L4_34XX_BASE + 0x56000)
-#define OMAP_DMA4_BASE                  (L4_24XX_BASE + 0x56000)
-#endif
+#define OMAP_DMA4_REVISION              0x00
+#define OMAP_DMA4_GCR                   0x78
-#define OMAP_DMA4_REVISION              (OMAP_DMA4_BASE + 0x00)
+#define OMAP_DMA4_IRQSTATUS_L0          0x08
-#define OMAP_DMA4_GCR_REG               (OMAP_DMA4_BASE + 0x78)
+#define OMAP_DMA4_IRQSTATUS_L1          0x0c
-#define OMAP_DMA4_IRQSTATUS_L0          (OMAP_DMA4_BASE + 0x08)
+#define OMAP_DMA4_IRQSTATUS_L2          0x10
-#define OMAP_DMA4_IRQSTATUS_L1          (OMAP_DMA4_BASE + 0x0c)
+#define OMAP_DMA4_IRQSTATUS_L3          0x14
-#define OMAP_DMA4_IRQSTATUS_L2          (OMAP_DMA4_BASE + 0x10)
+#define OMAP_DMA4_IRQENABLE_L0          0x18
-#define OMAP_DMA4_IRQSTATUS_L3          (OMAP_DMA4_BASE + 0x14)
+#define OMAP_DMA4_IRQENABLE_L1          0x1c
-#define OMAP_DMA4_IRQENABLE_L0          (OMAP_DMA4_BASE + 0x18)
+#define OMAP_DMA4_IRQENABLE_L2          0x20
-#define OMAP_DMA4_IRQENABLE_L1          (OMAP_DMA4_BASE + 0x1c)
+#define OMAP_DMA4_IRQENABLE_L3          0x24
-#define OMAP_DMA4_IRQENABLE_L2          (OMAP_DMA4_BASE + 0x20)
+#define OMAP_DMA4_SYSSTATUS             0x28
-#define OMAP_DMA4_IRQENABLE_L3          (OMAP_DMA4_BASE + 0x24)
+#define OMAP_DMA4_OCP_SYSCONFIG         0x2c
-#define OMAP_DMA4_SYSSTATUS             (OMAP_DMA4_BASE + 0x28)
+#define OMAP_DMA4_CAPS_0                0x64
-#define OMAP_DMA4_OCP_SYSCONFIG         (OMAP_DMA4_BASE + 0x2c)
+#define OMAP_DMA4_CAPS_2                0x6c
-#define OMAP_DMA4_CAPS_0                (OMAP_DMA4_BASE + 0x64)
+#define OMAP_DMA4_CAPS_3                0x70
-#define OMAP_DMA4_CAPS_2                (OMAP_DMA4_BASE + 0x6c)
+#define OMAP_DMA4_CAPS_4                0x74
-#define OMAP_DMA4_CAPS_3                (OMAP_DMA4_BASE + 0x70)
-#define OMAP_DMA4_CAPS_4                (OMAP_DMA4_BASE + 0x74)
 #define OMAP1_LOGICAL_DMA_CH_COUNT      17
 #define OMAP_DMA4_LOGICAL_DMA_CH_COUNT  32      /* REVISIT: Is this 32 + 2? */
-#ifdef CONFIG_ARCH_OMAP1
 /* Common channel specific registers for omap1 */
-#define OMAP_DMA_CSDP_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)
+#define OMAP1_DMA_CH_BASE(n)            (0x40 * (n) + 0x00)
-#define OMAP_DMA_CCR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)
+#define OMAP1_DMA_CSDP(n)               (0x40 * (n) + 0x00)
-#define OMAP_DMA_CICR_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)
+#define OMAP1_DMA_CCR(n)                (0x40 * (n) + 0x02)
-#define OMAP_DMA_CSR_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)
+#define OMAP1_DMA_CICR(n)               (0x40 * (n) + 0x04)
-#define OMAP_DMA_CEN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)
+#define OMAP1_DMA_CSR(n)                (0x40 * (n) + 0x06)
-#define OMAP_DMA_CFN_REG(n)             __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)
+#define OMAP1_DMA_CEN(n)                (0x40 * (n) + 0x10)
-#define OMAP_DMA_CSFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)
+#define OMAP1_DMA_CFN(n)                (0x40 * (n) + 0x12)
-#define OMAP_DMA_CSEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)
+#define OMAP1_DMA_CSFI(n)               (0x40 * (n) + 0x14)
-#define OMAP_DMA_CSAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)
+#define OMAP1_DMA_CSEI(n)               (0x40 * (n) + 0x16)
-#define OMAP_DMA_CDAC_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)
+#define OMAP1_DMA_CPC(n)                (0x40 * (n) + 0x18)     /* 15xx only */
-#define OMAP_DMA_CDEI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)
+#define OMAP1_DMA_CSAC(n)               (0x40 * (n) + 0x18)
-#define OMAP_DMA_CDFI_REG(n)            __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)
+#define OMAP1_DMA_CDAC(n)               (0x40 * (n) + 0x1a)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)
+#define OMAP1_DMA_CDEI(n)               (0x40 * (n) + 0x1c)
+#define OMAP1_DMA_CDFI(n)               (0x40 * (n) + 0x1e)
-#else
+#define OMAP1_DMA_CLNK_CTRL(n)          (0x40 * (n) + 0x28)
 /* Common channel specific registers for omap2 */
-#define OMAP_DMA_CCR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)
+#define OMAP_DMA4_CH_BASE(n)            (0x60 * (n) + 0x80)
-#define OMAP_DMA_CLNK_CTRL_REG(n)       __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)
+#define OMAP_DMA4_CCR(n)                (0x60 * (n) + 0x80)
-#define OMAP_DMA_CICR_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)
+#define OMAP_DMA4_CLNK_CTRL(n)          (0x60 * (n) + 0x84)
-#define OMAP_DMA_CSR_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)
+#define OMAP_DMA4_CICR(n)               (0x60 * (n) + 0x88)
-#define OMAP_DMA_CSDP_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)
+#define OMAP_DMA4_CSR(n)                (0x60 * (n) + 0x8c)
-#define OMAP_DMA_CEN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)
+#define OMAP_DMA4_CSDP(n)               (0x60 * (n) + 0x90)
-#define OMAP_DMA_CFN_REG(n)             __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)
+#define OMAP_DMA4_CEN(n)                (0x60 * (n) + 0x94)
-#define OMAP_DMA_CSEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)
+#define OMAP_DMA4_CFN(n)                (0x60 * (n) + 0x98)
-#define OMAP_DMA_CSFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)
+#define OMAP_DMA4_CSEI(n)               (0x60 * (n) + 0xa4)
-#define OMAP_DMA_CDEI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)
+#define OMAP_DMA4_CSFI(n)               (0x60 * (n) + 0xa8)
-#define OMAP_DMA_CDFI_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)
+#define OMAP_DMA4_CDEI(n)               (0x60 * (n) + 0xac)
-#define OMAP_DMA_CSAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)
+#define OMAP_DMA4_CDFI(n)               (0x60 * (n) + 0xb0)
-#define OMAP_DMA_CDAC_REG(n)            __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)
+#define OMAP_DMA4_CSAC(n)               (0x60 * (n) + 0xb4)
+#define OMAP_DMA4_CDAC(n)               (0x60 * (n) + 0xb8)
-#endif
 /* Channel specific registers only on omap1 */
-#define OMAP1_DMA_CSSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)
+#define OMAP1_DMA_CSSA_L(n)             (0x40 * (n) + 0x08)
-#define OMAP1_DMA_CSSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)
+#define OMAP1_DMA_CSSA_U(n)             (0x40 * (n) + 0x0a)
-#define OMAP1_DMA_CDSA_L_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)
+#define OMAP1_DMA_CDSA_L(n)             (0x40 * (n) + 0x0c)
-#define OMAP1_DMA_CDSA_U_REG(n)         __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)
+#define OMAP1_DMA_CDSA_U(n)             (0x40 * (n) + 0x0e)
-#define OMAP1_DMA_COLOR_L_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)
+#define OMAP1_DMA_COLOR_L(n)            (0x40 * (n) + 0x20)
-#define OMAP1_DMA_CCR2_REG(n)           __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)
+#define OMAP1_DMA_COLOR_U(n)            (0x40 * (n) + 0x22)
-#define OMAP1_DMA_COLOR_U_REG(n)        __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)
+#define OMAP1_DMA_CCR2(n)               (0x40 * (n) + 0x24)
-#define OMAP1_DMA_LCH_CTRL_REG(n)       __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)
+#define OMAP1_DMA_LCH_CTRL(n)           (0x40 * (n) + 0x2a)     /* not on 15xx */
+#define OMAP1_DMA_CCEN(n)               0
+#define OMAP1_DMA_CCFN(n)               0
 /* Channel specific registers only on omap2 */
-#define OMAP2_DMA_CSSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)
+#define OMAP_DMA4_CSSA(n)               (0x60 * (n) + 0x9c)
-#define OMAP2_DMA_CDSA_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)
+#define OMAP_DMA4_CDSA(n)               (0x60 * (n) + 0xa0)
-#define OMAP2_DMA_CCEN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)
+#define OMAP_DMA4_CCEN(n)               (0x60 * (n) + 0xbc)
-#define OMAP2_DMA_CCFN_REG(n)           __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)
+#define OMAP_DMA4_CCFN(n)               (0x60 * (n) + 0xc0)
-#define OMAP2_DMA_COLOR_REG(n)          __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)
+#define OMAP_DMA4_COLOR(n)              (0x60 * (n) + 0xc4)
+/* Dummy defines to keep multi-omap compiles happy */
+#define OMAP1_DMA_REVISION              0
+#define OMAP1_DMA_IRQSTATUS_L0          0
+#define OMAP1_DMA_IRQENABLE_L0          0
+#define OMAP1_DMA_OCP_SYSCONFIG         0
+#define OMAP_DMA4_HW_ID                 0
+#define OMAP_DMA4_CAPS_0_L              0
+#define OMAP_DMA4_CAPS_0_U              0
+#define OMAP_DMA4_CAPS_1_L              0
+#define OMAP_DMA4_CAPS_1_U              0
+#define OMAP_DMA4_GSCR                  0
+#define OMAP_DMA4_CPC(n)                0
+#define OMAP_DMA4_LCH_CTRL(n)           0
+#define OMAP_DMA4_COLOR_L(n)            0
+#define OMAP_DMA4_COLOR_U(n)            0
+#define OMAP_DMA4_CCR2(n)               0
+#define OMAP1_DMA_CSSA(n)               0
+#define OMAP1_DMA_CDSA(n)               0
+#define OMAP_DMA4_CSSA_L(n)             0
+#define OMAP_DMA4_CSSA_U(n)             0
+#define OMAP_DMA4_CDSA_L(n)             0
+#define OMAP_DMA4_CDSA_U(n)             0
 /*----------------------------------------------------------------------------*/
@@ -369,6 +390,13 @@ enum omap_dma_write_mode {
        OMAP_DMA_WRITE_LAST_NON_POSTED
 };
+enum omap_dma_channel_mode {
+        OMAP_DMA_LCH_2D = 0,
+        OMAP_DMA_LCH_G,
+        OMAP_DMA_LCH_P,
+        OMAP_DMA_LCH_PD
+};
 struct omap_dma_channel_params {
        int data_type;          /* data type 8,16,32 */
        int elem_count;         /* number of elements in a frame */
@@ -417,6 +445,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
 extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
                                    u32 color);
 extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
+extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
                                    unsigned long src_start,
@@ -447,6 +476,7 @@ extern dma_addr_t omap_get_dma_src_pos(int lch);
 extern dma_addr_t omap_get_dma_dst_pos(int lch);
 extern int omap_get_dma_src_addr_counter(int lch);
 extern void omap_clear_dma(int lch);
+extern int omap_get_dma_active_status(int lch);
 extern int omap_dma_running(void);
 extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
                                       int tparams);

diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h index 46fe5a40a25e..d188100f8f45 100644 --- a/include/asm-arm/arch-omap/dma.h +++ b/include/asm-arm/arch-omap/dma.h
@@ -22,107 +22,128 @@
22	#define __ASM_ARCH_DMA_H	22	#define __ASM_ARCH_DMA_H
23		23
24	/* Hardware registers for omap1 */	24	/* Hardware registers for omap1 */
25	#define OMAP_DMA_BASE (0xfffed800)	25	#define OMAP1_DMA_BASE (0xfffed800)
26	#define OMAP_DMA_GCR (OMAP_DMA_BASE + 0x400)	26
27	#define OMAP_DMA_GSCR (OMAP_DMA_BASE + 0x404)	27	#define OMAP1_DMA_GCR 0x400
28	#define OMAP_DMA_GRST (OMAP_DMA_BASE + 0x408)	28	#define OMAP1_DMA_GSCR 0x404
29	#define OMAP_DMA_HW_ID (OMAP_DMA_BASE + 0x442)	29	#define OMAP1_DMA_GRST 0x408
30	#define OMAP_DMA_PCH2_ID (OMAP_DMA_BASE + 0x444)	30	#define OMAP1_DMA_HW_ID 0x442
31	#define OMAP_DMA_PCH0_ID (OMAP_DMA_BASE + 0x446)	31	#define OMAP1_DMA_PCH2_ID 0x444
32	#define OMAP_DMA_PCH1_ID (OMAP_DMA_BASE + 0x448)	32	#define OMAP1_DMA_PCH0_ID 0x446
33	#define OMAP_DMA_PCHG_ID (OMAP_DMA_BASE + 0x44a)	33	#define OMAP1_DMA_PCH1_ID 0x448
34	#define OMAP_DMA_PCHD_ID (OMAP_DMA_BASE + 0x44c)	34	#define OMAP1_DMA_PCHG_ID 0x44a
35	#define OMAP_DMA_CAPS_0_U (OMAP_DMA_BASE + 0x44e)	35	#define OMAP1_DMA_PCHD_ID 0x44c
36	#define OMAP_DMA_CAPS_0_L (OMAP_DMA_BASE + 0x450)	36	#define OMAP1_DMA_CAPS_0_U 0x44e
37	#define OMAP_DMA_CAPS_1_U (OMAP_DMA_BASE + 0x452)	37	#define OMAP1_DMA_CAPS_0_L 0x450
38	#define OMAP_DMA_CAPS_1_L (OMAP_DMA_BASE + 0x454)	38	#define OMAP1_DMA_CAPS_1_U 0x452
39	#define OMAP_DMA_CAPS_2 (OMAP_DMA_BASE + 0x456)	39	#define OMAP1_DMA_CAPS_1_L 0x454
40	#define OMAP_DMA_CAPS_3 (OMAP_DMA_BASE + 0x458)	40	#define OMAP1_DMA_CAPS_2 0x456
41	#define OMAP_DMA_CAPS_4 (OMAP_DMA_BASE + 0x45a)	41	#define OMAP1_DMA_CAPS_3 0x458
42	#define OMAP_DMA_PCH2_SR (OMAP_DMA_BASE + 0x460)	42	#define OMAP1_DMA_CAPS_4 0x45a
43	#define OMAP_DMA_PCH0_SR (OMAP_DMA_BASE + 0x480)	43	#define OMAP1_DMA_PCH2_SR 0x460
44	#define OMAP_DMA_PCH1_SR (OMAP_DMA_BASE + 0x482)	44	#define OMAP1_DMA_PCH0_SR 0x480
45	#define OMAP_DMA_PCHD_SR (OMAP_DMA_BASE + 0x4c0)	45	#define OMAP1_DMA_PCH1_SR 0x482
46		46	#define OMAP1_DMA_PCHD_SR 0x4c0
47	/* Hardware registers for omap2 */	47
48	#if defined(CONFIG_ARCH_OMAP3)	48	/* Hardware registers for omap2 and omap3 */
49	#define OMAP_DMA4_BASE (L4_34XX_BASE + 0x56000)	49	#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50	#else /* CONFIG_ARCH_OMAP2 */	50	#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51	#define OMAP_DMA4_BASE (L4_24XX_BASE + 0x56000)	51
52	#endif	52	#define OMAP_DMA4_REVISION 0x00
53		53	#define OMAP_DMA4_GCR 0x78
54	#define OMAP_DMA4_REVISION (OMAP_DMA4_BASE + 0x00)	54	#define OMAP_DMA4_IRQSTATUS_L0 0x08
55	#define OMAP_DMA4_GCR_REG (OMAP_DMA4_BASE + 0x78)	55	#define OMAP_DMA4_IRQSTATUS_L1 0x0c
56	#define OMAP_DMA4_IRQSTATUS_L0 (OMAP_DMA4_BASE + 0x08)	56	#define OMAP_DMA4_IRQSTATUS_L2 0x10
57	#define OMAP_DMA4_IRQSTATUS_L1 (OMAP_DMA4_BASE + 0x0c)	57	#define OMAP_DMA4_IRQSTATUS_L3 0x14
58	#define OMAP_DMA4_IRQSTATUS_L2 (OMAP_DMA4_BASE + 0x10)	58	#define OMAP_DMA4_IRQENABLE_L0 0x18
59	#define OMAP_DMA4_IRQSTATUS_L3 (OMAP_DMA4_BASE + 0x14)	59	#define OMAP_DMA4_IRQENABLE_L1 0x1c
60	#define OMAP_DMA4_IRQENABLE_L0 (OMAP_DMA4_BASE + 0x18)	60	#define OMAP_DMA4_IRQENABLE_L2 0x20
61	#define OMAP_DMA4_IRQENABLE_L1 (OMAP_DMA4_BASE + 0x1c)	61	#define OMAP_DMA4_IRQENABLE_L3 0x24
62	#define OMAP_DMA4_IRQENABLE_L2 (OMAP_DMA4_BASE + 0x20)	62	#define OMAP_DMA4_SYSSTATUS 0x28
63	#define OMAP_DMA4_IRQENABLE_L3 (OMAP_DMA4_BASE + 0x24)	63	#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
64	#define OMAP_DMA4_SYSSTATUS (OMAP_DMA4_BASE + 0x28)	64	#define OMAP_DMA4_CAPS_0 0x64
65	#define OMAP_DMA4_OCP_SYSCONFIG (OMAP_DMA4_BASE + 0x2c)	65	#define OMAP_DMA4_CAPS_2 0x6c
66	#define OMAP_DMA4_CAPS_0 (OMAP_DMA4_BASE + 0x64)	66	#define OMAP_DMA4_CAPS_3 0x70
67	#define OMAP_DMA4_CAPS_2 (OMAP_DMA4_BASE + 0x6c)	67	#define OMAP_DMA4_CAPS_4 0x74
68	#define OMAP_DMA4_CAPS_3 (OMAP_DMA4_BASE + 0x70)
69	#define OMAP_DMA4_CAPS_4 (OMAP_DMA4_BASE + 0x74)
70		68
71	#define OMAP1_LOGICAL_DMA_CH_COUNT 17	69	#define OMAP1_LOGICAL_DMA_CH_COUNT 17
72	#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */	70	#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
73		71
74	#ifdef CONFIG_ARCH_OMAP1
75
76	/* Common channel specific registers for omap1 */	72	/* Common channel specific registers for omap1 */
77	#define OMAP_DMA_CSDP_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x00)	73	#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
78	#define OMAP_DMA_CCR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x02)	74	#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
79	#define OMAP_DMA_CICR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x04)	75	#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
80	#define OMAP_DMA_CSR_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x06)	76	#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
81	#define OMAP_DMA_CEN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x10)	77	#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
82	#define OMAP_DMA_CFN_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x12)	78	#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
83	#define OMAP_DMA_CSFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x14)	79	#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
84	#define OMAP_DMA_CSEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x16)	80	#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
85	#define OMAP_DMA_CSAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x18)	81	#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
86	#define OMAP_DMA_CDAC_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1a)	82	#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
87	#define OMAP_DMA_CDEI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1c)	83	#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
88	#define OMAP_DMA_CDFI_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x1e)	84	#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
89	#define OMAP_DMA_CLNK_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x28)	85	#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
90		86	#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
91	#else	87	#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
92		88
93	/* Common channel specific registers for omap2 */	89	/* Common channel specific registers for omap2 */
94	#define OMAP_DMA_CCR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x80)	90	#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
95	#define OMAP_DMA_CLNK_CTRL_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x84)	91	#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
96	#define OMAP_DMA_CICR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x88)	92	#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
97	#define OMAP_DMA_CSR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x8c)	93	#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
98	#define OMAP_DMA_CSDP_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x90)	94	#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
99	#define OMAP_DMA_CEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x94)	95	#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
100	#define OMAP_DMA_CFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x98)	96	#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
101	#define OMAP_DMA_CSEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa4)	97	#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
102	#define OMAP_DMA_CSFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa8)	98	#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
103	#define OMAP_DMA_CDEI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xac)	99	#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
104	#define OMAP_DMA_CDFI_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb0)	100	#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
105	#define OMAP_DMA_CSAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb4)	101	#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
106	#define OMAP_DMA_CDAC_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xb8)	102	#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
107		103	#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
108	#endif
109		104
110	/* Channel specific registers only on omap1 */	105	/* Channel specific registers only on omap1 */
111	#define OMAP1_DMA_CSSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x08)	106	#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
112	#define OMAP1_DMA_CSSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0a)	107	#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
113	#define OMAP1_DMA_CDSA_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0c)	108	#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
114	#define OMAP1_DMA_CDSA_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x0e)	109	#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
115	#define OMAP1_DMA_COLOR_L_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x20)	110	#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
116	#define OMAP1_DMA_CCR2_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x24)	111	#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
117	#define OMAP1_DMA_COLOR_U_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x22)	112	#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
118	#define OMAP1_DMA_LCH_CTRL_REG(n) __REG16(OMAP_DMA_BASE + 0x40 * (n) + 0x2a)	113	#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
		114	#define OMAP1_DMA_CCEN(n) 0
		115	#define OMAP1_DMA_CCFN(n) 0
119		116
120	/* Channel specific registers only on omap2 */	117	/* Channel specific registers only on omap2 */
121	#define OMAP2_DMA_CSSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0x9c)	118	#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
122	#define OMAP2_DMA_CDSA_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xa0)	119	#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
123	#define OMAP2_DMA_CCEN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xbc)	120	#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
124	#define OMAP2_DMA_CCFN_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc0)	121	#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
125	#define OMAP2_DMA_COLOR_REG(n) __REG32(OMAP_DMA4_BASE + 0x60 * (n) + 0xc4)	122	#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
		123
		124	/* Dummy defines to keep multi-omap compiles happy */
		125	#define OMAP1_DMA_REVISION 0
		126	#define OMAP1_DMA_IRQSTATUS_L0 0
		127	#define OMAP1_DMA_IRQENABLE_L0 0
		128	#define OMAP1_DMA_OCP_SYSCONFIG 0
		129	#define OMAP_DMA4_HW_ID 0
		130	#define OMAP_DMA4_CAPS_0_L 0
		131	#define OMAP_DMA4_CAPS_0_U 0
		132	#define OMAP_DMA4_CAPS_1_L 0
		133	#define OMAP_DMA4_CAPS_1_U 0
		134	#define OMAP_DMA4_GSCR 0
		135	#define OMAP_DMA4_CPC(n) 0
		136
		137	#define OMAP_DMA4_LCH_CTRL(n) 0
		138	#define OMAP_DMA4_COLOR_L(n) 0
		139	#define OMAP_DMA4_COLOR_U(n) 0
		140	#define OMAP_DMA4_CCR2(n) 0
		141	#define OMAP1_DMA_CSSA(n) 0
		142	#define OMAP1_DMA_CDSA(n) 0
		143	#define OMAP_DMA4_CSSA_L(n) 0
		144	#define OMAP_DMA4_CSSA_U(n) 0
		145	#define OMAP_DMA4_CDSA_L(n) 0
		146	#define OMAP_DMA4_CDSA_U(n) 0
126		147
127	/----------------------------------------------------------------------------/	148	/----------------------------------------------------------------------------/
128		149
@@ -369,6 +390,13 @@ enum omap_dma_write_mode {
369	OMAP_DMA_WRITE_LAST_NON_POSTED	390	OMAP_DMA_WRITE_LAST_NON_POSTED
370	};	391	};
371		392
		393	enum omap_dma_channel_mode {
		394	OMAP_DMA_LCH_2D = 0,
		395	OMAP_DMA_LCH_G,
		396	OMAP_DMA_LCH_P,
		397	OMAP_DMA_LCH_PD
		398	};
		399
372	struct omap_dma_channel_params {	400	struct omap_dma_channel_params {
373	int data_type; /* data type 8,16,32 */	401	int data_type; /* data type 8,16,32 */
374	int elem_count; /* number of elements in a frame */	402	int elem_count; /* number of elements in a frame */
@@ -417,6 +445,7 @@ extern void omap_set_dma_transfer_params(int lch, int data_type,
417	extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,	445	extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
418	u32 color);	446	u32 color);
419	extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);	447	extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
		448	extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
420		449
421	extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,	450	extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
422	unsigned long src_start,	451	unsigned long src_start,
@@ -447,6 +476,7 @@ extern dma_addr_t omap_get_dma_src_pos(int lch);
447	extern dma_addr_t omap_get_dma_dst_pos(int lch);	476	extern dma_addr_t omap_get_dma_dst_pos(int lch);
448	extern int omap_get_dma_src_addr_counter(int lch);	477	extern int omap_get_dma_src_addr_counter(int lch);
449	extern void omap_clear_dma(int lch);	478	extern void omap_clear_dma(int lch);
		479	extern int omap_get_dma_active_status(int lch);
450	extern int omap_dma_running(void);	480	extern int omap_dma_running(void);
451	extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,	481	extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
452	int tparams);	482	int tparams);