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-rw-r--r--include/asm-arm/arch-omap/dma.h570
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diff --git a/include/asm-arm/arch-omap/dma.h b/include/asm-arm/arch-omap/dma.h
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--- a/include/asm-arm/arch-omap/dma.h
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@@ -1,570 +0,0 @@
1/*
2 * linux/include/asm-arm/arch-omap/dma.h
3 *
4 * Copyright (C) 2003 Nokia Corporation
5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21#ifndef __ASM_ARCH_DMA_H
22#define __ASM_ARCH_DMA_H
23
24/* Hardware registers for omap1 */
25#define OMAP1_DMA_BASE (0xfffed800)
26
27#define OMAP1_DMA_GCR 0x400
28#define OMAP1_DMA_GSCR 0x404
29#define OMAP1_DMA_GRST 0x408
30#define OMAP1_DMA_HW_ID 0x442
31#define OMAP1_DMA_PCH2_ID 0x444
32#define OMAP1_DMA_PCH0_ID 0x446
33#define OMAP1_DMA_PCH1_ID 0x448
34#define OMAP1_DMA_PCHG_ID 0x44a
35#define OMAP1_DMA_PCHD_ID 0x44c
36#define OMAP1_DMA_CAPS_0_U 0x44e
37#define OMAP1_DMA_CAPS_0_L 0x450
38#define OMAP1_DMA_CAPS_1_U 0x452
39#define OMAP1_DMA_CAPS_1_L 0x454
40#define OMAP1_DMA_CAPS_2 0x456
41#define OMAP1_DMA_CAPS_3 0x458
42#define OMAP1_DMA_CAPS_4 0x45a
43#define OMAP1_DMA_PCH2_SR 0x460
44#define OMAP1_DMA_PCH0_SR 0x480
45#define OMAP1_DMA_PCH1_SR 0x482
46#define OMAP1_DMA_PCHD_SR 0x4c0
47
48/* Hardware registers for omap2 and omap3 */
49#define OMAP24XX_DMA4_BASE (L4_24XX_BASE + 0x56000)
50#define OMAP34XX_DMA4_BASE (L4_34XX_BASE + 0x56000)
51
52#define OMAP_DMA4_REVISION 0x00
53#define OMAP_DMA4_GCR 0x78
54#define OMAP_DMA4_IRQSTATUS_L0 0x08
55#define OMAP_DMA4_IRQSTATUS_L1 0x0c
56#define OMAP_DMA4_IRQSTATUS_L2 0x10
57#define OMAP_DMA4_IRQSTATUS_L3 0x14
58#define OMAP_DMA4_IRQENABLE_L0 0x18
59#define OMAP_DMA4_IRQENABLE_L1 0x1c
60#define OMAP_DMA4_IRQENABLE_L2 0x20
61#define OMAP_DMA4_IRQENABLE_L3 0x24
62#define OMAP_DMA4_SYSSTATUS 0x28
63#define OMAP_DMA4_OCP_SYSCONFIG 0x2c
64#define OMAP_DMA4_CAPS_0 0x64
65#define OMAP_DMA4_CAPS_2 0x6c
66#define OMAP_DMA4_CAPS_3 0x70
67#define OMAP_DMA4_CAPS_4 0x74
68
69#define OMAP1_LOGICAL_DMA_CH_COUNT 17
70#define OMAP_DMA4_LOGICAL_DMA_CH_COUNT 32 /* REVISIT: Is this 32 + 2? */
71
72/* Common channel specific registers for omap1 */
73#define OMAP1_DMA_CH_BASE(n) (0x40 * (n) + 0x00)
74#define OMAP1_DMA_CSDP(n) (0x40 * (n) + 0x00)
75#define OMAP1_DMA_CCR(n) (0x40 * (n) + 0x02)
76#define OMAP1_DMA_CICR(n) (0x40 * (n) + 0x04)
77#define OMAP1_DMA_CSR(n) (0x40 * (n) + 0x06)
78#define OMAP1_DMA_CEN(n) (0x40 * (n) + 0x10)
79#define OMAP1_DMA_CFN(n) (0x40 * (n) + 0x12)
80#define OMAP1_DMA_CSFI(n) (0x40 * (n) + 0x14)
81#define OMAP1_DMA_CSEI(n) (0x40 * (n) + 0x16)
82#define OMAP1_DMA_CPC(n) (0x40 * (n) + 0x18) /* 15xx only */
83#define OMAP1_DMA_CSAC(n) (0x40 * (n) + 0x18)
84#define OMAP1_DMA_CDAC(n) (0x40 * (n) + 0x1a)
85#define OMAP1_DMA_CDEI(n) (0x40 * (n) + 0x1c)
86#define OMAP1_DMA_CDFI(n) (0x40 * (n) + 0x1e)
87#define OMAP1_DMA_CLNK_CTRL(n) (0x40 * (n) + 0x28)
88
89/* Common channel specific registers for omap2 */
90#define OMAP_DMA4_CH_BASE(n) (0x60 * (n) + 0x80)
91#define OMAP_DMA4_CCR(n) (0x60 * (n) + 0x80)
92#define OMAP_DMA4_CLNK_CTRL(n) (0x60 * (n) + 0x84)
93#define OMAP_DMA4_CICR(n) (0x60 * (n) + 0x88)
94#define OMAP_DMA4_CSR(n) (0x60 * (n) + 0x8c)
95#define OMAP_DMA4_CSDP(n) (0x60 * (n) + 0x90)
96#define OMAP_DMA4_CEN(n) (0x60 * (n) + 0x94)
97#define OMAP_DMA4_CFN(n) (0x60 * (n) + 0x98)
98#define OMAP_DMA4_CSEI(n) (0x60 * (n) + 0xa4)
99#define OMAP_DMA4_CSFI(n) (0x60 * (n) + 0xa8)
100#define OMAP_DMA4_CDEI(n) (0x60 * (n) + 0xac)
101#define OMAP_DMA4_CDFI(n) (0x60 * (n) + 0xb0)
102#define OMAP_DMA4_CSAC(n) (0x60 * (n) + 0xb4)
103#define OMAP_DMA4_CDAC(n) (0x60 * (n) + 0xb8)
104
105/* Channel specific registers only on omap1 */
106#define OMAP1_DMA_CSSA_L(n) (0x40 * (n) + 0x08)
107#define OMAP1_DMA_CSSA_U(n) (0x40 * (n) + 0x0a)
108#define OMAP1_DMA_CDSA_L(n) (0x40 * (n) + 0x0c)
109#define OMAP1_DMA_CDSA_U(n) (0x40 * (n) + 0x0e)
110#define OMAP1_DMA_COLOR_L(n) (0x40 * (n) + 0x20)
111#define OMAP1_DMA_COLOR_U(n) (0x40 * (n) + 0x22)
112#define OMAP1_DMA_CCR2(n) (0x40 * (n) + 0x24)
113#define OMAP1_DMA_LCH_CTRL(n) (0x40 * (n) + 0x2a) /* not on 15xx */
114#define OMAP1_DMA_CCEN(n) 0
115#define OMAP1_DMA_CCFN(n) 0
116
117/* Channel specific registers only on omap2 */
118#define OMAP_DMA4_CSSA(n) (0x60 * (n) + 0x9c)
119#define OMAP_DMA4_CDSA(n) (0x60 * (n) + 0xa0)
120#define OMAP_DMA4_CCEN(n) (0x60 * (n) + 0xbc)
121#define OMAP_DMA4_CCFN(n) (0x60 * (n) + 0xc0)
122#define OMAP_DMA4_COLOR(n) (0x60 * (n) + 0xc4)
123
124/* Dummy defines to keep multi-omap compiles happy */
125#define OMAP1_DMA_REVISION 0
126#define OMAP1_DMA_IRQSTATUS_L0 0
127#define OMAP1_DMA_IRQENABLE_L0 0
128#define OMAP1_DMA_OCP_SYSCONFIG 0
129#define OMAP_DMA4_HW_ID 0
130#define OMAP_DMA4_CAPS_0_L 0
131#define OMAP_DMA4_CAPS_0_U 0
132#define OMAP_DMA4_CAPS_1_L 0
133#define OMAP_DMA4_CAPS_1_U 0
134#define OMAP_DMA4_GSCR 0
135#define OMAP_DMA4_CPC(n) 0
136
137#define OMAP_DMA4_LCH_CTRL(n) 0
138#define OMAP_DMA4_COLOR_L(n) 0
139#define OMAP_DMA4_COLOR_U(n) 0
140#define OMAP_DMA4_CCR2(n) 0
141#define OMAP1_DMA_CSSA(n) 0
142#define OMAP1_DMA_CDSA(n) 0
143#define OMAP_DMA4_CSSA_L(n) 0
144#define OMAP_DMA4_CSSA_U(n) 0
145#define OMAP_DMA4_CDSA_L(n) 0
146#define OMAP_DMA4_CDSA_U(n) 0
147
148/*----------------------------------------------------------------------------*/
149
150/* DMA channels for omap1 */
151#define OMAP_DMA_NO_DEVICE 0
152#define OMAP_DMA_MCSI1_TX 1
153#define OMAP_DMA_MCSI1_RX 2
154#define OMAP_DMA_I2C_RX 3
155#define OMAP_DMA_I2C_TX 4
156#define OMAP_DMA_EXT_NDMA_REQ 5
157#define OMAP_DMA_EXT_NDMA_REQ2 6
158#define OMAP_DMA_UWIRE_TX 7
159#define OMAP_DMA_MCBSP1_TX 8
160#define OMAP_DMA_MCBSP1_RX 9
161#define OMAP_DMA_MCBSP3_TX 10
162#define OMAP_DMA_MCBSP3_RX 11
163#define OMAP_DMA_UART1_TX 12
164#define OMAP_DMA_UART1_RX 13
165#define OMAP_DMA_UART2_TX 14
166#define OMAP_DMA_UART2_RX 15
167#define OMAP_DMA_MCBSP2_TX 16
168#define OMAP_DMA_MCBSP2_RX 17
169#define OMAP_DMA_UART3_TX 18
170#define OMAP_DMA_UART3_RX 19
171#define OMAP_DMA_CAMERA_IF_RX 20
172#define OMAP_DMA_MMC_TX 21
173#define OMAP_DMA_MMC_RX 22
174#define OMAP_DMA_NAND 23
175#define OMAP_DMA_IRQ_LCD_LINE 24
176#define OMAP_DMA_MEMORY_STICK 25
177#define OMAP_DMA_USB_W2FC_RX0 26
178#define OMAP_DMA_USB_W2FC_RX1 27
179#define OMAP_DMA_USB_W2FC_RX2 28
180#define OMAP_DMA_USB_W2FC_TX0 29
181#define OMAP_DMA_USB_W2FC_TX1 30
182#define OMAP_DMA_USB_W2FC_TX2 31
183
184/* These are only for 1610 */
185#define OMAP_DMA_CRYPTO_DES_IN 32
186#define OMAP_DMA_SPI_TX 33
187#define OMAP_DMA_SPI_RX 34
188#define OMAP_DMA_CRYPTO_HASH 35
189#define OMAP_DMA_CCP_ATTN 36
190#define OMAP_DMA_CCP_FIFO_NOT_EMPTY 37
191#define OMAP_DMA_CMT_APE_TX_CHAN_0 38
192#define OMAP_DMA_CMT_APE_RV_CHAN_0 39
193#define OMAP_DMA_CMT_APE_TX_CHAN_1 40
194#define OMAP_DMA_CMT_APE_RV_CHAN_1 41
195#define OMAP_DMA_CMT_APE_TX_CHAN_2 42
196#define OMAP_DMA_CMT_APE_RV_CHAN_2 43
197#define OMAP_DMA_CMT_APE_TX_CHAN_3 44
198#define OMAP_DMA_CMT_APE_RV_CHAN_3 45
199#define OMAP_DMA_CMT_APE_TX_CHAN_4 46
200#define OMAP_DMA_CMT_APE_RV_CHAN_4 47
201#define OMAP_DMA_CMT_APE_TX_CHAN_5 48
202#define OMAP_DMA_CMT_APE_RV_CHAN_5 49
203#define OMAP_DMA_CMT_APE_TX_CHAN_6 50
204#define OMAP_DMA_CMT_APE_RV_CHAN_6 51
205#define OMAP_DMA_CMT_APE_TX_CHAN_7 52
206#define OMAP_DMA_CMT_APE_RV_CHAN_7 53
207#define OMAP_DMA_MMC2_TX 54
208#define OMAP_DMA_MMC2_RX 55
209#define OMAP_DMA_CRYPTO_DES_OUT 56
210
211/* DMA channels for 24xx */
212#define OMAP24XX_DMA_NO_DEVICE 0
213#define OMAP24XX_DMA_XTI_DMA 1 /* S_DMA_0 */
214#define OMAP24XX_DMA_EXT_DMAREQ0 2 /* S_DMA_1 */
215#define OMAP24XX_DMA_EXT_DMAREQ1 3 /* S_DMA_2 */
216#define OMAP24XX_DMA_GPMC 4 /* S_DMA_3 */
217#define OMAP24XX_DMA_GFX 5 /* S_DMA_4 */
218#define OMAP24XX_DMA_DSS 6 /* S_DMA_5 */
219#define OMAP242X_DMA_VLYNQ_TX 7 /* S_DMA_6 */
220#define OMAP24XX_DMA_EXT_DMAREQ2 7 /* S_DMA_6 */
221#define OMAP24XX_DMA_CWT 8 /* S_DMA_7 */
222#define OMAP24XX_DMA_AES_TX 9 /* S_DMA_8 */
223#define OMAP24XX_DMA_AES_RX 10 /* S_DMA_9 */
224#define OMAP24XX_DMA_DES_TX 11 /* S_DMA_10 */
225#define OMAP24XX_DMA_DES_RX 12 /* S_DMA_11 */
226#define OMAP24XX_DMA_SHA1MD5_RX 13 /* S_DMA_12 */
227#define OMAP34XX_DMA_SHA2MD5_RX 13 /* S_DMA_12 */
228#define OMAP242X_DMA_EXT_DMAREQ2 14 /* S_DMA_13 */
229#define OMAP242X_DMA_EXT_DMAREQ3 15 /* S_DMA_14 */
230#define OMAP242X_DMA_EXT_DMAREQ4 16 /* S_DMA_15 */
231#define OMAP242X_DMA_EAC_AC_RD 17 /* S_DMA_16 */
232#define OMAP242X_DMA_EAC_AC_WR 18 /* S_DMA_17 */
233#define OMAP242X_DMA_EAC_MD_UL_RD 19 /* S_DMA_18 */
234#define OMAP242X_DMA_EAC_MD_UL_WR 20 /* S_DMA_19 */
235#define OMAP242X_DMA_EAC_MD_DL_RD 21 /* S_DMA_20 */
236#define OMAP242X_DMA_EAC_MD_DL_WR 22 /* S_DMA_21 */
237#define OMAP242X_DMA_EAC_BT_UL_RD 23 /* S_DMA_22 */
238#define OMAP242X_DMA_EAC_BT_UL_WR 24 /* S_DMA_23 */
239#define OMAP242X_DMA_EAC_BT_DL_RD 25 /* S_DMA_24 */
240#define OMAP242X_DMA_EAC_BT_DL_WR 26 /* S_DMA_25 */
241#define OMAP243X_DMA_EXT_DMAREQ3 14 /* S_DMA_13 */
242#define OMAP24XX_DMA_SPI3_TX0 15 /* S_DMA_14 */
243#define OMAP24XX_DMA_SPI3_RX0 16 /* S_DMA_15 */
244#define OMAP24XX_DMA_MCBSP3_TX 17 /* S_DMA_16 */
245#define OMAP24XX_DMA_MCBSP3_RX 18 /* S_DMA_17 */
246#define OMAP24XX_DMA_MCBSP4_TX 19 /* S_DMA_18 */
247#define OMAP24XX_DMA_MCBSP4_RX 20 /* S_DMA_19 */
248#define OMAP24XX_DMA_MCBSP5_TX 21 /* S_DMA_20 */
249#define OMAP24XX_DMA_MCBSP5_RX 22 /* S_DMA_21 */
250#define OMAP24XX_DMA_SPI3_TX1 23 /* S_DMA_22 */
251#define OMAP24XX_DMA_SPI3_RX1 24 /* S_DMA_23 */
252#define OMAP243X_DMA_EXT_DMAREQ4 25 /* S_DMA_24 */
253#define OMAP243X_DMA_EXT_DMAREQ5 26 /* S_DMA_25 */
254#define OMAP34XX_DMA_I2C3_TX 25 /* S_DMA_24 */
255#define OMAP34XX_DMA_I2C3_RX 26 /* S_DMA_25 */
256#define OMAP24XX_DMA_I2C1_TX 27 /* S_DMA_26 */
257#define OMAP24XX_DMA_I2C1_RX 28 /* S_DMA_27 */
258#define OMAP24XX_DMA_I2C2_TX 29 /* S_DMA_28 */
259#define OMAP24XX_DMA_I2C2_RX 30 /* S_DMA_29 */
260#define OMAP24XX_DMA_MCBSP1_TX 31 /* S_DMA_30 */
261#define OMAP24XX_DMA_MCBSP1_RX 32 /* S_DMA_31 */
262#define OMAP24XX_DMA_MCBSP2_TX 33 /* S_DMA_32 */
263#define OMAP24XX_DMA_MCBSP2_RX 34 /* S_DMA_33 */
264#define OMAP24XX_DMA_SPI1_TX0 35 /* S_DMA_34 */
265#define OMAP24XX_DMA_SPI1_RX0 36 /* S_DMA_35 */
266#define OMAP24XX_DMA_SPI1_TX1 37 /* S_DMA_36 */
267#define OMAP24XX_DMA_SPI1_RX1 38 /* S_DMA_37 */
268#define OMAP24XX_DMA_SPI1_TX2 39 /* S_DMA_38 */
269#define OMAP24XX_DMA_SPI1_RX2 40 /* S_DMA_39 */
270#define OMAP24XX_DMA_SPI1_TX3 41 /* S_DMA_40 */
271#define OMAP24XX_DMA_SPI1_RX3 42 /* S_DMA_41 */
272#define OMAP24XX_DMA_SPI2_TX0 43 /* S_DMA_42 */
273#define OMAP24XX_DMA_SPI2_RX0 44 /* S_DMA_43 */
274#define OMAP24XX_DMA_SPI2_TX1 45 /* S_DMA_44 */
275#define OMAP24XX_DMA_SPI2_RX1 46 /* S_DMA_45 */
276#define OMAP24XX_DMA_MMC2_TX 47 /* S_DMA_46 */
277#define OMAP24XX_DMA_MMC2_RX 48 /* S_DMA_47 */
278#define OMAP24XX_DMA_UART1_TX 49 /* S_DMA_48 */
279#define OMAP24XX_DMA_UART1_RX 50 /* S_DMA_49 */
280#define OMAP24XX_DMA_UART2_TX 51 /* S_DMA_50 */
281#define OMAP24XX_DMA_UART2_RX 52 /* S_DMA_51 */
282#define OMAP24XX_DMA_UART3_TX 53 /* S_DMA_52 */
283#define OMAP24XX_DMA_UART3_RX 54 /* S_DMA_53 */
284#define OMAP24XX_DMA_USB_W2FC_TX0 55 /* S_DMA_54 */
285#define OMAP24XX_DMA_USB_W2FC_RX0 56 /* S_DMA_55 */
286#define OMAP24XX_DMA_USB_W2FC_TX1 57 /* S_DMA_56 */
287#define OMAP24XX_DMA_USB_W2FC_RX1 58 /* S_DMA_57 */
288#define OMAP24XX_DMA_USB_W2FC_TX2 59 /* S_DMA_58 */
289#define OMAP24XX_DMA_USB_W2FC_RX2 60 /* S_DMA_59 */
290#define OMAP24XX_DMA_MMC1_TX 61 /* S_DMA_60 */
291#define OMAP24XX_DMA_MMC1_RX 62 /* S_DMA_61 */
292#define OMAP24XX_DMA_MS 63 /* S_DMA_62 */
293#define OMAP242X_DMA_EXT_DMAREQ5 64 /* S_DMA_63 */
294#define OMAP243X_DMA_EXT_DMAREQ6 64 /* S_DMA_63 */
295#define OMAP34XX_DMA_EXT_DMAREQ3 64 /* S_DMA_63 */
296#define OMAP34XX_DMA_AES2_TX 65 /* S_DMA_64 */
297#define OMAP34XX_DMA_AES2_RX 66 /* S_DMA_65 */
298#define OMAP34XX_DMA_DES2_TX 67 /* S_DMA_66 */
299#define OMAP34XX_DMA_DES2_RX 68 /* S_DMA_67 */
300#define OMAP34XX_DMA_SHA1MD5_RX 69 /* S_DMA_68 */
301#define OMAP34XX_DMA_SPI4_TX0 70 /* S_DMA_69 */
302#define OMAP34XX_DMA_SPI4_RX0 71 /* S_DMA_70 */
303#define OMAP34XX_DSS_DMA0 72 /* S_DMA_71 */
304#define OMAP34XX_DSS_DMA1 73 /* S_DMA_72 */
305#define OMAP34XX_DSS_DMA2 74 /* S_DMA_73 */
306#define OMAP34XX_DSS_DMA3 75 /* S_DMA_74 */
307#define OMAP34XX_DMA_MMC3_TX 77 /* S_DMA_76 */
308#define OMAP34XX_DMA_MMC3_RX 78 /* S_DMA_77 */
309#define OMAP34XX_DMA_USIM_TX 79 /* S_DMA_78 */
310#define OMAP34XX_DMA_USIM_RX 80 /* S_DMA_79 */
311
312/*----------------------------------------------------------------------------*/
313
314/* Hardware registers for LCD DMA */
315#define OMAP1510_DMA_LCD_BASE (0xfffedb00)
316#define OMAP1510_DMA_LCD_CTRL (OMAP1510_DMA_LCD_BASE + 0x00)
317#define OMAP1510_DMA_LCD_TOP_F1_L (OMAP1510_DMA_LCD_BASE + 0x02)
318#define OMAP1510_DMA_LCD_TOP_F1_U (OMAP1510_DMA_LCD_BASE + 0x04)
319#define OMAP1510_DMA_LCD_BOT_F1_L (OMAP1510_DMA_LCD_BASE + 0x06)
320#define OMAP1510_DMA_LCD_BOT_F1_U (OMAP1510_DMA_LCD_BASE + 0x08)
321
322#define OMAP1610_DMA_LCD_BASE (0xfffee300)
323#define OMAP1610_DMA_LCD_CSDP (OMAP1610_DMA_LCD_BASE + 0xc0)
324#define OMAP1610_DMA_LCD_CCR (OMAP1610_DMA_LCD_BASE + 0xc2)
325#define OMAP1610_DMA_LCD_CTRL (OMAP1610_DMA_LCD_BASE + 0xc4)
326#define OMAP1610_DMA_LCD_TOP_B1_L (OMAP1610_DMA_LCD_BASE + 0xc8)
327#define OMAP1610_DMA_LCD_TOP_B1_U (OMAP1610_DMA_LCD_BASE + 0xca)
328#define OMAP1610_DMA_LCD_BOT_B1_L (OMAP1610_DMA_LCD_BASE + 0xcc)
329#define OMAP1610_DMA_LCD_BOT_B1_U (OMAP1610_DMA_LCD_BASE + 0xce)
330#define OMAP1610_DMA_LCD_TOP_B2_L (OMAP1610_DMA_LCD_BASE + 0xd0)
331#define OMAP1610_DMA_LCD_TOP_B2_U (OMAP1610_DMA_LCD_BASE + 0xd2)
332#define OMAP1610_DMA_LCD_BOT_B2_L (OMAP1610_DMA_LCD_BASE + 0xd4)
333#define OMAP1610_DMA_LCD_BOT_B2_U (OMAP1610_DMA_LCD_BASE + 0xd6)
334#define OMAP1610_DMA_LCD_SRC_EI_B1 (OMAP1610_DMA_LCD_BASE + 0xd8)
335#define OMAP1610_DMA_LCD_SRC_FI_B1_L (OMAP1610_DMA_LCD_BASE + 0xda)
336#define OMAP1610_DMA_LCD_SRC_EN_B1 (OMAP1610_DMA_LCD_BASE + 0xe0)
337#define OMAP1610_DMA_LCD_SRC_FN_B1 (OMAP1610_DMA_LCD_BASE + 0xe4)
338#define OMAP1610_DMA_LCD_LCH_CTRL (OMAP1610_DMA_LCD_BASE + 0xea)
339#define OMAP1610_DMA_LCD_SRC_FI_B1_U (OMAP1610_DMA_LCD_BASE + 0xf4)
340
341#define OMAP1_DMA_TOUT_IRQ (1 << 0)
342#define OMAP_DMA_DROP_IRQ (1 << 1)
343#define OMAP_DMA_HALF_IRQ (1 << 2)
344#define OMAP_DMA_FRAME_IRQ (1 << 3)
345#define OMAP_DMA_LAST_IRQ (1 << 4)
346#define OMAP_DMA_BLOCK_IRQ (1 << 5)
347#define OMAP1_DMA_SYNC_IRQ (1 << 6)
348#define OMAP2_DMA_PKT_IRQ (1 << 7)
349#define OMAP2_DMA_TRANS_ERR_IRQ (1 << 8)
350#define OMAP2_DMA_SECURE_ERR_IRQ (1 << 9)
351#define OMAP2_DMA_SUPERVISOR_ERR_IRQ (1 << 10)
352#define OMAP2_DMA_MISALIGNED_ERR_IRQ (1 << 11)
353
354#define OMAP_DMA_DATA_TYPE_S8 0x00
355#define OMAP_DMA_DATA_TYPE_S16 0x01
356#define OMAP_DMA_DATA_TYPE_S32 0x02
357
358#define OMAP_DMA_SYNC_ELEMENT 0x00
359#define OMAP_DMA_SYNC_FRAME 0x01
360#define OMAP_DMA_SYNC_BLOCK 0x02
361#define OMAP_DMA_SYNC_PACKET 0x03
362
363#define OMAP_DMA_SRC_SYNC 0x01
364#define OMAP_DMA_DST_SYNC 0x00
365
366#define OMAP_DMA_PORT_EMIFF 0x00
367#define OMAP_DMA_PORT_EMIFS 0x01
368#define OMAP_DMA_PORT_OCP_T1 0x02
369#define OMAP_DMA_PORT_TIPB 0x03
370#define OMAP_DMA_PORT_OCP_T2 0x04
371#define OMAP_DMA_PORT_MPUI 0x05
372
373#define OMAP_DMA_AMODE_CONSTANT 0x00
374#define OMAP_DMA_AMODE_POST_INC 0x01
375#define OMAP_DMA_AMODE_SINGLE_IDX 0x02
376#define OMAP_DMA_AMODE_DOUBLE_IDX 0x03
377
378#define DMA_DEFAULT_FIFO_DEPTH 0x10
379#define DMA_DEFAULT_ARB_RATE 0x01
380/* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
381#define DMA_THREAD_RESERVE_NORM (0x00 << 12) /* Def */
382#define DMA_THREAD_RESERVE_ONET (0x01 << 12)
383#define DMA_THREAD_RESERVE_TWOT (0x02 << 12)
384#define DMA_THREAD_RESERVE_THREET (0x03 << 12)
385#define DMA_THREAD_FIFO_NONE (0x00 << 14) /* Def */
386#define DMA_THREAD_FIFO_75 (0x01 << 14)
387#define DMA_THREAD_FIFO_25 (0x02 << 14)
388#define DMA_THREAD_FIFO_50 (0x03 << 14)
389
390/* Chaining modes*/
391#ifndef CONFIG_ARCH_OMAP1
392#define OMAP_DMA_STATIC_CHAIN 0x1
393#define OMAP_DMA_DYNAMIC_CHAIN 0x2
394#define OMAP_DMA_CHAIN_ACTIVE 0x1
395#define OMAP_DMA_CHAIN_INACTIVE 0x0
396#endif
397
398#define DMA_CH_PRIO_HIGH 0x1
399#define DMA_CH_PRIO_LOW 0x0 /* Def */
400
401/* LCD DMA block numbers */
402enum {
403 OMAP_LCD_DMA_B1_TOP,
404 OMAP_LCD_DMA_B1_BOTTOM,
405 OMAP_LCD_DMA_B2_TOP,
406 OMAP_LCD_DMA_B2_BOTTOM
407};
408
409enum omap_dma_burst_mode {
410 OMAP_DMA_DATA_BURST_DIS = 0,
411 OMAP_DMA_DATA_BURST_4,
412 OMAP_DMA_DATA_BURST_8,
413 OMAP_DMA_DATA_BURST_16,
414};
415
416enum end_type {
417 OMAP_DMA_LITTLE_ENDIAN = 0,
418 OMAP_DMA_BIG_ENDIAN
419};
420
421enum omap_dma_color_mode {
422 OMAP_DMA_COLOR_DIS = 0,
423 OMAP_DMA_CONSTANT_FILL,
424 OMAP_DMA_TRANSPARENT_COPY
425};
426
427enum omap_dma_write_mode {
428 OMAP_DMA_WRITE_NON_POSTED = 0,
429 OMAP_DMA_WRITE_POSTED,
430 OMAP_DMA_WRITE_LAST_NON_POSTED
431};
432
433enum omap_dma_channel_mode {
434 OMAP_DMA_LCH_2D = 0,
435 OMAP_DMA_LCH_G,
436 OMAP_DMA_LCH_P,
437 OMAP_DMA_LCH_PD
438};
439
440struct omap_dma_channel_params {
441 int data_type; /* data type 8,16,32 */
442 int elem_count; /* number of elements in a frame */
443 int frame_count; /* number of frames in a element */
444
445 int src_port; /* Only on OMAP1 REVISIT: Is this needed? */
446 int src_amode; /* constant, post increment, indexed,
447 double indexed */
448 unsigned long src_start; /* source address : physical */
449 int src_ei; /* source element index */
450 int src_fi; /* source frame index */
451
452 int dst_port; /* Only on OMAP1 REVISIT: Is this needed? */
453 int dst_amode; /* constant, post increment, indexed,
454 double indexed */
455 unsigned long dst_start; /* source address : physical */
456 int dst_ei; /* source element index */
457 int dst_fi; /* source frame index */
458
459 int trigger; /* trigger attached if the channel is
460 synchronized */
461 int sync_mode; /* sycn on element, frame , block or packet */
462 int src_or_dst_synch; /* source synch(1) or destination synch(0) */
463
464 int ie; /* interrupt enabled */
465
466 unsigned char read_prio;/* read priority */
467 unsigned char write_prio;/* write priority */
468
469#ifndef CONFIG_ARCH_OMAP1
470 enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
471#endif
472};
473
474
475extern void omap_set_dma_priority(int lch, int dst_port, int priority);
476extern int omap_request_dma(int dev_id, const char *dev_name,
477 void (*callback)(int lch, u16 ch_status, void *data),
478 void *data, int *dma_ch);
479extern void omap_enable_dma_irq(int ch, u16 irq_bits);
480extern void omap_disable_dma_irq(int ch, u16 irq_bits);
481extern void omap_free_dma(int ch);
482extern void omap_start_dma(int lch);
483extern void omap_stop_dma(int lch);
484extern void omap_set_dma_transfer_params(int lch, int data_type,
485 int elem_count, int frame_count,
486 int sync_mode,
487 int dma_trigger, int src_or_dst_synch);
488extern void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode,
489 u32 color);
490extern void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode);
491extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
492
493extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
494 unsigned long src_start,
495 int src_ei, int src_fi);
496extern void omap_set_dma_src_index(int lch, int eidx, int fidx);
497extern void omap_set_dma_src_data_pack(int lch, int enable);
498extern void omap_set_dma_src_burst_mode(int lch,
499 enum omap_dma_burst_mode burst_mode);
500
501extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
502 unsigned long dest_start,
503 int dst_ei, int dst_fi);
504extern void omap_set_dma_dest_index(int lch, int eidx, int fidx);
505extern void omap_set_dma_dest_data_pack(int lch, int enable);
506extern void omap_set_dma_dest_burst_mode(int lch,
507 enum omap_dma_burst_mode burst_mode);
508
509extern void omap_set_dma_params(int lch,
510 struct omap_dma_channel_params *params);
511
512extern void omap_dma_link_lch(int lch_head, int lch_queue);
513extern void omap_dma_unlink_lch(int lch_head, int lch_queue);
514
515extern int omap_set_dma_callback(int lch,
516 void (*callback)(int lch, u16 ch_status, void *data),
517 void *data);
518extern dma_addr_t omap_get_dma_src_pos(int lch);
519extern dma_addr_t omap_get_dma_dst_pos(int lch);
520extern void omap_clear_dma(int lch);
521extern int omap_get_dma_active_status(int lch);
522extern int omap_dma_running(void);
523extern void omap_dma_set_global_params(int arb_rate, int max_fifo_depth,
524 int tparams);
525extern int omap_dma_set_prio_lch(int lch, unsigned char read_prio,
526 unsigned char write_prio);
527extern void omap_set_dma_dst_endian_type(int lch, enum end_type etype);
528extern void omap_set_dma_src_endian_type(int lch, enum end_type etype);
529extern int omap_get_dma_index(int lch, int *ei, int *fi);
530
531/* Chaining APIs */
532#ifndef CONFIG_ARCH_OMAP1
533extern int omap_request_dma_chain(int dev_id, const char *dev_name,
534 void (*callback) (int chain_id, u16 ch_status,
535 void *data),
536 int *chain_id, int no_of_chans,
537 int chain_mode,
538 struct omap_dma_channel_params params);
539extern int omap_free_dma_chain(int chain_id);
540extern int omap_dma_chain_a_transfer(int chain_id, int src_start,
541 int dest_start, int elem_count,
542 int frame_count, void *callbk_data);
543extern int omap_start_dma_chain_transfers(int chain_id);
544extern int omap_stop_dma_chain_transfers(int chain_id);
545extern int omap_get_dma_chain_index(int chain_id, int *ei, int *fi);
546extern int omap_get_dma_chain_dst_pos(int chain_id);
547extern int omap_get_dma_chain_src_pos(int chain_id);
548
549extern int omap_modify_dma_chain_params(int chain_id,
550 struct omap_dma_channel_params params);
551extern int omap_dma_chain_status(int chain_id);
552#endif
553
554/* LCD DMA functions */
555extern int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
556 void *data);
557extern void omap_free_lcd_dma(void);
558extern void omap_setup_lcd_dma(void);
559extern void omap_enable_lcd_dma(void);
560extern void omap_stop_lcd_dma(void);
561extern void omap_set_lcd_dma_ext_controller(int external);
562extern void omap_set_lcd_dma_single_transfer(int single);
563extern void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
564 int data_type);
565extern void omap_set_lcd_dma_b1_rotation(int rotate);
566extern void omap_set_lcd_dma_b1_vxres(unsigned long vxres);
567extern void omap_set_lcd_dma_b1_mirror(int mirror);
568extern void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale);
569
570#endif /* __ASM_ARCH_DMA_H */
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