aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm/arch-mxc/mxc_timer.h
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm/arch-mxc/mxc_timer.h')
-rw-r--r--include/asm-arm/arch-mxc/mxc_timer.h158
1 files changed, 158 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mxc/mxc_timer.h b/include/asm-arm/arch-mxc/mxc_timer.h
new file mode 100644
index 000000000000..6cb11f4f1a06
--- /dev/null
+++ b/include/asm-arm/arch-mxc/mxc_timer.h
@@ -0,0 +1,158 @@
1/*
2 * mxc_timer.h
3 *
4 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
5 *
6 * Platform independent (i.MX1, i.MX2, i.MX3) definition for timer handling.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor,
20 * Boston, MA 02110-1301, USA.
21 */
22
23#ifndef __PLAT_MXC_TIMER_H
24#define __PLAT_MXC_TIMER_H
25
26#include <linux/clk.h>
27#include <asm/hardware.h>
28
29#ifdef CONFIG_ARCH_IMX
30#define TIMER_BASE IO_ADDRESS(TIM1_BASE_ADDR)
31#define TIMER_INTERRUPT TIM1_INT
32
33#define TCTL_VAL TCTL_CLK_PCLK1
34#define TCTL_IRQEN (1<<4)
35#define TCTL_FRR (1<<8)
36#define TCTL_CLK_PCLK1 (1<<1)
37#define TCTL_CLK_PCLK1_4 (2<<1)
38#define TCTL_CLK_TIN (3<<1)
39#define TCTL_CLK_32 (4<<1)
40
41#define MXC_TCTL 0x00
42#define MXC_TPRER 0x04
43#define MXC_TCMP 0x08
44#define MXC_TCR 0x0c
45#define MXC_TCN 0x10
46#define MXC_TSTAT 0x14
47#define TSTAT_CAPT (1<<1)
48#define TSTAT_COMP (1<<0)
49
50static inline void gpt_irq_disable(void)
51{
52 unsigned int tmp;
53
54 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
55 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
56}
57
58static inline void gpt_irq_enable(void)
59{
60 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
61 TIMER_BASE + MXC_TCTL);
62}
63
64static void gpt_irq_acknowledge(void)
65{
66 __raw_writel(0, TIMER_BASE + MXC_TSTAT);
67}
68#endif /* CONFIG_ARCH_IMX */
69
70#ifdef CONFIG_ARCH_MX2
71#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
72#define TIMER_INTERRUPT MXC_INT_GPT1
73
74#define MXC_TCTL 0x00
75#define TCTL_VAL TCTL_CLK_PCLK1
76#define TCTL_CLK_PCLK1 (1<<1)
77#define TCTL_CLK_PCLK1_4 (2<<1)
78#define TCTL_IRQEN (1<<4)
79#define TCTL_FRR (1<<8)
80#define MXC_TPRER 0x04
81#define MXC_TCMP 0x08
82#define MXC_TCR 0x0c
83#define MXC_TCN 0x10
84#define MXC_TSTAT 0x14
85#define TSTAT_CAPT (1<<1)
86#define TSTAT_COMP (1<<0)
87
88static inline void gpt_irq_disable(void)
89{
90 unsigned int tmp;
91
92 tmp = __raw_readl(TIMER_BASE + MXC_TCTL);
93 __raw_writel(tmp & ~TCTL_IRQEN, TIMER_BASE + MXC_TCTL);
94}
95
96static inline void gpt_irq_enable(void)
97{
98 __raw_writel(__raw_readl(TIMER_BASE + MXC_TCTL) | TCTL_IRQEN,
99 TIMER_BASE + MXC_TCTL);
100}
101
102static void gpt_irq_acknowledge(void)
103{
104 __raw_writel(TSTAT_CAPT | TSTAT_COMP, TIMER_BASE + MXC_TSTAT);
105}
106#endif /* CONFIG_ARCH_MX2 */
107
108#ifdef CONFIG_ARCH_MX3
109#define TIMER_BASE IO_ADDRESS(GPT1_BASE_ADDR)
110#define TIMER_INTERRUPT MXC_INT_GPT
111
112#define MXC_TCTL 0x00
113#define TCTL_VAL (TCTL_CLK_IPG | TCTL_WAITEN)
114#define TCTL_CLK_IPG (1<<6)
115#define TCTL_FRR (1<<9)
116#define TCTL_WAITEN (1<<3)
117
118#define MXC_TPRER 0x04
119#define MXC_TSTAT 0x08
120#define TSTAT_OF1 (1<<0)
121#define TSTAT_OF2 (1<<1)
122#define TSTAT_OF3 (1<<2)
123#define TSTAT_IF1 (1<<3)
124#define TSTAT_IF2 (1<<4)
125#define TSTAT_ROV (1<<5)
126#define MXC_IR 0x0c
127#define MXC_TCMP 0x10
128#define MXC_TCMP2 0x14
129#define MXC_TCMP3 0x18
130#define MXC_TCR 0x1c
131#define MXC_TCN 0x24
132
133static inline void gpt_irq_disable(void)
134{
135 __raw_writel(0, TIMER_BASE + MXC_IR);
136}
137
138static inline void gpt_irq_enable(void)
139{
140 __raw_writel(1<<0, TIMER_BASE + MXC_IR);
141}
142
143static inline void gpt_irq_acknowledge(void)
144{
145 __raw_writel(TSTAT_OF1, TIMER_BASE + MXC_TSTAT);
146}
147#endif /* CONFIG_ARCH_MX3 */
148
149#define TCTL_SWR (1<<15)
150#define TCTL_CC (1<<10)
151#define TCTL_OM (1<<9)
152#define TCTL_CAP_RIS (1<<6)
153#define TCTL_CAP_FAL (2<<6)
154#define TCTL_CAP_RIS_FAL (3<<6)
155#define TCTL_CAP_ENA (1<<5)
156#define TCTL_TEN (1<<0)
157
158#endif