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-rw-r--r--include/asm-arm/arch-mxc/mxc.h152
1 files changed, 18 insertions, 134 deletions
diff --git a/include/asm-arm/arch-mxc/mxc.h b/include/asm-arm/arch-mxc/mxc.h
index 146d3f60951a..332eda4dbd3b 100644
--- a/include/asm-arm/arch-mxc/mxc.h
+++ b/include/asm-arm/arch-mxc/mxc.h
@@ -1,11 +1,20 @@
1/* 1/*
2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. 2 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */ 3 * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
4 4 *
5/* 5 * This program is free software; you can redistribute it and/or
6 * This program is free software; you can redistribute it and/or modify 6 * modify it under the terms of the GNU General Public License
7 * it under the terms of the GNU General Public License version 2 as 7 * as published by the Free Software Foundation; either version 2
8 * published by the Free Software Foundation. 8 * of the License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
17 * MA 02110-1301, USA.
9 */ 18 */
10 19
11#ifndef __ASM_ARCH_MXC_H__ 20#ifndef __ASM_ARCH_MXC_H__
@@ -20,133 +29,8 @@
20# define cpu_is_mx31() (0) 29# define cpu_is_mx31() (0)
21#endif 30#endif
22 31
23/* 32#ifndef CONFIG_MACH_MX27
24 ***************************************** 33# define cpu_is_mx27() (0)
25 * GPT Register definitions * 34#endif
26 *****************************************
27 */
28#define MXC_GPT_GPTCR IO_ADDRESS(GPT1_BASE_ADDR + 0x00)
29#define MXC_GPT_GPTPR IO_ADDRESS(GPT1_BASE_ADDR + 0x04)
30#define MXC_GPT_GPTSR IO_ADDRESS(GPT1_BASE_ADDR + 0x08)
31#define MXC_GPT_GPTIR IO_ADDRESS(GPT1_BASE_ADDR + 0x0C)
32#define MXC_GPT_GPTOCR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x10)
33#define MXC_GPT_GPTOCR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x14)
34#define MXC_GPT_GPTOCR3 IO_ADDRESS(GPT1_BASE_ADDR + 0x18)
35#define MXC_GPT_GPTICR1 IO_ADDRESS(GPT1_BASE_ADDR + 0x1C)
36#define MXC_GPT_GPTICR2 IO_ADDRESS(GPT1_BASE_ADDR + 0x20)
37#define MXC_GPT_GPTCNT IO_ADDRESS(GPT1_BASE_ADDR + 0x24)
38
39/* GPT Control register bit definitions */
40#define GPTCR_FO3 (1 << 31)
41#define GPTCR_FO2 (1 << 30)
42#define GPTCR_FO1 (1 << 29)
43
44#define GPTCR_OM3_SHIFT 26
45#define GPTCR_OM3_MASK (7 << GPTCR_OM3_SHIFT)
46#define GPTCR_OM3_DISCONNECTED (0 << GPTCR_OM3_SHIFT)
47#define GPTCR_OM3_TOGGLE (1 << GPTCR_OM3_SHIFT)
48#define GPTCR_OM3_CLEAR (2 << GPTCR_OM3_SHIFT)
49#define GPTCR_OM3_SET (3 << GPTCR_OM3_SHIFT)
50#define GPTCR_OM3_GENERATE_LOW (7 << GPTCR_OM3_SHIFT)
51
52#define GPTCR_OM2_SHIFT 23
53#define GPTCR_OM2_MASK (7 << GPTCR_OM2_SHIFT)
54#define GPTCR_OM2_DISCONNECTED (0 << GPTCR_OM2_SHIFT)
55#define GPTCR_OM2_TOGGLE (1 << GPTCR_OM2_SHIFT)
56#define GPTCR_OM2_CLEAR (2 << GPTCR_OM2_SHIFT)
57#define GPTCR_OM2_SET (3 << GPTCR_OM2_SHIFT)
58#define GPTCR_OM2_GENERATE_LOW (7 << GPTCR_OM2_SHIFT)
59
60#define GPTCR_OM1_SHIFT 20
61#define GPTCR_OM1_MASK (7 << GPTCR_OM1_SHIFT)
62#define GPTCR_OM1_DISCONNECTED (0 << GPTCR_OM1_SHIFT)
63#define GPTCR_OM1_TOGGLE (1 << GPTCR_OM1_SHIFT)
64#define GPTCR_OM1_CLEAR (2 << GPTCR_OM1_SHIFT)
65#define GPTCR_OM1_SET (3 << GPTCR_OM1_SHIFT)
66#define GPTCR_OM1_GENERATE_LOW (7 << GPTCR_OM1_SHIFT)
67
68#define GPTCR_IM2_SHIFT 18
69#define GPTCR_IM2_MASK (3 << GPTCR_IM2_SHIFT)
70#define GPTCR_IM2_CAPTURE_DISABLE (0 << GPTCR_IM2_SHIFT)
71#define GPTCR_IM2_CAPTURE_RISING (1 << GPTCR_IM2_SHIFT)
72#define GPTCR_IM2_CAPTURE_FALLING (2 << GPTCR_IM2_SHIFT)
73#define GPTCR_IM2_CAPTURE_BOTH (3 << GPTCR_IM2_SHIFT)
74
75#define GPTCR_IM1_SHIFT 16
76#define GPTCR_IM1_MASK (3 << GPTCR_IM1_SHIFT)
77#define GPTCR_IM1_CAPTURE_DISABLE (0 << GPTCR_IM1_SHIFT)
78#define GPTCR_IM1_CAPTURE_RISING (1 << GPTCR_IM1_SHIFT)
79#define GPTCR_IM1_CAPTURE_FALLING (2 << GPTCR_IM1_SHIFT)
80#define GPTCR_IM1_CAPTURE_BOTH (3 << GPTCR_IM1_SHIFT)
81
82#define GPTCR_SWR (1 << 15)
83#define GPTCR_FRR (1 << 9)
84
85#define GPTCR_CLKSRC_SHIFT 6
86#define GPTCR_CLKSRC_MASK (7 << GPTCR_CLKSRC_SHIFT)
87#define GPTCR_CLKSRC_NOCLOCK (0 << GPTCR_CLKSRC_SHIFT)
88#define GPTCR_CLKSRC_HIGHFREQ (2 << GPTCR_CLKSRC_SHIFT)
89#define GPTCR_CLKSRC_CLKIN (3 << GPTCR_CLKSRC_SHIFT)
90#define GPTCR_CLKSRC_CLK32K (7 << GPTCR_CLKSRC_SHIFT)
91
92#define GPTCR_STOPEN (1 << 5)
93#define GPTCR_DOZEN (1 << 4)
94#define GPTCR_WAITEN (1 << 3)
95#define GPTCR_DBGEN (1 << 2)
96
97#define GPTCR_ENMOD (1 << 1)
98#define GPTCR_ENABLE (1 << 0)
99
100#define GPTSR_OF1 (1 << 0)
101#define GPTSR_OF2 (1 << 1)
102#define GPTSR_OF3 (1 << 2)
103#define GPTSR_IF1 (1 << 3)
104#define GPTSR_IF2 (1 << 4)
105#define GPTSR_ROV (1 << 5)
106
107#define GPTIR_OF1IE GPTSR_OF1
108#define GPTIR_OF2IE GPTSR_OF2
109#define GPTIR_OF3IE GPTSR_OF3
110#define GPTIR_IF1IE GPTSR_IF1
111#define GPTIR_IF2IE GPTSR_IF2
112#define GPTIR_ROVIE GPTSR_ROV
113
114/*
115 *****************************************
116 * AVIC Registers *
117 *****************************************
118 */
119#define AVIC_BASE IO_ADDRESS(AVIC_BASE_ADDR)
120#define AVIC_INTCNTL (AVIC_BASE + 0x00) /* int control reg */
121#define AVIC_NIMASK (AVIC_BASE + 0x04) /* int mask reg */
122#define AVIC_INTENNUM (AVIC_BASE + 0x08) /* int enable number reg */
123#define AVIC_INTDISNUM (AVIC_BASE + 0x0C) /* int disable number reg */
124#define AVIC_INTENABLEH (AVIC_BASE + 0x10) /* int enable reg high */
125#define AVIC_INTENABLEL (AVIC_BASE + 0x14) /* int enable reg low */
126#define AVIC_INTTYPEH (AVIC_BASE + 0x18) /* int type reg high */
127#define AVIC_INTTYPEL (AVIC_BASE + 0x1C) /* int type reg low */
128#define AVIC_NIPRIORITY7 (AVIC_BASE + 0x20) /* norm int priority lvl7 */
129#define AVIC_NIPRIORITY6 (AVIC_BASE + 0x24) /* norm int priority lvl6 */
130#define AVIC_NIPRIORITY5 (AVIC_BASE + 0x28) /* norm int priority lvl5 */
131#define AVIC_NIPRIORITY4 (AVIC_BASE + 0x2C) /* norm int priority lvl4 */
132#define AVIC_NIPRIORITY3 (AVIC_BASE + 0x30) /* norm int priority lvl3 */
133#define AVIC_NIPRIORITY2 (AVIC_BASE + 0x34) /* norm int priority lvl2 */
134#define AVIC_NIPRIORITY1 (AVIC_BASE + 0x38) /* norm int priority lvl1 */
135#define AVIC_NIPRIORITY0 (AVIC_BASE + 0x3C) /* norm int priority lvl0 */
136#define AVIC_NIVECSR (AVIC_BASE + 0x40) /* norm int vector/status */
137#define AVIC_FIVECSR (AVIC_BASE + 0x44) /* fast int vector/status */
138#define AVIC_INTSRCH (AVIC_BASE + 0x48) /* int source reg high */
139#define AVIC_INTSRCL (AVIC_BASE + 0x4C) /* int source reg low */
140#define AVIC_INTFRCH (AVIC_BASE + 0x50) /* int force reg high */
141#define AVIC_INTFRCL (AVIC_BASE + 0x54) /* int force reg low */
142#define AVIC_NIPNDH (AVIC_BASE + 0x58) /* norm int pending high */
143#define AVIC_NIPNDL (AVIC_BASE + 0x5C) /* norm int pending low */
144#define AVIC_FIPNDH (AVIC_BASE + 0x60) /* fast int pending high */
145#define AVIC_FIPNDL (AVIC_BASE + 0x64) /* fast int pending low */
146
147#define SYSTEM_PREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x20)
148#define SYSTEM_SREV_REG IO_ADDRESS(IIM_BASE_ADDR + 0x24)
149#define IIM_PROD_REV_SH 3
150#define IIM_PROD_REV_LEN 5
151 35
152#endif /* __ASM_ARCH_MXC_H__ */ 36#endif /* __ASM_ARCH_MXC_H__ */
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