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diff --git a/include/asm-arm/arch-mxc/board-mx27ads.h b/include/asm-arm/arch-mxc/board-mx27ads.h
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1/*
2 * Copyright 2005-2007 Freescale Semiconductor, Inc. All Rights Reserved.
3 */
4
5/*
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#ifndef __ASM_ARCH_MXC_BOARD_MX27ADS_H__
15#define __ASM_ARCH_MXC_BOARD_MX27ADS_H__
16
17/* external interrupt multiplexer */
18#define MXC_EXP_IO_BASE (MXC_GPIO_BASE + MXC_MAX_GPIO_LINES)
19
20#define MXC_VIRTUAL_INTS_BASE (MXC_EXP_IO_BASE + MXC_MAX_EXP_IO_LINES)
21#define MXC_SDIO1_CARD_IRQ MXC_VIRTUAL_INTS_BASE
22#define MXC_SDIO2_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 1)
23#define MXC_SDIO3_CARD_IRQ (MXC_VIRTUAL_INTS_BASE + 2)
24
25#define MXC_MAX_BOARD_INTS (MXC_MAX_EXP_IO_LINES + \
26 MXC_MAX_VIRTUAL_INTS)
27
28/*
29 * MXC UART EVB board level configurations
30 */
31
32#define MXC_LL_EXTUART_PADDR (CS4_BASE_ADDR + 0x20000)
33#define MXC_LL_EXTUART_VADDR (CS4_BASE_ADDR_VIRT + 0x20000)
34#define MXC_LL_EXTUART_16BIT_BUS
35
36#define MXC_LL_UART_PADDR UART1_BASE_ADDR
37#define MXC_LL_UART_VADDR AIPI_IO_ADDRESS(UART1_BASE_ADDR)
38
39/*
40 * @name Memory Size parameters
41 */
42
43/*
44 * Size of SDRAM memory
45 */
46#define SDRAM_MEM_SIZE SZ_128M
47
48/*
49 * PBC Controller parameters
50 */
51
52/*
53 * Base address of PBC controller, CS4
54 */
55#define PBC_BASE_ADDRESS 0xEB000000
56#define PBC_REG_ADDR(offset) (PBC_BASE_ADDRESS + (offset))
57
58/*
59 * PBC Interupt name definitions
60 */
61#define PBC_GPIO1_0 0
62#define PBC_GPIO1_1 1
63#define PBC_GPIO1_2 2
64#define PBC_GPIO1_3 3
65#define PBC_GPIO1_4 4
66#define PBC_GPIO1_5 5
67
68#define PBC_INTR_MAX_NUM 6
69#define PBC_INTR_SHARED_MAX_NUM 8
70
71/* When the PBC address connection is fixed in h/w, defined as 1 */
72#define PBC_ADDR_SH 0
73
74/* Offsets for the PBC Controller register */
75/*
76 * PBC Board version register offset
77 */
78#define PBC_VERSION_REG PBC_REG_ADDR(0x00000 >> PBC_ADDR_SH)
79/*
80 * PBC Board control register 1 set address.
81 */
82#define PBC_BCTRL1_SET_REG PBC_REG_ADDR(0x00008 >> PBC_ADDR_SH)
83/*
84 * PBC Board control register 1 clear address.
85 */
86#define PBC_BCTRL1_CLEAR_REG PBC_REG_ADDR(0x0000C >> PBC_ADDR_SH)
87/*
88 * PBC Board control register 2 set address.
89 */
90#define PBC_BCTRL2_SET_REG PBC_REG_ADDR(0x00010 >> PBC_ADDR_SH)
91/*
92 * PBC Board control register 2 clear address.
93 */
94#define PBC_BCTRL2_CLEAR_REG PBC_REG_ADDR(0x00014 >> PBC_ADDR_SH)
95/*
96 * PBC Board control register 3 set address.
97 */
98#define PBC_BCTRL3_SET_REG PBC_REG_ADDR(0x00018 >> PBC_ADDR_SH)
99/*
100 * PBC Board control register 3 clear address.
101 */
102#define PBC_BCTRL3_CLEAR_REG PBC_REG_ADDR(0x0001C >> PBC_ADDR_SH)
103/*
104 * PBC Board control register 3 set address.
105 */
106#define PBC_BCTRL4_SET_REG PBC_REG_ADDR(0x00020 >> PBC_ADDR_SH)
107/*
108 * PBC Board control register 4 clear address.
109 */
110#define PBC_BCTRL4_CLEAR_REG PBC_REG_ADDR(0x00024 >> PBC_ADDR_SH)
111/*PBC_ADDR_SH
112 * PBC Board status register 1.
113 */
114#define PBC_BSTAT1_REG PBC_REG_ADDR(0x00028 >> PBC_ADDR_SH)
115/*
116 * PBC Board interrupt status register.
117 */
118#define PBC_INTSTATUS_REG PBC_REG_ADDR(0x0002C >> PBC_ADDR_SH)
119/*
120 * PBC Board interrupt current status register.
121 */
122#define PBC_INTCURR_STATUS_REG PBC_REG_ADDR(0x00034 >> PBC_ADDR_SH)
123/*
124 * PBC Interrupt mask register set address.
125 */
126#define PBC_INTMASK_SET_REG PBC_REG_ADDR(0x00038 >> PBC_ADDR_SH)
127/*
128 * PBC Interrupt mask register clear address.
129 */
130#define PBC_INTMASK_CLEAR_REG PBC_REG_ADDR(0x0003C >> PBC_ADDR_SH)
131/*
132 * External UART A.
133 */
134#define PBC_SC16C652_UARTA_REG PBC_REG_ADDR(0x20000 >> PBC_ADDR_SH)
135/*
136 * UART 4 Expanding Signal Status.
137 */
138#define PBC_UART_STATUS_REG PBC_REG_ADDR(0x22000 >> PBC_ADDR_SH)
139/*
140 * UART 4 Expanding Signal Control Set.
141 */
142#define PBC_UCTRL_SET_REG PBC_REG_ADDR(0x24000 >> PBC_ADDR_SH)
143/*
144 * UART 4 Expanding Signal Control Clear.
145 */
146#define PBC_UCTRL_CLR_REG PBC_REG_ADDR(0x26000 >> PBC_ADDR_SH)
147/*
148 * Ethernet Controller IO base address.
149 */
150#define PBC_CS8900A_IOBASE_REG PBC_REG_ADDR(0x40000 >> PBC_ADDR_SH)
151/*
152 * Ethernet Controller Memory base address.
153 */
154#define PBC_CS8900A_MEMBASE_REG PBC_REG_ADDR(0x42000 >> PBC_ADDR_SH)
155/*
156 * Ethernet Controller DMA base address.
157 */
158#define PBC_CS8900A_DMABASE_REG PBC_REG_ADDR(0x44000 >> PBC_ADDR_SH)
159
160/* PBC Board Version Register bit definition */
161#define PBC_VERSION_ADS 0x8000 /* Bit15=1 means version for ads */
162#define PBC_VERSION_EVB_REVB 0x4000 /* BIT14=1 means version for evb revb */
163
164/* PBC Board Control Register 1 bit definitions */
165#define PBC_BCTRL1_ERST 0x0001 /* Ethernet Reset */
166#define PBC_BCTRL1_URST 0x0002 /* Reset External UART controller */
167#define PBC_BCTRL1_FRST 0x0004 /* FEC Reset */
168#define PBC_BCTRL1_ESLEEP 0x0010 /* Enable ethernet Sleep */
169#define PBC_BCTRL1_LCDON 0x0800 /* Enable the LCD */
170
171/* PBC Board Control Register 2 bit definitions */
172#define PBC_BCTRL2_VCC_EN 0x0004 /* Enable VCC */
173#define PBC_BCTRL2_VPP_EN 0x0008 /* Enable Vpp */
174#define PBC_BCTRL2_ATAFEC_EN 0X0010
175#define PBC_BCTRL2_ATAFEC_SEL 0X0020
176#define PBC_BCTRL2_ATA_EN 0X0040
177#define PBC_BCTRL2_IRDA_SD 0X0080
178#define PBC_BCTRL2_IRDA_EN 0X0100
179#define PBC_BCTRL2_CCTL10 0X0200
180#define PBC_BCTRL2_CCTL11 0X0400
181
182/* PBC Board Control Register 3 bit definitions */
183#define PBC_BCTRL3_HSH_EN 0X0020
184#define PBC_BCTRL3_FSH_MOD 0X0040
185#define PBC_BCTRL3_OTG_HS_EN 0X0080
186#define PBC_BCTRL3_OTG_VBUS_EN 0X0100
187#define PBC_BCTRL3_FSH_VBUS_EN 0X0200
188#define PBC_BCTRL3_USB_OTG_ON 0X0800
189#define PBC_BCTRL3_USB_FSH_ON 0X1000
190
191/* PBC Board Control Register 4 bit definitions */
192#define PBC_BCTRL4_REGEN_SEL 0X0001
193#define PBC_BCTRL4_USER_OFF 0X0002
194#define PBC_BCTRL4_VIB_EN 0X0004
195#define PBC_BCTRL4_PWRGT1_EN 0X0008
196#define PBC_BCTRL4_PWRGT2_EN 0X0010
197#define PBC_BCTRL4_STDBY_PRI 0X0020
198
199#ifndef __ASSEMBLY__
200/*
201 * Enumerations for SD cards and memory stick card. This corresponds to
202 * the card EN bits in the IMR: SD1_EN | MS_EN | SD3_EN | SD2_EN.
203 */
204enum mxc_card_no {
205 MXC_CARD_SD2 = 0,
206 MXC_CARD_SD3,
207 MXC_CARD_MS,
208 MXC_CARD_SD1,
209 MXC_CARD_MIN = MXC_CARD_SD2,
210 MXC_CARD_MAX = MXC_CARD_SD1,
211};
212#endif
213
214#define MXC_CPLD_VER_1_50 0x01
215
216/*
217 * PBC BSTAT Register bit definitions
218 */
219#define PBC_BSTAT_PRI_INT 0X0001
220#define PBC_BSTAT_USB_BYP 0X0002
221#define PBC_BSTAT_ATA_IOCS16 0X0004
222#define PBC_BSTAT_ATA_CBLID 0X0008
223#define PBC_BSTAT_ATA_DASP 0X0010
224#define PBC_BSTAT_PWR_RDY 0X0020
225#define PBC_BSTAT_SD3_WP 0X0100
226#define PBC_BSTAT_SD2_WP 0X0200
227#define PBC_BSTAT_SD1_WP 0X0400
228#define PBC_BSTAT_SD3_DET 0X0800
229#define PBC_BSTAT_SD2_DET 0X1000
230#define PBC_BSTAT_SD1_DET 0X2000
231#define PBC_BSTAT_MS_DET 0X4000
232#define PBC_BSTAT_SD3_DET_BIT 11
233#define PBC_BSTAT_SD2_DET_BIT 12
234#define PBC_BSTAT_SD1_DET_BIT 13
235#define PBC_BSTAT_MS_DET_BIT 14
236#define MXC_BSTAT_BIT(n) ((n == MXC_CARD_SD2) ? PBC_BSTAT_SD2_DET : \
237 ((n == MXC_CARD_SD3) ? PBC_BSTAT_SD3_DET : \
238 ((n == MXC_CARD_SD1) ? PBC_BSTAT_SD1_DET : \
239 ((n == MXC_CARD_MS) ? PBC_BSTAT_MS_DET : \
240 0x0))))
241
242/*
243 * PBC UART Control Register bit definitions
244 */
245#define PBC_UCTRL_DCE_DCD 0X0001
246#define PBC_UCTRL_DCE_DSR 0X0002
247#define PBC_UCTRL_DCE_RI 0X0004
248#define PBC_UCTRL_DTE_DTR 0X0100
249
250/*
251 * PBC UART Status Register bit definitions
252 */
253#define PBC_USTAT_DTE_DCD 0X0001
254#define PBC_USTAT_DTE_DSR 0X0002
255#define PBC_USTAT_DTE_RI 0X0004
256#define PBC_USTAT_DCE_DTR 0X0100
257
258/*
259 * PBC Interupt mask register bit definitions
260 */
261#define PBC_INTR_SD3_R_EN_BIT 4
262#define PBC_INTR_SD2_R_EN_BIT 0
263#define PBC_INTR_SD1_R_EN_BIT 6
264#define PBC_INTR_MS_R_EN_BIT 5
265#define PBC_INTR_SD3_EN_BIT 13
266#define PBC_INTR_SD2_EN_BIT 12
267#define PBC_INTR_MS_EN_BIT 14
268#define PBC_INTR_SD1_EN_BIT 15
269
270#define PBC_INTR_SD2_R_EN 0x0001
271#define PBC_INTR_LOW_BAT 0X0002
272#define PBC_INTR_OTG_FSOVER 0X0004
273#define PBC_INTR_FSH_OVER 0X0008
274#define PBC_INTR_SD3_R_EN 0x0010
275#define PBC_INTR_MS_R_EN 0x0020
276#define PBC_INTR_SD1_R_EN 0x0040
277#define PBC_INTR_FEC_INT 0X0080
278#define PBC_INTR_ENET_INT 0X0100
279#define PBC_INTR_OTGFS_INT 0X0200
280#define PBC_INTR_XUART_INT 0X0400
281#define PBC_INTR_CCTL12 0X0800
282#define PBC_INTR_SD2_EN 0x1000
283#define PBC_INTR_SD3_EN 0x2000
284#define PBC_INTR_MS_EN 0x4000
285#define PBC_INTR_SD1_EN 0x8000
286
287
288
289/* For interrupts like xuart, enet etc */
290#define EXPIO_PARENT_INT IOMUX_TO_IRQ(MX27_PIN_TIN)
291#define MXC_MAX_EXP_IO_LINES 16
292
293/*
294 * This corresponds to PBC_INTMASK_SET_REG at offset 0x38.
295 *
296 */
297#define EXPIO_INT_LOW_BAT (MXC_EXP_IO_BASE + 1)
298#define EXPIO_INT_OTG_FS_OVR (MXC_EXP_IO_BASE + 2)
299#define EXPIO_INT_FSH_OVR (MXC_EXP_IO_BASE + 3)
300#define EXPIO_INT_RES4 (MXC_EXP_IO_BASE + 4)
301#define EXPIO_INT_RES5 (MXC_EXP_IO_BASE + 5)
302#define EXPIO_INT_RES6 (MXC_EXP_IO_BASE + 6)
303#define EXPIO_INT_FEC (MXC_EXP_IO_BASE + 7)
304#define EXPIO_INT_ENET_INT (MXC_EXP_IO_BASE + 8)
305#define EXPIO_INT_OTG_FS_INT (MXC_EXP_IO_BASE + 9)
306#define EXPIO_INT_XUART_INTA (MXC_EXP_IO_BASE + 10)
307#define EXPIO_INT_CCTL12_INT (MXC_EXP_IO_BASE + 11)
308#define EXPIO_INT_SD2_EN (MXC_EXP_IO_BASE + 12)
309#define EXPIO_INT_SD3_EN (MXC_EXP_IO_BASE + 13)
310#define EXPIO_INT_MS_EN (MXC_EXP_IO_BASE + 14)
311#define EXPIO_INT_SD1_EN (MXC_EXP_IO_BASE + 15)
312
313/*
314 * This is System IRQ used by CS8900A for interrupt generation
315 * taken from platform.h
316 */
317#define CS8900AIRQ EXPIO_INT_ENET_INT
318/* This is I/O Base address used to access registers of CS8900A on MXC ADS */
319#define CS8900A_BASE_ADDRESS (PBC_CS8900A_IOBASE_REG + 0x300)
320
321#define MXC_PMIC_INT_LINE IOMUX_TO_IRQ(MX27_PIN_TOUT)
322
323/*
324* This is used to detect if the CPLD version is for mx27 evb board rev-a
325*/
326#define PBC_CPLD_VERSION_IS_REVA() \
327 ((__raw_readw(PBC_VERSION_REG) & \
328 (PBC_VERSION_ADS | PBC_VERSION_EVB_REVB))\
329 == 0)
330
331/* This is used to active or inactive ata signal in CPLD .
332 * It is dependent with hardware
333 */
334#define PBC_ATA_SIGNAL_ACTIVE() \
335 __raw_writew( \
336 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
337 PBC_BCTRL2_CLEAR_REG)
338
339#define PBC_ATA_SIGNAL_INACTIVE() \
340 __raw_writew( \
341 PBC_BCTRL2_ATAFEC_EN|PBC_BCTRL2_ATAFEC_SEL|PBC_BCTRL2_ATA_EN, \
342 PBC_BCTRL2_SET_REG)
343
344#define MXC_BD_LED1 (1 << 5)
345#define MXC_BD_LED2 (1 << 6)
346#define MXC_BD_LED_ON(led) \
347 __raw_writew(led, PBC_BCTRL1_SET_REG)
348#define MXC_BD_LED_OFF(led) \
349 __raw_writew(led, PBC_BCTRL1_CLEAR_REG)
350
351/* to determine the correct external crystal reference */
352#define CKIH_27MHZ_BIT_SET (1 << 3)
353
354#endif /* __ASM_ARCH_MXC_BOARD_MX27ADS_H__ */
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