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-rw-r--r--include/asm-arm/arch-mv78xx0/debug-macro.S20
-rw-r--r--include/asm-arm/arch-mv78xx0/dma.h1
-rw-r--r--include/asm-arm/arch-mv78xx0/entry-macro.S39
-rw-r--r--include/asm-arm/arch-mv78xx0/hardware.h21
-rw-r--r--include/asm-arm/arch-mv78xx0/io.h26
-rw-r--r--include/asm-arm/arch-mv78xx0/irqs.h91
-rw-r--r--include/asm-arm/arch-mv78xx0/memory.h14
-rw-r--r--include/asm-arm/arch-mv78xx0/mv78xx0.h126
-rw-r--r--include/asm-arm/arch-mv78xx0/system.h37
-rw-r--r--include/asm-arm/arch-mv78xx0/timex.h9
-rw-r--r--include/asm-arm/arch-mv78xx0/uncompress.h47
-rw-r--r--include/asm-arm/arch-mv78xx0/vmalloc.h5
12 files changed, 436 insertions, 0 deletions
diff --git a/include/asm-arm/arch-mv78xx0/debug-macro.S b/include/asm-arm/arch-mv78xx0/debug-macro.S
new file mode 100644
index 000000000000..d0595bd645e5
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/debug-macro.S
@@ -0,0 +1,20 @@
1/*
2 * include/asm-arm/arch-mv78xx0/debug-macro.S
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7*/
8
9#include <asm/arch/mv78xx0.h>
10
11 .macro addruart,rx
12 mrc p15, 0, \rx, c1, c0
13 tst \rx, #1 @ MMU enabled?
14 ldreq \rx, =MV78XX0_REGS_PHYS_BASE
15 ldrne \rx, =MV78XX0_REGS_VIRT_BASE
16 orr \rx, \rx, #0x00012000
17 .endm
18
19#define UART_SHIFT 2
20#include <asm/hardware/debug-8250.S>
diff --git a/include/asm-arm/arch-mv78xx0/dma.h b/include/asm-arm/arch-mv78xx0/dma.h
new file mode 100644
index 000000000000..40a8c178f10d
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/dma.h
@@ -0,0 +1 @@
/* empty */
diff --git a/include/asm-arm/arch-mv78xx0/entry-macro.S b/include/asm-arm/arch-mv78xx0/entry-macro.S
new file mode 100644
index 000000000000..e9a606b12669
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * include/asm-arm/arch-mv78xx0/entry-macro.S
3 *
4 * Low-level IRQ helper macros for Marvell MV78xx0 platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#include <asm/arch/mv78xx0.h>
12
13 .macro disable_fiq
14 .endm
15
16 .macro arch_ret_to_user, tmp1, tmp2
17 .endm
18
19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =IRQ_VIRT_BASE
21 .endm
22
23 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
24 @ check low interrupts
25 ldr \irqstat, [\base, #IRQ_CAUSE_LOW_OFF]
26 ldr \tmp, [\base, #IRQ_MASK_LOW_OFF]
27 mov \irqnr, #31
28 ands \irqstat, \irqstat, \tmp
29
30 @ if no low interrupts set, check high interrupts
31 ldreq \irqstat, [\base, #IRQ_CAUSE_HIGH_OFF]
32 ldreq \tmp, [\base, #IRQ_MASK_HIGH_OFF]
33 moveq \irqnr, #63
34 andeqs \irqstat, \irqstat, \tmp
35
36 @ find first active interrupt source
37 clzne \irqstat, \irqstat
38 subne \irqnr, \irqnr, \irqstat
39 .endm
diff --git a/include/asm-arm/arch-mv78xx0/hardware.h b/include/asm-arm/arch-mv78xx0/hardware.h
new file mode 100644
index 000000000000..8e17926086c6
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/hardware.h
@@ -0,0 +1,21 @@
1/*
2 * include/asm-arm/arch-mv78xx0/hardware.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_HARDWARE_H
10#define __ASM_ARCH_HARDWARE_H
11
12#include "mv78xx0.h"
13
14#define pcibios_assign_all_busses() 1
15
16#define PCIBIOS_MIN_IO 0x00001000
17#define PCIBIOS_MIN_MEM 0x01000000
18#define PCIMEM_BASE MV78XX0_PCIE_MEM_PHYS_BASE /* mem base for VGA */
19
20
21#endif
diff --git a/include/asm-arm/arch-mv78xx0/io.h b/include/asm-arm/arch-mv78xx0/io.h
new file mode 100644
index 000000000000..415d4c98e3d1
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/io.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-mv78xx0/io.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_IO_H
10#define __ASM_ARCH_IO_H
11
12#include "mv78xx0.h"
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16static inline void __iomem *__io(unsigned long addr)
17{
18 return (void __iomem *)((addr - MV78XX0_PCIE_IO_PHYS_BASE(0))
19 + MV78XX0_PCIE_IO_VIRT_BASE(0));
20}
21
22#define __io(a) __io(a)
23#define __mem_pci(a) (a)
24
25
26#endif
diff --git a/include/asm-arm/arch-mv78xx0/irqs.h b/include/asm-arm/arch-mv78xx0/irqs.h
new file mode 100644
index 000000000000..75930450cd65
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/irqs.h
@@ -0,0 +1,91 @@
1/*
2 * include/asm-arm/arch-mv78xx0/irqs.h
3 *
4 * IRQ definitions for Marvell MV78xx0 SoCs
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_IRQS_H
12#define __ASM_ARCH_IRQS_H
13
14#include "mv78xx0.h" /* need GPIO_MAX */
15
16/*
17 * MV78xx0 Low Interrupt Controller
18 */
19#define IRQ_MV78XX0_ERR 0
20#define IRQ_MV78XX0_SPI 1
21#define IRQ_MV78XX0_I2C_0 2
22#define IRQ_MV78XX0_I2C_1 3
23#define IRQ_MV78XX0_IDMA_0 4
24#define IRQ_MV78XX0_IDMA_1 5
25#define IRQ_MV78XX0_IDMA_2 6
26#define IRQ_MV78XX0_IDMA_3 7
27#define IRQ_MV78XX0_TIMER_0 8
28#define IRQ_MV78XX0_TIMER_1 9
29#define IRQ_MV78XX0_TIMER_2 10
30#define IRQ_MV78XX0_TIMER_3 11
31#define IRQ_MV78XX0_UART_0 12
32#define IRQ_MV78XX0_UART_1 13
33#define IRQ_MV78XX0_UART_2 14
34#define IRQ_MV78XX0_UART_3 15
35#define IRQ_MV78XX0_USB_0 16
36#define IRQ_MV78XX0_USB_1 17
37#define IRQ_MV78XX0_USB_2 18
38#define IRQ_MV78XX0_CRYPTO 19
39#define IRQ_MV78XX0_SDIO_0 20
40#define IRQ_MV78XX0_SDIO_1 21
41#define IRQ_MV78XX0_XOR_0 22
42#define IRQ_MV78XX0_XOR_1 23
43#define IRQ_MV78XX0_I2S_0 24
44#define IRQ_MV78XX0_I2S_1 25
45#define IRQ_MV78XX0_SATA 26
46#define IRQ_MV78XX0_TDMI 27
47
48/*
49 * MV78xx0 High Interrupt Controller
50 */
51#define IRQ_MV78XX0_PCIE_00 32
52#define IRQ_MV78XX0_PCIE_01 33
53#define IRQ_MV78XX0_PCIE_02 34
54#define IRQ_MV78XX0_PCIE_03 35
55#define IRQ_MV78XX0_PCIE_10 36
56#define IRQ_MV78XX0_PCIE_11 37
57#define IRQ_MV78XX0_PCIE_12 38
58#define IRQ_MV78XX0_PCIE_13 39
59#define IRQ_MV78XX0_GE00_SUM 40
60#define IRQ_MV78XX0_GE00_RX 41
61#define IRQ_MV78XX0_GE00_TX 42
62#define IRQ_MV78XX0_GE00_MISC 43
63#define IRQ_MV78XX0_GE01_SUM 44
64#define IRQ_MV78XX0_GE01_RX 45
65#define IRQ_MV78XX0_GE01_TX 46
66#define IRQ_MV78XX0_GE01_MISC 47
67#define IRQ_MV78XX0_GE10_SUM 48
68#define IRQ_MV78XX0_GE10_RX 49
69#define IRQ_MV78XX0_GE10_TX 50
70#define IRQ_MV78XX0_GE10_MISC 51
71#define IRQ_MV78XX0_GE11_SUM 52
72#define IRQ_MV78XX0_GE11_RX 53
73#define IRQ_MV78XX0_GE11_TX 54
74#define IRQ_MV78XX0_GE11_MISC 55
75#define IRQ_MV78XX0_GPIO_0_7 56
76#define IRQ_MV78XX0_GPIO_8_15 57
77#define IRQ_MV78XX0_GPIO_16_23 58
78#define IRQ_MV78XX0_GPIO_24_31 59
79#define IRQ_MV78XX0_DB_IN 60
80#define IRQ_MV78XX0_DB_OUT 61
81
82/*
83 * MV78XX0 General Purpose Pins
84 */
85#define IRQ_MV78XX0_GPIO_START 64
86#define NR_GPIO_IRQS GPIO_MAX
87
88#define NR_IRQS (IRQ_MV78XX0_GPIO_START + NR_GPIO_IRQS)
89
90
91#endif
diff --git a/include/asm-arm/arch-mv78xx0/memory.h b/include/asm-arm/arch-mv78xx0/memory.h
new file mode 100644
index 000000000000..721a6b185b91
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/memory.h
@@ -0,0 +1,14 @@
1/*
2 * include/asm-arm/arch-mv78xx0/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#define PHYS_OFFSET UL(0x00000000)
9
10#define __virt_to_bus(x) __virt_to_phys(x)
11#define __bus_to_virt(x) __phys_to_virt(x)
12
13
14#endif
diff --git a/include/asm-arm/arch-mv78xx0/mv78xx0.h b/include/asm-arm/arch-mv78xx0/mv78xx0.h
new file mode 100644
index 000000000000..9f5d83c73faa
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/mv78xx0.h
@@ -0,0 +1,126 @@
1/*
2 * include/asm-arm/arch-mv78xx0/mv78xx0.h
3 *
4 * Generic definitions for Marvell MV78xx0 SoC flavors:
5 * MV781x0 and MV782x0.
6 *
7 * This file is licensed under the terms of the GNU General Public
8 * License version 2. This program is licensed "as is" without any
9 * warranty of any kind, whether express or implied.
10 */
11
12#ifndef __ASM_ARCH_MV78XX0_H
13#define __ASM_ARCH_MV78XX0_H
14
15/*
16 * Marvell MV78xx0 address maps.
17 *
18 * phys
19 * c0000000 PCIe Memory space
20 * f0800000 PCIe #0 I/O space
21 * f0900000 PCIe #1 I/O space
22 * f0a00000 PCIe #2 I/O space
23 * f0b00000 PCIe #3 I/O space
24 * f0c00000 PCIe #4 I/O space
25 * f0d00000 PCIe #5 I/O space
26 * f0e00000 PCIe #6 I/O space
27 * f0f00000 PCIe #7 I/O space
28 * f1000000 on-chip peripheral registers
29 *
30 * virt phys size
31 * fe400000 f102x000 16K core-specific peripheral registers
32 * fe700000 f0800000 1M PCIe #0 I/O space
33 * fe800000 f0900000 1M PCIe #1 I/O space
34 * fe900000 f0a00000 1M PCIe #2 I/O space
35 * fea00000 f0b00000 1M PCIe #3 I/O space
36 * feb00000 f0c00000 1M PCIe #4 I/O space
37 * fec00000 f0d00000 1M PCIe #5 I/O space
38 * fed00000 f0e00000 1M PCIe #6 I/O space
39 * fee00000 f0f00000 1M PCIe #7 I/O space
40 * fef00000 f1000000 1M on-chip peripheral registers
41 */
42#define MV78XX0_CORE0_REGS_PHYS_BASE 0xf1020000
43#define MV78XX0_CORE1_REGS_PHYS_BASE 0xf1024000
44#define MV78XX0_CORE_REGS_VIRT_BASE 0xfe400000
45#define MV78XX0_CORE_REGS_SIZE SZ_16K
46
47#define MV78XX0_PCIE_IO_PHYS_BASE(i) (0xf0800000 + ((i) << 20))
48#define MV78XX0_PCIE_IO_VIRT_BASE(i) (0xfe700000 + ((i) << 20))
49#define MV78XX0_PCIE_IO_SIZE SZ_1M
50
51#define MV78XX0_REGS_PHYS_BASE 0xf1000000
52#define MV78XX0_REGS_VIRT_BASE 0xfef00000
53#define MV78XX0_REGS_SIZE SZ_1M
54
55#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
56#define MV78XX0_PCIE_MEM_SIZE 0x30000000
57
58/*
59 * Core-specific peripheral registers.
60 */
61#define BRIDGE_VIRT_BASE (MV78XX0_CORE_REGS_VIRT_BASE)
62#define CPU_CONTROL (BRIDGE_VIRT_BASE | 0x0104)
63#define L2_WRITETHROUGH 0x00020000
64#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
65#define SOFT_RESET_OUT_EN 0x00000004
66#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
67#define SOFT_RESET 0x00000001
68#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
69#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
70#define BRIDGE_INT_TIMER0 0x0002
71#define BRIDGE_INT_TIMER1 0x0004
72#define BRIDGE_INT_TIMER1_CLR (~0x0004)
73#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
74#define IRQ_CAUSE_LOW_OFF 0x0004
75#define IRQ_CAUSE_HIGH_OFF 0x0008
76#define IRQ_MASK_LOW_OFF 0x0010
77#define IRQ_MASK_HIGH_OFF 0x0014
78#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
79
80/*
81 * Register Map
82 */
83#define DDR_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x00000)
84#define DDR_WINDOW_CPU0_BASE (DDR_VIRT_BASE | 0x1500)
85#define DDR_WINDOW_CPU1_BASE (DDR_VIRT_BASE | 0x1700)
86
87#define DEV_BUS_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x10000)
88#define DEV_BUS_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x10000)
89#define SAMPLE_AT_RESET_LOW (DEV_BUS_VIRT_BASE | 0x0030)
90#define SAMPLE_AT_RESET_HIGH (DEV_BUS_VIRT_BASE | 0x0034)
91#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
92#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
93#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
94#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
95#define UART2_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2200)
96#define UART2_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2200)
97#define UART3_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2300)
98#define UART3_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2300)
99
100#define GE10_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x30000)
101#define GE11_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x34000)
102
103#define PCIE00_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x40000)
104#define PCIE01_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x44000)
105#define PCIE02_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x48000)
106#define PCIE03_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x4c000)
107
108#define USB0_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x50000)
109#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x51000)
110#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x52000)
111
112#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x70000)
113#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0x74000)
114
115#define PCIE10_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x80000)
116#define PCIE11_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x84000)
117#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x88000)
118#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE | 0x8c000)
119
120#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE | 0xa0000)
121
122
123#define GPIO_MAX 32
124
125
126#endif
diff --git a/include/asm-arm/arch-mv78xx0/system.h b/include/asm-arm/arch-mv78xx0/system.h
new file mode 100644
index 000000000000..7eb47d376db9
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/system.h
@@ -0,0 +1,37 @@
1/*
2 * include/asm-arm/arch-mv78xx0/system.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#ifndef __ASM_ARCH_SYSTEM_H
10#define __ASM_ARCH_SYSTEM_H
11
12#include <asm/arch/hardware.h>
13#include <asm/arch/mv78xx0.h>
14
15static inline void arch_idle(void)
16{
17 cpu_do_idle();
18}
19
20static inline void arch_reset(char mode)
21{
22 /*
23 * Enable soft reset to assert RSTOUTn.
24 */
25 writel(SOFT_RESET_OUT_EN, RSTOUTn_MASK);
26
27 /*
28 * Assert soft reset.
29 */
30 writel(SOFT_RESET, SYSTEM_SOFT_RESET);
31
32 while (1)
33 ;
34}
35
36
37#endif
diff --git a/include/asm-arm/arch-mv78xx0/timex.h b/include/asm-arm/arch-mv78xx0/timex.h
new file mode 100644
index 000000000000..a854b1ccbd01
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/timex.h
@@ -0,0 +1,9 @@
1/*
2 * include/asm-arm/arch-mv78xx0/timex.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#define CLOCK_TICK_RATE (100 * HZ)
diff --git a/include/asm-arm/arch-mv78xx0/uncompress.h b/include/asm-arm/arch-mv78xx0/uncompress.h
new file mode 100644
index 000000000000..3bfe0a293ef7
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/uncompress.h
@@ -0,0 +1,47 @@
1/*
2 * include/asm-arm/arch-mv78xx0/uncompress.h
3 *
4 * This file is licensed under the terms of the GNU General Public
5 * License version 2. This program is licensed "as is" without any
6 * warranty of any kind, whether express or implied.
7 */
8
9#include <linux/serial_reg.h>
10#include <asm/arch/mv78xx0.h>
11
12#define SERIAL_BASE ((unsigned char *)UART0_PHYS_BASE)
13
14static void putc(const char c)
15{
16 unsigned char *base = SERIAL_BASE;
17 int i;
18
19 for (i = 0; i < 0x1000; i++) {
20 if (base[UART_LSR << 2] & UART_LSR_THRE)
21 break;
22 barrier();
23 }
24
25 base[UART_TX << 2] = c;
26}
27
28static void flush(void)
29{
30 unsigned char *base = SERIAL_BASE;
31 unsigned char mask;
32 int i;
33
34 mask = UART_LSR_TEMT | UART_LSR_THRE;
35
36 for (i = 0; i < 0x1000; i++) {
37 if ((base[UART_LSR << 2] & mask) == mask)
38 break;
39 barrier();
40 }
41}
42
43/*
44 * nothing to do
45 */
46#define arch_decomp_setup()
47#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-mv78xx0/vmalloc.h b/include/asm-arm/arch-mv78xx0/vmalloc.h
new file mode 100644
index 000000000000..f2c512197579
--- /dev/null
+++ b/include/asm-arm/arch-mv78xx0/vmalloc.h
@@ -0,0 +1,5 @@
1/*
2 * include/asm-arm/arch-mv78xx0/vmalloc.h
3 */
4
5#define VMALLOC_END 0xfe000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-08 06:31:25 -0500