1 files changed, 0 insertions, 90 deletions
diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h
deleted file mode 100644
index e62a108b1857..000000000000
--- a/include/asm-arm/arch-msm/irqs.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/* linux/include/asm-arm/arch-msm/irqs.h
- *
- * Copyright (C) 2007 Google, Inc.
- * Author: Brian Swetland <swetland@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- */
-#ifndef __ASM_ARCH_MSM_IRQS_H
-#define __ASM_ARCH_MSM_IRQS_H
-/* MSM ARM11 Interrupt Numbers */
-/* See 80-VE113-1 A, pp219-221     */
-#define INT_A9_M2A_0         0
-#define INT_A9_M2A_1         1
-#define INT_A9_M2A_2         2
-#define INT_A9_M2A_3         3
-#define INT_A9_M2A_4         4
-#define INT_A9_M2A_5         5
-#define INT_A9_M2A_6         6
-#define INT_GP_TIMER_EXP     7
-#define INT_DEBUG_TIMER_EXP  8
-#define INT_UART1            9
-#define INT_UART2            10
-#define INT_UART3            11
-#define INT_UART1_RX         12
-#define INT_UART2_RX         13
-#define INT_UART3_RX         14
-#define INT_USB_OTG          15
-#define INT_MDDI_PRI         16
-#define INT_MDDI_EXT         17
-#define INT_MDDI_CLIENT      18
-#define INT_MDP              19
-#define INT_GRAPHICS         20
-#define INT_ADM_AARM         21
-#define INT_ADSP_A11         22
-#define INT_ADSP_A9_A11      23
-#define INT_SDC1_0           24
-#define INT_SDC1_1           25
-#define INT_SDC2_0           26
-#define INT_SDC2_1           27
-#define INT_KEYSENSE         28
-#define INT_TCHSCRN_SSBI     29
-#define INT_TCHSCRN1         30
-#define INT_TCHSCRN2         31
-#define INT_GPIO_GROUP1      (32 + 0)
-#define INT_GPIO_GROUP2      (32 + 1)
-#define INT_PWB_I2C          (32 + 2)
-#define INT_SOFTRESET        (32 + 3)
-#define INT_NAND_WR_ER_DONE  (32 + 4)
-#define INT_NAND_OP_DONE     (32 + 5)
-#define INT_PBUS_ARM11       (32 + 6)
-#define INT_AXI_MPU_SMI      (32 + 7)
-#define INT_AXI_MPU_EBI1     (32 + 8)
-#define INT_AD_HSSD          (32 + 9)
-#define INT_ARM11_PMU        (32 + 10)
-#define INT_ARM11_DMA        (32 + 11)
-#define INT_TSIF_IRQ         (32 + 12)
-#define INT_UART1DM_IRQ      (32 + 13)
-#define INT_UART1DM_RX       (32 + 14)
-#define INT_USB_HS           (32 + 15)
-#define INT_SDC3_0           (32 + 16)
-#define INT_SDC3_1           (32 + 17)
-#define INT_SDC4_0           (32 + 18)
-#define INT_SDC4_1           (32 + 19)
-#define INT_UART2DM_RX       (32 + 20)
-#define INT_UART2DM_IRQ      (32 + 21)
-/* 22-31 are reserved */
-#define MSM_IRQ_BIT(irq)     (1 << ((irq) & 31))
-#define NR_MSM_IRQS 64
-#define NR_GPIO_IRQS 122
-#define NR_BOARD_IRQS 64
-#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
-#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
-#endif

diff --git a/include/asm-arm/arch-msm/irqs.h b/include/asm-arm/arch-msm/irqs.h deleted file mode 100644 index e62a108b1857..000000000000 --- a/include/asm-arm/arch-msm/irqs.h +++ /dev/null
@@ -1,90 +0,0 @@
1	/* linux/include/asm-arm/arch-msm/irqs.h
2	*
3	* Copyright (C) 2007 Google, Inc.
4	* Author: Brian Swetland <swetland@google.com>
5	*
6	* This software is licensed under the terms of the GNU General Public
7	* License version 2, as published by the Free Software Foundation, and
8	* may be copied, distributed, and modified under those terms.
9	*
10	* This program is distributed in the hope that it will be useful,
11	* but WITHOUT ANY WARRANTY; without even the implied warranty of
12	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13	* GNU General Public License for more details.
14	*
15	*/
16
17	#ifndef __ASM_ARCH_MSM_IRQS_H
18	#define __ASM_ARCH_MSM_IRQS_H
19
20	/* MSM ARM11 Interrupt Numbers */
21	/* See 80-VE113-1 A, pp219-221 */
22
23	#define INT_A9_M2A_0 0
24	#define INT_A9_M2A_1 1
25	#define INT_A9_M2A_2 2
26	#define INT_A9_M2A_3 3
27	#define INT_A9_M2A_4 4
28	#define INT_A9_M2A_5 5
29	#define INT_A9_M2A_6 6
30	#define INT_GP_TIMER_EXP 7
31	#define INT_DEBUG_TIMER_EXP 8
32	#define INT_UART1 9
33	#define INT_UART2 10
34	#define INT_UART3 11
35	#define INT_UART1_RX 12
36	#define INT_UART2_RX 13
37	#define INT_UART3_RX 14
38	#define INT_USB_OTG 15
39	#define INT_MDDI_PRI 16
40	#define INT_MDDI_EXT 17
41	#define INT_MDDI_CLIENT 18
42	#define INT_MDP 19
43	#define INT_GRAPHICS 20
44	#define INT_ADM_AARM 21
45	#define INT_ADSP_A11 22
46	#define INT_ADSP_A9_A11 23
47	#define INT_SDC1_0 24
48	#define INT_SDC1_1 25
49	#define INT_SDC2_0 26
50	#define INT_SDC2_1 27
51	#define INT_KEYSENSE 28
52	#define INT_TCHSCRN_SSBI 29
53	#define INT_TCHSCRN1 30
54	#define INT_TCHSCRN2 31
55
56	#define INT_GPIO_GROUP1 (32 + 0)
57	#define INT_GPIO_GROUP2 (32 + 1)
58	#define INT_PWB_I2C (32 + 2)
59	#define INT_SOFTRESET (32 + 3)
60	#define INT_NAND_WR_ER_DONE (32 + 4)
61	#define INT_NAND_OP_DONE (32 + 5)
62	#define INT_PBUS_ARM11 (32 + 6)
63	#define INT_AXI_MPU_SMI (32 + 7)
64	#define INT_AXI_MPU_EBI1 (32 + 8)
65	#define INT_AD_HSSD (32 + 9)
66	#define INT_ARM11_PMU (32 + 10)
67	#define INT_ARM11_DMA (32 + 11)
68	#define INT_TSIF_IRQ (32 + 12)
69	#define INT_UART1DM_IRQ (32 + 13)
70	#define INT_UART1DM_RX (32 + 14)
71	#define INT_USB_HS (32 + 15)
72	#define INT_SDC3_0 (32 + 16)
73	#define INT_SDC3_1 (32 + 17)
74	#define INT_SDC4_0 (32 + 18)
75	#define INT_SDC4_1 (32 + 19)
76	#define INT_UART2DM_RX (32 + 20)
77	#define INT_UART2DM_IRQ (32 + 21)
78
79	/* 22-31 are reserved */
80
81	#define MSM_IRQ_BIT(irq) (1 << ((irq) & 31))
82
83	#define NR_MSM_IRQS 64
84	#define NR_GPIO_IRQS 122
85	#define NR_BOARD_IRQS 64
86	#define NR_IRQS (NR_MSM_IRQS + NR_GPIO_IRQS + NR_BOARD_IRQS)
87
88	#define MSM_GPIO_TO_INT(n) (NR_MSM_IRQS + (n))
89
90	#endif