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-rw-r--r--include/asm-arm/arch-loki/loki.h97
1 files changed, 97 insertions, 0 deletions
diff --git a/include/asm-arm/arch-loki/loki.h b/include/asm-arm/arch-loki/loki.h
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1/*
2 * include/asm-arm/arch-loki/loki.h
3 *
4 * Generic definitions for Marvell Loki (88RC8480) SoC flavors
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#ifndef __ASM_ARCH_LOKI_H
12#define __ASM_ARCH_LOKI_H
13
14/*
15 * Marvell Loki (88RC8480) address maps.
16 *
17 * phys
18 * d0000000 on-chip peripheral registers
19 * e0000000 PCIe 0 Memory space
20 * e8000000 PCIe 1 Memory space
21 * f0000000 PCIe 0 I/O space
22 * f0100000 PCIe 1 I/O space
23 *
24 * virt phys size
25 * fed00000 d0000000 1M on-chip peripheral registers
26 * fee00000 f0000000 64K PCIe 0 I/O space
27 * fef00000 f0100000 64K PCIe 1 I/O space
28 */
29
30#define LOKI_REGS_PHYS_BASE 0xd0000000
31#define LOKI_REGS_VIRT_BASE 0xfed00000
32#define LOKI_REGS_SIZE SZ_1M
33
34#define LOKI_PCIE0_IO_PHYS_BASE 0xf0000000
35#define LOKI_PCIE0_IO_VIRT_BASE 0xfee00000
36#define LOKI_PCIE0_IO_BUS_BASE 0x00000000
37#define LOKI_PCIE0_IO_SIZE SZ_64K
38
39#define LOKI_PCIE1_IO_PHYS_BASE 0xf0100000
40#define LOKI_PCIE1_IO_VIRT_BASE 0xfef00000
41#define LOKI_PCIE1_IO_BUS_BASE 0x00000000
42#define LOKI_PCIE1_IO_SIZE SZ_64K
43
44#define LOKI_PCIE0_MEM_PHYS_BASE 0xe0000000
45#define LOKI_PCIE0_MEM_SIZE SZ_128M
46
47#define LOKI_PCIE1_MEM_PHYS_BASE 0xe8000000
48#define LOKI_PCIE1_MEM_SIZE SZ_128M
49
50/*
51 * Register Map
52 */
53#define DEV_BUS_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x10000)
54#define DEV_BUS_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x10000)
55#define UART0_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2000)
56#define UART0_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2000)
57#define UART1_PHYS_BASE (DEV_BUS_PHYS_BASE | 0x2100)
58#define UART1_VIRT_BASE (DEV_BUS_VIRT_BASE | 0x2100)
59
60#define BRIDGE_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x20000)
61#define BRIDGE_REG(x) (BRIDGE_VIRT_BASE | (x))
62#define RSTOUTn_MASK (BRIDGE_VIRT_BASE | 0x0108)
63#define SOFT_RESET_OUT_EN 0x00000004
64#define SYSTEM_SOFT_RESET (BRIDGE_VIRT_BASE | 0x010c)
65#define SOFT_RESET 0x00000001
66#define BRIDGE_CAUSE (BRIDGE_VIRT_BASE | 0x0110)
67#define BRIDGE_MASK (BRIDGE_VIRT_BASE | 0x0114)
68#define BRIDGE_INT_TIMER0 0x0002
69#define BRIDGE_INT_TIMER1 0x0004
70#define BRIDGE_INT_TIMER1_CLR 0x0004
71#define IRQ_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0200)
72#define IRQ_CAUSE_OFF 0x0000
73#define IRQ_MASK_OFF 0x0004
74#define TIMER_VIRT_BASE (BRIDGE_VIRT_BASE | 0x0300)
75
76#define PCIE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x30000)
77
78#define PCIE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0x40000)
79
80#define SAS0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x80000)
81
82#define SAS1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0x90000)
83
84#define GE0_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xa0000)
85#define GE0_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xa0000)
86
87#define GE1_PHYS_BASE (LOKI_REGS_PHYS_BASE | 0xb0000)
88#define GE1_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xb0000)
89
90#define DDR_VIRT_BASE (LOKI_REGS_VIRT_BASE | 0xf0000)
91#define DDR_REG(x) (DDR_VIRT_BASE | (x))
92
93
94#define GPIO_MAX 8
95
96
97#endif