diff options
Diffstat (limited to 'include/asm-arm/arch-ks8695/regs-wan.h')
| -rw-r--r-- | include/asm-arm/arch-ks8695/regs-wan.h | 65 |
1 files changed, 0 insertions, 65 deletions
diff --git a/include/asm-arm/arch-ks8695/regs-wan.h b/include/asm-arm/arch-ks8695/regs-wan.h deleted file mode 100644 index 52e35b0d65e4..000000000000 --- a/include/asm-arm/arch-ks8695/regs-wan.h +++ /dev/null | |||
| @@ -1,65 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-ks8695/regs-wan.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2006 Andrew Victor | ||
| 5 | * | ||
| 6 | * KS8695 - WAN Registers and bit definitions. | ||
| 7 | * | ||
| 8 | * This file is licensed under the terms of the GNU General Public | ||
| 9 | * License version 2. This program is licensed "as is" without any | ||
| 10 | * warranty of any kind, whether express or implied. | ||
| 11 | */ | ||
| 12 | |||
| 13 | #ifndef KS8695_WAN_H | ||
| 14 | #define KS8695_WAN_H | ||
| 15 | |||
| 16 | #define KS8695_WAN_OFFSET (0xF0000 + 0x6000) | ||
| 17 | #define KS8695_WAN_VA (KS8695_IO_VA + KS8695_WAN_OFFSET) | ||
| 18 | #define KS8695_WAN_PA (KS8695_IO_PA + KS8695_WAN_OFFSET) | ||
| 19 | |||
| 20 | |||
| 21 | /* | ||
| 22 | * WAN registers | ||
| 23 | */ | ||
| 24 | #define KS8695_WMDTXC (0x00) /* DMA Transmit Control */ | ||
| 25 | #define KS8695_WMDRXC (0x04) /* DMA Receive Control */ | ||
| 26 | #define KS8695_WMDTSC (0x08) /* DMA Transmit Start Command */ | ||
| 27 | #define KS8695_WMDRSC (0x0c) /* DMA Receive Start Command */ | ||
| 28 | #define KS8695_WTDLB (0x10) /* Transmit Descriptor List Base Address */ | ||
| 29 | #define KS8695_WRDLB (0x14) /* Receive Descriptor List Base Address */ | ||
| 30 | #define KS8695_WMAL (0x18) /* MAC Station Address Low */ | ||
| 31 | #define KS8695_WMAH (0x1c) /* MAC Station Address High */ | ||
| 32 | #define KS8695_WMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ | ||
| 33 | #define KS8695_WMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ | ||
| 34 | |||
| 35 | |||
| 36 | /* DMA Transmit Control Register */ | ||
| 37 | #define WMDTXC_WMTRST (1 << 31) /* Soft Reset */ | ||
| 38 | #define WMDTXC_WMTBS (0x3f << 24) /* Transmit Burst Size */ | ||
| 39 | #define WMDTXC_WMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ | ||
| 40 | #define WMDTXC_WMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ | ||
| 41 | #define WMDTXC_WMTICG (1 << 16) /* Transmit IP Checksum Generate */ | ||
| 42 | #define WMDTXC_WMTFCE (1 << 9) /* Transmit Flow Control Enable */ | ||
| 43 | #define WMDTXC_WMTLB (1 << 8) /* Loopback mode */ | ||
| 44 | #define WMDTXC_WMTEP (1 << 2) /* Transmit Enable Padding */ | ||
| 45 | #define WMDTXC_WMTAC (1 << 1) /* Transmit Add CRC */ | ||
| 46 | #define WMDTXC_WMTE (1 << 0) /* TX Enable */ | ||
| 47 | |||
| 48 | /* DMA Receive Control Register */ | ||
| 49 | #define WMDRXC_WMRBS (0x3f << 24) /* Receive Burst Size */ | ||
| 50 | #define WMDRXC_WMRUCC (1 << 18) /* Receive UDP Checksum check */ | ||
| 51 | #define WMDRXC_WMRTCG (1 << 17) /* Receive TCP Checksum check */ | ||
| 52 | #define WMDRXC_WMRICG (1 << 16) /* Receive IP Checksum check */ | ||
| 53 | #define WMDRXC_WMRFCE (1 << 9) /* Receive Flow Control Enable */ | ||
| 54 | #define WMDRXC_WMRB (1 << 6) /* Receive Broadcast */ | ||
| 55 | #define WMDRXC_WMRM (1 << 5) /* Receive Multicast */ | ||
| 56 | #define WMDRXC_WMRU (1 << 4) /* Receive Unicast */ | ||
| 57 | #define WMDRXC_WMRERR (1 << 3) /* Receive Error Frame */ | ||
| 58 | #define WMDRXC_WMRA (1 << 2) /* Receive All */ | ||
| 59 | #define WMDRXC_WMRE (1 << 0) /* RX Enable */ | ||
| 60 | |||
| 61 | /* Additional Station Address High */ | ||
| 62 | #define WMAAH_E (1 << 31) /* Address Enabled */ | ||
| 63 | |||
| 64 | |||
| 65 | #endif | ||