diff options
Diffstat (limited to 'include/asm-arm/arch-ks8695/regs-lan.h')
-rw-r--r-- | include/asm-arm/arch-ks8695/regs-lan.h | 65 |
1 files changed, 65 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ks8695/regs-lan.h b/include/asm-arm/arch-ks8695/regs-lan.h new file mode 100644 index 000000000000..a63bd61c64ed --- /dev/null +++ b/include/asm-arm/arch-ks8695/regs-lan.h | |||
@@ -0,0 +1,65 @@ | |||
1 | /* | ||
2 | * include/asm-arm/arch-ks8695/regs-lan.h | ||
3 | * | ||
4 | * Copyright (C) 2006 Andrew Victor | ||
5 | * | ||
6 | * KS8695 - LAN Registers and bit definitions. | ||
7 | * | ||
8 | * This file is licensed under the terms of the GNU General Public | ||
9 | * License version 2. This program is licensed "as is" without any | ||
10 | * warranty of any kind, whether express or implied. | ||
11 | */ | ||
12 | |||
13 | #ifndef KS8695_LAN_H | ||
14 | #define KS8695_LAN_H | ||
15 | |||
16 | #define KS8695_LAN_OFFSET (0xF0000 + 0x8000) | ||
17 | #define KS8695_LAN_VA (KS8695_IO_VA + KS8695_LAN_OFFSET) | ||
18 | #define KS8695_LAN_PA (KS8695_IO_PA + KS8695_LAN_OFFSET) | ||
19 | |||
20 | |||
21 | /* | ||
22 | * LAN registers | ||
23 | */ | ||
24 | #define KS8695_LMDTXC (0x00) /* DMA Transmit Control */ | ||
25 | #define KS8695_LMDRXC (0x04) /* DMA Receive Control */ | ||
26 | #define KS8695_LMDTSC (0x08) /* DMA Transmit Start Command */ | ||
27 | #define KS8695_LMDRSC (0x0c) /* DMA Receive Start Command */ | ||
28 | #define KS8695_LTDLB (0x10) /* Transmit Descriptor List Base Address */ | ||
29 | #define KS8695_LRDLB (0x14) /* Receive Descriptor List Base Address */ | ||
30 | #define KS8695_LMAL (0x18) /* MAC Station Address Low */ | ||
31 | #define KS8695_LMAH (0x1c) /* MAC Station Address High */ | ||
32 | #define KS8695_LMAAL_(n) (0x80 + ((n)*8)) /* MAC Additional Station Address (0..15) Low */ | ||
33 | #define KS8695_LMAAH_(n) (0x84 + ((n)*8)) /* MAC Additional Station Address (0..15) High */ | ||
34 | |||
35 | |||
36 | /* DMA Transmit Control Register */ | ||
37 | #define LMDTXC_LMTRST (1 << 31) /* Soft Reset */ | ||
38 | #define LMDTXC_LMTBS (0x3f << 24) /* Transmit Burst Size */ | ||
39 | #define LMDTXC_LMTUCG (1 << 18) /* Transmit UDP Checksum Generate */ | ||
40 | #define LMDTXC_LMTTCG (1 << 17) /* Transmit TCP Checksum Generate */ | ||
41 | #define LMDTXC_LMTICG (1 << 16) /* Transmit IP Checksum Generate */ | ||
42 | #define LMDTXC_LMTFCE (1 << 9) /* Transmit Flow Control Enable */ | ||
43 | #define LMDTXC_LMTLB (1 << 8) /* Loopback mode */ | ||
44 | #define LMDTXC_LMTEP (1 << 2) /* Transmit Enable Padding */ | ||
45 | #define LMDTXC_LMTAC (1 << 1) /* Transmit Add CRC */ | ||
46 | #define LMDTXC_LMTE (1 << 0) /* TX Enable */ | ||
47 | |||
48 | /* DMA Receive Control Register */ | ||
49 | #define LMDRXC_LMRBS (0x3f << 24) /* Receive Burst Size */ | ||
50 | #define LMDRXC_LMRUCC (1 << 18) /* Receive UDP Checksum check */ | ||
51 | #define LMDRXC_LMRTCG (1 << 17) /* Receive TCP Checksum check */ | ||
52 | #define LMDRXC_LMRICG (1 << 16) /* Receive IP Checksum check */ | ||
53 | #define LMDRXC_LMRFCE (1 << 9) /* Receive Flow Control Enable */ | ||
54 | #define LMDRXC_LMRB (1 << 6) /* Receive Broadcast */ | ||
55 | #define LMDRXC_LMRM (1 << 5) /* Receive Multicast */ | ||
56 | #define LMDRXC_LMRU (1 << 4) /* Receive Unicast */ | ||
57 | #define LMDRXC_LMRERR (1 << 3) /* Receive Error Frame */ | ||
58 | #define LMDRXC_LMRA (1 << 2) /* Receive All */ | ||
59 | #define LMDRXC_LMRE (1 << 1) /* RX Enable */ | ||
60 | |||
61 | /* Additional Station Address High */ | ||
62 | #define LMAAH_E (1 << 31) /* Address Enabled */ | ||
63 | |||
64 | |||
65 | #endif | ||