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-rw-r--r--include/asm-arm/arch-ixp4xx/coyote.h36
-rw-r--r--include/asm-arm/arch-ixp4xx/debug-macro.S34
-rw-r--r--include/asm-arm/arch-ixp4xx/dma.h26
-rw-r--r--include/asm-arm/arch-ixp4xx/entry-macro.S39
-rw-r--r--include/asm-arm/arch-ixp4xx/gtwx5715.h120
-rw-r--r--include/asm-arm/arch-ixp4xx/hardware.h48
-rw-r--r--include/asm-arm/arch-ixp4xx/io.h388
-rw-r--r--include/asm-arm/arch-ixp4xx/irq.h13
-rw-r--r--include/asm-arm/arch-ixp4xx/irqs.h96
-rw-r--r--include/asm-arm/arch-ixp4xx/ixdp425.h38
-rw-r--r--include/asm-arm/arch-ixp4xx/ixp4xx-regs.h591
-rw-r--r--include/asm-arm/arch-ixp4xx/memory.h61
-rw-r--r--include/asm-arm/arch-ixp4xx/param.h3
-rw-r--r--include/asm-arm/arch-ixp4xx/platform.h126
-rw-r--r--include/asm-arm/arch-ixp4xx/prpmc1100.h33
-rw-r--r--include/asm-arm/arch-ixp4xx/system.h42
-rw-r--r--include/asm-arm/arch-ixp4xx/timex.h13
-rw-r--r--include/asm-arm/arch-ixp4xx/uncompress.h64
-rw-r--r--include/asm-arm/arch-ixp4xx/vmalloc.h17
19 files changed, 1788 insertions, 0 deletions
diff --git a/include/asm-arm/arch-ixp4xx/coyote.h b/include/asm-arm/arch-ixp4xx/coyote.h
new file mode 100644
index 000000000000..dd0c2d2d8503
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/coyote.h
@@ -0,0 +1,36 @@
1/*
2 * include/asm-arm/arch-ixp4xx/coyote.h
3 *
4 * ADI Engineering platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <asm/hardware.h>"
17#endif
18
19#define COYOTE_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
20#define COYOTE_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE * 2
21
22/* PCI controller GPIO to IRQ pin mappings */
23#define COYOTE_PCI_SLOT0_PIN 6
24#define COYOTE_PCI_SLOT1_PIN 11
25
26#define COYOTE_PCI_SLOT0_DEVID 14
27#define COYOTE_PCI_SLOT1_DEVID 15
28
29#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_CS3_BASE_PHYS
30#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
31#define COYOTE_IDE_REGION_SIZE 0x1000
32
33#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
34#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
35#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
36
diff --git a/include/asm-arm/arch-ixp4xx/debug-macro.S b/include/asm-arm/arch-ixp4xx/debug-macro.S
new file mode 100644
index 000000000000..4499ae8e4b44
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/debug-macro.S
@@ -0,0 +1,34 @@
1/* linux/include/asm-arm/arch-ixp4xx/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11*/
12
13 .macro addruart,rx
14 mrc p15, 0, \rx, c1, c0
15 tst \rx, #1 @ MMU enabled?
16 moveq \rx, #0xc8000000
17 movne \rx, #0xff000000
18 add \rx,\rx,#3 @ Uart regs are at off set of 3 if
19 @ byte writes used - Big Endian.
20 .endm
21
22 .macro senduart,rd,rx
23 strb \rd, [\rx]
24 .endm
25
26 .macro waituart,rd,rx
271002: ldrb \rd, [\rx, #0x14]
28 and \rd, \rd, #0x60 @ check THRE and TEMT bits
29 teq \rd, #0x60
30 bne 1002b
31 .endm
32
33 .macro busyuart,rd,rx
34 .endm
diff --git a/include/asm-arm/arch-ixp4xx/dma.h b/include/asm-arm/arch-ixp4xx/dma.h
new file mode 100644
index 000000000000..312065dc0e7a
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/dma.h
@@ -0,0 +1,26 @@
1/*
2 * include/asm-arm/arch-ixp4xx/dma.h
3 *
4 * Copyright (C) 2001-2004 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11#ifndef __ASM_ARCH_DMA_H
12#define __ASM_ARCH_DMA_H
13
14#include <linux/config.h>
15#include <linux/device.h>
16#include <linux/pci.h>
17#include <asm/page.h>
18#include <asm/sizes.h>
19#include <asm/hardware.h>
20
21#define MAX_DMA_ADDRESS (PAGE_OFFSET + SZ_64M)
22
23/* No DMA */
24#define MAX_DMA_CHANNELS 0
25
26#endif /* _ASM_ARCH_DMA_H */
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S
new file mode 100644
index 000000000000..455da64832de
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/entry-macro.S
@@ -0,0 +1,39 @@
1/*
2 * include/asm-arm/arch-ixp4xx/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IXP4xx-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11 .macro disable_fiq
12 .endm
13
14 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
15 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP_OFFSET)
16 ldr \irqstat, [\irqstat] @ get interrupts
17 cmp \irqstat, #0
18 beq 1001f
19 clz \irqnr, \irqstat
20 mov \base, #31
21 subs \irqnr, \base, \irqnr
22
231001:
24 /*
25 * IXP465 has an upper IRQ status register
26 */
27#if defined(CONFIG_CPU_IXP46X)
28 bne 1002f
29 ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
30 ldr \irqstat, [\irqstat] @ get upper interrupts
31 mov \irqnr, #63
32 clz \irqstat, \irqstat
33 cmp \irqstat, #32
34 subne \irqnr, \irqnr, \irqstat
351002:
36#endif
37 .endm
38
39
diff --git a/include/asm-arm/arch-ixp4xx/gtwx5715.h b/include/asm-arm/arch-ixp4xx/gtwx5715.h
new file mode 100644
index 000000000000..fc460af70627
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/gtwx5715.h
@@ -0,0 +1,120 @@
1/*
2 * include/asm-arm/arch-ixp4xx/gtwx5715.h
3 *
4 * Gemtek GTWX5715 Gateway (Linksys WRV54G)
5 *
6 * Copyright 2004 (c) George T. Joseph
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * as published by the Free Software Foundation; either version 2
11 * of the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
21 */
22
23#ifndef __ASM_ARCH_HARDWARE_H__
24#error "Do not include this directly, instead #include <asm/hardware.h>"
25#endif
26#include "irqs.h"
27
28#define GTWX5715_GPIO0 0
29#define GTWX5715_GPIO1 1
30#define GTWX5715_GPIO2 2
31#define GTWX5715_GPIO3 3
32#define GTWX5715_GPIO4 4
33#define GTWX5715_GPIO5 5
34#define GTWX5715_GPIO6 6
35#define GTWX5715_GPIO7 7
36#define GTWX5715_GPIO8 8
37#define GTWX5715_GPIO9 9
38#define GTWX5715_GPIO10 10
39#define GTWX5715_GPIO11 11
40#define GTWX5715_GPIO12 12
41#define GTWX5715_GPIO13 13
42#define GTWX5715_GPIO14 14
43
44#define GTWX5715_GPIO0_IRQ IRQ_IXP4XX_GPIO0
45#define GTWX5715_GPIO1_IRQ IRQ_IXP4XX_GPIO1
46#define GTWX5715_GPIO2_IRQ IRQ_IXP4XX_GPIO2
47#define GTWX5715_GPIO3_IRQ IRQ_IXP4XX_GPIO3
48#define GTWX5715_GPIO4_IRQ IRQ_IXP4XX_GPIO4
49#define GTWX5715_GPIO5_IRQ IRQ_IXP4XX_GPIO5
50#define GTWX5715_GPIO6_IRQ IRQ_IXP4XX_GPIO6
51#define GTWX5715_GPIO7_IRQ IRQ_IXP4XX_GPIO7
52#define GTWX5715_GPIO8_IRQ IRQ_IXP4XX_GPIO8
53#define GTWX5715_GPIO9_IRQ IRQ_IXP4XX_GPIO9
54#define GTWX5715_GPIO10_IRQ IRQ_IXP4XX_GPIO10
55#define GTWX5715_GPIO11_IRQ IRQ_IXP4XX_GPIO11
56#define GTWX5715_GPIO12_IRQ IRQ_IXP4XX_GPIO12
57#define GTWX5715_GPIO13_IRQ IRQ_IXP4XX_SW_INT1
58#define GTWX5715_GPIO14_IRQ IRQ_IXP4XX_SW_INT2
59
60
61#define GTWX5715_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
62#define GTWX5715_FLASH_SIZE (0x00800000)
63
64/* PCI controller GPIO to IRQ pin mappings
65
66 INTA INTB
67SLOT 0 10 11
68SLOT 1 11 10
69
70*/
71
72#define GTWX5715_PCI_SLOT0_DEVID 0
73#define GTWX5715_PCI_SLOT0_INTA_GPIO GTWX5715_GPIO10
74#define GTWX5715_PCI_SLOT0_INTB_GPIO GTWX5715_GPIO11
75#define GTWX5715_PCI_SLOT0_INTA_IRQ GTWX5715_GPIO10_IRQ
76#define GTWX5715_PCI_SLOT0_INTB_IRQ GTWX5715_GPIO11_IRQ
77
78#define GTWX5715_PCI_SLOT1_DEVID 1
79#define GTWX5715_PCI_SLOT1_INTA_GPIO GTWX5715_GPIO11
80#define GTWX5715_PCI_SLOT1_INTB_GPIO GTWX5715_GPIO10
81#define GTWX5715_PCI_SLOT1_INTA_IRQ GTWX5715_GPIO11_IRQ
82#define GTWX5715_PCI_SLOT1_INTB_IRQ GTWX5715_GPIO10_IRQ
83
84#define GTWX5715_PCI_SLOT_COUNT 2
85#define GTWX5715_PCI_INT_PIN_COUNT 2
86
87/*
88 * GPIO 5,6,7 and12 are hard wired to the Kendin KS8995M Switch
89 * and operate as an SPI type interface. The details of the interface
90 * are available on Kendin/Micrel's web site.
91 */
92
93#define GTWX5715_KSSPI_SELECT GTWX5715_GPIO5
94#define GTWX5715_KSSPI_TXD GTWX5715_GPIO6
95#define GTWX5715_KSSPI_CLOCK GTWX5715_GPIO7
96#define GTWX5715_KSSPI_RXD GTWX5715_GPIO12
97
98/*
99 * The "reset" button is wired to GPIO 3.
100 * The GPIO is brought "low" when the button is pushed.
101 */
102
103#define GTWX5715_BUTTON_GPIO GTWX5715_GPIO3
104#define GTWX5715_BUTTON_IRQ GTWX5715_GPIO3_IRQ
105
106/*
107 * Board Label Front Label
108 * LED1 Power
109 * LED2 Wireless-G
110 * LED3 not populated but could be
111 * LED4 Internet
112 * LED5 - LED8 Controlled by KS8995M Switch
113 * LED9 DMZ
114 */
115
116#define GTWX5715_LED1_GPIO GTWX5715_GPIO2
117#define GTWX5715_LED2_GPIO GTWX5715_GPIO9
118#define GTWX5715_LED3_GPIO GTWX5715_GPIO8
119#define GTWX5715_LED4_GPIO GTWX5715_GPIO1
120#define GTWX5715_LED9_GPIO GTWX5715_GPIO4
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
new file mode 100644
index 000000000000..4ac964b9078a
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -0,0 +1,48 @@
1/*
2 * include/asm-arm/arch-ixp4xx/hardware.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 * Copyright (C) 2003-2004 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13/*
14 * Hardware definitions for IXP4xx based systems
15 */
16
17#ifndef __ASM_ARCH_HARDWARE_H__
18#define __ASM_ARCH_HARDWARE_H__
19
20#define PCIBIOS_MIN_IO 0x00001000
21#define PCIBIOS_MIN_MEM 0x48000000
22
23/*
24 * We override the standard dma-mask routines for bouncing.
25 */
26#define HAVE_ARCH_PCI_SET_DMA_MASK
27
28#define pcibios_assign_all_busses() 1
29
30#if defined(CONFIG_CPU_IXP465) && !defined(__ASSEMBLY__)
31extern unsigned int processor_id;
32#define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200)
33#else
34#define cpu_is_ixp465() (0)
35#endif
36
37/* Register locations and bits */
38#include "ixp4xx-regs.h"
39
40/* Platform helper functions and definitions */
41#include "platform.h"
42
43/* Platform specific details */
44#include "ixdp425.h"
45#include "coyote.h"
46#include "prpmc1100.h"
47
48#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
new file mode 100644
index 000000000000..c27b9d3079a7
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -0,0 +1,388 @@
1/*
2 * linux/include/asm-arm/arch-ixp4xx/io.h
3 *
4 * Author: Deepak Saxena <dsaxena@plexity.net>
5 *
6 * Copyright (C) 2002-2004 MontaVista Software, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#ifndef __ASM_ARM_ARCH_IO_H
14#define __ASM_ARM_ARCH_IO_H
15
16#include <asm/hardware.h>
17
18#define IO_SPACE_LIMIT 0xffff0000
19
20#define BIT(x) ((1)<<(x))
21
22
23extern int (*ixp4xx_pci_read)(u32 addr, u32 cmd, u32* data);
24extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
25
26
27/*
28 * IXP4xx provides two methods of accessing PCI memory space:
29 *
30 * 1) A direct mapped window from 0x48000000 to 0x4bffffff (64MB).
31 * To access PCI via this space, we simply ioremap() the BAR
32 * into the kernel and we can use the standard read[bwl]/write[bwl]
33 * macros. This is the preffered method due to speed but it
34 * limits the system to just 64MB of PCI memory. This can be
35 * problamatic if using video cards and other memory-heavy
36 * targets.
37 *
38 * 2) If > 64MB of memory space is required, the IXP4xx can be configured
39 * to use indirect registers to access PCI (as we do below for I/O
40 * transactions). This allows for up to 128MB (0x48000000 to 0x4fffffff)
41 * of memory on the bus. The disadvantadge of this is that every
42 * PCI access requires three local register accesses plus a spinlock,
43 * but in some cases the performance hit is acceptable. In addition,
44 * you cannot mmap() PCI devices in this case.
45 *
46 */
47#ifndef CONFIG_IXP4XX_INDIRECT_PCI
48
49#define __mem_pci(a) (a)
50
51#else
52
53#include <linux/mm.h>
54
55/*
56 * In the case of using indirect PCI, we simply return the actual PCI
57 * address and our read/write implementation use that to drive the
58 * access registers. If something outside of PCI is ioremap'd, we
59 * fallback to the default.
60 */
61static inline void __iomem *
62__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags, unsigned long align)
63{
64 extern void __iomem * __ioremap(unsigned long, size_t, unsigned long, unsigned long);
65 if((addr < 0x48000000) || (addr > 0x4fffffff))
66 return __ioremap(addr, size, flags, align);
67
68 return (void *)addr;
69}
70
71static inline void
72__ixp4xx_iounmap(void __iomem *addr)
73{
74 extern void __iounmap(void __iomem *addr);
75
76 if ((u32)addr >= VMALLOC_START)
77 __iounmap(addr);
78}
79
80#define __arch_ioremap(a, s, f, x) __ixp4xx_ioremap(a, s, f, x)
81#define __arch_iounmap(a) __ixp4xx_iounmap(a)
82
83#define writeb(p, v) __ixp4xx_writeb(p, v)
84#define writew(p, v) __ixp4xx_writew(p, v)
85#define writel(p, v) __ixp4xx_writel(p, v)
86
87#define writesb(p, v, l) __ixp4xx_writesb(p, v, l)
88#define writesw(p, v, l) __ixp4xx_writesw(p, v, l)
89#define writesl(p, v, l) __ixp4xx_writesl(p, v, l)
90
91#define readb(p) __ixp4xx_readb(p)
92#define readw(p) __ixp4xx_readw(p)
93#define readl(p) __ixp4xx_readl(p)
94
95#define readsb(p, v, l) __ixp4xx_readsb(p, v, l)
96#define readsw(p, v, l) __ixp4xx_readsw(p, v, l)
97#define readsl(p, v, l) __ixp4xx_readsl(p, v, l)
98
99static inline void
100__ixp4xx_writeb(u8 value, u32 addr)
101{
102 u32 n, byte_enables, data;
103
104 if (addr >= VMALLOC_START) {
105 __raw_writeb(value, addr);
106 return;
107 }
108
109 n = addr % 4;
110 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
111 data = value << (8*n);
112 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
113}
114
115static inline void
116__ixp4xx_writesb(u32 bus_addr, u8 *vaddr, int count)
117{
118 while (count--)
119 writeb(*vaddr++, bus_addr);
120}
121
122static inline void
123__ixp4xx_writew(u16 value, u32 addr)
124{
125 u32 n, byte_enables, data;
126
127 if (addr >= VMALLOC_START) {
128 __raw_writew(value, addr);
129 return;
130 }
131
132 n = addr % 4;
133 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
134 data = value << (8*n);
135 ixp4xx_pci_write(addr, byte_enables | NP_CMD_MEMWRITE, data);
136}
137
138static inline void
139__ixp4xx_writesw(u32 bus_addr, u16 *vaddr, int count)
140{
141 while (count--)
142 writew(*vaddr++, bus_addr);
143}
144
145static inline void
146__ixp4xx_writel(u32 value, u32 addr)
147{
148 if (addr >= VMALLOC_START) {
149 __raw_writel(value, addr);
150 return;
151 }
152
153 ixp4xx_pci_write(addr, NP_CMD_MEMWRITE, value);
154}
155
156static inline void
157__ixp4xx_writesl(u32 bus_addr, u32 *vaddr, int count)
158{
159 while (count--)
160 writel(*vaddr++, bus_addr);
161}
162
163static inline unsigned char
164__ixp4xx_readb(u32 addr)
165{
166 u32 n, byte_enables, data;
167
168 if (addr >= VMALLOC_START)
169 return __raw_readb(addr);
170
171 n = addr % 4;
172 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
173 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
174 return 0xff;
175
176 return data >> (8*n);
177}
178
179static inline void
180__ixp4xx_readsb(u32 bus_addr, u8 *vaddr, u32 count)
181{
182 while (count--)
183 *vaddr++ = readb(bus_addr);
184}
185
186static inline unsigned short
187__ixp4xx_readw(u32 addr)
188{
189 u32 n, byte_enables, data;
190
191 if (addr >= VMALLOC_START)
192 return __raw_readw(addr);
193
194 n = addr % 4;
195 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
196 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_MEMREAD, &data))
197 return 0xffff;
198
199 return data>>(8*n);
200}
201
202static inline void
203__ixp4xx_readsw(u32 bus_addr, u16 *vaddr, u32 count)
204{
205 while (count--)
206 *vaddr++ = readw(bus_addr);
207}
208
209static inline unsigned long
210__ixp4xx_readl(u32 addr)
211{
212 u32 data;
213
214 if (addr >= VMALLOC_START)
215 return __raw_readl(addr);
216
217 if (ixp4xx_pci_read(addr, NP_CMD_MEMREAD, &data))
218 return 0xffffffff;
219
220 return data;
221}
222
223static inline void
224__ixp4xx_readsl(u32 bus_addr, u32 *vaddr, u32 count)
225{
226 while (count--)
227 *vaddr++ = readl(bus_addr);
228}
229
230
231/*
232 * We can use the built-in functions b/c they end up calling writeb/readb
233 */
234#define memset_io(c,v,l) _memset_io((c),(v),(l))
235#define memcpy_fromio(a,c,l) _memcpy_fromio((a),(c),(l))
236#define memcpy_toio(c,a,l) _memcpy_toio((c),(a),(l))
237
238#define eth_io_copy_and_sum(s,c,l,b) \
239 eth_copy_and_sum((s),__mem_pci(c),(l),(b))
240
241static inline int
242check_signature(unsigned long bus_addr, const unsigned char *signature,
243 int length)
244{
245 int retval = 0;
246 do {
247 if (readb(bus_addr) != *signature)
248 goto out;
249 bus_addr++;
250 signature++;
251 length--;
252 } while (length);
253 retval = 1;
254out:
255 return retval;
256}
257
258#endif
259
260/*
261 * IXP4xx does not have a transparent cpu -> PCI I/O translation
262 * window. Instead, it has a set of registers that must be tweaked
263 * with the proper byte lanes, command types, and address for the
264 * transaction. This means that we need to override the default
265 * I/O functions.
266 */
267#define outb(p, v) __ixp4xx_outb(p, v)
268#define outw(p, v) __ixp4xx_outw(p, v)
269#define outl(p, v) __ixp4xx_outl(p, v)
270
271#define outsb(p, v, l) __ixp4xx_outsb(p, v, l)
272#define outsw(p, v, l) __ixp4xx_outsw(p, v, l)
273#define outsl(p, v, l) __ixp4xx_outsl(p, v, l)
274
275#define inb(p) __ixp4xx_inb(p)
276#define inw(p) __ixp4xx_inw(p)
277#define inl(p) __ixp4xx_inl(p)
278
279#define insb(p, v, l) __ixp4xx_insb(p, v, l)
280#define insw(p, v, l) __ixp4xx_insw(p, v, l)
281#define insl(p, v, l) __ixp4xx_insl(p, v, l)
282
283
284static inline void
285__ixp4xx_outb(u8 value, u32 addr)
286{
287 u32 n, byte_enables, data;
288 n = addr % 4;
289 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
290 data = value << (8*n);
291 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
292}
293
294static inline void
295__ixp4xx_outsb(u32 io_addr, const u8 *vaddr, u32 count)
296{
297 while (count--)
298 outb(*vaddr++, io_addr);
299}
300
301static inline void
302__ixp4xx_outw(u16 value, u32 addr)
303{
304 u32 n, byte_enables, data;
305 n = addr % 4;
306 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
307 data = value << (8*n);
308 ixp4xx_pci_write(addr, byte_enables | NP_CMD_IOWRITE, data);
309}
310
311static inline void
312__ixp4xx_outsw(u32 io_addr, const u16 *vaddr, u32 count)
313{
314 while (count--)
315 outw(cpu_to_le16(*vaddr++), io_addr);
316}
317
318static inline void
319__ixp4xx_outl(u32 value, u32 addr)
320{
321 ixp4xx_pci_write(addr, NP_CMD_IOWRITE, value);
322}
323
324static inline void
325__ixp4xx_outsl(u32 io_addr, const u32 *vaddr, u32 count)
326{
327 while (count--)
328 outl(*vaddr++, io_addr);
329}
330
331static inline u8
332__ixp4xx_inb(u32 addr)
333{
334 u32 n, byte_enables, data;
335 n = addr % 4;
336 byte_enables = (0xf & ~BIT(n)) << IXP4XX_PCI_NP_CBE_BESL;
337 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
338 return 0xff;
339
340 return data >> (8*n);
341}
342
343static inline void
344__ixp4xx_insb(u32 io_addr, u8 *vaddr, u32 count)
345{
346 while (count--)
347 *vaddr++ = inb(io_addr);
348}
349
350static inline u16
351__ixp4xx_inw(u32 addr)
352{
353 u32 n, byte_enables, data;
354 n = addr % 4;
355 byte_enables = (0xf & ~(BIT(n) | BIT(n+1))) << IXP4XX_PCI_NP_CBE_BESL;
356 if (ixp4xx_pci_read(addr, byte_enables | NP_CMD_IOREAD, &data))
357 return 0xffff;
358
359 return data>>(8*n);
360}
361
362static inline void
363__ixp4xx_insw(u32 io_addr, u16 *vaddr, u32 count)
364{
365 while (count--)
366 *vaddr++ = le16_to_cpu(inw(io_addr));
367}
368
369static inline u32
370__ixp4xx_inl(u32 addr)
371{
372 u32 data;
373 if (ixp4xx_pci_read(addr, NP_CMD_IOREAD, &data))
374 return 0xffffffff;
375
376 return data;
377}
378
379static inline void
380__ixp4xx_insl(u32 io_addr, u32 *vaddr, u32 count)
381{
382 while (count--)
383 *vaddr++ = inl(io_addr);
384}
385
386
387#endif // __ASM_ARM_ARCH_IO_H
388
diff --git a/include/asm-arm/arch-ixp4xx/irq.h b/include/asm-arm/arch-ixp4xx/irq.h
new file mode 100644
index 000000000000..87da70695f0a
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/irq.h
@@ -0,0 +1,13 @@
1/*
2 * irq.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#define fixup_irq(irq) (irq)
13
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
new file mode 100644
index 000000000000..ca808281c7f9
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -0,0 +1,96 @@
1/*
2 * include/asm-arm/arch-ixp4xx/irqs.h
3 *
4 * IRQ definitions for IXP4XX based systems
5 *
6 * Copyright (C) 2002 Intel Corporation.
7 * Copyright (C) 2003 MontaVista Software, Inc.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 *
13 */
14
15#ifndef _ARCH_IXP4XX_IRQS_H_
16#define _ARCH_IXP4XX_IRQS_H_
17
18
19#define IRQ_IXP4XX_NPEA 0
20#define IRQ_IXP4XX_NPEB 1
21#define IRQ_IXP4XX_NPEC 2
22#define IRQ_IXP4XX_QM1 3
23#define IRQ_IXP4XX_QM2 4
24#define IRQ_IXP4XX_TIMER1 5
25#define IRQ_IXP4XX_GPIO0 6
26#define IRQ_IXP4XX_GPIO1 7
27#define IRQ_IXP4XX_PCI_INT 8
28#define IRQ_IXP4XX_PCI_DMA1 9
29#define IRQ_IXP4XX_PCI_DMA2 10
30#define IRQ_IXP4XX_TIMER2 11
31#define IRQ_IXP4XX_USB 12
32#define IRQ_IXP4XX_UART2 13
33#define IRQ_IXP4XX_TIMESTAMP 14
34#define IRQ_IXP4XX_UART1 15
35#define IRQ_IXP4XX_WDOG 16
36#define IRQ_IXP4XX_AHB_PMU 17
37#define IRQ_IXP4XX_XSCALE_PMU 18
38#define IRQ_IXP4XX_GPIO2 19
39#define IRQ_IXP4XX_GPIO3 20
40#define IRQ_IXP4XX_GPIO4 21
41#define IRQ_IXP4XX_GPIO5 22
42#define IRQ_IXP4XX_GPIO6 23
43#define IRQ_IXP4XX_GPIO7 24
44#define IRQ_IXP4XX_GPIO8 25
45#define IRQ_IXP4XX_GPIO9 26
46#define IRQ_IXP4XX_GPIO10 27
47#define IRQ_IXP4XX_GPIO11 28
48#define IRQ_IXP4XX_GPIO12 29
49#define IRQ_IXP4XX_SW_INT1 30
50#define IRQ_IXP4XX_SW_INT2 31
51#define IRQ_IXP4XX_USB_HOST 32
52#define IRQ_IXP4XX_I2C 33
53#define IRQ_IXP4XX_SSP 34
54#define IRQ_IXP4XX_TSYNC 35
55#define IRQ_IXP4XX_EAU_DONE 36
56#define IRQ_IXP4XX_SHA_DONE 37
57#define IRQ_IXP4XX_SWCP_PE 58
58#define IRQ_IXP4XX_QM_PE 60
59#define IRQ_IXP4XX_MCU_ECC 61
60#define IRQ_IXP4XX_EXP_PE 62
61
62/*
63 * Only first 32 sources are valid if running on IXP42x systems
64 */
65#ifndef CONFIG_CPU_IXP46X
66#define NR_IRQS 32
67#else
68#define NR_IRQS 64
69#endif
70
71#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
72
73/*
74 * IXDP425 board IRQs
75 */
76#define IRQ_IXDP425_PCI_INTA IRQ_IXP4XX_GPIO11
77#define IRQ_IXDP425_PCI_INTB IRQ_IXP4XX_GPIO10
78#define IRQ_IXDP425_PCI_INTC IRQ_IXP4XX_GPIO9
79#define IRQ_IXDP425_PCI_INTD IRQ_IXP4XX_GPIO8
80
81/*
82 * PrPMC1100 Board IRQs
83 */
84#define IRQ_PRPMC1100_PCI_INTA IRQ_IXP4XX_GPIO11
85#define IRQ_PRPMC1100_PCI_INTB IRQ_IXP4XX_GPIO10
86#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
87#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
88
89/*
90 * ADI Coyote Board IRQs
91 */
92#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
93#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
94#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
95
96#endif
diff --git a/include/asm-arm/arch-ixp4xx/ixdp425.h b/include/asm-arm/arch-ixp4xx/ixdp425.h
new file mode 100644
index 000000000000..7d21bf941379
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/ixdp425.h
@@ -0,0 +1,38 @@
1/*
2 * include/asm-arm/arch-ixp4xx/ixdp425.h
3 *
4 * IXDP425 platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <asm/hardware.h>"
17#endif
18
19#define IXDP425_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
20#define IXDP425_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
21
22#define IXDP425_SDA_PIN 7
23#define IXDP425_SCL_PIN 6
24
25/*
26 * IXDP425 PCI IRQs
27 */
28#define IXDP425_PCI_MAX_DEV 4
29#define IXDP425_PCI_IRQ_LINES 4
30
31
32/* PCI controller GPIO to IRQ pin mappings */
33#define IXDP425_PCI_INTA_PIN 11
34#define IXDP425_PCI_INTB_PIN 10
35#define IXDP425_PCI_INTC_PIN 9
36#define IXDP425_PCI_INTD_PIN 8
37
38
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
new file mode 100644
index 000000000000..8eeb1db6309d
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -0,0 +1,591 @@
1/*
2 * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3 *
4 * Register definitions for IXP4xx chipset. This file contains
5 * register location and bit definitions only. Platform specific
6 * definitions and helper function declarations are in platform.h
7 * and machine-name.h.
8 *
9 * Copyright (C) 2002 Intel Corporation.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <asm/hardware.h>"
20#endif
21
22#ifndef _ASM_ARM_IXP4XX_H_
23#define _ASM_ARM_IXP4XX_H_
24
25/*
26 * IXP4xx Linux Memory Map:
27 *
28 * Phy Size Virt Description
29 * =========================================================================
30 *
31 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
32 *
33 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
34 *
35 * 0x50000000 0x10000000 ioremap'd EXP BUS
36 *
37 * 0x6000000 0x00004000 ioremap'd QMgr
38 *
39 * 0xC0000000 0x00001000 0xffbfe000 PCI CFG
40 *
41 * 0xC4000000 0x00001000 0xffbfd000 EXP CFG
42 *
43 * 0xC8000000 0x0000C000 0xffbf2000 On-Chip Peripherals
44 */
45
46/*
47 * Queue Manager
48 */
49#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
50
51/*
52 * Expansion BUS Configuration registers
53 */
54#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
55#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFD000)
56#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
57
58/*
59 * PCI Config registers
60 */
61#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
62#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFE000)
63#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
64
65/*
66 * Peripheral space
67 */
68#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
69#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000)
70#define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000)
71
72#define IXP4XX_EXP_CS0_OFFSET 0x00
73#define IXP4XX_EXP_CS1_OFFSET 0x04
74#define IXP4XX_EXP_CS2_OFFSET 0x08
75#define IXP4XX_EXP_CS3_OFFSET 0x0C
76#define IXP4XX_EXP_CS4_OFFSET 0x10
77#define IXP4XX_EXP_CS5_OFFSET 0x14
78#define IXP4XX_EXP_CS6_OFFSET 0x18
79#define IXP4XX_EXP_CS7_OFFSET 0x1C
80#define IXP4XX_EXP_CFG0_OFFSET 0x20
81#define IXP4XX_EXP_CFG1_OFFSET 0x24
82#define IXP4XX_EXP_CFG2_OFFSET 0x28
83#define IXP4XX_EXP_CFG3_OFFSET 0x2C
84
85/*
86 * Expansion Bus Controller registers.
87 */
88#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
89
90#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
91#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
92#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
93#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
94#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
95#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
96#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
97#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
98
99#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
100#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
101#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
102#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
103
104
105/*
106 * Peripheral Space Register Region Base Addresses
107 */
108#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
109#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
110#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
111#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
112#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
113#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
114#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
115#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
116#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
117
118#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
119#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
120#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
121#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
122#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
123#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
124#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
125#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
126#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
127
128/*
129 * Constants to make it easy to access Interrupt Controller registers
130 */
131#define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */
132#define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */
133#define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
134#define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */
135#define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */
136#define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */
137#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
138#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
139
140/*
141 * IXP465-only
142 */
143#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */
144#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */
145#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */
146#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */
147#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */
148#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */
149
150
151/*
152 * Interrupt Controller Register Definitions.
153 */
154
155#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
156
157#define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
158#define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
159#define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
160#define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
161#define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
162#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
163#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
164#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
165#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
166#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
167#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
168#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
169#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
170#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
171
172/*
173 * Constants to make it easy to access GPIO registers
174 */
175#define IXP4XX_GPIO_GPOUTR_OFFSET 0x00
176#define IXP4XX_GPIO_GPOER_OFFSET 0x04
177#define IXP4XX_GPIO_GPINR_OFFSET 0x08
178#define IXP4XX_GPIO_GPISR_OFFSET 0x0C
179#define IXP4XX_GPIO_GPIT1R_OFFSET 0x10
180#define IXP4XX_GPIO_GPIT2R_OFFSET 0x14
181#define IXP4XX_GPIO_GPCLKR_OFFSET 0x18
182#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
183
184/*
185 * GPIO Register Definitions.
186 * [Only perform 32bit reads/writes]
187 */
188#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
189
190#define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
191#define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
192#define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
193#define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
194#define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
195#define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
196#define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
197#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
198
199/*
200 * GPIO register bit definitions
201 */
202
203/* Interrupt styles
204 */
205#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
206#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
207#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
208#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
209#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
210
211/*
212 * Mask used to clear interrupt styles
213 */
214#define IXP4XX_GPIO_STYLE_CLEAR 0x7
215#define IXP4XX_GPIO_STYLE_SIZE 3
216
217/*
218 * Constants to make it easy to access Timer Control/Status registers
219 */
220#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
221#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
222#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
223#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
224#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
225#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
226#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
227#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
228#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
229
230/*
231 * Operating System Timer Register Definitions.
232 */
233
234#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
235
236#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
237#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
238#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
239#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
240#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
241#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
242#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
243#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
244#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
245
246/*
247 * Timer register values and bit definitions
248 */
249#define IXP4XX_OST_ENABLE 0x00000001
250#define IXP4XX_OST_ONE_SHOT 0x00000002
251/* Low order bits of reload value ignored */
252#define IXP4XX_OST_RELOAD_MASK 0x00000003
253#define IXP4XX_OST_DISABLED 0x00000000
254#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
255#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
256#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
257#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
258#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
259
260#define IXP4XX_WDT_KEY 0x0000482E
261
262#define IXP4XX_WDT_RESET_ENABLE 0x00000001
263#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
264#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
265
266
267/*
268 * Constants to make it easy to access PCI Control/Status registers
269 */
270#define PCI_NP_AD_OFFSET 0x00
271#define PCI_NP_CBE_OFFSET 0x04
272#define PCI_NP_WDATA_OFFSET 0x08
273#define PCI_NP_RDATA_OFFSET 0x0c
274#define PCI_CRP_AD_CBE_OFFSET 0x10
275#define PCI_CRP_WDATA_OFFSET 0x14
276#define PCI_CRP_RDATA_OFFSET 0x18
277#define PCI_CSR_OFFSET 0x1c
278#define PCI_ISR_OFFSET 0x20
279#define PCI_INTEN_OFFSET 0x24
280#define PCI_DMACTRL_OFFSET 0x28
281#define PCI_AHBMEMBASE_OFFSET 0x2c
282#define PCI_AHBIOBASE_OFFSET 0x30
283#define PCI_PCIMEMBASE_OFFSET 0x34
284#define PCI_AHBDOORBELL_OFFSET 0x38
285#define PCI_PCIDOORBELL_OFFSET 0x3C
286#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
287#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
288#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
289#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
290#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
291#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
292
293/*
294 * PCI Control/Status Registers
295 */
296#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
297
298#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
299#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
300#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
301#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
302#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
303#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
304#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
305#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
306#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
307#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
308#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
309#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
310#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
311#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
312#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
313#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
314#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
315#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
316#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
317#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
318#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
319#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
320
321/*
322 * PCI register values and bit definitions
323 */
324
325/* CSR bit definitions */
326#define PCI_CSR_HOST 0x00000001
327#define PCI_CSR_ARBEN 0x00000002
328#define PCI_CSR_ADS 0x00000004
329#define PCI_CSR_PDS 0x00000008
330#define PCI_CSR_ABE 0x00000010
331#define PCI_CSR_DBT 0x00000020
332#define PCI_CSR_ASE 0x00000100
333#define PCI_CSR_IC 0x00008000
334
335/* ISR (Interrupt status) Register bit definitions */
336#define PCI_ISR_PSE 0x00000001
337#define PCI_ISR_PFE 0x00000002
338#define PCI_ISR_PPE 0x00000004
339#define PCI_ISR_AHBE 0x00000008
340#define PCI_ISR_APDC 0x00000010
341#define PCI_ISR_PADC 0x00000020
342#define PCI_ISR_ADB 0x00000040
343#define PCI_ISR_PDB 0x00000080
344
345/* INTEN (Interrupt Enable) Register bit definitions */
346#define PCI_INTEN_PSE 0x00000001
347#define PCI_INTEN_PFE 0x00000002
348#define PCI_INTEN_PPE 0x00000004
349#define PCI_INTEN_AHBE 0x00000008
350#define PCI_INTEN_APDC 0x00000010
351#define PCI_INTEN_PADC 0x00000020
352#define PCI_INTEN_ADB 0x00000040
353#define PCI_INTEN_PDB 0x00000080
354
355/*
356 * Shift value for byte enable on NP cmd/byte enable register
357 */
358#define IXP4XX_PCI_NP_CBE_BESL 4
359
360/*
361 * PCI commands supported by NP access unit
362 */
363#define NP_CMD_IOREAD 0x2
364#define NP_CMD_IOWRITE 0x3
365#define NP_CMD_CONFIGREAD 0xa
366#define NP_CMD_CONFIGWRITE 0xb
367#define NP_CMD_MEMREAD 0x6
368#define NP_CMD_MEMWRITE 0x7
369
370/*
371 * Constants for CRP access into local config space
372 */
373#define CRP_AD_CBE_BESL 20
374#define CRP_AD_CBE_WRITE 0x00010000
375
376
377/*
378 * USB Device Controller
379 *
380 * These are used by the USB gadget driver, so they don't follow the
381 * IXP4XX_ naming convetions.
382 *
383 */
384# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
385
386/* UDC Undocumented - Reserved1 */
387#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
388/* UDC Undocumented - Reserved2 */
389#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
390/* UDC Undocumented - Reserved3 */
391#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
392/* UDC Control Register */
393#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
394/* UDC Endpoint 0 Control/Status Register */
395#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
396/* UDC Endpoint 1 (IN) Control/Status Register */
397#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
398/* UDC Endpoint 2 (OUT) Control/Status Register */
399#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
400/* UDC Endpoint 3 (IN) Control/Status Register */
401#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
402/* UDC Endpoint 4 (OUT) Control/Status Register */
403#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
404/* UDC Endpoint 5 (Interrupt) Control/Status Register */
405#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
406/* UDC Endpoint 6 (IN) Control/Status Register */
407#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
408/* UDC Endpoint 7 (OUT) Control/Status Register */
409#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
410/* UDC Endpoint 8 (IN) Control/Status Register */
411#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
412/* UDC Endpoint 9 (OUT) Control/Status Register */
413#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
414/* UDC Endpoint 10 (Interrupt) Control/Status Register */
415#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
416/* UDC Endpoint 11 (IN) Control/Status Register */
417#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
418/* UDC Endpoint 12 (OUT) Control/Status Register */
419#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
420/* UDC Endpoint 13 (IN) Control/Status Register */
421#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
422/* UDC Endpoint 14 (OUT) Control/Status Register */
423#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
424/* UDC Endpoint 15 (Interrupt) Control/Status Register */
425#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
426/* UDC Frame Number Register High */
427#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
428/* UDC Frame Number Register Low */
429#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
430/* UDC Byte Count Reg 2 */
431#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
432/* UDC Byte Count Reg 4 */
433#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
434/* UDC Byte Count Reg 7 */
435#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
436/* UDC Byte Count Reg 9 */
437#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
438/* UDC Byte Count Reg 12 */
439#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
440/* UDC Byte Count Reg 14 */
441#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
442/* UDC Endpoint 0 Data Register */
443#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
444/* UDC Endpoint 1 Data Register */
445#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
446/* UDC Endpoint 2 Data Register */
447#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
448/* UDC Endpoint 3 Data Register */
449#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
450/* UDC Endpoint 4 Data Register */
451#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
452/* UDC Endpoint 5 Data Register */
453#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
454/* UDC Endpoint 6 Data Register */
455#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
456/* UDC Endpoint 7 Data Register */
457#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
458/* UDC Endpoint 8 Data Register */
459#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
460/* UDC Endpoint 9 Data Register */
461#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
462/* UDC Endpoint 10 Data Register */
463#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
464/* UDC Endpoint 11 Data Register */
465#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
466/* UDC Endpoint 12 Data Register */
467#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
468/* UDC Endpoint 13 Data Register */
469#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
470/* UDC Endpoint 14 Data Register */
471#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
472/* UDC Endpoint 15 Data Register */
473#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
474/* UDC Interrupt Control Register 0 */
475#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
476/* UDC Interrupt Control Register 1 */
477#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
478/* UDC Status Interrupt Register 0 */
479#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
480/* UDC Status Interrupt Register 1 */
481#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
482
483#define UDCCR_UDE (1 << 0) /* UDC enable */
484#define UDCCR_UDA (1 << 1) /* UDC active */
485#define UDCCR_RSM (1 << 2) /* Device resume */
486#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
487#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
488#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
489#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
490#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
491
492#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
493#define UDCCS0_IPR (1 << 1) /* IN packet ready */
494#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
495#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
496#define UDCCS0_SST (1 << 4) /* Sent stall */
497#define UDCCS0_FST (1 << 5) /* Force stall */
498#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
499#define UDCCS0_SA (1 << 7) /* Setup active */
500
501#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
502#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
503#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
504#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
505#define UDCCS_BI_SST (1 << 4) /* Sent stall */
506#define UDCCS_BI_FST (1 << 5) /* Force stall */
507#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
508
509#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
510#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
511#define UDCCS_BO_DME (1 << 3) /* DMA enable */
512#define UDCCS_BO_SST (1 << 4) /* Sent stall */
513#define UDCCS_BO_FST (1 << 5) /* Force stall */
514#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
515#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
516
517#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
518#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
519#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
520#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
521#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
522
523#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
524#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
525#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
526#define UDCCS_IO_DME (1 << 3) /* DMA enable */
527#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
528#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
529
530#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
531#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
532#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
533#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
534#define UDCCS_INT_SST (1 << 4) /* Sent stall */
535#define UDCCS_INT_FST (1 << 5) /* Force stall */
536#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
537
538#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
539#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
540#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
541#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
542#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
543#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
544#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
545#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
546
547#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
548#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
549#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
550#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
551#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
552#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
553#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
554#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
555
556#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
557#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
558#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
559#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
560#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
561#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
562#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
563#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
564
565#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
566#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
567#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
568#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
569#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
570#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
571#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
572#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
573
574#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
575
576#ifndef __ASSEMBLY__
577static inline int cpu_is_ixp46x(void)
578{
579#ifdef CONFIG_CPU_IXP46X
580 unsigned int processor_id;
581
582 asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
583
584 if ((processor_id & 0xffffff00) == 0x69054200)
585 return 1;
586#endif
587 return 0;
588}
589#endif
590
591#endif
diff --git a/include/asm-arm/arch-ixp4xx/memory.h b/include/asm-arm/arch-ixp4xx/memory.h
new file mode 100644
index 000000000000..d348548b592b
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/memory.h
@@ -0,0 +1,61 @@
1/*
2 * linux/include/asm-arm/arch-ixp4xx/memory.h
3 *
4 * Copyright (c) 2001-2004 MontaVista Software, Inc.
5 */
6
7#ifndef __ASM_ARCH_MEMORY_H
8#define __ASM_ARCH_MEMORY_H
9
10#include <asm/sizes.h>
11
12/*
13 * Physical DRAM offset.
14 */
15#define PHYS_OFFSET (0x00000000UL)
16
17#ifndef __ASSEMBLY__
18
19/*
20 * Only first 64MB of memory can be accessed via PCI.
21 * We use GFP_DMA to allocate safe buffers to do map/unmap.
22 * This is really ugly and we need a better way of specifying
23 * DMA-capable regions of memory.
24 */
25static inline void __arch_adjust_zones(int node, unsigned long *zone_size,
26 unsigned long *zhole_size)
27{
28 unsigned int sz = SZ_64M >> PAGE_SHIFT;
29
30 /*
31 * Only adjust if > 64M on current system
32 */
33 if (node || (zone_size[0] <= sz))
34 return;
35
36 zone_size[1] = zone_size[0] - sz;
37 zone_size[0] = sz;
38 zhole_size[1] = zhole_size[0];
39 zhole_size[0] = 0;
40}
41
42#define arch_adjust_zones(node, size, holes) \
43 __arch_adjust_zones(node, size, holes)
44
45#define ISA_DMA_THRESHOLD (SZ_64M - 1)
46
47#endif
48
49/*
50 * Virtual view <-> DMA view memory address translations
51 * virt_to_bus: Used to translate the virtual address to an
52 * address suitable to be passed to set_dma_addr
53 * bus_to_virt: Used to convert an address for DMA operations
54 * to an address that the kernel can use.
55 *
56 * These are dummies for now.
57 */
58#define __virt_to_bus(x) __virt_to_phys(x)
59#define __bus_to_virt(x) __phys_to_virt(x)
60
61#endif
diff --git a/include/asm-arm/arch-ixp4xx/param.h b/include/asm-arm/arch-ixp4xx/param.h
new file mode 100644
index 000000000000..8a757125e5e7
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/param.h
@@ -0,0 +1,3 @@
1/*
2 * linux/include/asm-arm/arch-ixp4xx/param.h
3 */
diff --git a/include/asm-arm/arch-ixp4xx/platform.h b/include/asm-arm/arch-ixp4xx/platform.h
new file mode 100644
index 000000000000..3a626c03ea26
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/platform.h
@@ -0,0 +1,126 @@
1/*
2 * include/asm-arm/arch-ixp4xx/platform.h
3 *
4 * Constants and functions that are useful to IXP4xx platform-specific code
5 * and device drivers.
6 *
7 * Copyright (C) 2004 MontaVista Software, Inc.
8 */
9
10#ifndef __ASM_ARCH_HARDWARE_H__
11#error "Do not include this directly, instead #include <asm/hardware.h>"
12#endif
13
14#ifndef __ASSEMBLY__
15
16#include <asm/types.h>
17
18#ifndef __ARMEB__
19#define REG_OFFSET 0
20#else
21#define REG_OFFSET 3
22#endif
23
24/*
25 * Expansion bus memory regions
26 */
27#define IXP4XX_EXP_BUS_BASE_PHYS (0x50000000)
28
29#define IXP4XX_EXP_BUS_CSX_REGION_SIZE (0x01000000)
30
31#define IXP4XX_EXP_BUS_CS0_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x00000000)
32#define IXP4XX_EXP_BUS_CS1_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x01000000)
33#define IXP4XX_EXP_BUS_CS2_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x02000000)
34#define IXP4XX_EXP_BUS_CS3_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x03000000)
35#define IXP4XX_EXP_BUS_CS4_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x04000000)
36#define IXP4XX_EXP_BUS_CS5_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x05000000)
37#define IXP4XX_EXP_BUS_CS6_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x06000000)
38#define IXP4XX_EXP_BUS_CS7_BASE_PHYS (IXP4XX_EXP_BUS_BASE_PHYS + 0x07000000)
39
40#define IXP4XX_FLASH_WRITABLE (0x2)
41#define IXP4XX_FLASH_DEFAULT (0xbcd23c40)
42#define IXP4XX_FLASH_WRITE (0xbcd23c42)
43
44/*
45 * Clock Speed Definitions.
46 */
47#define IXP4XX_PERIPHERAL_BUS_CLOCK (66) /* 66Mhzi APB BUS */
48#define IXP4XX_UART_XTAL 14745600
49
50/*
51 * The IXP4xx chips do not have an I2C unit, so GPIO lines are just
52 * used to
53 * Used as platform_data to provide GPIO pin information to the ixp42x
54 * I2C driver.
55 */
56struct ixp4xx_i2c_pins {
57 unsigned long sda_pin;
58 unsigned long scl_pin;
59};
60
61
62struct sys_timer;
63
64/*
65 * Functions used by platform-level setup code
66 */
67extern void ixp4xx_map_io(void);
68extern void ixp4xx_init_irq(void);
69extern void ixp4xx_sys_init(void);
70extern struct sys_timer ixp4xx_timer;
71extern void ixp4xx_pci_preinit(void);
72struct pci_sys_data;
73extern int ixp4xx_setup(int nr, struct pci_sys_data *sys);
74extern struct pci_bus *ixp4xx_scan_bus(int nr, struct pci_sys_data *sys);
75
76/*
77 * GPIO-functions
78 */
79/*
80 * The following converted to the real HW bits the gpio_line_config
81 */
82/* GPIO pin types */
83#define IXP4XX_GPIO_OUT 0x1
84#define IXP4XX_GPIO_IN 0x2
85
86#define IXP4XX_GPIO_INTSTYLE_MASK 0x7C /* Bits [6:2] define interrupt style */
87
88/*
89 * GPIO interrupt types.
90 */
91#define IXP4XX_GPIO_ACTIVE_HIGH 0x4 /* Default */
92#define IXP4XX_GPIO_ACTIVE_LOW 0x8
93#define IXP4XX_GPIO_RISING_EDGE 0x10
94#define IXP4XX_GPIO_FALLING_EDGE 0x20
95#define IXP4XX_GPIO_TRANSITIONAL 0x40
96
97/* GPIO signal types */
98#define IXP4XX_GPIO_LOW 0
99#define IXP4XX_GPIO_HIGH 1
100
101/* GPIO Clocks */
102#define IXP4XX_GPIO_CLK_0 14
103#define IXP4XX_GPIO_CLK_1 15
104
105extern void gpio_line_config(u8 line, u32 style);
106
107static inline void gpio_line_get(u8 line, int *value)
108{
109 *value = (*IXP4XX_GPIO_GPINR >> line) & 0x1;
110}
111
112static inline void gpio_line_set(u8 line, int value)
113{
114 if (value == IXP4XX_GPIO_HIGH)
115 *IXP4XX_GPIO_GPOUTR |= (1 << line);
116 else if (value == IXP4XX_GPIO_LOW)
117 *IXP4XX_GPIO_GPOUTR &= ~(1 << line);
118}
119
120static inline void gpio_line_isr_clear(u8 line)
121{
122 *IXP4XX_GPIO_GPISR = (1 << line);
123}
124
125#endif // __ASSEMBLY__
126
diff --git a/include/asm-arm/arch-ixp4xx/prpmc1100.h b/include/asm-arm/arch-ixp4xx/prpmc1100.h
new file mode 100644
index 000000000000..e2532ab7f48f
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/prpmc1100.h
@@ -0,0 +1,33 @@
1/*
2 * include/asm-arm/arch-ixp4xx/prpmc1100.h
3 *
4 * Motorolla PrPMC1100 platform specific definitions
5 *
6 * Author: Deepak Saxena <dsaxena@plexity.net>
7 *
8 * Copyright 2004 (c) MontaVista, Software, Inc.
9 *
10 * This file is licensed under the terms of the GNU General Public
11 * License version 2. This program is licensed "as is" without any
12 * warranty of any kind, whether express or implied.
13 */
14
15#ifndef __ASM_ARCH_HARDWARE_H__
16#error "Do not include this directly, instead #include <asm/hardware.h>"
17#endif
18
19#define PRPMC1100_FLASH_BASE IXP4XX_EXP_BUS_CS0_BASE_PHYS
20#define PRPMC1100_FLASH_SIZE IXP4XX_EXP_BUS_CSX_REGION_SIZE
21
22#define PRPMC1100_PCI_MIN_DEVID 10
23#define PRPMC1100_PCI_MAX_DEVID 16
24#define PRPMC1100_PCI_IRQ_LINES 4
25
26
27/* PCI controller GPIO to IRQ pin mappings */
28#define PRPMC1100_PCI_INTA_PIN 11
29#define PRPMC1100_PCI_INTB_PIN 10
30#define PRPMC1100_PCI_INTC_PIN 9
31#define PRPMC1100_PCI_INTD_PIN 8
32
33
diff --git a/include/asm-arm/arch-ixp4xx/system.h b/include/asm-arm/arch-ixp4xx/system.h
new file mode 100644
index 000000000000..73589aad8dd6
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/system.h
@@ -0,0 +1,42 @@
1/*
2 * include/asm-arm/arch-ixp4x//system.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12#include <asm/hardware.h>
13
14static inline void arch_idle(void)
15{
16#if 0
17 if (!hlt_counter)
18 cpu_do_idle(0);
19#endif
20}
21
22
23static inline void arch_reset(char mode)
24{
25 if ( 1 && mode == 's') {
26 /* Jump into ROM at address 0 */
27 cpu_reset(0);
28 } else {
29 /* Use on-chip reset capability */
30
31 /* set the "key" register to enable access to
32 * "timer" and "enable" registers
33 */
34 *IXP4XX_OSWK = IXP4XX_WDT_KEY;
35
36 /* write 0 to the timer register for an immediate reset */
37 *IXP4XX_OSWT = 0;
38
39 *IXP4XX_OSWE = IXP4XX_WDT_RESET_ENABLE | IXP4XX_WDT_COUNT_ENABLE;
40 }
41}
42
diff --git a/include/asm-arm/arch-ixp4xx/timex.h b/include/asm-arm/arch-ixp4xx/timex.h
new file mode 100644
index 000000000000..38c9d77d3727
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/timex.h
@@ -0,0 +1,13 @@
1/*
2 * linux/include/asm-arm/arch-ixp4xx/timex.h
3 *
4 */
5
6#include <asm/hardware.h>
7
8/*
9 * We use IXP425 General purpose timer for our timer needs, it runs at
10 * 66.66... MHz
11 */
12#define CLOCK_TICK_RATE (66666666)
13
diff --git a/include/asm-arm/arch-ixp4xx/uncompress.h b/include/asm-arm/arch-ixp4xx/uncompress.h
new file mode 100644
index 000000000000..960c35810a22
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/uncompress.h
@@ -0,0 +1,64 @@
1/*
2 * include/asm-arm/arch-ixp4xx/uncompress.h
3 *
4 * Copyright (C) 2002 Intel Corporation.
5 * Copyright (C) 2003-2004 MontaVista Software, Inc.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12
13#ifndef _ARCH_UNCOMPRESS_H_
14#define _ARCH_UNCOMPRESS_H_
15
16#include <asm/hardware.h>
17#include <asm/mach-types.h>
18#include <linux/serial_reg.h>
19
20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
21
22static volatile u32* uart_base;
23
24static __inline__ void putc(char c)
25{
26 /* Check THRE and TEMT bits before we transmit the character.
27 */
28 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE);
29 *uart_base = c;
30}
31
32/*
33 * This does not append a newline
34 */
35static void putstr(const char *s)
36{
37 while (*s)
38 {
39 putc(*s);
40 if (*s == '\n')
41 putc('\r');
42 s++;
43 }
44}
45
46static __inline__ void __arch_decomp_setup(unsigned long arch_id)
47{
48 /*
49 * Coyote and gtwx5715 only have UART2 connected
50 */
51 if (machine_is_adi_coyote() || machine_is_gtwx5715())
52 uart_base = (volatile u32*) IXP4XX_UART2_BASE_PHYS;
53 else
54 uart_base = (volatile u32*) IXP4XX_UART1_BASE_PHYS;
55}
56
57/*
58 * arch_id is a variable in decompress_kernel()
59 */
60#define arch_decomp_setup() __arch_decomp_setup(arch_id)
61
62#define arch_decomp_wdog()
63
64#endif
diff --git a/include/asm-arm/arch-ixp4xx/vmalloc.h b/include/asm-arm/arch-ixp4xx/vmalloc.h
new file mode 100644
index 000000000000..da46e560ad6f
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/vmalloc.h
@@ -0,0 +1,17 @@
1/*
2 * linux/include/asm-arm/arch-ixp4xx/vmalloc.h
3 */
4
5/*
6 * Just any arbitrary offset to the start of the vmalloc VM area: the
7 * current 8MB value just means that there will be a 8MB "hole" after the
8 * physical memory until the kernel virtual memory starts. That means that
9 * any out-of-bounds memory accesses will hopefully be caught.
10 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
11 * area for the same reason. ;)
12 */
13#define VMALLOC_OFFSET (8*1024*1024)
14#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
15#define VMALLOC_VMADDR(x) ((unsigned long)(x))
16#define VMALLOC_END (0xFF000000)
17
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