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Diffstat (limited to 'include/asm-arm/arch-ixp4xx/ixp4xx-regs.h')
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diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
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index 000000000000..8eeb1db6309d
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1/*
2 * include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
3 *
4 * Register definitions for IXP4xx chipset. This file contains
5 * register location and bit definitions only. Platform specific
6 * definitions and helper function declarations are in platform.h
7 * and machine-name.h.
8 *
9 * Copyright (C) 2002 Intel Corporation.
10 * Copyright (C) 2003-2004 MontaVista Software, Inc.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 *
16 */
17
18#ifndef __ASM_ARCH_HARDWARE_H__
19#error "Do not include this directly, instead #include <asm/hardware.h>"
20#endif
21
22#ifndef _ASM_ARM_IXP4XX_H_
23#define _ASM_ARM_IXP4XX_H_
24
25/*
26 * IXP4xx Linux Memory Map:
27 *
28 * Phy Size Virt Description
29 * =========================================================================
30 *
31 * 0x00000000 0x10000000(max) PAGE_OFFSET System RAM
32 *
33 * 0x48000000 0x04000000 ioremap'd PCI Memory Space
34 *
35 * 0x50000000 0x10000000 ioremap'd EXP BUS
36 *
37 * 0x6000000 0x00004000 ioremap'd QMgr
38 *
39 * 0xC0000000 0x00001000 0xffbfe000 PCI CFG
40 *
41 * 0xC4000000 0x00001000 0xffbfd000 EXP CFG
42 *
43 * 0xC8000000 0x0000C000 0xffbf2000 On-Chip Peripherals
44 */
45
46/*
47 * Queue Manager
48 */
49#define IXP4XX_QMGR_BASE_PHYS (0x60000000)
50
51/*
52 * Expansion BUS Configuration registers
53 */
54#define IXP4XX_EXP_CFG_BASE_PHYS (0xC4000000)
55#define IXP4XX_EXP_CFG_BASE_VIRT (0xFFBFD000)
56#define IXP4XX_EXP_CFG_REGION_SIZE (0x00001000)
57
58/*
59 * PCI Config registers
60 */
61#define IXP4XX_PCI_CFG_BASE_PHYS (0xC0000000)
62#define IXP4XX_PCI_CFG_BASE_VIRT (0xFFBFE000)
63#define IXP4XX_PCI_CFG_REGION_SIZE (0x00001000)
64
65/*
66 * Peripheral space
67 */
68#define IXP4XX_PERIPHERAL_BASE_PHYS (0xC8000000)
69#define IXP4XX_PERIPHERAL_BASE_VIRT (0xFFBF2000)
70#define IXP4XX_PERIPHERAL_REGION_SIZE (0x0000C000)
71
72#define IXP4XX_EXP_CS0_OFFSET 0x00
73#define IXP4XX_EXP_CS1_OFFSET 0x04
74#define IXP4XX_EXP_CS2_OFFSET 0x08
75#define IXP4XX_EXP_CS3_OFFSET 0x0C
76#define IXP4XX_EXP_CS4_OFFSET 0x10
77#define IXP4XX_EXP_CS5_OFFSET 0x14
78#define IXP4XX_EXP_CS6_OFFSET 0x18
79#define IXP4XX_EXP_CS7_OFFSET 0x1C
80#define IXP4XX_EXP_CFG0_OFFSET 0x20
81#define IXP4XX_EXP_CFG1_OFFSET 0x24
82#define IXP4XX_EXP_CFG2_OFFSET 0x28
83#define IXP4XX_EXP_CFG3_OFFSET 0x2C
84
85/*
86 * Expansion Bus Controller registers.
87 */
88#define IXP4XX_EXP_REG(x) ((volatile u32 *)(IXP4XX_EXP_CFG_BASE_VIRT+(x)))
89
90#define IXP4XX_EXP_CS0 IXP4XX_EXP_REG(IXP4XX_EXP_CS0_OFFSET)
91#define IXP4XX_EXP_CS1 IXP4XX_EXP_REG(IXP4XX_EXP_CS1_OFFSET)
92#define IXP4XX_EXP_CS2 IXP4XX_EXP_REG(IXP4XX_EXP_CS2_OFFSET)
93#define IXP4XX_EXP_CS3 IXP4XX_EXP_REG(IXP4XX_EXP_CS3_OFFSET)
94#define IXP4XX_EXP_CS4 IXP4XX_EXP_REG(IXP4XX_EXP_CS4_OFFSET)
95#define IXP4XX_EXP_CS5 IXP4XX_EXP_REG(IXP4XX_EXP_CS5_OFFSET)
96#define IXP4XX_EXP_CS6 IXP4XX_EXP_REG(IXP4XX_EXP_CS6_OFFSET)
97#define IXP4XX_EXP_CS7 IXP4XX_EXP_REG(IXP4XX_EXP_CS7_OFFSET)
98
99#define IXP4XX_EXP_CFG0 IXP4XX_EXP_REG(IXP4XX_EXP_CFG0_OFFSET)
100#define IXP4XX_EXP_CFG1 IXP4XX_EXP_REG(IXP4XX_EXP_CFG1_OFFSET)
101#define IXP4XX_EXP_CFG2 IXP4XX_EXP_REG(IXP4XX_EXP_CFG2_OFFSET)
102#define IXP4XX_EXP_CFG3 IXP4XX_EXP_REG(IXP4XX_EXP_CFG3_OFFSET)
103
104
105/*
106 * Peripheral Space Register Region Base Addresses
107 */
108#define IXP4XX_UART1_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x0000)
109#define IXP4XX_UART2_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x1000)
110#define IXP4XX_PMU_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x2000)
111#define IXP4XX_INTC_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x3000)
112#define IXP4XX_GPIO_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x4000)
113#define IXP4XX_TIMER_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x5000)
114#define IXP4XX_EthA_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0x9000)
115#define IXP4XX_EthB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xA000)
116#define IXP4XX_USB_BASE_PHYS (IXP4XX_PERIPHERAL_BASE_PHYS + 0xB000)
117
118#define IXP4XX_UART1_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x0000)
119#define IXP4XX_UART2_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x1000)
120#define IXP4XX_PMU_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x2000)
121#define IXP4XX_INTC_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x3000)
122#define IXP4XX_GPIO_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x4000)
123#define IXP4XX_TIMER_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x5000)
124#define IXP4XX_EthA_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0x9000)
125#define IXP4XX_EthB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xA000)
126#define IXP4XX_USB_BASE_VIRT (IXP4XX_PERIPHERAL_BASE_VIRT + 0xB000)
127
128/*
129 * Constants to make it easy to access Interrupt Controller registers
130 */
131#define IXP4XX_ICPR_OFFSET 0x00 /* Interrupt Status */
132#define IXP4XX_ICMR_OFFSET 0x04 /* Interrupt Enable */
133#define IXP4XX_ICLR_OFFSET 0x08 /* Interrupt IRQ/FIQ Select */
134#define IXP4XX_ICIP_OFFSET 0x0C /* IRQ Status */
135#define IXP4XX_ICFP_OFFSET 0x10 /* FIQ Status */
136#define IXP4XX_ICHR_OFFSET 0x14 /* Interrupt Priority */
137#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
138#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
139
140/*
141 * IXP465-only
142 */
143#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */
144#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */
145#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */
146#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */
147#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */
148#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */
149
150
151/*
152 * Interrupt Controller Register Definitions.
153 */
154
155#define IXP4XX_INTC_REG(x) ((volatile u32 *)(IXP4XX_INTC_BASE_VIRT+(x)))
156
157#define IXP4XX_ICPR IXP4XX_INTC_REG(IXP4XX_ICPR_OFFSET)
158#define IXP4XX_ICMR IXP4XX_INTC_REG(IXP4XX_ICMR_OFFSET)
159#define IXP4XX_ICLR IXP4XX_INTC_REG(IXP4XX_ICLR_OFFSET)
160#define IXP4XX_ICIP IXP4XX_INTC_REG(IXP4XX_ICIP_OFFSET)
161#define IXP4XX_ICFP IXP4XX_INTC_REG(IXP4XX_ICFP_OFFSET)
162#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
163#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
164#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
165#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
166#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
167#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
168#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
169#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
170#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
171
172/*
173 * Constants to make it easy to access GPIO registers
174 */
175#define IXP4XX_GPIO_GPOUTR_OFFSET 0x00
176#define IXP4XX_GPIO_GPOER_OFFSET 0x04
177#define IXP4XX_GPIO_GPINR_OFFSET 0x08
178#define IXP4XX_GPIO_GPISR_OFFSET 0x0C
179#define IXP4XX_GPIO_GPIT1R_OFFSET 0x10
180#define IXP4XX_GPIO_GPIT2R_OFFSET 0x14
181#define IXP4XX_GPIO_GPCLKR_OFFSET 0x18
182#define IXP4XX_GPIO_GPDBSELR_OFFSET 0x1C
183
184/*
185 * GPIO Register Definitions.
186 * [Only perform 32bit reads/writes]
187 */
188#define IXP4XX_GPIO_REG(x) ((volatile u32 *)(IXP4XX_GPIO_BASE_VIRT+(x)))
189
190#define IXP4XX_GPIO_GPOUTR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOUTR_OFFSET)
191#define IXP4XX_GPIO_GPOER IXP4XX_GPIO_REG(IXP4XX_GPIO_GPOER_OFFSET)
192#define IXP4XX_GPIO_GPINR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPINR_OFFSET)
193#define IXP4XX_GPIO_GPISR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPISR_OFFSET)
194#define IXP4XX_GPIO_GPIT1R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT1R_OFFSET)
195#define IXP4XX_GPIO_GPIT2R IXP4XX_GPIO_REG(IXP4XX_GPIO_GPIT2R_OFFSET)
196#define IXP4XX_GPIO_GPCLKR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPCLKR_OFFSET)
197#define IXP4XX_GPIO_GPDBSELR IXP4XX_GPIO_REG(IXP4XX_GPIO_GPDBSELR_OFFSET)
198
199/*
200 * GPIO register bit definitions
201 */
202
203/* Interrupt styles
204 */
205#define IXP4XX_GPIO_STYLE_ACTIVE_HIGH 0x0
206#define IXP4XX_GPIO_STYLE_ACTIVE_LOW 0x1
207#define IXP4XX_GPIO_STYLE_RISING_EDGE 0x2
208#define IXP4XX_GPIO_STYLE_FALLING_EDGE 0x3
209#define IXP4XX_GPIO_STYLE_TRANSITIONAL 0x4
210
211/*
212 * Mask used to clear interrupt styles
213 */
214#define IXP4XX_GPIO_STYLE_CLEAR 0x7
215#define IXP4XX_GPIO_STYLE_SIZE 3
216
217/*
218 * Constants to make it easy to access Timer Control/Status registers
219 */
220#define IXP4XX_OSTS_OFFSET 0x00 /* Continious TimeStamp */
221#define IXP4XX_OST1_OFFSET 0x04 /* Timer 1 Timestamp */
222#define IXP4XX_OSRT1_OFFSET 0x08 /* Timer 1 Reload */
223#define IXP4XX_OST2_OFFSET 0x0C /* Timer 2 Timestamp */
224#define IXP4XX_OSRT2_OFFSET 0x10 /* Timer 2 Reload */
225#define IXP4XX_OSWT_OFFSET 0x14 /* Watchdog Timer */
226#define IXP4XX_OSWE_OFFSET 0x18 /* Watchdog Enable */
227#define IXP4XX_OSWK_OFFSET 0x1C /* Watchdog Key */
228#define IXP4XX_OSST_OFFSET 0x20 /* Timer Status */
229
230/*
231 * Operating System Timer Register Definitions.
232 */
233
234#define IXP4XX_TIMER_REG(x) ((volatile u32 *)(IXP4XX_TIMER_BASE_VIRT+(x)))
235
236#define IXP4XX_OSTS IXP4XX_TIMER_REG(IXP4XX_OSTS_OFFSET)
237#define IXP4XX_OST1 IXP4XX_TIMER_REG(IXP4XX_OST1_OFFSET)
238#define IXP4XX_OSRT1 IXP4XX_TIMER_REG(IXP4XX_OSRT1_OFFSET)
239#define IXP4XX_OST2 IXP4XX_TIMER_REG(IXP4XX_OST2_OFFSET)
240#define IXP4XX_OSRT2 IXP4XX_TIMER_REG(IXP4XX_OSRT2_OFFSET)
241#define IXP4XX_OSWT IXP4XX_TIMER_REG(IXP4XX_OSWT_OFFSET)
242#define IXP4XX_OSWE IXP4XX_TIMER_REG(IXP4XX_OSWE_OFFSET)
243#define IXP4XX_OSWK IXP4XX_TIMER_REG(IXP4XX_OSWK_OFFSET)
244#define IXP4XX_OSST IXP4XX_TIMER_REG(IXP4XX_OSST_OFFSET)
245
246/*
247 * Timer register values and bit definitions
248 */
249#define IXP4XX_OST_ENABLE 0x00000001
250#define IXP4XX_OST_ONE_SHOT 0x00000002
251/* Low order bits of reload value ignored */
252#define IXP4XX_OST_RELOAD_MASK 0x00000003
253#define IXP4XX_OST_DISABLED 0x00000000
254#define IXP4XX_OSST_TIMER_1_PEND 0x00000001
255#define IXP4XX_OSST_TIMER_2_PEND 0x00000002
256#define IXP4XX_OSST_TIMER_TS_PEND 0x00000004
257#define IXP4XX_OSST_TIMER_WDOG_PEND 0x00000008
258#define IXP4XX_OSST_TIMER_WARM_RESET 0x00000010
259
260#define IXP4XX_WDT_KEY 0x0000482E
261
262#define IXP4XX_WDT_RESET_ENABLE 0x00000001
263#define IXP4XX_WDT_IRQ_ENABLE 0x00000002
264#define IXP4XX_WDT_COUNT_ENABLE 0x00000004
265
266
267/*
268 * Constants to make it easy to access PCI Control/Status registers
269 */
270#define PCI_NP_AD_OFFSET 0x00
271#define PCI_NP_CBE_OFFSET 0x04
272#define PCI_NP_WDATA_OFFSET 0x08
273#define PCI_NP_RDATA_OFFSET 0x0c
274#define PCI_CRP_AD_CBE_OFFSET 0x10
275#define PCI_CRP_WDATA_OFFSET 0x14
276#define PCI_CRP_RDATA_OFFSET 0x18
277#define PCI_CSR_OFFSET 0x1c
278#define PCI_ISR_OFFSET 0x20
279#define PCI_INTEN_OFFSET 0x24
280#define PCI_DMACTRL_OFFSET 0x28
281#define PCI_AHBMEMBASE_OFFSET 0x2c
282#define PCI_AHBIOBASE_OFFSET 0x30
283#define PCI_PCIMEMBASE_OFFSET 0x34
284#define PCI_AHBDOORBELL_OFFSET 0x38
285#define PCI_PCIDOORBELL_OFFSET 0x3C
286#define PCI_ATPDMA0_AHBADDR_OFFSET 0x40
287#define PCI_ATPDMA0_PCIADDR_OFFSET 0x44
288#define PCI_ATPDMA0_LENADDR_OFFSET 0x48
289#define PCI_ATPDMA1_AHBADDR_OFFSET 0x4C
290#define PCI_ATPDMA1_PCIADDR_OFFSET 0x50
291#define PCI_ATPDMA1_LENADDR_OFFSET 0x54
292
293/*
294 * PCI Control/Status Registers
295 */
296#define IXP4XX_PCI_CSR(x) ((volatile u32 *)(IXP4XX_PCI_CFG_BASE_VIRT+(x)))
297
298#define PCI_NP_AD IXP4XX_PCI_CSR(PCI_NP_AD_OFFSET)
299#define PCI_NP_CBE IXP4XX_PCI_CSR(PCI_NP_CBE_OFFSET)
300#define PCI_NP_WDATA IXP4XX_PCI_CSR(PCI_NP_WDATA_OFFSET)
301#define PCI_NP_RDATA IXP4XX_PCI_CSR(PCI_NP_RDATA_OFFSET)
302#define PCI_CRP_AD_CBE IXP4XX_PCI_CSR(PCI_CRP_AD_CBE_OFFSET)
303#define PCI_CRP_WDATA IXP4XX_PCI_CSR(PCI_CRP_WDATA_OFFSET)
304#define PCI_CRP_RDATA IXP4XX_PCI_CSR(PCI_CRP_RDATA_OFFSET)
305#define PCI_CSR IXP4XX_PCI_CSR(PCI_CSR_OFFSET)
306#define PCI_ISR IXP4XX_PCI_CSR(PCI_ISR_OFFSET)
307#define PCI_INTEN IXP4XX_PCI_CSR(PCI_INTEN_OFFSET)
308#define PCI_DMACTRL IXP4XX_PCI_CSR(PCI_DMACTRL_OFFSET)
309#define PCI_AHBMEMBASE IXP4XX_PCI_CSR(PCI_AHBMEMBASE_OFFSET)
310#define PCI_AHBIOBASE IXP4XX_PCI_CSR(PCI_AHBIOBASE_OFFSET)
311#define PCI_PCIMEMBASE IXP4XX_PCI_CSR(PCI_PCIMEMBASE_OFFSET)
312#define PCI_AHBDOORBELL IXP4XX_PCI_CSR(PCI_AHBDOORBELL_OFFSET)
313#define PCI_PCIDOORBELL IXP4XX_PCI_CSR(PCI_PCIDOORBELL_OFFSET)
314#define PCI_ATPDMA0_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_AHBADDR_OFFSET)
315#define PCI_ATPDMA0_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_PCIADDR_OFFSET)
316#define PCI_ATPDMA0_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA0_LENADDR_OFFSET)
317#define PCI_ATPDMA1_AHBADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_AHBADDR_OFFSET)
318#define PCI_ATPDMA1_PCIADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_PCIADDR_OFFSET)
319#define PCI_ATPDMA1_LENADDR IXP4XX_PCI_CSR(PCI_ATPDMA1_LENADDR_OFFSET)
320
321/*
322 * PCI register values and bit definitions
323 */
324
325/* CSR bit definitions */
326#define PCI_CSR_HOST 0x00000001
327#define PCI_CSR_ARBEN 0x00000002
328#define PCI_CSR_ADS 0x00000004
329#define PCI_CSR_PDS 0x00000008
330#define PCI_CSR_ABE 0x00000010
331#define PCI_CSR_DBT 0x00000020
332#define PCI_CSR_ASE 0x00000100
333#define PCI_CSR_IC 0x00008000
334
335/* ISR (Interrupt status) Register bit definitions */
336#define PCI_ISR_PSE 0x00000001
337#define PCI_ISR_PFE 0x00000002
338#define PCI_ISR_PPE 0x00000004
339#define PCI_ISR_AHBE 0x00000008
340#define PCI_ISR_APDC 0x00000010
341#define PCI_ISR_PADC 0x00000020
342#define PCI_ISR_ADB 0x00000040
343#define PCI_ISR_PDB 0x00000080
344
345/* INTEN (Interrupt Enable) Register bit definitions */
346#define PCI_INTEN_PSE 0x00000001
347#define PCI_INTEN_PFE 0x00000002
348#define PCI_INTEN_PPE 0x00000004
349#define PCI_INTEN_AHBE 0x00000008
350#define PCI_INTEN_APDC 0x00000010
351#define PCI_INTEN_PADC 0x00000020
352#define PCI_INTEN_ADB 0x00000040
353#define PCI_INTEN_PDB 0x00000080
354
355/*
356 * Shift value for byte enable on NP cmd/byte enable register
357 */
358#define IXP4XX_PCI_NP_CBE_BESL 4
359
360/*
361 * PCI commands supported by NP access unit
362 */
363#define NP_CMD_IOREAD 0x2
364#define NP_CMD_IOWRITE 0x3
365#define NP_CMD_CONFIGREAD 0xa
366#define NP_CMD_CONFIGWRITE 0xb
367#define NP_CMD_MEMREAD 0x6
368#define NP_CMD_MEMWRITE 0x7
369
370/*
371 * Constants for CRP access into local config space
372 */
373#define CRP_AD_CBE_BESL 20
374#define CRP_AD_CBE_WRITE 0x00010000
375
376
377/*
378 * USB Device Controller
379 *
380 * These are used by the USB gadget driver, so they don't follow the
381 * IXP4XX_ naming convetions.
382 *
383 */
384# define IXP4XX_USB_REG(x) (*((volatile u32 *)(x)))
385
386/* UDC Undocumented - Reserved1 */
387#define UDC_RES1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0004)
388/* UDC Undocumented - Reserved2 */
389#define UDC_RES2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0008)
390/* UDC Undocumented - Reserved3 */
391#define UDC_RES3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x000C)
392/* UDC Control Register */
393#define UDCCR IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0000)
394/* UDC Endpoint 0 Control/Status Register */
395#define UDCCS0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0010)
396/* UDC Endpoint 1 (IN) Control/Status Register */
397#define UDCCS1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0014)
398/* UDC Endpoint 2 (OUT) Control/Status Register */
399#define UDCCS2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0018)
400/* UDC Endpoint 3 (IN) Control/Status Register */
401#define UDCCS3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x001C)
402/* UDC Endpoint 4 (OUT) Control/Status Register */
403#define UDCCS4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0020)
404/* UDC Endpoint 5 (Interrupt) Control/Status Register */
405#define UDCCS5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0024)
406/* UDC Endpoint 6 (IN) Control/Status Register */
407#define UDCCS6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0028)
408/* UDC Endpoint 7 (OUT) Control/Status Register */
409#define UDCCS7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x002C)
410/* UDC Endpoint 8 (IN) Control/Status Register */
411#define UDCCS8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0030)
412/* UDC Endpoint 9 (OUT) Control/Status Register */
413#define UDCCS9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0034)
414/* UDC Endpoint 10 (Interrupt) Control/Status Register */
415#define UDCCS10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0038)
416/* UDC Endpoint 11 (IN) Control/Status Register */
417#define UDCCS11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x003C)
418/* UDC Endpoint 12 (OUT) Control/Status Register */
419#define UDCCS12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0040)
420/* UDC Endpoint 13 (IN) Control/Status Register */
421#define UDCCS13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0044)
422/* UDC Endpoint 14 (OUT) Control/Status Register */
423#define UDCCS14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0048)
424/* UDC Endpoint 15 (Interrupt) Control/Status Register */
425#define UDCCS15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x004C)
426/* UDC Frame Number Register High */
427#define UFNRH IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0060)
428/* UDC Frame Number Register Low */
429#define UFNRL IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0064)
430/* UDC Byte Count Reg 2 */
431#define UBCR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0068)
432/* UDC Byte Count Reg 4 */
433#define UBCR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x006c)
434/* UDC Byte Count Reg 7 */
435#define UBCR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0070)
436/* UDC Byte Count Reg 9 */
437#define UBCR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0074)
438/* UDC Byte Count Reg 12 */
439#define UBCR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0078)
440/* UDC Byte Count Reg 14 */
441#define UBCR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x007c)
442/* UDC Endpoint 0 Data Register */
443#define UDDR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0080)
444/* UDC Endpoint 1 Data Register */
445#define UDDR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0100)
446/* UDC Endpoint 2 Data Register */
447#define UDDR2 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0180)
448/* UDC Endpoint 3 Data Register */
449#define UDDR3 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0200)
450/* UDC Endpoint 4 Data Register */
451#define UDDR4 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0400)
452/* UDC Endpoint 5 Data Register */
453#define UDDR5 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00A0)
454/* UDC Endpoint 6 Data Register */
455#define UDDR6 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0600)
456/* UDC Endpoint 7 Data Register */
457#define UDDR7 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0680)
458/* UDC Endpoint 8 Data Register */
459#define UDDR8 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0700)
460/* UDC Endpoint 9 Data Register */
461#define UDDR9 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0900)
462/* UDC Endpoint 10 Data Register */
463#define UDDR10 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00C0)
464/* UDC Endpoint 11 Data Register */
465#define UDDR11 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B00)
466/* UDC Endpoint 12 Data Register */
467#define UDDR12 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0B80)
468/* UDC Endpoint 13 Data Register */
469#define UDDR13 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0C00)
470/* UDC Endpoint 14 Data Register */
471#define UDDR14 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0E00)
472/* UDC Endpoint 15 Data Register */
473#define UDDR15 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x00E0)
474/* UDC Interrupt Control Register 0 */
475#define UICR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0050)
476/* UDC Interrupt Control Register 1 */
477#define UICR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0054)
478/* UDC Status Interrupt Register 0 */
479#define USIR0 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x0058)
480/* UDC Status Interrupt Register 1 */
481#define USIR1 IXP4XX_USB_REG(IXP4XX_USB_BASE_VIRT+0x005C)
482
483#define UDCCR_UDE (1 << 0) /* UDC enable */
484#define UDCCR_UDA (1 << 1) /* UDC active */
485#define UDCCR_RSM (1 << 2) /* Device resume */
486#define UDCCR_RESIR (1 << 3) /* Resume interrupt request */
487#define UDCCR_SUSIR (1 << 4) /* Suspend interrupt request */
488#define UDCCR_SRM (1 << 5) /* Suspend/resume interrupt mask */
489#define UDCCR_RSTIR (1 << 6) /* Reset interrupt request */
490#define UDCCR_REM (1 << 7) /* Reset interrupt mask */
491
492#define UDCCS0_OPR (1 << 0) /* OUT packet ready */
493#define UDCCS0_IPR (1 << 1) /* IN packet ready */
494#define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
495#define UDCCS0_DRWF (1 << 3) /* Device remote wakeup feature */
496#define UDCCS0_SST (1 << 4) /* Sent stall */
497#define UDCCS0_FST (1 << 5) /* Force stall */
498#define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
499#define UDCCS0_SA (1 << 7) /* Setup active */
500
501#define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
502#define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
503#define UDCCS_BI_FTF (1 << 2) /* Flush Tx FIFO */
504#define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
505#define UDCCS_BI_SST (1 << 4) /* Sent stall */
506#define UDCCS_BI_FST (1 << 5) /* Force stall */
507#define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
508
509#define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
510#define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
511#define UDCCS_BO_DME (1 << 3) /* DMA enable */
512#define UDCCS_BO_SST (1 << 4) /* Sent stall */
513#define UDCCS_BO_FST (1 << 5) /* Force stall */
514#define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
515#define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
516
517#define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
518#define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
519#define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
520#define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
521#define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
522
523#define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
524#define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
525#define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
526#define UDCCS_IO_DME (1 << 3) /* DMA enable */
527#define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
528#define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
529
530#define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
531#define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
532#define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
533#define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
534#define UDCCS_INT_SST (1 << 4) /* Sent stall */
535#define UDCCS_INT_FST (1 << 5) /* Force stall */
536#define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
537
538#define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
539#define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
540#define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
541#define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
542#define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
543#define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
544#define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
545#define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
546
547#define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
548#define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
549#define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
550#define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
551#define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
552#define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
553#define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
554#define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
555
556#define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
557#define USIR0_IR1 (1 << 1) /* Interrup request ep 1 */
558#define USIR0_IR2 (1 << 2) /* Interrup request ep 2 */
559#define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
560#define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
561#define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
562#define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
563#define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
564
565#define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
566#define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
567#define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
568#define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
569#define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
570#define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
571#define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
572#define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
573
574#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
575
576#ifndef __ASSEMBLY__
577static inline int cpu_is_ixp46x(void)
578{
579#ifdef CONFIG_CPU_IXP46X
580 unsigned int processor_id;
581
582 asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
583
584 if ((processor_id & 0xffffff00) == 0x69054200)
585 return 1;
586#endif
587 return 0;
588}
589#endif
590
591#endif