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Diffstat (limited to 'include/asm-arm/arch-ixp2000/ixp2000-regs.h')
-rw-r--r--include/asm-arm/arch-ixp2000/ixp2000-regs.h22
1 files changed, 21 insertions, 1 deletions
diff --git a/include/asm-arm/arch-ixp2000/ixp2000-regs.h b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
index 6c56708d0ff0..75623f81ef75 100644
--- a/include/asm-arm/arch-ixp2000/ixp2000-regs.h
+++ b/include/asm-arm/arch-ixp2000/ixp2000-regs.h
@@ -18,6 +18,21 @@
18#ifndef _IXP2000_REGS_H_ 18#ifndef _IXP2000_REGS_H_
19#define _IXP2000_REGS_H_ 19#define _IXP2000_REGS_H_
20 20
21/*
22 * IXP2000 linux memory map:
23 *
24 * virt phys size
25 * fb000000 db000000 16M PCI CFG1
26 * fc000000 da000000 16M PCI CFG0
27 * fd000000 d8000000 16M PCI I/O
28 * fe[0-7]00000 8M per-platform mappings
29 * feb00000 c8000000 1M MSF
30 * fec00000 df000000 1M PCI CSRs
31 * fed00000 de000000 1M PCI CREG
32 * fee00000 d6000000 1M INTCTL
33 * fef00000 c0000000 1M CAP
34 */
35
21/* 36/*
22 * Static I/O regions. 37 * Static I/O regions.
23 * 38 *
@@ -71,6 +86,10 @@
71#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000 86#define IXP2000_PCI_CSR_VIRT_BASE 0xfec00000
72#define IXP2000_PCI_CSR_SIZE 0x00100000 87#define IXP2000_PCI_CSR_SIZE 0x00100000
73 88
89#define IXP2000_MSF_PHYS_BASE 0xc8000000
90#define IXP2000_MSF_VIRT_BASE 0xfeb00000
91#define IXP2000_MSF_SIZE 0x00100000
92
74#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000 93#define IXP2000_PCI_IO_PHYS_BASE 0xd8000000
75#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000 94#define IXP2000_PCI_IO_VIRT_BASE 0xfd000000
76#define IXP2000_PCI_IO_SIZE 0x01000000 95#define IXP2000_PCI_IO_SIZE 0x01000000
@@ -241,7 +260,7 @@
241#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */ 260#define PCI_CONTROL_BE_DEI (1 << 21) /* Big Endian Data Enable In */
242#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */ 261#define PCI_CONTROL_BE_BEO (1 << 20) /* Big Endian Byte Enable Out */
243#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */ 262#define PCI_CONTROL_BE_BEI (1 << 19) /* Big Endian Byte Enable In */
244#define PCI_CONTROL_PNR (1 << 17) /* PCI Not Reset bit */ 263#define PCI_CONTROL_IEE (1 << 17) /* I/O cycle Endian swap Enable */
245 264
246#define IXP2000_PCI_RST_REL (1 << 2) 265#define IXP2000_PCI_RST_REL (1 << 2)
247#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF) 266#define CFG_RST_DIR (*IXP2000_PCI_CONTROL & IXP2000_PCICNTL_PCF)
@@ -363,6 +382,7 @@
363#define IXP2000_MIN_REV_MASK 0x0000000F 382#define IXP2000_MIN_REV_MASK 0x0000000F
364#define IXP2000_PROD_ID_MASK 0xFFFFFFFF 383#define IXP2000_PROD_ID_MASK 0xFFFFFFFF
365 384
385#define IXP2000_PRODUCT_ID GLOBAL_REG(0x00)
366#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04) 386#define IXP2000_MISC_CONTROL GLOBAL_REG(0x04)
367#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08) 387#define IXP2000_MSF_CLK_CNTRL GLOBAL_REG(0x08)
368#define IXP2000_RESET0 GLOBAL_REG(0x0c) 388#define IXP2000_RESET0 GLOBAL_REG(0x0c)