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-rw-r--r--include/asm-arm/arch-iop3xx/debug-macro.S48
-rw-r--r--include/asm-arm/arch-iop3xx/dma.h16
-rw-r--r--include/asm-arm/arch-iop3xx/entry-macro.S56
-rw-r--r--include/asm-arm/arch-iop3xx/hardware.h57
-rw-r--r--include/asm-arm/arch-iop3xx/io.h20
-rw-r--r--include/asm-arm/arch-iop3xx/iop321-irqs.h100
-rw-r--r--include/asm-arm/arch-iop3xx/iop321.h345
-rw-r--r--include/asm-arm/arch-iop3xx/iop331-irqs.h136
-rw-r--r--include/asm-arm/arch-iop3xx/iop331.h363
-rw-r--r--include/asm-arm/arch-iop3xx/iq31244.h24
-rw-r--r--include/asm-arm/arch-iop3xx/iq80321.h24
-rw-r--r--include/asm-arm/arch-iop3xx/iq80331.h23
-rw-r--r--include/asm-arm/arch-iop3xx/iq80332.h23
-rw-r--r--include/asm-arm/arch-iop3xx/irqs.h21
-rw-r--r--include/asm-arm/arch-iop3xx/memory.h41
-rw-r--r--include/asm-arm/arch-iop3xx/param.h3
-rw-r--r--include/asm-arm/arch-iop3xx/system.h35
-rw-r--r--include/asm-arm/arch-iop3xx/timex.h21
-rw-r--r--include/asm-arm/arch-iop3xx/uncompress.h57
-rw-r--r--include/asm-arm/arch-iop3xx/vmalloc.h19
20 files changed, 1432 insertions, 0 deletions
diff --git a/include/asm-arm/arch-iop3xx/debug-macro.S b/include/asm-arm/arch-iop3xx/debug-macro.S
new file mode 100644
index 000000000000..cc15f80ebd9a
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/debug-macro.S
@@ -0,0 +1,48 @@
1/* linux/include/asm-arm/arch-iop3xx/debug-macro.S
2 *
3 * Debugging macro include header
4 *
5 * Copyright (C) 1994-1999 Russell King
6 * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12*/
13
14 .macro addruart,rx
15 mov \rx, #0xfe000000 @ physical
16#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
17 orr \rx, \rx, #0x00800000 @ location of the UART
18#elif defined(CONFIG_ARCH_IOP331)
19 mrc p15, 0, \rx, c1, c0
20 tst \rx, #1 @ MMU enabled?
21 moveq \rx, #0x000fe000 @ Physical Base
22 movne \rx, #0
23 orr \rx, \rx, #0xfe000000
24 orr \rx, \rx, #0x00f00000 @ Virtual Base
25 orr \rx, \rx, #0x00001700 @ location of the UART
26#else
27#error Unknown IOP3XX implementation
28#endif
29 .endm
30
31 .macro senduart,rd,rx
32 strb \rd, [\rx]
33 .endm
34
35 .macro busyuart,rd,rx
361002: ldrb \rd, [\rx, #0x5]
37 and \rd, \rd, #0x60
38 teq \rd, #0x60
39 bne 1002b
40 .endm
41
42 .macro waituart,rd,rx
43#if !defined(CONFIG_ARCH_IQ80321) || !defined(CONFIG_ARCH_IQ31244) || !defined(CONFIG_ARCH_IQ80331)
441001: ldrb \rd, [\rx, #0x6]
45 tst \rd, #0x10
46 beq 1001b
47#endif
48 .endm
diff --git a/include/asm-arm/arch-iop3xx/dma.h b/include/asm-arm/arch-iop3xx/dma.h
new file mode 100644
index 000000000000..797f9e6fc745
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/dma.h
@@ -0,0 +1,16 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/dma.h
3 *
4 * Copyright (C) 2004 Intel Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef _IOP3XX_DMA_H_P
12#define _IOP3XX_DMA_H_P
13
14#define MAX_DMA_ADDRESS 0xffffffff
15
16#endif /* _ASM_ARCH_DMA_H_P */
diff --git a/include/asm-arm/arch-iop3xx/entry-macro.S b/include/asm-arm/arch-iop3xx/entry-macro.S
new file mode 100644
index 000000000000..e2ce7f5467c8
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/entry-macro.S
@@ -0,0 +1,56 @@
1/*
2 * include/asm-arm/arch-iop3xx/entry-macro.S
3 *
4 * Low-level IRQ helper macros for IOP3xx-based platforms
5 *
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
9 */
10
11#if defined(CONFIG_ARCH_IOP321)
12 .macro disable_fiq
13 .endm
14
15 /*
16 * Note: only deal with normal interrupts, not FIQ
17 */
18 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
19 mov \irqnr, #0
20 mrc p6, 0, \irqstat, c8, c0, 0 @ Read IINTSRC
21 cmp \irqstat, #0
22 beq 1001f
23 clz \irqnr, \irqstat
24 mov \base, #31
25 subs \irqnr,\base,\irqnr
26 add \irqnr,\irqnr,#IRQ_IOP321_DMA0_EOT
271001:
28 .endm
29
30#elif defined(CONFIG_ARCH_IOP331)
31 .macro disable_fiq
32 .endm
33
34 /*
35 * Note: only deal with normal interrupts, not FIQ
36 */
37 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
38 mov \irqnr, #0
39 mrc p6, 0, \irqstat, c4, c0, 0 @ Read IINTSRC0
40 cmp \irqstat, #0
41 bne 1002f
42 mrc p6, 0, \irqstat, c5, c0, 0 @ Read IINTSRC1
43 cmp \irqstat, #0
44 beq 1001f
45 clz \irqnr, \irqstat
46 rsbs \irqnr,\irqnr,#31 @ recommend by RMK
47 add \irqnr,\irqnr,#IRQ_IOP331_XINT8
48 b 1001f
491002: clz \irqnr, \irqstat
50 rsbs \irqnr,\irqnr,#31 @ recommend by RMK
51 add \irqnr,\irqnr,#IRQ_IOP331_DMA0_EOT
521001:
53 .endm
54
55#endif
56
diff --git a/include/asm-arm/arch-iop3xx/hardware.h b/include/asm-arm/arch-iop3xx/hardware.h
new file mode 100644
index 000000000000..3b138171d086
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/hardware.h
@@ -0,0 +1,57 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/hardware.h
3 */
4#ifndef __ASM_ARCH_HARDWARE_H
5#define __ASM_ARCH_HARDWARE_H
6
7#include <asm/types.h>
8
9/*
10 * Note about PCI IO space mappings
11 *
12 * To make IO space accesses efficient, we store virtual addresses in
13 * the IO resources.
14 *
15 * The PCI IO space is located at virtual 0xfe000000 from physical
16 * 0x90000000. The PCI BARs must be programmed with physical addresses,
17 * but when we read them, we convert them to virtual addresses. See
18 * arch/arm/mach-iop3xx/iop3xx-pci.c
19 */
20
21#define pcibios_assign_all_busses() 1
22
23
24/*
25 * The min PCI I/O and MEM space are dependent on what specific
26 * chipset/platform we are running on, so instead of hardcoding with
27 * #ifdefs, we just fill these in the platform level PCI init code.
28 */
29#ifndef __ASSEMBLY__
30extern unsigned long iop3xx_pcibios_min_io;
31extern unsigned long iop3xx_pcibios_min_mem;
32
33extern unsigned int processor_id;
34#endif
35
36/*
37 * We just set these to zero since they are really bogus anyways
38 */
39#define PCIBIOS_MIN_IO (iop3xx_pcibios_min_io)
40#define PCIBIOS_MIN_MEM (iop3xx_pcibios_min_mem)
41
42/*
43 * Generic chipset bits
44 *
45 */
46#include "iop321.h"
47#include "iop331.h"
48
49/*
50 * Board specific bits
51 */
52#include "iq80321.h"
53#include "iq31244.h"
54#include "iq80331.h"
55#include "iq80332.h"
56
57#endif /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-iop3xx/io.h b/include/asm-arm/arch-iop3xx/io.h
new file mode 100644
index 000000000000..2761dfd8694d
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/io.h
@@ -0,0 +1,20 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/io.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __ASM_ARM_ARCH_IO_H
12#define __ASM_ARM_ARCH_IO_H
13
14#define IO_SPACE_LIMIT 0xffffffff
15
16#define __io(p) ((void __iomem *)(p))
17#define __mem_pci(a) (a)
18#define __mem_isa(a) (a)
19
20#endif
diff --git a/include/asm-arm/arch-iop3xx/iop321-irqs.h b/include/asm-arm/arch-iop3xx/iop321-irqs.h
new file mode 100644
index 000000000000..2fcc1654cb9d
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop321-irqs.h
@@ -0,0 +1,100 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/irqs.h
3 *
4 * Author: Rory Bolt <rorybolt@pacbell.net>
5 * Copyright: (C) 2002 Rory Bolt
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#ifndef _IOP321_IRQS_H_
13#define _IOP321_IRQS_H_
14
15/*
16 * IOP80321 chipset interrupts
17 */
18#define IOP321_IRQ_OFS 0
19#define IOP321_IRQ(x) (IOP321_IRQ_OFS + (x))
20
21/*
22 * On IRQ or FIQ register
23 */
24#define IRQ_IOP321_DMA0_EOT IOP321_IRQ(0)
25#define IRQ_IOP321_DMA0_EOC IOP321_IRQ(1)
26#define IRQ_IOP321_DMA1_EOT IOP321_IRQ(2)
27#define IRQ_IOP321_DMA1_EOC IOP321_IRQ(3)
28#define IRQ_IOP321_RSVD_4 IOP321_IRQ(4)
29#define IRQ_IOP321_RSVD_5 IOP321_IRQ(5)
30#define IRQ_IOP321_AA_EOT IOP321_IRQ(6)
31#define IRQ_IOP321_AA_EOC IOP321_IRQ(7)
32#define IRQ_IOP321_CORE_PMON IOP321_IRQ(8)
33#define IRQ_IOP321_TIMER0 IOP321_IRQ(9)
34#define IRQ_IOP321_TIMER1 IOP321_IRQ(10)
35#define IRQ_IOP321_I2C_0 IOP321_IRQ(11)
36#define IRQ_IOP321_I2C_1 IOP321_IRQ(12)
37#define IRQ_IOP321_MESSAGING IOP321_IRQ(13)
38#define IRQ_IOP321_ATU_BIST IOP321_IRQ(14)
39#define IRQ_IOP321_PERFMON IOP321_IRQ(15)
40#define IRQ_IOP321_CORE_PMU IOP321_IRQ(16)
41#define IRQ_IOP321_BIU_ERR IOP321_IRQ(17)
42#define IRQ_IOP321_ATU_ERR IOP321_IRQ(18)
43#define IRQ_IOP321_MCU_ERR IOP321_IRQ(19)
44#define IRQ_IOP321_DMA0_ERR IOP321_IRQ(20)
45#define IRQ_IOP321_DMA1_ERR IOP321_IRQ(21)
46#define IRQ_IOP321_RSVD_22 IOP321_IRQ(22)
47#define IRQ_IOP321_AA_ERR IOP321_IRQ(23)
48#define IRQ_IOP321_MSG_ERR IOP321_IRQ(24)
49#define IRQ_IOP321_SSP IOP321_IRQ(25)
50#define IRQ_IOP321_RSVD_26 IOP321_IRQ(26)
51#define IRQ_IOP321_XINT0 IOP321_IRQ(27)
52#define IRQ_IOP321_XINT1 IOP321_IRQ(28)
53#define IRQ_IOP321_XINT2 IOP321_IRQ(29)
54#define IRQ_IOP321_XINT3 IOP321_IRQ(30)
55#define IRQ_IOP321_HPI IOP321_IRQ(31)
56
57#define NR_IOP321_IRQS (IOP321_IRQ(31) + 1)
58
59#define NR_IRQS NR_IOP321_IRQS
60
61
62/*
63 * Interrupts available on the IQ80321 board
64 */
65
66/*
67 * On board devices
68 */
69#define IRQ_IQ80321_I82544 IRQ_IOP321_XINT0
70#define IRQ_IQ80321_UART IRQ_IOP321_XINT1
71
72/*
73 * PCI interrupts
74 */
75#define IRQ_IQ80321_INTA IRQ_IOP321_XINT0
76#define IRQ_IQ80321_INTB IRQ_IOP321_XINT1
77#define IRQ_IQ80321_INTC IRQ_IOP321_XINT2
78#define IRQ_IQ80321_INTD IRQ_IOP321_XINT3
79
80/*
81 * Interrupts on the IQ31244 board
82 */
83
84/*
85 * On board devices
86 */
87#define IRQ_IQ31244_UART IRQ_IOP321_XINT1
88#define IRQ_IQ31244_I82546 IRQ_IOP321_XINT0
89#define IRQ_IQ31244_SATA IRQ_IOP321_XINT2
90#define IRQ_IQ31244_PCIX_SLOT IRQ_IOP321_XINT3
91
92/*
93 * PCI interrupts
94 */
95#define IRQ_IQ31244_INTA IRQ_IOP321_XINT0
96#define IRQ_IQ31244_INTB IRQ_IOP321_XINT1
97#define IRQ_IQ31244_INTC IRQ_IOP321_XINT2
98#define IRQ_IQ31244_INTD IRQ_IOP321_XINT3
99
100#endif // _IOP321_IRQ_H_
diff --git a/include/asm-arm/arch-iop3xx/iop321.h b/include/asm-arm/arch-iop3xx/iop321.h
new file mode 100644
index 000000000000..200621ff3690
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop321.h
@@ -0,0 +1,345 @@
1/*
2 * linux/include/asm/arch-iop3xx/iop321.h
3 *
4 * Intel IOP321 Chip definitions
5 *
6 * Author: Rory Bolt <rorybolt@pacbell.net>
7 * Copyright (C) 2002 Rory Bolt
8 * Copyright (C) 2004 Intel Corp.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License version 2 as
12 * published by the Free Software Foundation.
13 */
14
15#ifndef _IOP321_HW_H_
16#define _IOP321_HW_H_
17
18
19/*
20 * This is needed for mixed drivers that need to work on all
21 * IOP3xx variants but behave slightly differently on each.
22 */
23#ifndef __ASSEMBLY__
24#ifdef CONFIG_ARCH_IOP321
25#define iop_is_321() (((processor_id & 0xfffff5e0) == 0x69052420))
26#else
27#define iop_is_321() 0
28#endif
29#endif
30
31/*
32 * IOP321 I/O and Mem space regions for PCI autoconfiguration
33 */
34#define IOP321_PCI_IO_WINDOW_SIZE 0x00010000
35#define IOP321_PCI_LOWER_IO_PA 0x90000000
36#define IOP321_PCI_LOWER_IO_VA 0xfe000000
37#define IOP321_PCI_LOWER_IO_BA (*IOP321_OIOWTVR)
38#define IOP321_PCI_UPPER_IO_PA (IOP321_PCI_LOWER_IO_PA + IOP321_PCI_IO_WINDOW_SIZE - 1)
39#define IOP321_PCI_UPPER_IO_VA (IOP321_PCI_LOWER_IO_VA + IOP321_PCI_IO_WINDOW_SIZE - 1)
40#define IOP321_PCI_UPPER_IO_BA (IOP321_PCI_LOWER_IO_BA + IOP321_PCI_IO_WINDOW_SIZE - 1)
41#define IOP321_PCI_IO_OFFSET (IOP321_PCI_LOWER_IO_VA - IOP321_PCI_LOWER_IO_BA)
42
43//#define IOP321_PCI_MEM_WINDOW_SIZE (~*IOP321_IALR1 + 1)
44#define IOP321_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
45#define IOP321_PCI_LOWER_MEM_PA 0x80000000
46#define IOP321_PCI_LOWER_MEM_BA (*IOP321_OMWTVR0)
47#define IOP321_PCI_UPPER_MEM_PA (IOP321_PCI_LOWER_MEM_PA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
48#define IOP321_PCI_UPPER_MEM_BA (IOP321_PCI_LOWER_MEM_BA + IOP321_PCI_MEM_WINDOW_SIZE - 1)
49#define IOP321_PCI_MEM_OFFSET (IOP321_PCI_LOWER_MEM_PA - IOP321_PCI_LOWER_MEM_BA)
50
51
52/*
53 * IOP321 chipset registers
54 */
55#define IOP321_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
56#define IOP321_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
57#define IOP321_REG_ADDR(reg) (IOP321_VIRT_MEM_BASE | (reg))
58
59/* Reserved 0x00000000 through 0x000000FF */
60
61/* Address Translation Unit 0x00000100 through 0x000001FF */
62#define IOP321_ATUVID (volatile u16 *)IOP321_REG_ADDR(0x00000100)
63#define IOP321_ATUDID (volatile u16 *)IOP321_REG_ADDR(0x00000102)
64#define IOP321_ATUCMD (volatile u16 *)IOP321_REG_ADDR(0x00000104)
65#define IOP321_ATUSR (volatile u16 *)IOP321_REG_ADDR(0x00000106)
66#define IOP321_ATURID (volatile u8 *)IOP321_REG_ADDR(0x00000108)
67#define IOP321_ATUCCR (volatile u32 *)IOP321_REG_ADDR(0x00000109)
68#define IOP321_ATUCLSR (volatile u8 *)IOP321_REG_ADDR(0x0000010C)
69#define IOP321_ATULT (volatile u8 *)IOP321_REG_ADDR(0x0000010D)
70#define IOP321_ATUHTR (volatile u8 *)IOP321_REG_ADDR(0x0000010E)
71#define IOP321_ATUBIST (volatile u8 *)IOP321_REG_ADDR(0x0000010F)
72#define IOP321_IABAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000110)
73#define IOP321_IAUBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000114)
74#define IOP321_IABAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000118)
75#define IOP321_IAUBAR1 (volatile u32 *)IOP321_REG_ADDR(0x0000011C)
76#define IOP321_IABAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000120)
77#define IOP321_IAUBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000124)
78#define IOP321_ASVIR (volatile u16 *)IOP321_REG_ADDR(0x0000012C)
79#define IOP321_ASIR (volatile u16 *)IOP321_REG_ADDR(0x0000012E)
80#define IOP321_ERBAR (volatile u32 *)IOP321_REG_ADDR(0x00000130)
81/* Reserved 0x00000134 through 0x0000013B */
82#define IOP321_ATUILR (volatile u8 *)IOP321_REG_ADDR(0x0000013C)
83#define IOP321_ATUIPR (volatile u8 *)IOP321_REG_ADDR(0x0000013D)
84#define IOP321_ATUMGNT (volatile u8 *)IOP321_REG_ADDR(0x0000013E)
85#define IOP321_ATUMLAT (volatile u8 *)IOP321_REG_ADDR(0x0000013F)
86#define IOP321_IALR0 (volatile u32 *)IOP321_REG_ADDR(0x00000140)
87#define IOP321_IATVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000144)
88#define IOP321_ERLR (volatile u32 *)IOP321_REG_ADDR(0x00000148)
89#define IOP321_ERTVR (volatile u32 *)IOP321_REG_ADDR(0x0000014C)
90#define IOP321_IALR1 (volatile u32 *)IOP321_REG_ADDR(0x00000150)
91#define IOP321_IALR2 (volatile u32 *)IOP321_REG_ADDR(0x00000154)
92#define IOP321_IATVR2 (volatile u32 *)IOP321_REG_ADDR(0x00000158)
93#define IOP321_OIOWTVR (volatile u32 *)IOP321_REG_ADDR(0x0000015C)
94#define IOP321_OMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000160)
95#define IOP321_OUMWTVR0 (volatile u32 *)IOP321_REG_ADDR(0x00000164)
96#define IOP321_OMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x00000168)
97#define IOP321_OUMWTVR1 (volatile u32 *)IOP321_REG_ADDR(0x0000016C)
98/* Reserved 0x00000170 through 0x00000177*/
99#define IOP321_OUDWTVR (volatile u32 *)IOP321_REG_ADDR(0x00000178)
100/* Reserved 0x0000017C through 0x0000017F*/
101#define IOP321_ATUCR (volatile u32 *)IOP321_REG_ADDR(0x00000180)
102#define IOP321_PCSR (volatile u32 *)IOP321_REG_ADDR(0x00000184)
103#define IOP321_ATUISR (volatile u32 *)IOP321_REG_ADDR(0x00000188)
104#define IOP321_ATUIMR (volatile u32 *)IOP321_REG_ADDR(0x0000018C)
105#define IOP321_IABAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000190)
106#define IOP321_IAUBAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000194)
107#define IOP321_IALR3 (volatile u32 *)IOP321_REG_ADDR(0x00000198)
108#define IOP321_IATVR3 (volatile u32 *)IOP321_REG_ADDR(0x0000019C)
109/* Reserved 0x000001A0 through 0x000001A3*/
110#define IOP321_OCCAR (volatile u32 *)IOP321_REG_ADDR(0x000001A4)
111/* Reserved 0x000001A8 through 0x000001AB*/
112#define IOP321_OCCDR (volatile u32 *)IOP321_REG_ADDR(0x000001AC)
113/* Reserved 0x000001B0 through 0x000001BB*/
114#define IOP321_PDSCR (volatile u32 *)IOP321_REG_ADDR(0x000001BC)
115#define IOP321_PMCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001C0)
116#define IOP321_PMNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001C1)
117#define IOP321_APMCR (volatile u16 *)IOP321_REG_ADDR(0x000001C2)
118#define IOP321_APMCSR (volatile u16 *)IOP321_REG_ADDR(0x000001C4)
119/* Reserved 0x000001C6 through 0x000001DF */
120#define IOP321_PCIXCAPID (volatile u8 *)IOP321_REG_ADDR(0x000001E0)
121#define IOP321_PCIXNEXT (volatile u8 *)IOP321_REG_ADDR(0x000001E1)
122#define IOP321_PCIXCMD (volatile u16 *)IOP321_REG_ADDR(0x000001E2)
123#define IOP321_PCIXSR (volatile u32 *)IOP321_REG_ADDR(0x000001E4)
124#define IOP321_PCIIRSR (volatile u32 *)IOP321_REG_ADDR(0x000001EC)
125
126/* Messaging Unit 0x00000300 through 0x000003FF */
127
128/* Reserved 0x00000300 through 0x0000030c */
129#define IOP321_IMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000310)
130#define IOP321_IMR1 (volatile u32 *)IOP321_REG_ADDR(0x00000314)
131#define IOP321_OMR0 (volatile u32 *)IOP321_REG_ADDR(0x00000318)
132#define IOP321_OMR1 (volatile u32 *)IOP321_REG_ADDR(0x0000031C)
133#define IOP321_IDR (volatile u32 *)IOP321_REG_ADDR(0x00000320)
134#define IOP321_IISR (volatile u32 *)IOP321_REG_ADDR(0x00000324)
135#define IOP321_IIMR (volatile u32 *)IOP321_REG_ADDR(0x00000328)
136#define IOP321_ODR (volatile u32 *)IOP321_REG_ADDR(0x0000032C)
137#define IOP321_OISR (volatile u32 *)IOP321_REG_ADDR(0x00000330)
138#define IOP321_OIMR (volatile u32 *)IOP321_REG_ADDR(0x00000334)
139/* Reserved 0x00000338 through 0x0000034F */
140#define IOP321_MUCR (volatile u32 *)IOP321_REG_ADDR(0x00000350)
141#define IOP321_QBAR (volatile u32 *)IOP321_REG_ADDR(0x00000354)
142/* Reserved 0x00000358 through 0x0000035C */
143#define IOP321_IFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000360)
144#define IOP321_IFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000364)
145#define IOP321_IPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000368)
146#define IOP321_IPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000036C)
147#define IOP321_OFHPR (volatile u32 *)IOP321_REG_ADDR(0x00000370)
148#define IOP321_OFTPR (volatile u32 *)IOP321_REG_ADDR(0x00000374)
149#define IOP321_OPHPR (volatile u32 *)IOP321_REG_ADDR(0x00000378)
150#define IOP321_OPTPR (volatile u32 *)IOP321_REG_ADDR(0x0000037C)
151#define IOP321_IAR (volatile u32 *)IOP321_REG_ADDR(0x00000380)
152
153#define IOP321_IIxR_MASK 0x7f /* masks all */
154#define IOP321_IIxR_IRI 0x40 /* RC Index Register Interrupt */
155#define IOP321_IIxR_OFQF 0x20 /* RC Output Free Q Full (ERROR) */
156#define IOP321_IIxR_ipq 0x10 /* RC Inbound Post Q (post) */
157#define IOP321_IIxR_ERRDI 0x08 /* RO Error Doorbell Interrupt */
158#define IOP321_IIxR_IDI 0x04 /* RO Inbound Doorbell Interrupt */
159#define IOP321_IIxR_IM1 0x02 /* RC Inbound Message 1 Interrupt */
160#define IOP321_IIxR_IM0 0x01 /* RC Inbound Message 0 Interrupt */
161
162/* Reserved 0x00000384 through 0x000003FF */
163
164/* DMA Controller 0x00000400 through 0x000004FF */
165#define IOP321_DMA0_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000400)
166#define IOP321_DMA0_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000404)
167#define IOP321_DMA0_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000040C)
168#define IOP321_DMA0_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000410)
169#define IOP321_DMA0_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000414)
170#define IOP321_DMA0_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000418)
171#define IOP321_DMA0_LADR (volatile u32 *)IOP321_REG_ADDR(0X0000041C)
172#define IOP321_DMA0_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000420)
173#define IOP321_DMA0_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000424)
174/* Reserved 0x00000428 through 0x0000043C */
175#define IOP321_DMA1_CCR (volatile u32 *)IOP321_REG_ADDR(0x00000440)
176#define IOP321_DMA1_CSR (volatile u32 *)IOP321_REG_ADDR(0x00000444)
177#define IOP321_DMA1_DAR (volatile u32 *)IOP321_REG_ADDR(0x0000044C)
178#define IOP321_DMA1_NDAR (volatile u32 *)IOP321_REG_ADDR(0x00000450)
179#define IOP321_DMA1_PADR (volatile u32 *)IOP321_REG_ADDR(0x00000454)
180#define IOP321_DMA1_PUADR (volatile u32 *)IOP321_REG_ADDR(0x00000458)
181#define IOP321_DMA1_LADR (volatile u32 *)IOP321_REG_ADDR(0x0000045C)
182#define IOP321_DMA1_BCR (volatile u32 *)IOP321_REG_ADDR(0x00000460)
183#define IOP321_DMA1_DCR (volatile u32 *)IOP321_REG_ADDR(0x00000464)
184/* Reserved 0x00000468 through 0x000004FF */
185
186/* Memory controller 0x00000500 through 0x0005FF */
187
188/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
189#define IOP321_PBCR (volatile u32 *)IOP321_REG_ADDR(0x00000680)
190#define IOP321_PBISR (volatile u32 *)IOP321_REG_ADDR(0x00000684)
191#define IOP321_PBBAR0 (volatile u32 *)IOP321_REG_ADDR(0x00000688)
192#define IOP321_PBLR0 (volatile u32 *)IOP321_REG_ADDR(0x0000068C)
193#define IOP321_PBBAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000690)
194#define IOP321_PBLR1 (volatile u32 *)IOP321_REG_ADDR(0x00000694)
195#define IOP321_PBBAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000698)
196#define IOP321_PBLR2 (volatile u32 *)IOP321_REG_ADDR(0x0000069C)
197#define IOP321_PBBAR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A0)
198#define IOP321_PBLR3 (volatile u32 *)IOP321_REG_ADDR(0x000006A4)
199#define IOP321_PBBAR4 (volatile u32 *)IOP321_REG_ADDR(0x000006A8)
200#define IOP321_PBLR4 (volatile u32 *)IOP321_REG_ADDR(0x000006AC)
201#define IOP321_PBBAR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B0)
202#define IOP321_PBLR5 (volatile u32 *)IOP321_REG_ADDR(0x000006B4)
203#define IOP321_PBDSCR (volatile u32 *)IOP321_REG_ADDR(0x000006B8)
204/* Reserved 0x000006BC */
205#define IOP321_PMBR0 (volatile u32 *)IOP321_REG_ADDR(0x000006C0)
206/* Reserved 0x000006C4 through 0x000006DC */
207#define IOP321_PMBR1 (volatile u32 *)IOP321_REG_ADDR(0x000006E0)
208#define IOP321_PMBR2 (volatile u32 *)IOP321_REG_ADDR(0x000006E4)
209
210#define IOP321_PBCR_EN 0x1
211
212#define IOP321_PBISR_BOOR_ERR 0x1
213
214/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
215#define IOP321_GTMR (volatile u32 *)IOP321_REG_ADDR(0x00000700)
216#define IOP321_ESR (volatile u32 *)IOP321_REG_ADDR(0x00000704)
217#define IOP321_EMISR (volatile u32 *)IOP321_REG_ADDR(0x00000708)
218/* reserved 0x00000070c */
219#define IOP321_GTSR (volatile u32 *)IOP321_REG_ADDR(0x00000710)
220/* PERC0 DOESN'T EXIST - index from 1! */
221#define IOP321_PERCR0 (volatile u32 *)IOP321_REG_ADDR(0x00000710)
222
223#define IOP321_GTMR_NGCE 0x04 /* (Not) Global Counter Enable */
224
225/* Internal arbitration unit 0x00000780 through 0x0007BF */
226#define IOP321_IACR (volatile u32 *)IOP321_REG_ADDR(0x00000780)
227#define IOP321_MTTR1 (volatile u32 *)IOP321_REG_ADDR(0x00000784)
228#define IOP321_MTTR2 (volatile u32 *)IOP321_REG_ADDR(0x00000788)
229
230/* General Purpose I/O Registers */
231#define IOP321_GPOE (volatile u32 *)IOP321_REG_ADDR(0x000007C4)
232#define IOP321_GPID (volatile u32 *)IOP321_REG_ADDR(0x000007C8)
233#define IOP321_GPOD (volatile u32 *)IOP321_REG_ADDR(0x000007CC)
234
235/* Interrupt Controller */
236#define IOP321_INTCTL (volatile u32 *)IOP321_REG_ADDR(0x000007D0)
237#define IOP321_INTSTR (volatile u32 *)IOP321_REG_ADDR(0x000007D4)
238#define IOP321_IINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007D8)
239#define IOP321_FINTSRC (volatile u32 *)IOP321_REG_ADDR(0x000007DC)
240
241/* Timers */
242
243#define IOP321_TU_TMR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E0)
244#define IOP321_TU_TMR1 (volatile u32 *)IOP321_REG_ADDR(0x000007E4)
245
246#ifdef CONFIG_ARCH_IQ80321
247#define IOP321_TICK_RATE 200000000 /* 200 MHz clock */
248#elif defined(CONFIG_ARCH_IQ31244)
249#define IOP321_TICK_RATE 198000000 /* 33.000 MHz crystal */
250#endif
251
252#ifdef CONFIG_ARCH_EP80219
253#undef IOP321_TICK_RATE
254#define IOP321_TICK_RATE 200000000 /* 33.333333 Mhz crystal */
255#endif
256
257#define IOP321_TMR_TC 0x01
258#define IOP321_TMR_EN 0x02
259#define IOP321_TMR_RELOAD 0x04
260#define IOP321_TMR_PRIVILEGED 0x09
261
262#define IOP321_TMR_RATIO_1_1 0x00
263#define IOP321_TMR_RATIO_4_1 0x10
264#define IOP321_TMR_RATIO_8_1 0x20
265#define IOP321_TMR_RATIO_16_1 0x30
266
267#define IOP321_TU_TCR0 (volatile u32 *)IOP321_REG_ADDR(0x000007E8)
268#define IOP321_TU_TCR1 (volatile u32 *)IOP321_REG_ADDR(0x000007EC)
269#define IOP321_TU_TRR0 (volatile u32 *)IOP321_REG_ADDR(0x000007F0)
270#define IOP321_TU_TRR1 (volatile u32 *)IOP321_REG_ADDR(0x000007F4)
271#define IOP321_TU_TISR (volatile u32 *)IOP321_REG_ADDR(0x000007F8)
272#define IOP321_TU_WDTCR (volatile u32 *)IOP321_REG_ADDR(0x000007FC)
273
274/* Application accelerator unit 0x00000800 - 0x000008FF */
275#define IOP321_AAU_ACR (volatile u32 *)IOP321_REG_ADDR(0x00000800)
276#define IOP321_AAU_ASR (volatile u32 *)IOP321_REG_ADDR(0x00000804)
277#define IOP321_AAU_ADAR (volatile u32 *)IOP321_REG_ADDR(0x00000808)
278#define IOP321_AAU_ANDAR (volatile u32 *)IOP321_REG_ADDR(0x0000080C)
279#define IOP321_AAU_SAR1 (volatile u32 *)IOP321_REG_ADDR(0x00000810)
280#define IOP321_AAU_SAR2 (volatile u32 *)IOP321_REG_ADDR(0x00000814)
281#define IOP321_AAU_SAR3 (volatile u32 *)IOP321_REG_ADDR(0x00000818)
282#define IOP321_AAU_SAR4 (volatile u32 *)IOP321_REG_ADDR(0x0000081C)
283#define IOP321_AAU_SAR5 (volatile u32 *)IOP321_REG_ADDR(0x0000082C)
284#define IOP321_AAU_SAR6 (volatile u32 *)IOP321_REG_ADDR(0x00000830)
285#define IOP321_AAU_SAR7 (volatile u32 *)IOP321_REG_ADDR(0x00000834)
286#define IOP321_AAU_SAR8 (volatile u32 *)IOP321_REG_ADDR(0x00000838)
287#define IOP321_AAU_SAR9 (volatile u32 *)IOP321_REG_ADDR(0x00000840)
288#define IOP321_AAU_SAR10 (volatile u32 *)IOP321_REG_ADDR(0x00000844)
289#define IOP321_AAU_SAR11 (volatile u32 *)IOP321_REG_ADDR(0x00000848)
290#define IOP321_AAU_SAR12 (volatile u32 *)IOP321_REG_ADDR(0x0000084C)
291#define IOP321_AAU_SAR13 (volatile u32 *)IOP321_REG_ADDR(0x00000850)
292#define IOP321_AAU_SAR14 (volatile u32 *)IOP321_REG_ADDR(0x00000854)
293#define IOP321_AAU_SAR15 (volatile u32 *)IOP321_REG_ADDR(0x00000858)
294#define IOP321_AAU_SAR16 (volatile u32 *)IOP321_REG_ADDR(0x0000085C)
295#define IOP321_AAU_SAR17 (volatile u32 *)IOP321_REG_ADDR(0x00000864)
296#define IOP321_AAU_SAR18 (volatile u32 *)IOP321_REG_ADDR(0x00000868)
297#define IOP321_AAU_SAR19 (volatile u32 *)IOP321_REG_ADDR(0x0000086C)
298#define IOP321_AAU_SAR20 (volatile u32 *)IOP321_REG_ADDR(0x00000870)
299#define IOP321_AAU_SAR21 (volatile u32 *)IOP321_REG_ADDR(0x00000874)
300#define IOP321_AAU_SAR22 (volatile u32 *)IOP321_REG_ADDR(0x00000878)
301#define IOP321_AAU_SAR23 (volatile u32 *)IOP321_REG_ADDR(0x0000087C)
302#define IOP321_AAU_SAR24 (volatile u32 *)IOP321_REG_ADDR(0x00000880)
303#define IOP321_AAU_SAR25 (volatile u32 *)IOP321_REG_ADDR(0x00000888)
304#define IOP321_AAU_SAR26 (volatile u32 *)IOP321_REG_ADDR(0x0000088C)
305#define IOP321_AAU_SAR27 (volatile u32 *)IOP321_REG_ADDR(0x00000890)
306#define IOP321_AAU_SAR28 (volatile u32 *)IOP321_REG_ADDR(0x00000894)
307#define IOP321_AAU_SAR29 (volatile u32 *)IOP321_REG_ADDR(0x00000898)
308#define IOP321_AAU_SAR30 (volatile u32 *)IOP321_REG_ADDR(0x0000089C)
309#define IOP321_AAU_SAR31 (volatile u32 *)IOP321_REG_ADDR(0x000008A0)
310#define IOP321_AAU_SAR32 (volatile u32 *)IOP321_REG_ADDR(0x000008A4)
311#define IOP321_AAU_DAR (volatile u32 *)IOP321_REG_ADDR(0x00000820)
312#define IOP321_AAU_ABCR (volatile u32 *)IOP321_REG_ADDR(0x00000824)
313#define IOP321_AAU_ADCR (volatile u32 *)IOP321_REG_ADDR(0x00000828)
314#define IOP321_AAU_EDCR0 (volatile u32 *)IOP321_REG_ADDR(0x0000083c)
315#define IOP321_AAU_EDCR1 (volatile u32 *)IOP321_REG_ADDR(0x00000860)
316#define IOP321_AAU_EDCR2 (volatile u32 *)IOP321_REG_ADDR(0x00000884)
317
318
319/* SSP serial port unit 0x00001600 - 0x0000167F */
320/* I2C bus interface unit 0x00001680 - 0x000016FF */
321#define IOP321_ICR0 (volatile u32 *)IOP321_REG_ADDR(0x00001680)
322#define IOP321_ISR0 (volatile u32 *)IOP321_REG_ADDR(0x00001684)
323#define IOP321_ISAR0 (volatile u32 *)IOP321_REG_ADDR(0x00001688)
324#define IOP321_IDBR0 (volatile u32 *)IOP321_REG_ADDR(0x0000168C)
325/* Reserved 0x00001690 */
326#define IOP321_IBMR0 (volatile u32 *)IOP321_REG_ADDR(0x00001694)
327/* Reserved 0x00001698 */
328/* Reserved 0x0000169C */
329#define IOP321_ICR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A0)
330#define IOP321_ISR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A4)
331#define IOP321_ISAR1 (volatile u32 *)IOP321_REG_ADDR(0x000016A8)
332#define IOP321_IDBR1 (volatile u32 *)IOP321_REG_ADDR(0x000016AC)
333#define IOP321_IBMR1 (volatile u32 *)IOP321_REG_ADDR(0x000016B4)
334/* Reserved 0x000016B8 through 0x000016FC */
335
336/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
337
338
339#ifndef __ASSEMBLY__
340extern void iop321_map_io(void);
341extern void iop321_init_irq(void);
342extern void iop321_time_init(void);
343#endif
344
345#endif // _IOP321_HW_H_
diff --git a/include/asm-arm/arch-iop3xx/iop331-irqs.h b/include/asm-arm/arch-iop3xx/iop331-irqs.h
new file mode 100644
index 000000000000..8ff73d487222
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop331-irqs.h
@@ -0,0 +1,136 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/irqs.h
3 *
4 * Author: Dave Jiang (dave.jiang@intel.com)
5 * Copyright: (C) 2003 Intel Corp.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 */
12#ifndef _IOP331_IRQS_H_
13#define _IOP331_IRQS_H_
14
15/*
16 * IOP80331 chipset interrupts
17 */
18#define IOP331_IRQ_OFS 0
19#define IOP331_IRQ(x) (IOP331_IRQ_OFS + (x))
20
21/*
22 * On IRQ or FIQ register
23 */
24#define IRQ_IOP331_DMA0_EOT IOP331_IRQ(0)
25#define IRQ_IOP331_DMA0_EOC IOP331_IRQ(1)
26#define IRQ_IOP331_DMA1_EOT IOP331_IRQ(2)
27#define IRQ_IOP331_DMA1_EOC IOP331_IRQ(3)
28#define IRQ_IOP331_RSVD_4 IOP331_IRQ(4)
29#define IRQ_IOP331_RSVD_5 IOP331_IRQ(5)
30#define IRQ_IOP331_AA_EOT IOP331_IRQ(6)
31#define IRQ_IOP331_AA_EOC IOP331_IRQ(7)
32#define IRQ_IOP331_TIMER0 IOP331_IRQ(8)
33#define IRQ_IOP331_TIMER1 IOP331_IRQ(9)
34#define IRQ_IOP331_I2C_0 IOP331_IRQ(10)
35#define IRQ_IOP331_I2C_1 IOP331_IRQ(11)
36#define IRQ_IOP331_MSG IOP331_IRQ(12)
37#define IRQ_IOP331_MSGIBQ IOP331_IRQ(13)
38#define IRQ_IOP331_ATU_BIST IOP331_IRQ(14)
39#define IRQ_IOP331_PERFMON IOP331_IRQ(15)
40#define IRQ_IOP331_CORE_PMU IOP331_IRQ(16)
41#define IRQ_IOP331_RSVD_17 IOP331_IRQ(17)
42#define IRQ_IOP331_RSVD_18 IOP331_IRQ(18)
43#define IRQ_IOP331_RSVD_19 IOP331_IRQ(19)
44#define IRQ_IOP331_RSVD_20 IOP331_IRQ(20)
45#define IRQ_IOP331_RSVD_21 IOP331_IRQ(21)
46#define IRQ_IOP331_RSVD_22 IOP331_IRQ(22)
47#define IRQ_IOP331_RSVD_23 IOP331_IRQ(23)
48#define IRQ_IOP331_XINT0 IOP331_IRQ(24)
49#define IRQ_IOP331_XINT1 IOP331_IRQ(25)
50#define IRQ_IOP331_XINT2 IOP331_IRQ(26)
51#define IRQ_IOP331_XINT3 IOP331_IRQ(27)
52#define IRQ_IOP331_RSVD_28 IOP331_IRQ(28)
53#define IRQ_IOP331_RSVD_29 IOP331_IRQ(29)
54#define IRQ_IOP331_RSVD_30 IOP331_IRQ(30)
55#define IRQ_IOP331_RSVD_31 IOP331_IRQ(31)
56#define IRQ_IOP331_XINT8 IOP331_IRQ(32) // 0
57#define IRQ_IOP331_XINT9 IOP331_IRQ(33) // 1
58#define IRQ_IOP331_XINT10 IOP331_IRQ(34) // 2
59#define IRQ_IOP331_XINT11 IOP331_IRQ(35) // 3
60#define IRQ_IOP331_XINT12 IOP331_IRQ(36) // 4
61#define IRQ_IOP331_XINT13 IOP331_IRQ(37) // 5
62#define IRQ_IOP331_XINT14 IOP331_IRQ(38) // 6
63#define IRQ_IOP331_XINT15 IOP331_IRQ(39) // 7
64#define IRQ_IOP331_RSVD_40 IOP331_IRQ(40) // 8
65#define IRQ_IOP331_RSVD_41 IOP331_IRQ(41) // 9
66#define IRQ_IOP331_RSVD_42 IOP331_IRQ(42) // 10
67#define IRQ_IOP331_RSVD_43 IOP331_IRQ(43) // 11
68#define IRQ_IOP331_RSVD_44 IOP331_IRQ(44) // 12
69#define IRQ_IOP331_RSVD_45 IOP331_IRQ(45) // 13
70#define IRQ_IOP331_RSVD_46 IOP331_IRQ(46) // 14
71#define IRQ_IOP331_RSVD_47 IOP331_IRQ(47) // 15
72#define IRQ_IOP331_RSVD_48 IOP331_IRQ(48) // 16
73#define IRQ_IOP331_RSVD_49 IOP331_IRQ(49) // 17
74#define IRQ_IOP331_RSVD_50 IOP331_IRQ(50) // 18
75#define IRQ_IOP331_UART0 IOP331_IRQ(51) // 19
76#define IRQ_IOP331_UART1 IOP331_IRQ(52) // 20
77#define IRQ_IOP331_PBIE IOP331_IRQ(53) // 21
78#define IRQ_IOP331_ATU_CRW IOP331_IRQ(54) // 22
79#define IRQ_IOP331_ATU_ERR IOP331_IRQ(55) // 23
80#define IRQ_IOP331_MCU_ERR IOP331_IRQ(56) // 24
81#define IRQ_IOP331_DMA0_ERR IOP331_IRQ(57) // 25
82#define IRQ_IOP331_DMA1_ERR IOP331_IRQ(58) // 26
83#define IRQ_IOP331_RSVD_59 IOP331_IRQ(59) // 27
84#define IRQ_IOP331_AA_ERR IOP331_IRQ(60) // 28
85#define IRQ_IOP331_RSVD_61 IOP331_IRQ(61) // 29
86#define IRQ_IOP331_MSG_ERR IOP331_IRQ(62) // 30
87#define IRQ_IOP331_HPI IOP331_IRQ(63) // 31
88
89#define NR_IOP331_IRQS (IOP331_IRQ(63) + 1)
90
91#define NR_IRQS NR_IOP331_IRQS
92
93
94#if defined(CONFIG_ARCH_IQ80331)
95/*
96 * Interrupts available on the IQ80331 board
97 */
98
99/*
100 * On board devices
101 */
102#define IRQ_IQ80331_I82544 IRQ_IOP331_XINT0
103#define IRQ_IQ80331_UART0 IRQ_IOP331_UART0
104#define IRQ_IQ80331_UART1 IRQ_IOP331_UART1
105
106/*
107 * PCI interrupts
108 */
109#define IRQ_IQ80331_INTA IRQ_IOP331_XINT0
110#define IRQ_IQ80331_INTB IRQ_IOP331_XINT1
111#define IRQ_IQ80331_INTC IRQ_IOP331_XINT2
112#define IRQ_IQ80331_INTD IRQ_IOP331_XINT3
113
114#elif defined(CONFIG_MACH_IQ80332)
115/*
116 * Interrupts available on the IQ80332 board
117 */
118
119/*
120 * On board devices
121 */
122#define IRQ_IQ80332_I82544 IRQ_IOP331_XINT0
123#define IRQ_IQ80332_UART0 IRQ_IOP331_UART0
124#define IRQ_IQ80332_UART1 IRQ_IOP331_UART1
125
126/*
127 * PCI interrupts
128 */
129#define IRQ_IQ80332_INTA IRQ_IOP331_XINT0
130#define IRQ_IQ80332_INTB IRQ_IOP331_XINT1
131#define IRQ_IQ80332_INTC IRQ_IOP331_XINT2
132#define IRQ_IQ80332_INTD IRQ_IOP331_XINT3
133
134#endif
135
136#endif // _IOP331_IRQ_H_
diff --git a/include/asm-arm/arch-iop3xx/iop331.h b/include/asm-arm/arch-iop3xx/iop331.h
new file mode 100644
index 000000000000..96adffd8bad2
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iop331.h
@@ -0,0 +1,363 @@
1/*
2 * linux/include/asm/arch-iop3xx/iop331.h
3 *
4 * Intel IOP331 Chip definitions
5 *
6 * Author: Dave Jiang (dave.jiang@intel.com)
7 * Copyright (C) 2003, 2004 Intel Corp.
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
14#ifndef _IOP331_HW_H_
15#define _IOP331_HW_H_
16
17
18/*
19 * This is needed for mixed drivers that need to work on all
20 * IOP3xx variants but behave slightly differently on each.
21 */
22#ifndef __ASSEMBLY__
23#ifdef CONFIG_ARCH_IOP331
24/*#define iop_is_331() ((processor_id & 0xffffffb0) == 0x69054090) */
25#define iop_is_331() ((processor_id & 0xffffff30) == 0x69054010)
26#else
27#define iop_is_331() 0
28#endif
29#endif
30
31/*
32 * IOP331 I/O and Mem space regions for PCI autoconfiguration
33 */
34#define IOP331_PCI_IO_WINDOW_SIZE 0x00010000
35#define IOP331_PCI_LOWER_IO_PA 0x90000000
36#define IOP331_PCI_LOWER_IO_VA 0xfe000000
37#define IOP331_PCI_LOWER_IO_BA (*IOP331_OIOWTVR)
38#define IOP331_PCI_UPPER_IO_PA (IOP331_PCI_LOWER_IO_PA + IOP331_PCI_IO_WINDOW_SIZE - 1)
39#define IOP331_PCI_UPPER_IO_VA (IOP331_PCI_LOWER_IO_VA + IOP331_PCI_IO_WINDOW_SIZE - 1)
40#define IOP331_PCI_UPPER_IO_BA (IOP331_PCI_LOWER_IO_BA + IOP331_PCI_IO_WINDOW_SIZE - 1)
41#define IOP331_PCI_IO_OFFSET (IOP331_PCI_LOWER_IO_VA - IOP331_PCI_LOWER_IO_BA)
42
43/* this can be 128M if OMWTVR1 is set */
44#define IOP331_PCI_MEM_WINDOW_SIZE 0x04000000 /* 64M outbound window */
45//#define IOP331_PCI_MEM_WINDOW_SIZE (~*IOP331_IALR1 + 1)
46#define IOP331_PCI_LOWER_MEM_PA 0x80000000
47#define IOP331_PCI_LOWER_MEM_BA (*IOP331_OMWTVR0)
48#define IOP331_PCI_UPPER_MEM_PA (IOP331_PCI_LOWER_MEM_PA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
49#define IOP331_PCI_UPPER_MEM_BA (IOP331_PCI_LOWER_MEM_BA + IOP331_PCI_MEM_WINDOW_SIZE - 1)
50#define IOP331_PCI_MEM_OFFSET (IOP331_PCI_LOWER_MEM_PA - IOP331_PCI_LOWER_MEM_BA)
51
52/*
53 * IOP331 chipset registers
54 */
55#define IOP331_VIRT_MEM_BASE 0xfeffe000 /* chip virtual mem address*/
56#define IOP331_PHYS_MEM_BASE 0xffffe000 /* chip physical memory address */
57#define IOP331_REG_ADDR(reg) (IOP331_VIRT_MEM_BASE | (reg))
58
59/* Reserved 0x00000000 through 0x000000FF */
60
61/* Address Translation Unit 0x00000100 through 0x000001FF */
62#define IOP331_ATUVID (volatile u16 *)IOP331_REG_ADDR(0x00000100)
63#define IOP331_ATUDID (volatile u16 *)IOP331_REG_ADDR(0x00000102)
64#define IOP331_ATUCMD (volatile u16 *)IOP331_REG_ADDR(0x00000104)
65#define IOP331_ATUSR (volatile u16 *)IOP331_REG_ADDR(0x00000106)
66#define IOP331_ATURID (volatile u8 *)IOP331_REG_ADDR(0x00000108)
67#define IOP331_ATUCCR (volatile u32 *)IOP331_REG_ADDR(0x00000109)
68#define IOP331_ATUCLSR (volatile u8 *)IOP331_REG_ADDR(0x0000010C)
69#define IOP331_ATULT (volatile u8 *)IOP331_REG_ADDR(0x0000010D)
70#define IOP331_ATUHTR (volatile u8 *)IOP331_REG_ADDR(0x0000010E)
71#define IOP331_ATUBIST (volatile u8 *)IOP331_REG_ADDR(0x0000010F)
72#define IOP331_IABAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000110)
73#define IOP331_IAUBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000114)
74#define IOP331_IABAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000118)
75#define IOP331_IAUBAR1 (volatile u32 *)IOP331_REG_ADDR(0x0000011C)
76#define IOP331_IABAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000120)
77#define IOP331_IAUBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000124)
78#define IOP331_ASVIR (volatile u16 *)IOP331_REG_ADDR(0x0000012C)
79#define IOP331_ASIR (volatile u16 *)IOP331_REG_ADDR(0x0000012E)
80#define IOP331_ERBAR (volatile u32 *)IOP331_REG_ADDR(0x00000130)
81#define IOP331_ATU_CAPPTR (volatile u32 *)IOP331_REG_ADDR(0x00000134)
82/* Reserved 0x00000138 through 0x0000013B */
83#define IOP331_ATUILR (volatile u8 *)IOP331_REG_ADDR(0x0000013C)
84#define IOP331_ATUIPR (volatile u8 *)IOP331_REG_ADDR(0x0000013D)
85#define IOP331_ATUMGNT (volatile u8 *)IOP331_REG_ADDR(0x0000013E)
86#define IOP331_ATUMLAT (volatile u8 *)IOP331_REG_ADDR(0x0000013F)
87#define IOP331_IALR0 (volatile u32 *)IOP331_REG_ADDR(0x00000140)
88#define IOP331_IATVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000144)
89#define IOP331_ERLR (volatile u32 *)IOP331_REG_ADDR(0x00000148)
90#define IOP331_ERTVR (volatile u32 *)IOP331_REG_ADDR(0x0000014C)
91#define IOP331_IALR1 (volatile u32 *)IOP331_REG_ADDR(0x00000150)
92#define IOP331_IALR2 (volatile u32 *)IOP331_REG_ADDR(0x00000154)
93#define IOP331_IATVR2 (volatile u32 *)IOP331_REG_ADDR(0x00000158)
94#define IOP331_OIOWTVR (volatile u32 *)IOP331_REG_ADDR(0x0000015C)
95#define IOP331_OMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000160)
96#define IOP331_OUMWTVR0 (volatile u32 *)IOP331_REG_ADDR(0x00000164)
97#define IOP331_OMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x00000168)
98#define IOP331_OUMWTVR1 (volatile u32 *)IOP331_REG_ADDR(0x0000016C)
99/* Reserved 0x00000170 through 0x00000177*/
100#define IOP331_OUDWTVR (volatile u32 *)IOP331_REG_ADDR(0x00000178)
101/* Reserved 0x0000017C through 0x0000017F*/
102#define IOP331_ATUCR (volatile u32 *)IOP331_REG_ADDR(0x00000180)
103#define IOP331_PCSR (volatile u32 *)IOP331_REG_ADDR(0x00000184)
104#define IOP331_ATUISR (volatile u32 *)IOP331_REG_ADDR(0x00000188)
105#define IOP331_ATUIMR (volatile u32 *)IOP331_REG_ADDR(0x0000018C)
106#define IOP331_IABAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000190)
107#define IOP331_IAUBAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000194)
108#define IOP331_IALR3 (volatile u32 *)IOP331_REG_ADDR(0x00000198)
109#define IOP331_IATVR3 (volatile u32 *)IOP331_REG_ADDR(0x0000019C)
110/* Reserved 0x000001A0 through 0x000001A3*/
111#define IOP331_OCCAR (volatile u32 *)IOP331_REG_ADDR(0x000001A4)
112/* Reserved 0x000001A8 through 0x000001AB*/
113#define IOP331_OCCDR (volatile u32 *)IOP331_REG_ADDR(0x000001AC)
114/* Reserved 0x000001B0 through 0x000001BB*/
115#define IOP331_VPDCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001B8)
116#define IOP331_VPDNXTP (volatile u8 *)IOP331_REG_ADDR(0x000001B9)
117#define IOP331_VPDAR (volatile u16 *)IOP331_REG_ADDR(0x000001BA)
118#define IOP331_VPDDR (volatile u32 *)IOP331_REG_ADDR(0x000001BC)
119#define IOP331_PMCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001C0)
120#define IOP331_PMNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001C1)
121#define IOP331_APMCR (volatile u16 *)IOP331_REG_ADDR(0x000001C2)
122#define IOP331_APMCSR (volatile u16 *)IOP331_REG_ADDR(0x000001C4)
123/* Reserved 0x000001C6 through 0x000001CF */
124#define IOP331_MSICAPID (volatile u8 *)IOP331_REG_ADDR(0x000001D0)
125#define IOP331_MSINXTP (volatile u8 *)IOP331_REG_ADDR(0x000001D1)
126#define IOP331_MSIMCR (volatile u16 *)IOP331_REG_ADDR(0x000001D2)
127#define IOP331_MSIMAR (volatile u32 *)IOP331_REG_ADDR(0x000001D4)
128#define IOP331_MSIMUAR (volatile u32 *)IOP331_REG_ADDR(0x000001D8)
129#define IOP331_MSIMDR (volatile u32 *)IOP331_REG_ADDR(0x000001DC)
130#define IOP331_PCIXCAPID (volatile u8 *)IOP331_REG_ADDR(0x000001E0)
131#define IOP331_PCIXNEXT (volatile u8 *)IOP331_REG_ADDR(0x000001E1)
132#define IOP331_PCIXCMD (volatile u16 *)IOP331_REG_ADDR(0x000001E2)
133#define IOP331_PCIXSR (volatile u32 *)IOP331_REG_ADDR(0x000001E4)
134#define IOP331_PCIIRSR (volatile u32 *)IOP331_REG_ADDR(0x000001EC)
135
136/* Messaging Unit 0x00000300 through 0x000003FF */
137
138/* Reserved 0x00000300 through 0x0000030c */
139#define IOP331_IMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000310)
140#define IOP331_IMR1 (volatile u32 *)IOP331_REG_ADDR(0x00000314)
141#define IOP331_OMR0 (volatile u32 *)IOP331_REG_ADDR(0x00000318)
142#define IOP331_OMR1 (volatile u32 *)IOP331_REG_ADDR(0x0000031C)
143#define IOP331_IDR (volatile u32 *)IOP331_REG_ADDR(0x00000320)
144#define IOP331_IISR (volatile u32 *)IOP331_REG_ADDR(0x00000324)
145#define IOP331_IIMR (volatile u32 *)IOP331_REG_ADDR(0x00000328)
146#define IOP331_ODR (volatile u32 *)IOP331_REG_ADDR(0x0000032C)
147#define IOP331_OISR (volatile u32 *)IOP331_REG_ADDR(0x00000330)
148#define IOP331_OIMR (volatile u32 *)IOP331_REG_ADDR(0x00000334)
149/* Reserved 0x00000338 through 0x0000034F */
150#define IOP331_MUCR (volatile u32 *)IOP331_REG_ADDR(0x00000350)
151#define IOP331_QBAR (volatile u32 *)IOP331_REG_ADDR(0x00000354)
152/* Reserved 0x00000358 through 0x0000035C */
153#define IOP331_IFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000360)
154#define IOP331_IFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000364)
155#define IOP331_IPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000368)
156#define IOP331_IPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000036C)
157#define IOP331_OFHPR (volatile u32 *)IOP331_REG_ADDR(0x00000370)
158#define IOP331_OFTPR (volatile u32 *)IOP331_REG_ADDR(0x00000374)
159#define IOP331_OPHPR (volatile u32 *)IOP331_REG_ADDR(0x00000378)
160#define IOP331_OPTPR (volatile u32 *)IOP331_REG_ADDR(0x0000037C)
161#define IOP331_IAR (volatile u32 *)IOP331_REG_ADDR(0x00000380)
162/* Reserved 0x00000384 through 0x000003FF */
163
164/* DMA Controller 0x00000400 through 0x000004FF */
165#define IOP331_DMA0_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000400)
166#define IOP331_DMA0_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000404)
167#define IOP331_DMA0_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000040C)
168#define IOP331_DMA0_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000410)
169#define IOP331_DMA0_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000414)
170#define IOP331_DMA0_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000418)
171#define IOP331_DMA0_LADR (volatile u32 *)IOP331_REG_ADDR(0X0000041C)
172#define IOP331_DMA0_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000420)
173#define IOP331_DMA0_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000424)
174/* Reserved 0x00000428 through 0x0000043C */
175#define IOP331_DMA1_CCR (volatile u32 *)IOP331_REG_ADDR(0x00000440)
176#define IOP331_DMA1_CSR (volatile u32 *)IOP331_REG_ADDR(0x00000444)
177#define IOP331_DMA1_DAR (volatile u32 *)IOP331_REG_ADDR(0x0000044C)
178#define IOP331_DMA1_NDAR (volatile u32 *)IOP331_REG_ADDR(0x00000450)
179#define IOP331_DMA1_PADR (volatile u32 *)IOP331_REG_ADDR(0x00000454)
180#define IOP331_DMA1_PUADR (volatile u32 *)IOP331_REG_ADDR(0x00000458)
181#define IOP331_DMA1_LADR (volatile u32 *)IOP331_REG_ADDR(0x0000045C)
182#define IOP331_DMA1_BCR (volatile u32 *)IOP331_REG_ADDR(0x00000460)
183#define IOP331_DMA1_DCR (volatile u32 *)IOP331_REG_ADDR(0x00000464)
184/* Reserved 0x00000468 through 0x000004FF */
185
186/* Memory controller 0x00000500 through 0x0005FF */
187
188/* Peripheral bus interface unit 0x00000680 through 0x0006FF */
189#define IOP331_PBCR (volatile u32 *)IOP331_REG_ADDR(0x00000680)
190#define IOP331_PBISR (volatile u32 *)IOP331_REG_ADDR(0x00000684)
191#define IOP331_PBBAR0 (volatile u32 *)IOP331_REG_ADDR(0x00000688)
192#define IOP331_PBLR0 (volatile u32 *)IOP331_REG_ADDR(0x0000068C)
193#define IOP331_PBBAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000690)
194#define IOP331_PBLR1 (volatile u32 *)IOP331_REG_ADDR(0x00000694)
195#define IOP331_PBBAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000698)
196#define IOP331_PBLR2 (volatile u32 *)IOP331_REG_ADDR(0x0000069C)
197#define IOP331_PBBAR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A0)
198#define IOP331_PBLR3 (volatile u32 *)IOP331_REG_ADDR(0x000006A4)
199#define IOP331_PBBAR4 (volatile u32 *)IOP331_REG_ADDR(0x000006A8)
200#define IOP331_PBLR4 (volatile u32 *)IOP331_REG_ADDR(0x000006AC)
201#define IOP331_PBBAR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B0)
202#define IOP331_PBLR5 (volatile u32 *)IOP331_REG_ADDR(0x000006B4)
203#define IOP331_PBDSCR (volatile u32 *)IOP331_REG_ADDR(0x000006B8)
204/* Reserved 0x000006BC */
205#define IOP331_PMBR0 (volatile u32 *)IOP331_REG_ADDR(0x000006C0)
206/* Reserved 0x000006C4 through 0x000006DC */
207#define IOP331_PMBR1 (volatile u32 *)IOP331_REG_ADDR(0x000006E0)
208#define IOP331_PMBR2 (volatile u32 *)IOP331_REG_ADDR(0x000006E4)
209
210#define IOP331_PBCR_EN 0x1
211
212#define IOP331_PBISR_BOOR_ERR 0x1
213
214
215
216/* Peripheral performance monitoring unit 0x00000700 through 0x00077F */
217/* Internal arbitration unit 0x00000780 through 0x0007BF */
218
219/* Interrupt Controller */
220#define IOP331_INTCTL0 (volatile u32 *)IOP331_REG_ADDR(0x00000790)
221#define IOP331_INTCTL1 (volatile u32 *)IOP331_REG_ADDR(0x00000794)
222#define IOP331_INTSTR0 (volatile u32 *)IOP331_REG_ADDR(0x00000798)
223#define IOP331_INTSTR1 (volatile u32 *)IOP331_REG_ADDR(0x0000079C)
224#define IOP331_IINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A0)
225#define IOP331_IINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007A4)
226#define IOP331_FINTSRC0 (volatile u32 *)IOP331_REG_ADDR(0x000007A8)
227#define IOP331_FINTSRC1 (volatile u32 *)IOP331_REG_ADDR(0x000007AC)
228#define IOP331_IPR0 (volatile u32 *)IOP331_REG_ADDR(0x000007B0)
229#define IOP331_IPR1 (volatile u32 *)IOP331_REG_ADDR(0x000007B4)
230#define IOP331_IPR2 (volatile u32 *)IOP331_REG_ADDR(0x000007B8)
231#define IOP331_IPR3 (volatile u32 *)IOP331_REG_ADDR(0x000007BC)
232#define IOP331_INTBASE (volatile u32 *)IOP331_REG_ADDR(0x000007C0)
233#define IOP331_INTSIZE (volatile u32 *)IOP331_REG_ADDR(0x000007C4)
234#define IOP331_IINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007C8)
235#define IOP331_FINTVEC (volatile u32 *)IOP331_REG_ADDR(0x000007CC)
236
237
238/* Timers */
239
240#define IOP331_TU_TMR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D0)
241#define IOP331_TU_TMR1 (volatile u32 *)IOP331_REG_ADDR(0x000007D4)
242
243#define IOP331_TMR_TC 0x01
244#define IOP331_TMR_EN 0x02
245#define IOP331_TMR_RELOAD 0x04
246#define IOP331_TMR_PRIVILEGED 0x09
247
248#define IOP331_TMR_RATIO_1_1 0x00
249#define IOP331_TMR_RATIO_4_1 0x10
250#define IOP331_TMR_RATIO_8_1 0x20
251#define IOP331_TMR_RATIO_16_1 0x30
252
253#define IOP331_TU_TCR0 (volatile u32 *)IOP331_REG_ADDR(0x000007D8)
254#define IOP331_TU_TCR1 (volatile u32 *)IOP331_REG_ADDR(0x000007DC)
255#define IOP331_TU_TRR0 (volatile u32 *)IOP331_REG_ADDR(0x000007E0)
256#define IOP331_TU_TRR1 (volatile u32 *)IOP331_REG_ADDR(0x000007E4)
257#define IOP331_TU_TISR (volatile u32 *)IOP331_REG_ADDR(0x000007E8)
258#define IOP331_TU_WDTCR (volatile u32 *)IOP331_REG_ADDR(0x000007EC)
259
260#if defined(CONFIG_ARCH_IOP331)
261#define IOP331_TICK_RATE 266000000 /* 266 MHz IB clock */
262#endif
263
264#if defined(CONFIG_IOP331_STEPD) || defined(CONFIG_ARCH_IQ80333)
265#undef IOP331_TICK_RATE
266#define IOP331_TICK_RATE 333000000 /* 333 Mhz IB clock */
267#endif
268
269/* Application accelerator unit 0x00000800 - 0x000008FF */
270#define IOP331_AAU_ACR (volatile u32 *)IOP331_REG_ADDR(0x00000800)
271#define IOP331_AAU_ASR (volatile u32 *)IOP331_REG_ADDR(0x00000804)
272#define IOP331_AAU_ADAR (volatile u32 *)IOP331_REG_ADDR(0x00000808)
273#define IOP331_AAU_ANDAR (volatile u32 *)IOP331_REG_ADDR(0x0000080C)
274#define IOP331_AAU_SAR1 (volatile u32 *)IOP331_REG_ADDR(0x00000810)
275#define IOP331_AAU_SAR2 (volatile u32 *)IOP331_REG_ADDR(0x00000814)
276#define IOP331_AAU_SAR3 (volatile u32 *)IOP331_REG_ADDR(0x00000818)
277#define IOP331_AAU_SAR4 (volatile u32 *)IOP331_REG_ADDR(0x0000081C)
278#define IOP331_AAU_SAR5 (volatile u32 *)IOP331_REG_ADDR(0x0000082C)
279#define IOP331_AAU_SAR6 (volatile u32 *)IOP331_REG_ADDR(0x00000830)
280#define IOP331_AAU_SAR7 (volatile u32 *)IOP331_REG_ADDR(0x00000834)
281#define IOP331_AAU_SAR8 (volatile u32 *)IOP331_REG_ADDR(0x00000838)
282#define IOP331_AAU_SAR9 (volatile u32 *)IOP331_REG_ADDR(0x00000840)
283#define IOP331_AAU_SAR10 (volatile u32 *)IOP331_REG_ADDR(0x00000844)
284#define IOP331_AAU_SAR11 (volatile u32 *)IOP331_REG_ADDR(0x00000848)
285#define IOP331_AAU_SAR12 (volatile u32 *)IOP331_REG_ADDR(0x0000084C)
286#define IOP331_AAU_SAR13 (volatile u32 *)IOP331_REG_ADDR(0x00000850)
287#define IOP331_AAU_SAR14 (volatile u32 *)IOP331_REG_ADDR(0x00000854)
288#define IOP331_AAU_SAR15 (volatile u32 *)IOP331_REG_ADDR(0x00000858)
289#define IOP331_AAU_SAR16 (volatile u32 *)IOP331_REG_ADDR(0x0000085C)
290#define IOP331_AAU_SAR17 (volatile u32 *)IOP331_REG_ADDR(0x00000864)
291#define IOP331_AAU_SAR18 (volatile u32 *)IOP331_REG_ADDR(0x00000868)
292#define IOP331_AAU_SAR19 (volatile u32 *)IOP331_REG_ADDR(0x0000086C)
293#define IOP331_AAU_SAR20 (volatile u32 *)IOP331_REG_ADDR(0x00000870)
294#define IOP331_AAU_SAR21 (volatile u32 *)IOP331_REG_ADDR(0x00000874)
295#define IOP331_AAU_SAR22 (volatile u32 *)IOP331_REG_ADDR(0x00000878)
296#define IOP331_AAU_SAR23 (volatile u32 *)IOP331_REG_ADDR(0x0000087C)
297#define IOP331_AAU_SAR24 (volatile u32 *)IOP331_REG_ADDR(0x00000880)
298#define IOP331_AAU_SAR25 (volatile u32 *)IOP331_REG_ADDR(0x00000888)
299#define IOP331_AAU_SAR26 (volatile u32 *)IOP331_REG_ADDR(0x0000088C)
300#define IOP331_AAU_SAR27 (volatile u32 *)IOP331_REG_ADDR(0x00000890)
301#define IOP331_AAU_SAR28 (volatile u32 *)IOP331_REG_ADDR(0x00000894)
302#define IOP331_AAU_SAR29 (volatile u32 *)IOP331_REG_ADDR(0x00000898)
303#define IOP331_AAU_SAR30 (volatile u32 *)IOP331_REG_ADDR(0x0000089C)
304#define IOP331_AAU_SAR31 (volatile u32 *)IOP331_REG_ADDR(0x000008A0)
305#define IOP331_AAU_SAR32 (volatile u32 *)IOP331_REG_ADDR(0x000008A4)
306#define IOP331_AAU_DAR (volatile u32 *)IOP331_REG_ADDR(0x00000820)
307#define IOP331_AAU_ABCR (volatile u32 *)IOP331_REG_ADDR(0x00000824)
308#define IOP331_AAU_ADCR (volatile u32 *)IOP331_REG_ADDR(0x00000828)
309#define IOP331_AAU_EDCR0 (volatile u32 *)IOP331_REG_ADDR(0x0000083c)
310#define IOP331_AAU_EDCR1 (volatile u32 *)IOP331_REG_ADDR(0x00000860)
311#define IOP331_AAU_EDCR2 (volatile u32 *)IOP331_REG_ADDR(0x00000884)
312
313
314#define IOP331_SPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C0)
315#define IOP331_PPDSCR (volatile u32 *)IOP331_REG_ADDR(0x000015C8)
316/* SSP serial port unit 0x00001600 - 0x0000167F */
317
318/* I2C bus interface unit 0x00001680 - 0x000016FF */
319/* for I2C bit defs see drivers/i2c/i2c-iop3xx.h */
320
321#define IOP331_ICR0 (volatile u32 *)IOP331_REG_ADDR(0x00001680)
322#define IOP331_ISR0 (volatile u32 *)IOP331_REG_ADDR(0x00001684)
323#define IOP331_ISAR0 (volatile u32 *)IOP331_REG_ADDR(0x00001688)
324#define IOP331_IDBR0 (volatile u32 *)IOP331_REG_ADDR(0x0000168C)
325/* Reserved 0x00001690 */
326#define IOP331_IBMR0 (volatile u32 *)IOP331_REG_ADDR(0x00001694)
327/* Reserved 0x00001698 */
328/* Reserved 0x0000169C */
329#define IOP331_ICR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A0)
330#define IOP331_ISR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A4)
331#define IOP331_ISAR1 (volatile u32 *)IOP331_REG_ADDR(0x000016A8)
332#define IOP331_IDBR1 (volatile u32 *)IOP331_REG_ADDR(0x000016AC)
333#define IOP331_IBMR1 (volatile u32 *)IOP331_REG_ADDR(0x000016B4)
334/* Reserved 0x000016B8 through 0x000016FF */
335
336/* 0x00001700 through 0x0000172C UART 0 */
337
338/* Reserved 0x00001730 through 0x0000173F */
339
340/* 0x00001740 through 0x0000176C UART 1 */
341
342#define IOP331_UART0_PHYS (IOP331_PHYS_MEM_BASE | 0x00001700) /* UART #1 physical */
343#define IOP331_UART1_PHYS (IOP331_PHYS_MEM_BASE | 0x00001740) /* UART #2 physical */
344#define IOP331_UART0_VIRT (IOP331_VIRT_MEM_BASE | 0x00001700) /* UART #1 virtual addr */
345#define IOP331_UART1_VIRT (IOP331_VIRT_MEM_BASE | 0x00001740) /* UART #2 virtual addr */
346
347/* Reserved 0x00001770 through 0x0000177F */
348
349/* General Purpose I/O Registers */
350#define IOP331_GPOE (volatile u32 *)IOP331_REG_ADDR(0x00001780)
351#define IOP331_GPID (volatile u32 *)IOP331_REG_ADDR(0x00001784)
352#define IOP331_GPOD (volatile u32 *)IOP331_REG_ADDR(0x00001788)
353
354/* Reserved 0x0000178c through 0x000019ff */
355
356
357#ifndef __ASSEMBLY__
358extern void iop331_map_io(void);
359extern void iop331_init_irq(void);
360extern void iop331_time_init(void);
361#endif
362
363#endif // _IOP331_HW_H_
diff --git a/include/asm-arm/arch-iop3xx/iq31244.h b/include/asm-arm/arch-iop3xx/iq31244.h
new file mode 100644
index 000000000000..4177cfa8100f
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iq31244.h
@@ -0,0 +1,24 @@
1/*
2 * linux/include/asm/arch-iop3xx/iq31244.h
3 *
4 * Intel IQ31244 evaluation board registers
5 */
6
7#ifndef _IQ31244_H_
8#define _IQ31244_H_
9
10#define IQ31244_FLASHBASE 0xf0000000 /* Flash */
11#define IQ31244_FLASHSIZE 0x00800000
12#define IQ31244_FLASHWIDTH 2
13
14#define IQ31244_UART 0xfe800000 /* UART #1 */
15#define IQ31244_7SEG_1 0xfe840000 /* 7-Segment MSB */
16#define IQ31244_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
17#define IQ31244_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
18#define IQ31244_BATT_STAT 0xfe8f0000 /* Battery Status */
19
20#ifndef __ASSEMBLY__
21extern void iq31244_map_io(void);
22#endif
23
24#endif // _IQ31244_H_
diff --git a/include/asm-arm/arch-iop3xx/iq80321.h b/include/asm-arm/arch-iop3xx/iq80321.h
new file mode 100644
index 000000000000..cb8725979ffa
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iq80321.h
@@ -0,0 +1,24 @@
1/*
2 * linux/include/asm/arch-iop3xx/iq80321.h
3 *
4 * Intel IQ80321 evaluation board registers
5 */
6
7#ifndef _IQ80321_H_
8#define _IQ80321_H_
9
10#define IQ80321_FLASHBASE 0xf0000000 /* Flash */
11#define IQ80321_FLASHSIZE 0x00800000
12#define IQ80321_FLASHWIDTH 1
13
14#define IQ80321_UART 0xfe800000 /* UART #1 */
15#define IQ80321_7SEG_1 0xfe840000 /* 7-Segment MSB */
16#define IQ80321_7SEG_0 0xfe850000 /* 7-Segment LSB (WO) */
17#define IQ80321_ROTARY_SW 0xfe8d0000 /* Rotary Switch */
18#define IQ80321_BATT_STAT 0xfe8f0000 /* Battery Status */
19
20#ifndef __ASSEMBLY__
21extern void iq80321_map_io(void);
22#endif
23
24#endif // _IQ80321_H_
diff --git a/include/asm-arm/arch-iop3xx/iq80331.h b/include/asm-arm/arch-iop3xx/iq80331.h
new file mode 100644
index 000000000000..0668e78d483e
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iq80331.h
@@ -0,0 +1,23 @@
1/*
2 * linux/include/asm/arch-iop3xx/iq80331.h
3 *
4 * Intel IQ80331 evaluation board registers
5 */
6
7#ifndef _IQ80331_H_
8#define _IQ80331_H_
9
10#define IQ80331_FLASHBASE 0xc0000000 /* Flash */
11#define IQ80331_FLASHSIZE 0x00800000
12#define IQ80331_FLASHWIDTH 1
13
14#define IQ80331_7SEG_1 0xce840000 /* 7-Segment MSB */
15#define IQ80331_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
16#define IQ80331_ROTARY_SW 0xce8d0000 /* Rotary Switch */
17#define IQ80331_BATT_STAT 0xce8f0000 /* Battery Status */
18
19#ifndef __ASSEMBLY__
20extern void iq80331_map_io(void);
21#endif
22
23#endif // _IQ80331_H_
diff --git a/include/asm-arm/arch-iop3xx/iq80332.h b/include/asm-arm/arch-iop3xx/iq80332.h
new file mode 100644
index 000000000000..e5fff1775d1a
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/iq80332.h
@@ -0,0 +1,23 @@
1/*
2 * linux/include/asm/arch-iop3xx/iq80332.h
3 *
4 * Intel IQ80332 evaluation board registers
5 */
6
7#ifndef _IQ80332_H_
8#define _IQ80332_H_
9
10#define IQ80332_FLASHBASE 0xc0000000 /* Flash */
11#define IQ80332_FLASHSIZE 0x00800000
12#define IQ80332_FLASHWIDTH 1
13
14#define IQ80332_7SEG_1 0xce840000 /* 7-Segment MSB */
15#define IQ80332_7SEG_0 0xce850000 /* 7-Segment LSB (WO) */
16#define IQ80332_ROTARY_SW 0xce8d0000 /* Rotary Switch */
17#define IQ80332_BATT_STAT 0xce8f0000 /* Battery Status */
18
19#ifndef __ASSEMBLY__
20extern void iq80332_map_io(void);
21#endif
22
23#endif // _IQ80332_H_
diff --git a/include/asm-arm/arch-iop3xx/irqs.h b/include/asm-arm/arch-iop3xx/irqs.h
new file mode 100644
index 000000000000..b2c03f4c269c
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/irqs.h
@@ -0,0 +1,21 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/irqs.h
3 *
4 * Copyright: (C) 2001-2003 MontaVista Software Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 */
11
12/*
13 * Chipset-specific bits
14 */
15#ifdef CONFIG_ARCH_IOP321
16#include "iop321-irqs.h"
17#endif
18
19#ifdef CONFIG_ARCH_IOP331
20#include "iop331-irqs.h"
21#endif
diff --git a/include/asm-arm/arch-iop3xx/memory.h b/include/asm-arm/arch-iop3xx/memory.h
new file mode 100644
index 000000000000..dc4735cb0c10
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/memory.h
@@ -0,0 +1,41 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/memory.h
3 */
4
5#ifndef __ASM_ARCH_MEMORY_H
6#define __ASM_ARCH_MEMORY_H
7
8#include <linux/config.h>
9#include <asm/hardware.h>
10
11/*
12 * Physical DRAM offset.
13 */
14#ifndef CONFIG_ARCH_IOP331
15#define PHYS_OFFSET (0xa0000000UL)
16#else
17#define PHYS_OFFSET (0x00000000UL)
18#endif
19
20/*
21 * Virtual view <-> PCI DMA view memory address translations
22 * virt_to_bus: Used to translate the virtual address to an
23 * address suitable to be passed to set_dma_addr
24 * bus_to_virt: Used to convert an address for DMA operations
25 * to an address that the kernel can use.
26 */
27#if defined(CONFIG_ARCH_IOP321)
28
29#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP321_IATVR2)) | ((*IOP321_IABAR2) & 0xfffffff0))
30#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP321_IALR2)) | ( *IOP321_IATVR2)))
31
32#elif defined(CONFIG_ARCH_IOP331)
33
34#define __virt_to_bus(x) (((__virt_to_phys(x)) & ~(*IOP331_IATVR2)) | ((*IOP331_IABAR2) & 0xfffffff0))
35#define __bus_to_virt(x) (__phys_to_virt(((x) & ~(*IOP331_IALR2)) | ( *IOP331_IATVR2)))
36
37#endif
38
39#define PFN_TO_NID(addr) (0)
40
41#endif
diff --git a/include/asm-arm/arch-iop3xx/param.h b/include/asm-arm/arch-iop3xx/param.h
new file mode 100644
index 000000000000..acf404e87358
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/param.h
@@ -0,0 +1,3 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/param.h
3 */
diff --git a/include/asm-arm/arch-iop3xx/system.h b/include/asm-arm/arch-iop3xx/system.h
new file mode 100644
index 000000000000..af6ae8cd36c9
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/system.h
@@ -0,0 +1,35 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/system.h
3 *
4 * Copyright (C) 2001 MontaVista Software, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11static inline void arch_idle(void)
12{
13 cpu_do_idle();
14}
15
16
17static inline void arch_reset(char mode)
18{
19#ifdef CONFIG_ARCH_IOP321
20 *IOP321_PCSR = 0x30;
21#endif
22
23#ifdef CONFIG_ARCH_IOP331
24 *IOP331_PCSR = 0x30;
25#endif
26
27 if ( 1 && mode == 's') {
28 /* Jump into ROM at address 0 */
29 cpu_reset(0);
30 } else {
31 /* No on-chip reset capability */
32 cpu_reset(0);
33 }
34}
35
diff --git a/include/asm-arm/arch-iop3xx/timex.h b/include/asm-arm/arch-iop3xx/timex.h
new file mode 100644
index 000000000000..d4187fe9a85a
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/timex.h
@@ -0,0 +1,21 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/timex.h
3 *
4 * IOP3xx architecture timex specifications
5 */
6#include <linux/config.h>
7
8
9#if defined(CONFIG_ARCH_IQ80321) || defined(CONFIG_ARCH_IQ31244)
10
11#define CLOCK_TICK_RATE IOP321_TICK_RATE
12
13#elif defined(CONFIG_ARCH_IQ80331) || defined(CONFIG_MACH_IQ80332)
14
15#define CLOCK_TICK_RATE IOP331_TICK_RATE
16
17#else
18
19#error "No IOP3xx timex information for this architecture"
20
21#endif
diff --git a/include/asm-arm/arch-iop3xx/uncompress.h b/include/asm-arm/arch-iop3xx/uncompress.h
new file mode 100644
index 000000000000..82b88762c3cc
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/uncompress.h
@@ -0,0 +1,57 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/uncompress.h
3 */
4#include <linux/config.h>
5#include <asm/types.h>
6#include <asm/mach-types.h>
7#include <linux/serial_reg.h>
8#include <asm/hardware.h>
9
10#ifdef CONFIG_ARCH_IOP321
11#define UTYPE unsigned char *
12#elif defined(CONFIG_ARCH_IOP331)
13#define UTYPE u32 *
14#else
15#error "Missing IOP3xx arch type def"
16#endif
17
18static volatile UTYPE uart_base;
19
20#define TX_DONE (UART_LSR_TEMT|UART_LSR_THRE)
21
22static __inline__ void putc(char c)
23{
24 while ((uart_base[UART_LSR] & TX_DONE) != TX_DONE);
25 *uart_base = c;
26}
27
28/*
29 * This does not append a newline
30 */
31static void putstr(const char *s)
32{
33 while (*s) {
34 putc(*s);
35 if (*s == '\n')
36 putc('\r');
37 s++;
38 }
39}
40
41static __inline__ void __arch_decomp_setup(unsigned long arch_id)
42{
43 if(machine_is_iq80321())
44 uart_base = (volatile UTYPE)IQ80321_UART;
45 else if(machine_is_iq31244())
46 uart_base = (volatile UTYPE)IQ31244_UART;
47 else if(machine_is_iq80331() || machine_is_iq80332())
48 uart_base = (volatile UTYPE)IOP331_UART0_PHYS;
49 else
50 uart_base = (volatile UTYPE)0xfe800000;
51}
52
53/*
54 * nothing to do
55 */
56#define arch_decomp_setup() __arch_decomp_setup(arch_id)
57#define arch_decomp_wdog()
diff --git a/include/asm-arm/arch-iop3xx/vmalloc.h b/include/asm-arm/arch-iop3xx/vmalloc.h
new file mode 100644
index 000000000000..dc1d2a957164
--- /dev/null
+++ b/include/asm-arm/arch-iop3xx/vmalloc.h
@@ -0,0 +1,19 @@
1/*
2 * linux/include/asm-arm/arch-iop3xx/vmalloc.h
3 */
4
5/*
6 * Just any arbitrary offset to the start of the vmalloc VM area: the
7 * current 8MB value just means that there will be a 8MB "hole" after the
8 * physical memory until the kernel virtual memory starts. That means that
9 * any out-of-bounds memory accesses will hopefully be caught.
10 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
11 * area for the same reason. ;)
12 */
13#define VMALLOC_OFFSET (8*1024*1024)
14#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
15#define VMALLOC_VMADDR(x) ((unsigned long)(x))
16//#define VMALLOC_END (0xe8000000)
17/* increase usable physical RAM to ~992M per RMK */
18#define VMALLOC_END (0xfe000000)
19
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-22 01:47:57 -0400