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-rw-r--r--include/asm-arm/arch-iop13xx/entry-macro.S18
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h38
-rw-r--r--include/asm-arm/arch-iop13xx/irqs.h17
-rw-r--r--include/asm-arm/arch-iop13xx/system.h2
-rw-r--r--include/asm-arm/arch-iop13xx/time.h51
5 files changed, 63 insertions, 63 deletions
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
index 94c50283dc56..a624a7870c64 100644
--- a/include/asm-arm/arch-iop13xx/entry-macro.S
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -19,21 +19,27 @@
19 .macro disable_fiq 19 .macro disable_fiq
20 .endm 20 .endm
21 21
22 .macro get_irqnr_preamble, base, tmp
23 mrc p15, 0, \tmp, c15, c1, 0
24 orr \tmp, \tmp, #(1 << 6)
25 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
26 .endm
27
22 /* 28 /*
23 * Note: a 1-cycle window exists where iintvec will return the value 29 * Note: a 1-cycle window exists where iintvec will return the value
24 * of iintbase, so we explicitly check for "bad zeros" 30 * of iintbase, so we explicitly check for "bad zeros"
25 */ 31 */
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 32 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mrc p15, 0, \tmp, c15, c1, 0
28 orr \tmp, \tmp, #(1 << 6)
29 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
30
31 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC 33 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
32 cmp \irqnr, #0 34 cmp \irqnr, #0
33 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero 35 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
34 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff 36 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
35 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr 37 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
38 .endm
36 39
37 biceq \tmp, \tmp, #(1 << 6) 40 .macro arch_ret_to_user, tmp1, tmp2
38 mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts 41 mrc p15, 0, \tmp1, c15, c1, 0
42 ands \tmp2, \tmp1, #(1 << 6)
43 bicne \tmp1, \tmp1, #(1 << 6)
44 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
39 .endm 45 .endm
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index a88522a0ff8e..d26b755a9879 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -9,34 +9,6 @@ void iop13xx_init_irq(void);
9void iop13xx_map_io(void); 9void iop13xx_map_io(void);
10void iop13xx_platform_init(void); 10void iop13xx_platform_init(void);
11void iop13xx_init_irq(void); 11void iop13xx_init_irq(void);
12void iop13xx_init_time(unsigned long tickrate);
13unsigned long iop13xx_gettimeoffset(void);
14
15/* handle cp6 access
16 * to do: handle access in entry-armv5.S and unify with
17 * the iop3xx implementation
18 * note: use iop13xx_cp6_enable_irq_save and iop13xx_cp6_irq_restore (irq.h)
19 * when interrupts are enabled
20 */
21static inline unsigned long iop13xx_cp6_save(void)
22{
23 u32 temp, cp_flags;
24
25 asm volatile (
26 "mrc p15, 0, %1, c15, c1, 0\n\t"
27 "orr %0, %1, #(1 << 6)\n\t"
28 "mcr p15, 0, %0, c15, c1, 0\n\t"
29 : "=r" (temp), "=r"(cp_flags));
30
31 return cp_flags;
32}
33
34static inline void iop13xx_cp6_restore(unsigned long cp_flags)
35{
36 asm volatile (
37 "mcr p15, 0, %0, c15, c1, 0\n\t"
38 : : "r" (cp_flags) );
39}
40 12
41/* CPUID CP6 R0 Page 0 */ 13/* CPUID CP6 R0 Page 0 */
42static inline int iop13xx_cpu_id(void) 14static inline int iop13xx_cpu_id(void)
@@ -479,14 +451,4 @@ static inline int iop13xx_cpu_id(void)
479#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) 451#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
480#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) 452#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
481 453
482#define IOP13XX_TMR_TC 0x01
483#define IOP13XX_TMR_EN 0x02
484#define IOP13XX_TMR_RELOAD 0x04
485#define IOP13XX_TMR_PRIVILEGED 0x08
486
487#define IOP13XX_TMR_RATIO_1_1 0x00
488#define IOP13XX_TMR_RATIO_4_1 0x10
489#define IOP13XX_TMR_RATIO_8_1 0x20
490#define IOP13XX_TMR_RATIO_16_1 0x30
491
492#endif /* _IOP13XX_HW_H_ */ 454#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/irqs.h b/include/asm-arm/arch-iop13xx/irqs.h
index 442e35a40359..5c6fac2a4004 100644
--- a/include/asm-arm/arch-iop13xx/irqs.h
+++ b/include/asm-arm/arch-iop13xx/irqs.h
@@ -3,8 +3,6 @@
3 3
4#ifndef __ASSEMBLER__ 4#ifndef __ASSEMBLER__
5#include <linux/types.h> 5#include <linux/types.h>
6#include <asm/system.h> /* local_irq_save */
7#include <asm/arch/iop13xx.h> /* iop13xx_cp6_* */
8 6
9/* INTPND0 CP6 R0 Page 3 7/* INTPND0 CP6 R0 Page 3
10 */ 8 */
@@ -41,21 +39,6 @@ static inline u32 read_intpnd_3(void)
41 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val)); 39 asm volatile("mrc p6, 0, %0, c3, c3, 0":"=r" (val));
42 return val; 40 return val;
43} 41}
44
45static inline void
46iop13xx_cp6_enable_irq_save(unsigned long *cp_flags, unsigned long *irq_flags)
47{
48 local_irq_save(*irq_flags);
49 *cp_flags = iop13xx_cp6_save();
50}
51
52static inline void
53iop13xx_cp6_irq_restore(unsigned long *cp_flags,
54 unsigned long *irq_flags)
55{
56 iop13xx_cp6_restore(*cp_flags);
57 local_irq_restore(*irq_flags);
58}
59#endif 42#endif
60 43
61#define INTBASE 0 44#define INTBASE 0
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
index ee3a62530af2..127827058e1f 100644
--- a/include/asm-arm/arch-iop13xx/system.h
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -48,12 +48,10 @@ static inline void arch_reset(char mode)
48 /* 48 /*
49 * Reset the internal bus (warning both cores are reset) 49 * Reset the internal bus (warning both cores are reset)
50 */ 50 */
51 u32 cp_flags = iop13xx_cp6_save();
52 write_wdtcr(IOP13XX_WDTCR_EN_ARM); 51 write_wdtcr(IOP13XX_WDTCR_EN_ARM);
53 write_wdtcr(IOP13XX_WDTCR_EN); 52 write_wdtcr(IOP13XX_WDTCR_EN);
54 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); 53 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
55 write_wdtcr(0x1000); 54 write_wdtcr(0x1000);
56 iop13xx_cp6_restore(cp_flags);
57 55
58 for(;;); 56 for(;;);
59} 57}
diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h
new file mode 100644
index 000000000000..77a837a02dec
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/time.h
@@ -0,0 +1,51 @@
1#ifndef _IOP13XX_TIME_H_
2#define _IOP13XX_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
4
5#define IOP_TMR_EN 0x02
6#define IOP_TMR_RELOAD 0x04
7#define IOP_TMR_PRIVILEGED 0x08
8#define IOP_TMR_RATIO_1_1 0x00
9
10void iop_init_time(unsigned long tickrate);
11unsigned long iop_gettimeoffset(void);
12
13static inline void write_tmr0(u32 val)
14{
15 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
16}
17
18static inline void write_tmr1(u32 val)
19{
20 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
21}
22
23static inline u32 read_tcr0(void)
24{
25 u32 val;
26 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
27 return val;
28}
29
30static inline u32 read_tcr1(void)
31{
32 u32 val;
33 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
34 return val;
35}
36
37static inline void write_trr0(u32 val)
38{
39 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
40}
41
42static inline void write_trr1(u32 val)
43{
44 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
45}
46
47static inline void write_tisr(u32 val)
48{
49 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
50}
51#endif