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-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h43
-rw-r--r--include/asm-arm/arch-iop13xx/system.h34
2 files changed, 45 insertions, 32 deletions
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index d4e4f828577c..52b7fab7ef60 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -19,6 +19,39 @@ static inline int iop13xx_cpu_id(void)
19 return id; 19 return id;
20} 20}
21 21
22/* WDTCR CP6 R7 Page 9 */
23static inline u32 read_wdtcr(void)
24{
25 u32 val;
26 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
27 return val;
28}
29static inline void write_wdtcr(u32 val)
30{
31 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
32}
33
34/* WDTSR CP6 R8 Page 9 */
35static inline u32 read_wdtsr(void)
36{
37 u32 val;
38 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
39 return val;
40}
41static inline void write_wdtsr(u32 val)
42{
43 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
44}
45
46/* RCSR - Reset Cause Status Register */
47static inline u32 read_rcsr(void)
48{
49 u32 val;
50 asm volatile("mrc p6, 0, %0, c0, c1, 0":"=r" (val));
51 return val;
52}
53
54extern unsigned long get_iop_tick_rate(void);
22#endif 55#endif
23 56
24/* 57/*
@@ -480,4 +513,14 @@ static inline int iop13xx_cpu_id(void)
480#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) 513#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
481 514
482#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180) 515#define IOP13XX_PROCESSOR_FREQ IOP13XX_REG_ADDR32(0x2180)
516
517/* Watchdog timer definitions */
518#define IOP_WDTCR_EN_ARM 0x1e1e1e1e
519#define IOP_WDTCR_EN 0xe1e1e1e1
520#define IOP_WDTCR_DIS_ARM 0x1f1f1f1f
521#define IOP_WDTCR_DIS 0xf1f1f1f1
522#define IOP_RCSR_WDT (1 << 5) /* reset caused by watchdog timer */
523#define IOP13XX_WDTSR_WRITE_EN (1 << 31) /* used to speed up reset requests */
524#define IOP13XX_WDTCR_IB_RESET (1 << 0)
525
483#endif /* _IOP13XX_HW_H_ */ 526#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/system.h b/include/asm-arm/arch-iop13xx/system.h
index 127827058e1f..8575af8db78c 100644
--- a/include/asm-arm/arch-iop13xx/system.h
+++ b/include/asm-arm/arch-iop13xx/system.h
@@ -13,43 +13,13 @@ static inline void arch_idle(void)
13 cpu_do_idle(); 13 cpu_do_idle();
14} 14}
15 15
16/* WDTCR CP6 R7 Page 9 */
17static inline u32 read_wdtcr(void)
18{
19 u32 val;
20 asm volatile("mrc p6, 0, %0, c7, c9, 0":"=r" (val));
21 return val;
22}
23static inline void write_wdtcr(u32 val)
24{
25 asm volatile("mcr p6, 0, %0, c7, c9, 0"::"r" (val));
26}
27
28/* WDTSR CP6 R8 Page 9 */
29static inline u32 read_wdtsr(void)
30{
31 u32 val;
32 asm volatile("mrc p6, 0, %0, c8, c9, 0":"=r" (val));
33 return val;
34}
35static inline void write_wdtsr(u32 val)
36{
37 asm volatile("mcr p6, 0, %0, c8, c9, 0"::"r" (val));
38}
39
40#define IOP13XX_WDTCR_EN_ARM 0x1e1e1e1e
41#define IOP13XX_WDTCR_EN 0xe1e1e1e1
42#define IOP13XX_WDTCR_DIS_ARM 0x1f1f1f1f
43#define IOP13XX_WDTCR_DIS 0xf1f1f1f1
44#define IOP13XX_WDTSR_WRITE_EN (1 << 31)
45#define IOP13XX_WDTCR_IB_RESET (1 << 0)
46static inline void arch_reset(char mode) 16static inline void arch_reset(char mode)
47{ 17{
48 /* 18 /*
49 * Reset the internal bus (warning both cores are reset) 19 * Reset the internal bus (warning both cores are reset)
50 */ 20 */
51 write_wdtcr(IOP13XX_WDTCR_EN_ARM); 21 write_wdtcr(IOP_WDTCR_EN_ARM);
52 write_wdtcr(IOP13XX_WDTCR_EN); 22 write_wdtcr(IOP_WDTCR_EN);
53 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET); 23 write_wdtsr(IOP13XX_WDTSR_WRITE_EN | IOP13XX_WDTCR_IB_RESET);
54 write_wdtcr(0x1000); 24 write_wdtcr(0x1000);
55 25