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Diffstat (limited to 'include/asm-arm/arch-iop13xx')
-rw-r--r--include/asm-arm/arch-iop13xx/iop13xx.h12
-rw-r--r--include/asm-arm/arch-iop13xx/time.h51
2 files changed, 51 insertions, 12 deletions
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index e7430593d6fb..d26b755a9879 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -9,8 +9,6 @@ void iop13xx_init_irq(void);
9void iop13xx_map_io(void); 9void iop13xx_map_io(void);
10void iop13xx_platform_init(void); 10void iop13xx_platform_init(void);
11void iop13xx_init_irq(void); 11void iop13xx_init_irq(void);
12void iop13xx_init_time(unsigned long tickrate);
13unsigned long iop13xx_gettimeoffset(void);
14 12
15/* CPUID CP6 R0 Page 0 */ 13/* CPUID CP6 R0 Page 0 */
16static inline int iop13xx_cpu_id(void) 14static inline int iop13xx_cpu_id(void)
@@ -453,14 +451,4 @@ static inline int iop13xx_cpu_id(void)
453#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10) 451#define IOP13XX_PBI_BAR1 IOP13XX_PBI_OFFSET(0x10)
454#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14) 452#define IOP13XX_PBI_LR1 IOP13XX_PBI_OFFSET(0x14)
455 453
456#define IOP13XX_TMR_TC 0x01
457#define IOP13XX_TMR_EN 0x02
458#define IOP13XX_TMR_RELOAD 0x04
459#define IOP13XX_TMR_PRIVILEGED 0x08
460
461#define IOP13XX_TMR_RATIO_1_1 0x00
462#define IOP13XX_TMR_RATIO_4_1 0x10
463#define IOP13XX_TMR_RATIO_8_1 0x20
464#define IOP13XX_TMR_RATIO_16_1 0x30
465
466#endif /* _IOP13XX_HW_H_ */ 454#endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h
new file mode 100644
index 000000000000..77a837a02dec
--- /dev/null
+++ b/include/asm-arm/arch-iop13xx/time.h
@@ -0,0 +1,51 @@
1#ifndef _IOP13XX_TIME_H_
2#define _IOP13XX_TIME_H_
3#define IRQ_IOP_TIMER0 IRQ_IOP13XX_TIMER0
4
5#define IOP_TMR_EN 0x02
6#define IOP_TMR_RELOAD 0x04
7#define IOP_TMR_PRIVILEGED 0x08
8#define IOP_TMR_RATIO_1_1 0x00
9
10void iop_init_time(unsigned long tickrate);
11unsigned long iop_gettimeoffset(void);
12
13static inline void write_tmr0(u32 val)
14{
15 asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
16}
17
18static inline void write_tmr1(u32 val)
19{
20 asm volatile("mcr p6, 0, %0, c1, c9, 0" : : "r" (val));
21}
22
23static inline u32 read_tcr0(void)
24{
25 u32 val;
26 asm volatile("mrc p6, 0, %0, c2, c9, 0" : "=r" (val));
27 return val;
28}
29
30static inline u32 read_tcr1(void)
31{
32 u32 val;
33 asm volatile("mrc p6, 0, %0, c3, c9, 0" : "=r" (val));
34 return val;
35}
36
37static inline void write_trr0(u32 val)
38{
39 asm volatile("mcr p6, 0, %0, c4, c9, 0" : : "r" (val));
40}
41
42static inline void write_trr1(u32 val)
43{
44 asm volatile("mcr p6, 0, %0, c5, c9, 0" : : "r" (val));
45}
46
47static inline void write_tisr(u32 val)
48{
49 asm volatile("mcr p6, 0, %0, c6, c9, 0" : : "r" (val));
50}
51#endif