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-rw-r--r--include/asm-arm/arch-iop13xx/entry-macro.S18
1 files changed, 12 insertions, 6 deletions
diff --git a/include/asm-arm/arch-iop13xx/entry-macro.S b/include/asm-arm/arch-iop13xx/entry-macro.S
index 94c50283dc56..a624a7870c64 100644
--- a/include/asm-arm/arch-iop13xx/entry-macro.S
+++ b/include/asm-arm/arch-iop13xx/entry-macro.S
@@ -19,21 +19,27 @@
19 .macro disable_fiq 19 .macro disable_fiq
20 .endm 20 .endm
21 21
22 .macro get_irqnr_preamble, base, tmp
23 mrc p15, 0, \tmp, c15, c1, 0
24 orr \tmp, \tmp, #(1 << 6)
25 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
26 .endm
27
22 /* 28 /*
23 * Note: a 1-cycle window exists where iintvec will return the value 29 * Note: a 1-cycle window exists where iintvec will return the value
24 * of iintbase, so we explicitly check for "bad zeros" 30 * of iintbase, so we explicitly check for "bad zeros"
25 */ 31 */
26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 32 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
27 mrc p15, 0, \tmp, c15, c1, 0
28 orr \tmp, \tmp, #(1 << 6)
29 mcr p15, 0, \tmp, c15, c1, 0 @ Enable cp6 access
30
31 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC 33 mrc p6, 0, \irqnr, c3, c2, 0 @ Read IINTVEC
32 cmp \irqnr, #0 34 cmp \irqnr, #0
33 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero 35 mrceq p6, 0, \irqnr, c3, c2, 0 @ Re-read on potentially bad zero
34 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff 36 adds \irqstat, \irqnr, #1 @ Check for 0xffffffff
35 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr 37 movne \irqnr, \irqnr, lsr #2 @ Convert to irqnr
38 .endm
36 39
37 biceq \tmp, \tmp, #(1 << 6) 40 .macro arch_ret_to_user, tmp1, tmp2
38 mcreq p15, 0, \tmp, c15, c1, 0 @ Disable cp6 access if no more interrupts 41 mrc p15, 0, \tmp1, c15, c1, 0
42 ands \tmp2, \tmp1, #(1 << 6)
43 bicne \tmp1, \tmp1, #(1 << 6)
44 mcrne p15, 0, \tmp1, c15, c1, 0 @ Disable cp6 access
39 .endm 45 .endm