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Diffstat (limited to 'include/asm-arm/arch-imx/imx-regs.h')
-rw-r--r--include/asm-arm/arch-imx/imx-regs.h10
1 files changed, 7 insertions, 3 deletions
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index a6912b3d8671..e56a4e247d62 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -41,7 +41,13 @@
41 41
42/* PLL registers */ 42/* PLL registers */
43#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */ 43#define CSCR __REG(IMX_PLL_BASE) /* Clock Source Control Register */
44#define CSCR_SYSTEM_SEL (1<<16) 44#define CSCR_SPLL_RESTART (1<<22)
45#define CSCR_MPLL_RESTART (1<<21)
46#define CSCR_SYSTEM_SEL (1<<16)
47#define CSCR_BCLK_DIV (0xf<<10)
48#define CSCR_MPU_PRESC (1<<15)
49#define CSCR_SPEN (1<<1)
50#define CSCR_MPEN (1<<0)
45 51
46#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */ 52#define MPCTL0 __REG(IMX_PLL_BASE + 0x4) /* MCU PLL Control Register 0 */
47#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */ 53#define MPCTL1 __REG(IMX_PLL_BASE + 0x8) /* MCU PLL and System Clock Register 1 */
@@ -49,8 +55,6 @@
49#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */ 55#define SPCTL1 __REG(IMX_PLL_BASE + 0x10) /* System PLL Control Register 1 */
50#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */ 56#define PCDR __REG(IMX_PLL_BASE + 0x20) /* Peripheral Clock Divider Register */
51 57
52#define CSCR_MPLL_RESTART (1<<21)
53
54/* 58/*
55 * GPIO Module and I/O Multiplexer 59 * GPIO Module and I/O Multiplexer
56 * x = 0..3 for reg_A, reg_B, reg_C, reg_D 60 * x = 0..3 for reg_A, reg_B, reg_C, reg_D