diff options
Diffstat (limited to 'include/asm-arm/arch-imx/imx-regs.h')
| -rw-r--r-- | include/asm-arm/arch-imx/imx-regs.h | 118 |
1 files changed, 0 insertions, 118 deletions
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h index e56a4e247d62..de6494a4dc6b 100644 --- a/include/asm-arm/arch-imx/imx-regs.h +++ b/include/asm-arm/arch-imx/imx-regs.h | |||
| @@ -477,122 +477,4 @@ | |||
| 477 | #define LCDISR_EOF (1<<1) | 477 | #define LCDISR_EOF (1<<1) |
| 478 | #define LCDISR_BOF (1<<0) | 478 | #define LCDISR_BOF (1<<0) |
| 479 | 479 | ||
| 480 | /* | ||
| 481 | * UART Module. Takes the UART base address as argument | ||
| 482 | */ | ||
| 483 | #define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */ | ||
| 484 | #define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */ | ||
| 485 | #define UCR1(x) __REG( 0x80 + (x)) /* Control Register 1 */ | ||
| 486 | #define UCR2(x) __REG( 0x84 + (x)) /* Control Register 2 */ | ||
| 487 | #define UCR3(x) __REG( 0x88 + (x)) /* Control Register 3 */ | ||
| 488 | #define UCR4(x) __REG( 0x8c + (x)) /* Control Register 4 */ | ||
| 489 | #define UFCR(x) __REG( 0x90 + (x)) /* FIFO Control Register */ | ||
| 490 | #define USR1(x) __REG( 0x94 + (x)) /* Status Register 1 */ | ||
| 491 | #define USR2(x) __REG( 0x98 + (x)) /* Status Register 2 */ | ||
| 492 | #define UESC(x) __REG( 0x9c + (x)) /* Escape Character Register */ | ||
| 493 | #define UTIM(x) __REG( 0xa0 + (x)) /* Escape Timer Register */ | ||
| 494 | #define UBIR(x) __REG( 0xa4 + (x)) /* BRM Incremental Register */ | ||
| 495 | #define UBMR(x) __REG( 0xa8 + (x)) /* BRM Modulator Register */ | ||
| 496 | #define UBRC(x) __REG( 0xac + (x)) /* Baud Rate Count Register */ | ||
| 497 | #define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */ | ||
| 498 | #define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */ | ||
| 499 | #define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */ | ||
| 500 | #define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */ | ||
| 501 | #define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */ | ||
| 502 | #define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */ | ||
| 503 | #define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */ | ||
| 504 | #define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */ | ||
| 505 | #define UTS(x) __REG( 0xd0 + (x)) /* UART Test Register */ | ||
| 506 | |||
| 507 | /* UART Control Register Bit Fields.*/ | ||
| 508 | #define URXD_CHARRDY (1<<15) | ||
| 509 | #define URXD_ERR (1<<14) | ||
| 510 | #define URXD_OVRRUN (1<<13) | ||
| 511 | #define URXD_FRMERR (1<<12) | ||
| 512 | #define URXD_BRK (1<<11) | ||
| 513 | #define URXD_PRERR (1<<10) | ||
| 514 | #define UCR1_ADEN (1<<15) /* Auto dectect interrupt */ | ||
| 515 | #define UCR1_ADBR (1<<14) /* Auto detect baud rate */ | ||
| 516 | #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */ | ||
| 517 | #define UCR1_IDEN (1<<12) /* Idle condition interrupt */ | ||
| 518 | #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */ | ||
| 519 | #define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */ | ||
| 520 | #define UCR1_IREN (1<<7) /* Infrared interface enable */ | ||
| 521 | #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */ | ||
| 522 | #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */ | ||
| 523 | #define UCR1_SNDBRK (1<<4) /* Send break */ | ||
| 524 | #define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */ | ||
| 525 | #define UCR1_UARTCLKEN (1<<2) /* UART clock enabled */ | ||
| 526 | #define UCR1_DOZE (1<<1) /* Doze */ | ||
| 527 | #define UCR1_UARTEN (1<<0) /* UART enabled */ | ||
| 528 | #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */ | ||
| 529 | #define UCR2_IRTS (1<<14) /* Ignore RTS pin */ | ||
| 530 | #define UCR2_CTSC (1<<13) /* CTS pin control */ | ||
| 531 | #define UCR2_CTS (1<<12) /* Clear to send */ | ||
| 532 | #define UCR2_ESCEN (1<<11) /* Escape enable */ | ||
| 533 | #define UCR2_PREN (1<<8) /* Parity enable */ | ||
| 534 | #define UCR2_PROE (1<<7) /* Parity odd/even */ | ||
| 535 | #define UCR2_STPB (1<<6) /* Stop */ | ||
| 536 | #define UCR2_WS (1<<5) /* Word size */ | ||
| 537 | #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */ | ||
| 538 | #define UCR2_TXEN (1<<2) /* Transmitter enabled */ | ||
| 539 | #define UCR2_RXEN (1<<1) /* Receiver enabled */ | ||
| 540 | #define UCR2_SRST (1<<0) /* SW reset */ | ||
| 541 | #define UCR3_DTREN (1<<13) /* DTR interrupt enable */ | ||
| 542 | #define UCR3_PARERREN (1<<12) /* Parity enable */ | ||
| 543 | #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */ | ||
| 544 | #define UCR3_DSR (1<<10) /* Data set ready */ | ||
| 545 | #define UCR3_DCD (1<<9) /* Data carrier detect */ | ||
| 546 | #define UCR3_RI (1<<8) /* Ring indicator */ | ||
| 547 | #define UCR3_TIMEOUTEN (1<<7) /* Timeout interrupt enable */ | ||
| 548 | #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */ | ||
| 549 | #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */ | ||
| 550 | #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */ | ||
| 551 | #define UCR3_REF25 (1<<3) /* Ref freq 25 MHz */ | ||
| 552 | #define UCR3_REF30 (1<<2) /* Ref Freq 30 MHz */ | ||
| 553 | #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */ | ||
| 554 | #define UCR3_BPEN (1<<0) /* Preset registers enable */ | ||
| 555 | #define UCR4_CTSTL_32 (32<<10) /* CTS trigger level (32 chars) */ | ||
| 556 | #define UCR4_INVR (1<<9) /* Inverted infrared reception */ | ||
| 557 | #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */ | ||
| 558 | #define UCR4_WKEN (1<<7) /* Wake interrupt enable */ | ||
| 559 | #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */ | ||
| 560 | #define UCR4_IRSC (1<<5) /* IR special case */ | ||
| 561 | #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */ | ||
| 562 | #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */ | ||
| 563 | #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */ | ||
| 564 | #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */ | ||
| 565 | #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */ | ||
| 566 | #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */ | ||
| 567 | #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */ | ||
| 568 | #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */ | ||
| 569 | #define USR1_RTSS (1<<14) /* RTS pin status */ | ||
| 570 | #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */ | ||
| 571 | #define USR1_RTSD (1<<12) /* RTS delta */ | ||
| 572 | #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */ | ||
| 573 | #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */ | ||
| 574 | #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */ | ||
| 575 | #define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */ | ||
| 576 | #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */ | ||
| 577 | #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */ | ||
| 578 | #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */ | ||
| 579 | #define USR2_ADET (1<<15) /* Auto baud rate detect complete */ | ||
| 580 | #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ | ||
| 581 | #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ | ||
| 582 | #define USR2_IDLE (1<<12) /* Idle condition */ | ||
| 583 | #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ | ||
| 584 | #define USR2_WAKE (1<<7) /* Wake */ | ||
| 585 | #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ | ||
| 586 | #define USR2_TXDC (1<<3) /* Transmitter complete */ | ||
| 587 | #define USR2_BRCD (1<<2) /* Break condition */ | ||
| 588 | #define USR2_ORE (1<<1) /* Overrun error */ | ||
| 589 | #define USR2_RDR (1<<0) /* Recv data ready */ | ||
| 590 | #define UTS_FRCPERR (1<<13) /* Force parity error */ | ||
| 591 | #define UTS_LOOP (1<<12) /* Loop tx and rx */ | ||
| 592 | #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */ | ||
| 593 | #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */ | ||
| 594 | #define UTS_TXFULL (1<<4) /* TxFIFO full */ | ||
| 595 | #define UTS_RXFULL (1<<3) /* RxFIFO full */ | ||
| 596 | #define UTS_SOFTRST (1<<0) /* Software reset */ | ||
| 597 | |||
| 598 | #endif // _IMX_REGS_H | 480 | #endif // _IMX_REGS_H |