diff options
Diffstat (limited to 'include/asm-arm/arch-epxa10db')
21 files changed, 1960 insertions, 0 deletions
diff --git a/include/asm-arm/arch-epxa10db/debug-macro.S b/include/asm-arm/arch-epxa10db/debug-macro.S new file mode 100644 index 000000000000..1d11c51f498f --- /dev/null +++ b/include/asm-arm/arch-epxa10db/debug-macro.S | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* linux/include/asm-arm/arch-epxa10db/debug-macro.S | ||
| 2 | * | ||
| 3 | * Debugging macro include header | ||
| 4 | * | ||
| 5 | * Copyright (C) 1994-1999 Russell King | ||
| 6 | * Moved from linux/arch/arm/kernel/debug.S by Ben Dooks | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License version 2 as | ||
| 10 | * published by the Free Software Foundation. | ||
| 11 | * | ||
| 12 | */ | ||
| 13 | |||
| 14 | #include <asm/arch/excalibur.h> | ||
| 15 | #define UART00_TYPE | ||
| 16 | #include <asm/arch/uart00.h> | ||
| 17 | |||
| 18 | .macro addruart,rx | ||
| 19 | mrc p15, 0, \rx, c1, c0 | ||
| 20 | tst \rx, #1 @ MMU enabled? | ||
| 21 | ldr \rx, =EXC_UART00_BASE @ physical base address | ||
| 22 | orrne \rx, \rx, #0xff000000 @ virtual base | ||
| 23 | orrne \rx, \rx, #0x00f00000 | ||
| 24 | .endm | ||
| 25 | |||
| 26 | .macro senduart,rd,rx | ||
| 27 | str \rd, [\rx, #UART_TD(0)] | ||
| 28 | .endm | ||
| 29 | |||
| 30 | .macro waituart,rd,rx | ||
| 31 | 1001: ldr \rd, [\rx, #UART_TSR(0)] | ||
| 32 | and \rd, \rd, #UART_TSR_TX_LEVEL_MSK | ||
| 33 | cmp \rd, #15 | ||
| 34 | beq 1001b | ||
| 35 | .endm | ||
| 36 | |||
| 37 | .macro busyuart,rd,rx | ||
| 38 | 1001: ldr \rd, [\rx, #UART_TSR(0)] | ||
| 39 | ands \rd, \rd, #UART_TSR_TX_LEVEL_MSK | ||
| 40 | bne 1001b | ||
| 41 | .endm | ||
diff --git a/include/asm-arm/arch-epxa10db/dma.h b/include/asm-arm/arch-epxa10db/dma.h new file mode 100644 index 000000000000..5d97734d1077 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/dma.h | |||
| @@ -0,0 +1,28 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-camelot/dma.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1997,1998 Russell King | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_DMA_H | ||
| 21 | #define __ASM_ARCH_DMA_H | ||
| 22 | |||
| 23 | #define MAX_DMA_ADDRESS 0xffffffff | ||
| 24 | |||
| 25 | #define MAX_DMA_CHANNELS 0 | ||
| 26 | |||
| 27 | #endif /* _ASM_ARCH_DMA_H */ | ||
| 28 | |||
diff --git a/include/asm-arm/arch-epxa10db/entry-macro.S b/include/asm-arm/arch-epxa10db/entry-macro.S new file mode 100644 index 000000000000..de6ae08334e2 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/entry-macro.S | |||
| @@ -0,0 +1,25 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-epxa10db/entry-macro.S | ||
| 3 | * | ||
| 4 | * Low-level IRQ helper macros for epxa10db platform | ||
| 5 | * | ||
| 6 | * This file is licensed under the terms of the GNU General Public | ||
| 7 | * License version 2. This program is licensed "as is" without any | ||
| 8 | * warranty of any kind, whether express or implied. | ||
| 9 | */ | ||
| 10 | #include <asm/arch/platform.h> | ||
| 11 | #undef IRQ_MODE /* same name defined in asm/proc/ptrace.h */ | ||
| 12 | #include <asm/arch/int_ctrl00.h> | ||
| 13 | |||
| 14 | .macro disable_fiq | ||
| 15 | .endm | ||
| 16 | |||
| 17 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | ||
| 18 | |||
| 19 | ldr \irqstat, =INT_ID(IO_ADDRESS(EXC_INT_CTRL00_BASE)) | ||
| 20 | ldr \irqnr,[\irqstat] | ||
| 21 | cmp \irqnr,#0 | ||
| 22 | subne \irqnr,\irqnr,#1 | ||
| 23 | |||
| 24 | .endm | ||
| 25 | |||
diff --git a/include/asm-arm/arch-epxa10db/ether00.h b/include/asm-arm/arch-epxa10db/ether00.h new file mode 100644 index 000000000000..b737b8aabe2f --- /dev/null +++ b/include/asm-arm/arch-epxa10db/ether00.h | |||
| @@ -0,0 +1,482 @@ | |||
| 1 | #ifndef __ETHER00_H | ||
| 2 | #define __ETHER00_H | ||
| 3 | |||
| 4 | |||
| 5 | |||
| 6 | /* | ||
| 7 | * Register definitions for the Ethernet MAC | ||
| 8 | */ | ||
| 9 | |||
| 10 | /* | ||
| 11 | * Copyright (c) Altera Corporation 2000. | ||
| 12 | * All rights reserved. | ||
| 13 | */ | ||
| 14 | |||
| 15 | /* | ||
| 16 | * Structures for the DMA controller | ||
| 17 | */ | ||
| 18 | typedef struct fda_desc | ||
| 19 | { | ||
| 20 | struct fda_desc * FDNext; | ||
| 21 | long FDSystem; | ||
| 22 | long FDStat; | ||
| 23 | short FDLength; | ||
| 24 | short FDCtl; | ||
| 25 | }FDA_DESC; | ||
| 26 | |||
| 27 | typedef struct buf_desc | ||
| 28 | { | ||
| 29 | char * BuffData; | ||
| 30 | short BuffLength; | ||
| 31 | char BDStat; | ||
| 32 | char BDCtl; | ||
| 33 | }BUF_DESC; | ||
| 34 | |||
| 35 | /* | ||
| 36 | * Control masks for the DMA controller | ||
| 37 | */ | ||
| 38 | #define FDCTL_BDCOUNT_MSK (0x1F) | ||
| 39 | #define FDCTL_BDCOUNT_OFST (0) | ||
| 40 | #define FDCTL_FRMOPT_MSK (0x7C00) | ||
| 41 | #define FDCTL_FRMOPT_OFST (10) | ||
| 42 | #define FDCTL_COWNSFD_MSK (0x8000) | ||
| 43 | #define FDCTL_COWNSFD_OFST (15) | ||
| 44 | |||
| 45 | #define BDCTL_RXBDSEQN_MSK (0x7F) | ||
| 46 | #define BDCTL_RXBDSEQN_OFST (0) | ||
| 47 | #define BDCTL_COWNSBD_MSK (0x80) | ||
| 48 | #define BDCTL_COWNSBD_OFST (7) | ||
| 49 | |||
| 50 | #define FDNEXT_EOL_MSK (0x1) | ||
| 51 | #define FDNEXT_EOL_OFST (0) | ||
| 52 | #define FDNEXT_EOL_POINTER_MSK (0xFFFFFFF0) | ||
| 53 | #define FDNEXT_EOL_POINTER_OFST (4) | ||
| 54 | |||
| 55 | #define ETHER_ARC_SIZE (21) | ||
| 56 | |||
| 57 | /* | ||
| 58 | * Register definitions and masks | ||
| 59 | */ | ||
| 60 | #define ETHER_DMA_CTL(base) (ETHER00_TYPE (base + 0x100)) | ||
| 61 | #define ETHER_DMA_CTL_DMBURST_OFST (2) | ||
| 62 | #define ETHER_DMA_CTL_DMBURST_MSK (0x1FC) | ||
| 63 | #define ETHER_DMA_CTL_POWRMGMNT_OFST (11) | ||
| 64 | #define ETHER_DMA_CTL_POWRMGMNT_MSK (0x1000) | ||
| 65 | #define ETHER_DMA_CTL_TXBIGE_OFST (14) | ||
| 66 | #define ETHER_DMA_CTL_TXBIGE_MSK (0x4000) | ||
| 67 | #define ETHER_DMA_CTL_RXBIGE_OFST (15) | ||
| 68 | #define ETHER_DMA_CTL_RXBIGE_MSK (0x8000) | ||
| 69 | #define ETHER_DMA_CTL_TXWAKEUP_OFST (16) | ||
| 70 | #define ETHER_DMA_CTL_TXWAKEUP_MSK (0x10000) | ||
| 71 | #define ETHER_DMA_CTL_SWINTREQ_OFST (17) | ||
| 72 | #define ETHER_DMA_CTL_SWINTREQ_MSK (0x20000) | ||
| 73 | #define ETHER_DMA_CTL_INTMASK_OFST (18) | ||
| 74 | #define ETHER_DMA_CTL_INTMASK_MSK (0x40000) | ||
| 75 | #define ETHER_DMA_CTL_M66ENSTAT_OFST (19) | ||
| 76 | #define ETHER_DMA_CTL_M66ENSTAT_MSK (0x80000) | ||
| 77 | #define ETHER_DMA_CTL_RMTXINIT_OFST (20) | ||
| 78 | #define ETHER_DMA_CTL_RMTXINIT_MSK (0x100000) | ||
| 79 | #define ETHER_DMA_CTL_RMRXINIT_OFST (21) | ||
| 80 | #define ETHER_DMA_CTL_RMRXINIT_MSK (0x200000) | ||
| 81 | #define ETHER_DMA_CTL_RXALIGN_OFST (22) | ||
| 82 | #define ETHER_DMA_CTL_RXALIGN_MSK (0xC00000) | ||
| 83 | #define ETHER_DMA_CTL_RMSWRQ_OFST (24) | ||
| 84 | #define ETHER_DMA_CTL_RMSWRQ_MSK (0x1000000) | ||
| 85 | #define ETHER_DMA_CTL_RMEMBANK_OFST (25) | ||
| 86 | #define ETHER_DMA_CTL_RMEMBANK_MSK (0x2000000) | ||
| 87 | |||
| 88 | #define ETHER_TXFRMPTR(base) (ETHER00_TYPE (base + 0x104)) | ||
| 89 | |||
| 90 | #define ETHER_TXTHRSH(base) (ETHER00_TYPE (base + 0x308)) | ||
| 91 | |||
| 92 | #define ETHER_TXPOLLCTR(base) (ETHER00_TYPE (base + 0x30c)) | ||
| 93 | |||
| 94 | #define ETHER_BLFRMPTR(base) (ETHER00_TYPE (base + 0x110)) | ||
| 95 | #define ETHER_BLFFRMPTR_EOL_OFST (0) | ||
| 96 | #define ETHER_BLFFRMPTR_EOL_MSK (0x1) | ||
| 97 | #define ETHER_BLFFRMPTR_ADDRESS_OFST (4) | ||
| 98 | #define ETHER_BLFFRMPTR_ADDRESS_MSK (0xFFFFFFF0) | ||
| 99 | |||
| 100 | #define ETHER_RXFRAGSIZE(base) (ETHER00_TYPE (base + 0x114)) | ||
| 101 | #define ETHER_RXFRAGSIZE_MINFRAG_OFST (2) | ||
| 102 | #define ETHER_RXFRAGSIZE_MINFRAG_MSK (0xFFC) | ||
| 103 | #define ETHER_RXFRAGSIZE_ENPACK_OFST (15) | ||
| 104 | #define ETHER_RXFRAGSIZE_ENPACK_MSK (0x8000) | ||
| 105 | |||
| 106 | #define ETHER_INT_EN(base) (ETHER00_TYPE (base + 0x118)) | ||
| 107 | #define ETHER_INT_EN_FDAEXEN_OFST (0) | ||
| 108 | #define ETHER_INT_EN_FDAEXEN_MSK (0x1) | ||
| 109 | #define ETHER_INT_EN_BLEXEN_OFST (1) | ||
| 110 | #define ETHER_INT_EN_BLEXN_MSK (0x2) | ||
| 111 | #define ETHER_INT_EN_STARGABTEN_OFST (2) | ||
| 112 | #define ETHER_INT_EN_STARGABTEN_MSK (0x4) | ||
| 113 | #define ETHER_INT_EN_RTARGABTEN_OFST (3) | ||
| 114 | #define ETHER_INT_EN_RTARGABTEN_MSK (0x8) | ||
| 115 | #define ETHER_INT_EN_RMASABTEN_OFST (4) | ||
| 116 | #define ETHER_INT_EN_RMASABTEN_MSK (0x10) | ||
| 117 | #define ETHER_INT_EN_SSYSERREN_OFST (5) | ||
| 118 | #define ETHER_INT_EN_SSYSERREN_MSK (0x20) | ||
| 119 | #define ETHER_INT_EN_DPARERREN_OFST (6) | ||
| 120 | #define ETHER_INT_EN_DPARERREN_MSK (0x40) | ||
| 121 | #define ETHER_INT_EN_EARNOTEN_OFST (7) | ||
| 122 | #define ETHER_INT_EN_EARNOTEN_MSK (0x80) | ||
| 123 | #define ETHER_INT_EN_DPARDEN_OFST (8) | ||
| 124 | #define ETHER_INT_EN_DPARDEN_MSK (0x100) | ||
| 125 | #define ETHER_INT_EN_DMPARERREN_OFST (9) | ||
| 126 | #define ETHER_INT_EN_DMPARERREN_MSK (0x200) | ||
| 127 | #define ETHER_INT_EN_TXCTLCMPEN_OFST (10) | ||
| 128 | #define ETHER_INT_EN_TXCTLCMPEN_MSK (0x400) | ||
| 129 | #define ETHER_INT_EN_NRABTEN_OFST (11) | ||
| 130 | #define ETHER_INT_EN_NRABTEN_MSK (0x800) | ||
| 131 | |||
| 132 | #define ETHER_FDA_BAS(base) (ETHER00_TYPE (base + 0x11C)) | ||
| 133 | #define ETHER_FDA_BAS_ADDRESS_OFST (4) | ||
| 134 | #define ETHER_FDA_BAS_ADDRESS_MSK (0xFFFFFFF0) | ||
| 135 | |||
| 136 | #define ETHER_FDA_LIM(base) (ETHER00_TYPE (base + 0x120)) | ||
| 137 | #define ETHER_FDA_LIM_COUNT_OFST (4) | ||
| 138 | #define ETHER_FDA_LIM_COUNT_MSK (0xFFF0) | ||
| 139 | |||
| 140 | #define ETHER_INT_SRC(base) (ETHER00_TYPE (base + 0x124)) | ||
| 141 | #define ETHER_INT_SRC_INTMACTX_OFST (0) | ||
| 142 | #define ETHER_INT_SRC_INTMACTX_MSK (0x1) | ||
| 143 | #define ETHER_INT_SRC_INTMACRX_OFST (1) | ||
| 144 | #define ETHER_INT_SRC_INTMACRX_MSK (0x2) | ||
| 145 | #define ETHER_INT_SRC_INTSBUS_OFST (2) | ||
| 146 | #define ETHER_INT_SRC_INTSBUS_MSK (0x4) | ||
| 147 | #define ETHER_INT_SRC_INTFDAEX_OFST (3) | ||
| 148 | #define ETHER_INT_SRC_INTFDAEX_MSK (0x8) | ||
| 149 | #define ETHER_INT_SRC_INTBLEX_OFST (4) | ||
| 150 | #define ETHER_INT_SRC_INTBLEX_MSK (0x10) | ||
| 151 | #define ETHER_INT_SRC_SWINT_OFST (5) | ||
| 152 | #define ETHER_INT_SRC_SWINT_MSK (0x20) | ||
| 153 | #define ETHER_INT_SRC_INTEARNOT_OFST (6) | ||
| 154 | #define ETHER_INT_SRC_INTEARNOT_MSK (0x40) | ||
| 155 | #define ETHER_INT_SRC_DMPARERR_OFST (7) | ||
| 156 | #define ETHER_INT_SRC_DMPARERR_MSK (0x80) | ||
| 157 | #define ETHER_INT_SRC_INTEXBD_OFST (8) | ||
| 158 | #define ETHER_INT_SRC_INTEXBD_MSK (0x100) | ||
| 159 | #define ETHER_INT_SRC_INTTXCTLCMP_OFST (9) | ||
| 160 | #define ETHER_INT_SRC_INTTXCTLCMP_MSK (0x200) | ||
| 161 | #define ETHER_INT_SRC_INTNRABT_OFST (10) | ||
| 162 | #define ETHER_INT_SRC_INTNRABT_MSK (0x400) | ||
| 163 | #define ETHER_INT_SRC_FDAEX_OFST (11) | ||
| 164 | #define ETHER_INT_SRC_FDAEX_MSK (0x800) | ||
| 165 | #define ETHER_INT_SRC_BLEX_OFST (12) | ||
| 166 | #define ETHER_INT_SRC_BLEX_MSK (0x1000) | ||
| 167 | #define ETHER_INT_SRC_DMPARERRSTAT_OFST (13) | ||
| 168 | #define ETHER_INT_SRC_DMPARERRSTAT_MSK (0x2000) | ||
| 169 | #define ETHER_INT_SRC_NRABT_OFST (14) | ||
| 170 | #define ETHER_INT_SRC_NRABT_MSK (0x4000) | ||
| 171 | #define ETHER_INT_SRC_INTLINK_OFST (15) | ||
| 172 | #define ETHER_INT_SRC_INTLINK_MSK (0x8000) | ||
| 173 | #define ETHER_INT_SRC_INTEXDEFER_OFST (16) | ||
| 174 | #define ETHER_INT_SRC_INTEXDEFER_MSK (0x10000) | ||
| 175 | #define ETHER_INT_SRC_INTRMON_OFST (17) | ||
| 176 | #define ETHER_INT_SRC_INTRMON_MSK (0x20000) | ||
| 177 | #define ETHER_INT_SRC_IRQ_MSK (0x83FF) | ||
| 178 | |||
| 179 | #define ETHER_PAUSECNT(base) (ETHER00_TYPE (base + 0x40)) | ||
| 180 | #define ETHER_PAUSECNT_COUNT_OFST (0) | ||
| 181 | #define ETHER_PAUSECNT_COUNT_MSK (0xFFFF) | ||
| 182 | |||
| 183 | #define ETHER_REMPAUCNT(base) (ETHER00_TYPE (base + 0x44)) | ||
| 184 | #define ETHER_REMPAUCNT_COUNT_OFST (0) | ||
| 185 | #define ETHER_REMPAUCNT_COUNT_MSK (0xFFFF) | ||
| 186 | |||
| 187 | #define ETHER_TXCONFRMSTAT(base) (ETHER00_TYPE (base + 0x348)) | ||
| 188 | #define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_OFST (0) | ||
| 189 | #define ETHER_TXCONFRMSTAT_TS_STAT_VALUE_MSK (0x3FFFFF) | ||
| 190 | |||
| 191 | #define ETHER_MAC_CTL(base) (ETHER00_TYPE (base + 0)) | ||
| 192 | #define ETHER_MAC_CTL_HALTREQ_OFST (0) | ||
| 193 | #define ETHER_MAC_CTL_HALTREQ_MSK (0x1) | ||
| 194 | #define ETHER_MAC_CTL_HALTIMM_OFST (1) | ||
| 195 | #define ETHER_MAC_CTL_HALTIMM_MSK (0x2) | ||
| 196 | #define ETHER_MAC_CTL_RESET_OFST (2) | ||
| 197 | #define ETHER_MAC_CTL_RESET_MSK (0x4) | ||
| 198 | #define ETHER_MAC_CTL_FULLDUP_OFST (3) | ||
| 199 | #define ETHER_MAC_CTL_FULLDUP_MSK (0x8) | ||
| 200 | #define ETHER_MAC_CTL_MACLOOP_OFST (4) | ||
| 201 | #define ETHER_MAC_CTL_MACLOOP_MSK (0x10) | ||
| 202 | #define ETHER_MAC_CTL_CONN_OFST (5) | ||
| 203 | #define ETHER_MAC_CTL_CONN_MSK (0x60) | ||
| 204 | #define ETHER_MAC_CTL_LOOP10_OFST (7) | ||
| 205 | #define ETHER_MAC_CTL_LOOP10_MSK (0x80) | ||
| 206 | #define ETHER_MAC_CTL_LNKCHG_OFST (8) | ||
| 207 | #define ETHER_MAC_CTL_LNKCHG_MSK (0x100) | ||
| 208 | #define ETHER_MAC_CTL_MISSROLL_OFST (10) | ||
| 209 | #define ETHER_MAC_CTL_MISSROLL_MSK (0x400) | ||
| 210 | #define ETHER_MAC_CTL_ENMISSROLL_OFST (13) | ||
| 211 | #define ETHER_MAC_CTL_ENMISSROLL_MSK (0x2000) | ||
| 212 | #define ETHER_MAC_CTL_LINK10_OFST (15) | ||
| 213 | #define ETHER_MAC_CTL_LINK10_MSK (0x8000) | ||
| 214 | |||
| 215 | #define ETHER_ARC_CTL(base) (ETHER00_TYPE (base + 0x4)) | ||
| 216 | #define ETHER_ARC_CTL_STATIONACC_OFST (0) | ||
| 217 | #define ETHER_ARC_CTL_STATIONACC_MSK (0x1) | ||
| 218 | #define ETHER_ARC_CTL_GROUPACC_OFST (1) | ||
| 219 | #define ETHER_ARC_CTL_GROUPACC_MSK (0x2) | ||
| 220 | #define ETHER_ARC_CTL_BROADACC_OFST (2) | ||
| 221 | #define ETHER_ARC_CTL_BROADACC_MSK (0x4) | ||
| 222 | #define ETHER_ARC_CTL_NEGARC_OFST (3) | ||
| 223 | #define ETHER_ARC_CTL_NEGARC_MSK (0x8) | ||
| 224 | #define ETHER_ARC_CTL_COMPEN_OFST (4) | ||
| 225 | #define ETHER_ARC_CTL_COMPEN_MSK (0x10) | ||
| 226 | |||
| 227 | #define ETHER_TX_CTL(base) (ETHER00_TYPE (base + 0x8)) | ||
| 228 | #define ETHER_TX_CTL_TXEN_OFST (0) | ||
| 229 | #define ETHER_TX_CTL_TXEN_MSK (0x1) | ||
| 230 | #define ETHER_TX_CTL_TXHALT_OFST (1) | ||
| 231 | #define ETHER_TX_CTL_TXHALT_MSK (0x2) | ||
| 232 | #define ETHER_TX_CTL_NOPAD_OFST (2) | ||
| 233 | #define ETHER_TX_CTL_NOPAD_MSK (0x4) | ||
| 234 | #define ETHER_TX_CTL_NOCRC_OFST (3) | ||
| 235 | #define ETHER_TX_CTL_NOCRC_MSK (0x8) | ||
| 236 | #define ETHER_TX_CTL_FBACK_OFST (4) | ||
| 237 | #define ETHER_TX_CTL_FBACK_MSK (0x10) | ||
| 238 | #define ETHER_TX_CTL_NOEXDEF_OFST (5) | ||
| 239 | #define ETHER_TX_CTL_NOEXDEF_MSK (0x20) | ||
| 240 | #define ETHER_TX_CTL_SDPAUSE_OFST (6) | ||
| 241 | #define ETHER_TX_CTL_SDPAUSE_MSK (0x40) | ||
| 242 | #define ETHER_TX_CTL_MII10_OFST (7) | ||
| 243 | #define ETHER_TX_CTL_MII10_MSK (0x80) | ||
| 244 | #define ETHER_TX_CTL_ENUNDER_OFST (8) | ||
| 245 | #define ETHER_TX_CTL_ENUNDER_MSK (0x100) | ||
| 246 | #define ETHER_TX_CTL_ENEXDEFER_OFST (9) | ||
| 247 | #define ETHER_TX_CTL_ENEXDEFER_MSK (0x200) | ||
| 248 | #define ETHER_TX_CTL_ENLCARR_OFST (10) | ||
| 249 | #define ETHER_TX_CTL_ENLCARR_MSK (0x400) | ||
| 250 | #define ETHER_TX_CTL_ENEXCOLL_OFST (11) | ||
| 251 | #define ETHER_TX_CTL_ENEXCOLL_MSK (0x800) | ||
| 252 | #define ETHER_TX_CTL_ENLATECOLL_OFST (12) | ||
| 253 | #define ETHER_TX_CTL_ENLATECOLL_MSK (0x1000) | ||
| 254 | #define ETHER_TX_CTL_ENTXPAR_OFST (13) | ||
| 255 | #define ETHER_TX_CTL_ENTXPAR_MSK (0x2000) | ||
| 256 | #define ETHER_TX_CTL_ENCOMP_OFST (14) | ||
| 257 | #define ETHER_TX_CTL_ENCOMP_MSK (0x4000) | ||
| 258 | |||
| 259 | #define ETHER_TX_STAT(base) (ETHER00_TYPE (base + 0xc)) | ||
| 260 | #define ETHER_TX_STAT_TXCOLL_OFST (0) | ||
| 261 | #define ETHER_TX_STAT_TXCOLL_MSK (0xF) | ||
| 262 | #define ETHER_TX_STAT_EXCOLL_OFST (4) | ||
| 263 | #define ETHER_TX_STAT_EXCOLL_MSK (0x10) | ||
| 264 | #define ETHER_TX_STAT_TXDEFER_OFST (5) | ||
| 265 | #define ETHER_TX_STAT_TXDEFER_MSK (0x20) | ||
| 266 | #define ETHER_TX_STAT_PAUSED_OFST (6) | ||
| 267 | #define ETHER_TX_STAT_PAUSED_MSK (0x40) | ||
| 268 | #define ETHER_TX_STAT_INTTX_OFST (7) | ||
| 269 | #define ETHER_TX_STAT_INTTX_MSK (0x80) | ||
| 270 | #define ETHER_TX_STAT_UNDER_OFST (8) | ||
| 271 | #define ETHER_TX_STAT_UNDER_MSK (0x100) | ||
| 272 | #define ETHER_TX_STAT_EXDEFER_OFST (9) | ||
| 273 | #define ETHER_TX_STAT_EXDEFER_MSK (0x200) | ||
| 274 | #define ETHER_TX_STAT_LCARR_OFST (10) | ||
| 275 | #define ETHER_TX_STAT_LCARR_MSK (0x400) | ||
| 276 | #define ETHER_TX_STAT_TX10STAT_OFST (11) | ||
| 277 | #define ETHER_TX_STAT_TX10STAT_MSK (0x800) | ||
| 278 | #define ETHER_TX_STAT_LATECOLL_OFST (12) | ||
| 279 | #define ETHER_TX_STAT_LATECOLL_MSK (0x1000) | ||
| 280 | #define ETHER_TX_STAT_TXPAR_OFST (13) | ||
| 281 | #define ETHER_TX_STAT_TXPAR_MSK (0x2000) | ||
| 282 | #define ETHER_TX_STAT_COMP_OFST (14) | ||
| 283 | #define ETHER_TX_STAT_COMP_MSK (0x4000) | ||
| 284 | #define ETHER_TX_STAT_TXHALTED_OFST (15) | ||
| 285 | #define ETHER_TX_STAT_TXHALTED_MSK (0x8000) | ||
| 286 | #define ETHER_TX_STAT_SQERR_OFST (16) | ||
| 287 | #define ETHER_TX_STAT_SQERR_MSK (0x10000) | ||
| 288 | #define ETHER_TX_STAT_TXMCAST_OFST (17) | ||
| 289 | #define ETHER_TX_STAT_TXMCAST_MSK (0x20000) | ||
| 290 | #define ETHER_TX_STAT_TXBCAST_OFST (18) | ||
| 291 | #define ETHER_TX_STAT_TXBCAST_MSK (0x40000) | ||
| 292 | #define ETHER_TX_STAT_VLAN_OFST (19) | ||
| 293 | #define ETHER_TX_STAT_VLAN_MSK (0x80000) | ||
| 294 | #define ETHER_TX_STAT_MACC_OFST (20) | ||
| 295 | #define ETHER_TX_STAT_MACC_MSK (0x100000) | ||
| 296 | #define ETHER_TX_STAT_TXPAUSE_OFST (21) | ||
| 297 | #define ETHER_TX_STAT_TXPAUSE_MSK (0x200000) | ||
| 298 | |||
| 299 | #define ETHER_RX_CTL(base) (ETHER00_TYPE (base + 0x10)) | ||
| 300 | #define ETHER_RX_CTL_RXEN_OFST (0) | ||
| 301 | #define ETHER_RX_CTL_RXEN_MSK (0x1) | ||
| 302 | #define ETHER_RX_CTL_RXHALT_OFST (1) | ||
| 303 | #define ETHER_RX_CTL_RXHALT_MSK (0x2) | ||
| 304 | #define ETHER_RX_CTL_LONGEN_OFST (2) | ||
| 305 | #define ETHER_RX_CTL_LONGEN_MSK (0x4) | ||
| 306 | #define ETHER_RX_CTL_SHORTEN_OFST (3) | ||
| 307 | #define ETHER_RX_CTL_SHORTEN_MSK (0x8) | ||
| 308 | #define ETHER_RX_CTL_STRIPCRC_OFST (4) | ||
| 309 | #define ETHER_RX_CTL_STRIPCRC_MSK (0x10) | ||
| 310 | #define ETHER_RX_CTL_PASSCTL_OFST (5) | ||
| 311 | #define ETHER_RX_CTL_PASSCTL_MSK (0x20) | ||
| 312 | #define ETHER_RX_CTL_IGNORECRC_OFST (6) | ||
| 313 | #define ETHER_RX_CTL_IGNORECRC_MSK (0x40) | ||
| 314 | #define ETHER_RX_CTL_ENALIGN_OFST (8) | ||
| 315 | #define ETHER_RX_CTL_ENALIGN_MSK (0x100) | ||
| 316 | #define ETHER_RX_CTL_ENCRCERR_OFST (9) | ||
| 317 | #define ETHER_RX_CTL_ENCRCERR_MSK (0x200) | ||
| 318 | #define ETHER_RX_CTL_ENOVER_OFST (10) | ||
| 319 | #define ETHER_RX_CTL_ENOVER_MSK (0x400) | ||
| 320 | #define ETHER_RX_CTL_ENLONGERR_OFST (11) | ||
| 321 | #define ETHER_RX_CTL_ENLONGERR_MSK (0x800) | ||
| 322 | #define ETHER_RX_CTL_ENRXPAR_OFST (13) | ||
| 323 | #define ETHER_RX_CTL_ENRXPAR_MSK (0x2000) | ||
| 324 | #define ETHER_RX_CTL_ENGOOD_OFST (14) | ||
| 325 | #define ETHER_RX_CTL_ENGOOD_MSK (0x4000) | ||
| 326 | |||
| 327 | #define ETHER_RX_STAT(base) (ETHER00_TYPE (base + 0x14)) | ||
| 328 | #define ETHER_RX_STAT_LENERR_OFST (4) | ||
| 329 | #define ETHER_RX_STAT_LENERR_MSK (0x10) | ||
| 330 | #define ETHER_RX_STAT_CTLRECD_OFST (5) | ||
| 331 | #define ETHER_RX_STAT_CTLRECD_MSK (0x20) | ||
| 332 | #define ETHER_RX_STAT_INTRX_OFST (6) | ||
| 333 | #define ETHER_RX_STAT_INTRX_MSK (0x40) | ||
| 334 | #define ETHER_RX_STAT_RX10STAT_OFST (7) | ||
| 335 | #define ETHER_RX_STAT_RX10STAT_MSK (0x80) | ||
| 336 | #define ETHER_RX_STAT_ALIGNERR_OFST (8) | ||
| 337 | #define ETHER_RX_STAT_ALIGNERR_MSK (0x100) | ||
| 338 | #define ETHER_RX_STAT_CRCERR_OFST (9) | ||
| 339 | #define ETHER_RX_STAT_CRCERR_MSK (0x200) | ||
| 340 | #define ETHER_RX_STAT_OVERFLOW_OFST (10) | ||
| 341 | #define ETHER_RX_STAT_OVERFLOW_MSK (0x400) | ||
| 342 | #define ETHER_RX_STAT_LONGERR_OFST (11) | ||
| 343 | #define ETHER_RX_STAT_LONGERR_MSK (0x800) | ||
| 344 | #define ETHER_RX_STAT_RXPAR_OFST (13) | ||
| 345 | #define ETHER_RX_STAT_RXPAR_MSK (0x2000) | ||
| 346 | #define ETHER_RX_STAT_GOOD_OFST (14) | ||
| 347 | #define ETHER_RX_STAT_GOOD_MSK (0x4000) | ||
| 348 | #define ETHER_RX_STAT_RXHALTED_OFST (15) | ||
| 349 | #define ETHER_RX_STAT_RXHALTED_MSK (0x8000) | ||
| 350 | #define ETHER_RX_STAT_RXMCAST_OFST (17) | ||
| 351 | #define ETHER_RX_STAT_RXMCAST_MSK (0x10000) | ||
| 352 | #define ETHER_RX_STAT_RXBCAST_OFST (18) | ||
| 353 | #define ETHER_RX_STAT_RXBCAST_MSK (0x20000) | ||
| 354 | #define ETHER_RX_STAT_RXVLAN_OFST (19) | ||
| 355 | #define ETHER_RX_STAT_RXVLAN_MSK (0x40000) | ||
| 356 | #define ETHER_RX_STAT_RXPAUSE_OFST (20) | ||
| 357 | #define ETHER_RX_STAT_RXPAUSE_MSK (0x80000) | ||
| 358 | #define ETHER_RX_STAT_ARCSTATUS_OFST (21) | ||
| 359 | #define ETHER_RX_STAT_ARCSTATUS_MSK (0xF00000) | ||
| 360 | #define ETHER_RX_STAT_ARCENT_OFST (25) | ||
| 361 | #define ETHER_RX_STAT_ARCENT_MSK (0x1F000000) | ||
| 362 | |||
| 363 | #define ETHER_MD_DATA(base) (ETHER00_TYPE (base + 0x18)) | ||
| 364 | |||
| 365 | #define ETHER_MD_CA(base) (ETHER00_TYPE (base + 0x1c)) | ||
| 366 | #define ETHER_MD_CA_ADDR_OFST (0) | ||
| 367 | #define ETHER_MD_CA_ADDR_MSK (0x1F) | ||
| 368 | #define ETHER_MD_CA_PHY_OFST (5) | ||
| 369 | #define ETHER_MD_CA_PHY_MSK (0x3E0) | ||
| 370 | #define ETHER_MD_CA_WR_OFST (10) | ||
| 371 | #define ETHER_MD_CA_WR_MSK (0x400) | ||
| 372 | #define ETHER_MD_CA_BUSY_OFST (11) | ||
| 373 | #define ETHER_MD_CA_BUSY_MSK (0x800) | ||
| 374 | #define ETHER_MD_CA_PRESUPP_OFST (12) | ||
| 375 | #define ETHER_MD_CA_PRESUPP_MSK (0x1000) | ||
| 376 | |||
| 377 | #define ETHER_ARC_ADR(base) (ETHER00_TYPE (base + 0x160)) | ||
| 378 | #define ETHER_ARC_ADR_ARC_LOC_OFST (2) | ||
| 379 | #define ETHER_ARC_ADR_ARC_LOC_MSK (0xFFC) | ||
| 380 | |||
| 381 | #define ETHER_ARC_DATA(base) (ETHER00_TYPE (base + 0x364)) | ||
| 382 | |||
| 383 | #define ETHER_ARC_ENA(base) (ETHER00_TYPE (base + 0x28)) | ||
| 384 | #define ETHER_ARC_ENA_MSK (0x1FFFFF) | ||
| 385 | |||
| 386 | #define ETHER_PROM_CTL(base) (ETHER00_TYPE (base + 0x2c)) | ||
| 387 | #define ETHER_PROM_CTL_PROM_ADDR_OFST (0) | ||
| 388 | #define ETHER_PROM_CTL_PROM_ADDR_MSK (0x3F) | ||
| 389 | #define ETHER_PROM_CTL_OPCODE_OFST (13) | ||
| 390 | #define ETHER_PROM_CTL_OPCODE_MSK (0x6000) | ||
| 391 | #define ETHER_PROM_CTL_OPCODE_READ_MSK (0x4000) | ||
| 392 | #define ETHER_PROM_CTL_OPCODE_WRITE_MSK (0x2000) | ||
| 393 | #define ETHER_PROM_CTL_OPCODE_ERASE_MSK (0x6000) | ||
| 394 | #define ETHER_PROM_CTL_ENABLE_MSK (0x0030) | ||
| 395 | #define ETHER_PROM_CTL_DISABLE_MSK (0x0000) | ||
| 396 | #define ETHER_PROM_CTL_BUSY_OFST (15) | ||
| 397 | #define ETHER_PROM_CTL_BUSY_MSK (0x8000) | ||
| 398 | |||
| 399 | #define ETHER_PROM_DATA(base) (ETHER00_TYPE (base + 0x30)) | ||
| 400 | |||
| 401 | #define ETHER_MISS_CNT(base) (ETHER00_TYPE (base + 0x3c)) | ||
| 402 | #define ETHER_MISS_CNT_COUNT_OFST (0) | ||
| 403 | #define ETHER_MISS_CNT_COUNT_MSK (0xFFFF) | ||
| 404 | |||
| 405 | #define ETHER_CNTDATA(base) (ETHER00_TYPE (base + 0x80)) | ||
| 406 | |||
| 407 | #define ETHER_CNTACC(base) (ETHER00_TYPE (base + 0x84)) | ||
| 408 | #define ETHER_CNTACC_ADDR_OFST (0) | ||
| 409 | #define ETHER_CNTACC_ADDR_MSK (0xFF) | ||
| 410 | #define ETHER_CNTACC_WRRDN_OFST (8) | ||
| 411 | #define ETHER_CNTACC_WRRDN_MSK (0x100) | ||
| 412 | #define ETHER_CNTACC_CLEAR_OFST (9) | ||
| 413 | #define ETHER_CNTACC_CLEAR_MSK (0x200) | ||
| 414 | |||
| 415 | #define ETHER_TXRMINTEN(base) (ETHER00_TYPE (base + 0x88)) | ||
| 416 | #define ETHER_TXRMINTEN_MSK (0x3FFFFFFF) | ||
| 417 | |||
| 418 | #define ETHER_RXRMINTEN(base) (ETHER00_TYPE (base + 0x8C)) | ||
| 419 | #define ETHER_RXRMINTEN_MSK (0xFFFFFF) | ||
| 420 | |||
| 421 | /* | ||
| 422 | * RMON Registers | ||
| 423 | */ | ||
| 424 | #define RMON_COLLISION0 0x0 | ||
| 425 | #define RMON_COLLISION1 0x1 | ||
| 426 | #define RMON_COLLISION2 0x2 | ||
| 427 | #define RMON_COLLISION3 0x3 | ||
| 428 | #define RMON_COLLISION4 0x4 | ||
| 429 | #define RMON_COLLISION5 0x5 | ||
| 430 | #define RMON_COLLISION6 0x6 | ||
| 431 | #define RMON_COLLISION7 0x7 | ||
| 432 | #define RMON_COLLISION8 0x8 | ||
| 433 | #define RMON_COLLISION9 0x9 | ||
| 434 | #define RMON_COLLISION10 0xa | ||
| 435 | #define RMON_COLLISION11 0xb | ||
| 436 | #define RMON_COLLISION12 0xc | ||
| 437 | #define RMON_COLLISION13 0xd | ||
| 438 | #define RMON_COLLISION14 0xe | ||
| 439 | #define RMON_COLLISION15 0xf | ||
| 440 | #define RMON_COLLISION16 0x10 | ||
| 441 | #define RMON_FRAMES_WITH_DEFERRED_XMISSIONS 0x11 | ||
| 442 | #define RMON_LATE_COLLISIONS 0x12 | ||
| 443 | #define RMON_FRAMES_LOST_DUE_TO_MAC_XMIT 0x13 | ||
| 444 | #define RMON_CARRIER_SENSE_ERRORS 0x14 | ||
| 445 | #define RMON_FRAMES_WITH_EXCESSIVE_DEFERAL 0x15 | ||
| 446 | #define RMON_UNICAST_FRAMES_TRANSMITTED_OK 0x16 | ||
| 447 | #define RMON_MULTICAST_FRAMES_XMITTED_OK 0x17 | ||
| 448 | #define RMON_BROADCAST_FRAMES_XMITTED_OK 0x18 | ||
| 449 | #define RMON_SQE_TEST_ERRORS 0x19 | ||
| 450 | #define RMON_PAUSE_MACCTRL_FRAMES_XMITTED 0x1A | ||
| 451 | #define RMON_MACCTRL_FRAMES_XMITTED 0x1B | ||
| 452 | #define RMON_VLAN_FRAMES_XMITTED 0x1C | ||
| 453 | #define RMON_OCTETS_XMITTED_OK 0x1D | ||
| 454 | #define RMON_OCTETS_XMITTED_OK_HI 0x1E | ||
| 455 | |||
| 456 | #define RMON_RX_PACKET_SIZES0 0x40 | ||
| 457 | #define RMON_RX_PACKET_SIZES1 0x41 | ||
| 458 | #define RMON_RX_PACKET_SIZES2 0x42 | ||
| 459 | #define RMON_RX_PACKET_SIZES3 0x43 | ||
| 460 | #define RMON_RX_PACKET_SIZES4 0x44 | ||
| 461 | #define RMON_RX_PACKET_SIZES5 0x45 | ||
| 462 | #define RMON_RX_PACKET_SIZES6 0x46 | ||
| 463 | #define RMON_RX_PACKET_SIZES7 0x47 | ||
| 464 | #define RMON_FRAME_CHECK_SEQUENCE_ERRORS 0x48 | ||
| 465 | #define RMON_ALIGNMENT_ERRORS 0x49 | ||
| 466 | #define RMON_FRAGMENTS 0x4A | ||
| 467 | #define RMON_JABBERS 0x4B | ||
| 468 | #define RMON_FRAMES_LOST_TO_INTMACRCVERR 0x4C | ||
| 469 | #define RMON_UNICAST_FRAMES_RCVD_OK 0x4D | ||
| 470 | #define RMON_MULTICAST_FRAMES_RCVD_OK 0x4E | ||
| 471 | #define RMON_BROADCAST_FRAMES_RCVD_OK 0x4F | ||
| 472 | #define RMON_IN_RANGE_LENGTH_ERRORS 0x50 | ||
| 473 | #define RMON_OUT_OF_RANGE_LENGTH_ERRORS 0x51 | ||
| 474 | #define RMON_VLAN_FRAMES_RCVD 0x52 | ||
| 475 | #define RMON_PAUSE_MAC_CTRL_FRAMES_RCVD 0x53 | ||
| 476 | #define RMON_MAC_CTRL_FRAMES_RCVD 0x54 | ||
| 477 | #define RMON_OCTETS_RCVD_OK 0x55 | ||
| 478 | #define RMON_OCTETS_RCVD_OK_HI 0x56 | ||
| 479 | #define RMON_OCTETS_RCVD_OTHER 0x57 | ||
| 480 | #define RMON_OCTETS_RCVD_OTHER_HI 0x58 | ||
| 481 | |||
| 482 | #endif /* __ETHER00_H */ | ||
diff --git a/include/asm-arm/arch-epxa10db/excalibur.h b/include/asm-arm/arch-epxa10db/excalibur.h new file mode 100644 index 000000000000..5c91dd6d7822 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/excalibur.h | |||
| @@ -0,0 +1,91 @@ | |||
| 1 | /* megafunction wizard: %ARM-Based Excalibur% | ||
| 2 | GENERATION: STANDARD | ||
| 3 | VERSION: WM1.0 | ||
| 4 | MODULE: ARM-Based Excalibur | ||
| 5 | PROJECT: excalibur | ||
| 6 | ============================================================ | ||
| 7 | File Name: v:\embedded\linux\bootldr\excalibur.h | ||
| 8 | Megafunction Name(s): ARM-Based Excalibur | ||
| 9 | ============================================================ | ||
| 10 | |||
| 11 | ************************************************************ | ||
| 12 | THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! | ||
| 13 | ************************************************************/ | ||
| 14 | |||
| 15 | #ifndef EXCALIBUR_H_INCLUDED | ||
| 16 | #define EXCALIBUR_H_INCLUDED | ||
| 17 | |||
| 18 | #define EXC_DEFINE_PROCESSOR_LITTLE_ENDIAN | ||
| 19 | #define EXC_DEFINE_BOOT_FROM_FLASH | ||
| 20 | |||
| 21 | #define EXC_INPUT_CLK_FREQUENCY (50000000) | ||
| 22 | #define EXC_AHB1_CLK_FREQUENCY (150000000) | ||
| 23 | #define EXC_AHB2_CLK_FREQUENCY (75000000) | ||
| 24 | #define EXC_SDRAM_CLK_FREQUENCY (75000000) | ||
| 25 | |||
| 26 | /* Registers Block */ | ||
| 27 | #define EXC_REGISTERS_BASE (0x7fffc000) | ||
| 28 | #define EXC_MODE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x000) | ||
| 29 | #define EXC_IO_CTRL00_BASE (EXC_REGISTERS_BASE + 0x040) | ||
| 30 | #define EXC_MMAP00_BASE (EXC_REGISTERS_BASE + 0x080) | ||
| 31 | #define EXC_PLD_CONFIG00_BASE (EXC_REGISTERS_BASE + 0x140) | ||
| 32 | #define EXC_TIMER00_BASE (EXC_REGISTERS_BASE + 0x200) | ||
| 33 | #define EXC_INT_CTRL00_BASE (EXC_REGISTERS_BASE + 0xc00) | ||
| 34 | #define EXC_CLOCK_CTRL00_BASE (EXC_REGISTERS_BASE + 0x300) | ||
| 35 | #define EXC_WATCHDOG00_BASE (EXC_REGISTERS_BASE + 0xa00) | ||
| 36 | #define EXC_UART00_BASE (EXC_REGISTERS_BASE + 0x280) | ||
| 37 | #define EXC_EBI00_BASE (EXC_REGISTERS_BASE + 0x380) | ||
| 38 | #define EXC_SDRAM00_BASE (EXC_REGISTERS_BASE + 0x400) | ||
| 39 | #define EXC_AHB12_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x800) | ||
| 40 | #define EXC_PLD_STRIPE_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) | ||
| 41 | #define EXC_STRIPE_PLD_BRIDGE_CTRL00_BASE (EXC_REGISTERS_BASE + 0x100) | ||
| 42 | |||
| 43 | #define EXC_REGISTERS_SIZE (0x00004000) | ||
| 44 | |||
| 45 | /* EBI Block(s) */ | ||
| 46 | #define EXC_EBI_BLOCK0_BASE (0x40000000) | ||
| 47 | #define EXC_EBI_BLOCK0_SIZE (0x00400000) | ||
| 48 | #define EXC_EBI_BLOCK0_WIDTH (8) | ||
| 49 | #define EXC_EBI_BLOCK0_NON_CACHEABLE | ||
| 50 | #define EXC_EBI_BLOCK1_BASE (0x40400000) | ||
| 51 | #define EXC_EBI_BLOCK1_SIZE (0x00400000) | ||
| 52 | #define EXC_EBI_BLOCK1_WIDTH (16) | ||
| 53 | #define EXC_EBI_BLOCK1_NON_CACHEABLE | ||
| 54 | #define EXC_EBI_BLOCK2_BASE (0x40800000) | ||
| 55 | #define EXC_EBI_BLOCK2_SIZE (0x00400000) | ||
| 56 | #define EXC_EBI_BLOCK2_WIDTH (16) | ||
| 57 | #define EXC_EBI_BLOCK2_NON_CACHEABLE | ||
| 58 | #define EXC_EBI_BLOCK3_BASE (0x40c00000) | ||
| 59 | #define EXC_EBI_BLOCK3_SIZE (0x00400000) | ||
| 60 | #define EXC_EBI_BLOCK3_WIDTH (16) | ||
| 61 | #define EXC_EBI_BLOCK3_NON_CACHEABLE | ||
| 62 | |||
| 63 | /* SDRAM Block(s) */ | ||
| 64 | #define EXC_SDRAM_BLOCK0_BASE (0x00000000) | ||
| 65 | #define EXC_SDRAM_BLOCK0_SIZE (0x04000000) | ||
| 66 | #define EXC_SDRAM_BLOCK0_WIDTH (32) | ||
| 67 | #define EXC_SDRAM_BLOCK1_BASE (0x04000000) | ||
| 68 | #define EXC_SDRAM_BLOCK1_SIZE (0x04000000) | ||
| 69 | #define EXC_SDRAM_BLOCK1_WIDTH (32) | ||
| 70 | |||
| 71 | /* Single Port SRAM Block(s) */ | ||
| 72 | #define EXC_SPSRAM_BLOCK0_BASE (0x08000000) | ||
| 73 | #define EXC_SPSRAM_BLOCK0_SIZE (0x00020000) | ||
| 74 | #define EXC_SPSRAM_BLOCK1_BASE (0x08020000) | ||
| 75 | #define EXC_SPSRAM_BLOCK1_SIZE (0x00020000) | ||
| 76 | |||
| 77 | /* PLD Block(s) */ | ||
| 78 | #define EXC_PLD_BLOCK0_BASE (0x80000000) | ||
| 79 | #define EXC_PLD_BLOCK0_SIZE (0x00004000) | ||
| 80 | #define EXC_PLD_BLOCK0_NON_CACHEABLE | ||
| 81 | #define EXC_PLD_BLOCK1_BASE (0xf000000) | ||
| 82 | #define EXC_PLD_BLOCK1_SIZE (0x00004000) | ||
| 83 | #define EXC_PLD_BLOCK1_NON_CACHEABLE | ||
| 84 | #define EXC_PLD_BLOCK2_BASE (0x80008000) | ||
| 85 | #define EXC_PLD_BLOCK2_SIZE (0x00004000) | ||
| 86 | #define EXC_PLD_BLOCK2_NON_CACHEABLE | ||
| 87 | #define EXC_PLD_BLOCK3_BASE (0x8000c000) | ||
| 88 | #define EXC_PLD_BLOCK3_SIZE (0x00004000) | ||
| 89 | #define EXC_PLD_BLOCK3_NON_CACHEABLE | ||
| 90 | |||
| 91 | #endif | ||
diff --git a/include/asm-arm/arch-epxa10db/hardware.h b/include/asm-arm/arch-epxa10db/hardware.h new file mode 100644 index 000000000000..b992c2924a77 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/hardware.h | |||
| @@ -0,0 +1,64 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-epxa10/hardware.h | ||
| 3 | * | ||
| 4 | * This file contains the hardware definitions of the Integrator. | ||
| 5 | * | ||
| 6 | * Copyright (C) 1999 ARM Limited. | ||
| 7 | * Copyright (C) 2001 Altera Corporation | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | * | ||
| 14 | * This program is distributed in the hope that it will be useful, | ||
| 15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 17 | * GNU General Public License for more details. | ||
| 18 | * | ||
| 19 | * You should have received a copy of the GNU General Public License | ||
| 20 | * along with this program; if not, write to the Free Software | ||
| 21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 22 | */ | ||
| 23 | #ifndef __ASM_ARCH_HARDWARE_H | ||
| 24 | #define __ASM_ARCH_HARDWARE_H | ||
| 25 | |||
| 26 | #include <asm/arch/platform.h> | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Where in virtual memory the IO devices (timers, system controllers | ||
| 30 | * and so on) | ||
| 31 | */ | ||
| 32 | #define IO_BASE 0xf0000000 // VA of IO | ||
| 33 | #define IO_SIZE 0x10000000 // How much? | ||
| 34 | #define IO_START EXC_REGISTERS_BASE // PA of IO | ||
| 35 | /* macro to get at IO space when running virtually */ | ||
| 36 | #define IO_ADDRESS(x) ((x) | 0xf0000000) | ||
| 37 | |||
| 38 | #define FLASH_VBASE 0xFE000000 | ||
| 39 | #define FLASH_SIZE 0x01000000 | ||
| 40 | #define FLASH_START EXC_EBI_BLOCK0_BASE | ||
| 41 | #define FLASH_VADDR(x) ((x)|0xFE000000) | ||
| 42 | /* | ||
| 43 | * Similar to above, but for PCI addresses (memory, IO, Config and the | ||
| 44 | * V3 chip itself). WARNING: this has to mirror definitions in platform.h | ||
| 45 | */ | ||
| 46 | #if 0 | ||
| 47 | #define PCI_MEMORY_VADDR 0xe8000000 | ||
| 48 | #define PCI_CONFIG_VADDR 0xec000000 | ||
| 49 | #define PCI_V3_VADDR 0xed000000 | ||
| 50 | #define PCI_IO_VADDR 0xee000000 | ||
| 51 | |||
| 52 | #define PCIO_BASE PCI_IO_VADDR | ||
| 53 | #define PCIMEM_BASE PCI_MEMORY_VADDR | ||
| 54 | |||
| 55 | |||
| 56 | #define pcibios_assign_all_busses() 1 | ||
| 57 | |||
| 58 | #define PCIBIOS_MIN_IO 0x6000 | ||
| 59 | #define PCIBIOS_MIN_MEM 0x00100000 | ||
| 60 | #endif | ||
| 61 | |||
| 62 | |||
| 63 | #endif | ||
| 64 | |||
diff --git a/include/asm-arm/arch-epxa10db/int_ctrl00.h b/include/asm-arm/arch-epxa10db/int_ctrl00.h new file mode 100644 index 000000000000..23ec864c40bb --- /dev/null +++ b/include/asm-arm/arch-epxa10db/int_ctrl00.h | |||
| @@ -0,0 +1,288 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * This file contains the register definitions for the Excalibur | ||
| 4 | * Timer TIMER00. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2001 Altera Corporation | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | #ifndef __INT_CTRL00_H | ||
| 24 | #define __INT_CTRL00_H | ||
| 25 | |||
| 26 | #define INT_MS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x00 )) | ||
| 27 | #define INT_MS_FC_MSK (0x10000) | ||
| 28 | #define INT_MS_FC_OFST (16) | ||
| 29 | #define INT_MS_M1_MSK (0x8000) | ||
| 30 | #define INT_MS_M1_OFST (15) | ||
| 31 | #define INT_MS_M0_MSK (0x4000) | ||
| 32 | #define INT_MS_M0_OFST (14) | ||
| 33 | #define INT_MS_AE_MSK (0x2000) | ||
| 34 | #define INT_MS_AE_OFST (13) | ||
| 35 | #define INT_MS_PE_MSK (0x1000) | ||
| 36 | #define INT_MS_PE_OFST (12) | ||
| 37 | #define INT_MS_EE_MSK (0x0800) | ||
| 38 | #define INT_MS_EE_OFST (11) | ||
| 39 | #define INT_MS_PS_MSK (0x0400) | ||
| 40 | #define INT_MS_PS_OFST (10) | ||
| 41 | #define INT_MS_T1_MSK (0x0200) | ||
| 42 | #define INT_MS_T1_OFST (9) | ||
| 43 | #define INT_MS_T0_MSK (0x0100) | ||
| 44 | #define INT_MS_T0_OFST (8) | ||
| 45 | #define INT_MS_UA_MSK (0x0080) | ||
| 46 | #define INT_MS_UA_OFST (7) | ||
| 47 | #define INT_MS_IP_MSK (0x0040) | ||
| 48 | #define INT_MS_IP_OFST (6) | ||
| 49 | #define INT_MS_P5_MSK (0x0020) | ||
| 50 | #define INT_MS_P5_OFST (5) | ||
| 51 | #define INT_MS_P4_MSK (0x0010) | ||
| 52 | #define INT_MS_P4_OFST (4) | ||
| 53 | #define INT_MS_P3_MSK (0x0008) | ||
| 54 | #define INT_MS_P3_OFST (3) | ||
| 55 | #define INT_MS_P2_MSK (0x0004) | ||
| 56 | #define INT_MS_P2_OFST (2) | ||
| 57 | #define INT_MS_P1_MSK (0x0002) | ||
| 58 | #define INT_MS_P1_OFST (1) | ||
| 59 | #define INT_MS_P0_MSK (0x0001) | ||
| 60 | #define INT_MS_P0_OFST (0) | ||
| 61 | |||
| 62 | #define INT_MC(base_addr) (INT_CTRL00_TYPE (base_addr + 0x04 )) | ||
| 63 | #define INT_MC_FC_MSK (0x10000) | ||
| 64 | #define INT_MC_FC_OFST (16) | ||
| 65 | #define INT_MC_M1_MSK (0x8000) | ||
| 66 | #define INT_MC_M1_OFST (15) | ||
| 67 | #define INT_MC_M0_MSK (0x4000) | ||
| 68 | #define INT_MC_M0_OFST (14) | ||
| 69 | #define INT_MC_AE_MSK (0x2000) | ||
| 70 | #define INT_MC_AE_OFST (13) | ||
| 71 | #define INT_MC_PE_MSK (0x1000) | ||
| 72 | #define INT_MC_PE_OFST (12) | ||
| 73 | #define INT_MC_EE_MSK (0x0800) | ||
| 74 | #define INT_MC_EE_OFST (11) | ||
| 75 | #define INT_MC_PS_MSK (0x0400) | ||
| 76 | #define INT_MC_PS_OFST (10) | ||
| 77 | #define INT_MC_T1_MSK (0x0200) | ||
| 78 | #define INT_MC_T1_OFST (9) | ||
| 79 | #define INT_MC_T0_MSK (0x0100) | ||
| 80 | #define INT_MC_T0_OFST (8) | ||
| 81 | #define INT_MC_UA_MSK (0x0080) | ||
| 82 | #define INT_MC_UA_OFST (7) | ||
| 83 | #define INT_MC_IP_MSK (0x0040) | ||
| 84 | #define INT_MC_IP_OFST (6) | ||
| 85 | #define INT_MC_P5_MSK (0x0020) | ||
| 86 | #define INT_MC_P5_OFST (5) | ||
| 87 | #define INT_MC_P4_MSK (0x0010) | ||
| 88 | #define INT_MC_P4_OFST (4) | ||
| 89 | #define INT_MC_P3_MSK (0x0008) | ||
| 90 | #define INT_MC_P3_OFST (3) | ||
| 91 | #define INT_MC_P2_MSK (0x0004) | ||
| 92 | #define INT_MC_P2_OFST (2) | ||
| 93 | #define INT_MC_P1_MSK (0x0002) | ||
| 94 | #define INT_MC_P1_OFST (1) | ||
| 95 | #define INT_MC_P0_MSK (0x0001) | ||
| 96 | #define INT_MC_P0_OFST (0) | ||
| 97 | |||
| 98 | #define INT_SS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x08 )) | ||
| 99 | #define INT_SS_FC_SSK (0x8000) | ||
| 100 | #define INT_SS_FC_OFST (15) | ||
| 101 | #define INT_SS_M1_SSK (0x8000) | ||
| 102 | #define INT_SS_M1_OFST (15) | ||
| 103 | #define INT_SS_M0_SSK (0x4000) | ||
| 104 | #define INT_SS_M0_OFST (14) | ||
| 105 | #define INT_SS_AE_SSK (0x2000) | ||
| 106 | #define INT_SS_AE_OFST (13) | ||
| 107 | #define INT_SS_PE_SSK (0x1000) | ||
| 108 | #define INT_SS_PE_OFST (12) | ||
| 109 | #define INT_SS_EE_SSK (0x0800) | ||
| 110 | #define INT_SS_EE_OFST (11) | ||
| 111 | #define INT_SS_PS_SSK (0x0400) | ||
| 112 | #define INT_SS_PS_OFST (10) | ||
| 113 | #define INT_SS_T1_SSK (0x0200) | ||
| 114 | #define INT_SS_T1_OFST (9) | ||
| 115 | #define INT_SS_T0_SSK (0x0100) | ||
| 116 | #define INT_SS_T0_OFST (8) | ||
| 117 | #define INT_SS_UA_SSK (0x0080) | ||
| 118 | #define INT_SS_UA_OFST (7) | ||
| 119 | #define INT_SS_IP_SSK (0x0040) | ||
| 120 | #define INT_SS_IP_OFST (6) | ||
| 121 | #define INT_SS_P5_SSK (0x0020) | ||
| 122 | #define INT_SS_P5_OFST (5) | ||
| 123 | #define INT_SS_P4_SSK (0x0010) | ||
| 124 | #define INT_SS_P4_OFST (4) | ||
| 125 | #define INT_SS_P3_SSK (0x0008) | ||
| 126 | #define INT_SS_P3_OFST (3) | ||
| 127 | #define INT_SS_P2_SSK (0x0004) | ||
| 128 | #define INT_SS_P2_OFST (2) | ||
| 129 | #define INT_SS_P1_SSK (0x0002) | ||
| 130 | #define INT_SS_P1_OFST (1) | ||
| 131 | #define INT_SS_P0_SSK (0x0001) | ||
| 132 | #define INT_SS_P0_OFST (0) | ||
| 133 | |||
| 134 | #define INT_RS(base_addr) (INT_CTRL00_TYPE (base_addr + 0x0C )) | ||
| 135 | #define INT_RS_FC_RSK (0x10000) | ||
| 136 | #define INT_RS_FC_OFST (16) | ||
| 137 | #define INT_RS_M1_RSK (0x8000) | ||
| 138 | #define INT_RS_M1_OFST (15) | ||
| 139 | #define INT_RS_M0_RSK (0x4000) | ||
| 140 | #define INT_RS_M0_OFST (14) | ||
| 141 | #define INT_RS_AE_RSK (0x2000) | ||
| 142 | #define INT_RS_AE_OFST (13) | ||
| 143 | #define INT_RS_PE_RSK (0x1000) | ||
| 144 | #define INT_RS_PE_OFST (12) | ||
| 145 | #define INT_RS_EE_RSK (0x0800) | ||
| 146 | #define INT_RS_EE_OFST (11) | ||
| 147 | #define INT_RS_PS_RSK (0x0400) | ||
| 148 | #define INT_RS_PS_OFST (10) | ||
| 149 | #define INT_RS_T1_RSK (0x0200) | ||
| 150 | #define INT_RS_T1_OFST (9) | ||
| 151 | #define INT_RS_T0_RSK (0x0100) | ||
| 152 | #define INT_RS_T0_OFST (8) | ||
| 153 | #define INT_RS_UA_RSK (0x0080) | ||
| 154 | #define INT_RS_UA_OFST (7) | ||
| 155 | #define INT_RS_IP_RSK (0x0040) | ||
| 156 | #define INT_RS_IP_OFST (6) | ||
| 157 | #define INT_RS_P5_RSK (0x0020) | ||
| 158 | #define INT_RS_P5_OFST (5) | ||
| 159 | #define INT_RS_P4_RSK (0x0010) | ||
| 160 | #define INT_RS_P4_OFST (4) | ||
| 161 | #define INT_RS_P3_RSK (0x0008) | ||
| 162 | #define INT_RS_P3_OFST (3) | ||
| 163 | #define INT_RS_P2_RSK (0x0004) | ||
| 164 | #define INT_RS_P2_OFST (2) | ||
| 165 | #define INT_RS_P1_RSK (0x0002) | ||
| 166 | #define INT_RS_P1_OFST (1) | ||
| 167 | #define INT_RS_P0_RSK (0x0001) | ||
| 168 | #define INT_RS_P0_OFST (0) | ||
| 169 | |||
| 170 | #define INT_ID(base_addr) (INT_CTRL00_TYPE (base_addr + 0x10 )) | ||
| 171 | #define INT_ID_ID_MSK (0x3F) | ||
| 172 | #define INT_ID_ID_OFST (0) | ||
| 173 | |||
| 174 | #define INT_PLD_PRIORITY(base_addr) (INT_CTRL00_TYPE (base_addr + 0x14 )) | ||
| 175 | #define INT_PLD_PRIORITY_PRI_MSK (0x3F) | ||
| 176 | #define INT_PLD_PRIORITY_PRI_OFST (0) | ||
| 177 | #define INT_PLD_PRIORITY_GA_MSK (0x40) | ||
| 178 | #define INT_PLD_PRIORITY_GA_OFST (6) | ||
| 179 | |||
| 180 | #define INT_MODE(base_addr) (INT_CTRL00_TYPE (base_addr + 0x18 )) | ||
| 181 | #define INT_MODE_MODE_MSK (0x3) | ||
| 182 | #define INT_MODE_MODE_OFST (0) | ||
| 183 | |||
| 184 | #define INT_PRIORITY_P0(base_addr) (INT_CTRL00_TYPE (base_addr + 0x80 )) | ||
| 185 | #define INT_PRIORITY_P0_PRI_MSK (0x3F) | ||
| 186 | #define INT_PRIORITY_P0_PRI_OFST (0) | ||
| 187 | #define INT_PRIORITY_P0_FQ_MSK (0x40) | ||
| 188 | #define INT_PRIORITY_P0_FQ_OFST (6) | ||
| 189 | |||
| 190 | #define INT_PRIORITY_P1(base_addr) (INT_CTRL00_TYPE (base_addr + 0x84 )) | ||
| 191 | #define INT_PRIORITY_P1_PRI_MSK (0x3F) | ||
| 192 | #define INT_PRIORITY_P1_PRI_OFST (0) | ||
| 193 | #define INT_PRIORITY_P1_FQ_MSK (0x40) | ||
| 194 | #define INT_PRIORITY_P1_FQ_OFST (6) | ||
| 195 | |||
| 196 | #define INT_PRIORITY_P2(base_addr) (INT_CTRL00_TYPE (base_addr + 0x88 )) | ||
| 197 | #define INT_PRIORITY_P2_PRI_MSK (0x3F) | ||
| 198 | #define INT_PRIORITY_P2_PRI_OFST (0) | ||
| 199 | #define INT_PRIORITY_P2_FQ_MSK (0x40) | ||
| 200 | #define INT_PRIORITY_P2_FQ_OFST (6) | ||
| 201 | |||
| 202 | #define INT_PRIORITY_P3(base_addr) (INT_CTRL00_TYPE (base_addr + 0x8C )) | ||
| 203 | #define INT_PRIORITY_P3_PRI_MSK (0x3F) | ||
| 204 | #define INT_PRIORITY_P3_PRI_OFST (0) | ||
| 205 | #define INT_PRIORITY_P3_FQ_MSK (0x40) | ||
| 206 | #define INT_PRIORITY_P3_FQ_OFST (6) | ||
| 207 | |||
| 208 | #define INT_PRIORITY_P4(base_addr) (INT_CTRL00_TYPE (base_addr + 0x90 )) | ||
| 209 | #define INT_PRIORITY_P4_PRI_MSK (0x3F) | ||
| 210 | #define INT_PRIORITY_P4_PRI_OFST (0) | ||
| 211 | #define INT_PRIORITY_P4_FQ_MSK (0x40) | ||
| 212 | #define INT_PRIORITY_P4_FQ_OFST (6) | ||
| 213 | |||
| 214 | #define INT_PRIORITY_P5(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) | ||
| 215 | #define INT_PRIORITY_P5_PRI_MSK (0x3F) | ||
| 216 | #define INT_PRIORITY_P5_PRI_OFST (0) | ||
| 217 | #define INT_PRIORITY_P5_FQ_MSK (0x40) | ||
| 218 | #define INT_PRIORITY_P5_FQ_OFST (6) | ||
| 219 | |||
| 220 | #define INT_PRIORITY_IP(base_addr) (INT_CTRL00_TYPE (base_addr + 0x94 )) | ||
| 221 | #define INT_PRIORITY_IP_PRI_MSK (0x3F) | ||
| 222 | #define INT_PRIORITY_IP_PRI_OFST (0) | ||
| 223 | #define INT_PRIORITY_IP_FQ_MSK (0x40) | ||
| 224 | #define INT_PRIORITY_IP_FQ_OFST (6) | ||
| 225 | |||
| 226 | #define INT_PRIORITY_UA(base_addr) (INT_CTRL00_TYPE (base_addr + 0x9C )) | ||
| 227 | #define INT_PRIORITY_UA_PRI_MSK (0x3F) | ||
| 228 | #define INT_PRIORITY_UA_PRI_OFST (0) | ||
| 229 | #define INT_PRIORITY_UA_FQ_MSK (0x40) | ||
| 230 | #define INT_PRIORITY_UA_FQ_OFST (6) | ||
| 231 | |||
| 232 | #define INT_PRIORITY_T0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA0 )) | ||
| 233 | #define INT_PRIORITY_T0_PRI_MSK (0x3F) | ||
| 234 | #define INT_PRIORITY_T0_PRI_OFST (0) | ||
| 235 | #define INT_PRIORITY_T0_FQ_MSK (0x40) | ||
| 236 | #define INT_PRIORITY_T0_FQ_OFST (6) | ||
| 237 | |||
| 238 | #define INT_PRIORITY_T1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA4 )) | ||
| 239 | #define INT_PRIORITY_T1_PRI_MSK (0x3F) | ||
| 240 | #define INT_PRIORITY_T1_PRI_OFST (0) | ||
| 241 | #define INT_PRIORITY_T1_FQ_MSK (0x40) | ||
| 242 | #define INT_PRIORITY_T1_FQ_OFST (6) | ||
| 243 | |||
| 244 | #define INT_PRIORITY_PS(base_addr) (INT_CTRL00_TYPE (base_addr + 0xA8 )) | ||
| 245 | #define INT_PRIORITY_PS_PRI_MSK (0x3F) | ||
| 246 | #define INT_PRIORITY_PS_PRI_OFST (0) | ||
| 247 | #define INT_PRIORITY_PS_FQ_MSK (0x40) | ||
| 248 | #define INT_PRIORITY_PS_FQ_OFST (6) | ||
| 249 | |||
| 250 | #define INT_PRIORITY_EE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xAC )) | ||
| 251 | #define INT_PRIORITY_EE_PRI_MSK (0x3F) | ||
| 252 | #define INT_PRIORITY_EE_PRI_OFST (0) | ||
| 253 | #define INT_PRIORITY_EE_FQ_MSK (0x40) | ||
| 254 | #define INT_PRIORITY_EE_FQ_OFST (6) | ||
| 255 | |||
| 256 | #define INT_PRIORITY_PE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB0 )) | ||
| 257 | #define INT_PRIORITY_PE_PRI_MSK (0x3F) | ||
| 258 | #define INT_PRIORITY_PE_PRI_OFST (0) | ||
| 259 | #define INT_PRIORITY_PE_FQ_MSK (0x40) | ||
| 260 | #define INT_PRIORITY_PE_FQ_OFST (6) | ||
| 261 | |||
| 262 | #define INT_PRIORITY_AE(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB4 )) | ||
| 263 | #define INT_PRIORITY_AE_PRI_MSK (0x3F) | ||
| 264 | #define INT_PRIORITY_AE_PRI_OFST (0) | ||
| 265 | #define INT_PRIORITY_AE_FQ_MSK (0x40) | ||
| 266 | #define INT_PRIORITY_AE_FQ_OFST (6) | ||
| 267 | |||
| 268 | #define INT_PRIORITY_M0(base_addr) (INT_CTRL00_TYPE (base_addr + 0xB8 )) | ||
| 269 | #define INT_PRIORITY_M0_PRI_MSK (0x3F) | ||
| 270 | #define INT_PRIORITY_M0_PRI_OFST (0) | ||
| 271 | #define INT_PRIORITY_M0_FQ_MSK (0x40) | ||
| 272 | #define INT_PRIORITY_M0_FQ_OFST (6) | ||
| 273 | |||
| 274 | #define INT_PRIORITY_M1(base_addr) (INT_CTRL00_TYPE (base_addr + 0xBC )) | ||
| 275 | #define INT_PRIORITY_M1_PRI_MSK (0x3F) | ||
| 276 | #define INT_PRIORITY_M1_PRI_OFST (0) | ||
| 277 | #define INT_PRIORITY_M1_FQ_MSK (0x40) | ||
| 278 | #define INT_PRIORITY_M1_FQ_OFST (6) | ||
| 279 | |||
| 280 | #define INT_PRIORITY_FC(base_addr) (INT_CTRL00_TYPE (base_addr + 0xC0 )) | ||
| 281 | #define INT_PRIORITY_FC_PRI_MSK (0x3F) | ||
| 282 | #define INT_PRIORITY_FC_PRI_OFST (0) | ||
| 283 | #define INT_PRIORITY_FC_FQ_MSK (0x40) | ||
| 284 | #define INT_PRIORITY_FC_FQ_OFST (6) | ||
| 285 | |||
| 286 | #endif /* __INT_CTRL00_H */ | ||
| 287 | |||
| 288 | |||
diff --git a/include/asm-arm/arch-epxa10db/io.h b/include/asm-arm/arch-epxa10db/io.h new file mode 100644 index 000000000000..1f0afa257621 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/io.h | |||
| @@ -0,0 +1,39 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-epxa10db/io.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARM_ARCH_IO_H | ||
| 21 | #define __ASM_ARM_ARCH_IO_H | ||
| 22 | |||
| 23 | #define IO_SPACE_LIMIT 0xffff | ||
| 24 | |||
| 25 | |||
| 26 | /* | ||
| 27 | * Generic virtual read/write | ||
| 28 | */ | ||
| 29 | /*#define outsw __arch_writesw | ||
| 30 | #define outsl __arch_writesl | ||
| 31 | #define outsb __arch_writesb | ||
| 32 | #define insb __arch_readsb | ||
| 33 | #define insw __arch_readsw | ||
| 34 | #define insl __arch_readsl*/ | ||
| 35 | |||
| 36 | #define __io(a) ((void __iomem *)(a)) | ||
| 37 | #define __mem_pci(a) (a) | ||
| 38 | |||
| 39 | #endif | ||
diff --git a/include/asm-arm/arch-epxa10db/irqs.h b/include/asm-arm/arch-epxa10db/irqs.h new file mode 100644 index 000000000000..c3758a3b5d9d --- /dev/null +++ b/include/asm-arm/arch-epxa10db/irqs.h | |||
| @@ -0,0 +1,45 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-camelot/irqs.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 Altera Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* Use the Excalibur chip definitions */ | ||
| 22 | #define INT_CTRL00_TYPE | ||
| 23 | #include "asm/arch/int_ctrl00.h" | ||
| 24 | |||
| 25 | |||
| 26 | #define IRQ_PLD0 INT_MS_P0_OFST | ||
| 27 | #define IRQ_PLD1 INT_MS_P1_OFST | ||
| 28 | #define IRQ_PLD2 INT_MS_P2_OFST | ||
| 29 | #define IRQ_PLD3 INT_MS_P3_OFST | ||
| 30 | #define IRQ_PLD4 INT_MS_P4_OFST | ||
| 31 | #define IRQ_PLD5 INT_MS_P5_OFST | ||
| 32 | #define IRQ_EXT INT_MS_IP_OFST | ||
| 33 | #define IRQ_UART INT_MS_UA_OFST | ||
| 34 | #define IRQ_TIMER0 INT_MS_T0_OFST | ||
| 35 | #define IRQ_TIMER1 INT_MS_T1_OFST | ||
| 36 | #define IRQ_PLL INT_MS_PLL_OFST | ||
| 37 | #define IRQ_EBI INT_MS_EBI_OFST | ||
| 38 | #define IRQ_STRIPE_BRIDGE INT_MS_PLL_OFST | ||
| 39 | #define IRQ_AHB_BRIDGE INT_MS_PLL_OFST | ||
| 40 | #define IRQ_COMMRX INT_MS_CR_OFST | ||
| 41 | #define IRQ_COMMTX INT_MS_CT_OFST | ||
| 42 | #define IRQ_FAST_COMM INT_MS_FC_OFST | ||
| 43 | |||
| 44 | #define NR_IRQS (INT_MS_FC_OFST + 1) | ||
| 45 | |||
diff --git a/include/asm-arm/arch-epxa10db/memory.h b/include/asm-arm/arch-epxa10db/memory.h new file mode 100644 index 000000000000..3f86bf7f67f0 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/memory.h | |||
| @@ -0,0 +1,38 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-epxa10/memory.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 Altera Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | #ifndef __ASM_ARCH_MEMORY_H | ||
| 21 | #define __ASM_ARCH_MEMORY_H | ||
| 22 | |||
| 23 | /* | ||
| 24 | * Physical DRAM offset. | ||
| 25 | */ | ||
| 26 | #define PHYS_OFFSET (0x00000000UL) | ||
| 27 | |||
| 28 | /* | ||
| 29 | * Virtual view <-> DMA view memory address translations | ||
| 30 | * virt_to_bus: Used to translate the virtual address to an | ||
| 31 | * address suitable to be passed to set_dma_addr | ||
| 32 | * bus_to_virt: Used to convert an address for DMA operations | ||
| 33 | * to an address that the kernel can use. | ||
| 34 | */ | ||
| 35 | #define __virt_to_bus(x) (x - PAGE_OFFSET + /*SDRAM_BASE*/0) | ||
| 36 | #define __bus_to_virt(x) (x - /*SDRAM_BASE*/0 + PAGE_OFFSET) | ||
| 37 | |||
| 38 | #endif | ||
diff --git a/include/asm-arm/arch-epxa10db/mode_ctrl00.h b/include/asm-arm/arch-epxa10db/mode_ctrl00.h new file mode 100644 index 000000000000..d8a7efa12e19 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/mode_ctrl00.h | |||
| @@ -0,0 +1,80 @@ | |||
| 1 | #ifndef __MODE_CTRL00_H | ||
| 2 | #define __MODE_CTRL00_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Register definitions for the reset and mode control | ||
| 6 | */ | ||
| 7 | |||
| 8 | /* | ||
| 9 | * Copyright (C) 2001 Altera Corporation | ||
| 10 | * | ||
| 11 | * This program is free software; you can redistribute it and/or modify | ||
| 12 | * it under the terms of the GNU General Public License as published by | ||
| 13 | * the Free Software Foundation; either version 2 of the License, or | ||
| 14 | * (at your option) any later version. | ||
| 15 | * | ||
| 16 | * This program is distributed in the hope that it will be useful, | ||
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 19 | * GNU General Public License for more details. | ||
| 20 | * | ||
| 21 | * You should have received a copy of the GNU General Public License | ||
| 22 | * along with this program; if not, write to the Free Software | ||
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 24 | */ | ||
| 25 | |||
| 26 | |||
| 27 | |||
| 28 | #define BOOT_CR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR )) | ||
| 29 | #define BOOT_CR_BF_MSK (0x1) | ||
| 30 | #define BOOT_CR_BF_OFST (0) | ||
| 31 | #define BOOT_CR_HM_MSK (0x2) | ||
| 32 | #define BOOT_CR_HM_OFST (1) | ||
| 33 | #define BOOT_CR_RE_MSK (0x4) | ||
| 34 | #define BOOT_CR_RE_OFST (2) | ||
| 35 | |||
| 36 | #define RESET_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x4 )) | ||
| 37 | #define RESET_SR_WR_MSK (0x1) | ||
| 38 | #define RESET_SR_WR_OFST (0) | ||
| 39 | #define RESET_SR_CR_MSK (0x2) | ||
| 40 | #define RESET_SR_CR_OFST (1) | ||
| 41 | #define RESET_SR_JT_MSK (0x4) | ||
| 42 | #define RESET_SR_JT_OFST (2) | ||
| 43 | #define RESET_SR_ER_MSK (0x8) | ||
| 44 | #define RESET_SR_ER_OFST (3) | ||
| 45 | |||
| 46 | #define ID_CODE(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x08 )) | ||
| 47 | |||
| 48 | #define SRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x20 )) | ||
| 49 | #define SRAM0_SR_SIZE_MSK (0xFFFFF000) | ||
| 50 | #define SRAM0_SR_SIZE_OFST (12) | ||
| 51 | |||
| 52 | #define SRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x24 )) | ||
| 53 | #define SRAM1_SR_SIZE_MSK (0xFFFFF000) | ||
| 54 | #define SRAM1_SR_SIZE_OFST (12) | ||
| 55 | |||
| 56 | #define DPSRAM0_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x30 )) | ||
| 57 | |||
| 58 | #define DPSRAM0_SR_MODE_MSK (0xF) | ||
| 59 | #define DPSRAM0_SR_MODE_OFST (0) | ||
| 60 | #define DPSRAM0_SR_GLBL_MSK (0x30) | ||
| 61 | #define DPSRAM0_SR_SIZE_MSK (0xFFFFF000) | ||
| 62 | #define DPSRAM0_SR_SIZE_OFST (12) | ||
| 63 | |||
| 64 | #define DPSRAM0_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x34 )) | ||
| 65 | #define DPSRAM0_LCR_LCKADDR_MSK (0x1FFE0) | ||
| 66 | #define DPSRAM0_LCR_LCKADDR_OFST (4) | ||
| 67 | |||
| 68 | #define DPSRAM1_SR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x38 )) | ||
| 69 | #define DPSRAM1_SR_MODE_MSK (0xF) | ||
| 70 | #define DPSRAM1_SR_MODE_OFST (0) | ||
| 71 | #define DPSRAM1_SR_GLBL_MSK (0x30) | ||
| 72 | #define DPSRAM1_SR_GLBL_OFST (4) | ||
| 73 | #define DPSRAM1_SR_SIZE_MSK (0xFFFFF000) | ||
| 74 | #define DPSRAM1_SR_SIZE_OFST (12) | ||
| 75 | |||
| 76 | #define DPSRAM1_LCR(BASE_ADDR) (MODE_CTRL00_TYPE (BASE_ADDR + 0x3C )) | ||
| 77 | #define DPSRAM1_LCR_LCKADDR_MSK (0x1FFE0) | ||
| 78 | #define DPSRAM1_LCR_LCKADDR_OFST (4) | ||
| 79 | |||
| 80 | #endif /* __MODE_CTRL00_H */ | ||
diff --git a/include/asm-arm/arch-epxa10db/param.h b/include/asm-arm/arch-epxa10db/param.h new file mode 100644 index 000000000000..783dedd71c8f --- /dev/null +++ b/include/asm-arm/arch-epxa10db/param.h | |||
| @@ -0,0 +1,19 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-epxa10db/param.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
diff --git a/include/asm-arm/arch-epxa10db/platform.h b/include/asm-arm/arch-epxa10db/platform.h new file mode 100644 index 000000000000..129bb0f212a0 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/platform.h | |||
| @@ -0,0 +1,7 @@ | |||
| 1 | #ifndef PLATFORM_H | ||
| 2 | #define PLATFORM_H | ||
| 3 | #include "excalibur.h" | ||
| 4 | |||
| 5 | #define MAXIRQNUM 15 | ||
| 6 | #endif | ||
| 7 | |||
diff --git a/include/asm-arm/arch-epxa10db/pld_conf00.h b/include/asm-arm/arch-epxa10db/pld_conf00.h new file mode 100644 index 000000000000..7af2c38dacc6 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/pld_conf00.h | |||
| @@ -0,0 +1,73 @@ | |||
| 1 | #ifndef __PLD_CONF00_H | ||
| 2 | #define __PLD_CONF00_H | ||
| 3 | |||
| 4 | /* | ||
| 5 | * Register definitions for the PLD Configuration Logic | ||
| 6 | */ | ||
| 7 | |||
| 8 | /* | ||
| 9 | * | ||
| 10 | * This file contains the register definitions for the Excalibur | ||
| 11 | * Interrupt controller INT_CTRL00. | ||
| 12 | * | ||
| 13 | * Copyright (C) 2001 Altera Corporation | ||
| 14 | * | ||
| 15 | * This program is free software; you can redistribute it and/or modify | ||
| 16 | * it under the terms of the GNU General Public License as published by | ||
| 17 | * the Free Software Foundation; either version 2 of the License, or | ||
| 18 | * (at your option) any later version. | ||
| 19 | * | ||
| 20 | * This program is distributed in the hope that it will be useful, | ||
| 21 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 22 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 23 | * GNU General Public License for more details. | ||
| 24 | * | ||
| 25 | * You should have received a copy of the GNU General Public License | ||
| 26 | * along with this program; if not, write to the Free Software | ||
| 27 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 28 | */ | ||
| 29 | |||
| 30 | #define CONFIG_CONTROL(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR)) | ||
| 31 | #define CONFIG_CONTROL_LK_MSK (0x1) | ||
| 32 | #define CONFIG_CONTROL_LK_OFST (0) | ||
| 33 | #define CONFIG_CONTROL_CO_MSK (0x2) | ||
| 34 | #define CONFIG_CONTROL_CO_OFST (1) | ||
| 35 | #define CONFIG_CONTROL_B_MSK (0x4) | ||
| 36 | #define CONFIG_CONTROL_B_OFST (2) | ||
| 37 | #define CONFIG_CONTROL_PC_MSK (0x8) | ||
| 38 | #define CONFIG_CONTROL_PC_OFST (3) | ||
| 39 | #define CONFIG_CONTROL_E_MSK (0x10) | ||
| 40 | #define CONFIG_CONTROL_E_OFST (4) | ||
| 41 | #define CONFIG_CONTROL_ES_MSK (0xE0) | ||
| 42 | #define CONFIG_CONTROL_ES_OFST (5) | ||
| 43 | #define CONFIG_CONTROL_ES_0_MSK (0x20) | ||
| 44 | #define CONFIG_CONTROL_ES_1_MSK (0x40) | ||
| 45 | #define CONFIG_CONTROL_ES_2_MSK (0x80) | ||
| 46 | |||
| 47 | #define CONFIG_CONTROL_CLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x4 )) | ||
| 48 | #define CONFIG_CONTROL_CLOCK_RATIO_MSK (0xFFFF) | ||
| 49 | #define CONFIG_CONTROL_CLOCK_RATIO_OFST (0) | ||
| 50 | |||
| 51 | #define CONFIG_CONTROL_DATA(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0x8 )) | ||
| 52 | #define CONFIG_CONTROL_DATA_MSK (0xFFFFFFFF) | ||
| 53 | #define CONFIG_CONTROL_DATA_OFST (0) | ||
| 54 | |||
| 55 | #define CONFIG_UNLOCK(BASE_ADDR) (PLD_CONF00_TYPE (BASE_ADDR + 0xC )) | ||
| 56 | #define CONFIG_UNLOCK_MSK (0xFFFFFFFF) | ||
| 57 | #define CONFIG_UNLOCK_OFST (0) | ||
| 58 | |||
| 59 | #define CONFIG_UNLOCK_MAGIC (0x554E4C4B) | ||
| 60 | |||
| 61 | #endif /* __PLD_CONF00_H */ | ||
| 62 | |||
| 63 | |||
| 64 | |||
| 65 | |||
| 66 | |||
| 67 | |||
| 68 | |||
| 69 | |||
| 70 | |||
| 71 | |||
| 72 | |||
| 73 | |||
diff --git a/include/asm-arm/arch-epxa10db/system.h b/include/asm-arm/arch-epxa10db/system.h new file mode 100644 index 000000000000..345b092a1ed5 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/system.h | |||
| @@ -0,0 +1,41 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-epxa10db/system.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) 2000 Deep Blue Solutions Ltd | ||
| 6 | * Copyright (C) 2001 Altera Corporation | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | #ifndef __ASM_ARCH_SYSTEM_H | ||
| 23 | #define __ASM_ARCH_SYSTEM_H | ||
| 24 | |||
| 25 | #include <asm/arch/platform.h> | ||
| 26 | |||
| 27 | static inline void arch_idle(void) | ||
| 28 | { | ||
| 29 | /* | ||
| 30 | * This should do all the clock switching | ||
| 31 | * and wait for interrupt tricks | ||
| 32 | */ | ||
| 33 | cpu_do_idle(); | ||
| 34 | } | ||
| 35 | |||
| 36 | extern __inline__ void arch_reset(char mode) | ||
| 37 | { | ||
| 38 | /* Hmm... We can probably do something with the watchdog... */ | ||
| 39 | } | ||
| 40 | |||
| 41 | #endif | ||
diff --git a/include/asm-arm/arch-epxa10db/tdkphy.h b/include/asm-arm/arch-epxa10db/tdkphy.h new file mode 100644 index 000000000000..5e107bd4e109 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/tdkphy.h | |||
| @@ -0,0 +1,209 @@ | |||
| 1 | /* | ||
| 2 | * linux/drivers/tdkphy.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2001 Altera Corporation | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | #ifndef __TDKPHY_H | ||
| 22 | #define __TDKPHY_H | ||
| 23 | |||
| 24 | /* | ||
| 25 | * Register definitions for the TDK 78Q2120 PHY | ||
| 26 | * which is on the Camelot board | ||
| 27 | */ | ||
| 28 | |||
| 29 | /* | ||
| 30 | * Copyright (c) Altera Corporation 2000. | ||
| 31 | * All rights reserved. | ||
| 32 | */ | ||
| 33 | #define PHY_CONTROL (0) | ||
| 34 | #define PHY_CONTROL_COLT_MSK (0x80) | ||
| 35 | #define PHY_CONTROL_COLT_OFST (7) | ||
| 36 | #define PHY_CONTROL_DUPLEX_MSK (0x100) | ||
| 37 | #define PHY_CONTROL_DUPLEX_OFST (8) | ||
| 38 | #define PHY_CONTROL_RANEG_MSK (0x200) | ||
| 39 | #define PHY_CONTROL_RANEG_OFST (9) | ||
| 40 | #define PHY_CONTROL_ISO_MSK (0x400) | ||
| 41 | #define PHY_CONTROL_ISO_OFST (10) | ||
| 42 | #define PHY_CONTROL_PWRDN_MSK (0x800) | ||
| 43 | #define PHY_CONTROL_PWRDN_OFST (11) | ||
| 44 | #define PHY_CONTROL_ANEGEN_MSK (0x1000) | ||
| 45 | #define PHY_CONTROL_ANEGEN_OFST (12) | ||
| 46 | #define PHY_CONTROL_SPEEDSL_MSK (0x2000) | ||
| 47 | #define PHY_CONTROL_SPEEDSL_OFST (13) | ||
| 48 | #define PHY_CONTROL_LOOPBK_MSK (0x4000) | ||
| 49 | #define PHY_CONTROL_LOOPBK_OFST (14) | ||
| 50 | #define PHY_CONTROL_RESET_MSK (0x8000) | ||
| 51 | #define PHY_CONTROL_RESET_OFST (15) | ||
| 52 | |||
| 53 | #define PHY_STATUS (1) | ||
| 54 | #define PHY_STATUS_ETXD_MSK (0x1) | ||
| 55 | #define PHY_STATUS_EXTD_OFST (0) | ||
| 56 | #define PHY_STATUS_JAB_MSK (0x2) | ||
| 57 | #define PHY_STATUS_JAB_OFST (1) | ||
| 58 | #define PHY_STATUS_LINK_MSK (0x4) | ||
| 59 | #define PHY_STATUS_LINK_OFST (2) | ||
| 60 | #define PHY_STATUS_ANEGA_MSK (0x8) | ||
| 61 | #define PHY_STATUS_ANEGA_OFST (3) | ||
| 62 | #define PHY_STATUS_RFAULT_MSK (0x10) | ||
| 63 | #define PHY_STATUS_RFAULT_OFST (4) | ||
| 64 | #define PHY_STATUS_ANEGC_MSK (0x20) | ||
| 65 | #define PHY_STATUS_ANEGC_OFST (5) | ||
| 66 | #define PHY_STATUS_10T_H_MSK (0x800) | ||
| 67 | #define PHY_STATUS_10T_H_OFST (11) | ||
| 68 | #define PHY_STATUS_10T_F_MSK (0x1000) | ||
| 69 | #define PHY_STATUS_10T_F_OFST (12) | ||
| 70 | #define PHY_STATUS_100_X_H_MSK (0x2000) | ||
| 71 | #define PHY_STATUS_100_X_H_OFST (13) | ||
| 72 | #define PHY_STATUS_100_X_F_MSK (0x4000) | ||
| 73 | #define PHY_STATUS_100_X_F_OFST (14) | ||
| 74 | #define PHY_STATUS_100T4_MSK (0x8000) | ||
| 75 | #define PHY_STATUS_100T4_OFST (15) | ||
| 76 | |||
| 77 | #define PHY_ID1 (2) | ||
| 78 | #define PHY_ID1_OUI_MSK (0xFFFF) | ||
| 79 | #define PHY_ID1_OUI_OFST (0) | ||
| 80 | |||
| 81 | #define PHY_ID2 (3) | ||
| 82 | #define PHY_ID2_RN_MSK (0xF) | ||
| 83 | #define PHY_ID2_RN_OFST (0) | ||
| 84 | #define PHY_ID2_MN_MSK (0x3F0) | ||
| 85 | #define PHY_ID2_MN_OFST (4) | ||
| 86 | #define PHY_ID2_OUI_MSK (0xFC00) | ||
| 87 | #define PHY_ID2_OUI_OFST (10) | ||
| 88 | |||
| 89 | #define PHY_AUTO_NEG_ADVERTISEMENT (4) | ||
| 90 | #define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_MSK (0x1F) | ||
| 91 | #define PHY_AUTO_NEG_ADVERTISEMENT_SELECTOR_OFST (0) | ||
| 92 | #define PHY_AUTO_NEG_ADVERTISEMENT_A0_MSK (0x20) | ||
| 93 | #define PHY_AUTO_NEG_ADVERTISEMENT_A0_OFST (5) | ||
| 94 | #define PHY_AUTO_NEG_ADVERTISEMENT_A1_MSK (0x40) | ||
| 95 | #define PHY_AUTO_NEG_ADVERTISEMENT_A1_OFST (6) | ||
| 96 | #define PHY_AUTO_NEG_ADVERTISEMENT_A2_MSK (0x80) | ||
| 97 | #define PHY_AUTO_NEG_ADVERTISEMENT_A2_OFST (7) | ||
| 98 | #define PHY_AUTO_NEG_ADVERTISEMENT_A3_MSK (0x100) | ||
| 99 | #define PHY_AUTO_NEG_ADVERTISEMENT_A3_OFST (8) | ||
| 100 | #define PHY_AUTO_NEG_ADVERTISEMENT_A4_MSK (0x200) | ||
| 101 | #define PHY_AUTO_NEG_ADVERTISEMENT_A4_OFST (9) | ||
| 102 | #define PHY_AUTO_NEG_ADVERTISEMENT_TAF_MSK (0x1FE0) | ||
| 103 | #define PHY_AUTO_NEG_ADVERTISEMENT_TAF_OFST (5) | ||
| 104 | #define PHY_AUTO_NEG_ADVERTISEMENT_RF_MSK (0x2000) | ||
| 105 | #define PHY_AUTO_NEG_ADVERTISEMENT_RF_OFST (13) | ||
| 106 | #define PHY_AUTO_NEG_ADVERTISEMENT_RSVD_MSK (0x4000) | ||
| 107 | #define PHY_AUTO_NEG_ADVERTISEMENT_RVSD_OFST (14) | ||
| 108 | #define PHY_AUTO_NEG_ADVERTISEMENT_NP_MSK (0x8000) | ||
| 109 | #define PHY_AUTO_NEG_ADVERTISEMENT_NP_OFST (15) | ||
| 110 | |||
| 111 | #define PHY_AUTO_NEG_LINK_PARTNER (5) | ||
| 112 | #define PHY_AUTO_NEG_LINK_PARTNER_S4_MSK (0x1F) | ||
| 113 | #define PHY_AUTO_NEG_LINK_PARTNER_S4_OFST (0) | ||
| 114 | #define PHY_AUTO_NEG_LINK_PARTNER_A7_MSK (0x1FE0) | ||
| 115 | #define PHY_AUTO_NEG_LINK_PARTNER_A7_OFST (5) | ||
| 116 | #define PHY_AUTO_NEG_LINK_PARTNER_RF_MSK (0x2000) | ||
| 117 | #define PHY_AUTO_NEG_LINK_PARTNER_RF_OFST (13) | ||
| 118 | #define PHY_AUTO_NEG_LINK_PARTNER_ACK_MSK (0x4000) | ||
| 119 | #define PHY_AUTO_NEG_LINK_PARTNER_ACK_OFST (14) | ||
| 120 | #define PHY_AUTO_NEG_LINK_PARTNER_NP_MSK (0x8000) | ||
| 121 | #define PHY_AUTO_NEG_LINK_PARTNER_NP_OFST (15) | ||
| 122 | |||
| 123 | #define PHY_AUTO_NEG_EXPANSION (6) | ||
| 124 | #define PHY_AUTO_NEG_EXPANSION_LPANEGA_MSK (0x1) | ||
| 125 | #define PHY_AUTO_NEG_EXPANSION_LPANEGA_OFST (0) | ||
| 126 | #define PHY_AUTO_NEG_EXPANSION_PRX_MSK (0x2) | ||
| 127 | #define PHY_AUTO_NEG_EXPANSION_PRX_OFST (1) | ||
| 128 | #define PHY_AUTO_NEG_EXPANSION_NPA_MSK (0x4) | ||
| 129 | #define PHY_AUTO_NEG_EXPANSION_NPA_OFST (2) | ||
| 130 | #define PHY_AUTO_NEG_EXPANSION_LPNPA_MSK (0x8) | ||
| 131 | #define PHY_AUTO_NEG_EXPANSION_LPNPA_OFST (3) | ||
| 132 | #define PHY_AUTO_NEG_EXPANSION_PDF_MSK (0x10) | ||
| 133 | #define PHY_AUTO_NEG_EXPANSION_PDF_OFST (4) | ||
| 134 | |||
| 135 | #define PHY_VENDOR_SPECIFIC (16) | ||
| 136 | #define PHY_VENDOR_SPECIFIC_RXCC_MSK (0x1) | ||
| 137 | #define PHY_VENDOR_SPECIFIC_RXCC_OFST (0) | ||
| 138 | #define PHY_VENDOR_SPECIFIC_PCSBP_MSK (0x2) | ||
| 139 | #define PHY_VENDOR_SPECIFIC_PCSBP_OFST (1) | ||
| 140 | #define PHY_VENDOR_SPECIFIC_RVSPOL_MSK (0x10) | ||
| 141 | #define PHY_VENDOR_SPECIFIC_RVSPOL_OFST (4) | ||
| 142 | #define PHY_VENDOR_SPECIFIC_APOL_MSK (0x20) | ||
| 143 | #define PHY_VENDOR_SPECIFIC_APOL_OFST (5) | ||
| 144 | #define PHY_VENDOR_SPECIFIC_GPIO0_DIR_MSK (0x40) | ||
| 145 | #define PHY_VENDOR_SPECIFIC_GPIO0_DIR_OFST (6) | ||
| 146 | #define PHY_VENDOR_SPECIFIC_GPIO0_DAT_MSK (0x80) | ||
| 147 | #define PHY_VENDOR_SPECIFIC_GPIO0_DAT_OFST (7) | ||
| 148 | #define PHY_VENDOR_SPECIFIC_GPIO1_DIR_MSK (0x100) | ||
| 149 | #define PHY_VENDOR_SPECIFIC_GPIO1_DIR_OFST (8) | ||
| 150 | #define PHY_VENDOR_SPECIFIC_GPIO1_DAT_MSK (0x200) | ||
| 151 | #define PHY_VENDOR_SPECIFIC_GPIO1_DAT_OFST (9) | ||
| 152 | #define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_MSK (0x400) | ||
| 153 | #define PHY_VENDOR_SPECIFIC_10BT_NATURAL_LOOPBACK_DAT_OFST (10) | ||
| 154 | #define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_MSK (0x800) | ||
| 155 | #define PHY_VENDOR_SPECIFIC_10BT_SQE_TEST_INHIBIT_OFST (11) | ||
| 156 | #define PHY_VENDOR_SPECIFIC_TXHIM_MSK (0x1000) | ||
| 157 | #define PHY_VENDOR_SPECIFIC_TXHIM_OFST (12) | ||
| 158 | #define PHY_VENDOR_SPECIFIC_INT_LEVEL_MSK (0x4000) | ||
| 159 | #define PHY_VENDOR_SPECIFIC_INT_LEVEL_OFST (14) | ||
| 160 | #define PHY_VENDOR_SPECIFIC_RPTR_MSK (0x8000) | ||
| 161 | #define PHY_VENDOR_SPECIFIC_RPTR_OFST (15) | ||
| 162 | |||
| 163 | #define PHY_IRQ_CONTROL (17) | ||
| 164 | #define PHY_IRQ_CONTROL_ANEG_COMP_INT_MSK (0x1) | ||
| 165 | #define PHY_IRQ_CONTROL_ANEG_COMP_INT_OFST (0) | ||
| 166 | #define PHY_IRQ_CONTROL_RFAULT_INT_MSK (0x2) | ||
| 167 | #define PHY_IRQ_CONTROL_RFAULT_INT_OFST (1) | ||
| 168 | #define PHY_IRQ_CONTROL_LS_CHG_INT_MSK (0x4) | ||
| 169 | #define PHY_IRQ_CONTROL_LS_CHG_INT_OFST (2) | ||
| 170 | #define PHY_IRQ_CONTROL_LP_ACK_INT_MSK (0x8) | ||
| 171 | #define PHY_IRQ_CONTROL_LP_ACK_INT_OFST (3) | ||
| 172 | #define PHY_IRQ_CONTROL_PDF_INT_MSK (0x10) | ||
| 173 | #define PHY_IRQ_CONTROL_PDF_INT_OFST (4) | ||
| 174 | #define PHY_IRQ_CONTROL_PRX_INT_MSK (0x20) | ||
| 175 | #define PHY_IRQ_CONTROL_PRX_INT_OFST (5) | ||
| 176 | #define PHY_IRQ_CONTROL_RXER_INT_MSK (0x40) | ||
| 177 | #define PHY_IRQ_CONTROL_RXER_INT_OFST (6) | ||
| 178 | #define PHY_IRQ_CONTROL_JABBER_INT_MSK (0x80) | ||
| 179 | #define PHY_IRQ_CONTROL_JABBER_INT_OFST (7) | ||
| 180 | #define PHY_IRQ_CONTROL_ANEG_COMP_IE_MSK (0x100) | ||
| 181 | #define PHY_IRQ_CONTROL_ANEG_COMP_IE_OFST (8) | ||
| 182 | #define PHY_IRQ_CONTROL_RFAULT_IE_MSK (0x200) | ||
| 183 | #define PHY_IRQ_CONTROL_RFAULT_IE_OFST (9) | ||
| 184 | #define PHY_IRQ_CONTROL_LS_CHG_IE_MSK (0x400) | ||
| 185 | #define PHY_IRQ_CONTROL_LS_CHG_IE_OFST (10) | ||
| 186 | #define PHY_IRQ_CONTROL_LP_ACK_IE_MSK (0x800) | ||
| 187 | #define PHY_IRQ_CONTROL_LP_ACK_IE_OFST (11) | ||
| 188 | #define PHY_IRQ_CONTROL_PDF_IE_MSK (0x1000) | ||
| 189 | #define PHY_IRQ_CONTROL_PDF_IE_OFST (12) | ||
| 190 | #define PHY_IRQ_CONTROL_PRX_IE_MSK (0x2000) | ||
| 191 | #define PHY_IRQ_CONTROL_PRX_IE_OFST (13) | ||
| 192 | #define PHY_IRQ_CONTROL_RXER_IE_MSK (0x4000) | ||
| 193 | #define PHY_IRQ_CONTROL_RXER_IE_OFST (14) | ||
| 194 | #define PHY_IRQ_CONTROL_JABBER_IE_MSK (0x8000) | ||
| 195 | #define PHY_IRQ_CONTROL_JABBER_IE_OFST (15) | ||
| 196 | |||
| 197 | #define PHY_DIAGNOSTIC (18) | ||
| 198 | #define PHY_DIAGNOSTIC_RX_LOCK_MSK (0x100) | ||
| 199 | #define PHY_DIAGNOSTIC_RX_LOCK_OFST (8) | ||
| 200 | #define PHY_DIAGNOSTIC_RX_PASS_MSK (0x200) | ||
| 201 | #define PHY_DIAGNOSTIC_RX_PASS_OFST (9) | ||
| 202 | #define PHY_DIAGNOSTIC_RATE_MSK (0x400) | ||
| 203 | #define PHY_DIAGNOSTIC_RATE_OFST (10) | ||
| 204 | #define PHY_DIAGNOSTIC_DPLX_MSK (0x800) | ||
| 205 | #define PHY_DIAGNOSTIC_DPLX_OFST (11) | ||
| 206 | #define PHY_DIAGNOSTIC_ANEGF_MSK (0x1000) | ||
| 207 | #define PHY_DIAGNOSTIC_ANEGF_OFST (12) | ||
| 208 | |||
| 209 | #endif /* __TDKPHY_H */ | ||
diff --git a/include/asm-arm/arch-epxa10db/timer00.h b/include/asm-arm/arch-epxa10db/timer00.h new file mode 100644 index 000000000000..52a3fb58b59d --- /dev/null +++ b/include/asm-arm/arch-epxa10db/timer00.h | |||
| @@ -0,0 +1,98 @@ | |||
| 1 | /* | ||
| 2 | * | ||
| 3 | * This file contains the register definitions for the Excalibur | ||
| 4 | * Timer TIMER00. | ||
| 5 | * | ||
| 6 | * Copyright (C) 2001 Altera Corporation | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | #ifndef __TIMER00_H | ||
| 23 | #define __TIMER00_H | ||
| 24 | |||
| 25 | /* | ||
| 26 | * Register definitions for the timers | ||
| 27 | */ | ||
| 28 | |||
| 29 | |||
| 30 | #define TIMER0_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 )) | ||
| 31 | #define TIMER0_CR_B_MSK (0x20) | ||
| 32 | #define TIMER0_CR_B_OFST (0x5) | ||
| 33 | #define TIMER0_CR_S_MSK (0x10) | ||
| 34 | #define TIMER0_CR_S_OFST (0x4) | ||
| 35 | #define TIMER0_CR_CI_MSK (0x08) | ||
| 36 | #define TIMER0_CR_CI_OFST (0x3) | ||
| 37 | #define TIMER0_CR_IE_MSK (0x04) | ||
| 38 | #define TIMER0_CR_IE_OFST (0x2) | ||
| 39 | #define TIMER0_CR_MODE_MSK (0x3) | ||
| 40 | #define TIMER0_CR_MODE_OFST (0) | ||
| 41 | #define TIMER0_CR_MODE_FREE (0) | ||
| 42 | #define TIMER0_CR_MODE_ONE (1) | ||
| 43 | #define TIMER0_CR_MODE_INTVL (2) | ||
| 44 | |||
| 45 | #define TIMER0_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x00 )) | ||
| 46 | #define TIMER0_SR_B_MSK (0x20) | ||
| 47 | #define TIMER0_SR_B_OFST (0x5) | ||
| 48 | #define TIMER0_SR_S_MSK (0x10) | ||
| 49 | #define TIMER0_SR_S_OFST (0x4) | ||
| 50 | #define TIMER0_SR_CI_MSK (0x08) | ||
| 51 | #define TIMER0_SR_CI_OFST (0x3) | ||
| 52 | #define TIMER0_SR_IE_MSK (0x04) | ||
| 53 | #define TIMER0_SR_IE_OFST (0x2) | ||
| 54 | #define TIMER0_SR_MODE_MSK (0x3) | ||
| 55 | #define TIMER0_SR_MODE_OFST (0) | ||
| 56 | #define TIMER0_SR_MODE_FREE (0) | ||
| 57 | #define TIMER0_SR_MODE_ONE (1) | ||
| 58 | #define TIMER0_SR_MODE_INTVL (2) | ||
| 59 | |||
| 60 | #define TIMER0_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x010 )) | ||
| 61 | #define TIMER0_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x020 )) | ||
| 62 | #define TIMER0_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x030 )) | ||
| 63 | |||
| 64 | #define TIMER1_CR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 )) | ||
| 65 | #define TIMER1_CR_B_MSK (0x20) | ||
| 66 | #define TIMER1_CR_B_OFST (0x5) | ||
| 67 | #define TIMER1_CR_S_MSK (0x10) | ||
| 68 | #define TIMER1_CR_S_OFST (0x4) | ||
| 69 | #define TIMER1_CR_CI_MSK (0x08) | ||
| 70 | #define TIMER1_CR_CI_OFST (0x3) | ||
| 71 | #define TIMER1_CR_IE_MSK (0x04) | ||
| 72 | #define TIMER1_CR_IE_OFST (0x2) | ||
| 73 | #define TIMER1_CR_MODE_MSK (0x3) | ||
| 74 | #define TIMER1_CR_MODE_OFST (0) | ||
| 75 | #define TIMER1_CR_MODE_FREE (0) | ||
| 76 | #define TIMER1_CR_MODE_ONE (1) | ||
| 77 | #define TIMER1_CR_MODE_INTVL (2) | ||
| 78 | |||
| 79 | #define TIMER1_SR(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x40 )) | ||
| 80 | #define TIMER1_SR_B_MSK (0x20) | ||
| 81 | #define TIMER1_SR_B_OFST (0x5) | ||
| 82 | #define TIMER1_SR_S_MSK (0x10) | ||
| 83 | #define TIMER1_SR_S_OFST (0x4) | ||
| 84 | #define TIMER1_SR_CI_MSK (0x08) | ||
| 85 | #define TIMER1_SR_CI_OFST (0x3) | ||
| 86 | #define TIMER1_SR_IE_MSK (0x04) | ||
| 87 | #define TIMER1_SR_IE_OFST (0x2) | ||
| 88 | #define TIMER1_SR_MODE_MSK (0x3) | ||
| 89 | #define TIMER1_SR_MODE_OFST (0) | ||
| 90 | #define TIMER1_SR_MODE_FREE (0) | ||
| 91 | #define TIMER1_SR_MODE_ONE (1) | ||
| 92 | #define TIMER1_SR_MODE_INTVL (2) | ||
| 93 | |||
| 94 | #define TIMER1_PRESCALE(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x050 )) | ||
| 95 | #define TIMER1_LIMIT(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x060 )) | ||
| 96 | #define TIMER1_READ(BASE_ADDR) (TIMER00_TYPE (BASE_ADDR + 0x070 )) | ||
| 97 | |||
| 98 | #endif /* __TIMER00_H */ | ||
diff --git a/include/asm-arm/arch-epxa10db/timex.h b/include/asm-arm/arch-epxa10db/timex.h new file mode 100644 index 000000000000..b87a75fc9589 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/timex.h | |||
| @@ -0,0 +1,26 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-epxa10db/timex.h | ||
| 3 | * | ||
| 4 | * Excalibur timex specifications | ||
| 5 | * | ||
| 6 | * Copyright (C) 2001 Altera Corporation | ||
| 7 | * | ||
| 8 | * This program is free software; you can redistribute it and/or modify | ||
| 9 | * it under the terms of the GNU General Public License as published by | ||
| 10 | * the Free Software Foundation; either version 2 of the License, or | ||
| 11 | * (at your option) any later version. | ||
| 12 | * | ||
| 13 | * This program is distributed in the hope that it will be useful, | ||
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 16 | * GNU General Public License for more details. | ||
| 17 | * | ||
| 18 | * You should have received a copy of the GNU General Public License | ||
| 19 | * along with this program; if not, write to the Free Software | ||
| 20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 21 | */ | ||
| 22 | |||
| 23 | /* | ||
| 24 | * ?? | ||
| 25 | */ | ||
| 26 | #define CLOCK_TICK_RATE (50000000 / 16) | ||
diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h new file mode 100644 index 000000000000..5abd8914d68b --- /dev/null +++ b/include/asm-arm/arch-epxa10db/uart00.h | |||
| @@ -0,0 +1,181 @@ | |||
| 1 | /* * | ||
| 2 | * Copyright (C) 2001 Altera Corporation | ||
| 3 | * | ||
| 4 | * This program is free software; you can redistribute it and/or modify | ||
| 5 | * it under the terms of the GNU General Public License as published by | ||
| 6 | * the Free Software Foundation; either version 2 of the License, or | ||
| 7 | * (at your option) any later version. | ||
| 8 | * | ||
| 9 | * This program is distributed in the hope that it will be useful, | ||
| 10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 12 | * GNU General Public License for more details. | ||
| 13 | * | ||
| 14 | * You should have received a copy of the GNU General Public License | ||
| 15 | * along with this program; if not, write to the Free Software | ||
| 16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 17 | */ | ||
| 18 | #ifndef __UART00_H | ||
| 19 | #define __UART00_H | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Register definitions for the UART | ||
| 23 | */ | ||
| 24 | |||
| 25 | #define UART_TX_FIFO_SIZE (15) | ||
| 26 | |||
| 27 | #define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x00 )) | ||
| 28 | #define UART_RSR_RX_LEVEL_MSK (0x1f) | ||
| 29 | #define UART_RSR_RX_LEVEL_OFST (0) | ||
| 30 | #define UART_RSR_RE_MSK (0x80) | ||
| 31 | #define UART_RSR_RE_OFST (7) | ||
| 32 | |||
| 33 | #define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x04 )) | ||
| 34 | #define UART_RDS_BI_MSK (0x8) | ||
| 35 | #define UART_RDS_BI_OFST (4) | ||
| 36 | #define UART_RDS_FE_MSK (0x4) | ||
| 37 | #define UART_RDS_FE_OFST (2) | ||
| 38 | #define UART_RDS_PE_MSK (0x2) | ||
| 39 | #define UART_RDS_PE_OFST (1) | ||
| 40 | #define UART_RDS_OE_MSK (0x1) | ||
| 41 | #define UART_RDS_OE_OFST (0) | ||
| 42 | |||
| 43 | #define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x08 )) | ||
| 44 | #define UART_RD_RX_DATA_MSK (0xff) | ||
| 45 | #define UART_RD_RX_DATA_OFST (0) | ||
| 46 | |||
| 47 | #define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x0c )) | ||
| 48 | #define UART_TSR_TX_LEVEL_MSK (0x1f) | ||
| 49 | #define UART_TSR_TX_LEVEL_OFST (0) | ||
| 50 | #define UART_TSR_TXI_MSK (0x80) | ||
| 51 | #define UART_TSR_TXI_OFST (7) | ||
| 52 | |||
| 53 | #define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x10 )) | ||
| 54 | #define UART_TD_TX_DATA_MSK (0xff) | ||
| 55 | #define UART_TD_TX_DATA_OFST (0) | ||
| 56 | |||
| 57 | #define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x14 )) | ||
| 58 | #define UART_FCR_RX_THR_MSK (0xd0) | ||
| 59 | #define UART_FCR_RX_THR_OFST (5) | ||
| 60 | #define UART_FCR_RX_THR_1 (0x00) | ||
| 61 | #define UART_FCR_RX_THR_2 (0x20) | ||
| 62 | #define UART_FCR_RX_THR_4 (0x40) | ||
| 63 | #define UART_FCR_RX_THR_6 (0x60) | ||
| 64 | #define UART_FCR_RX_THR_8 (0x80) | ||
| 65 | #define UART_FCR_RX_THR_10 (0xa0) | ||
| 66 | #define UART_FCR_RX_THR_12 (0xc0) | ||
| 67 | #define UART_FCR_RX_THR_14 (0xd0) | ||
| 68 | #define UART_FCR_TX_THR_MSK (0x1c) | ||
| 69 | #define UART_FCR_TX_THR_OFST (2) | ||
| 70 | #define UART_FCR_TX_THR_0 (0x00) | ||
| 71 | #define UART_FCR_TX_THR_2 (0x04) | ||
| 72 | #define UART_FCR_TX_THR_4 (0x08) | ||
| 73 | #define UART_FCR_TX_THR_8 (0x0c) | ||
| 74 | #define UART_FCR_TX_THR_10 (0x10) | ||
| 75 | #define UART_FCR_TX_THR_12 (0x14) | ||
| 76 | #define UART_FCR_TX_THR_14 (0x18) | ||
| 77 | #define UART_FCR_TX_THR_15 (0x1c) | ||
| 78 | #define UART_FCR_RC_MSK (0x02) | ||
| 79 | #define UART_FCR_RC_OFST (1) | ||
| 80 | #define UART_FCR_TC_MSK (0x01) | ||
| 81 | #define UART_FCR_TC_OFST (0) | ||
| 82 | |||
| 83 | #define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x18 )) | ||
| 84 | #define UART_IES_ME_MSK (0x8) | ||
| 85 | #define UART_IES_ME_OFST (3) | ||
| 86 | #define UART_IES_TIE_MSK (0x4) | ||
| 87 | #define UART_IES_TIE_OFST (2) | ||
| 88 | #define UART_IES_TE_MSK (0x2) | ||
| 89 | #define UART_IES_TE_OFST (1) | ||
| 90 | #define UART_IES_RE_MSK (0x1) | ||
| 91 | #define UART_IES_RE_OFST (0) | ||
| 92 | |||
| 93 | #define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x1c )) | ||
| 94 | #define UART_IEC_ME_MSK (0x8) | ||
| 95 | #define UART_IEC_ME_OFST (3) | ||
| 96 | #define UART_IEC_TIE_MSK (0x4) | ||
| 97 | #define UART_IEC_TIE_OFST (2) | ||
| 98 | #define UART_IEC_TE_MSK (0x2) | ||
| 99 | #define UART_IEC_TE_OFST (1) | ||
| 100 | #define UART_IEC_RE_MSK (0x1) | ||
| 101 | #define UART_IEC_RE_OFST (0) | ||
| 102 | |||
| 103 | #define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x20 )) | ||
| 104 | #define UART_ISR_MI_MSK (0x8) | ||
| 105 | #define UART_ISR_MI_OFST (3) | ||
| 106 | #define UART_ISR_TII_MSK (0x4) | ||
| 107 | #define UART_ISR_TII_OFST (2) | ||
| 108 | #define UART_ISR_TI_MSK (0x2) | ||
| 109 | #define UART_ISR_TI_OFST (1) | ||
| 110 | #define UART_ISR_RI_MSK (0x1) | ||
| 111 | #define UART_ISR_RI_OFST (0) | ||
| 112 | |||
| 113 | #define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x24 )) | ||
| 114 | #define UART_IID_IID_MSK (0x7) | ||
| 115 | #define UART_IID_IID_OFST (0) | ||
| 116 | |||
| 117 | #define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x28 )) | ||
| 118 | #define UART_MC_OE_MSK (0x40) | ||
| 119 | #define UART_MC_OE_OFST (6) | ||
| 120 | #define UART_MC_SP_MSK (0x20) | ||
| 121 | #define UART_MC_SP_OFST (5) | ||
| 122 | #define UART_MC_EP_MSK (0x10) | ||
| 123 | #define UART_MC_EP_OFST (4) | ||
| 124 | #define UART_MC_PE_MSK (0x08) | ||
| 125 | #define UART_MC_PE_OFST (3) | ||
| 126 | #define UART_MC_ST_MSK (0x04) | ||
| 127 | #define UART_MC_ST_ONE (0x0) | ||
| 128 | #define UART_MC_ST_TWO (0x04) | ||
| 129 | #define UART_MC_ST_OFST (2) | ||
| 130 | #define UART_MC_CLS_MSK (0x03) | ||
| 131 | #define UART_MC_CLS_OFST (0) | ||
| 132 | #define UART_MC_CLS_CHARLEN_5 (0) | ||
| 133 | #define UART_MC_CLS_CHARLEN_6 (1) | ||
| 134 | #define UART_MC_CLS_CHARLEN_7 (2) | ||
| 135 | #define UART_MC_CLS_CHARLEN_8 (3) | ||
| 136 | |||
| 137 | #define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x2c )) | ||
| 138 | #define UART_MCR_AC_MSK (0x80) | ||
| 139 | #define UART_MCR_AC_OFST (7) | ||
| 140 | #define UART_MCR_AR_MSK (0x40) | ||
| 141 | #define UART_MCR_AR_OFST (6) | ||
| 142 | #define UART_MCR_BR_MSK (0x20) | ||
| 143 | #define UART_MCR_BR_OFST (5) | ||
| 144 | #define UART_MCR_LB_MSK (0x10) | ||
| 145 | #define UART_MCR_LB_OFST (4) | ||
| 146 | #define UART_MCR_DCD_MSK (0x08) | ||
| 147 | #define UART_MCR_DCD_OFST (3) | ||
| 148 | #define UART_MCR_RI_MSK (0x04) | ||
| 149 | #define UART_MCR_RI_OFST (2) | ||
| 150 | #define UART_MCR_DTR_MSK (0x02) | ||
| 151 | #define UART_MCR_DTR_OFST (1) | ||
| 152 | #define UART_MCR_RTS_MSK (0x01) | ||
| 153 | #define UART_MCR_RTS_OFST (0) | ||
| 154 | |||
| 155 | #define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x30 )) | ||
| 156 | #define UART_MSR_DCD_MSK (0x80) | ||
| 157 | #define UART_MSR_DCD_OFST (7) | ||
| 158 | #define UART_MSR_RI_MSK (0x40) | ||
| 159 | #define UART_MSR_RI_OFST (6) | ||
| 160 | #define UART_MSR_DSR_MSK (0x20) | ||
| 161 | #define UART_MSR_DSR_OFST (5) | ||
| 162 | #define UART_MSR_CTS_MSK (0x10) | ||
| 163 | #define UART_MSR_CTS_OFST (4) | ||
| 164 | #define UART_MSR_DDCD_MSK (0x08) | ||
| 165 | #define UART_MSR_DDCD_OFST (3) | ||
| 166 | #define UART_MSR_TERI_MSK (0x04) | ||
| 167 | #define UART_MSR_TERI_OFST (2) | ||
| 168 | #define UART_MSR_DDSR_MSK (0x02) | ||
| 169 | #define UART_MSR_DDSR_OFST (1) | ||
| 170 | #define UART_MSR_DCTS_MSK (0x01) | ||
| 171 | #define UART_MSR_DCTS_OFST (0) | ||
| 172 | |||
| 173 | #define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x34 )) | ||
| 174 | #define UART_DIV_LO_DIV_MSK (0xff) | ||
| 175 | #define UART_DIV_LO_DIV_OFST (0) | ||
| 176 | |||
| 177 | #define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x38 )) | ||
| 178 | #define UART_DIV_HI_DIV_MSK (0xff) | ||
| 179 | #define UART_DIV_HI_DIV_OFST (0) | ||
| 180 | |||
| 181 | #endif /* __UART00_H */ | ||
diff --git a/include/asm-arm/arch-epxa10db/uncompress.h b/include/asm-arm/arch-epxa10db/uncompress.h new file mode 100644 index 000000000000..d33ad6a93749 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/uncompress.h | |||
| @@ -0,0 +1,54 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-epxa10db/uncompress.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 1999 ARM Limited | ||
| 5 | * Copyright (C) 2001 Altera Corporation | ||
| 6 | * | ||
| 7 | * This program is free software; you can redistribute it and/or modify | ||
| 8 | * it under the terms of the GNU General Public License as published by | ||
| 9 | * the Free Software Foundation; either version 2 of the License, or | ||
| 10 | * (at your option) any later version. | ||
| 11 | * | ||
| 12 | * This program is distributed in the hope that it will be useful, | ||
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 15 | * GNU General Public License for more details. | ||
| 16 | * | ||
| 17 | * You should have received a copy of the GNU General Public License | ||
| 18 | * along with this program; if not, write to the Free Software | ||
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 20 | */ | ||
| 21 | #include "asm/arch/platform.h" | ||
| 22 | #include "asm/arch/hardware.h" | ||
| 23 | #define UART00_TYPE (volatile unsigned int*) | ||
| 24 | #include "asm/arch/uart00.h" | ||
| 25 | |||
| 26 | /* | ||
| 27 | * This does not append a newline | ||
| 28 | */ | ||
| 29 | static void putstr(const char *s) | ||
| 30 | { | ||
| 31 | while (*s) { | ||
| 32 | while ((*UART_TSR(EXC_UART00_BASE) & | ||
| 33 | UART_TSR_TX_LEVEL_MSK)==15) | ||
| 34 | barrier(); | ||
| 35 | |||
| 36 | *UART_TD(EXC_UART00_BASE) = *s; | ||
| 37 | |||
| 38 | if (*s == '\n') { | ||
| 39 | while ((*UART_TSR(EXC_UART00_BASE) & | ||
| 40 | UART_TSR_TX_LEVEL_MSK)==15) | ||
| 41 | barrier(); | ||
| 42 | |||
| 43 | *UART_TD(EXC_UART00_BASE) = '\r'; | ||
| 44 | } | ||
| 45 | s++; | ||
| 46 | } | ||
| 47 | } | ||
| 48 | |||
| 49 | /* | ||
| 50 | * nothing to do | ||
| 51 | */ | ||
| 52 | #define arch_decomp_setup() | ||
| 53 | |||
| 54 | #define arch_decomp_wdog() | ||
diff --git a/include/asm-arm/arch-epxa10db/vmalloc.h b/include/asm-arm/arch-epxa10db/vmalloc.h new file mode 100644 index 000000000000..d31ef8584760 --- /dev/null +++ b/include/asm-arm/arch-epxa10db/vmalloc.h | |||
| @@ -0,0 +1,31 @@ | |||
| 1 | /* | ||
| 2 | * linux/include/asm-arm/arch-epxa10db/vmalloc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2000 Russell King. | ||
| 5 | * | ||
| 6 | * This program is free software; you can redistribute it and/or modify | ||
| 7 | * it under the terms of the GNU General Public License as published by | ||
| 8 | * the Free Software Foundation; either version 2 of the License, or | ||
| 9 | * (at your option) any later version. | ||
| 10 | * | ||
| 11 | * This program is distributed in the hope that it will be useful, | ||
| 12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| 13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| 14 | * GNU General Public License for more details. | ||
| 15 | * | ||
| 16 | * You should have received a copy of the GNU General Public License | ||
| 17 | * along with this program; if not, write to the Free Software | ||
| 18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
| 19 | */ | ||
| 20 | |||
| 21 | /* | ||
| 22 | * Just any arbitrary offset to the start of the vmalloc VM area: the | ||
| 23 | * current 8MB value just means that there will be a 8MB "hole" after the | ||
| 24 | * physical memory until the kernel virtual memory starts. That means that | ||
| 25 | * any out-of-bounds memory accesses will hopefully be caught. | ||
| 26 | * The vmalloc() routines leaves a hole of 4kB between each vmalloced | ||
| 27 | * area for the same reason. ;) | ||
| 28 | */ | ||
| 29 | #define VMALLOC_OFFSET (8*1024*1024) | ||
| 30 | #define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)) | ||
| 31 | #define VMALLOC_END (PAGE_OFFSET + 0x10000000) | ||