diff options
Diffstat (limited to 'include/asm-arm/arch-epxa10db/uart00.h')
-rw-r--r-- | include/asm-arm/arch-epxa10db/uart00.h | 181 |
1 files changed, 181 insertions, 0 deletions
diff --git a/include/asm-arm/arch-epxa10db/uart00.h b/include/asm-arm/arch-epxa10db/uart00.h new file mode 100644 index 000000000000..5abd8914d68b --- /dev/null +++ b/include/asm-arm/arch-epxa10db/uart00.h | |||
@@ -0,0 +1,181 @@ | |||
1 | /* * | ||
2 | * Copyright (C) 2001 Altera Corporation | ||
3 | * | ||
4 | * This program is free software; you can redistribute it and/or modify | ||
5 | * it under the terms of the GNU General Public License as published by | ||
6 | * the Free Software Foundation; either version 2 of the License, or | ||
7 | * (at your option) any later version. | ||
8 | * | ||
9 | * This program is distributed in the hope that it will be useful, | ||
10 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
11 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
12 | * GNU General Public License for more details. | ||
13 | * | ||
14 | * You should have received a copy of the GNU General Public License | ||
15 | * along with this program; if not, write to the Free Software | ||
16 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | ||
17 | */ | ||
18 | #ifndef __UART00_H | ||
19 | #define __UART00_H | ||
20 | |||
21 | /* | ||
22 | * Register definitions for the UART | ||
23 | */ | ||
24 | |||
25 | #define UART_TX_FIFO_SIZE (15) | ||
26 | |||
27 | #define UART_RSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x00 )) | ||
28 | #define UART_RSR_RX_LEVEL_MSK (0x1f) | ||
29 | #define UART_RSR_RX_LEVEL_OFST (0) | ||
30 | #define UART_RSR_RE_MSK (0x80) | ||
31 | #define UART_RSR_RE_OFST (7) | ||
32 | |||
33 | #define UART_RDS(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x04 )) | ||
34 | #define UART_RDS_BI_MSK (0x8) | ||
35 | #define UART_RDS_BI_OFST (4) | ||
36 | #define UART_RDS_FE_MSK (0x4) | ||
37 | #define UART_RDS_FE_OFST (2) | ||
38 | #define UART_RDS_PE_MSK (0x2) | ||
39 | #define UART_RDS_PE_OFST (1) | ||
40 | #define UART_RDS_OE_MSK (0x1) | ||
41 | #define UART_RDS_OE_OFST (0) | ||
42 | |||
43 | #define UART_RD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x08 )) | ||
44 | #define UART_RD_RX_DATA_MSK (0xff) | ||
45 | #define UART_RD_RX_DATA_OFST (0) | ||
46 | |||
47 | #define UART_TSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x0c )) | ||
48 | #define UART_TSR_TX_LEVEL_MSK (0x1f) | ||
49 | #define UART_TSR_TX_LEVEL_OFST (0) | ||
50 | #define UART_TSR_TXI_MSK (0x80) | ||
51 | #define UART_TSR_TXI_OFST (7) | ||
52 | |||
53 | #define UART_TD(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x10 )) | ||
54 | #define UART_TD_TX_DATA_MSK (0xff) | ||
55 | #define UART_TD_TX_DATA_OFST (0) | ||
56 | |||
57 | #define UART_FCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x14 )) | ||
58 | #define UART_FCR_RX_THR_MSK (0xd0) | ||
59 | #define UART_FCR_RX_THR_OFST (5) | ||
60 | #define UART_FCR_RX_THR_1 (0x00) | ||
61 | #define UART_FCR_RX_THR_2 (0x20) | ||
62 | #define UART_FCR_RX_THR_4 (0x40) | ||
63 | #define UART_FCR_RX_THR_6 (0x60) | ||
64 | #define UART_FCR_RX_THR_8 (0x80) | ||
65 | #define UART_FCR_RX_THR_10 (0xa0) | ||
66 | #define UART_FCR_RX_THR_12 (0xc0) | ||
67 | #define UART_FCR_RX_THR_14 (0xd0) | ||
68 | #define UART_FCR_TX_THR_MSK (0x1c) | ||
69 | #define UART_FCR_TX_THR_OFST (2) | ||
70 | #define UART_FCR_TX_THR_0 (0x00) | ||
71 | #define UART_FCR_TX_THR_2 (0x04) | ||
72 | #define UART_FCR_TX_THR_4 (0x08) | ||
73 | #define UART_FCR_TX_THR_8 (0x0c) | ||
74 | #define UART_FCR_TX_THR_10 (0x10) | ||
75 | #define UART_FCR_TX_THR_12 (0x14) | ||
76 | #define UART_FCR_TX_THR_14 (0x18) | ||
77 | #define UART_FCR_TX_THR_15 (0x1c) | ||
78 | #define UART_FCR_RC_MSK (0x02) | ||
79 | #define UART_FCR_RC_OFST (1) | ||
80 | #define UART_FCR_TC_MSK (0x01) | ||
81 | #define UART_FCR_TC_OFST (0) | ||
82 | |||
83 | #define UART_IES(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x18 )) | ||
84 | #define UART_IES_ME_MSK (0x8) | ||
85 | #define UART_IES_ME_OFST (3) | ||
86 | #define UART_IES_TIE_MSK (0x4) | ||
87 | #define UART_IES_TIE_OFST (2) | ||
88 | #define UART_IES_TE_MSK (0x2) | ||
89 | #define UART_IES_TE_OFST (1) | ||
90 | #define UART_IES_RE_MSK (0x1) | ||
91 | #define UART_IES_RE_OFST (0) | ||
92 | |||
93 | #define UART_IEC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x1c )) | ||
94 | #define UART_IEC_ME_MSK (0x8) | ||
95 | #define UART_IEC_ME_OFST (3) | ||
96 | #define UART_IEC_TIE_MSK (0x4) | ||
97 | #define UART_IEC_TIE_OFST (2) | ||
98 | #define UART_IEC_TE_MSK (0x2) | ||
99 | #define UART_IEC_TE_OFST (1) | ||
100 | #define UART_IEC_RE_MSK (0x1) | ||
101 | #define UART_IEC_RE_OFST (0) | ||
102 | |||
103 | #define UART_ISR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x20 )) | ||
104 | #define UART_ISR_MI_MSK (0x8) | ||
105 | #define UART_ISR_MI_OFST (3) | ||
106 | #define UART_ISR_TII_MSK (0x4) | ||
107 | #define UART_ISR_TII_OFST (2) | ||
108 | #define UART_ISR_TI_MSK (0x2) | ||
109 | #define UART_ISR_TI_OFST (1) | ||
110 | #define UART_ISR_RI_MSK (0x1) | ||
111 | #define UART_ISR_RI_OFST (0) | ||
112 | |||
113 | #define UART_IID(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x24 )) | ||
114 | #define UART_IID_IID_MSK (0x7) | ||
115 | #define UART_IID_IID_OFST (0) | ||
116 | |||
117 | #define UART_MC(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x28 )) | ||
118 | #define UART_MC_OE_MSK (0x40) | ||
119 | #define UART_MC_OE_OFST (6) | ||
120 | #define UART_MC_SP_MSK (0x20) | ||
121 | #define UART_MC_SP_OFST (5) | ||
122 | #define UART_MC_EP_MSK (0x10) | ||
123 | #define UART_MC_EP_OFST (4) | ||
124 | #define UART_MC_PE_MSK (0x08) | ||
125 | #define UART_MC_PE_OFST (3) | ||
126 | #define UART_MC_ST_MSK (0x04) | ||
127 | #define UART_MC_ST_ONE (0x0) | ||
128 | #define UART_MC_ST_TWO (0x04) | ||
129 | #define UART_MC_ST_OFST (2) | ||
130 | #define UART_MC_CLS_MSK (0x03) | ||
131 | #define UART_MC_CLS_OFST (0) | ||
132 | #define UART_MC_CLS_CHARLEN_5 (0) | ||
133 | #define UART_MC_CLS_CHARLEN_6 (1) | ||
134 | #define UART_MC_CLS_CHARLEN_7 (2) | ||
135 | #define UART_MC_CLS_CHARLEN_8 (3) | ||
136 | |||
137 | #define UART_MCR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x2c )) | ||
138 | #define UART_MCR_AC_MSK (0x80) | ||
139 | #define UART_MCR_AC_OFST (7) | ||
140 | #define UART_MCR_AR_MSK (0x40) | ||
141 | #define UART_MCR_AR_OFST (6) | ||
142 | #define UART_MCR_BR_MSK (0x20) | ||
143 | #define UART_MCR_BR_OFST (5) | ||
144 | #define UART_MCR_LB_MSK (0x10) | ||
145 | #define UART_MCR_LB_OFST (4) | ||
146 | #define UART_MCR_DCD_MSK (0x08) | ||
147 | #define UART_MCR_DCD_OFST (3) | ||
148 | #define UART_MCR_RI_MSK (0x04) | ||
149 | #define UART_MCR_RI_OFST (2) | ||
150 | #define UART_MCR_DTR_MSK (0x02) | ||
151 | #define UART_MCR_DTR_OFST (1) | ||
152 | #define UART_MCR_RTS_MSK (0x01) | ||
153 | #define UART_MCR_RTS_OFST (0) | ||
154 | |||
155 | #define UART_MSR(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x30 )) | ||
156 | #define UART_MSR_DCD_MSK (0x80) | ||
157 | #define UART_MSR_DCD_OFST (7) | ||
158 | #define UART_MSR_RI_MSK (0x40) | ||
159 | #define UART_MSR_RI_OFST (6) | ||
160 | #define UART_MSR_DSR_MSK (0x20) | ||
161 | #define UART_MSR_DSR_OFST (5) | ||
162 | #define UART_MSR_CTS_MSK (0x10) | ||
163 | #define UART_MSR_CTS_OFST (4) | ||
164 | #define UART_MSR_DDCD_MSK (0x08) | ||
165 | #define UART_MSR_DDCD_OFST (3) | ||
166 | #define UART_MSR_TERI_MSK (0x04) | ||
167 | #define UART_MSR_TERI_OFST (2) | ||
168 | #define UART_MSR_DDSR_MSK (0x02) | ||
169 | #define UART_MSR_DDSR_OFST (1) | ||
170 | #define UART_MSR_DCTS_MSK (0x01) | ||
171 | #define UART_MSR_DCTS_OFST (0) | ||
172 | |||
173 | #define UART_DIV_LO(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x34 )) | ||
174 | #define UART_DIV_LO_DIV_MSK (0xff) | ||
175 | #define UART_DIV_LO_DIV_OFST (0) | ||
176 | |||
177 | #define UART_DIV_HI(BASE_ADDR) (UART00_TYPE (BASE_ADDR + 0x38 )) | ||
178 | #define UART_DIV_HI_DIV_MSK (0xff) | ||
179 | #define UART_DIV_HI_DIV_OFST (0) | ||
180 | |||
181 | #endif /* __UART00_H */ | ||