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-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200.h118
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_sys.h3
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_twi.h57
-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_usart.h123
-rw-r--r--include/asm-arm/arch-at91rm9200/board.h5
-rw-r--r--include/asm-arm/arch-at91rm9200/gpio.h18
-rw-r--r--include/asm-arm/arch-at91rm9200/hardware.h30
-rw-r--r--include/asm-arm/arch-at91rm9200/irqs.h2
8 files changed, 146 insertions, 210 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200.h b/include/asm-arm/arch-at91rm9200/at91rm9200.h
index 58f40931a5c1..a5a86b1ff886 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200.h
@@ -19,67 +19,80 @@
19/* 19/*
20 * Peripheral identifiers/interrupts. 20 * Peripheral identifiers/interrupts.
21 */ 21 */
22#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 22#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
23#define AT91_ID_SYS 1 /* System Peripheral */ 23#define AT91_ID_SYS 1 /* System Peripheral */
24#define AT91_ID_PIOA 2 /* Parallel IO Controller A */ 24#define AT91RM9200_ID_PIOA 2 /* Parallel IO Controller A */
25#define AT91_ID_PIOB 3 /* Parallel IO Controller B */ 25#define AT91RM9200_ID_PIOB 3 /* Parallel IO Controller B */
26#define AT91_ID_PIOC 4 /* Parallel IO Controller C */ 26#define AT91RM9200_ID_PIOC 4 /* Parallel IO Controller C */
27#define AT91_ID_PIOD 5 /* Parallel IO Controller D */ 27#define AT91RM9200_ID_PIOD 5 /* Parallel IO Controller D */
28#define AT91_ID_US0 6 /* USART 0 */ 28#define AT91RM9200_ID_US0 6 /* USART 0 */
29#define AT91_ID_US1 7 /* USART 1 */ 29#define AT91RM9200_ID_US1 7 /* USART 1 */
30#define AT91_ID_US2 8 /* USART 2 */ 30#define AT91RM9200_ID_US2 8 /* USART 2 */
31#define AT91_ID_US3 9 /* USART 3 */ 31#define AT91RM9200_ID_US3 9 /* USART 3 */
32#define AT91_ID_MCI 10 /* Multimedia Card Interface */ 32#define AT91RM9200_ID_MCI 10 /* Multimedia Card Interface */
33#define AT91_ID_UDP 11 /* USB Device Port */ 33#define AT91RM9200_ID_UDP 11 /* USB Device Port */
34#define AT91_ID_TWI 12 /* Two-Wire Interface */ 34#define AT91RM9200_ID_TWI 12 /* Two-Wire Interface */
35#define AT91_ID_SPI 13 /* Serial Peripheral Interface */ 35#define AT91RM9200_ID_SPI 13 /* Serial Peripheral Interface */
36#define AT91_ID_SSC0 14 /* Serial Synchronous Controller 0 */ 36#define AT91RM9200_ID_SSC0 14 /* Serial Synchronous Controller 0 */
37#define AT91_ID_SSC1 15 /* Serial Synchronous Controller 1 */ 37#define AT91RM9200_ID_SSC1 15 /* Serial Synchronous Controller 1 */
38#define AT91_ID_SSC2 16 /* Serial Synchronous Controller 2 */ 38#define AT91RM9200_ID_SSC2 16 /* Serial Synchronous Controller 2 */
39#define AT91_ID_TC0 17 /* Timer Counter 0 */ 39#define AT91RM9200_ID_TC0 17 /* Timer Counter 0 */
40#define AT91_ID_TC1 18 /* Timer Counter 1 */ 40#define AT91RM9200_ID_TC1 18 /* Timer Counter 1 */
41#define AT91_ID_TC2 19 /* Timer Counter 2 */ 41#define AT91RM9200_ID_TC2 19 /* Timer Counter 2 */
42#define AT91_ID_TC3 20 /* Timer Counter 3 */ 42#define AT91RM9200_ID_TC3 20 /* Timer Counter 3 */
43#define AT91_ID_TC4 21 /* Timer Counter 4 */ 43#define AT91RM9200_ID_TC4 21 /* Timer Counter 4 */
44#define AT91_ID_TC5 22 /* Timer Counter 5 */ 44#define AT91RM9200_ID_TC5 22 /* Timer Counter 5 */
45#define AT91_ID_UHP 23 /* USB Host port */ 45#define AT91RM9200_ID_UHP 23 /* USB Host port */
46#define AT91_ID_EMAC 24 /* Ethernet MAC */ 46#define AT91RM9200_ID_EMAC 24 /* Ethernet MAC */
47#define AT91_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */ 47#define AT91RM9200_ID_IRQ0 25 /* Advanced Interrupt Controller (IRQ0) */
48#define AT91_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */ 48#define AT91RM9200_ID_IRQ1 26 /* Advanced Interrupt Controller (IRQ1) */
49#define AT91_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */ 49#define AT91RM9200_ID_IRQ2 27 /* Advanced Interrupt Controller (IRQ2) */
50#define AT91_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */ 50#define AT91RM9200_ID_IRQ3 28 /* Advanced Interrupt Controller (IRQ3) */
51#define AT91_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */ 51#define AT91RM9200_ID_IRQ4 29 /* Advanced Interrupt Controller (IRQ4) */
52#define AT91_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */ 52#define AT91RM9200_ID_IRQ5 30 /* Advanced Interrupt Controller (IRQ5) */
53#define AT91_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */ 53#define AT91RM9200_ID_IRQ6 31 /* Advanced Interrupt Controller (IRQ6) */
54 54
55 55
56/* 56/*
57 * Peripheral physical base addresses. 57 * Peripheral physical base addresses.
58 */ 58 */
59#define AT91_BASE_TCB0 0xfffa0000 59#define AT91RM9200_BASE_TCB0 0xfffa0000
60#define AT91_BASE_TC0 0xfffa0000 60#define AT91RM9200_BASE_TC0 0xfffa0000
61#define AT91_BASE_TC1 0xfffa0040 61#define AT91RM9200_BASE_TC1 0xfffa0040
62#define AT91_BASE_TC2 0xfffa0080 62#define AT91RM9200_BASE_TC2 0xfffa0080
63#define AT91_BASE_TCB1 0xfffa4000 63#define AT91RM9200_BASE_TCB1 0xfffa4000
64#define AT91_BASE_TC3 0xfffa4000 64#define AT91RM9200_BASE_TC3 0xfffa4000
65#define AT91_BASE_TC4 0xfffa4040 65#define AT91RM9200_BASE_TC4 0xfffa4040
66#define AT91_BASE_TC5 0xfffa4080 66#define AT91RM9200_BASE_TC5 0xfffa4080
67#define AT91_BASE_UDP 0xfffb0000 67#define AT91RM9200_BASE_UDP 0xfffb0000
68#define AT91_BASE_MCI 0xfffb4000 68#define AT91RM9200_BASE_MCI 0xfffb4000
69#define AT91_BASE_TWI 0xfffb8000 69#define AT91RM9200_BASE_TWI 0xfffb8000
70#define AT91_BASE_EMAC 0xfffbc000 70#define AT91RM9200_BASE_EMAC 0xfffbc000
71#define AT91_BASE_US0 0xfffc0000 71#define AT91RM9200_BASE_US0 0xfffc0000
72#define AT91_BASE_US1 0xfffc4000 72#define AT91RM9200_BASE_US1 0xfffc4000
73#define AT91_BASE_US2 0xfffc8000 73#define AT91RM9200_BASE_US2 0xfffc8000
74#define AT91_BASE_US3 0xfffcc000 74#define AT91RM9200_BASE_US3 0xfffcc000
75#define AT91_BASE_SSC0 0xfffd0000 75#define AT91RM9200_BASE_SSC0 0xfffd0000
76#define AT91_BASE_SSC1 0xfffd4000 76#define AT91RM9200_BASE_SSC1 0xfffd4000
77#define AT91_BASE_SSC2 0xfffd8000 77#define AT91RM9200_BASE_SSC2 0xfffd8000
78#define AT91_BASE_SPI 0xfffe0000 78#define AT91RM9200_BASE_SPI 0xfffe0000
79#define AT91_BASE_SYS 0xfffff000 79#define AT91_BASE_SYS 0xfffff000
80 80
81 81
82/* 82/*
83 * Internal Memory.
84 */
85#define AT91RM9200_ROM_BASE 0x00100000 /* Internal ROM base address */
86#define AT91RM9200_ROM_SIZE SZ_128K /* Internal ROM size (128Kb) */
87
88#define AT91RM9200_SRAM_BASE 0x00200000 /* Internal SRAM base address */
89#define AT91RM9200_SRAM_SIZE SZ_16K /* Internal SRAM size (16Kb) */
90
91#define AT91RM9200_UHP_BASE 0x00300000 /* USB Host controller */
92
93
94#if 0
95/*
83 * PIO pin definitions (peripheral A/B multiplexing). 96 * PIO pin definitions (peripheral A/B multiplexing).
84 */ 97 */
85#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */ 98#define AT91_PA0_MISO (1 << 0) /* A: SPI Master-In Slave-Out */
@@ -257,5 +270,6 @@
257#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */ 270#define AT91_PD25_TPK13 (1 << 25) /* B: ETM Trace Packet Port 13 */
258#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */ 271#define AT91_PD26_TPK14 (1 << 26) /* B: ETM Trace Packet Port 14 */
259#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */ 272#define AT91_PD27_TPK15 (1 << 27) /* B: ETM Trace Packet Port 15 */
273#endif
260 274
261#endif 275#endif
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 0f4c12d5f0cd..73693fea76a2 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -80,6 +80,9 @@
80#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ 80#define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */
81#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ 81#define AT91_CIDR_EXT (1 << 31) /* Extension Flag */
82 82
83#define AT91_AIC_FFER (AT91_AIC + 0x140) /* Fast Forcing Enable Register [SAM9 only] */
84#define AT91_AIC_FFDR (AT91_AIC + 0x144) /* Fast Forcing Disable Register [SAM9 only] */
85#define AT91_AIC_FFSR (AT91_AIC + 0x148) /* Fast Forcing Status Register [SAM9 only] */
83 86
84/* 87/*
85 * PIO Controllers. 88 * PIO Controllers.
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
new file mode 100644
index 000000000000..93547d7482bd
--- /dev/null
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
@@ -0,0 +1,57 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_twi.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Two-wire Interface (TWI) registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_TWI_H
17#define AT91RM9200_TWI_H
18
19#define AT91_TWI_CR 0x00 /* Control Register */
20#define AT91_TWI_START (1 << 0) /* Send a Start Condition */
21#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
22#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
23#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
24#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
25
26#define AT91_TWI_MMR 0x04 /* Master Mode Register */
27#define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */
28#define AT91_TWI_IADRSZ_NO (0 << 8)
29#define AT91_TWI_IADRSZ_1 (1 << 8)
30#define AT91_TWI_IADRSZ_2 (2 << 8)
31#define AT91_TWI_IADRSZ_3 (3 << 8)
32#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
33#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
34
35#define AT91_TWI_IADR 0x0c /* Internal Address Register */
36
37#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
38#define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */
39#define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */
40#define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */
41
42#define AT91_TWI_SR 0x20 /* Status Register */
43#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
44#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
45#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
46#define AT91_TWI_OVRE (1 << 6) /* Overrun Error */
47#define AT91_TWI_UNRE (1 << 7) /* Underrun Error */
48#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
49
50#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
51#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
52#define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */
53#define AT91_TWI_RHR 0x30 /* Receive Holding Register */
54#define AT91_TWI_THR 0x34 /* Transmit Holding Register */
55
56#endif
57
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h b/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
deleted file mode 100644
index 79f851e31b9c..000000000000
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
+++ /dev/null
@@ -1,123 +0,0 @@
1/*
2 * include/asm-arm/arch-at91rm9200/at91rm9200_usart.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * USART registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91RM9200_USART_H
17#define AT91RM9200_USART_H
18
19#define AT91_US_CR 0x00 /* Control Register */
20#define AT91_US_RSTRX (1 << 2) /* Reset Receiver */
21#define AT91_US_RSTTX (1 << 3) /* Reset Transmitter */
22#define AT91_US_RXEN (1 << 4) /* Receiver Enable */
23#define AT91_US_RXDIS (1 << 5) /* Receiver Disable */
24#define AT91_US_TXEN (1 << 6) /* Transmitter Enable */
25#define AT91_US_TXDIS (1 << 7) /* Transmitter Disable */
26#define AT91_US_RSTSTA (1 << 8) /* Reset Status Bits */
27#define AT91_US_STTBRK (1 << 9) /* Start Break */
28#define AT91_US_STPBRK (1 << 10) /* Stop Break */
29#define AT91_US_STTTO (1 << 11) /* Start Time-out */
30#define AT91_US_SENDA (1 << 12) /* Send Address */
31#define AT91_US_RSTIT (1 << 13) /* Reset Iterations */
32#define AT91_US_RSTNACK (1 << 14) /* Reset Non Acknowledge */
33#define AT91_US_RETTO (1 << 15) /* Rearm Time-out */
34#define AT91_US_DTREN (1 << 16) /* Data Terminal Ready Enable */
35#define AT91_US_DTRDIS (1 << 17) /* Data Terminal Ready Disable */
36#define AT91_US_RTSEN (1 << 18) /* Request To Send Enable */
37#define AT91_US_RTSDIS (1 << 19) /* Request To Send Disable */
38
39#define AT91_US_MR 0x04 /* Mode Register */
40#define AT91_US_USMODE (0xf << 0) /* Mode of the USART */
41#define AT91_US_USMODE_NORMAL 0
42#define AT91_US_USMODE_RS485 1
43#define AT91_US_USMODE_HWHS 2
44#define AT91_US_USMODE_MODEM 3
45#define AT91_US_USMODE_ISO7816_T0 4
46#define AT91_US_USMODE_ISO7816_T1 6
47#define AT91_US_USMODE_IRDA 8
48#define AT91_US_USCLKS (3 << 4) /* Clock Selection */
49#define AT91_US_CHRL (3 << 6) /* Character Length */
50#define AT91_US_CHRL_5 (0 << 6)
51#define AT91_US_CHRL_6 (1 << 6)
52#define AT91_US_CHRL_7 (2 << 6)
53#define AT91_US_CHRL_8 (3 << 6)
54#define AT91_US_SYNC (1 << 8) /* Synchronous Mode Select */
55#define AT91_US_PAR (7 << 9) /* Parity Type */
56#define AT91_US_PAR_EVEN (0 << 9)
57#define AT91_US_PAR_ODD (1 << 9)
58#define AT91_US_PAR_SPACE (2 << 9)
59#define AT91_US_PAR_MARK (3 << 9)
60#define AT91_US_PAR_NONE (4 << 9)
61#define AT91_US_PAR_MULTI_DROP (6 << 9)
62#define AT91_US_NBSTOP (3 << 12) /* Number of Stop Bits */
63#define AT91_US_NBSTOP_1 (0 << 12)
64#define AT91_US_NBSTOP_1_5 (1 << 12)
65#define AT91_US_NBSTOP_2 (2 << 12)
66#define AT91_US_CHMODE (3 << 14) /* Channel Mode */
67#define AT91_US_CHMODE_NORMAL (0 << 14)
68#define AT91_US_CHMODE_ECHO (1 << 14)
69#define AT91_US_CHMODE_LOC_LOOP (2 << 14)
70#define AT91_US_CHMODE_REM_LOOP (3 << 14)
71#define AT91_US_MSBF (1 << 16) /* Bit Order */
72#define AT91_US_MODE9 (1 << 17) /* 9-bit Character Length */
73#define AT91_US_CLKO (1 << 18) /* Clock Output Select */
74#define AT91_US_OVER (1 << 19) /* Oversampling Mode */
75#define AT91_US_INACK (1 << 20) /* Inhibit Non Acknowledge */
76#define AT91_US_DSNACK (1 << 21) /* Disable Successive NACK */
77#define AT91_US_MAX_ITER (7 << 24) /* Max Iterations */
78#define AT91_US_FILTER (1 << 28) /* Infrared Receive Line Filter */
79
80#define AT91_US_IER 0x08 /* Interrupt Enable Register */
81#define AT91_US_RXRDY (1 << 0) /* Receiver Ready */
82#define AT91_US_TXRDY (1 << 1) /* Transmitter Ready */
83#define AT91_US_RXBRK (1 << 2) /* Break Received / End of Break */
84#define AT91_US_ENDRX (1 << 3) /* End of Receiver Transfer */
85#define AT91_US_ENDTX (1 << 4) /* End of Transmitter Transfer */
86#define AT91_US_OVRE (1 << 5) /* Overrun Error */
87#define AT91_US_FRAME (1 << 6) /* Framing Error */
88#define AT91_US_PARE (1 << 7) /* Parity Error */
89#define AT91_US_TIMEOUT (1 << 8) /* Receiver Time-out */
90#define AT91_US_TXEMPTY (1 << 9) /* Transmitter Empty */
91#define AT91_US_ITERATION (1 << 10) /* Max number of Repetitions Reached */
92#define AT91_US_TXBUFE (1 << 11) /* Transmission Buffer Empty */
93#define AT91_US_RXBUFF (1 << 12) /* Reception Buffer Full */
94#define AT91_US_NACK (1 << 13) /* Non Acknowledge */
95#define AT91_US_RIIC (1 << 16) /* Ring Indicator Input Change */
96#define AT91_US_DSRIC (1 << 17) /* Data Set Ready Input Change */
97#define AT91_US_DCDIC (1 << 18) /* Data Carrier Detect Input Change */
98#define AT91_US_CTSIC (1 << 19) /* Clear to Send Input Change */
99#define AT91_US_RI (1 << 20) /* RI */
100#define AT91_US_DSR (1 << 21) /* DSR */
101#define AT91_US_DCD (1 << 22) /* DCD */
102#define AT91_US_CTS (1 << 23) /* CTS */
103
104#define AT91_US_IDR 0x0c /* Interrupt Disable Register */
105#define AT91_US_IMR 0x10 /* Interrupt Mask Register */
106#define AT91_US_CSR 0x14 /* Channel Status Register */
107#define AT91_US_RHR 0x18 /* Receiver Holding Register */
108#define AT91_US_THR 0x1c /* Transmitter Holding Register */
109
110#define AT91_US_BRGR 0x20 /* Baud Rate Generator Register */
111#define AT91_US_CD (0xffff << 0) /* Clock Divider */
112
113#define AT91_US_RTOR 0x24 /* Receiver Time-out Register */
114#define AT91_US_TO (0xffff << 0) /* Time-out Value */
115
116#define AT91_US_TTGR 0x28 /* Transmitter Timeguard Register */
117#define AT91_US_TG (0xff << 0) /* Timeguard Value */
118
119#define AT91_US_FIDI 0x40 /* FI DI Ratio Register */
120#define AT91_US_NER 0x44 /* Number of Errors Register */
121#define AT91_US_IF 0x4c /* IrDA Filter Register */
122
123#endif
diff --git a/include/asm-arm/arch-at91rm9200/board.h b/include/asm-arm/arch-at91rm9200/board.h
index c1ca9a4658ec..3cc9aec80f9d 100644
--- a/include/asm-arm/arch-at91rm9200/board.h
+++ b/include/asm-arm/arch-at91rm9200/board.h
@@ -97,12 +97,13 @@ struct at91_uart_config {
97 unsigned short nr_tty; /* number of serial tty's */ 97 unsigned short nr_tty; /* number of serial tty's */
98 short tty_map[]; /* map UART to tty number */ 98 short tty_map[]; /* map UART to tty number */
99}; 99};
100extern struct platform_device *at91_default_console_device; 100extern struct platform_device *atmel_default_console_device;
101extern void __init at91_init_serial(struct at91_uart_config *config); 101extern void __init at91_init_serial(struct at91_uart_config *config);
102 102
103struct at91_uart_data { 103struct atmel_uart_data {
104 short use_dma_tx; /* use transmit DMA? */ 104 short use_dma_tx; /* use transmit DMA? */
105 short use_dma_rx; /* use receive DMA? */ 105 short use_dma_rx; /* use receive DMA? */
106 void __iomem *regs; /* virtual base address, if any */
106}; 107};
107extern void __init at91_add_device_serial(void); 108extern void __init at91_add_device_serial(void);
108 109
diff --git a/include/asm-arm/arch-at91rm9200/gpio.h b/include/asm-arm/arch-at91rm9200/gpio.h
index dbde1baaf251..a011d27876a2 100644
--- a/include/asm-arm/arch-at91rm9200/gpio.h
+++ b/include/asm-arm/arch-at91rm9200/gpio.h
@@ -17,10 +17,9 @@
17 17
18#define PIN_BASE NR_AIC_IRQS 18#define PIN_BASE NR_AIC_IRQS
19 19
20#define PQFP_GPIO_BANKS 3 /* PQFP package has 3 banks */ 20#define MAX_GPIO_BANKS 4
21#define BGA_GPIO_BANKS 4 /* BGA package has 4 banks */
22 21
23/* these pin numbers double as IRQ numbers, like AT91_ID_* values */ 22/* these pin numbers double as IRQ numbers, like AT91xxx_ID_* values */
24 23
25#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0) 24#define AT91_PIN_PA0 (PIN_BASE + 0x00 + 0)
26#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1) 25#define AT91_PIN_PA1 (PIN_BASE + 0x00 + 1)
@@ -180,17 +179,18 @@
180 179
181#ifndef __ASSEMBLY__ 180#ifndef __ASSEMBLY__
182/* setup setup routines, called from board init or driver probe() */ 181/* setup setup routines, called from board init or driver probe() */
183extern int at91_set_A_periph(unsigned pin, int use_pullup); 182extern int __init_or_module at91_set_A_periph(unsigned pin, int use_pullup);
184extern int at91_set_B_periph(unsigned pin, int use_pullup); 183extern int __init_or_module at91_set_B_periph(unsigned pin, int use_pullup);
185extern int at91_set_gpio_input(unsigned pin, int use_pullup); 184extern int __init_or_module at91_set_gpio_input(unsigned pin, int use_pullup);
186extern int at91_set_gpio_output(unsigned pin, int value); 185extern int __init_or_module at91_set_gpio_output(unsigned pin, int value);
187extern int at91_set_deglitch(unsigned pin, int is_on); 186extern int __init_or_module at91_set_deglitch(unsigned pin, int is_on);
188extern int at91_set_multi_drive(unsigned pin, int is_on); 187extern int __init_or_module at91_set_multi_drive(unsigned pin, int is_on);
189 188
190/* callable at any time */ 189/* callable at any time */
191extern int at91_set_gpio_value(unsigned pin, int value); 190extern int at91_set_gpio_value(unsigned pin, int value);
192extern int at91_get_gpio_value(unsigned pin); 191extern int at91_get_gpio_value(unsigned pin);
193 192
193/* callable only from core power-management code */
194extern void at91_gpio_suspend(void); 194extern void at91_gpio_suspend(void);
195extern void at91_gpio_resume(void); 195extern void at91_gpio_resume(void);
196#endif 196#endif
diff --git a/include/asm-arm/arch-at91rm9200/hardware.h b/include/asm-arm/arch-at91rm9200/hardware.h
index 235d39d91107..9ca4cc9c0b2e 100644
--- a/include/asm-arm/arch-at91rm9200/hardware.h
+++ b/include/asm-arm/arch-at91rm9200/hardware.h
@@ -34,30 +34,17 @@
34 * Virtual to Physical Address mapping for IO devices. 34 * Virtual to Physical Address mapping for IO devices.
35 */ 35 */
36#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS) 36#define AT91_VA_BASE_SYS AT91_IO_P2V(AT91_BASE_SYS)
37#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91_BASE_SPI) 37#define AT91_VA_BASE_SPI AT91_IO_P2V(AT91RM9200_BASE_SPI)
38#define AT91_VA_BASE_SSC2 AT91_IO_P2V(AT91_BASE_SSC2) 38#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91RM9200_BASE_EMAC)
39#define AT91_VA_BASE_SSC1 AT91_IO_P2V(AT91_BASE_SSC1) 39#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91RM9200_BASE_TWI)
40#define AT91_VA_BASE_SSC0 AT91_IO_P2V(AT91_BASE_SSC0) 40#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91RM9200_BASE_MCI)
41#define AT91_VA_BASE_US3 AT91_IO_P2V(AT91_BASE_US3) 41#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91RM9200_BASE_UDP)
42#define AT91_VA_BASE_US2 AT91_IO_P2V(AT91_BASE_US2)
43#define AT91_VA_BASE_US1 AT91_IO_P2V(AT91_BASE_US1)
44#define AT91_VA_BASE_US0 AT91_IO_P2V(AT91_BASE_US0)
45#define AT91_VA_BASE_EMAC AT91_IO_P2V(AT91_BASE_EMAC)
46#define AT91_VA_BASE_TWI AT91_IO_P2V(AT91_BASE_TWI)
47#define AT91_VA_BASE_MCI AT91_IO_P2V(AT91_BASE_MCI)
48#define AT91_VA_BASE_UDP AT91_IO_P2V(AT91_BASE_UDP)
49#define AT91_VA_BASE_TCB1 AT91_IO_P2V(AT91_BASE_TCB1)
50#define AT91_VA_BASE_TCB0 AT91_IO_P2V(AT91_BASE_TCB0)
51
52/* Internal SRAM */
53#define AT91_SRAM_BASE 0x00200000 /* Internal SRAM base address */
54#define AT91_SRAM_SIZE 0x00004000 /* Internal SRAM SIZE (16Kb) */
55 42
56 /* Internal SRAM is mapped below the IO devices */ 43 /* Internal SRAM is mapped below the IO devices */
57#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91_SRAM_SIZE) 44#define AT91_SRAM_VIRT_BASE (AT91_IO_VIRT_BASE - AT91RM9200_SRAM_SIZE)
58 45
59/* Serial ports */ 46/* Serial ports */
60#define AT91_NR_UART 5 /* 4 USART3's and one DBGU port */ 47#define ATMEL_MAX_UART 5 /* 4 USART3's and one DBGU port */
61 48
62/* FLASH */ 49/* FLASH */
63#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */ 50#define AT91_FLASH_BASE 0x10000000 /* NCS0: Flash physical base address */
@@ -71,9 +58,6 @@
71/* Compact Flash */ 58/* Compact Flash */
72#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */ 59#define AT91_CF_BASE 0x50000000 /* NCS4-NCS6: Compact Flash physical base address */
73 60
74/* Multi-Master Memory controller */
75#define AT91_UHP_BASE 0x00300000 /* USB Host controller */
76
77/* Clocks */ 61/* Clocks */
78#define AT91_SLOW_CLOCK 32768 /* slow clock */ 62#define AT91_SLOW_CLOCK 32768 /* slow clock */
79 63
diff --git a/include/asm-arm/arch-at91rm9200/irqs.h b/include/asm-arm/arch-at91rm9200/irqs.h
index f63842c2c093..763cb96c418b 100644
--- a/include/asm-arm/arch-at91rm9200/irqs.h
+++ b/include/asm-arm/arch-at91rm9200/irqs.h
@@ -32,7 +32,7 @@
32 32
33 33
34/* 34/*
35 * IRQ interrupt symbols are the AT91_ID_* symbols in at91rm9200.h 35 * IRQ interrupt symbols are the AT91xxx_ID_* symbols
36 * for IRQs handled directly through the AIC, or else the AT91_PIN_* 36 * for IRQs handled directly through the AIC, or else the AT91_PIN_*
37 * symbols in gpio.h for ones handled indirectly as GPIOs. 37 * symbols in gpio.h for ones handled indirectly as GPIOs.
38 * We make provision for 4 banks of GPIO. 38 * We make provision for 4 banks of GPIO.
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-21 16:13:50 -0500