diff options
Diffstat (limited to 'include/asm-arm/arch-at91rm9200/at91_dbgu.h')
-rw-r--r-- | include/asm-arm/arch-at91rm9200/at91_dbgu.h | 45 |
1 files changed, 45 insertions, 0 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91_dbgu.h b/include/asm-arm/arch-at91rm9200/at91_dbgu.h new file mode 100644 index 000000000000..e4b8b27acfca --- /dev/null +++ b/include/asm-arm/arch-at91rm9200/at91_dbgu.h | |||
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1 | /* | ||
2 | * include/asm-arm/arch-at91rm9200/at91_dbgu.h | ||
3 | * | ||
4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
5 | * Copyright (C) SAN People | ||
6 | * | ||
7 | * Debug Unit (DBGU) - System peripherals registers. | ||
8 | * Based on AT91RM9200 datasheet revision E. | ||
9 | * | ||
10 | * This program is free software; you can redistribute it and/or modify | ||
11 | * it under the terms of the GNU General Public License as published by | ||
12 | * the Free Software Foundation; either version 2 of the License, or | ||
13 | * (at your option) any later version. | ||
14 | */ | ||
15 | |||
16 | #ifndef AT91_DBGU_H | ||
17 | #define AT91_DBGU_H | ||
18 | |||
19 | #define AT91_DBGU_CR (AT91_DBGU + 0x00) /* Control Register */ | ||
20 | #define AT91_DBGU_MR (AT91_DBGU + 0x04) /* Mode Register */ | ||
21 | #define AT91_DBGU_IER (AT91_DBGU + 0x08) /* Interrupt Enable Register */ | ||
22 | #define AT91_DBGU_TXRDY (1 << 1) /* Transmitter Ready */ | ||
23 | #define AT91_DBGU_TXEMPTY (1 << 9) /* Transmitter Empty */ | ||
24 | #define AT91_DBGU_IDR (AT91_DBGU + 0x0c) /* Interrupt Disable Register */ | ||
25 | #define AT91_DBGU_IMR (AT91_DBGU + 0x10) /* Interrupt Mask Register */ | ||
26 | #define AT91_DBGU_SR (AT91_DBGU + 0x14) /* Status Register */ | ||
27 | #define AT91_DBGU_RHR (AT91_DBGU + 0x18) /* Receiver Holding Register */ | ||
28 | #define AT91_DBGU_THR (AT91_DBGU + 0x1c) /* Transmitter Holding Register */ | ||
29 | #define AT91_DBGU_BRGR (AT91_DBGU + 0x20) /* Baud Rate Generator Register */ | ||
30 | |||
31 | #define AT91_DBGU_CIDR (AT91_DBGU + 0x40) /* Chip ID Register */ | ||
32 | #define AT91_DBGU_EXID (AT91_DBGU + 0x44) /* Chip ID Extension Register */ | ||
33 | #define AT91_CIDR_VERSION (0x1f << 0) /* Version of the Device */ | ||
34 | #define AT91_CIDR_EPROC (7 << 5) /* Embedded Processor */ | ||
35 | #define AT91_CIDR_NVPSIZ (0xf << 8) /* Nonvolatile Program Memory Size */ | ||
36 | #define AT91_CIDR_NVPSIZ2 (0xf << 12) /* Second Nonvolatile Program Memory Size */ | ||
37 | #define AT91_CIDR_SRAMSIZ (0xf << 16) /* Internal SRAM Size */ | ||
38 | #define AT91_CIDR_ARCH (0xff << 20) /* Architecture Identifier */ | ||
39 | #define AT91_CIDR_NVPTYP (7 << 28) /* Nonvolatile Program Memory Type */ | ||
40 | #define AT91_CIDR_EXT (1 << 31) /* Extension Flag */ | ||
41 | |||
42 | #define AT91_DBGU_FNR (AT91_DBGU + 0x48) /* Force NTRST Register [SAM9 only] */ | ||
43 | #define AT91_DBGU_FNTRST (1 << 0) /* Force NTRST */ | ||
44 | |||
45 | #endif | ||