aboutsummaryrefslogtreecommitdiffstats
path: root/include/asm-arm/arch-at91
diff options
context:
space:
mode:
Diffstat (limited to 'include/asm-arm/arch-at91')
-rw-r--r--include/asm-arm/arch-at91/at91_lcdc.h148
-rw-r--r--include/asm-arm/arch-at91/at91_pmc.h9
-rw-r--r--include/asm-arm/arch-at91/at91_rtt.h8
-rw-r--r--include/asm-arm/arch-at91/at91_twi.h11
-rw-r--r--include/asm-arm/arch-at91/at91cap9.h121
-rw-r--r--include/asm-arm/arch-at91/at91cap9_matrix.h132
-rw-r--r--include/asm-arm/arch-at91/at91sam9260_matrix.h2
-rw-r--r--include/asm-arm/arch-at91/at91sam9263_matrix.h2
-rw-r--r--include/asm-arm/arch-at91/at91sam9rl_matrix.h2
-rw-r--r--include/asm-arm/arch-at91/board.h38
-rw-r--r--include/asm-arm/arch-at91/cpu.h9
-rw-r--r--include/asm-arm/arch-at91/entry-macro.S2
-rw-r--r--include/asm-arm/arch-at91/hardware.h2
-rw-r--r--include/asm-arm/arch-at91/timex.h5
14 files changed, 328 insertions, 163 deletions
diff --git a/include/asm-arm/arch-at91/at91_lcdc.h b/include/asm-arm/arch-at91/at91_lcdc.h
deleted file mode 100644
index ab040a40d37b..000000000000
--- a/include/asm-arm/arch-at91/at91_lcdc.h
+++ /dev/null
@@ -1,148 +0,0 @@
1/*
2 * include/asm-arm/arch-at91/at91_lcdc.h
3 *
4 * LCD Controller (LCDC).
5 * Based on AT91SAM9261 datasheet revision E.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13#ifndef AT91_LCDC_H
14#define AT91_LCDC_H
15
16#define AT91_LCDC_DMABADDR1 0x00 /* DMA Base Address Register 1 */
17#define AT91_LCDC_DMABADDR2 0x04 /* DMA Base Address Register 2 */
18#define AT91_LCDC_DMAFRMPT1 0x08 /* DMA Frame Pointer Register 1 */
19#define AT91_LCDC_DMAFRMPT2 0x0c /* DMA Frame Pointer Register 2 */
20#define AT91_LCDC_DMAFRMADD1 0x10 /* DMA Frame Address Register 1 */
21#define AT91_LCDC_DMAFRMADD2 0x14 /* DMA Frame Address Register 2 */
22
23#define AT91_LCDC_DMAFRMCFG 0x18 /* DMA Frame Configuration Register */
24#define AT91_LCDC_FRSIZE (0x7fffff << 0) /* Frame Size */
25#define AT91_LCDC_BLENGTH (0x7f << 24) /* Burst Length */
26
27#define AT91_LCDC_DMACON 0x1c /* DMA Control Register */
28#define AT91_LCDC_DMAEN (0x1 << 0) /* DMA Enable */
29#define AT91_LCDC_DMARST (0x1 << 1) /* DMA Reset */
30#define AT91_LCDC_DMABUSY (0x1 << 2) /* DMA Busy */
31
32#define AT91_LCDC_LCDCON1 0x0800 /* LCD Control Register 1 */
33#define AT91_LCDC_BYPASS (1 << 0) /* Bypass lcd_dotck divider */
34#define AT91_LCDC_CLKVAL (0x1ff << 12) /* Clock Divider */
35#define AT91_LCDC_LINCNT (0x7ff << 21) /* Line Counter */
36
37#define AT91_LCDC_LCDCON2 0x0804 /* LCD Control Register 2 */
38#define AT91_LCDC_DISTYPE (3 << 0) /* Display Type */
39#define AT91_LCDC_DISTYPE_STNMONO (0 << 0)
40#define AT91_LCDC_DISTYPE_STNCOLOR (1 << 0)
41#define AT91_LCDC_DISTYPE_TFT (2 << 0)
42#define AT91_LCDC_SCANMOD (1 << 2) /* Scan Mode */
43#define AT91_LCDC_SCANMOD_SINGLE (0 << 2)
44#define AT91_LCDC_SCANMOD_DUAL (1 << 2)
45#define AT91_LCDC_IFWIDTH (3 << 3) /*Interface Width */
46#define AT91_LCDC_IFWIDTH_4 (0 << 3)
47#define AT91_LCDC_IFWIDTH_8 (1 << 3)
48#define AT91_LCDC_IFWIDTH_16 (2 << 3)
49#define AT91_LCDC_PIXELSIZE (7 << 5) /* Bits per pixel */
50#define AT91_LCDC_PIXELSIZE_1 (0 << 5)
51#define AT91_LCDC_PIXELSIZE_2 (1 << 5)
52#define AT91_LCDC_PIXELSIZE_4 (2 << 5)
53#define AT91_LCDC_PIXELSIZE_8 (3 << 5)
54#define AT91_LCDC_PIXELSIZE_16 (4 << 5)
55#define AT91_LCDC_PIXELSIZE_24 (5 << 5)
56#define AT91_LCDC_INVVD (1 << 8) /* LCD Data polarity */
57#define AT91_LCDC_INVVD_NORMAL (0 << 8)
58#define AT91_LCDC_INVVD_INVERTED (1 << 8)
59#define AT91_LCDC_INVFRAME (1 << 9 ) /* LCD VSync polarity */
60#define AT91_LCDC_INVFRAME_NORMAL (0 << 9)
61#define AT91_LCDC_INVFRAME_INVERTED (1 << 9)
62#define AT91_LCDC_INVLINE (1 << 10) /* LCD HSync polarity */
63#define AT91_LCDC_INVLINE_NORMAL (0 << 10)
64#define AT91_LCDC_INVLINE_INVERTED (1 << 10)
65#define AT91_LCDC_INVCLK (1 << 11) /* LCD dotclk polarity */
66#define AT91_LCDC_INVCLK_NORMAL (0 << 11)
67#define AT91_LCDC_INVCLK_INVERTED (1 << 11)
68#define AT91_LCDC_INVDVAL (1 << 12) /* LCD dval polarity */
69#define AT91_LCDC_INVDVAL_NORMAL (0 << 12)
70#define AT91_LCDC_INVDVAL_INVERTED (1 << 12)
71#define AT91_LCDC_CLKMOD (1 << 15) /* LCD dotclk mode */
72#define AT91_LCDC_CLKMOD_ACTIVEDISPLAY (0 << 15)
73#define AT91_LCDC_CLKMOD_ALWAYSACTIVE (1 << 15)
74#define AT91_LCDC_MEMOR (1 << 31) /* Memory Ordering Format */
75#define AT91_LCDC_MEMOR_BIG (0 << 31)
76#define AT91_LCDC_MEMOR_LITTLE (1 << 31)
77
78#define AT91_LCDC_TIM1 0x0808 /* LCD Timing Register 1 */
79#define AT91_LCDC_VFP (0xff << 0) /* Vertical Front Porch */
80#define AT91_LCDC_VBP (0xff << 8) /* Vertical Back Porch */
81#define AT91_LCDC_VPW (0x3f << 16) /* Vertical Synchronization Pulse Width */
82#define AT91_LCDC_VHDLY (0xf << 24) /* Vertical to Horizontal Delay */
83
84#define AT91_LCDC_TIM2 0x080c /* LCD Timing Register 2 */
85#define AT91_LCDC_HBP (0xff << 0) /* Horizontal Back Porch */
86#define AT91_LCDC_HPW (0x3f << 8) /* Horizontal Synchronization Pulse Width */
87#define AT91_LCDC_HFP (0x7ff << 21) /* Horizontal Front Porch */
88
89#define AT91_LCDC_LCDFRMCFG 0x0810 /* LCD Frame Configuration Register */
90#define AT91_LCDC_LINEVAL (0x7ff << 0) /* Vertical Size of LCD Module */
91#define AT91_LCDC_HOZVAL (0x7ff << 21) /* Horizontal Size of LCD Module */
92
93#define AT91_LCDC_FIFO 0x0814 /* LCD FIFO Register */
94#define AT91_LCDC_FIFOTH (0xffff) /* FIFO Threshold */
95
96#define AT91_LCDC_DP1_2 0x081c /* Dithering Pattern DP1_2 Register */
97#define AT91_LCDC_DP4_7 0x0820 /* Dithering Pattern DP4_7 Register */
98#define AT91_LCDC_DP3_5 0x0824 /* Dithering Pattern DP3_5 Register */
99#define AT91_LCDC_DP2_3 0x0828 /* Dithering Pattern DP2_3 Register */
100#define AT91_LCDC_DP5_7 0x082c /* Dithering Pattern DP5_7 Register */
101#define AT91_LCDC_DP3_4 0x0830 /* Dithering Pattern DP3_4 Register */
102#define AT91_LCDC_DP4_5 0x0834 /* Dithering Pattern DP4_5 Register */
103#define AT91_LCDC_DP6_7 0x0838 /* Dithering Pattern DP6_7 Register */
104#define AT91_LCDC_DP1_2_VAL (0xff)
105#define AT91_LCDC_DP4_7_VAL (0xfffffff)
106#define AT91_LCDC_DP3_5_VAL (0xfffff)
107#define AT91_LCDC_DP2_3_VAL (0xfff)
108#define AT91_LCDC_DP5_7_VAL (0xfffffff)
109#define AT91_LCDC_DP3_4_VAL (0xffff)
110#define AT91_LCDC_DP4_5_VAL (0xfffff)
111#define AT91_LCDC_DP6_7_VAL (0xfffffff)
112
113#define AT91_LCDC_PWRCON 0x083c /* Power Control Register */
114#define AT91_LCDC_PWR (1 << 0) /* LCD Module Power Control */
115#define AT91_LCDC_GUARDT (0x7f << 1) /* Delay in Frame Period */
116#define AT91_LCDC_BUSY (1 << 31) /* LCD Busy */
117
118#define AT91_LCDC_CONTRAST_CTR 0x0840 /* Contrast Control Register */
119#define AT91_LCDC_PS (3 << 0) /* Contrast Counter Prescaler */
120#define AT91_LCDC_PS_DIV1 (0 << 0)
121#define AT91_LCDC_PS_DIV2 (1 << 0)
122#define AT91_LCDC_PS_DIV4 (2 << 0)
123#define AT91_LCDC_PS_DIV8 (3 << 0)
124#define AT91_LCDC_POL (1 << 2) /* Polarity of output Pulse */
125#define AT91_LCDC_POL_NEGATIVE (0 << 2)
126#define AT91_LCDC_POL_POSITIVE (1 << 2)
127#define AT91_LCDC_ENA (1 << 3) /* PWM generator Control */
128#define AT91_LCDC_ENA_PWMDISABLE (0 << 3)
129#define AT91_LCDC_ENA_PWMENABLE (1 << 3)
130
131#define AT91_LCDC_CONTRAST_VAL 0x0844 /* Contrast Value Register */
132#define AT91_LCDC_CVAL (0xff) /* PWM compare value */
133
134#define AT91_LCDC_IER 0x0848 /* Interrupt Enable Register */
135#define AT91_LCDC_IDR 0x084c /* Interrupt Disable Register */
136#define AT91_LCDC_IMR 0x0850 /* Interrupt Mask Register */
137#define AT91_LCDC_ISR 0x0854 /* Interrupt Enable Register */
138#define AT91_LCDC_ICR 0x0858 /* Interrupt Clear Register */
139#define AT91_LCDC_LNI (1 << 0) /* Line Interrupt */
140#define AT91_LCDC_LSTLNI (1 << 1) /* Last Line Interrupt */
141#define AT91_LCDC_EOFI (1 << 2) /* DMA End Of Frame Interrupt */
142#define AT91_LCDC_UFLWI (1 << 4) /* FIFO Underflow Interrupt */
143#define AT91_LCDC_OWRI (1 << 5) /* FIFO Overwrite Interrupt */
144#define AT91_LCDC_MERI (1 << 6) /* DMA Memory Error Interrupt */
145
146#define AT91_LCDC_LUT_(n) (0x0c00 + ((n)*4)) /* Palette Entry 0..255 */
147
148#endif
diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
index 33ff5b6798ee..52cd8e5dabc9 100644
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ b/include/asm-arm/arch-at91/at91_pmc.h
@@ -25,6 +25,7 @@
25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
26#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 26#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
27#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 27#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
28#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
28#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 29#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
29#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 30#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
30#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 31#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
@@ -37,7 +38,9 @@
37#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */ 38#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
38#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */ 39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
39 40
40#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register */ 41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
42
43#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
41#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 44#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
42#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */ 45#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [AT91SAM926x only] */
43#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 46#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
@@ -52,6 +55,10 @@
52#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 55#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
53#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 56#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
54#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ 57#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
58#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
59#define AT91_PMC_USBDIV_1 (0 << 28)
60#define AT91_PMC_USBDIV_2 (1 << 28)
61#define AT91_PMC_USBDIV_4 (2 << 28)
55#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 62#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
56 63
57#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */ 64#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
diff --git a/include/asm-arm/arch-at91/at91_rtt.h b/include/asm-arm/arch-at91/at91_rtt.h
index bae1103fbbb2..39a32633b275 100644
--- a/include/asm-arm/arch-at91/at91_rtt.h
+++ b/include/asm-arm/arch-at91/at91_rtt.h
@@ -13,19 +13,19 @@
13#ifndef AT91_RTT_H 13#ifndef AT91_RTT_H
14#define AT91_RTT_H 14#define AT91_RTT_H
15 15
16#define AT91_RTT_MR (AT91_RTT + 0x00) /* Real-time Mode Register */ 16#define AT91_RTT_MR 0x00 /* Real-time Mode Register */
17#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */ 17#define AT91_RTT_RTPRES (0xffff << 0) /* Real-time Timer Prescaler Value */
18#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */ 18#define AT91_RTT_ALMIEN (1 << 16) /* Alarm Interrupt Enable */
19#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */ 19#define AT91_RTT_RTTINCIEN (1 << 17) /* Real Time Timer Increment Interrupt Enable */
20#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */ 20#define AT91_RTT_RTTRST (1 << 18) /* Real Time Timer Restart */
21 21
22#define AT91_RTT_AR (AT91_RTT + 0x04) /* Real-time Alarm Register */ 22#define AT91_RTT_AR 0x04 /* Real-time Alarm Register */
23#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */ 23#define AT91_RTT_ALMV (0xffffffff) /* Alarm Value */
24 24
25#define AT91_RTT_VR (AT91_RTT + 0x08) /* Real-time Value Register */ 25#define AT91_RTT_VR 0x08 /* Real-time Value Register */
26#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */ 26#define AT91_RTT_CRTV (0xffffffff) /* Current Real-time Value */
27 27
28#define AT91_RTT_SR (AT91_RTT + 0x0c) /* Real-time Status Register */ 28#define AT91_RTT_SR 0x0c /* Real-time Status Register */
29#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */ 29#define AT91_RTT_ALMS (1 << 0) /* Real-time Alarm Status */
30#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */ 30#define AT91_RTT_RTTINC (1 << 1) /* Real-time Timer Increment */
31 31
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h
index ca9a90733456..f9f2e3cd95c5 100644
--- a/include/asm-arm/arch-at91/at91_twi.h
+++ b/include/asm-arm/arch-at91/at91_twi.h
@@ -21,6 +21,8 @@
21#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ 21#define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */
22#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ 22#define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */
23#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ 23#define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */
24#define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */
25#define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */
24#define AT91_TWI_SWRST (1 << 7) /* Software Reset */ 26#define AT91_TWI_SWRST (1 << 7) /* Software Reset */
25 27
26#define AT91_TWI_MMR 0x04 /* Master Mode Register */ 28#define AT91_TWI_MMR 0x04 /* Master Mode Register */
@@ -32,6 +34,9 @@
32#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ 34#define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */
33#define AT91_TWI_DADR (0x7f << 16) /* Device Address */ 35#define AT91_TWI_DADR (0x7f << 16) /* Device Address */
34 36
37#define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */
38#define AT91_TWI_SADR (0x7f << 16) /* Slave Address */
39
35#define AT91_TWI_IADR 0x0c /* Internal Address Register */ 40#define AT91_TWI_IADR 0x0c /* Internal Address Register */
36 41
37#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ 42#define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */
@@ -43,9 +48,15 @@
43#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ 48#define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */
44#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ 49#define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */
45#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ 50#define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */
51#define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */
52#define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */
53#define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */
46#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ 54#define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */
47#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ 55#define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */
48#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ 56#define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */
57#define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */
58#define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */
59#define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */
49 60
50#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ 61#define AT91_TWI_IER 0x24 /* Interrupt Enable Register */
51#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ 62#define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */
diff --git a/include/asm-arm/arch-at91/at91cap9.h b/include/asm-arm/arch-at91/at91cap9.h
new file mode 100644
index 000000000000..73e1fcf4a0aa
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9.h
@@ -0,0 +1,121 @@
1/*
2 * include/asm-arm/arch-at91/at91cap9.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2007 Atmel Corporation.
7 *
8 * Common definitions.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_H
18#define AT91CAP9_H
19
20/*
21 * Peripheral identifiers/interrupts.
22 */
23#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */
24#define AT91_ID_SYS 1 /* System Peripherals */
25#define AT91CAP9_ID_PIOABCD 2 /* Parallel IO Controller A, B, C and D */
26#define AT91CAP9_ID_MPB0 3 /* MP Block Peripheral 0 */
27#define AT91CAP9_ID_MPB1 4 /* MP Block Peripheral 1 */
28#define AT91CAP9_ID_MPB2 5 /* MP Block Peripheral 2 */
29#define AT91CAP9_ID_MPB3 6 /* MP Block Peripheral 3 */
30#define AT91CAP9_ID_MPB4 7 /* MP Block Peripheral 4 */
31#define AT91CAP9_ID_US0 8 /* USART 0 */
32#define AT91CAP9_ID_US1 9 /* USART 1 */
33#define AT91CAP9_ID_US2 10 /* USART 2 */
34#define AT91CAP9_ID_MCI0 11 /* Multimedia Card Interface 0 */
35#define AT91CAP9_ID_MCI1 12 /* Multimedia Card Interface 1 */
36#define AT91CAP9_ID_CAN 13 /* CAN */
37#define AT91CAP9_ID_TWI 14 /* Two-Wire Interface */
38#define AT91CAP9_ID_SPI0 15 /* Serial Peripheral Interface 0 */
39#define AT91CAP9_ID_SPI1 16 /* Serial Peripheral Interface 0 */
40#define AT91CAP9_ID_SSC0 17 /* Serial Synchronous Controller 0 */
41#define AT91CAP9_ID_SSC1 18 /* Serial Synchronous Controller 1 */
42#define AT91CAP9_ID_AC97C 19 /* AC97 Controller */
43#define AT91CAP9_ID_TCB 20 /* Timer Counter 0, 1 and 2 */
44#define AT91CAP9_ID_PWMC 21 /* Pulse Width Modulation Controller */
45#define AT91CAP9_ID_EMAC 22 /* Ethernet */
46#define AT91CAP9_ID_AESTDES 23 /* Advanced Encryption Standard, Triple DES */
47#define AT91CAP9_ID_ADC 24 /* Analog-to-Digital Converter */
48#define AT91CAP9_ID_ISI 25 /* Image Sensor Interface */
49#define AT91CAP9_ID_LCDC 26 /* LCD Controller */
50#define AT91CAP9_ID_DMA 27 /* DMA Controller */
51#define AT91CAP9_ID_UDPHS 28 /* USB High Speed Device Port */
52#define AT91CAP9_ID_UHP 29 /* USB Host Port */
53#define AT91CAP9_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */
54#define AT91CAP9_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */
55
56/*
57 * User Peripheral physical base addresses.
58 */
59#define AT91CAP9_BASE_UDPHS 0xfff78000
60#define AT91CAP9_BASE_TCB0 0xfff7c000
61#define AT91CAP9_BASE_TC0 0xfff7c000
62#define AT91CAP9_BASE_TC1 0xfff7c040
63#define AT91CAP9_BASE_TC2 0xfff7c080
64#define AT91CAP9_BASE_MCI0 0xfff80000
65#define AT91CAP9_BASE_MCI1 0xfff84000
66#define AT91CAP9_BASE_TWI 0xfff88000
67#define AT91CAP9_BASE_US0 0xfff8c000
68#define AT91CAP9_BASE_US1 0xfff90000
69#define AT91CAP9_BASE_US2 0xfff94000
70#define AT91CAP9_BASE_SSC0 0xfff98000
71#define AT91CAP9_BASE_SSC1 0xfff9c000
72#define AT91CAP9_BASE_AC97C 0xfffa0000
73#define AT91CAP9_BASE_SPI0 0xfffa4000
74#define AT91CAP9_BASE_SPI1 0xfffa8000
75#define AT91CAP9_BASE_CAN 0xfffac000
76#define AT91CAP9_BASE_PWMC 0xfffb8000
77#define AT91CAP9_BASE_EMAC 0xfffbc000
78#define AT91CAP9_BASE_ADC 0xfffc0000
79#define AT91CAP9_BASE_ISI 0xfffc4000
80#define AT91_BASE_SYS 0xffffe200
81
82/*
83 * System Peripherals (offset from AT91_BASE_SYS)
84 */
85#define AT91_ECC (0xffffe200 - AT91_BASE_SYS)
86#define AT91_BCRAMC (0xffffe400 - AT91_BASE_SYS)
87#define AT91_DDRSDRC (0xffffe600 - AT91_BASE_SYS)
88#define AT91_SMC (0xffffe800 - AT91_BASE_SYS)
89#define AT91_MATRIX (0xffffea00 - AT91_BASE_SYS)
90#define AT91_CCFG (0xffffeb10 - AT91_BASE_SYS)
91#define AT91_DMA (0xffffec00 - AT91_BASE_SYS)
92#define AT91_DBGU (0xffffee00 - AT91_BASE_SYS)
93#define AT91_AIC (0xfffff000 - AT91_BASE_SYS)
94#define AT91_PIOA (0xfffff200 - AT91_BASE_SYS)
95#define AT91_PIOB (0xfffff400 - AT91_BASE_SYS)
96#define AT91_PIOC (0xfffff600 - AT91_BASE_SYS)
97#define AT91_PIOD (0xfffff800 - AT91_BASE_SYS)
98#define AT91_PMC (0xfffffc00 - AT91_BASE_SYS)
99#define AT91_RSTC (0xfffffd00 - AT91_BASE_SYS)
100#define AT91_SHDC (0xfffffd10 - AT91_BASE_SYS)
101#define AT91_RTT (0xfffffd20 - AT91_BASE_SYS)
102#define AT91_PIT (0xfffffd30 - AT91_BASE_SYS)
103#define AT91_WDT (0xfffffd40 - AT91_BASE_SYS)
104#define AT91_GPBR (0xfffffd50 - AT91_BASE_SYS)
105
106/*
107 * Internal Memory.
108 */
109#define AT91CAP9_SRAM_BASE 0x00100000 /* Internal SRAM base address */
110#define AT91CAP9_SRAM_SIZE (32 * SZ_1K) /* Internal SRAM size (32Kb) */
111
112#define AT91CAP9_ROM_BASE 0x00400000 /* Internal ROM base address */
113#define AT91CAP9_ROM_SIZE (32 * SZ_1K) /* Internal ROM size (32Kb) */
114
115#define AT91CAP9_LCDC_BASE 0x00500000 /* LCD Controller */
116#define AT91CAP9_UDPHS_BASE 0x00600000 /* USB High Speed Device Port */
117#define AT91CAP9_UHP_BASE 0x00700000 /* USB Host controller */
118
119#define CONFIG_DRAM_BASE AT91_CHIPSELECT_6
120
121#endif
diff --git a/include/asm-arm/arch-at91/at91cap9_matrix.h b/include/asm-arm/arch-at91/at91cap9_matrix.h
new file mode 100644
index 000000000000..a641686b6c3d
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91cap9_matrix.h
@@ -0,0 +1,132 @@
1/*
2 * include/asm-arm/arch-at91/at91cap9_matrix.h
3 *
4 * Copyright (C) 2007 Stelian Pop <stelian.pop@leadtechdesign.com>
5 * Copyright (C) 2007 Lead Tech Design <www.leadtechdesign.com>
6 * Copyright (C) 2006 Atmel Corporation.
7 *
8 * Memory Controllers (MATRIX, EBI) - System peripherals registers.
9 * Based on AT91CAP9 datasheet revision B (Preliminary).
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
15 */
16
17#ifndef AT91CAP9_MATRIX_H
18#define AT91CAP9_MATRIX_H
19
20#define AT91_MATRIX_MCFG0 (AT91_MATRIX + 0x00) /* Master Configuration Register 0 */
21#define AT91_MATRIX_MCFG1 (AT91_MATRIX + 0x04) /* Master Configuration Register 1 */
22#define AT91_MATRIX_MCFG2 (AT91_MATRIX + 0x08) /* Master Configuration Register 2 */
23#define AT91_MATRIX_MCFG3 (AT91_MATRIX + 0x0C) /* Master Configuration Register 3 */
24#define AT91_MATRIX_MCFG4 (AT91_MATRIX + 0x10) /* Master Configuration Register 4 */
25#define AT91_MATRIX_MCFG5 (AT91_MATRIX + 0x14) /* Master Configuration Register 5 */
26#define AT91_MATRIX_MCFG6 (AT91_MATRIX + 0x18) /* Master Configuration Register 6 */
27#define AT91_MATRIX_MCFG7 (AT91_MATRIX + 0x1C) /* Master Configuration Register 7 */
28#define AT91_MATRIX_MCFG8 (AT91_MATRIX + 0x20) /* Master Configuration Register 8 */
29#define AT91_MATRIX_MCFG9 (AT91_MATRIX + 0x24) /* Master Configuration Register 9 */
30#define AT91_MATRIX_MCFG10 (AT91_MATRIX + 0x28) /* Master Configuration Register 10 */
31#define AT91_MATRIX_MCFG11 (AT91_MATRIX + 0x2C) /* Master Configuration Register 11 */
32#define AT91_MATRIX_ULBT (7 << 0) /* Undefined Length Burst Type */
33#define AT91_MATRIX_ULBT_INFINITE (0 << 0)
34#define AT91_MATRIX_ULBT_SINGLE (1 << 0)
35#define AT91_MATRIX_ULBT_FOUR (2 << 0)
36#define AT91_MATRIX_ULBT_EIGHT (3 << 0)
37#define AT91_MATRIX_ULBT_SIXTEEN (4 << 0)
38
39#define AT91_MATRIX_SCFG0 (AT91_MATRIX + 0x40) /* Slave Configuration Register 0 */
40#define AT91_MATRIX_SCFG1 (AT91_MATRIX + 0x44) /* Slave Configuration Register 1 */
41#define AT91_MATRIX_SCFG2 (AT91_MATRIX + 0x48) /* Slave Configuration Register 2 */
42#define AT91_MATRIX_SCFG3 (AT91_MATRIX + 0x4C) /* Slave Configuration Register 3 */
43#define AT91_MATRIX_SCFG4 (AT91_MATRIX + 0x50) /* Slave Configuration Register 4 */
44#define AT91_MATRIX_SCFG5 (AT91_MATRIX + 0x54) /* Slave Configuration Register 5 */
45#define AT91_MATRIX_SCFG6 (AT91_MATRIX + 0x58) /* Slave Configuration Register 6 */
46#define AT91_MATRIX_SCFG7 (AT91_MATRIX + 0x5C) /* Slave Configuration Register 7 */
47#define AT91_MATRIX_SCFG8 (AT91_MATRIX + 0x60) /* Slave Configuration Register 8 */
48#define AT91_MATRIX_SCFG9 (AT91_MATRIX + 0x64) /* Slave Configuration Register 9 */
49#define AT91_MATRIX_SLOT_CYCLE (0xff << 0) /* Maximum Number of Allowed Cycles for a Burst */
50#define AT91_MATRIX_DEFMSTR_TYPE (3 << 16) /* Default Master Type */
51#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
52#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
53#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
54#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
55#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
56#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
57#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
58
59#define AT91_MATRIX_PRAS0 (AT91_MATRIX + 0x80) /* Priority Register A for Slave 0 */
60#define AT91_MATRIX_PRBS0 (AT91_MATRIX + 0x84) /* Priority Register B for Slave 0 */
61#define AT91_MATRIX_PRAS1 (AT91_MATRIX + 0x88) /* Priority Register A for Slave 1 */
62#define AT91_MATRIX_PRBS1 (AT91_MATRIX + 0x8C) /* Priority Register B for Slave 1 */
63#define AT91_MATRIX_PRAS2 (AT91_MATRIX + 0x90) /* Priority Register A for Slave 2 */
64#define AT91_MATRIX_PRBS2 (AT91_MATRIX + 0x94) /* Priority Register B for Slave 2 */
65#define AT91_MATRIX_PRAS3 (AT91_MATRIX + 0x98) /* Priority Register A for Slave 3 */
66#define AT91_MATRIX_PRBS3 (AT91_MATRIX + 0x9C) /* Priority Register B for Slave 3 */
67#define AT91_MATRIX_PRAS4 (AT91_MATRIX + 0xA0) /* Priority Register A for Slave 4 */
68#define AT91_MATRIX_PRBS4 (AT91_MATRIX + 0xA4) /* Priority Register B for Slave 4 */
69#define AT91_MATRIX_PRAS5 (AT91_MATRIX + 0xA8) /* Priority Register A for Slave 5 */
70#define AT91_MATRIX_PRBS5 (AT91_MATRIX + 0xAC) /* Priority Register B for Slave 5 */
71#define AT91_MATRIX_PRAS6 (AT91_MATRIX + 0xB0) /* Priority Register A for Slave 6 */
72#define AT91_MATRIX_PRBS6 (AT91_MATRIX + 0xB4) /* Priority Register B for Slave 6 */
73#define AT91_MATRIX_PRAS7 (AT91_MATRIX + 0xB8) /* Priority Register A for Slave 7 */
74#define AT91_MATRIX_PRBS7 (AT91_MATRIX + 0xBC) /* Priority Register B for Slave 7 */
75#define AT91_MATRIX_PRAS8 (AT91_MATRIX + 0xC0) /* Priority Register A for Slave 8 */
76#define AT91_MATRIX_PRBS8 (AT91_MATRIX + 0xC4) /* Priority Register B for Slave 8 */
77#define AT91_MATRIX_PRAS9 (AT91_MATRIX + 0xC8) /* Priority Register A for Slave 9 */
78#define AT91_MATRIX_PRBS9 (AT91_MATRIX + 0xCC) /* Priority Register B for Slave 9 */
79#define AT91_MATRIX_M0PR (3 << 0) /* Master 0 Priority */
80#define AT91_MATRIX_M1PR (3 << 4) /* Master 1 Priority */
81#define AT91_MATRIX_M2PR (3 << 8) /* Master 2 Priority */
82#define AT91_MATRIX_M3PR (3 << 12) /* Master 3 Priority */
83#define AT91_MATRIX_M4PR (3 << 16) /* Master 4 Priority */
84#define AT91_MATRIX_M5PR (3 << 20) /* Master 5 Priority */
85#define AT91_MATRIX_M6PR (3 << 24) /* Master 6 Priority */
86#define AT91_MATRIX_M7PR (3 << 28) /* Master 7 Priority */
87#define AT91_MATRIX_M8PR (3 << 0) /* Master 8 Priority (in Register B) */
88#define AT91_MATRIX_M9PR (3 << 4) /* Master 9 Priority (in Register B) */
89#define AT91_MATRIX_M10PR (3 << 8) /* Master 10 Priority (in Register B) */
90#define AT91_MATRIX_M11PR (3 << 12) /* Master 11 Priority (in Register B) */
91
92#define AT91_MATRIX_MRCR (AT91_MATRIX + 0x100) /* Master Remap Control Register */
93#define AT91_MATRIX_RCB0 (1 << 0) /* Remap Command for AHB Master 0 (ARM926EJ-S Instruction Master) */
94#define AT91_MATRIX_RCB1 (1 << 1) /* Remap Command for AHB Master 1 (ARM926EJ-S Data Master) */
95#define AT91_MATRIX_RCB2 (1 << 2)
96#define AT91_MATRIX_RCB3 (1 << 3)
97#define AT91_MATRIX_RCB4 (1 << 4)
98#define AT91_MATRIX_RCB5 (1 << 5)
99#define AT91_MATRIX_RCB6 (1 << 6)
100#define AT91_MATRIX_RCB7 (1 << 7)
101#define AT91_MATRIX_RCB8 (1 << 8)
102#define AT91_MATRIX_RCB9 (1 << 9)
103#define AT91_MATRIX_RCB10 (1 << 10)
104#define AT91_MATRIX_RCB11 (1 << 11)
105
106#define AT91_MPBS0_SFR (AT91_MATRIX + 0x114) /* MPBlock Slave 0 Special Function Register */
107#define AT91_MPBS1_SFR (AT91_MATRIX + 0x11C) /* MPBlock Slave 1 Special Function Register */
108
109#define AT91_MATRIX_EBICSA (AT91_MATRIX + 0x120) /* EBI Chip Select Assignment Register */
110#define AT91_MATRIX_EBI_CS1A (1 << 1) /* Chip Select 1 Assignment */
111#define AT91_MATRIX_EBI_CS1A_SMC (0 << 1)
112#define AT91_MATRIX_EBI_CS1A_BCRAMC (1 << 1)
113#define AT91_MATRIX_EBI_CS3A (1 << 3) /* Chip Select 3 Assignment */
114#define AT91_MATRIX_EBI_CS3A_SMC (0 << 3)
115#define AT91_MATRIX_EBI_CS3A_SMC_SMARTMEDIA (1 << 3)
116#define AT91_MATRIX_EBI_CS4A (1 << 4) /* Chip Select 4 Assignment */
117#define AT91_MATRIX_EBI_CS4A_SMC (0 << 4)
118#define AT91_MATRIX_EBI_CS4A_SMC_CF1 (1 << 4)
119#define AT91_MATRIX_EBI_CS5A (1 << 5) /* Chip Select 5 Assignment */
120#define AT91_MATRIX_EBI_CS5A_SMC (0 << 5)
121#define AT91_MATRIX_EBI_CS5A_SMC_CF2 (1 << 5)
122#define AT91_MATRIX_EBI_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
123#define AT91_MATRIX_EBI_DQSPDC (1 << 9) /* Data Qualifier Strobe Pull-Down Configuration */
124#define AT91_MATRIX_EBI_VDDIOMSEL (1 << 16) /* Memory voltage selection */
125#define AT91_MATRIX_EBI_VDDIOMSEL_1_8V (0 << 16)
126#define AT91_MATRIX_EBI_VDDIOMSEL_3_3V (1 << 16)
127
128#define AT91_MPBS2_SFR (AT91_MATRIX + 0x12C) /* MPBlock Slave 2 Special Function Register */
129#define AT91_MPBS3_SFR (AT91_MATRIX + 0x130) /* MPBlock Slave 3 Special Function Register */
130#define AT91_APB_SFR (AT91_MATRIX + 0x134) /* APB Bridge Special Function Register */
131
132#endif
diff --git a/include/asm-arm/arch-at91/at91sam9260_matrix.h b/include/asm-arm/arch-at91/at91sam9260_matrix.h
index aacb1e976422..a8e9fec6c735 100644
--- a/include/asm-arm/arch-at91/at91sam9260_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9260_matrix.h
@@ -67,7 +67,7 @@
67#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */ 67#define AT91_MATRIX_CS4A (1 << 4) /* Chip Select 4 Assignment */
68#define AT91_MATRIX_CS4A_SMC (0 << 4) 68#define AT91_MATRIX_CS4A_SMC (0 << 4)
69#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4) 69#define AT91_MATRIX_CS4A_SMC_CF1 (1 << 4)
70#define AT91_MATRIX_CS5A (1 << 5 ) /* Chip Select 5 Assignment */ 70#define AT91_MATRIX_CS5A (1 << 5) /* Chip Select 5 Assignment */
71#define AT91_MATRIX_CS5A_SMC (0 << 5) 71#define AT91_MATRIX_CS5A_SMC (0 << 5)
72#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5) 72#define AT91_MATRIX_CS5A_SMC_CF2 (1 << 5)
73#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */ 73#define AT91_MATRIX_DBPUC (1 << 8) /* Data Bus Pull-up Configuration */
diff --git a/include/asm-arm/arch-at91/at91sam9263_matrix.h b/include/asm-arm/arch-at91/at91sam9263_matrix.h
index 6fc6e4be624e..72f6e668e414 100644
--- a/include/asm-arm/arch-at91/at91sam9263_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9263_matrix.h
@@ -44,7 +44,7 @@
44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 44#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 45#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 46#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
47#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ 47#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ 48#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 49#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 50#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/at91sam9rl_matrix.h b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
index b15f11b7c08d..84224174e6a1 100644
--- a/include/asm-arm/arch-at91/at91sam9rl_matrix.h
+++ b/include/asm-arm/arch-at91/at91sam9rl_matrix.h
@@ -38,7 +38,7 @@
38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16) 38#define AT91_MATRIX_DEFMSTR_TYPE_NONE (0 << 16)
39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16) 39#define AT91_MATRIX_DEFMSTR_TYPE_LAST (1 << 16)
40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16) 40#define AT91_MATRIX_DEFMSTR_TYPE_FIXED (2 << 16)
41#define AT91_MATRIX_FIXED_DEFMSTR (7 << 18) /* Fixed Index of Default Master */ 41#define AT91_MATRIX_FIXED_DEFMSTR (0xf << 18) /* Fixed Index of Default Master */
42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */ 42#define AT91_MATRIX_ARBT (3 << 24) /* Arbitration Type */
43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24) 43#define AT91_MATRIX_ARBT_ROUND_ROBIN (0 << 24)
44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24) 44#define AT91_MATRIX_ARBT_FIXED_PRIORITY (1 << 24)
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 79054965baa6..55b07bd5316c 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -34,6 +34,7 @@
34#include <linux/mtd/partitions.h> 34#include <linux/mtd/partitions.h>
35#include <linux/device.h> 35#include <linux/device.h>
36#include <linux/i2c.h> 36#include <linux/i2c.h>
37#include <linux/leds.h>
37#include <linux/spi/spi.h> 38#include <linux/spi/spi.h>
38 39
39 /* USB Device */ 40 /* USB Device */
@@ -71,7 +72,7 @@ struct at91_eth_data {
71}; 72};
72extern void __init at91_add_device_eth(struct at91_eth_data *data); 73extern void __init at91_add_device_eth(struct at91_eth_data *data);
73 74
74#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) 75#if defined(CONFIG_ARCH_AT91SAM9260) || defined(CONFIG_ARCH_AT91SAM9263) || defined(CONFIG_ARCH_AT91CAP9)
75#define eth_platform_data at91_eth_data 76#define eth_platform_data at91_eth_data
76#endif 77#endif
77 78
@@ -101,13 +102,23 @@ extern void __init at91_add_device_i2c(struct i2c_board_info *devices, int nr_de
101extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices); 102extern void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices);
102 103
103 /* Serial */ 104 /* Serial */
105#define ATMEL_UART_CTS 0x01
106#define ATMEL_UART_RTS 0x02
107#define ATMEL_UART_DSR 0x04
108#define ATMEL_UART_DTR 0x08
109#define ATMEL_UART_DCD 0x10
110#define ATMEL_UART_RI 0x20
111
112extern void __init at91_register_uart(unsigned id, unsigned portnr, unsigned pins);
113extern void __init at91_set_serial_console(unsigned portnr);
114
104struct at91_uart_config { 115struct at91_uart_config {
105 unsigned short console_tty; /* tty number of serial console */ 116 unsigned short console_tty; /* tty number of serial console */
106 unsigned short nr_tty; /* number of serial tty's */ 117 unsigned short nr_tty; /* number of serial tty's */
107 short tty_map[]; /* map UART to tty number */ 118 short tty_map[]; /* map UART to tty number */
108}; 119};
109extern struct platform_device *atmel_default_console_device; 120extern struct platform_device *atmel_default_console_device;
110extern void __init at91_init_serial(struct at91_uart_config *config); 121extern void __init __deprecated at91_init_serial(struct at91_uart_config *config);
111 122
112struct atmel_uart_data { 123struct atmel_uart_data {
113 short use_dma_tx; /* use transmit DMA? */ 124 short use_dma_tx; /* use transmit DMA? */
@@ -116,6 +127,23 @@ struct atmel_uart_data {
116}; 127};
117extern void __init at91_add_device_serial(void); 128extern void __init at91_add_device_serial(void);
118 129
130/*
131 * SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
132 * platform devices. Their SSC ID is part of their configuration data,
133 * along with information about which SSC signals they should use.
134 */
135#define ATMEL_SSC_TK 0x01
136#define ATMEL_SSC_TF 0x02
137#define ATMEL_SSC_TD 0x04
138#define ATMEL_SSC_TX (ATMEL_SSC_TK | ATMEL_SSC_TF | ATMEL_SSC_TD)
139
140#define ATMEL_SSC_RK 0x10
141#define ATMEL_SSC_RF 0x20
142#define ATMEL_SSC_RD 0x40
143#define ATMEL_SSC_RX (ATMEL_SSC_RK | ATMEL_SSC_RF | ATMEL_SSC_RD)
144
145extern void __init at91_add_device_ssc(unsigned id, unsigned pins);
146
119 /* LCD Controller */ 147 /* LCD Controller */
120struct atmel_lcdfb_info; 148struct atmel_lcdfb_info;
121extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data); 149extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
@@ -126,10 +154,12 @@ struct atmel_ac97_data {
126}; 154};
127extern void __init at91_add_device_ac97(struct atmel_ac97_data *data); 155extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
128 156
157 /* ISI */
158extern void __init at91_add_device_isi(void);
159
129 /* LEDs */ 160 /* LEDs */
130extern u8 at91_leds_cpu;
131extern u8 at91_leds_timer;
132extern void __init at91_init_leds(u8 cpu_led, u8 timer_led); 161extern void __init at91_init_leds(u8 cpu_led, u8 timer_led);
162extern void __init at91_gpio_leds(struct gpio_led *leds, int nr);
133 163
134/* FIXME: this needs a better location, but gets stuff building again */ 164/* FIXME: this needs a better location, but gets stuff building again */
135extern int at91_suspend_entering_slow_clock(void); 165extern int at91_suspend_entering_slow_clock(void);
diff --git a/include/asm-arm/arch-at91/cpu.h b/include/asm-arm/arch-at91/cpu.h
index 080cbb401a87..7145166826a2 100644
--- a/include/asm-arm/arch-at91/cpu.h
+++ b/include/asm-arm/arch-at91/cpu.h
@@ -21,13 +21,13 @@
21#define ARCH_ID_AT91SAM9260 0x019803a0 21#define ARCH_ID_AT91SAM9260 0x019803a0
22#define ARCH_ID_AT91SAM9261 0x019703a0 22#define ARCH_ID_AT91SAM9261 0x019703a0
23#define ARCH_ID_AT91SAM9263 0x019607a0 23#define ARCH_ID_AT91SAM9263 0x019607a0
24#define ARCH_ID_AT91SAM9RL64 0x019b03a0
25#define ARCH_ID_AT91CAP9 0x039A03A0
24 26
25#define ARCH_ID_AT91SAM9XE128 0x329973a0 27#define ARCH_ID_AT91SAM9XE128 0x329973a0
26#define ARCH_ID_AT91SAM9XE256 0x329a93a0 28#define ARCH_ID_AT91SAM9XE256 0x329a93a0
27#define ARCH_ID_AT91SAM9XE512 0x329aa3a0 29#define ARCH_ID_AT91SAM9XE512 0x329aa3a0
28 30
29#define ARCH_ID_AT91SAM9RL64 0x019b03a0
30
31#define ARCH_ID_AT91M40800 0x14080044 31#define ARCH_ID_AT91M40800 0x14080044
32#define ARCH_ID_AT91R40807 0x44080746 32#define ARCH_ID_AT91R40807 0x44080746
33#define ARCH_ID_AT91M40807 0x14080745 33#define ARCH_ID_AT91M40807 0x14080745
@@ -81,6 +81,11 @@ static inline unsigned long at91_arch_identify(void)
81#define cpu_is_at91sam9rl() (0) 81#define cpu_is_at91sam9rl() (0)
82#endif 82#endif
83 83
84#ifdef CONFIG_ARCH_AT91CAP9
85#define cpu_is_at91cap9() (at91_cpu_identify() == ARCH_ID_AT91CAP9)
86#else
87#define cpu_is_at91cap9() (0)
88#endif
84 89
85/* 90/*
86 * Since this is ARM, we will never run on any AVR32 CPU. But these 91 * Since this is ARM, we will never run on any AVR32 CPU. But these
diff --git a/include/asm-arm/arch-at91/entry-macro.S b/include/asm-arm/arch-at91/entry-macro.S
index cc1d850a0788..1005eee6219b 100644
--- a/include/asm-arm/arch-at91/entry-macro.S
+++ b/include/asm-arm/arch-at91/entry-macro.S
@@ -17,13 +17,13 @@
17 .endm 17 .endm
18 18
19 .macro get_irqnr_preamble, base, tmp 19 .macro get_irqnr_preamble, base, tmp
20 ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
20 .endm 21 .endm
21 22
22 .macro arch_ret_to_user, tmp1, tmp2 23 .macro arch_ret_to_user, tmp1, tmp2
23 .endm 24 .endm
24 25
25 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp 26 .macro get_irqnr_and_base, irqnr, irqstat, base, tmp
26 ldr \base, =(AT91_VA_BASE_SYS + AT91_AIC) @ base virtual address of AIC peripheral
27 ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt) 27 ldr \irqnr, [\base, #(AT91_AIC_IVR - AT91_AIC)] @ read IRQ vector register: de-asserts nIRQ to processor (and clears interrupt)
28 ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number 28 ldr \irqstat, [\base, #(AT91_AIC_ISR - AT91_AIC)] @ read interrupt source number
29 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt 29 teq \irqstat, #0 @ ISR is 0 when no current interrupt, or spurious interrupt
diff --git a/include/asm-arm/arch-at91/hardware.h b/include/asm-arm/arch-at91/hardware.h
index 8f1cdd38a969..2c826d8247a3 100644
--- a/include/asm-arm/arch-at91/hardware.h
+++ b/include/asm-arm/arch-at91/hardware.h
@@ -26,6 +26,8 @@
26#include <asm/arch/at91sam9263.h> 26#include <asm/arch/at91sam9263.h>
27#elif defined(CONFIG_ARCH_AT91SAM9RL) 27#elif defined(CONFIG_ARCH_AT91SAM9RL)
28#include <asm/arch/at91sam9rl.h> 28#include <asm/arch/at91sam9rl.h>
29#elif defined(CONFIG_ARCH_AT91CAP9)
30#include <asm/arch/at91cap9.h>
29#elif defined(CONFIG_ARCH_AT91X40) 31#elif defined(CONFIG_ARCH_AT91X40)
30#include <asm/arch/at91x40.h> 32#include <asm/arch/at91x40.h>
31#else 33#else
diff --git a/include/asm-arm/arch-at91/timex.h b/include/asm-arm/arch-at91/timex.h
index a310698fb4da..f1933b0fa43f 100644
--- a/include/asm-arm/arch-at91/timex.h
+++ b/include/asm-arm/arch-at91/timex.h
@@ -42,6 +42,11 @@
42#define AT91SAM9_MASTER_CLOCK 100000000 42#define AT91SAM9_MASTER_CLOCK 100000000
43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16) 43#define CLOCK_TICK_RATE (AT91SAM9_MASTER_CLOCK/16)
44 44
45#elif defined(CONFIG_ARCH_AT91CAP9)
46
47#define AT91CAP9_MASTER_CLOCK 100000000
48#define CLOCK_TICK_RATE (AT91CAP9_MASTER_CLOCK/16)
49
45#elif defined(CONFIG_ARCH_AT91X40) 50#elif defined(CONFIG_ARCH_AT91X40)
46 51
47#define AT91X40_MASTER_CLOCK 40000000 52#define AT91X40_MASTER_CLOCK 40000000
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-17 03:20:53 -0500