diff options
Diffstat (limited to 'include/asm-arm/arch-at91/at91_twi.h')
| -rw-r--r-- | include/asm-arm/arch-at91/at91_twi.h | 68 |
1 files changed, 0 insertions, 68 deletions
diff --git a/include/asm-arm/arch-at91/at91_twi.h b/include/asm-arm/arch-at91/at91_twi.h deleted file mode 100644 index f9f2e3cd95c5..000000000000 --- a/include/asm-arm/arch-at91/at91_twi.h +++ /dev/null | |||
| @@ -1,68 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_twi.h | ||
| 3 | * | ||
| 4 | * Copyright (C) 2005 Ivan Kokshaysky | ||
| 5 | * Copyright (C) SAN People | ||
| 6 | * | ||
| 7 | * Two-wire Interface (TWI) registers. | ||
| 8 | * Based on AT91RM9200 datasheet revision E. | ||
| 9 | * | ||
| 10 | * This program is free software; you can redistribute it and/or modify | ||
| 11 | * it under the terms of the GNU General Public License as published by | ||
| 12 | * the Free Software Foundation; either version 2 of the License, or | ||
| 13 | * (at your option) any later version. | ||
| 14 | */ | ||
| 15 | |||
| 16 | #ifndef AT91_TWI_H | ||
| 17 | #define AT91_TWI_H | ||
| 18 | |||
| 19 | #define AT91_TWI_CR 0x00 /* Control Register */ | ||
| 20 | #define AT91_TWI_START (1 << 0) /* Send a Start Condition */ | ||
| 21 | #define AT91_TWI_STOP (1 << 1) /* Send a Stop Condition */ | ||
| 22 | #define AT91_TWI_MSEN (1 << 2) /* Master Transfer Enable */ | ||
| 23 | #define AT91_TWI_MSDIS (1 << 3) /* Master Transfer Disable */ | ||
| 24 | #define AT91_TWI_SVEN (1 << 4) /* Slave Transfer Enable [SAM9260 only] */ | ||
| 25 | #define AT91_TWI_SVDIS (1 << 5) /* Slave Transfer Disable [SAM9260 only] */ | ||
| 26 | #define AT91_TWI_SWRST (1 << 7) /* Software Reset */ | ||
| 27 | |||
| 28 | #define AT91_TWI_MMR 0x04 /* Master Mode Register */ | ||
| 29 | #define AT91_TWI_IADRSZ (3 << 8) /* Internal Device Address Size */ | ||
| 30 | #define AT91_TWI_IADRSZ_NO (0 << 8) | ||
| 31 | #define AT91_TWI_IADRSZ_1 (1 << 8) | ||
| 32 | #define AT91_TWI_IADRSZ_2 (2 << 8) | ||
| 33 | #define AT91_TWI_IADRSZ_3 (3 << 8) | ||
| 34 | #define AT91_TWI_MREAD (1 << 12) /* Master Read Direction */ | ||
| 35 | #define AT91_TWI_DADR (0x7f << 16) /* Device Address */ | ||
| 36 | |||
| 37 | #define AT91_TWI_SMR 0x08 /* Slave Mode Register [SAM9260 only] */ | ||
| 38 | #define AT91_TWI_SADR (0x7f << 16) /* Slave Address */ | ||
| 39 | |||
| 40 | #define AT91_TWI_IADR 0x0c /* Internal Address Register */ | ||
| 41 | |||
| 42 | #define AT91_TWI_CWGR 0x10 /* Clock Waveform Generator Register */ | ||
| 43 | #define AT91_TWI_CLDIV (0xff << 0) /* Clock Low Divisor */ | ||
| 44 | #define AT91_TWI_CHDIV (0xff << 8) /* Clock High Divisor */ | ||
| 45 | #define AT91_TWI_CKDIV (7 << 16) /* Clock Divider */ | ||
| 46 | |||
| 47 | #define AT91_TWI_SR 0x20 /* Status Register */ | ||
| 48 | #define AT91_TWI_TXCOMP (1 << 0) /* Transmission Complete */ | ||
| 49 | #define AT91_TWI_RXRDY (1 << 1) /* Receive Holding Register Ready */ | ||
| 50 | #define AT91_TWI_TXRDY (1 << 2) /* Transmit Holding Register Ready */ | ||
| 51 | #define AT91_TWI_SVREAD (1 << 3) /* Slave Read [SAM9260 only] */ | ||
| 52 | #define AT91_TWI_SVACC (1 << 4) /* Slave Access [SAM9260 only] */ | ||
| 53 | #define AT91_TWI_GACC (1 << 5) /* General Call Access [SAM9260 only] */ | ||
| 54 | #define AT91_TWI_OVRE (1 << 6) /* Overrun Error [AT91RM9200 only] */ | ||
| 55 | #define AT91_TWI_UNRE (1 << 7) /* Underrun Error [AT91RM9200 only] */ | ||
| 56 | #define AT91_TWI_NACK (1 << 8) /* Not Acknowledged */ | ||
| 57 | #define AT91_TWI_ARBLST (1 << 9) /* Arbitration Lost [SAM9260 only] */ | ||
| 58 | #define AT91_TWI_SCLWS (1 << 10) /* Clock Wait State [SAM9260 only] */ | ||
| 59 | #define AT91_TWI_EOSACC (1 << 11) /* End of Slave Address [SAM9260 only] */ | ||
| 60 | |||
| 61 | #define AT91_TWI_IER 0x24 /* Interrupt Enable Register */ | ||
| 62 | #define AT91_TWI_IDR 0x28 /* Interrupt Disable Register */ | ||
| 63 | #define AT91_TWI_IMR 0x2c /* Interrupt Mask Register */ | ||
| 64 | #define AT91_TWI_RHR 0x30 /* Receive Holding Register */ | ||
| 65 | #define AT91_TWI_THR 0x34 /* Transmit Holding Register */ | ||
| 66 | |||
| 67 | #endif | ||
| 68 | |||