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-rw-r--r--include/asm-arm/arch-at91/at91_pmc.h111
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diff --git a/include/asm-arm/arch-at91/at91_pmc.h b/include/asm-arm/arch-at91/at91_pmc.h
deleted file mode 100644
index 2001e81f2267..000000000000
--- a/include/asm-arm/arch-at91/at91_pmc.h
+++ /dev/null
@@ -1,111 +0,0 @@
1/*
2 * include/asm-arm/arch-at91/at91_pmc.h
3 *
4 * Copyright (C) 2005 Ivan Kokshaysky
5 * Copyright (C) SAN People
6 *
7 * Power Management Controller (PMC) - System peripherals registers.
8 * Based on AT91RM9200 datasheet revision E.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 */
15
16#ifndef AT91_PMC_H
17#define AT91_PMC_H
18
19#define AT91_PMC_SCER (AT91_PMC + 0x00) /* System Clock Enable Register */
20#define AT91_PMC_SCDR (AT91_PMC + 0x04) /* System Clock Disable Register */
21
22#define AT91_PMC_SCSR (AT91_PMC + 0x08) /* System Clock Status Register */
23#define AT91_PMC_PCK (1 << 0) /* Processor Clock */
24#define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */
25#define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */
26#define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */
27#define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */
28#define AT91CAP9_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91CAP9 only] */
29#define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */
30#define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */
31#define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */
32#define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */
33#define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */
34#define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */
35#define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */
36
37#define AT91_PMC_PCER (AT91_PMC + 0x10) /* Peripheral Clock Enable Register */
38#define AT91_PMC_PCDR (AT91_PMC + 0x14) /* Peripheral Clock Disable Register */
39#define AT91_PMC_PCSR (AT91_PMC + 0x18) /* Peripheral Clock Status Register */
40
41#define AT91_CKGR_UCKR (AT91_PMC + 0x1C) /* UTMI Clock Register [SAM9RL, CAP9] */
42#define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */
43#define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */
44#define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */
45#define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI PLL Start-up Time */
46
47#define AT91_CKGR_MOR (AT91_PMC + 0x20) /* Main Oscillator Register [not on SAM9RL] */
48#define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */
49#define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass [SAM9x, CAP9] */
50#define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */
51
52#define AT91_CKGR_MCFR (AT91_PMC + 0x24) /* Main Clock Frequency Register */
53#define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */
54#define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */
55
56#define AT91_CKGR_PLLAR (AT91_PMC + 0x28) /* PLL A Register */
57#define AT91_CKGR_PLLBR (AT91_PMC + 0x2c) /* PLL B Register */
58#define AT91_PMC_DIV (0xff << 0) /* Divider */
59#define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */
60#define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */
61#define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */
62#define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */
63#define AT91_PMC_USBDIV_1 (0 << 28)
64#define AT91_PMC_USBDIV_2 (1 << 28)
65#define AT91_PMC_USBDIV_4 (2 << 28)
66#define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */
67
68#define AT91_PMC_MCKR (AT91_PMC + 0x30) /* Master Clock Register */
69#define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */
70#define AT91_PMC_CSS_SLOW (0 << 0)
71#define AT91_PMC_CSS_MAIN (1 << 0)
72#define AT91_PMC_CSS_PLLA (2 << 0)
73#define AT91_PMC_CSS_PLLB (3 << 0)
74#define AT91_PMC_PRES (7 << 2) /* Master Clock Prescaler */
75#define AT91_PMC_PRES_1 (0 << 2)
76#define AT91_PMC_PRES_2 (1 << 2)
77#define AT91_PMC_PRES_4 (2 << 2)
78#define AT91_PMC_PRES_8 (3 << 2)
79#define AT91_PMC_PRES_16 (4 << 2)
80#define AT91_PMC_PRES_32 (5 << 2)
81#define AT91_PMC_PRES_64 (6 << 2)
82#define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */
83#define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */
84#define AT91RM9200_PMC_MDIV_2 (1 << 8)
85#define AT91RM9200_PMC_MDIV_3 (2 << 8)
86#define AT91RM9200_PMC_MDIV_4 (3 << 8)
87#define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9,CAP9 only] */
88#define AT91SAM9_PMC_MDIV_2 (1 << 8)
89#define AT91SAM9_PMC_MDIV_4 (2 << 8)
90#define AT91SAM9_PMC_MDIV_6 (3 << 8)
91#define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */
92#define AT91_PMC_PDIV_1 (0 << 12)
93#define AT91_PMC_PDIV_2 (1 << 12)
94
95#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
96
97#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
98#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
99#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
100#define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */
101#define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */
102#define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */
103#define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */
104#define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [AT91CAP9 only] */
105#define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */
106#define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */
107#define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */
108#define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */
109#define AT91_PMC_IMR (AT91_PMC + 0x6c) /* Interrupt Mask Register */
110
111#endif
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