diff options
Diffstat (limited to 'include/asm-arm/arch-at91/at91_adc.h')
| -rw-r--r-- | include/asm-arm/arch-at91/at91_adc.h | 61 |
1 files changed, 0 insertions, 61 deletions
diff --git a/include/asm-arm/arch-at91/at91_adc.h b/include/asm-arm/arch-at91/at91_adc.h deleted file mode 100644 index 6d71ea2637b1..000000000000 --- a/include/asm-arm/arch-at91/at91_adc.h +++ /dev/null | |||
| @@ -1,61 +0,0 @@ | |||
| 1 | /* | ||
| 2 | * include/asm-arm/arch-at91/at91_adc.h | ||
| 3 | * | ||
| 4 | * Copyright (C) SAN People | ||
| 5 | * | ||
| 6 | * Analog-to-Digital Converter (ADC) registers. | ||
| 7 | * Based on AT91SAM9260 datasheet revision D. | ||
| 8 | * | ||
| 9 | * This program is free software; you can redistribute it and/or modify | ||
| 10 | * it under the terms of the GNU General Public License as published by | ||
| 11 | * the Free Software Foundation; either version 2 of the License, or | ||
| 12 | * (at your option) any later version. | ||
| 13 | */ | ||
| 14 | |||
| 15 | #ifndef AT91_ADC_H | ||
| 16 | #define AT91_ADC_H | ||
| 17 | |||
| 18 | #define AT91_ADC_CR 0x00 /* Control Register */ | ||
| 19 | #define AT91_ADC_SWRST (1 << 0) /* Software Reset */ | ||
| 20 | #define AT91_ADC_START (1 << 1) /* Start Conversion */ | ||
| 21 | |||
| 22 | #define AT91_ADC_MR 0x04 /* Mode Register */ | ||
| 23 | #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */ | ||
| 24 | #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */ | ||
| 25 | #define AT91_ADC_TRGSEL_TC0 (0 << 1) | ||
| 26 | #define AT91_ADC_TRGSEL_TC1 (1 << 1) | ||
| 27 | #define AT91_ADC_TRGSEL_TC2 (2 << 1) | ||
| 28 | #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1) | ||
| 29 | #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */ | ||
| 30 | #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */ | ||
| 31 | #define AT91_ADC_PRESCAL (0x3f << 8) /* Prescalar Rate Selection */ | ||
| 32 | #define AT91_ADC_PRESCAL_(x) ((x) << 8) | ||
| 33 | #define AT91_ADC_STARTUP (0x1f << 16) /* Startup Up Time */ | ||
| 34 | #define AT91_ADC_STARTUP_(x) ((x) << 16) | ||
| 35 | #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */ | ||
| 36 | #define AT91_ADC_SHTIM_(x) ((x) << 24) | ||
| 37 | |||
| 38 | #define AT91_ADC_CHER 0x10 /* Channel Enable Register */ | ||
| 39 | #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */ | ||
| 40 | #define AT91_ADC_CHSR 0x18 /* Channel Status Register */ | ||
| 41 | #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */ | ||
| 42 | |||
| 43 | #define AT91_ADC_SR 0x1C /* Status Register */ | ||
| 44 | #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */ | ||
| 45 | #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */ | ||
| 46 | #define AT91_ADC_DRDY (1 << 16) /* Data Ready */ | ||
| 47 | #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */ | ||
| 48 | #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */ | ||
| 49 | #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */ | ||
| 50 | |||
| 51 | #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */ | ||
| 52 | #define AT91_ADC_LDATA (0x3ff) | ||
| 53 | |||
| 54 | #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */ | ||
| 55 | #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */ | ||
| 56 | #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */ | ||
| 57 | |||
| 58 | #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */ | ||
| 59 | #define AT91_ADC_DATA (0x3ff) | ||
| 60 | |||
| 61 | #endif | ||