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-rw-r--r--include/asm-alpha/barrier.h2
-rw-r--r--include/asm-alpha/param.h4
-rw-r--r--include/asm-alpha/pgtable.h21
3 files changed, 24 insertions, 3 deletions
diff --git a/include/asm-alpha/barrier.h b/include/asm-alpha/barrier.h
index 384dc08d6f53..ac78eba909bc 100644
--- a/include/asm-alpha/barrier.h
+++ b/include/asm-alpha/barrier.h
@@ -24,7 +24,7 @@ __asm__ __volatile__("mb": : :"memory")
24#define smp_mb() barrier() 24#define smp_mb() barrier()
25#define smp_rmb() barrier() 25#define smp_rmb() barrier()
26#define smp_wmb() barrier() 26#define smp_wmb() barrier()
27#define smp_read_barrier_depends() barrier() 27#define smp_read_barrier_depends() do { } while (0)
28#endif 28#endif
29 29
30#define set_mb(var, value) \ 30#define set_mb(var, value) \
diff --git a/include/asm-alpha/param.h b/include/asm-alpha/param.h
index 0982f1d39499..e691ecfedb2c 100644
--- a/include/asm-alpha/param.h
+++ b/include/asm-alpha/param.h
@@ -5,8 +5,12 @@
5 hardware ignores reprogramming. We also need userland buy-in to the 5 hardware ignores reprogramming. We also need userland buy-in to the
6 change in HZ, since this is visible in the wait4 resources etc. */ 6 change in HZ, since this is visible in the wait4 resources etc. */
7 7
8#ifdef __KERNEL__
8#define HZ CONFIG_HZ 9#define HZ CONFIG_HZ
9#define USER_HZ HZ 10#define USER_HZ HZ
11#else
12#define HZ 1024
13#endif
10 14
11#define EXEC_PAGESIZE 8192 15#define EXEC_PAGESIZE 8192
12 16
diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h
index 05ce5fba43e3..3f0c59f6d8aa 100644
--- a/include/asm-alpha/pgtable.h
+++ b/include/asm-alpha/pgtable.h
@@ -287,17 +287,34 @@ extern inline pte_t pte_mkspecial(pte_t pte) { return pte; }
287#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1)) 287#define pgd_index(address) (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
288#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address)) 288#define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
289 289
290/*
291 * The smp_read_barrier_depends() in the following functions are required to
292 * order the load of *dir (the pointer in the top level page table) with any
293 * subsequent load of the returned pmd_t *ret (ret is data dependent on *dir).
294 *
295 * If this ordering is not enforced, the CPU might load an older value of
296 * *ret, which may be uninitialized data. See mm/memory.c:__pte_alloc for
297 * more details.
298 *
299 * Note that we never change the mm->pgd pointer after the task is running, so
300 * pgd_offset does not require such a barrier.
301 */
302
290/* Find an entry in the second-level page table.. */ 303/* Find an entry in the second-level page table.. */
291extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address) 304extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
292{ 305{
293 return (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1)); 306 pmd_t *ret = (pmd_t *) pgd_page_vaddr(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PAGE - 1));
307 smp_read_barrier_depends(); /* see above */
308 return ret;
294} 309}
295 310
296/* Find an entry in the third-level page table.. */ 311/* Find an entry in the third-level page table.. */
297extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address) 312extern inline pte_t * pte_offset_kernel(pmd_t * dir, unsigned long address)
298{ 313{
299 return (pte_t *) pmd_page_vaddr(*dir) 314 pte_t *ret = (pte_t *) pmd_page_vaddr(*dir)
300 + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1)); 315 + ((address >> PAGE_SHIFT) & (PTRS_PER_PAGE - 1));
316 smp_read_barrier_depends(); /* see above */
317 return ret;
301} 318}
302 319
303#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr)) 320#define pte_offset_map(dir,addr) pte_offset_kernel((dir),(addr))