1 files changed, 70 insertions, 71 deletions
diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h
index 33de5f4d2ccc..67312c3a915a 100644
--- a/include/acpi/actbl1.h
+++ b/include/acpi/actbl1.h
@@ -49,88 +49,87 @@
 /*
 * ACPI 1.0 Root System Description Table (RSDT)
 */
-struct rsdt_descriptor_rev1
+struct rsdt_descriptor_rev1 {
-{
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
-        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
+        u32 table_offset_entry[1];      /* Array of pointers to ACPI tables */
-        u32                             table_offset_entry [1]; /* Array of pointers to other */
-                         /* ACPI tables */
 };
 /*
 * ACPI 1.0 Firmware ACPI Control Structure (FACS)
 */
-struct facs_descriptor_rev1
+struct facs_descriptor_rev1 {
-{
+        char signature[4];      /* ASCII table signature */
-        char                            signature[4];           /* ACPI Signature */
+        u32 length;             /* Length of structure in bytes */
-        u32                             length;                 /* Length of structure, in bytes */
+        u32 hardware_signature; /* Hardware configuration signature */
-        u32                             hardware_signature;     /* Hardware configuration signature */
+        u32 firmware_waking_vector;     /* ACPI OS waking vector */
-        u32                             firmware_waking_vector; /* ACPI OS waking vector */
+        u32 global_lock;        /* Global Lock */
-        u32                             global_lock;            /* Global Lock */
-        u32                             S4bios_f        : 1;    /* Indicates if S4BIOS support is present */
+        /* Flags (32 bits) */
-        u32                             reserved1       : 31;   /* Must be 0 */
-        u8                              resverved3 [40];        /* Reserved - must be zero */
-};
+        u8 S4bios_f:1;          /* 00:    S4BIOS support is present */
+         u8:7;                  /* 01-07: Reserved, must be zero */
+        u8 reserved1[3];        /* 08-31: Reserved, must be zero */
+        u8 reserved2[40];       /* Reserved, must be zero */
+};
 /*
 * ACPI 1.0 Fixed ACPI Description Table (FADT)
 */
-struct fadt_descriptor_rev1
+struct fadt_descriptor_rev1 {
-{
+        ACPI_TABLE_HEADER_DEF   /* ACPI common table header */
-        ACPI_TABLE_HEADER_DEF                           /* ACPI common table header */
+        u32 firmware_ctrl;      /* Physical address of FACS */
-        u32                             firmware_ctrl;          /* Physical address of FACS */
+        u32 dsdt;               /* Physical address of DSDT */
-        u32                             dsdt;                   /* Physical address of DSDT */
+        u8 model;               /* System Interrupt Model */
-        u8                              model;                  /* System Interrupt Model */
+        u8 reserved1;           /* Reserved, must be zero */
-        u8                              reserved1;              /* Reserved */
+        u16 sci_int;            /* System vector of SCI interrupt */
-        u16                             sci_int;                /* System vector of SCI interrupt */
+        u32 smi_cmd;            /* Port address of SMI command port */
-        u32                             smi_cmd;                /* Port address of SMI command port */
+        u8 acpi_enable;         /* Value to write to smi_cmd to enable ACPI */
-        u8                              acpi_enable;            /* Value to write to smi_cmd to enable ACPI */
+        u8 acpi_disable;        /* Value to write to smi_cmd to disable ACPI */
-        u8                              acpi_disable;           /* Value to write to smi_cmd to disable ACPI */
+        u8 S4bios_req;          /* Value to write to SMI CMD to enter S4BIOS state */
-        u8                              S4bios_req;             /* Value to write to SMI CMD to enter S4BIOS state */
+        u8 reserved2;           /* Reserved, must be zero */
-        u8                              reserved2;              /* Reserved - must be zero */
+        u32 pm1a_evt_blk;       /* Port address of Power Mgt 1a acpi_event Reg Blk */
-        u32                             pm1a_evt_blk;           /* Port address of Power Mgt 1a acpi_event Reg Blk */
+        u32 pm1b_evt_blk;       /* Port address of Power Mgt 1b acpi_event Reg Blk */
-        u32                             pm1b_evt_blk;           /* Port address of Power Mgt 1b acpi_event Reg Blk */
+        u32 pm1a_cnt_blk;       /* Port address of Power Mgt 1a Control Reg Blk */
-        u32                             pm1a_cnt_blk;           /* Port address of Power Mgt 1a Control Reg Blk */
+        u32 pm1b_cnt_blk;       /* Port address of Power Mgt 1b Control Reg Blk */
-        u32                             pm1b_cnt_blk;           /* Port address of Power Mgt 1b Control Reg Blk */
+        u32 pm2_cnt_blk;        /* Port address of Power Mgt 2 Control Reg Blk */
-        u32                             pm2_cnt_blk;            /* Port address of Power Mgt 2 Control Reg Blk */
+        u32 pm_tmr_blk;         /* Port address of Power Mgt Timer Ctrl Reg Blk */
-        u32                             pm_tmr_blk;             /* Port address of Power Mgt Timer Ctrl Reg Blk */
+        u32 gpe0_blk;           /* Port addr of General Purpose acpi_event 0 Reg Blk */
-        u32                             gpe0_blk;               /* Port addr of General Purpose acpi_event 0 Reg Blk */
+        u32 gpe1_blk;           /* Port addr of General Purpose acpi_event 1 Reg Blk */
-        u32                             gpe1_blk;               /* Port addr of General Purpose acpi_event 1 Reg Blk */
+        u8 pm1_evt_len;         /* Byte length of ports at pm1_x_evt_blk */
-        u8                              pm1_evt_len;            /* Byte length of ports at pm1_x_evt_blk */
+        u8 pm1_cnt_len;         /* Byte length of ports at pm1_x_cnt_blk */
-        u8                              pm1_cnt_len;            /* Byte length of ports at pm1_x_cnt_blk */
+        u8 pm2_cnt_len;         /* Byte Length of ports at pm2_cnt_blk */
-        u8                              pm2_cnt_len;            /* Byte Length of ports at pm2_cnt_blk */
+        u8 pm_tm_len;           /* Byte Length of ports at pm_tm_blk */
-        u8                              pm_tm_len;              /* Byte Length of ports at pm_tm_blk */
+        u8 gpe0_blk_len;        /* Byte Length of ports at gpe0_blk */
-        u8                              gpe0_blk_len;           /* Byte Length of ports at gpe0_blk */
+        u8 gpe1_blk_len;        /* Byte Length of ports at gpe1_blk */
-        u8                              gpe1_blk_len;           /* Byte Length of ports at gpe1_blk */
+        u8 gpe1_base;           /* Offset in gpe model where gpe1 events start */
-        u8                              gpe1_base;              /* Offset in gpe model where gpe1 events start */
+        u8 reserved3;           /* Reserved, must be zero */
-        u8                              reserved3;              /* Reserved */
+        u16 plvl2_lat;          /* Worst case HW latency to enter/exit C2 state */
-        u16                             plvl2_lat;              /* Worst case HW latency to enter/exit C2 state */
+        u16 plvl3_lat;          /* Worst case HW latency to enter/exit C3 state */
-        u16                             plvl3_lat;              /* Worst case HW latency to enter/exit C3 state */
+        u16 flush_size;         /* Size of area read to flush caches */
-        u16                             flush_size;             /* Size of area read to flush caches */
+        u16 flush_stride;       /* Stride used in flushing caches */
-        u16                             flush_stride;           /* Stride used in flushing caches */
+        u8 duty_offset;         /* Bit location of duty cycle field in p_cnt reg */
-        u8                              duty_offset;            /* Bit location of duty cycle field in p_cnt reg */
+        u8 duty_width;          /* Bit width of duty cycle field in p_cnt reg */
-        u8                              duty_width;             /* Bit width of duty cycle field in p_cnt reg */
+        u8 day_alrm;            /* Index to day-of-month alarm in RTC CMOS RAM */
-        u8                              day_alrm;               /* Index to day-of-month alarm in RTC CMOS RAM */
+        u8 mon_alrm;            /* Index to month-of-year alarm in RTC CMOS RAM */
-        u8                              mon_alrm;               /* Index to month-of-year alarm in RTC CMOS RAM */
+        u8 century;             /* Index to century in RTC CMOS RAM */
-        u8                              century;                /* Index to century in RTC CMOS RAM */
+        u8 reserved4[3];        /* Reserved, must be zero */
-        u8                              reserved4;              /* Reserved */
-        u8                              reserved4a;             /* Reserved */
-        u8                              reserved4b;             /* Reserved */
-        u32                             wb_invd         : 1;    /* The wbinvd instruction works properly */
-        u32                             wb_invd_flush   : 1;    /* The wbinvd flushes but does not invalidate */
-        u32                             proc_c1         : 1;    /* All processors support C1 state */
-        u32                             plvl2_up        : 1;    /* C2 state works on MP system */
-        u32                             pwr_button      : 1;    /* Power button is handled as a generic feature */
-        u32                             sleep_button    : 1;    /* Sleep button is handled as a generic feature, or not present */
-        u32                             fixed_rTC       : 1;    /* RTC wakeup stat not in fixed register space */
-        u32                             rtcs4           : 1;    /* RTC wakeup stat not possible from S4 */
-        u32                             tmr_val_ext     : 1;    /* The tmr_val width is 32 bits (0 = 24 bits) */
-        u32                             reserved5       : 23;   /* Reserved - must be zero */
-};
-#pragma pack()
+        /* Flags (32 bits) */
-#endif /* __ACTBL1_H__ */
+        u8 wb_invd:1;           /* 00:    The wbinvd instruction works properly */
+        u8 wb_invd_flush:1;     /* 01:    The wbinvd flushes but does not invalidate */
+        u8 proc_c1:1;           /* 02:    All processors support C1 state */
+        u8 plvl2_up:1;          /* 03:    C2 state works on MP system */
+        u8 pwr_button:1;        /* 04:    Power button is handled as a generic feature */
+        u8 sleep_button:1;      /* 05:    Sleep button is handled as a generic feature, or not present */
+        u8 fixed_rTC:1;         /* 06:    RTC wakeup stat not in fixed register space */
+        u8 rtcs4:1;             /* 07:    RTC wakeup stat not possible from S4 */
+        u8 tmr_val_ext:1;       /* 08:    tmr_val width is 32 bits (0 = 24 bits) */
+         u8:7;                  /* 09-15: Reserved, must be zero */
+        u8 reserved5[2];        /* 16-31: Reserved, must be zero */
+};
+#pragma pack()
+#endif                          /* __ACTBL1_H__ */

diff --git a/include/acpi/actbl1.h b/include/acpi/actbl1.h index 33de5f4d2ccc..67312c3a915a 100644 --- a/include/acpi/actbl1.h +++ b/include/acpi/actbl1.h
@@ -49,88 +49,87 @@
49	/*	49	/*
50	* ACPI 1.0 Root System Description Table (RSDT)	50	* ACPI 1.0 Root System Description Table (RSDT)
51	*/	51	*/
52	struct rsdt_descriptor_rev1	52	struct rsdt_descriptor_rev1 {
53	{	53	ACPI_TABLE_HEADER_DEF /* ACPI common table header */
54	ACPI_TABLE_HEADER_DEF /* ACPI common table header */	54	u32 table_offset_entry[1]; /* Array of pointers to ACPI tables */
55	u32 table_offset_entry [1]; /* Array of pointers to other */
56	/* ACPI tables */
57	};	55	};
58		56
59
60	/*	57	/*
61	* ACPI 1.0 Firmware ACPI Control Structure (FACS)	58	* ACPI 1.0 Firmware ACPI Control Structure (FACS)
62	*/	59	*/
63	struct facs_descriptor_rev1	60	struct facs_descriptor_rev1 {
64	{	61	char signature[4]; /* ASCII table signature */
65	char signature[4]; /* ACPI Signature */	62	u32 length; /* Length of structure in bytes */
66	u32 length; /* Length of structure, in bytes */	63	u32 hardware_signature; /* Hardware configuration signature */
67	u32 hardware_signature; /* Hardware configuration signature */	64	u32 firmware_waking_vector; /* ACPI OS waking vector */
68	u32 firmware_waking_vector; /* ACPI OS waking vector */	65	u32 global_lock; /* Global Lock */
69	u32 global_lock; /* Global Lock */	66
70	u32 S4bios_f : 1; /* Indicates if S4BIOS support is present */	67	/* Flags (32 bits) */
71	u32 reserved1 : 31; /* Must be 0 */
72	u8 resverved3 [40]; /* Reserved - must be zero */
73	};
74		68
		69	u8 S4bios_f:1; /* 00: S4BIOS support is present */
		70	u8:7; /* 01-07: Reserved, must be zero */
		71	u8 reserved1[3]; /* 08-31: Reserved, must be zero */
		72
		73	u8 reserved2[40]; /* Reserved, must be zero */
		74	};
75		75
76	/*	76	/*
77	* ACPI 1.0 Fixed ACPI Description Table (FADT)	77	* ACPI 1.0 Fixed ACPI Description Table (FADT)
78	*/	78	*/
79	struct fadt_descriptor_rev1	79	struct fadt_descriptor_rev1 {
80	{	80	ACPI_TABLE_HEADER_DEF /* ACPI common table header */
81	ACPI_TABLE_HEADER_DEF /* ACPI common table header */	81	u32 firmware_ctrl; /* Physical address of FACS */
82	u32 firmware_ctrl; /* Physical address of FACS */	82	u32 dsdt; /* Physical address of DSDT */
83	u32 dsdt; /* Physical address of DSDT */	83	u8 model; /* System Interrupt Model */
84	u8 model; /* System Interrupt Model */	84	u8 reserved1; /* Reserved, must be zero */
85	u8 reserved1; /* Reserved */	85	u16 sci_int; /* System vector of SCI interrupt */
86	u16 sci_int; /* System vector of SCI interrupt */	86	u32 smi_cmd; /* Port address of SMI command port */
87	u32 smi_cmd; /* Port address of SMI command port */	87	u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */
88	u8 acpi_enable; /* Value to write to smi_cmd to enable ACPI */	88	u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */
89	u8 acpi_disable; /* Value to write to smi_cmd to disable ACPI */	89	u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */
90	u8 S4bios_req; /* Value to write to SMI CMD to enter S4BIOS state */	90	u8 reserved2; /* Reserved, must be zero */
91	u8 reserved2; /* Reserved - must be zero */	91	u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */
92	u32 pm1a_evt_blk; /* Port address of Power Mgt 1a acpi_event Reg Blk */	92	u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */
93	u32 pm1b_evt_blk; /* Port address of Power Mgt 1b acpi_event Reg Blk */	93	u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */
94	u32 pm1a_cnt_blk; /* Port address of Power Mgt 1a Control Reg Blk */	94	u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */
95	u32 pm1b_cnt_blk; /* Port address of Power Mgt 1b Control Reg Blk */	95	u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */
96	u32 pm2_cnt_blk; /* Port address of Power Mgt 2 Control Reg Blk */	96	u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */
97	u32 pm_tmr_blk; /* Port address of Power Mgt Timer Ctrl Reg Blk */	97	u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */
98	u32 gpe0_blk; /* Port addr of General Purpose acpi_event 0 Reg Blk */	98	u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */
99	u32 gpe1_blk; /* Port addr of General Purpose acpi_event 1 Reg Blk */	99	u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */
100	u8 pm1_evt_len; /* Byte length of ports at pm1_x_evt_blk */	100	u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */
101	u8 pm1_cnt_len; /* Byte length of ports at pm1_x_cnt_blk */	101	u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */
102	u8 pm2_cnt_len; /* Byte Length of ports at pm2_cnt_blk */	102	u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */
103	u8 pm_tm_len; /* Byte Length of ports at pm_tm_blk */	103	u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */
104	u8 gpe0_blk_len; /* Byte Length of ports at gpe0_blk */	104	u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */
105	u8 gpe1_blk_len; /* Byte Length of ports at gpe1_blk */	105	u8 gpe1_base; /* Offset in gpe model where gpe1 events start */
106	u8 gpe1_base; /* Offset in gpe model where gpe1 events start */	106	u8 reserved3; /* Reserved, must be zero */
107	u8 reserved3; /* Reserved */	107	u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */
108	u16 plvl2_lat; /* Worst case HW latency to enter/exit C2 state */	108	u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */
109	u16 plvl3_lat; /* Worst case HW latency to enter/exit C3 state */	109	u16 flush_size; /* Size of area read to flush caches */
110	u16 flush_size; /* Size of area read to flush caches */	110	u16 flush_stride; /* Stride used in flushing caches */
111	u16 flush_stride; /* Stride used in flushing caches */	111	u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */
112	u8 duty_offset; /* Bit location of duty cycle field in p_cnt reg */	112	u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */
113	u8 duty_width; /* Bit width of duty cycle field in p_cnt reg */	113	u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */
114	u8 day_alrm; /* Index to day-of-month alarm in RTC CMOS RAM */	114	u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */
115	u8 mon_alrm; /* Index to month-of-year alarm in RTC CMOS RAM */	115	u8 century; /* Index to century in RTC CMOS RAM */
116	u8 century; /* Index to century in RTC CMOS RAM */	116	u8 reserved4[3]; /* Reserved, must be zero */
117	u8 reserved4; /* Reserved */
118	u8 reserved4a; /* Reserved */
119	u8 reserved4b; /* Reserved */
120	u32 wb_invd : 1; /* The wbinvd instruction works properly */
121	u32 wb_invd_flush : 1; /* The wbinvd flushes but does not invalidate */
122	u32 proc_c1 : 1; /* All processors support C1 state */
123	u32 plvl2_up : 1; /* C2 state works on MP system */
124	u32 pwr_button : 1; /* Power button is handled as a generic feature */
125	u32 sleep_button : 1; /* Sleep button is handled as a generic feature, or not present */
126	u32 fixed_rTC : 1; /* RTC wakeup stat not in fixed register space */
127	u32 rtcs4 : 1; /* RTC wakeup stat not possible from S4 */
128	u32 tmr_val_ext : 1; /* The tmr_val width is 32 bits (0 = 24 bits) */
129	u32 reserved5 : 23; /* Reserved - must be zero */
130	};
131		117
132	#pragma pack()	118	/* Flags (32 bits) */
133		119
134	#endif /* __ACTBL1_H__ */	120	u8 wb_invd:1; /* 00: The wbinvd instruction works properly */
		121	u8 wb_invd_flush:1; /* 01: The wbinvd flushes but does not invalidate */
		122	u8 proc_c1:1; /* 02: All processors support C1 state */
		123	u8 plvl2_up:1; /* 03: C2 state works on MP system */
		124	u8 pwr_button:1; /* 04: Power button is handled as a generic feature */
		125	u8 sleep_button:1; /* 05: Sleep button is handled as a generic feature, or not present */
		126	u8 fixed_rTC:1; /* 06: RTC wakeup stat not in fixed register space */
		127	u8 rtcs4:1; /* 07: RTC wakeup stat not possible from S4 */
		128	u8 tmr_val_ext:1; /* 08: tmr_val width is 32 bits (0 = 24 bits) */
		129	u8:7; /* 09-15: Reserved, must be zero */
		130	u8 reserved5[2]; /* 16-31: Reserved, must be zero */
		131	};
135		132
		133	#pragma pack()
136		134
		135	#endif /* __ACTBL1_H__ */