diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/dma/ste_dma40.c | 72 | ||||
-rw-r--r-- | drivers/dma/ste_dma40_ll.h | 3 |
2 files changed, 26 insertions, 49 deletions
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c index 35b078d688d5..2797f64e5e48 100644 --- a/drivers/dma/ste_dma40.c +++ b/drivers/dma/ste_dma40.c | |||
@@ -13,6 +13,7 @@ | |||
13 | #include <linux/clk.h> | 13 | #include <linux/clk.h> |
14 | #include <linux/delay.h> | 14 | #include <linux/delay.h> |
15 | #include <linux/err.h> | 15 | #include <linux/err.h> |
16 | #include <linux/amba/bus.h> | ||
16 | 17 | ||
17 | #include <plat/ste_dma40.h> | 18 | #include <plat/ste_dma40.h> |
18 | 19 | ||
@@ -44,9 +45,6 @@ | |||
44 | #define D40_ALLOC_PHY (1 << 30) | 45 | #define D40_ALLOC_PHY (1 << 30) |
45 | #define D40_ALLOC_LOG_FREE 0 | 46 | #define D40_ALLOC_LOG_FREE 0 |
46 | 47 | ||
47 | /* Hardware designer of the block */ | ||
48 | #define D40_HW_DESIGNER 0x8 | ||
49 | |||
50 | /** | 48 | /** |
51 | * enum 40_command - The different commands and/or statuses. | 49 | * enum 40_command - The different commands and/or statuses. |
52 | * | 50 | * |
@@ -2525,25 +2523,6 @@ static int __init d40_phy_res_init(struct d40_base *base) | |||
2525 | 2523 | ||
2526 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) | 2524 | static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) |
2527 | { | 2525 | { |
2528 | static const struct d40_reg_val dma_id_regs[] = { | ||
2529 | /* Peripheral Id */ | ||
2530 | { .reg = D40_DREG_PERIPHID0, .val = 0x0040}, | ||
2531 | { .reg = D40_DREG_PERIPHID1, .val = 0x0000}, | ||
2532 | /* | ||
2533 | * D40_DREG_PERIPHID2 Depends on HW revision: | ||
2534 | * DB8500ed has 0x0008, | ||
2535 | * ? has 0x0018, | ||
2536 | * DB8500v1 has 0x0028 | ||
2537 | * DB8500v2 has 0x0038 | ||
2538 | */ | ||
2539 | { .reg = D40_DREG_PERIPHID3, .val = 0x0000}, | ||
2540 | |||
2541 | /* PCell Id */ | ||
2542 | { .reg = D40_DREG_CELLID0, .val = 0x000d}, | ||
2543 | { .reg = D40_DREG_CELLID1, .val = 0x00f0}, | ||
2544 | { .reg = D40_DREG_CELLID2, .val = 0x0005}, | ||
2545 | { .reg = D40_DREG_CELLID3, .val = 0x00b1} | ||
2546 | }; | ||
2547 | struct stedma40_platform_data *plat_data; | 2526 | struct stedma40_platform_data *plat_data; |
2548 | struct clk *clk = NULL; | 2527 | struct clk *clk = NULL; |
2549 | void __iomem *virtbase = NULL; | 2528 | void __iomem *virtbase = NULL; |
@@ -2552,8 +2531,9 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) | |||
2552 | int num_log_chans = 0; | 2531 | int num_log_chans = 0; |
2553 | int num_phy_chans; | 2532 | int num_phy_chans; |
2554 | int i; | 2533 | int i; |
2555 | u32 val; | 2534 | u32 pid; |
2556 | u32 rev; | 2535 | u32 cid; |
2536 | u8 rev; | ||
2557 | 2537 | ||
2558 | clk = clk_get(&pdev->dev, NULL); | 2538 | clk = clk_get(&pdev->dev, NULL); |
2559 | 2539 | ||
@@ -2577,32 +2557,32 @@ static struct d40_base * __init d40_hw_detect_init(struct platform_device *pdev) | |||
2577 | if (!virtbase) | 2557 | if (!virtbase) |
2578 | goto failure; | 2558 | goto failure; |
2579 | 2559 | ||
2580 | /* HW version check */ | 2560 | /* This is just a regular AMBA PrimeCell ID actually */ |
2581 | for (i = 0; i < ARRAY_SIZE(dma_id_regs); i++) { | 2561 | for (pid = 0, i = 0; i < 4; i++) |
2582 | if (dma_id_regs[i].val != | 2562 | pid |= (readl(virtbase + resource_size(res) - 0x20 + 4 * i) |
2583 | readl(virtbase + dma_id_regs[i].reg)) { | 2563 | & 255) << (i * 8); |
2584 | d40_err(&pdev->dev, | 2564 | for (cid = 0, i = 0; i < 4; i++) |
2585 | "Unknown hardware! Expected 0x%x at 0x%x but got 0x%x\n", | 2565 | cid |= (readl(virtbase + resource_size(res) - 0x10 + 4 * i) |
2586 | dma_id_regs[i].val, | 2566 | & 255) << (i * 8); |
2587 | dma_id_regs[i].reg, | ||
2588 | readl(virtbase + dma_id_regs[i].reg)); | ||
2589 | goto failure; | ||
2590 | } | ||
2591 | } | ||
2592 | |||
2593 | /* Get silicon revision and designer */ | ||
2594 | val = readl(virtbase + D40_DREG_PERIPHID2); | ||
2595 | 2567 | ||
2596 | if ((val & D40_DREG_PERIPHID2_DESIGNER_MASK) != | 2568 | if (cid != AMBA_CID) { |
2597 | D40_HW_DESIGNER) { | 2569 | d40_err(&pdev->dev, "Unknown hardware! No PrimeCell ID\n"); |
2570 | goto failure; | ||
2571 | } | ||
2572 | if (AMBA_MANF_BITS(pid) != AMBA_VENDOR_ST) { | ||
2598 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", | 2573 | d40_err(&pdev->dev, "Unknown designer! Got %x wanted %x\n", |
2599 | val & D40_DREG_PERIPHID2_DESIGNER_MASK, | 2574 | AMBA_MANF_BITS(pid), |
2600 | D40_HW_DESIGNER); | 2575 | AMBA_VENDOR_ST); |
2601 | goto failure; | 2576 | goto failure; |
2602 | } | 2577 | } |
2603 | 2578 | /* | |
2604 | rev = (val & D40_DREG_PERIPHID2_REV_MASK) >> | 2579 | * HW revision: |
2605 | D40_DREG_PERIPHID2_REV_POS; | 2580 | * DB8500ed has revision 0 |
2581 | * ? has revision 1 | ||
2582 | * DB8500v1 has revision 2 | ||
2583 | * DB8500v2 has revision 3 | ||
2584 | */ | ||
2585 | rev = AMBA_REV_BITS(pid); | ||
2606 | 2586 | ||
2607 | /* The number of physical channels on this HW */ | 2587 | /* The number of physical channels on this HW */ |
2608 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; | 2588 | num_phy_chans = 4 * (readl(virtbase + D40_DREG_ICFG) & 0x7) + 4; |
diff --git a/drivers/dma/ste_dma40_ll.h b/drivers/dma/ste_dma40_ll.h index 195ee65ee7f3..b44c455158de 100644 --- a/drivers/dma/ste_dma40_ll.h +++ b/drivers/dma/ste_dma40_ll.h | |||
@@ -184,9 +184,6 @@ | |||
184 | #define D40_DREG_PERIPHID0 0xFE0 | 184 | #define D40_DREG_PERIPHID0 0xFE0 |
185 | #define D40_DREG_PERIPHID1 0xFE4 | 185 | #define D40_DREG_PERIPHID1 0xFE4 |
186 | #define D40_DREG_PERIPHID2 0xFE8 | 186 | #define D40_DREG_PERIPHID2 0xFE8 |
187 | #define D40_DREG_PERIPHID2_REV_POS 4 | ||
188 | #define D40_DREG_PERIPHID2_REV_MASK (0xf << D40_DREG_PERIPHID2_REV_POS) | ||
189 | #define D40_DREG_PERIPHID2_DESIGNER_MASK 0xf | ||
190 | #define D40_DREG_PERIPHID3 0xFEC | 187 | #define D40_DREG_PERIPHID3 0xFEC |
191 | #define D40_DREG_CELLID0 0xFF0 | 188 | #define D40_DREG_CELLID0 0xFF0 |
192 | #define D40_DREG_CELLID1 0xFF4 | 189 | #define D40_DREG_CELLID1 0xFF4 |