11 files changed, 777 insertions, 51 deletions

diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index 5286e2d333b0..1f70e84b442c 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -4,6 +4,15 @@
 
 menu "Bus devices"
 
+config IMX_WEIM
+        bool "Freescale EIM DRIVER"
+        depends on ARCH_MXC
+        help
+          Driver for i.MX6 WEIM controller.
+          The WEIM(Wireless External Interface Module) works like a bus.
+          You can attach many different devices on it, such as NOR, onenand.
+          But now, we only support the Parallel NOR.
+
 config MVEBU_MBUS
         bool
         depends on PLAT_ORION
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 670cea443802..8947bdd0de8b 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -2,6 +2,7 @@
 # Makefile for the bus drivers.
 #
 
+obj-$(CONFIG_IMX_WEIM)  += imx-weim.o
 obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o
 obj-$(CONFIG_OMAP_OCP2SCP)      += omap-ocp2scp.o
 
diff --git a/drivers/bus/imx-weim.c b/drivers/bus/imx-weim.c
new file mode 100644
index 000000000000..349f14e886b7
--- /dev/null
+++ b/drivers/bus/imx-weim.c
@@ -0,0 +1,138 @@
+/*
+ * EIM driver for Freescale's i.MX chips
+ *
+ * Copyright (C) 2013 Freescale Semiconductor, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/module.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/of_device.h>
+
+struct imx_weim {
+        void __iomem *base;
+        struct clk *clk;
+};
+
+static const struct of_device_id weim_id_table[] = {
+        { .compatible = "fsl,imx6q-weim", },
+        {}
+};
+MODULE_DEVICE_TABLE(of, weim_id_table);
+
+#define CS_TIMING_LEN 6
+#define CS_REG_RANGE  0x18
+
+/* Parse and set the timing for this device. */
+static int
+weim_timing_setup(struct platform_device *pdev, struct device_node *np)
+{
+        struct imx_weim *weim = platform_get_drvdata(pdev);
+        u32 value[CS_TIMING_LEN];
+        u32 cs_idx;
+        int ret;
+        int i;
+
+        /* get the CS index from this child node's "reg" property. */
+        ret = of_property_read_u32(np, "reg", &cs_idx);
+        if (ret)
+                return ret;
+
+        /* The weim has four chip selects. */
+        if (cs_idx > 3)
+                return -EINVAL;
+
+        ret = of_property_read_u32_array(np, "fsl,weim-cs-timing",
+                                        value, CS_TIMING_LEN);
+        if (ret)
+                return ret;
+
+        /* set the timing for WEIM */
+        for (i = 0; i < CS_TIMING_LEN; i++)
+                writel(value[i], weim->base + cs_idx * CS_REG_RANGE + i * 4);
+        return 0;
+}
+
+static int weim_parse_dt(struct platform_device *pdev)
+{
+        struct device_node *child;
+        int ret;
+
+        for_each_child_of_node(pdev->dev.of_node, child) {
+                if (!child->name)
+                        continue;
+
+                ret = weim_timing_setup(pdev, child);
+                if (ret) {
+                        dev_err(&pdev->dev, "%s set timing failed.\n",
+                                child->full_name);
+                        return ret;
+                }
+        }
+
+        ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
+        if (ret)
+                dev_err(&pdev->dev, "%s fail to create devices.\n",
+                        pdev->dev.of_node->full_name);
+        return ret;
+}
+
+static int weim_probe(struct platform_device *pdev)
+{
+        struct imx_weim *weim;
+        struct resource *res;
+        int ret = -EINVAL;
+
+        weim = devm_kzalloc(&pdev->dev, sizeof(*weim), GFP_KERNEL);
+        if (!weim) {
+                ret = -ENOMEM;
+                goto weim_err;
+        }
+        platform_set_drvdata(pdev, weim);
+
+        /* get the resource */
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        weim->base = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(weim->base)) {
+                ret = PTR_ERR(weim->base);
+                goto weim_err;
+        }
+
+        /* get the clock */
+        weim->clk = devm_clk_get(&pdev->dev, NULL);
+        if (IS_ERR(weim->clk))
+                goto weim_err;
+
+        ret = clk_prepare_enable(weim->clk);
+        if (ret)
+                goto weim_err;
+
+        /* parse the device node */
+        ret = weim_parse_dt(pdev);
+        if (ret) {
+                clk_disable_unprepare(weim->clk);
+                goto weim_err;
+        }
+
+        dev_info(&pdev->dev, "WEIM driver registered.\n");
+        return 0;
+
+weim_err:
+        return ret;
+}
+
+static struct platform_driver weim_driver = {
+        .driver = {
+                .name = "imx-weim",
+                .of_match_table = weim_id_table,
+        },
+        .probe   = weim_probe,
+};
+
+module_platform_driver(weim_driver);
+MODULE_AUTHOR("Freescale Semiconductor Inc.");
+MODULE_DESCRIPTION("i.MX EIM Controller Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/clk-nomadik.c b/drivers/clk/clk-nomadik.c
index 6b4c70f7d23d..6d819a37f647 100644
--- a/drivers/clk/clk-nomadik.c
+++ b/drivers/clk/clk-nomadik.c
@@ -1,48 +1,566 @@
+/*
+ * Nomadik clock implementation
+ * Copyright (C) 2013 ST-Ericsson AB
+ * License terms: GNU General Public License (GPL) version 2
+ * Author: Linus Walleij <linus.walleij@linaro.org>
+ */
+
+#define pr_fmt(fmt) "Nomadik SRC clocks: " fmt
+
+#include <linux/bitops.h>
 #include <linux/clk.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>
 #include <linux/io.h>
 #include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/debugfs.h>
+#include <linux/seq_file.h>
+#include <linux/spinlock.h>
+#include <linux/reboot.h>
 
 /*
  * The Nomadik clock tree is described in the STN8815A12 DB V4.2
  * reference manual for the chip, page 94 ff.
+ * Clock IDs are in the STn8815 Reference Manual table 3, page 27.
  */
 
-void __init nomadik_clk_init(void)
+#define SRC_CR                  0x00U
+#define SRC_XTALCR              0x0CU
+#define SRC_XTALCR_XTALTIMEN    BIT(20)
+#define SRC_XTALCR_SXTALDIS     BIT(19)
+#define SRC_XTALCR_MXTALSTAT    BIT(2)
+#define SRC_XTALCR_MXTALEN      BIT(1)
+#define SRC_XTALCR_MXTALOVER    BIT(0)
+#define SRC_PLLCR               0x10U
+#define SRC_PLLCR_PLLTIMEN      BIT(29)
+#define SRC_PLLCR_PLL2EN        BIT(28)
+#define SRC_PLLCR_PLL1STAT      BIT(2)
+#define SRC_PLLCR_PLL1EN        BIT(1)
+#define SRC_PLLCR_PLL1OVER      BIT(0)
+#define SRC_PLLFR               0x14U
+#define SRC_PCKEN0              0x24U
+#define SRC_PCKDIS0             0x28U
+#define SRC_PCKENSR0            0x2CU
+#define SRC_PCKSR0              0x30U
+#define SRC_PCKEN1              0x34U
+#define SRC_PCKDIS1             0x38U
+#define SRC_PCKENSR1            0x3CU
+#define SRC_PCKSR1              0x40U
+
+/* Lock protecting the SRC_CR register */
+static DEFINE_SPINLOCK(src_lock);
+/* Base address of the SRC */
+static void __iomem *src_base;
+
+/**
+ * struct clk_pll1 - Nomadik PLL1 clock
+ * @hw: corresponding clock hardware entry
+ * @id: PLL instance: 1 or 2
+ */
+struct clk_pll {
+        struct clk_hw hw;
+        int id;
+};
+
+/**
+ * struct clk_src - Nomadik src clock
+ * @hw: corresponding clock hardware entry
+ * @id: the clock ID
+ * @group1: true if the clock is in group1, else it is in group0
+ * @clkbit: bit 0...31 corresponding to the clock in each clock register
+ */
+struct clk_src {
+        struct clk_hw hw;
+        int id;
+        bool group1;
+        u32 clkbit;
+};
+
+#define to_pll(_hw) container_of(_hw, struct clk_pll, hw)
+#define to_src(_hw) container_of(_hw, struct clk_src, hw)
+
+static int pll_clk_enable(struct clk_hw *hw)
+{
+        struct clk_pll *pll = to_pll(hw);
+        u32 val;
+
+        spin_lock(&src_lock);
+        val = readl(src_base + SRC_PLLCR);
+        if (pll->id == 1) {
+                if (val & SRC_PLLCR_PLL1OVER) {
+                        val |= SRC_PLLCR_PLL1EN;
+                        writel(val, src_base + SRC_PLLCR);
+                }
+        } else if (pll->id == 2) {
+                val |= SRC_PLLCR_PLL2EN;
+                writel(val, src_base + SRC_PLLCR);
+        }
+        spin_unlock(&src_lock);
+        return 0;
+}
+
+static void pll_clk_disable(struct clk_hw *hw)
+{
+        struct clk_pll *pll = to_pll(hw);
+        u32 val;
+
+        spin_lock(&src_lock);
+        val = readl(src_base + SRC_PLLCR);
+        if (pll->id == 1) {
+                if (val & SRC_PLLCR_PLL1OVER) {
+                        val &= ~SRC_PLLCR_PLL1EN;
+                        writel(val, src_base + SRC_PLLCR);
+                }
+        } else if (pll->id == 2) {
+                val &= ~SRC_PLLCR_PLL2EN;
+                writel(val, src_base + SRC_PLLCR);
+        }
+        spin_unlock(&src_lock);
+}
+
+static int pll_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_pll *pll = to_pll(hw);
+        u32 val;
+
+        val = readl(src_base + SRC_PLLCR);
+        if (pll->id == 1) {
+                if (val & SRC_PLLCR_PLL1OVER)
+                        return !!(val & SRC_PLLCR_PLL1EN);
+        } else if (pll->id == 2) {
+                return !!(val & SRC_PLLCR_PLL2EN);
+        }
+        return 1;
+}
+
+static unsigned long pll_clk_recalc_rate(struct clk_hw *hw,
+                                          unsigned long parent_rate)
+{
+        struct clk_pll *pll = to_pll(hw);
+        u32 val;
+
+        val = readl(src_base + SRC_PLLFR);
+
+        if (pll->id == 1) {
+                u8 mul;
+                u8 div;
+
+                mul = (val >> 8) & 0x3FU;
+                mul += 2;
+                div = val & 0x07U;
+                return (parent_rate * mul) >> div;
+        }
+
+        if (pll->id == 2) {
+                u8 mul;
+
+                mul = (val >> 24) & 0x3FU;
+                mul += 2;
+                return (parent_rate * mul);
+        }
+
+        /* Unknown PLL */
+        return 0;
+}
+
+
+static const struct clk_ops pll_clk_ops = {
+        .enable = pll_clk_enable,
+        .disable = pll_clk_disable,
+        .is_enabled = pll_clk_is_enabled,
+        .recalc_rate = pll_clk_recalc_rate,
+};
+
+static struct clk * __init
+pll_clk_register(struct device *dev, const char *name,
+                 const char *parent_name, u32 id)
 {
         struct clk *clk;
+        struct clk_pll *pll;
+        struct clk_init_data init;
 
-        clk = clk_register_fixed_rate(NULL, "apb_pclk", NULL, CLK_IS_ROOT, 0);
-        clk_register_clkdev(clk, "apb_pclk", NULL);
-        clk_register_clkdev(clk, NULL, "gpio.0");
-        clk_register_clkdev(clk, NULL, "gpio.1");
-        clk_register_clkdev(clk, NULL, "gpio.2");
-        clk_register_clkdev(clk, NULL, "gpio.3");
-        clk_register_clkdev(clk, NULL, "rng");
-        clk_register_clkdev(clk, NULL, "fsmc-nand");
+        if (id != 1 && id != 2) {
+                pr_err("%s: the Nomadik has only PLL 1 & 2\n", __func__);
+                return ERR_PTR(-EINVAL);
+        }
 
-        /*
-         * The 2.4 MHz TIMCLK reference clock is active at boot time, this is
-         * actually the MXTALCLK @19.2 MHz divided by 8. This clock is used
-         * by the timers and watchdog. See page 105 ff.
-         */
-        clk = clk_register_fixed_rate(NULL, "TIMCLK", NULL, CLK_IS_ROOT,
-                                      2400000);
-        clk_register_clkdev(clk, NULL, "mtu0");
-        clk_register_clkdev(clk, NULL, "mtu1");
+        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: could not allocate PLL clk\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        init.name = name;
+        init.ops = &pll_clk_ops;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+        pll->hw.init = &init;
+        pll->id = id;
+
+        pr_debug("register PLL1 clock \"%s\"\n", name);
+
+        clk = clk_register(dev, &pll->hw);
+        if (IS_ERR(clk))
+                kfree(pll);
+
+        return clk;
+}
+
+/*
+ * The Nomadik SRC clocks are gated, but not in the sense that
+ * you read-modify-write a register. Instead there are separate
+ * clock enable and clock disable registers. Writing a '1' bit in
+ * the enable register for a certain clock ungates that clock without
+ * affecting the other clocks. The disable register works the opposite
+ * way.
+ */
+
+static int src_clk_enable(struct clk_hw *hw)
+{
+        struct clk_src *sclk = to_src(hw);
+        u32 enreg = sclk->group1 ? SRC_PCKEN1 : SRC_PCKEN0;
+        u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
+
+        writel(sclk->clkbit, src_base + enreg);
+        /* spin until enabled */
+        while (!(readl(src_base + sreg) & sclk->clkbit))
+                cpu_relax();
+        return 0;
+}
+
+static void src_clk_disable(struct clk_hw *hw)
+{
+        struct clk_src *sclk = to_src(hw);
+        u32 disreg = sclk->group1 ? SRC_PCKDIS1 : SRC_PCKDIS0;
+        u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
+
+        writel(sclk->clkbit, src_base + disreg);
+        /* spin until disabled */
+        while (readl(src_base + sreg) & sclk->clkbit)
+                cpu_relax();
+}
+
+static int src_clk_is_enabled(struct clk_hw *hw)
+{
+        struct clk_src *sclk = to_src(hw);
+        u32 sreg = sclk->group1 ? SRC_PCKSR1 : SRC_PCKSR0;
+        u32 val = readl(src_base + sreg);
 
+        return !!(val & sclk->clkbit);
+}
+
+static unsigned long
+src_clk_recalc_rate(struct clk_hw *hw,
+                    unsigned long parent_rate)
+{
+        return parent_rate;
+}
+
+static const struct clk_ops src_clk_ops = {
+        .enable = src_clk_enable,
+        .disable = src_clk_disable,
+        .is_enabled = src_clk_is_enabled,
+        .recalc_rate = src_clk_recalc_rate,
+};
+
+static struct clk * __init
+src_clk_register(struct device *dev, const char *name,
+                 const char *parent_name, u8 id)
+{
+        struct clk *clk;
+        struct clk_src *sclk;
+        struct clk_init_data init;
+
+        sclk = kzalloc(sizeof(*sclk), GFP_KERNEL);
+        if (!sclk) {
+                pr_err("could not allocate SRC clock %s\n",
+                        name);
+                return ERR_PTR(-ENOMEM);
+        }
+        init.name = name;
+        init.ops = &src_clk_ops;
+        /* Do not force-disable the static SDRAM controller */
+        if (id == 2)
+                init.flags = CLK_IGNORE_UNUSED;
+        else
+                init.flags = 0;
+        init.parent_names = (parent_name ? &parent_name : NULL);
+        init.num_parents = (parent_name ? 1 : 0);
+        sclk->hw.init = &init;
+        sclk->id = id;
+        sclk->group1 = (id > 31);
+        sclk->clkbit = BIT(id & 0x1f);
+
+        pr_debug("register clock \"%s\" ID: %d group: %d bits: %08x\n",
+                 name, id, sclk->group1, sclk->clkbit);
+
+        clk = clk_register(dev, &sclk->hw);
+        if (IS_ERR(clk))
+                kfree(sclk);
+
+        return clk;
+}
+
+#ifdef CONFIG_DEBUG_FS
+
+static u32 src_pcksr0_boot;
+static u32 src_pcksr1_boot;
+
+static const char * const src_clk_names[] = {
+        "HCLKDMA0  ",
+        "HCLKSMC   ",
+        "HCLKSDRAM ",
+        "HCLKDMA1  ",
+        "HCLKCLCD  ",
+        "PCLKIRDA  ",
+        "PCLKSSP   ",
+        "PCLKUART0 ",
+        "PCLKSDI   ",
+        "PCLKI2C0  ",
+        "PCLKI2C1  ",
+        "PCLKUART1 ",
+        "PCLMSP0   ",
+        "HCLKUSB   ",
+        "HCLKDIF   ",
+        "HCLKSAA   ",
+        "HCLKSVA   ",
+        "PCLKHSI   ",
+        "PCLKXTI   ",
+        "PCLKUART2 ",
+        "PCLKMSP1  ",
+        "PCLKMSP2  ",
+        "PCLKOWM   ",
+        "HCLKHPI   ",
+        "PCLKSKE   ",
+        "PCLKHSEM  ",
+        "HCLK3D    ",
+        "HCLKHASH  ",
+        "HCLKCRYP  ",
+        "PCLKMSHC  ",
+        "HCLKUSBM  ",
+        "HCLKRNG   ",
+        "RESERVED  ",
+        "RESERVED  ",
+        "RESERVED  ",
+        "RESERVED  ",
+        "CLDCLK    ",
+        "IRDACLK   ",
+        "SSPICLK   ",
+        "UART0CLK  ",
+        "SDICLK    ",
+        "I2C0CLK   ",
+        "I2C1CLK   ",
+        "UART1CLK  ",
+        "MSPCLK0   ",
+        "USBCLK    ",
+        "DIFCLK    ",
+        "IPI2CCLK  ",
+        "IPBMCCLK  ",
+        "HSICLKRX  ",
+        "HSICLKTX  ",
+        "UART2CLK  ",
+        "MSPCLK1   ",
+        "MSPCLK2   ",
+        "OWMCLK    ",
+        "RESERVED  ",
+        "SKECLK    ",
+        "RESERVED  ",
+        "3DCLK     ",
+        "PCLKMSP3  ",
+        "MSPCLK3   ",
+        "MSHCCLK   ",
+        "USBMCLK   ",
+        "RNGCCLK   ",
+};
+
+static int nomadik_src_clk_show(struct seq_file *s, void *what)
+{
+        int i;
+        u32 src_pcksr0 = readl(src_base + SRC_PCKSR0);
+        u32 src_pcksr1 = readl(src_base + SRC_PCKSR1);
+        u32 src_pckensr0 = readl(src_base + SRC_PCKENSR0);
+        u32 src_pckensr1 = readl(src_base + SRC_PCKENSR1);
+
+        seq_printf(s, "Clock:      Boot:   Now:    Request: ASKED:\n");
+        for (i = 0; i < ARRAY_SIZE(src_clk_names); i++) {
+                u32 pcksrb = (i < 0x20) ? src_pcksr0_boot : src_pcksr1_boot;
+                u32 pcksr = (i < 0x20) ? src_pcksr0 : src_pcksr1;
+                u32 pckreq = (i < 0x20) ? src_pckensr0 : src_pckensr1;
+                u32 mask = BIT(i & 0x1f);
+
+                seq_printf(s, "%s  %s     %s     %s\n",
+                           src_clk_names[i],
+                           (pcksrb & mask) ? "on " : "off",
+                           (pcksr & mask) ? "on " : "off",
+                           (pckreq & mask) ? "on " : "off");
+        }
+        return 0;
+}
+
+static int nomadik_src_clk_open(struct inode *inode, struct file *file)
+{
+        return single_open(file, nomadik_src_clk_show, NULL);
+}
+
+static const struct file_operations nomadik_src_clk_debugfs_ops = {
+        .open           = nomadik_src_clk_open,
+        .read           = seq_read,
+        .llseek         = seq_lseek,
+        .release        = single_release,
+};
+
+static int __init nomadik_src_clk_init_debugfs(void)
+{
+        src_pcksr0_boot = readl(src_base + SRC_PCKSR0);
+        src_pcksr1_boot = readl(src_base + SRC_PCKSR1);
+        debugfs_create_file("nomadik-src-clk", S_IFREG | S_IRUGO,
+                            NULL, NULL, &nomadik_src_clk_debugfs_ops);
+        return 0;
+}
+
+module_init(nomadik_src_clk_init_debugfs);
+
+#endif
+
+static void __init of_nomadik_pll_setup(struct device_node *np)
+{
+        struct clk *clk = ERR_PTR(-EINVAL);
+        const char *clk_name = np->name;
+        const char *parent_name;
+        u32 pll_id;
+
+        if (of_property_read_u32(np, "pll-id", &pll_id)) {
+                pr_err("%s: PLL \"%s\" missing pll-id property\n",
+                        __func__, clk_name);
+                return;
+        }
+        parent_name = of_clk_get_parent_name(np, 0);
+        clk = pll_clk_register(NULL, clk_name, parent_name, pll_id);
+        if (!IS_ERR(clk))
+                of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static void __init of_nomadik_hclk_setup(struct device_node *np)
+{
+        struct clk *clk = ERR_PTR(-EINVAL);
+        const char *clk_name = np->name;
+        const char *parent_name;
+
+        parent_name = of_clk_get_parent_name(np, 0);
         /*
-         * At boot time, PLL2 is set to generate a set of fixed clocks,
-         * one of them is CLK48, the 48 MHz clock, routed to the UART, MMC/SD
-         * I2C, IrDA, USB and SSP blocks.
+         * The HCLK divides PLL1 with 1 (passthru), 2, 3 or 4.
          */
-        clk = clk_register_fixed_rate(NULL, "CLK48", NULL, CLK_IS_ROOT,
-                                      48000000);
-        clk_register_clkdev(clk, NULL, "uart0");
-        clk_register_clkdev(clk, NULL, "uart1");
-        clk_register_clkdev(clk, NULL, "mmci");
-        clk_register_clkdev(clk, NULL, "ssp");
-        clk_register_clkdev(clk, NULL, "nmk-i2c.0");
-        clk_register_clkdev(clk, NULL, "nmk-i2c.1");
+        clk = clk_register_divider(NULL, clk_name, parent_name,
+                           0, src_base + SRC_CR,
+                           13, 2,
+                           CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                           &src_lock);
+        if (!IS_ERR(clk))
+                of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static void __init of_nomadik_src_clk_setup(struct device_node *np)
+{
+        struct clk *clk = ERR_PTR(-EINVAL);
+        const char *clk_name = np->name;
+        const char *parent_name;
+        u32 clk_id;
+
+        if (of_property_read_u32(np, "clock-id", &clk_id)) {
+                pr_err("%s: SRC clock \"%s\" missing clock-id property\n",
+                        __func__, clk_name);
+                return;
+        }
+        parent_name = of_clk_get_parent_name(np, 0);
+        clk = src_clk_register(NULL, clk_name, parent_name, clk_id);
+        if (!IS_ERR(clk))
+                of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static const __initconst struct of_device_id nomadik_src_match[] = {
+        { .compatible = "stericsson,nomadik-src" },
+        { /* sentinel */ }
+};
+
+static const __initconst struct of_device_id nomadik_src_clk_match[] = {
+        {
+                .compatible = "fixed-clock",
+                .data = of_fixed_clk_setup,
+        },
+        {
+                .compatible = "fixed-factor-clock",
+                .data = of_fixed_factor_clk_setup,
+        },
+        {
+                .compatible = "st,nomadik-pll-clock",
+                .data = of_nomadik_pll_setup,
+        },
+        {
+                .compatible = "st,nomadik-hclk-clock",
+                .data = of_nomadik_hclk_setup,
+        },
+        {
+                .compatible = "st,nomadik-src-clock",
+                .data = of_nomadik_src_clk_setup,
+        },
+        { /* sentinel */ }
+};
+
+static int nomadik_clk_reboot_handler(struct notifier_block *this,
+                                unsigned long code,
+                                void *unused)
+{
+        u32 val;
+
+        /* The main chrystal need to be enabled for reboot to work */
+        val = readl(src_base + SRC_XTALCR);
+        val &= ~SRC_XTALCR_MXTALOVER;
+        val |= SRC_XTALCR_MXTALEN;
+        pr_crit("force-enabling MXTALO\n");
+        writel(val, src_base + SRC_XTALCR);
+        return NOTIFY_OK;
+}
+
+static struct notifier_block nomadik_clk_reboot_notifier = {
+        .notifier_call = nomadik_clk_reboot_handler,
+};
+
+void __init nomadik_clk_init(void)
+{
+        struct device_node *np;
+        u32 val;
+
+        np = of_find_matching_node(NULL, nomadik_src_match);
+        if (!np) {
+                pr_crit("no matching node for SRC, aborting clock init\n");
+                return;
+        }
+        src_base = of_iomap(np, 0);
+        if (!src_base) {
+                pr_err("%s: must have src parent node with REGS (%s)\n",
+                       __func__, np->name);
+                return;
+        }
+        val = readl(src_base + SRC_XTALCR);
+        pr_info("SXTALO is %s\n",
+                (val & SRC_XTALCR_SXTALDIS) ? "disabled" : "enabled");
+        pr_info("MXTAL is %s\n",
+                (val & SRC_XTALCR_MXTALSTAT) ? "enabled" : "disabled");
+        if (of_property_read_bool(np, "disable-sxtalo")) {
+                /* The machine uses an external oscillator circuit */
+                val |= SRC_XTALCR_SXTALDIS;
+                pr_info("disabling SXTALO\n");
+        }
+        if (of_property_read_bool(np, "disable-mxtalo")) {
+                /* Disable this too: also run by external oscillator */
+                val |= SRC_XTALCR_MXTALOVER;
+                val &= ~SRC_XTALCR_MXTALEN;
+                pr_info("disabling MXTALO\n");
+        }
+        writel(val, src_base + SRC_XTALCR);
+        register_reboot_notifier(&nomadik_clk_reboot_notifier);
+
+        of_clk_init(nomadik_src_clk_match);
 }
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 3c1f88868f29..addc738a06fb 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -151,7 +151,7 @@ enum exynos4_clks {
         sclk_audio1, sclk_audio2, sclk_spdif, sclk_spi0, sclk_spi1, sclk_spi2,
         sclk_slimbus, sclk_fimd1, sclk_mipi1, sclk_pcm1, sclk_pcm2, sclk_i2s1,
         sclk_i2s2, sclk_mipihsi, sclk_mfc, sclk_pcm0, sclk_g3d, sclk_pwm_isp,
-        sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp,
+        sclk_spi0_isp, sclk_spi1_isp, sclk_uart_isp, sclk_fimg2d,
 
         /* gate clocks */
         fimc0 = 256, fimc1, fimc2, fimc3, csis0, csis1, jpeg, smmu_fimc0,
@@ -484,6 +484,9 @@ struct samsung_mux_clock exynos4x12_mux_clks[] __initdata = {
         MUX(none, "mout_spi0_isp", group1_p4x12, E4X12_SRC_ISP, 4, 4),
         MUX(none, "mout_spi1_isp", group1_p4x12, E4X12_SRC_ISP, 8, 4),
         MUX(none, "mout_uart_isp", group1_p4x12, E4X12_SRC_ISP, 12, 4),
+        MUX(none, "mout_g2d0", sclk_ampll_p4210, SRC_DMC, 20, 1),
+        MUX(none, "mout_g2d1", sclk_evpll_p, SRC_DMC, 24, 1),
+        MUX(none, "mout_g2d", mout_g2d_p, SRC_DMC, 28, 1),
 };
 
 /* list of divider clocks supported in all exynos4 soc's */
@@ -552,7 +555,7 @@ struct samsung_div_clock exynos4_div_clks[] __initdata = {
 /* list of divider clocks supported in exynos4210 soc */
 struct samsung_div_clock exynos4210_div_clks[] __initdata = {
         DIV(aclk200, "aclk200", "mout_aclk200", DIV_TOP, 0, 3),
-        DIV(none, "div_g2d", "mout_g2d", DIV_IMAGE, 0, 4),
+        DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_IMAGE, 0, 4),
         DIV(none, "div_fimd1", "mout_fimd1", E4210_DIV_LCD1, 0, 4),
         DIV(none, "div_mipi1", "mout_mipi1", E4210_DIV_LCD1, 16, 4),
         DIV(none, "div_sata", "mout_sata", DIV_FSYS0, 20, 4),
@@ -582,6 +585,7 @@ struct samsung_div_clock exynos4x12_div_clks[] __initdata = {
         DIV(none, "div_mpwm", "div_isp1", E4X12_DIV_ISP1, 0, 3),
         DIV(div_mcuisp0, "div_mcuisp0", "aclk400_mcuisp", E4X12_DIV_ISP1, 4, 3),
         DIV(div_mcuisp1, "div_mcuisp1", "div_mcuisp0", E4X12_DIV_ISP1, 8, 3),
+        DIV(sclk_fimg2d, "sclk_fimg2d", "mout_g2d", DIV_DMC1, 0, 4),
 };
 
 /* list of gate clocks supported in all exynos4 soc's */
@@ -909,6 +913,7 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
                         CLK_IGNORE_UNUSED, 0),
         GATE(spi1_isp, "spi1_isp", "aclk200", E4X12_GATE_ISP1, 13,
                         CLK_IGNORE_UNUSED, 0),
+        GATE(g2d, "g2d", "aclk200", GATE_IP_DMC, 23, 0, 0),
 };
 
 /*
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index e405531e1cc5..b9415b622f55 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -13,6 +13,9 @@
 #include <linux/io.h>
 #include <linux/clockchips.h>
 #include <linux/clocksource.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
 #include <linux/clk.h>
 #include <linux/jiffies.h>
 #include <linux/delay.h>
@@ -188,22 +191,15 @@ static struct irqaction nmdk_timer_irq = {
         .dev_id         = &nmdk_clkevt,
 };
 
-void __init nmdk_timer_init(void __iomem *base, int irq)
+static void __init __nmdk_timer_init(void __iomem *base, int irq,
+                                     struct clk *pclk, struct clk *clk)
 {
         unsigned long rate;
-        struct clk *clk0, *pclk0;
 
         mtu_base = base;
 
-        pclk0 = clk_get_sys("mtu0", "apb_pclk");
-        BUG_ON(IS_ERR(pclk0));
-        BUG_ON(clk_prepare(pclk0) < 0);
-        BUG_ON(clk_enable(pclk0) < 0);
-
-        clk0 = clk_get_sys("mtu0", NULL);
-        BUG_ON(IS_ERR(clk0));
-        BUG_ON(clk_prepare(clk0) < 0);
-        BUG_ON(clk_enable(clk0) < 0);
+        BUG_ON(clk_prepare_enable(pclk));
+        BUG_ON(clk_prepare_enable(clk));
 
         /*
          * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
@@ -213,7 +209,7 @@ void __init nmdk_timer_init(void __iomem *base, int irq)
          * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
          * with 16 gives too low timer resolution.
          */
-        rate = clk_get_rate(clk0);
+        rate = clk_get_rate(clk);
         if (rate > 32000000) {
                 rate /= 16;
                 clk_prescale = MTU_CRn_PRESCALE_16;
@@ -247,3 +243,43 @@ void __init nmdk_timer_init(void __iomem *base, int irq)
         mtu_delay_timer.freq = rate;
         register_current_timer_delay(&mtu_delay_timer);
 }
+
+void __init nmdk_timer_init(void __iomem *base, int irq)
+{
+        struct clk *clk0, *pclk0;
+
+        pclk0 = clk_get_sys("mtu0", "apb_pclk");
+        BUG_ON(IS_ERR(pclk0));
+        clk0 = clk_get_sys("mtu0", NULL);
+        BUG_ON(IS_ERR(clk0));
+
+        __nmdk_timer_init(base, irq, pclk0, clk0);
+}
+
+static void __init nmdk_timer_of_init(struct device_node *node)
+{
+        struct clk *pclk;
+        struct clk *clk;
+        void __iomem *base;
+        int irq;
+
+        base = of_iomap(node, 0);
+        if (!base)
+                panic("Can't remap registers");
+
+        pclk = of_clk_get_by_name(node, "apb_pclk");
+        if (IS_ERR(pclk))
+                panic("could not get apb_pclk");
+
+        clk = of_clk_get_by_name(node, "timclk");
+        if (IS_ERR(clk))
+                panic("could not get timclk");
+
+        irq = irq_of_parse_and_map(node, 0);
+        if (irq <= 0)
+                panic("Can't parse IRQ");
+
+        __nmdk_timer_init(base, irq, pclk, clk);
+}
+CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
+                       nmdk_timer_of_init);
diff --git a/drivers/crypto/ux500/cryp/cryp_core.c b/drivers/crypto/ux500/cryp/cryp_core.c
index 32f480622b97..8c2777cf02f6 100644
--- a/drivers/crypto/ux500/cryp/cryp_core.c
+++ b/drivers/crypto/ux500/cryp/cryp_core.c
@@ -1743,6 +1743,11 @@ static int ux500_cryp_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(ux500_cryp_pm, ux500_cryp_suspend, ux500_cryp_resume);
 
+static const struct of_device_id ux500_cryp_match[] = {
+        { .compatible = "stericsson,ux500-cryp" },
+        { },
+};
+
 static struct platform_driver cryp_driver = {
         .probe  = ux500_cryp_probe,
         .remove = ux500_cryp_remove,
@@ -1750,6 +1755,7 @@ static struct platform_driver cryp_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name  = "cryp1",
+                .of_match_table = ux500_cryp_match,
                 .pm    = &ux500_cryp_pm,
         }
 };
diff --git a/drivers/crypto/ux500/hash/hash_core.c b/drivers/crypto/ux500/hash/hash_core.c
index cf5508967539..3b8f661d0edf 100644
--- a/drivers/crypto/ux500/hash/hash_core.c
+++ b/drivers/crypto/ux500/hash/hash_core.c
@@ -1961,6 +1961,11 @@ static int ux500_hash_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(ux500_hash_pm, ux500_hash_suspend, ux500_hash_resume);
 
+static const struct of_device_id ux500_hash_match[] = {
+        { .compatible = "stericsson,ux500-hash" },
+        { },
+};
+
 static struct platform_driver hash_driver = {
         .probe  = ux500_hash_probe,
         .remove = ux500_hash_remove,
@@ -1968,6 +1973,7 @@ static struct platform_driver hash_driver = {
         .driver = {
                 .owner = THIS_MODULE,
                 .name  = "hash1",
+                .of_match_table = ux500_hash_match,
                 .pm    = &ux500_hash_pm,
         }
 };
diff --git a/drivers/irqchip/irq-renesas-intc-irqpin.c b/drivers/irqchip/irq-renesas-intc-irqpin.c
index 5a68e5accec1..82cec63a9011 100644
--- a/drivers/irqchip/irq-renesas-intc-irqpin.c
+++ b/drivers/irqchip/irq-renesas-intc-irqpin.c
@@ -18,6 +18,7 @@
  */
 
 #include <linux/init.h>
+#include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/interrupt.h>
@@ -347,8 +348,14 @@ static int intc_irqpin_probe(struct platform_device *pdev)
         }
 
         /* deal with driver instance configuration */
-        if (pdata)
+        if (pdata) {
                 memcpy(&p->config, pdata, sizeof(*pdata));
+        } else {
+                of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width",
+                                     &p->config.sense_bitfield_width);
+                p->config.control_parent = of_property_read_bool(pdev->dev.of_node,
+                                                                 "control-parent");
+        }
         if (!p->config.sense_bitfield_width)
                 p->config.sense_bitfield_width = 4; /* default to 4 bits */
 
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 34281754b629..8a4f9c5c0b8e 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -2104,15 +2104,15 @@ static struct pinctrl_desc nmk_pinctrl_desc = {
 
 static const struct of_device_id nmk_pinctrl_match[] = {
         {
-                .compatible = "stericsson,nmk-pinctrl-stn8815",
+                .compatible = "stericsson,stn8815-pinctrl",
                 .data = (void *)PINCTRL_NMK_STN8815,
         },
         {
-                .compatible = "stericsson,nmk-pinctrl",
+                .compatible = "stericsson,db8500-pinctrl",
                 .data = (void *)PINCTRL_NMK_DB8500,
         },
         {
-                .compatible = "stericsson,nmk-pinctrl-db8540",
+                .compatible = "stericsson,db8540-pinctrl",
                 .data = (void *)PINCTRL_NMK_DB8540,
         },
         {},
diff --git a/drivers/regulator/ab8500.c b/drivers/regulator/ab8500.c
index f6656b8c28b6..a19045ee0ec4 100644
--- a/drivers/regulator/ab8500.c
+++ b/drivers/regulator/ab8500.c
@@ -2901,7 +2901,7 @@ static struct of_regulator_match ab8500_regulator_match[] = {
         { .name = "ab8500_ldo_tvout",   .driver_data = (void *) AB8500_LDO_TVOUT, },
         { .name = "ab8500_ldo_audio",   .driver_data = (void *) AB8500_LDO_AUDIO, },
         { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8500_LDO_ANAMIC1, },
-        { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
+        { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8500_LDO_ANAMIC2, },
         { .name = "ab8500_ldo_dmic",    .driver_data = (void *) AB8500_LDO_DMIC, },
         { .name = "ab8500_ldo_ana",     .driver_data = (void *) AB8500_LDO_ANA, },
 };
@@ -2917,7 +2917,7 @@ static struct of_regulator_match ab8505_regulator_match[] = {
         { .name = "ab8500_ldo_adc",     .driver_data = (void *) AB8505_LDO_ADC, },
         { .name = "ab8500_ldo_audio",   .driver_data = (void *) AB8505_LDO_AUDIO, },
         { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8505_LDO_ANAMIC1, },
-        { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
+        { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8505_LDO_ANAMIC2, },
         { .name = "ab8500_ldo_aux8",    .driver_data = (void *) AB8505_LDO_AUX8, },
         { .name = "ab8500_ldo_ana",     .driver_data = (void *) AB8505_LDO_ANA, },
 };
@@ -2933,7 +2933,7 @@ static struct of_regulator_match ab8540_regulator_match[] = {
         { .name = "ab8500_ldo_tvout",   .driver_data = (void *) AB8540_LDO_TVOUT, },
         { .name = "ab8500_ldo_audio",   .driver_data = (void *) AB8540_LDO_AUDIO, },
         { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB8540_LDO_ANAMIC1, },
-        { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
+        { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB8540_LDO_ANAMIC2, },
         { .name = "ab8500_ldo_dmic",    .driver_data = (void *) AB8540_LDO_DMIC, },
         { .name = "ab8500_ldo_ana",     .driver_data = (void *) AB8540_LDO_ANA, },
         { .name = "ab8500_ldo_sdio",    .driver_data = (void *) AB8540_LDO_SDIO, },
@@ -2948,7 +2948,7 @@ static struct of_regulator_match ab9540_regulator_match[] = {
         { .name = "ab8500_ldo_tvout",   .driver_data = (void *) AB9540_LDO_TVOUT, },
         { .name = "ab8500_ldo_audio",   .driver_data = (void *) AB9540_LDO_AUDIO, },
         { .name = "ab8500_ldo_anamic1", .driver_data = (void *) AB9540_LDO_ANAMIC1, },
-        { .name = "ab8500_ldo_amamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
+        { .name = "ab8500_ldo_anamic2", .driver_data = (void *) AB9540_LDO_ANAMIC2, },
         { .name = "ab8500_ldo_dmic",    .driver_data = (void *) AB9540_LDO_DMIC, },
         { .name = "ab8500_ldo_ana",     .driver_data = (void *) AB9540_LDO_ANA, },
 };