139 files changed, 6895 insertions, 2240 deletions

diff --git a/drivers/isdn/gigaset/bas-gigaset.c b/drivers/isdn/gigaset/bas-gigaset.c
index b7ae0a0dd5b6..aecec6d32463 100644
--- a/drivers/isdn/gigaset/bas-gigaset.c
+++ b/drivers/isdn/gigaset/bas-gigaset.c
@@ -2365,7 +2365,7 @@ static int gigaset_probe(struct usb_interface *interface,
         endpoint = &hostif->endpoint[0].desc;
         usb_fill_int_urb(ucs->urb_int_in, udev,
                          usb_rcvintpipe(udev,
-                                        (endpoint->bEndpointAddress) & 0x0f),
+                                        usb_endpoint_num(endpoint)),
                          ucs->int_in_buf, IP_MSGSIZE, read_int_callback, cs,
                          endpoint->bInterval);
         rc = usb_submit_urb(ucs->urb_int_in, GFP_KERNEL);
diff --git a/drivers/isdn/gigaset/usb-gigaset.c b/drivers/isdn/gigaset/usb-gigaset.c
index d0a41cb0cf62..00d40773b07f 100644
--- a/drivers/isdn/gigaset/usb-gigaset.c
+++ b/drivers/isdn/gigaset/usb-gigaset.c
@@ -751,7 +751,7 @@ static int gigaset_probe(struct usb_interface *interface,
         /* Fill the interrupt urb and send it to the core */
         usb_fill_int_urb(ucs->read_urb, udev,
                          usb_rcvintpipe(udev,
-                                        endpoint->bEndpointAddress & 0x0f),
+                                        usb_endpoint_num(endpoint)),
                          ucs->rcvbuf, buffer_size,
                          gigaset_read_int_callback,
                          cs, endpoint->bInterval);
diff --git a/drivers/isdn/mISDN/dsp_cmx.c b/drivers/isdn/mISDN/dsp_cmx.c
index a4f05c54c32b..87f7dff20ff6 100644
--- a/drivers/isdn/mISDN/dsp_cmx.c
+++ b/drivers/isdn/mISDN/dsp_cmx.c
@@ -1454,66 +1454,63 @@ dsp_cmx_send_member(struct dsp *dsp, int len, s32 *c, int members)
 #ifdef CMX_CONF_DEBUG
         if (0) {
 #else
-                if (members == 2) {
+        if (members == 2) {
 #endif
-                        /* "other" becomes other party */
-                        other = (list_entry(conf->mlist.next,
-                                            struct dsp_conf_member, list))->dsp;
-                        if (other == member)
-                                other = (list_entry(conf->mlist.prev,
-                                                    struct dsp_conf_member, list))->dsp;
-                        o_q = other->rx_buff; /* received data */
-                        o_rr = (other->rx_R + len) & CMX_BUFF_MASK;
-                        /* end of rx-pointer */
-                        o_r = (o_rr - rr + r) & CMX_BUFF_MASK;
-                        /* start rx-pointer at current read position*/
-                        /* -> if echo is NOT enabled */
-                        if (!dsp->echo.software) {
-                                /*
-                                 * -> copy other member's rx-data,
-                                 * if tx-data is available, mix
-                                 */
-                                while (o_r != o_rr && t != tt) {
-                                        *d++ = dsp_audio_mix_law[(p[t] << 8) | o_q[o_r]];
-                                        t = (t + 1) & CMX_BUFF_MASK;
-                                        o_r = (o_r + 1) & CMX_BUFF_MASK;
-                                }
-                                while (o_r != o_rr) {
-                                        *d++ = o_q[o_r];
-                                        o_r = (o_r + 1) & CMX_BUFF_MASK;
-                                }
-                                /* -> if echo is enabled */
-                        } else {
-                                /*
-                                 * -> mix other member's rx-data with echo,
-                                 * if tx-data is available, mix
-                                 */
-                                while (r != rr && t != tt) {
-                                        sample = dsp_audio_law_to_s32[p[t]] +
-                                                dsp_audio_law_to_s32[q[r]] +
-                                                dsp_audio_law_to_s32[o_q[o_r]];
-                                        if (sample < -32768)
-                                                sample = -32768;
-                                        else if (sample > 32767)
-                                                sample = 32767;
-                                        *d++ = dsp_audio_s16_to_law[sample & 0xffff];
-                                        /* tx-data + rx_data + echo */
-                                        t = (t + 1) & CMX_BUFF_MASK;
-                                        r = (r + 1) & CMX_BUFF_MASK;
-                                        o_r = (o_r + 1) & CMX_BUFF_MASK;
-                                }
-                                while (r != rr) {
-                                        *d++ = dsp_audio_mix_law[(q[r] << 8) | o_q[o_r]];
-                                        r = (r + 1) & CMX_BUFF_MASK;
-                                        o_r = (o_r + 1) & CMX_BUFF_MASK;
-                                }
+                /* "other" becomes other party */
+                other = (list_entry(conf->mlist.next,
+                                    struct dsp_conf_member, list))->dsp;
+                if (other == member)
+                        other = (list_entry(conf->mlist.prev,
+                                    struct dsp_conf_member, list))->dsp;
+                o_q = other->rx_buff; /* received data */
+                o_rr = (other->rx_R + len) & CMX_BUFF_MASK;
+                /* end of rx-pointer */
+                o_r = (o_rr - rr + r) & CMX_BUFF_MASK;
+                /* start rx-pointer at current read position*/
+                /* -> if echo is NOT enabled */
+                if (!dsp->echo.software) {
+                        /*
+                         * -> copy other member's rx-data,
+                         * if tx-data is available, mix
+                         */
+                        while (o_r != o_rr && t != tt) {
+                                *d++ = dsp_audio_mix_law[(p[t] << 8) | o_q[o_r]];
+                                t = (t + 1) & CMX_BUFF_MASK;
+                                o_r = (o_r + 1) & CMX_BUFF_MASK;
+                        }
+                        while (o_r != o_rr) {
+                                *d++ = o_q[o_r];
+                                o_r = (o_r + 1) & CMX_BUFF_MASK;
+                        }
+                        /* -> if echo is enabled */
+                } else {
+                        /*
+                         * -> mix other member's rx-data with echo,
+                         * if tx-data is available, mix
+                         */
+                        while (r != rr && t != tt) {
+                                sample = dsp_audio_law_to_s32[p[t]] +
+                                        dsp_audio_law_to_s32[q[r]] +
+                                        dsp_audio_law_to_s32[o_q[o_r]];
+                                if (sample < -32768)
+                                        sample = -32768;
+                                else if (sample > 32767)
+                                        sample = 32767;
+                                *d++ = dsp_audio_s16_to_law[sample & 0xffff];
+                                /* tx-data + rx_data + echo */
+                                t = (t + 1) & CMX_BUFF_MASK;
+                                r = (r + 1) & CMX_BUFF_MASK;
+                                o_r = (o_r + 1) & CMX_BUFF_MASK;
+                        }
+                        while (r != rr) {
+                                *d++ = dsp_audio_mix_law[(q[r] << 8) | o_q[o_r]];
+                                r = (r + 1) & CMX_BUFF_MASK;
+                                o_r = (o_r + 1) & CMX_BUFF_MASK;
                         }
-                        dsp->tx_R = t;
-                        goto send_packet;
                 }
-#ifdef DSP_NEVER_DEFINED
+                dsp->tx_R = t;
+                goto send_packet;
         }
-#endif
         /* PROCESS DATA (three or more members) */
         /* -> if echo is NOT enabled */
         if (!dsp->echo.software) {
diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c
index 95dd1f58c260..73c21e233131 100644
--- a/drivers/net/bonding/bond_alb.c
+++ b/drivers/net/bonding/bond_alb.c
@@ -1388,7 +1388,7 @@ static int bond_do_alb_xmit(struct sk_buff *skb, struct bonding *bond,
         }
 
         if (tx_slave && bond_slave_can_tx(tx_slave)) {
-                if (tx_slave != rcu_dereference(bond->curr_active_slave)) {
+                if (tx_slave != rcu_access_pointer(bond->curr_active_slave)) {
                         ether_addr_copy(eth_data->h_source,
                                         tx_slave->dev->dev_addr);
                 }
diff --git a/drivers/net/bonding/bond_netlink.c b/drivers/net/bonding/bond_netlink.c
index d163e112f04c..e1489d9df2a4 100644
--- a/drivers/net/bonding/bond_netlink.c
+++ b/drivers/net/bonding/bond_netlink.c
@@ -96,6 +96,10 @@ static const struct nla_policy bond_policy[IFLA_BOND_MAX + 1] = {
         [IFLA_BOND_AD_INFO]             = { .type = NLA_NESTED },
 };
 
+static const struct nla_policy bond_slave_policy[IFLA_BOND_SLAVE_MAX + 1] = {
+        [IFLA_BOND_SLAVE_QUEUE_ID]      = { .type = NLA_U16 },
+};
+
 static int bond_validate(struct nlattr *tb[], struct nlattr *data[])
 {
         if (tb[IFLA_ADDRESS]) {
@@ -107,6 +111,33 @@ static int bond_validate(struct nlattr *tb[], struct nlattr *data[])
         return 0;
 }
 
+static int bond_slave_changelink(struct net_device *bond_dev,
+                                 struct net_device *slave_dev,
+                                 struct nlattr *tb[], struct nlattr *data[])
+{
+        struct bonding *bond = netdev_priv(bond_dev);
+        struct bond_opt_value newval;
+        int err;
+
+        if (!data)
+                return 0;
+
+        if (data[IFLA_BOND_SLAVE_QUEUE_ID]) {
+                u16 queue_id = nla_get_u16(data[IFLA_BOND_SLAVE_QUEUE_ID]);
+                char queue_id_str[IFNAMSIZ + 7];
+
+                /* queue_id option setting expects slave_name:queue_id */
+                snprintf(queue_id_str, sizeof(queue_id_str), "%s:%u\n",
+                         slave_dev->name, queue_id);
+                bond_opt_initstr(&newval, queue_id_str);
+                err = __bond_opt_set(bond, BOND_OPT_QUEUE_ID, &newval);
+                if (err)
+                        return err;
+        }
+
+        return 0;
+}
+
 static int bond_changelink(struct net_device *bond_dev,
                            struct nlattr *tb[], struct nlattr *data[])
 {
@@ -562,6 +593,9 @@ struct rtnl_link_ops bond_link_ops __read_mostly = {
         .get_num_tx_queues      = bond_get_num_tx_queues,
         .get_num_rx_queues      = bond_get_num_tx_queues, /* Use the same number
                                                              as for TX queues */
+        .slave_maxtype          = IFLA_BOND_SLAVE_MAX,
+        .slave_policy           = bond_slave_policy,
+        .slave_changelink       = bond_slave_changelink,
         .get_slave_size         = bond_get_slave_size,
         .fill_slave_info        = bond_fill_slave_info,
 };
diff --git a/drivers/net/bonding/bond_options.c b/drivers/net/bonding/bond_options.c
index dc73463c2c23..d8dc17faa6b4 100644
--- a/drivers/net/bonding/bond_options.c
+++ b/drivers/net/bonding/bond_options.c
@@ -625,6 +625,8 @@ int __bond_opt_set(struct bonding *bond,
 out:
         if (ret)
                 bond_opt_error_interpret(bond, opt, ret, val);
+        else
+                call_netdevice_notifiers(NETDEV_CHANGEINFODATA, bond->dev);
 
         return ret;
 }
diff --git a/drivers/net/can/Kconfig b/drivers/net/can/Kconfig
index 41688229c570..e78d6b32431d 100644
--- a/drivers/net/can/Kconfig
+++ b/drivers/net/can/Kconfig
@@ -143,6 +143,8 @@ source "drivers/net/can/sja1000/Kconfig"
 
 source "drivers/net/can/c_can/Kconfig"
 
+source "drivers/net/can/m_can/Kconfig"
+
 source "drivers/net/can/cc770/Kconfig"
 
 source "drivers/net/can/spi/Kconfig"
diff --git a/drivers/net/can/Makefile b/drivers/net/can/Makefile
index 1697f22353a9..fc9304143f44 100644
--- a/drivers/net/can/Makefile
+++ b/drivers/net/can/Makefile
@@ -17,6 +17,7 @@ obj-y				+= softing/
 obj-$(CONFIG_CAN_SJA1000)       += sja1000/
 obj-$(CONFIG_CAN_MSCAN)         += mscan/
 obj-$(CONFIG_CAN_C_CAN)         += c_can/
+obj-$(CONFIG_CAN_M_CAN)         += m_can/
 obj-$(CONFIG_CAN_CC770)         += cc770/
 obj-$(CONFIG_CAN_AT91)          += at91_can.o
 obj-$(CONFIG_CAN_TI_HECC)       += ti_hecc.o
@@ -28,4 +29,4 @@ obj-$(CONFIG_CAN_GRCAN)		+= grcan.o
 obj-$(CONFIG_CAN_RCAR)          += rcar_can.o
 obj-$(CONFIG_CAN_XILINXCAN)     += xilinx_can.o
 
-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
+subdir-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/c_can/Makefile b/drivers/net/can/c_can/Makefile
index ad1cc842170a..9fdc678b5b37 100644
--- a/drivers/net/can/c_can/Makefile
+++ b/drivers/net/can/c_can/Makefile
@@ -5,5 +5,3 @@
 obj-$(CONFIG_CAN_C_CAN) += c_can.o
 obj-$(CONFIG_CAN_C_CAN_PLATFORM) += c_can_platform.o
 obj-$(CONFIG_CAN_C_CAN_PCI) += c_can_pci.o
-
-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/cc770/Makefile b/drivers/net/can/cc770/Makefile
index 9fb8321b33eb..8657f879ae19 100644
--- a/drivers/net/can/cc770/Makefile
+++ b/drivers/net/can/cc770/Makefile
@@ -5,5 +5,3 @@
 obj-$(CONFIG_CAN_CC770) += cc770.o
 obj-$(CONFIG_CAN_CC770_ISA) += cc770_isa.o
 obj-$(CONFIG_CAN_CC770_PLATFORM) += cc770_platform.o
-
-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/dev.c b/drivers/net/can/dev.c
index 9f91fcba43f8..02492d241e4c 100644
--- a/drivers/net/can/dev.c
+++ b/drivers/net/can/dev.c
@@ -103,11 +103,11 @@ static int can_calc_bittiming(struct net_device *dev, struct can_bittiming *bt,
                               const struct can_bittiming_const *btc)
 {
         struct can_priv *priv = netdev_priv(dev);
-        long rate, best_rate = 0;
         long best_error = 1000000000, error = 0;
         int best_tseg = 0, best_brp = 0, brp = 0;
         int tsegall, tseg = 0, tseg1 = 0, tseg2 = 0;
         int spt_error = 1000, spt = 0, sampl_pt;
+        long rate;
         u64 v64;
 
         /* Use CIA recommended sample points */
@@ -152,7 +152,6 @@ static int can_calc_bittiming(struct net_device *dev, struct can_bittiming *bt,
                 }
                 best_tseg = tseg / 2;
                 best_brp = brp;
-                best_rate = rate;
                 if (error == 0)
                         break;
         }
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c
index 944aa5d3af6e..2700865efcad 100644
--- a/drivers/net/can/flexcan.c
+++ b/drivers/net/can/flexcan.c
@@ -92,6 +92,27 @@
 #define FLEXCAN_CTRL_ERR_ALL \
         (FLEXCAN_CTRL_ERR_BUS | FLEXCAN_CTRL_ERR_STATE)
 
+/* FLEXCAN control register 2 (CTRL2) bits */
+#define FLEXCAN_CRL2_ECRWRE             BIT(29)
+#define FLEXCAN_CRL2_WRMFRZ             BIT(28)
+#define FLEXCAN_CRL2_RFFN(x)            (((x) & 0x0f) << 24)
+#define FLEXCAN_CRL2_TASD(x)            (((x) & 0x1f) << 19)
+#define FLEXCAN_CRL2_MRP                BIT(18)
+#define FLEXCAN_CRL2_RRS                BIT(17)
+#define FLEXCAN_CRL2_EACEN              BIT(16)
+
+/* FLEXCAN memory error control register (MECR) bits */
+#define FLEXCAN_MECR_ECRWRDIS           BIT(31)
+#define FLEXCAN_MECR_HANCEI_MSK         BIT(19)
+#define FLEXCAN_MECR_FANCEI_MSK         BIT(18)
+#define FLEXCAN_MECR_CEI_MSK            BIT(16)
+#define FLEXCAN_MECR_HAERRIE            BIT(15)
+#define FLEXCAN_MECR_FAERRIE            BIT(14)
+#define FLEXCAN_MECR_EXTERRIE           BIT(13)
+#define FLEXCAN_MECR_RERRDIS            BIT(9)
+#define FLEXCAN_MECR_ECCDIS             BIT(8)
+#define FLEXCAN_MECR_NCEFAFRZ           BIT(7)
+
 /* FLEXCAN error and status register (ESR) bits */
 #define FLEXCAN_ESR_TWRN_INT            BIT(17)
 #define FLEXCAN_ESR_RWRN_INT            BIT(16)
@@ -150,18 +171,20 @@
  * FLEXCAN hardware feature flags
  *
  * Below is some version info we got:
- *    SOC   Version   IP-Version  Glitch-  [TR]WRN_INT
- *                                Filter?   connected?
- *   MX25  FlexCAN2  03.00.00.00     no         no
- *   MX28  FlexCAN2  03.00.04.00    yes        yes
- *   MX35  FlexCAN2  03.00.00.00     no         no
- *   MX53  FlexCAN2  03.00.00.00    yes         no
- *   MX6s  FlexCAN3  10.00.12.00    yes        yes
+ *    SOC   Version   IP-Version  Glitch-  [TR]WRN_INT  Memory err
+ *                                Filter?   connected?  detection
+ *   MX25  FlexCAN2  03.00.00.00     no         no         no
+ *   MX28  FlexCAN2  03.00.04.00    yes        yes         no
+ *   MX35  FlexCAN2  03.00.00.00     no         no         no
+ *   MX53  FlexCAN2  03.00.00.00    yes         no         no
+ *   MX6s  FlexCAN3  10.00.12.00    yes        yes         no
+ *   VF610 FlexCAN3  ?               no        yes        yes
  *
  * Some SOCs do not have the RX_WARN & TX_WARN interrupt line connected.
  */
 #define FLEXCAN_HAS_V10_FEATURES        BIT(1) /* For core version >= 10 */
 #define FLEXCAN_HAS_BROKEN_ERR_STATE    BIT(2) /* [TR]WRN_INT not connected */
+#define FLEXCAN_HAS_MECR_FEATURES       BIT(3) /* Memory error detection */
 
 /* Structure of the message buffer */
 struct flexcan_mb {
@@ -192,8 +215,17 @@ struct flexcan_regs {
         u32 crcr;               /* 0x44 */
         u32 rxfgmask;           /* 0x48 */
         u32 rxfir;              /* 0x4c */
-        u32 _reserved3[12];
-        struct flexcan_mb cantxfg[64];
+        u32 _reserved3[12];     /* 0x50 */
+        struct flexcan_mb cantxfg[64];  /* 0x80 */
+        u32 _reserved4[408];
+        u32 mecr;               /* 0xae0 */
+        u32 erriar;             /* 0xae4 */
+        u32 erridpr;            /* 0xae8 */
+        u32 errippr;            /* 0xaec */
+        u32 rerrar;             /* 0xaf0 */
+        u32 rerrdr;             /* 0xaf4 */
+        u32 rerrsynr;           /* 0xaf8 */
+        u32 errsr;              /* 0xafc */
 };
 
 struct flexcan_devtype_data {
@@ -223,6 +255,9 @@ static struct flexcan_devtype_data fsl_imx28_devtype_data;
 static struct flexcan_devtype_data fsl_imx6q_devtype_data = {
         .features = FLEXCAN_HAS_V10_FEATURES,
 };
+static struct flexcan_devtype_data fsl_vf610_devtype_data = {
+        .features = FLEXCAN_HAS_V10_FEATURES | FLEXCAN_HAS_MECR_FEATURES,
+};
 
 static const struct can_bittiming_const flexcan_bittiming_const = {
         .name = DRV_NAME,
@@ -378,8 +413,9 @@ static int flexcan_chip_softreset(struct flexcan_priv *priv)
         return 0;
 }
 
-static int flexcan_get_berr_counter(const struct net_device *dev,
-                                    struct can_berr_counter *bec)
+
+static int __flexcan_get_berr_counter(const struct net_device *dev,
+                                      struct can_berr_counter *bec)
 {
         const struct flexcan_priv *priv = netdev_priv(dev);
         struct flexcan_regs __iomem *regs = priv->base;
@@ -391,6 +427,29 @@ static int flexcan_get_berr_counter(const struct net_device *dev,
         return 0;
 }
 
+static int flexcan_get_berr_counter(const struct net_device *dev,
+                                    struct can_berr_counter *bec)
+{
+        const struct flexcan_priv *priv = netdev_priv(dev);
+        int err;
+
+        err = clk_prepare_enable(priv->clk_ipg);
+        if (err)
+                return err;
+
+        err = clk_prepare_enable(priv->clk_per);
+        if (err)
+                goto out_disable_ipg;
+
+        err = __flexcan_get_berr_counter(dev, bec);
+
+        clk_disable_unprepare(priv->clk_per);
+ out_disable_ipg:
+        clk_disable_unprepare(priv->clk_ipg);
+
+        return err;
+}
+
 static int flexcan_start_xmit(struct sk_buff *skb, struct net_device *dev)
 {
         const struct flexcan_priv *priv = netdev_priv(dev);
@@ -503,7 +562,7 @@ static void do_state(struct net_device *dev,
         struct flexcan_priv *priv = netdev_priv(dev);
         struct can_berr_counter bec;
 
-        flexcan_get_berr_counter(dev, &bec);
+        __flexcan_get_berr_counter(dev, &bec);
 
         switch (priv->can.state) {
         case CAN_STATE_ERROR_ACTIVE:
@@ -800,7 +859,7 @@ static int flexcan_chip_start(struct net_device *dev)
         struct flexcan_priv *priv = netdev_priv(dev);
         struct flexcan_regs __iomem *regs = priv->base;
         int err;
-        u32 reg_mcr, reg_ctrl;
+        u32 reg_mcr, reg_ctrl, reg_crl2, reg_mecr;
 
         /* enable module */
         err = flexcan_chip_enable(priv);
@@ -879,6 +938,31 @@ static int flexcan_chip_start(struct net_device *dev)
         if (priv->devtype_data->features & FLEXCAN_HAS_V10_FEATURES)
                 flexcan_write(0x0, &regs->rxfgmask);
 
+        /*
+         * On Vybrid, disable memory error detection interrupts
+         * and freeze mode.
+         * This also works around errata e5295 which generates
+         * false positive memory errors and put the device in
+         * freeze mode.
+         */
+        if (priv->devtype_data->features & FLEXCAN_HAS_MECR_FEATURES) {
+                /*
+                 * Follow the protocol as described in "Detection
+                 * and Correction of Memory Errors" to write to
+                 * MECR register
+                 */
+                reg_crl2 = flexcan_read(&regs->crl2);
+                reg_crl2 |= FLEXCAN_CRL2_ECRWRE;
+                flexcan_write(reg_crl2, &regs->crl2);
+
+                reg_mecr = flexcan_read(&regs->mecr);
+                reg_mecr &= ~FLEXCAN_MECR_ECRWRDIS;
+                flexcan_write(reg_mecr, &regs->mecr);
+                reg_mecr &= ~(FLEXCAN_MECR_NCEFAFRZ | FLEXCAN_MECR_HANCEI_MSK |
+                                FLEXCAN_MECR_FANCEI_MSK);
+                flexcan_write(reg_mecr, &regs->mecr);
+        }
+
         err = flexcan_transceiver_enable(priv);
         if (err)
                 goto out_chip_disable;
@@ -1089,6 +1173,7 @@ static const struct of_device_id flexcan_of_match[] = {
         { .compatible = "fsl,imx6q-flexcan", .data = &fsl_imx6q_devtype_data, },
         { .compatible = "fsl,imx28-flexcan", .data = &fsl_imx28_devtype_data, },
         { .compatible = "fsl,p1010-flexcan", .data = &fsl_p1010_devtype_data, },
+        { .compatible = "fsl,vf610-flexcan", .data = &fsl_vf610_devtype_data, },
         { /* sentinel */ },
 };
 MODULE_DEVICE_TABLE(of, flexcan_of_match);
diff --git a/drivers/net/can/m_can/Kconfig b/drivers/net/can/m_can/Kconfig
new file mode 100644
index 000000000000..fca5482c09ac
--- /dev/null
+++ b/drivers/net/can/m_can/Kconfig
@@ -0,0 +1,4 @@
+config CAN_M_CAN
+        tristate "Bosch M_CAN devices"
+        ---help---
+          Say Y here if you want to support for Bosch M_CAN controller.
diff --git a/drivers/net/can/m_can/Makefile b/drivers/net/can/m_can/Makefile
new file mode 100644
index 000000000000..8bbd7f24f5be
--- /dev/null
+++ b/drivers/net/can/m_can/Makefile
@@ -0,0 +1,5 @@
+#
+#  Makefile for the Bosch M_CAN controller driver.
+#
+
+obj-$(CONFIG_CAN_M_CAN) += m_can.o
diff --git a/drivers/net/can/m_can/m_can.c b/drivers/net/can/m_can/m_can.c
new file mode 100644
index 000000000000..10d571eaed85
--- /dev/null
+++ b/drivers/net/can/m_can/m_can.c
@@ -0,0 +1,1202 @@
+/*
+ * CAN bus driver for Bosch M_CAN controller
+ *
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *      Dong Aisheng <b29396@freescale.com>
+ *
+ * Bosch M_CAN user manual can be obtained from:
+ * http://www.bosch-semiconductors.de/media/pdf_1/ipmodules_1/m_can/
+ * mcan_users_manual_v302.pdf
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/clk.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/io.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <linux/can/dev.h>
+
+/* napi related */
+#define M_CAN_NAPI_WEIGHT       64
+
+/* message ram configuration data length */
+#define MRAM_CFG_LEN    8
+
+/* registers definition */
+enum m_can_reg {
+        M_CAN_CREL      = 0x0,
+        M_CAN_ENDN      = 0x4,
+        M_CAN_CUST      = 0x8,
+        M_CAN_FBTP      = 0xc,
+        M_CAN_TEST      = 0x10,
+        M_CAN_RWD       = 0x14,
+        M_CAN_CCCR      = 0x18,
+        M_CAN_BTP       = 0x1c,
+        M_CAN_TSCC      = 0x20,
+        M_CAN_TSCV      = 0x24,
+        M_CAN_TOCC      = 0x28,
+        M_CAN_TOCV      = 0x2c,
+        M_CAN_ECR       = 0x40,
+        M_CAN_PSR       = 0x44,
+        M_CAN_IR        = 0x50,
+        M_CAN_IE        = 0x54,
+        M_CAN_ILS       = 0x58,
+        M_CAN_ILE       = 0x5c,
+        M_CAN_GFC       = 0x80,
+        M_CAN_SIDFC     = 0x84,
+        M_CAN_XIDFC     = 0x88,
+        M_CAN_XIDAM     = 0x90,
+        M_CAN_HPMS      = 0x94,
+        M_CAN_NDAT1     = 0x98,
+        M_CAN_NDAT2     = 0x9c,
+        M_CAN_RXF0C     = 0xa0,
+        M_CAN_RXF0S     = 0xa4,
+        M_CAN_RXF0A     = 0xa8,
+        M_CAN_RXBC      = 0xac,
+        M_CAN_RXF1C     = 0xb0,
+        M_CAN_RXF1S     = 0xb4,
+        M_CAN_RXF1A     = 0xb8,
+        M_CAN_RXESC     = 0xbc,
+        M_CAN_TXBC      = 0xc0,
+        M_CAN_TXFQS     = 0xc4,
+        M_CAN_TXESC     = 0xc8,
+        M_CAN_TXBRP     = 0xcc,
+        M_CAN_TXBAR     = 0xd0,
+        M_CAN_TXBCR     = 0xd4,
+        M_CAN_TXBTO     = 0xd8,
+        M_CAN_TXBCF     = 0xdc,
+        M_CAN_TXBTIE    = 0xe0,
+        M_CAN_TXBCIE    = 0xe4,
+        M_CAN_TXEFC     = 0xf0,
+        M_CAN_TXEFS     = 0xf4,
+        M_CAN_TXEFA     = 0xf8,
+};
+
+/* m_can lec values */
+enum m_can_lec_type {
+        LEC_NO_ERROR = 0,
+        LEC_STUFF_ERROR,
+        LEC_FORM_ERROR,
+        LEC_ACK_ERROR,
+        LEC_BIT1_ERROR,
+        LEC_BIT0_ERROR,
+        LEC_CRC_ERROR,
+        LEC_UNUSED,
+};
+
+enum m_can_mram_cfg {
+        MRAM_SIDF = 0,
+        MRAM_XIDF,
+        MRAM_RXF0,
+        MRAM_RXF1,
+        MRAM_RXB,
+        MRAM_TXE,
+        MRAM_TXB,
+        MRAM_CFG_NUM,
+};
+
+/* Test Register (TEST) */
+#define TEST_LBCK       BIT(4)
+
+/* CC Control Register(CCCR) */
+#define CCCR_TEST       BIT(7)
+#define CCCR_MON        BIT(5)
+#define CCCR_CCE        BIT(1)
+#define CCCR_INIT       BIT(0)
+
+/* Bit Timing & Prescaler Register (BTP) */
+#define BTR_BRP_MASK            0x3ff
+#define BTR_BRP_SHIFT           16
+#define BTR_TSEG1_SHIFT         8
+#define BTR_TSEG1_MASK          (0x3f << BTR_TSEG1_SHIFT)
+#define BTR_TSEG2_SHIFT         4
+#define BTR_TSEG2_MASK          (0xf << BTR_TSEG2_SHIFT)
+#define BTR_SJW_SHIFT           0
+#define BTR_SJW_MASK            0xf
+
+/* Error Counter Register(ECR) */
+#define ECR_RP                  BIT(15)
+#define ECR_REC_SHIFT           8
+#define ECR_REC_MASK            (0x7f << ECR_REC_SHIFT)
+#define ECR_TEC_SHIFT           0
+#define ECR_TEC_MASK            0xff
+
+/* Protocol Status Register(PSR) */
+#define PSR_BO          BIT(7)
+#define PSR_EW          BIT(6)
+#define PSR_EP          BIT(5)
+#define PSR_LEC_MASK    0x7
+
+/* Interrupt Register(IR) */
+#define IR_ALL_INT      0xffffffff
+#define IR_STE          BIT(31)
+#define IR_FOE          BIT(30)
+#define IR_ACKE         BIT(29)
+#define IR_BE           BIT(28)
+#define IR_CRCE         BIT(27)
+#define IR_WDI          BIT(26)
+#define IR_BO           BIT(25)
+#define IR_EW           BIT(24)
+#define IR_EP           BIT(23)
+#define IR_ELO          BIT(22)
+#define IR_BEU          BIT(21)
+#define IR_BEC          BIT(20)
+#define IR_DRX          BIT(19)
+#define IR_TOO          BIT(18)
+#define IR_MRAF         BIT(17)
+#define IR_TSW          BIT(16)
+#define IR_TEFL         BIT(15)
+#define IR_TEFF         BIT(14)
+#define IR_TEFW         BIT(13)
+#define IR_TEFN         BIT(12)
+#define IR_TFE          BIT(11)
+#define IR_TCF          BIT(10)
+#define IR_TC           BIT(9)
+#define IR_HPM          BIT(8)
+#define IR_RF1L         BIT(7)
+#define IR_RF1F         BIT(6)
+#define IR_RF1W         BIT(5)
+#define IR_RF1N         BIT(4)
+#define IR_RF0L         BIT(3)
+#define IR_RF0F         BIT(2)
+#define IR_RF0W         BIT(1)
+#define IR_RF0N         BIT(0)
+#define IR_ERR_STATE    (IR_BO | IR_EW | IR_EP)
+#define IR_ERR_LEC      (IR_STE | IR_FOE | IR_ACKE | IR_BE | IR_CRCE)
+#define IR_ERR_BUS      (IR_ERR_LEC | IR_WDI | IR_ELO | IR_BEU | \
+                         IR_BEC | IR_TOO | IR_MRAF | IR_TSW | IR_TEFL | \
+                         IR_RF1L | IR_RF0L)
+#define IR_ERR_ALL      (IR_ERR_STATE | IR_ERR_BUS)
+
+/* Interrupt Line Select (ILS) */
+#define ILS_ALL_INT0    0x0
+#define ILS_ALL_INT1    0xFFFFFFFF
+
+/* Interrupt Line Enable (ILE) */
+#define ILE_EINT0       BIT(0)
+#define ILE_EINT1       BIT(1)
+
+/* Rx FIFO 0/1 Configuration (RXF0C/RXF1C) */
+#define RXFC_FWM_OFF    24
+#define RXFC_FWM_MASK   0x7f
+#define RXFC_FWM_1      (1 << RXFC_FWM_OFF)
+#define RXFC_FS_OFF     16
+#define RXFC_FS_MASK    0x7f
+
+/* Rx FIFO 0/1 Status (RXF0S/RXF1S) */
+#define RXFS_RFL        BIT(25)
+#define RXFS_FF         BIT(24)
+#define RXFS_FPI_OFF    16
+#define RXFS_FPI_MASK   0x3f0000
+#define RXFS_FGI_OFF    8
+#define RXFS_FGI_MASK   0x3f00
+#define RXFS_FFL_MASK   0x7f
+
+/* Rx Buffer / FIFO Element Size Configuration (RXESC) */
+#define M_CAN_RXESC_8BYTES      0x0
+
+/* Tx Buffer Configuration(TXBC) */
+#define TXBC_NDTB_OFF           16
+#define TXBC_NDTB_MASK          0x3f
+
+/* Tx Buffer Element Size Configuration(TXESC) */
+#define TXESC_TBDS_8BYTES       0x0
+
+/* Tx Event FIFO Con.guration (TXEFC) */
+#define TXEFC_EFS_OFF           16
+#define TXEFC_EFS_MASK          0x3f
+
+/* Message RAM Configuration (in bytes) */
+#define SIDF_ELEMENT_SIZE       4
+#define XIDF_ELEMENT_SIZE       8
+#define RXF0_ELEMENT_SIZE       16
+#define RXF1_ELEMENT_SIZE       16
+#define RXB_ELEMENT_SIZE        16
+#define TXE_ELEMENT_SIZE        8
+#define TXB_ELEMENT_SIZE        16
+
+/* Message RAM Elements */
+#define M_CAN_FIFO_ID           0x0
+#define M_CAN_FIFO_DLC          0x4
+#define M_CAN_FIFO_DATA(n)      (0x8 + ((n) << 2))
+
+/* Rx Buffer Element */
+#define RX_BUF_ESI              BIT(31)
+#define RX_BUF_XTD              BIT(30)
+#define RX_BUF_RTR              BIT(29)
+
+/* Tx Buffer Element */
+#define TX_BUF_XTD              BIT(30)
+#define TX_BUF_RTR              BIT(29)
+
+/* address offset and element number for each FIFO/Buffer in the Message RAM */
+struct mram_cfg {
+        u16 off;
+        u8  num;
+};
+
+/* m_can private data structure */
+struct m_can_priv {
+        struct can_priv can;    /* must be the first member */
+        struct napi_struct napi;
+        struct net_device *dev;
+        struct device *device;
+        struct clk *hclk;
+        struct clk *cclk;
+        void __iomem *base;
+        u32 irqstatus;
+
+        /* message ram configuration */
+        void __iomem *mram_base;
+        struct mram_cfg mcfg[MRAM_CFG_NUM];
+};
+
+static inline u32 m_can_read(const struct m_can_priv *priv, enum m_can_reg reg)
+{
+        return readl(priv->base + reg);
+}
+
+static inline void m_can_write(const struct m_can_priv *priv,
+                               enum m_can_reg reg, u32 val)
+{
+        writel(val, priv->base + reg);
+}
+
+static inline u32 m_can_fifo_read(const struct m_can_priv *priv,
+                                  u32 fgi, unsigned int offset)
+{
+        return readl(priv->mram_base + priv->mcfg[MRAM_RXF0].off +
+                     fgi * RXF0_ELEMENT_SIZE + offset);
+}
+
+static inline void m_can_fifo_write(const struct m_can_priv *priv,
+                                    u32 fpi, unsigned int offset, u32 val)
+{
+        return writel(val, priv->mram_base + priv->mcfg[MRAM_TXB].off +
+                      fpi * TXB_ELEMENT_SIZE + offset);
+}
+
+static inline void m_can_config_endisable(const struct m_can_priv *priv,
+                                          bool enable)
+{
+        u32 cccr = m_can_read(priv, M_CAN_CCCR);
+        u32 timeout = 10;
+        u32 val = 0;
+
+        if (enable) {
+                /* enable m_can configuration */
+                m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT);
+                /* CCCR.CCE can only be set/reset while CCCR.INIT = '1' */
+                m_can_write(priv, M_CAN_CCCR, cccr | CCCR_INIT | CCCR_CCE);
+        } else {
+                m_can_write(priv, M_CAN_CCCR, cccr & ~(CCCR_INIT | CCCR_CCE));
+        }
+
+        /* there's a delay for module initialization */
+        if (enable)
+                val = CCCR_INIT | CCCR_CCE;
+
+        while ((m_can_read(priv, M_CAN_CCCR) & (CCCR_INIT | CCCR_CCE)) != val) {
+                if (timeout == 0) {
+                        netdev_warn(priv->dev, "Failed to init module\n");
+                        return;
+                }
+                timeout--;
+                udelay(1);
+        }
+}
+
+static inline void m_can_enable_all_interrupts(const struct m_can_priv *priv)
+{
+        m_can_write(priv, M_CAN_ILE, ILE_EINT0 | ILE_EINT1);
+}
+
+static inline void m_can_disable_all_interrupts(const struct m_can_priv *priv)
+{
+        m_can_write(priv, M_CAN_ILE, 0x0);
+}
+
+static void m_can_read_fifo(const struct net_device *dev, struct can_frame *cf,
+                            u32 rxfs)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        u32 id, fgi;
+
+        /* calculate the fifo get index for where to read data */
+        fgi = (rxfs & RXFS_FGI_MASK) >> RXFS_FGI_OFF;
+        id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_ID);
+        if (id & RX_BUF_XTD)
+                cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
+        else
+                cf->can_id = (id >> 18) & CAN_SFF_MASK;
+
+        if (id & RX_BUF_RTR) {
+                cf->can_id |= CAN_RTR_FLAG;
+        } else {
+                id = m_can_fifo_read(priv, fgi, M_CAN_FIFO_DLC);
+                cf->can_dlc = get_can_dlc((id >> 16) & 0x0F);
+                *(u32 *)(cf->data + 0) = m_can_fifo_read(priv, fgi,
+                                                         M_CAN_FIFO_DATA(0));
+                *(u32 *)(cf->data + 4) = m_can_fifo_read(priv, fgi,
+                                                         M_CAN_FIFO_DATA(1));
+        }
+
+        /* acknowledge rx fifo 0 */
+        m_can_write(priv, M_CAN_RXF0A, fgi);
+}
+
+static int m_can_do_rx_poll(struct net_device *dev, int quota)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        struct net_device_stats *stats = &dev->stats;
+        struct sk_buff *skb;
+        struct can_frame *frame;
+        u32 pkts = 0;
+        u32 rxfs;
+
+        rxfs = m_can_read(priv, M_CAN_RXF0S);
+        if (!(rxfs & RXFS_FFL_MASK)) {
+                netdev_dbg(dev, "no messages in fifo0\n");
+                return 0;
+        }
+
+        while ((rxfs & RXFS_FFL_MASK) && (quota > 0)) {
+                if (rxfs & RXFS_RFL)
+                        netdev_warn(dev, "Rx FIFO 0 Message Lost\n");
+
+                skb = alloc_can_skb(dev, &frame);
+                if (!skb) {
+                        stats->rx_dropped++;
+                        return pkts;
+                }
+
+                m_can_read_fifo(dev, frame, rxfs);
+
+                stats->rx_packets++;
+                stats->rx_bytes += frame->can_dlc;
+
+                netif_receive_skb(skb);
+
+                quota--;
+                pkts++;
+                rxfs = m_can_read(priv, M_CAN_RXF0S);
+        }
+
+        if (pkts)
+                can_led_event(dev, CAN_LED_EVENT_RX);
+
+        return pkts;
+}
+
+static int m_can_handle_lost_msg(struct net_device *dev)
+{
+        struct net_device_stats *stats = &dev->stats;
+        struct sk_buff *skb;
+        struct can_frame *frame;
+
+        netdev_err(dev, "msg lost in rxf0\n");
+
+        stats->rx_errors++;
+        stats->rx_over_errors++;
+
+        skb = alloc_can_err_skb(dev, &frame);
+        if (unlikely(!skb))
+                return 0;
+
+        frame->can_id |= CAN_ERR_CRTL;
+        frame->data[1] = CAN_ERR_CRTL_RX_OVERFLOW;
+
+        netif_receive_skb(skb);
+
+        return 1;
+}
+
+static int m_can_handle_lec_err(struct net_device *dev,
+                                enum m_can_lec_type lec_type)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        struct net_device_stats *stats = &dev->stats;
+        struct can_frame *cf;
+        struct sk_buff *skb;
+
+        priv->can.can_stats.bus_error++;
+        stats->rx_errors++;
+
+        /* propagate the error condition to the CAN stack */
+        skb = alloc_can_err_skb(dev, &cf);
+        if (unlikely(!skb))
+                return 0;
+
+        /* check for 'last error code' which tells us the
+         * type of the last error to occur on the CAN bus
+         */
+        cf->can_id |= CAN_ERR_PROT | CAN_ERR_BUSERROR;
+        cf->data[2] |= CAN_ERR_PROT_UNSPEC;
+
+        switch (lec_type) {
+        case LEC_STUFF_ERROR:
+                netdev_dbg(dev, "stuff error\n");
+                cf->data[2] |= CAN_ERR_PROT_STUFF;
+                break;
+        case LEC_FORM_ERROR:
+                netdev_dbg(dev, "form error\n");
+                cf->data[2] |= CAN_ERR_PROT_FORM;
+                break;
+        case LEC_ACK_ERROR:
+                netdev_dbg(dev, "ack error\n");
+                cf->data[3] |= (CAN_ERR_PROT_LOC_ACK |
+                                CAN_ERR_PROT_LOC_ACK_DEL);
+                break;
+        case LEC_BIT1_ERROR:
+                netdev_dbg(dev, "bit1 error\n");
+                cf->data[2] |= CAN_ERR_PROT_BIT1;
+                break;
+        case LEC_BIT0_ERROR:
+                netdev_dbg(dev, "bit0 error\n");
+                cf->data[2] |= CAN_ERR_PROT_BIT0;
+                break;
+        case LEC_CRC_ERROR:
+                netdev_dbg(dev, "CRC error\n");
+                cf->data[3] |= (CAN_ERR_PROT_LOC_CRC_SEQ |
+                                CAN_ERR_PROT_LOC_CRC_DEL);
+                break;
+        default:
+                break;
+        }
+
+        stats->rx_packets++;
+        stats->rx_bytes += cf->can_dlc;
+        netif_receive_skb(skb);
+
+        return 1;
+}
+
+static int m_can_get_berr_counter(const struct net_device *dev,
+                                  struct can_berr_counter *bec)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        unsigned int ecr;
+        int err;
+
+        err = clk_prepare_enable(priv->hclk);
+        if (err)
+                return err;
+
+        err = clk_prepare_enable(priv->cclk);
+        if (err) {
+                clk_disable_unprepare(priv->hclk);
+                return err;
+        }
+
+        ecr = m_can_read(priv, M_CAN_ECR);
+        bec->rxerr = (ecr & ECR_REC_MASK) >> ECR_REC_SHIFT;
+        bec->txerr = ecr & ECR_TEC_MASK;
+
+        clk_disable_unprepare(priv->cclk);
+        clk_disable_unprepare(priv->hclk);
+
+        return 0;
+}
+
+static int m_can_handle_state_change(struct net_device *dev,
+                                     enum can_state new_state)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        struct net_device_stats *stats = &dev->stats;
+        struct can_frame *cf;
+        struct sk_buff *skb;
+        struct can_berr_counter bec;
+        unsigned int ecr;
+
+        switch (new_state) {
+        case CAN_STATE_ERROR_ACTIVE:
+                /* error warning state */
+                priv->can.can_stats.error_warning++;
+                priv->can.state = CAN_STATE_ERROR_WARNING;
+                break;
+        case CAN_STATE_ERROR_PASSIVE:
+                /* error passive state */
+                priv->can.can_stats.error_passive++;
+                priv->can.state = CAN_STATE_ERROR_PASSIVE;
+                break;
+        case CAN_STATE_BUS_OFF:
+                /* bus-off state */
+                priv->can.state = CAN_STATE_BUS_OFF;
+                m_can_disable_all_interrupts(priv);
+                can_bus_off(dev);
+                break;
+        default:
+                break;
+        }
+
+        /* propagate the error condition to the CAN stack */
+        skb = alloc_can_err_skb(dev, &cf);
+        if (unlikely(!skb))
+                return 0;
+
+        m_can_get_berr_counter(dev, &bec);
+
+        switch (new_state) {
+        case CAN_STATE_ERROR_ACTIVE:
+                /* error warning state */
+                cf->can_id |= CAN_ERR_CRTL;
+                cf->data[1] = (bec.txerr > bec.rxerr) ?
+                        CAN_ERR_CRTL_TX_WARNING :
+                        CAN_ERR_CRTL_RX_WARNING;
+                cf->data[6] = bec.txerr;
+                cf->data[7] = bec.rxerr;
+                break;
+        case CAN_STATE_ERROR_PASSIVE:
+                /* error passive state */
+                cf->can_id |= CAN_ERR_CRTL;
+                ecr = m_can_read(priv, M_CAN_ECR);
+                if (ecr & ECR_RP)
+                        cf->data[1] |= CAN_ERR_CRTL_RX_PASSIVE;
+                if (bec.txerr > 127)
+                        cf->data[1] |= CAN_ERR_CRTL_TX_PASSIVE;
+                cf->data[6] = bec.txerr;
+                cf->data[7] = bec.rxerr;
+                break;
+        case CAN_STATE_BUS_OFF:
+                /* bus-off state */
+                cf->can_id |= CAN_ERR_BUSOFF;
+                break;
+        default:
+                break;
+        }
+
+        stats->rx_packets++;
+        stats->rx_bytes += cf->can_dlc;
+        netif_receive_skb(skb);
+
+        return 1;
+}
+
+static int m_can_handle_state_errors(struct net_device *dev, u32 psr)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        int work_done = 0;
+
+        if ((psr & PSR_EW) &&
+            (priv->can.state != CAN_STATE_ERROR_WARNING)) {
+                netdev_dbg(dev, "entered error warning state\n");
+                work_done += m_can_handle_state_change(dev,
+                                                       CAN_STATE_ERROR_WARNING);
+        }
+
+        if ((psr & PSR_EP) &&
+            (priv->can.state != CAN_STATE_ERROR_PASSIVE)) {
+                netdev_dbg(dev, "entered error warning state\n");
+                work_done += m_can_handle_state_change(dev,
+                                                       CAN_STATE_ERROR_PASSIVE);
+        }
+
+        if ((psr & PSR_BO) &&
+            (priv->can.state != CAN_STATE_BUS_OFF)) {
+                netdev_dbg(dev, "entered error warning state\n");
+                work_done += m_can_handle_state_change(dev,
+                                                       CAN_STATE_BUS_OFF);
+        }
+
+        return work_done;
+}
+
+static void m_can_handle_other_err(struct net_device *dev, u32 irqstatus)
+{
+        if (irqstatus & IR_WDI)
+                netdev_err(dev, "Message RAM Watchdog event due to missing READY\n");
+        if (irqstatus & IR_BEU)
+                netdev_err(dev, "Error Logging Overflow\n");
+        if (irqstatus & IR_BEU)
+                netdev_err(dev, "Bit Error Uncorrected\n");
+        if (irqstatus & IR_BEC)
+                netdev_err(dev, "Bit Error Corrected\n");
+        if (irqstatus & IR_TOO)
+                netdev_err(dev, "Timeout reached\n");
+        if (irqstatus & IR_MRAF)
+                netdev_err(dev, "Message RAM access failure occurred\n");
+}
+
+static inline bool is_lec_err(u32 psr)
+{
+        psr &= LEC_UNUSED;
+
+        return psr && (psr != LEC_UNUSED);
+}
+
+static int m_can_handle_bus_errors(struct net_device *dev, u32 irqstatus,
+                                   u32 psr)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        int work_done = 0;
+
+        if (irqstatus & IR_RF0L)
+                work_done += m_can_handle_lost_msg(dev);
+
+        /* handle lec errors on the bus */
+        if ((priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING) &&
+            is_lec_err(psr))
+                work_done += m_can_handle_lec_err(dev, psr & LEC_UNUSED);
+
+        /* other unproccessed error interrupts */
+        m_can_handle_other_err(dev, irqstatus);
+
+        return work_done;
+}
+
+static int m_can_poll(struct napi_struct *napi, int quota)
+{
+        struct net_device *dev = napi->dev;
+        struct m_can_priv *priv = netdev_priv(dev);
+        int work_done = 0;
+        u32 irqstatus, psr;
+
+        irqstatus = priv->irqstatus | m_can_read(priv, M_CAN_IR);
+        if (!irqstatus)
+                goto end;
+
+        psr = m_can_read(priv, M_CAN_PSR);
+        if (irqstatus & IR_ERR_STATE)
+                work_done += m_can_handle_state_errors(dev, psr);
+
+        if (irqstatus & IR_ERR_BUS)
+                work_done += m_can_handle_bus_errors(dev, irqstatus, psr);
+
+        if (irqstatus & IR_RF0N)
+                work_done += m_can_do_rx_poll(dev, (quota - work_done));
+
+        if (work_done < quota) {
+                napi_complete(napi);
+                m_can_enable_all_interrupts(priv);
+        }
+
+end:
+        return work_done;
+}
+
+static irqreturn_t m_can_isr(int irq, void *dev_id)
+{
+        struct net_device *dev = (struct net_device *)dev_id;
+        struct m_can_priv *priv = netdev_priv(dev);
+        struct net_device_stats *stats = &dev->stats;
+        u32 ir;
+
+        ir = m_can_read(priv, M_CAN_IR);
+        if (!ir)
+                return IRQ_NONE;
+
+        /* ACK all irqs */
+        if (ir & IR_ALL_INT)
+                m_can_write(priv, M_CAN_IR, ir);
+
+        /* schedule NAPI in case of
+         * - rx IRQ
+         * - state change IRQ
+         * - bus error IRQ and bus error reporting
+         */
+        if ((ir & IR_RF0N) || (ir & IR_ERR_ALL)) {
+                priv->irqstatus = ir;
+                m_can_disable_all_interrupts(priv);
+                napi_schedule(&priv->napi);
+        }
+
+        /* transmission complete interrupt */
+        if (ir & IR_TC) {
+                stats->tx_bytes += can_get_echo_skb(dev, 0);
+                stats->tx_packets++;
+                can_led_event(dev, CAN_LED_EVENT_TX);
+                netif_wake_queue(dev);
+        }
+
+        return IRQ_HANDLED;
+}
+
+static const struct can_bittiming_const m_can_bittiming_const = {
+        .name = KBUILD_MODNAME,
+        .tseg1_min = 2,         /* Time segment 1 = prop_seg + phase_seg1 */
+        .tseg1_max = 64,
+        .tseg2_min = 1,         /* Time segment 2 = phase_seg2 */
+        .tseg2_max = 16,
+        .sjw_max = 16,
+        .brp_min = 1,
+        .brp_max = 1024,
+        .brp_inc = 1,
+};
+
+static int m_can_set_bittiming(struct net_device *dev)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        const struct can_bittiming *bt = &priv->can.bittiming;
+        u16 brp, sjw, tseg1, tseg2;
+        u32 reg_btp;
+
+        brp = bt->brp - 1;
+        sjw = bt->sjw - 1;
+        tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
+        tseg2 = bt->phase_seg2 - 1;
+        reg_btp = (brp << BTR_BRP_SHIFT) | (sjw << BTR_SJW_SHIFT) |
+                        (tseg1 << BTR_TSEG1_SHIFT) | (tseg2 << BTR_TSEG2_SHIFT);
+        m_can_write(priv, M_CAN_BTP, reg_btp);
+        netdev_dbg(dev, "setting BTP 0x%x\n", reg_btp);
+
+        return 0;
+}
+
+/* Configure M_CAN chip:
+ * - set rx buffer/fifo element size
+ * - configure rx fifo
+ * - accept non-matching frame into fifo 0
+ * - configure tx buffer
+ * - configure mode
+ * - setup bittiming
+ */
+static void m_can_chip_config(struct net_device *dev)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        u32 cccr, test;
+
+        m_can_config_endisable(priv, true);
+
+        /* RX Buffer/FIFO Element Size 8 bytes data field */
+        m_can_write(priv, M_CAN_RXESC, M_CAN_RXESC_8BYTES);
+
+        /* Accept Non-matching Frames Into FIFO 0 */
+        m_can_write(priv, M_CAN_GFC, 0x0);
+
+        /* only support one Tx Buffer currently */
+        m_can_write(priv, M_CAN_TXBC, (1 << TXBC_NDTB_OFF) |
+                    priv->mcfg[MRAM_TXB].off);
+
+        /* only support 8 bytes firstly */
+        m_can_write(priv, M_CAN_TXESC, TXESC_TBDS_8BYTES);
+
+        m_can_write(priv, M_CAN_TXEFC, (1 << TXEFC_EFS_OFF) |
+                    priv->mcfg[MRAM_TXE].off);
+
+        /* rx fifo configuration, blocking mode, fifo size 1 */
+        m_can_write(priv, M_CAN_RXF0C,
+                    (priv->mcfg[MRAM_RXF0].num << RXFC_FS_OFF) |
+                    RXFC_FWM_1 | priv->mcfg[MRAM_RXF0].off);
+
+        m_can_write(priv, M_CAN_RXF1C,
+                    (priv->mcfg[MRAM_RXF1].num << RXFC_FS_OFF) |
+                    RXFC_FWM_1 | priv->mcfg[MRAM_RXF1].off);
+
+        cccr = m_can_read(priv, M_CAN_CCCR);
+        cccr &= ~(CCCR_TEST | CCCR_MON);
+        test = m_can_read(priv, M_CAN_TEST);
+        test &= ~TEST_LBCK;
+
+        if (priv->can.ctrlmode & CAN_CTRLMODE_LISTENONLY)
+                cccr |= CCCR_MON;
+
+        if (priv->can.ctrlmode & CAN_CTRLMODE_LOOPBACK) {
+                cccr |= CCCR_TEST;
+                test |= TEST_LBCK;
+        }
+
+        m_can_write(priv, M_CAN_CCCR, cccr);
+        m_can_write(priv, M_CAN_TEST, test);
+
+        /* enable interrupts */
+        m_can_write(priv, M_CAN_IR, IR_ALL_INT);
+        if (!(priv->can.ctrlmode & CAN_CTRLMODE_BERR_REPORTING))
+                m_can_write(priv, M_CAN_IE, IR_ALL_INT & ~IR_ERR_LEC);
+        else
+                m_can_write(priv, M_CAN_IE, IR_ALL_INT);
+
+        /* route all interrupts to INT0 */
+        m_can_write(priv, M_CAN_ILS, ILS_ALL_INT0);
+
+        /* set bittiming params */
+        m_can_set_bittiming(dev);
+
+        m_can_config_endisable(priv, false);
+}
+
+static void m_can_start(struct net_device *dev)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+
+        /* basic m_can configuration */
+        m_can_chip_config(dev);
+
+        priv->can.state = CAN_STATE_ERROR_ACTIVE;
+
+        m_can_enable_all_interrupts(priv);
+}
+
+static int m_can_set_mode(struct net_device *dev, enum can_mode mode)
+{
+        switch (mode) {
+        case CAN_MODE_START:
+                m_can_start(dev);
+                netif_wake_queue(dev);
+                break;
+        default:
+                return -EOPNOTSUPP;
+        }
+
+        return 0;
+}
+
+static void free_m_can_dev(struct net_device *dev)
+{
+        free_candev(dev);
+}
+
+static struct net_device *alloc_m_can_dev(void)
+{
+        struct net_device *dev;
+        struct m_can_priv *priv;
+
+        dev = alloc_candev(sizeof(*priv), 1);
+        if (!dev)
+                return NULL;
+
+        priv = netdev_priv(dev);
+        netif_napi_add(dev, &priv->napi, m_can_poll, M_CAN_NAPI_WEIGHT);
+
+        priv->dev = dev;
+        priv->can.bittiming_const = &m_can_bittiming_const;
+        priv->can.do_set_mode = m_can_set_mode;
+        priv->can.do_get_berr_counter = m_can_get_berr_counter;
+        priv->can.ctrlmode_supported = CAN_CTRLMODE_LOOPBACK |
+                                        CAN_CTRLMODE_LISTENONLY |
+                                        CAN_CTRLMODE_BERR_REPORTING;
+
+        return dev;
+}
+
+static int m_can_open(struct net_device *dev)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        int err;
+
+        err = clk_prepare_enable(priv->hclk);
+        if (err)
+                return err;
+
+        err = clk_prepare_enable(priv->cclk);
+        if (err)
+                goto exit_disable_hclk;
+
+        /* open the can device */
+        err = open_candev(dev);
+        if (err) {
+                netdev_err(dev, "failed to open can device\n");
+                goto exit_disable_cclk;
+        }
+
+        /* register interrupt handler */
+        err = request_irq(dev->irq, m_can_isr, IRQF_SHARED, dev->name,
+                          dev);
+        if (err < 0) {
+                netdev_err(dev, "failed to request interrupt\n");
+                goto exit_irq_fail;
+        }
+
+        /* start the m_can controller */
+        m_can_start(dev);
+
+        can_led_event(dev, CAN_LED_EVENT_OPEN);
+        napi_enable(&priv->napi);
+        netif_start_queue(dev);
+
+        return 0;
+
+exit_irq_fail:
+        close_candev(dev);
+exit_disable_cclk:
+        clk_disable_unprepare(priv->cclk);
+exit_disable_hclk:
+        clk_disable_unprepare(priv->hclk);
+        return err;
+}
+
+static void m_can_stop(struct net_device *dev)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+
+        /* disable all interrupts */
+        m_can_disable_all_interrupts(priv);
+
+        clk_disable_unprepare(priv->hclk);
+        clk_disable_unprepare(priv->cclk);
+
+        /* set the state as STOPPED */
+        priv->can.state = CAN_STATE_STOPPED;
+}
+
+static int m_can_close(struct net_device *dev)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+
+        netif_stop_queue(dev);
+        napi_disable(&priv->napi);
+        m_can_stop(dev);
+        free_irq(dev->irq, dev);
+        close_candev(dev);
+        can_led_event(dev, CAN_LED_EVENT_STOP);
+
+        return 0;
+}
+
+static netdev_tx_t m_can_start_xmit(struct sk_buff *skb,
+                                    struct net_device *dev)
+{
+        struct m_can_priv *priv = netdev_priv(dev);
+        struct can_frame *cf = (struct can_frame *)skb->data;
+        u32 id;
+
+        if (can_dropped_invalid_skb(dev, skb))
+                return NETDEV_TX_OK;
+
+        netif_stop_queue(dev);
+
+        if (cf->can_id & CAN_EFF_FLAG) {
+                id = cf->can_id & CAN_EFF_MASK;
+                id |= TX_BUF_XTD;
+        } else {
+                id = ((cf->can_id & CAN_SFF_MASK) << 18);
+        }
+
+        if (cf->can_id & CAN_RTR_FLAG)
+                id |= TX_BUF_RTR;
+
+        /* message ram configuration */
+        m_can_fifo_write(priv, 0, M_CAN_FIFO_ID, id);
+        m_can_fifo_write(priv, 0, M_CAN_FIFO_DLC, cf->can_dlc << 16);
+        m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(0), *(u32 *)(cf->data + 0));
+        m_can_fifo_write(priv, 0, M_CAN_FIFO_DATA(1), *(u32 *)(cf->data + 4));
+        can_put_echo_skb(skb, dev, 0);
+
+        /* enable first TX buffer to start transfer  */
+        m_can_write(priv, M_CAN_TXBTIE, 0x1);
+        m_can_write(priv, M_CAN_TXBAR, 0x1);
+
+        return NETDEV_TX_OK;
+}
+
+static const struct net_device_ops m_can_netdev_ops = {
+        .ndo_open = m_can_open,
+        .ndo_stop = m_can_close,
+        .ndo_start_xmit = m_can_start_xmit,
+};
+
+static int register_m_can_dev(struct net_device *dev)
+{
+        dev->flags |= IFF_ECHO; /* we support local echo */
+        dev->netdev_ops = &m_can_netdev_ops;
+
+        return register_candev(dev);
+}
+
+static int m_can_of_parse_mram(struct platform_device *pdev,
+                               struct m_can_priv *priv)
+{
+        struct device_node *np = pdev->dev.of_node;
+        struct resource *res;
+        void __iomem *addr;
+        u32 out_val[MRAM_CFG_LEN];
+        int ret;
+
+        /* message ram could be shared */
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "message_ram");
+        if (!res)
+                return -ENODEV;
+
+        addr = devm_ioremap(&pdev->dev, res->start, resource_size(res));
+        if (!addr)
+                return -ENOMEM;
+
+        /* get message ram configuration */
+        ret = of_property_read_u32_array(np, "bosch,mram-cfg",
+                                         out_val, sizeof(out_val) / 4);
+        if (ret) {
+                dev_err(&pdev->dev, "can not get message ram configuration\n");
+                return -ENODEV;
+        }
+
+        priv->mram_base = addr;
+        priv->mcfg[MRAM_SIDF].off = out_val[0];
+        priv->mcfg[MRAM_SIDF].num = out_val[1];
+        priv->mcfg[MRAM_XIDF].off = priv->mcfg[MRAM_SIDF].off +
+                        priv->mcfg[MRAM_SIDF].num * SIDF_ELEMENT_SIZE;
+        priv->mcfg[MRAM_XIDF].num = out_val[2];
+        priv->mcfg[MRAM_RXF0].off = priv->mcfg[MRAM_XIDF].off +
+                        priv->mcfg[MRAM_XIDF].num * XIDF_ELEMENT_SIZE;
+        priv->mcfg[MRAM_RXF0].num = out_val[3] & RXFC_FS_MASK;
+        priv->mcfg[MRAM_RXF1].off = priv->mcfg[MRAM_RXF0].off +
+                        priv->mcfg[MRAM_RXF0].num * RXF0_ELEMENT_SIZE;
+        priv->mcfg[MRAM_RXF1].num = out_val[4] & RXFC_FS_MASK;
+        priv->mcfg[MRAM_RXB].off = priv->mcfg[MRAM_RXF1].off +
+                        priv->mcfg[MRAM_RXF1].num * RXF1_ELEMENT_SIZE;
+        priv->mcfg[MRAM_RXB].num = out_val[5];
+        priv->mcfg[MRAM_TXE].off = priv->mcfg[MRAM_RXB].off +
+                        priv->mcfg[MRAM_RXB].num * RXB_ELEMENT_SIZE;
+        priv->mcfg[MRAM_TXE].num = out_val[6];
+        priv->mcfg[MRAM_TXB].off = priv->mcfg[MRAM_TXE].off +
+                        priv->mcfg[MRAM_TXE].num * TXE_ELEMENT_SIZE;
+        priv->mcfg[MRAM_TXB].num = out_val[7] & TXBC_NDTB_MASK;
+
+        dev_dbg(&pdev->dev, "mram_base %p sidf 0x%x %d xidf 0x%x %d rxf0 0x%x %d rxf1 0x%x %d rxb 0x%x %d txe 0x%x %d txb 0x%x %d\n",
+                priv->mram_base,
+                priv->mcfg[MRAM_SIDF].off, priv->mcfg[MRAM_SIDF].num,
+                priv->mcfg[MRAM_XIDF].off, priv->mcfg[MRAM_XIDF].num,
+                priv->mcfg[MRAM_RXF0].off, priv->mcfg[MRAM_RXF0].num,
+                priv->mcfg[MRAM_RXF1].off, priv->mcfg[MRAM_RXF1].num,
+                priv->mcfg[MRAM_RXB].off, priv->mcfg[MRAM_RXB].num,
+                priv->mcfg[MRAM_TXE].off, priv->mcfg[MRAM_TXE].num,
+                priv->mcfg[MRAM_TXB].off, priv->mcfg[MRAM_TXB].num);
+
+        return 0;
+}
+
+static int m_can_plat_probe(struct platform_device *pdev)
+{
+        struct net_device *dev;
+        struct m_can_priv *priv;
+        struct resource *res;
+        void __iomem *addr;
+        struct clk *hclk, *cclk;
+        int irq, ret;
+
+        hclk = devm_clk_get(&pdev->dev, "hclk");
+        cclk = devm_clk_get(&pdev->dev, "cclk");
+        if (IS_ERR(hclk) || IS_ERR(cclk)) {
+                dev_err(&pdev->dev, "no clock find\n");
+                return -ENODEV;
+        }
+
+        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "m_can");
+        addr = devm_ioremap_resource(&pdev->dev, res);
+        irq = platform_get_irq_byname(pdev, "int0");
+        if (IS_ERR(addr) || irq < 0)
+                return -EINVAL;
+
+        /* allocate the m_can device */
+        dev = alloc_m_can_dev();
+        if (!dev)
+                return -ENOMEM;
+
+        priv = netdev_priv(dev);
+        dev->irq = irq;
+        priv->base = addr;
+        priv->device = &pdev->dev;
+        priv->hclk = hclk;
+        priv->cclk = cclk;
+        priv->can.clock.freq = clk_get_rate(cclk);
+
+        ret = m_can_of_parse_mram(pdev, priv);
+        if (ret)
+                goto failed_free_dev;
+
+        platform_set_drvdata(pdev, dev);
+        SET_NETDEV_DEV(dev, &pdev->dev);
+
+        ret = register_m_can_dev(dev);
+        if (ret) {
+                dev_err(&pdev->dev, "registering %s failed (err=%d)\n",
+                        KBUILD_MODNAME, ret);
+                goto failed_free_dev;
+        }
+
+        devm_can_led_init(dev);
+
+        dev_info(&pdev->dev, "%s device registered (regs=%p, irq=%d)\n",
+                 KBUILD_MODNAME, priv->base, dev->irq);
+
+        return 0;
+
+failed_free_dev:
+        free_m_can_dev(dev);
+        return ret;
+}
+
+static __maybe_unused int m_can_suspend(struct device *dev)
+{
+        struct net_device *ndev = dev_get_drvdata(dev);
+        struct m_can_priv *priv = netdev_priv(ndev);
+
+        if (netif_running(ndev)) {
+                netif_stop_queue(ndev);
+                netif_device_detach(ndev);
+        }
+
+        /* TODO: enter low power */
+
+        priv->can.state = CAN_STATE_SLEEPING;
+
+        return 0;
+}
+
+static __maybe_unused int m_can_resume(struct device *dev)
+{
+        struct net_device *ndev = dev_get_drvdata(dev);
+        struct m_can_priv *priv = netdev_priv(ndev);
+
+        /* TODO: exit low power */
+
+        priv->can.state = CAN_STATE_ERROR_ACTIVE;
+
+        if (netif_running(ndev)) {
+                netif_device_attach(ndev);
+                netif_start_queue(ndev);
+        }
+
+        return 0;
+}
+
+static void unregister_m_can_dev(struct net_device *dev)
+{
+        unregister_candev(dev);
+}
+
+static int m_can_plat_remove(struct platform_device *pdev)
+{
+        struct net_device *dev = platform_get_drvdata(pdev);
+
+        unregister_m_can_dev(dev);
+        platform_set_drvdata(pdev, NULL);
+
+        free_m_can_dev(dev);
+
+        return 0;
+}
+
+static const struct dev_pm_ops m_can_pmops = {
+        SET_SYSTEM_SLEEP_PM_OPS(m_can_suspend, m_can_resume)
+};
+
+static const struct of_device_id m_can_of_table[] = {
+        { .compatible = "bosch,m_can", .data = NULL },
+        { /* sentinel */ },
+};
+MODULE_DEVICE_TABLE(of, m_can_of_table);
+
+static struct platform_driver m_can_plat_driver = {
+        .driver = {
+                .name = KBUILD_MODNAME,
+                .of_match_table = m_can_of_table,
+                .pm     = &m_can_pmops,
+        },
+        .probe = m_can_plat_probe,
+        .remove = m_can_plat_remove,
+};
+
+module_platform_driver(m_can_plat_driver);
+
+MODULE_AUTHOR("Dong Aisheng <b29396@freescale.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller");
diff --git a/drivers/net/can/mscan/Makefile b/drivers/net/can/mscan/Makefile
index c9fab17cd8b4..58903b45f5fb 100644
--- a/drivers/net/can/mscan/Makefile
+++ b/drivers/net/can/mscan/Makefile
@@ -1,5 +1,3 @@
 
 obj-$(CONFIG_CAN_MPC5XXX)       += mscan-mpc5xxx.o
 mscan-mpc5xxx-objs              := mscan.o mpc5xxx_can.o
-
-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/rcar_can.c b/drivers/net/can/rcar_can.c
index 5268d216ecfa..1abe133d1594 100644
--- a/drivers/net/can/rcar_can.c
+++ b/drivers/net/can/rcar_can.c
@@ -20,6 +20,7 @@
 #include <linux/can/dev.h>
 #include <linux/clk.h>
 #include <linux/can/platform/rcar_can.h>
+#include <linux/of.h>
 
 #define RCAR_CAN_DRV_NAME       "rcar_can"
 
@@ -87,6 +88,7 @@ struct rcar_can_priv {
         struct napi_struct napi;
         struct rcar_can_regs __iomem *regs;
         struct clk *clk;
+        struct clk *can_clk;
         u8 tx_dlc[RCAR_CAN_FIFO_DEPTH];
         u32 tx_head;
         u32 tx_tail;
@@ -505,14 +507,20 @@ static int rcar_can_open(struct net_device *ndev)
 
         err = clk_prepare_enable(priv->clk);
         if (err) {
-                netdev_err(ndev, "clk_prepare_enable() failed, error %d\n",
+                netdev_err(ndev, "failed to enable periperal clock, error %d\n",
                            err);
                 goto out;
         }
+        err = clk_prepare_enable(priv->can_clk);
+        if (err) {
+                netdev_err(ndev, "failed to enable CAN clock, error %d\n",
+                           err);
+                goto out_clock;
+        }
         err = open_candev(ndev);
         if (err) {
                 netdev_err(ndev, "open_candev() failed, error %d\n", err);
-                goto out_clock;
+                goto out_can_clock;
         }
         napi_enable(&priv->napi);
         err = request_irq(ndev->irq, rcar_can_interrupt, 0, ndev->name, ndev);
@@ -527,6 +535,8 @@ static int rcar_can_open(struct net_device *ndev)
 out_close:
         napi_disable(&priv->napi);
         close_candev(ndev);
+out_can_clock:
+        clk_disable_unprepare(priv->can_clk);
 out_clock:
         clk_disable_unprepare(priv->clk);
 out:
@@ -565,6 +575,7 @@ static int rcar_can_close(struct net_device *ndev)
         rcar_can_stop(ndev);
         free_irq(ndev->irq, ndev);
         napi_disable(&priv->napi);
+        clk_disable_unprepare(priv->can_clk);
         clk_disable_unprepare(priv->clk);
         close_candev(ndev);
         can_led_event(ndev, CAN_LED_EVENT_STOP);
@@ -715,6 +726,12 @@ static int rcar_can_get_berr_counter(const struct net_device *dev,
         return 0;
 }
 
+static const char * const clock_names[] = {
+        [CLKR_CLKP1]    = "clkp1",
+        [CLKR_CLKP2]    = "clkp2",
+        [CLKR_CLKEXT]   = "can_clk",
+};
+
 static int rcar_can_probe(struct platform_device *pdev)
 {
         struct rcar_can_platform_data *pdata;
@@ -722,13 +739,20 @@ static int rcar_can_probe(struct platform_device *pdev)
         struct net_device *ndev;
         struct resource *mem;
         void __iomem *addr;
+        u32 clock_select = CLKR_CLKP1;
         int err = -ENODEV;
         int irq;
 
-        pdata = dev_get_platdata(&pdev->dev);
-        if (!pdata) {
-                dev_err(&pdev->dev, "No platform data provided!\n");
-                goto fail;
+        if (pdev->dev.of_node) {
+                of_property_read_u32(pdev->dev.of_node,
+                                     "renesas,can-clock-select", &clock_select);
+        } else {
+                pdata = dev_get_platdata(&pdev->dev);
+                if (!pdata) {
+                        dev_err(&pdev->dev, "No platform data provided!\n");
+                        goto fail;
+                }
+                clock_select = pdata->clock_select;
         }
 
         irq = platform_get_irq(pdev, 0);
@@ -753,10 +777,22 @@ static int rcar_can_probe(struct platform_device *pdev)
 
         priv = netdev_priv(ndev);
 
-        priv->clk = devm_clk_get(&pdev->dev, NULL);
+        priv->clk = devm_clk_get(&pdev->dev, "clkp1");
         if (IS_ERR(priv->clk)) {
                 err = PTR_ERR(priv->clk);
-                dev_err(&pdev->dev, "cannot get clock: %d\n", err);
+                dev_err(&pdev->dev, "cannot get peripheral clock: %d\n", err);
+                goto fail_clk;
+        }
+
+        if (clock_select >= ARRAY_SIZE(clock_names)) {
+                err = -EINVAL;
+                dev_err(&pdev->dev, "invalid CAN clock selected\n");
+                goto fail_clk;
+        }
+        priv->can_clk = devm_clk_get(&pdev->dev, clock_names[clock_select]);
+        if (IS_ERR(priv->can_clk)) {
+                err = PTR_ERR(priv->can_clk);
+                dev_err(&pdev->dev, "cannot get CAN clock: %d\n", err);
                 goto fail_clk;
         }
 
@@ -765,8 +801,8 @@ static int rcar_can_probe(struct platform_device *pdev)
         ndev->flags |= IFF_ECHO;
         priv->ndev = ndev;
         priv->regs = addr;
-        priv->clock_select = pdata->clock_select;
-        priv->can.clock.freq = clk_get_rate(priv->clk);
+        priv->clock_select = clock_select;
+        priv->can.clock.freq = clk_get_rate(priv->can_clk);
         priv->can.bittiming_const = &rcar_can_bittiming_const;
         priv->can.do_set_mode = rcar_can_do_set_mode;
         priv->can.do_get_berr_counter = rcar_can_get_berr_counter;
@@ -858,10 +894,20 @@ static int __maybe_unused rcar_can_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(rcar_can_pm_ops, rcar_can_suspend, rcar_can_resume);
 
+static const struct of_device_id rcar_can_of_table[] __maybe_unused = {
+        { .compatible = "renesas,can-r8a7778" },
+        { .compatible = "renesas,can-r8a7779" },
+        { .compatible = "renesas,can-r8a7790" },
+        { .compatible = "renesas,can-r8a7791" },
+        { }
+};
+MODULE_DEVICE_TABLE(of, rcar_can_of_table);
+
 static struct platform_driver rcar_can_driver = {
         .driver = {
                 .name = RCAR_CAN_DRV_NAME,
                 .owner = THIS_MODULE,
+                .of_match_table = of_match_ptr(rcar_can_of_table),
                 .pm = &rcar_can_pm_ops,
         },
         .probe = rcar_can_probe,
diff --git a/drivers/net/can/sja1000/Makefile b/drivers/net/can/sja1000/Makefile
index 531d5fcc97e5..be11ddd11b87 100644
--- a/drivers/net/can/sja1000/Makefile
+++ b/drivers/net/can/sja1000/Makefile
@@ -12,5 +12,3 @@ obj-$(CONFIG_CAN_PEAK_PCMCIA) += peak_pcmcia.o
 obj-$(CONFIG_CAN_PEAK_PCI) += peak_pci.o
 obj-$(CONFIG_CAN_PLX_PCI) += plx_pci.o
 obj-$(CONFIG_CAN_TSCAN1) += tscan1.o
-
-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/softing/Makefile b/drivers/net/can/softing/Makefile
index c5e5016c742e..a23da492dad5 100644
--- a/drivers/net/can/softing/Makefile
+++ b/drivers/net/can/softing/Makefile
@@ -2,5 +2,3 @@
 softing-y := softing_main.o softing_fw.o
 obj-$(CONFIG_CAN_SOFTING) += softing.o
 obj-$(CONFIG_CAN_SOFTING_CS) += softing_cs.o
-
-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/spi/Makefile b/drivers/net/can/spi/Makefile
index 90bcacffbc65..0e86040cdd8c 100644
--- a/drivers/net/can/spi/Makefile
+++ b/drivers/net/can/spi/Makefile
@@ -4,5 +4,3 @@
 
 
 obj-$(CONFIG_CAN_MCP251X)       += mcp251x.o
-
-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/can/spi/mcp251x.c b/drivers/net/can/spi/mcp251x.c
index 5df239e68812..c66d699640a9 100644
--- a/drivers/net/can/spi/mcp251x.c
+++ b/drivers/net/can/spi/mcp251x.c
@@ -1107,10 +1107,10 @@ static int mcp251x_can_probe(struct spi_device *spi)
                  * Minimum coherent DMA allocation is PAGE_SIZE, so allocate
                  * that much and share it between Tx and Rx DMA buffers.
                  */
-                priv->spi_tx_buf = dma_alloc_coherent(&spi->dev,
-                                                      PAGE_SIZE,
-                                                      &priv->spi_tx_dma,
-                                                      GFP_DMA);
+                priv->spi_tx_buf = dmam_alloc_coherent(&spi->dev,
+                                                       PAGE_SIZE,
+                                                       &priv->spi_tx_dma,
+                                                       GFP_DMA);
 
                 if (priv->spi_tx_buf) {
                         priv->spi_rx_buf = (priv->spi_tx_buf + (PAGE_SIZE / 2));
@@ -1156,9 +1156,6 @@ static int mcp251x_can_probe(struct spi_device *spi)
         return 0;
 
 error_probe:
-        if (mcp251x_enable_dma)
-                dma_free_coherent(&spi->dev, PAGE_SIZE,
-                                  priv->spi_tx_buf, priv->spi_tx_dma);
         mcp251x_power_enable(priv->power, 0);
 
 out_clk:
@@ -1178,11 +1175,6 @@ static int mcp251x_can_remove(struct spi_device *spi)
 
         unregister_candev(net);
 
-        if (mcp251x_enable_dma) {
-                dma_free_coherent(&spi->dev, PAGE_SIZE,
-                                  priv->spi_tx_buf, priv->spi_tx_dma);
-        }
-
         mcp251x_power_enable(priv->power, 0);
 
         if (!IS_ERR(priv->clk))
diff --git a/drivers/net/can/usb/Makefile b/drivers/net/can/usb/Makefile
index 7b9a393b1ac8..a64cf983fb87 100644
--- a/drivers/net/can/usb/Makefile
+++ b/drivers/net/can/usb/Makefile
@@ -8,5 +8,3 @@ obj-$(CONFIG_CAN_GS_USB) += gs_usb.o
 obj-$(CONFIG_CAN_KVASER_USB) += kvaser_usb.o
 obj-$(CONFIG_CAN_PEAK_USB) += peak_usb/
 obj-$(CONFIG_CAN_8DEV_USB) += usb_8dev.o
-
-ccflags-$(CONFIG_CAN_DEBUG_DEVICES) := -DDEBUG
diff --git a/drivers/net/dsa/Kconfig b/drivers/net/dsa/Kconfig
index b8fe808b7957..c6ee07c6a1b5 100644
--- a/drivers/net/dsa/Kconfig
+++ b/drivers/net/dsa/Kconfig
@@ -36,4 +36,15 @@ config NET_DSA_MV88E6123_61_65
           This enables support for the Marvell 88E6123/6161/6165
           ethernet switch chips.
 
+config NET_DSA_BCM_SF2
+        tristate "Broadcom Starfighter 2 Ethernet switch support"
+        select NET_DSA
+        select NET_DSA_TAG_BRCM
+        select FIXED_PHY if NET_DSA_BCM_SF2=y
+        select BCM7XXX_PHY
+        select MDIO_BCM_UNIMAC
+        ---help---
+          This enables support for the Broadcom Starfighter 2 Ethernet
+          switch chips.
+
 endmenu
diff --git a/drivers/net/dsa/Makefile b/drivers/net/dsa/Makefile
index f3bda05536cc..dd3cd3b8157f 100644
--- a/drivers/net/dsa/Makefile
+++ b/drivers/net/dsa/Makefile
@@ -7,3 +7,4 @@ endif
 ifdef CONFIG_NET_DSA_MV88E6131
 mv88e6xxx_drv-y += mv88e6131.o
 endif
+obj-$(CONFIG_NET_DSA_BCM_SF2)   += bcm_sf2.o
diff --git a/drivers/net/dsa/bcm_sf2.c b/drivers/net/dsa/bcm_sf2.c
new file mode 100644
index 000000000000..bb7cb8e283b1
--- /dev/null
+++ b/drivers/net/dsa/bcm_sf2.c
@@ -0,0 +1,626 @@
+/*
+ * Broadcom Starfighter 2 DSA switch driver
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/list.h>
+#include <linux/module.h>
+#include <linux/netdevice.h>
+#include <linux/interrupt.h>
+#include <linux/platform_device.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/phy_fixed.h>
+#include <linux/mii.h>
+#include <linux/of.h>
+#include <linux/of_irq.h>
+#include <linux/of_address.h>
+#include <net/dsa.h>
+
+#include "bcm_sf2.h"
+#include "bcm_sf2_regs.h"
+
+/* String, offset, and register size in bytes if different from 4 bytes */
+static const struct bcm_sf2_hw_stats bcm_sf2_mib[] = {
+        { "TxOctets",           0x000, 8        },
+        { "TxDropPkts",         0x020           },
+        { "TxQPKTQ0",           0x030           },
+        { "TxBroadcastPkts",    0x040           },
+        { "TxMulticastPkts",    0x050           },
+        { "TxUnicastPKts",      0x060           },
+        { "TxCollisions",       0x070           },
+        { "TxSingleCollision",  0x080           },
+        { "TxMultipleCollision", 0x090          },
+        { "TxDeferredCollision", 0x0a0          },
+        { "TxLateCollision",    0x0b0           },
+        { "TxExcessiveCollision", 0x0c0         },
+        { "TxFrameInDisc",      0x0d0           },
+        { "TxPausePkts",        0x0e0           },
+        { "TxQPKTQ1",           0x0f0           },
+        { "TxQPKTQ2",           0x100           },
+        { "TxQPKTQ3",           0x110           },
+        { "TxQPKTQ4",           0x120           },
+        { "TxQPKTQ5",           0x130           },
+        { "RxOctets",           0x140, 8        },
+        { "RxUndersizePkts",    0x160           },
+        { "RxPausePkts",        0x170           },
+        { "RxPkts64Octets",     0x180           },
+        { "RxPkts65to127Octets", 0x190          },
+        { "RxPkts128to255Octets", 0x1a0         },
+        { "RxPkts256to511Octets", 0x1b0         },
+        { "RxPkts512to1023Octets", 0x1c0        },
+        { "RxPkts1024toMaxPktsOctets", 0x1d0    },
+        { "RxOversizePkts",     0x1e0           },
+        { "RxJabbers",          0x1f0           },
+        { "RxAlignmentErrors",  0x200           },
+        { "RxFCSErrors",        0x210           },
+        { "RxGoodOctets",       0x220, 8        },
+        { "RxDropPkts",         0x240           },
+        { "RxUnicastPkts",      0x250           },
+        { "RxMulticastPkts",    0x260           },
+        { "RxBroadcastPkts",    0x270           },
+        { "RxSAChanges",        0x280           },
+        { "RxFragments",        0x290           },
+        { "RxJumboPkt",         0x2a0           },
+        { "RxSymblErr",         0x2b0           },
+        { "InRangeErrCount",    0x2c0           },
+        { "OutRangeErrCount",   0x2d0           },
+        { "EEELpiEvent",        0x2e0           },
+        { "EEELpiDuration",     0x2f0           },
+        { "RxDiscard",          0x300, 8        },
+        { "TxQPKTQ6",           0x320           },
+        { "TxQPKTQ7",           0x330           },
+        { "TxPkts64Octets",     0x340           },
+        { "TxPkts65to127Octets", 0x350          },
+        { "TxPkts128to255Octets", 0x360         },
+        { "TxPkts256to511Ocets", 0x370          },
+        { "TxPkts512to1023Ocets", 0x380         },
+        { "TxPkts1024toMaxPktOcets", 0x390      },
+};
+
+#define BCM_SF2_STATS_SIZE      ARRAY_SIZE(bcm_sf2_mib)
+
+static void bcm_sf2_sw_get_strings(struct dsa_switch *ds,
+                                   int port, uint8_t *data)
+{
+        unsigned int i;
+
+        for (i = 0; i < BCM_SF2_STATS_SIZE; i++)
+                memcpy(data + i * ETH_GSTRING_LEN,
+                       bcm_sf2_mib[i].string, ETH_GSTRING_LEN);
+}
+
+static void bcm_sf2_sw_get_ethtool_stats(struct dsa_switch *ds,
+                                         int port, uint64_t *data)
+{
+        struct bcm_sf2_priv *priv = ds_to_priv(ds);
+        const struct bcm_sf2_hw_stats *s;
+        unsigned int i;
+        u64 val = 0;
+        u32 offset;
+
+        mutex_lock(&priv->stats_mutex);
+
+        /* Now fetch the per-port counters */
+        for (i = 0; i < BCM_SF2_STATS_SIZE; i++) {
+                s = &bcm_sf2_mib[i];
+
+                /* Do a latched 64-bit read if needed */
+                offset = s->reg + CORE_P_MIB_OFFSET(port);
+                if (s->sizeof_stat == 8)
+                        val = core_readq(priv, offset);
+                else
+                        val = core_readl(priv, offset);
+
+                data[i] = (u64)val;
+        }
+
+        mutex_unlock(&priv->stats_mutex);
+}
+
+static int bcm_sf2_sw_get_sset_count(struct dsa_switch *ds)
+{
+        return BCM_SF2_STATS_SIZE;
+}
+
+static char *bcm_sf2_sw_probe(struct mii_bus *bus, int sw_addr)
+{
+        return "Broadcom Starfighter 2";
+}
+
+static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
+{
+        struct bcm_sf2_priv *priv = ds_to_priv(ds);
+        unsigned int i;
+        u32 reg, val;
+
+        /* Enable the port memories */
+        reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
+        reg &= ~P_TXQ_PSM_VDD(port);
+        core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
+
+        /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
+        reg = core_readl(priv, CORE_IMP_CTL);
+        reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
+        reg &= ~(RX_DIS | TX_DIS);
+        core_writel(priv, reg, CORE_IMP_CTL);
+
+        /* Enable forwarding */
+        core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
+
+        /* Enable IMP port in dumb mode */
+        reg = core_readl(priv, CORE_SWITCH_CTRL);
+        reg |= MII_DUMB_FWDG_EN;
+        core_writel(priv, reg, CORE_SWITCH_CTRL);
+
+        /* Resolve which bit controls the Broadcom tag */
+        switch (port) {
+        case 8:
+                val = BRCM_HDR_EN_P8;
+                break;
+        case 7:
+                val = BRCM_HDR_EN_P7;
+                break;
+        case 5:
+                val = BRCM_HDR_EN_P5;
+                break;
+        default:
+                val = 0;
+                break;
+        }
+
+        /* Enable Broadcom tags for IMP port */
+        reg = core_readl(priv, CORE_BRCM_HDR_CTRL);
+        reg |= val;
+        core_writel(priv, reg, CORE_BRCM_HDR_CTRL);
+
+        /* Enable reception Broadcom tag for CPU TX (switch RX) to
+         * allow us to tag outgoing frames
+         */
+        reg = core_readl(priv, CORE_BRCM_HDR_RX_DIS);
+        reg &= ~(1 << port);
+        core_writel(priv, reg, CORE_BRCM_HDR_RX_DIS);
+
+        /* Enable transmission of Broadcom tags from the switch (CPU RX) to
+         * allow delivering frames to the per-port net_devices
+         */
+        reg = core_readl(priv, CORE_BRCM_HDR_TX_DIS);
+        reg &= ~(1 << port);
+        core_writel(priv, reg, CORE_BRCM_HDR_TX_DIS);
+
+        /* Force link status for IMP port */
+        reg = core_readl(priv, CORE_STS_OVERRIDE_IMP);
+        reg |= (MII_SW_OR | LINK_STS);
+        core_writel(priv, reg, CORE_STS_OVERRIDE_IMP);
+
+        /* Enable the IMP Port to be in the same VLAN as the other ports
+         * on a per-port basis such that we only have Port i and IMP in
+         * the same VLAN.
+         */
+        for (i = 0; i < priv->hw_params.num_ports; i++) {
+                if (!((1 << i) & ds->phys_port_mask))
+                        continue;
+
+                reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(i));
+                reg |= (1 << port);
+                core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(i));
+        }
+}
+
+static void bcm_sf2_port_setup(struct dsa_switch *ds, int port)
+{
+        struct bcm_sf2_priv *priv = ds_to_priv(ds);
+        u32 reg;
+
+        /* Clear the memory power down */
+        reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
+        reg &= ~P_TXQ_PSM_VDD(port);
+        core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
+
+        /* Clear the Rx and Tx disable bits and set to no spanning tree */
+        core_writel(priv, 0, CORE_G_PCTL_PORT(port));
+
+        /* Enable port 7 interrupts to get notified */
+        if (port == 7)
+                intrl2_1_mask_clear(priv, P_IRQ_MASK(P7_IRQ_OFF));
+
+        /* Set this port, and only this one to be in the default VLAN */
+        reg = core_readl(priv, CORE_PORT_VLAN_CTL_PORT(port));
+        reg &= ~PORT_VLAN_CTRL_MASK;
+        reg |= (1 << port);
+        core_writel(priv, reg, CORE_PORT_VLAN_CTL_PORT(port));
+}
+
+static void bcm_sf2_port_disable(struct dsa_switch *ds, int port)
+{
+        struct bcm_sf2_priv *priv = ds_to_priv(ds);
+        u32 off, reg;
+
+        if (dsa_is_cpu_port(ds, port))
+                off = CORE_IMP_CTL;
+        else
+                off = CORE_G_PCTL_PORT(port);
+
+        reg = core_readl(priv, off);
+        reg |= RX_DIS | TX_DIS;
+        core_writel(priv, reg, off);
+
+        /* Power down the port memory */
+        reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
+        reg |= P_TXQ_PSM_VDD(port);
+        core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
+}
+
+static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
+{
+        struct bcm_sf2_priv *priv = dev_id;
+
+        priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
+                                ~priv->irq0_mask;
+        intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
+
+        return IRQ_HANDLED;
+}
+
+static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
+{
+        struct bcm_sf2_priv *priv = dev_id;
+
+        priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
+                                ~priv->irq1_mask;
+        intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
+
+        if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF))
+                priv->port_sts[7].link = 1;
+        if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF))
+                priv->port_sts[7].link = 0;
+
+        return IRQ_HANDLED;
+}
+
+static int bcm_sf2_sw_setup(struct dsa_switch *ds)
+{
+        const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
+        struct bcm_sf2_priv *priv = ds_to_priv(ds);
+        struct device_node *dn;
+        void __iomem **base;
+        unsigned int port;
+        unsigned int i;
+        u32 reg, rev;
+        int ret;
+
+        spin_lock_init(&priv->indir_lock);
+        mutex_init(&priv->stats_mutex);
+
+        /* All the interesting properties are at the parent device_node
+         * level
+         */
+        dn = ds->pd->of_node->parent;
+
+        priv->irq0 = irq_of_parse_and_map(dn, 0);
+        priv->irq1 = irq_of_parse_and_map(dn, 1);
+
+        base = &priv->core;
+        for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
+                *base = of_iomap(dn, i);
+                if (*base == NULL) {
+                        pr_err("unable to find register: %s\n", reg_names[i]);
+                        return -ENODEV;
+                }
+                base++;
+        }
+
+        /* Disable all interrupts and request them */
+        intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
+        intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+        intrl2_0_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+        intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_MASK_SET);
+        intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
+        intrl2_1_writel(priv, 0, INTRL2_CPU_MASK_CLEAR);
+
+        ret = request_irq(priv->irq0, bcm_sf2_switch_0_isr, 0,
+                          "switch_0", priv);
+        if (ret < 0) {
+                pr_err("failed to request switch_0 IRQ\n");
+                goto out_unmap;
+        }
+
+        ret = request_irq(priv->irq1, bcm_sf2_switch_1_isr, 0,
+                          "switch_1", priv);
+        if (ret < 0) {
+                pr_err("failed to request switch_1 IRQ\n");
+                goto out_free_irq0;
+        }
+
+        /* Reset the MIB counters */
+        reg = core_readl(priv, CORE_GMNCFGCFG);
+        reg |= RST_MIB_CNT;
+        core_writel(priv, reg, CORE_GMNCFGCFG);
+        reg &= ~RST_MIB_CNT;
+        core_writel(priv, reg, CORE_GMNCFGCFG);
+
+        /* Get the maximum number of ports for this switch */
+        priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
+        if (priv->hw_params.num_ports > DSA_MAX_PORTS)
+                priv->hw_params.num_ports = DSA_MAX_PORTS;
+
+        /* Assume a single GPHY setup if we can't read that property */
+        if (of_property_read_u32(dn, "brcm,num-gphy",
+                                 &priv->hw_params.num_gphy))
+                priv->hw_params.num_gphy = 1;
+
+        /* Enable all valid ports and disable those unused */
+        for (port = 0; port < priv->hw_params.num_ports; port++) {
+                /* IMP port receives special treatment */
+                if ((1 << port) & ds->phys_port_mask)
+                        bcm_sf2_port_setup(ds, port);
+                else if (dsa_is_cpu_port(ds, port))
+                        bcm_sf2_imp_setup(ds, port);
+                else
+                        bcm_sf2_port_disable(ds, port);
+        }
+
+        /* Include the pseudo-PHY address and the broadcast PHY address to
+         * divert reads towards our workaround
+         */
+        ds->phys_mii_mask |= ((1 << 30) | (1 << 0));
+
+        rev = reg_readl(priv, REG_SWITCH_REVISION);
+        priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
+                                        SWITCH_TOP_REV_MASK;
+        priv->hw_params.core_rev = (rev & SF2_REV_MASK);
+
+        pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
+                priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
+                priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
+                priv->core, priv->irq0, priv->irq1);
+
+        return 0;
+
+out_free_irq0:
+        free_irq(priv->irq0, priv);
+out_unmap:
+        base = &priv->core;
+        for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
+                iounmap(*base);
+                base++;
+        }
+        return ret;
+}
+
+static int bcm_sf2_sw_set_addr(struct dsa_switch *ds, u8 *addr)
+{
+        return 0;
+}
+
+static int bcm_sf2_sw_indir_rw(struct dsa_switch *ds, int op, int addr,
+                               int regnum, u16 val)
+{
+        struct bcm_sf2_priv *priv = ds_to_priv(ds);
+        int ret = 0;
+        u32 reg;
+
+        reg = reg_readl(priv, REG_SWITCH_CNTRL);
+        reg |= MDIO_MASTER_SEL;
+        reg_writel(priv, reg, REG_SWITCH_CNTRL);
+
+        /* Page << 8 | offset */
+        reg = 0x70;
+        reg <<= 2;
+        core_writel(priv, addr, reg);
+
+        /* Page << 8 | offset */
+        reg = 0x80 << 8 | regnum << 1;
+        reg <<= 2;
+
+        if (op)
+                ret = core_readl(priv, reg);
+        else
+                core_writel(priv, val, reg);
+
+        reg = reg_readl(priv, REG_SWITCH_CNTRL);
+        reg &= ~MDIO_MASTER_SEL;
+        reg_writel(priv, reg, REG_SWITCH_CNTRL);
+
+        return ret & 0xffff;
+}
+
+static int bcm_sf2_sw_phy_read(struct dsa_switch *ds, int addr, int regnum)
+{
+        /* Intercept reads from the MDIO broadcast address or Broadcom
+         * pseudo-PHY address
+         */
+        switch (addr) {
+        case 0:
+        case 30:
+                return bcm_sf2_sw_indir_rw(ds, 1, addr, regnum, 0);
+        default:
+                return 0xffff;
+        }
+}
+
+static int bcm_sf2_sw_phy_write(struct dsa_switch *ds, int addr, int regnum,
+                                u16 val)
+{
+        /* Intercept writes to the MDIO broadcast address or Broadcom
+         * pseudo-PHY address
+         */
+        switch (addr) {
+        case 0:
+        case 30:
+                bcm_sf2_sw_indir_rw(ds, 0, addr, regnum, val);
+                break;
+        }
+
+        return 0;
+}
+
+static void bcm_sf2_sw_adjust_link(struct dsa_switch *ds, int port,
+                                   struct phy_device *phydev)
+{
+        struct bcm_sf2_priv *priv = ds_to_priv(ds);
+        u32 id_mode_dis = 0, port_mode;
+        const char *str = NULL;
+        u32 reg;
+
+        switch (phydev->interface) {
+        case PHY_INTERFACE_MODE_RGMII:
+                str = "RGMII (no delay)";
+                id_mode_dis = 1;
+        case PHY_INTERFACE_MODE_RGMII_TXID:
+                if (!str)
+                        str = "RGMII (TX delay)";
+                port_mode = EXT_GPHY;
+                break;
+        case PHY_INTERFACE_MODE_MII:
+                str = "MII";
+                port_mode = EXT_EPHY;
+                break;
+        case PHY_INTERFACE_MODE_REVMII:
+                str = "Reverse MII";
+                port_mode = EXT_REVMII;
+                break;
+        default:
+                goto force_link;
+        }
+
+        /* Clear id_mode_dis bit, and the existing port mode, but
+         * make sure we enable the RGMII block for data to pass
+         */
+        reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
+        reg &= ~ID_MODE_DIS;
+        reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
+        reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
+
+        reg |= port_mode | RGMII_MODE_EN;
+        if (id_mode_dis)
+                reg |= ID_MODE_DIS;
+
+        if (phydev->pause) {
+                if (phydev->asym_pause)
+                        reg |= TX_PAUSE_EN;
+                reg |= RX_PAUSE_EN;
+        }
+
+        reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
+
+        pr_info("Port %d configured for %s\n", port, str);
+
+force_link:
+        /* Force link settings detected from the PHY */
+        reg = SW_OVERRIDE;
+        switch (phydev->speed) {
+        case SPEED_1000:
+                reg |= SPDSTS_1000 << SPEED_SHIFT;
+                break;
+        case SPEED_100:
+                reg |= SPDSTS_100 << SPEED_SHIFT;
+                break;
+        }
+
+        if (phydev->link)
+                reg |= LINK_STS;
+        if (phydev->duplex == DUPLEX_FULL)
+                reg |= DUPLX_MODE;
+
+        core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(port));
+}
+
+static void bcm_sf2_sw_fixed_link_update(struct dsa_switch *ds, int port,
+                                         struct fixed_phy_status *status)
+{
+        struct bcm_sf2_priv *priv = ds_to_priv(ds);
+        u32 link, duplex, pause, speed;
+        u32 reg;
+
+        link = core_readl(priv, CORE_LNKSTS);
+        duplex = core_readl(priv, CORE_DUPSTS);
+        pause = core_readl(priv, CORE_PAUSESTS);
+        speed = core_readl(priv, CORE_SPDSTS);
+
+        speed >>= (port * SPDSTS_SHIFT);
+        speed &= SPDSTS_MASK;
+
+        status->link = 0;
+
+        /* Port 7 is special as we do not get link status from CORE_LNKSTS,
+         * which means that we need to force the link at the port override
+         * level to get the data to flow. We do use what the interrupt handler
+         * did determine before.
+         */
+        if (port == 7) {
+                status->link = priv->port_sts[port].link;
+                reg = core_readl(priv, CORE_STS_OVERRIDE_GMIIP_PORT(7));
+                reg |= SW_OVERRIDE;
+                if (status->link)
+                        reg |= LINK_STS;
+                else
+                        reg &= ~LINK_STS;
+                core_writel(priv, reg, CORE_STS_OVERRIDE_GMIIP_PORT(7));
+                status->duplex = 1;
+        } else {
+                status->link = !!(link & (1 << port));
+                status->duplex = !!(duplex & (1 << port));
+        }
+
+        switch (speed) {
+        case SPDSTS_10:
+                status->speed = SPEED_10;
+                break;
+        case SPDSTS_100:
+                status->speed = SPEED_100;
+                break;
+        case SPDSTS_1000:
+                status->speed = SPEED_1000;
+                break;
+        }
+
+        if ((pause & (1 << port)) &&
+            (pause & (1 << (port + PAUSESTS_TX_PAUSE_SHIFT)))) {
+                status->asym_pause = 1;
+                status->pause = 1;
+        }
+
+        if (pause & (1 << port))
+                status->pause = 1;
+}
+
+static struct dsa_switch_driver bcm_sf2_switch_driver = {
+        .tag_protocol           = htons(ETH_P_BRCMTAG),
+        .priv_size              = sizeof(struct bcm_sf2_priv),
+        .probe                  = bcm_sf2_sw_probe,
+        .setup                  = bcm_sf2_sw_setup,
+        .set_addr               = bcm_sf2_sw_set_addr,
+        .phy_read               = bcm_sf2_sw_phy_read,
+        .phy_write              = bcm_sf2_sw_phy_write,
+        .get_strings            = bcm_sf2_sw_get_strings,
+        .get_ethtool_stats      = bcm_sf2_sw_get_ethtool_stats,
+        .get_sset_count         = bcm_sf2_sw_get_sset_count,
+        .adjust_link            = bcm_sf2_sw_adjust_link,
+        .fixed_link_update      = bcm_sf2_sw_fixed_link_update,
+};
+
+static int __init bcm_sf2_init(void)
+{
+        register_switch_driver(&bcm_sf2_switch_driver);
+
+        return 0;
+}
+module_init(bcm_sf2_init);
+
+static void __exit bcm_sf2_exit(void)
+{
+        unregister_switch_driver(&bcm_sf2_switch_driver);
+}
+module_exit(bcm_sf2_exit);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:brcm-sf2");
diff --git a/drivers/net/dsa/bcm_sf2.h b/drivers/net/dsa/bcm_sf2.h
new file mode 100644
index 000000000000..260bab313e58
--- /dev/null
+++ b/drivers/net/dsa/bcm_sf2.h
@@ -0,0 +1,140 @@
+/*
+ * Broadcom Starfighter2 private context
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __BCM_SF2_H
+#define __BCM_SF2_H
+
+#include <linux/platform_device.h>
+#include <linux/kernel.h>
+#include <linux/io.h>
+#include <linux/spinlock.h>
+#include <linux/mutex.h>
+#include <linux/mii.h>
+
+#include <net/dsa.h>
+
+#include "bcm_sf2_regs.h"
+
+struct bcm_sf2_hw_params {
+        u16     top_rev;
+        u16     core_rev;
+        u32     num_gphy;
+        u8      num_acb_queue;
+        u8      num_rgmii;
+        u8      num_ports;
+        u8      fcb_pause_override:1;
+        u8      acb_packets_inflight:1;
+};
+
+#define BCM_SF2_REGS_NAME {\
+        "core", "reg", "intrl2_0", "intrl2_1", "fcb", "acb" \
+}
+
+#define BCM_SF2_REGS_NUM        6
+
+struct bcm_sf2_port_status {
+        unsigned int link;
+};
+
+struct bcm_sf2_priv {
+        /* Base registers, keep those in order with BCM_SF2_REGS_NAME */
+        void __iomem                    *core;
+        void __iomem                    *reg;
+        void __iomem                    *intrl2_0;
+        void __iomem                    *intrl2_1;
+        void __iomem                    *fcb;
+        void __iomem                    *acb;
+
+        /* spinlock protecting access to the indirect registers */
+        spinlock_t                      indir_lock;
+
+        int                             irq0;
+        int                             irq1;
+        u32                             irq0_stat;
+        u32                             irq0_mask;
+        u32                             irq1_stat;
+        u32                             irq1_mask;
+
+        /* Mutex protecting access to the MIB counters */
+        struct mutex                    stats_mutex;
+
+        struct bcm_sf2_hw_params        hw_params;
+
+        struct bcm_sf2_port_status      port_sts[DSA_MAX_PORTS];
+};
+
+struct bcm_sf2_hw_stats {
+        const char      *string;
+        u16             reg;
+        u8              sizeof_stat;
+};
+
+#define SF2_IO_MACRO(name) \
+static inline u32 name##_readl(struct bcm_sf2_priv *priv, u32 off)      \
+{                                                                       \
+        return __raw_readl(priv->name + off);                           \
+}                                                                       \
+static inline void name##_writel(struct bcm_sf2_priv *priv,             \
+                                  u32 val, u32 off)                     \
+{                                                                       \
+        __raw_writel(val, priv->name + off);                            \
+}                                                                       \
+
+/* Accesses to 64-bits register requires us to latch the hi/lo pairs
+ * using the REG_DIR_DATA_{READ,WRITE} ancillary registers. The 'indir_lock'
+ * spinlock is automatically grabbed and released to provide relative
+ * atomiticy with latched reads/writes.
+ */
+#define SF2_IO64_MACRO(name) \
+static inline u64 name##_readq(struct bcm_sf2_priv *priv, u32 off)      \
+{                                                                       \
+        u32 indir, dir;                                                 \
+        spin_lock(&priv->indir_lock);                                   \
+        indir = reg_readl(priv, REG_DIR_DATA_READ);                     \
+        dir = __raw_readl(priv->name + off);                            \
+        spin_unlock(&priv->indir_lock);                                 \
+        return (u64)indir << 32 | dir;                                  \
+}                                                                       \
+static inline void name##_writeq(struct bcm_sf2_priv *priv, u32 off,    \
+                                                        u64 val)        \
+{                                                                       \
+        spin_lock(&priv->indir_lock);                                   \
+        reg_writel(priv, upper_32_bits(val), REG_DIR_DATA_WRITE);       \
+        __raw_writel(lower_32_bits(val), priv->name + off);             \
+        spin_unlock(&priv->indir_lock);                                 \
+}
+
+#define SWITCH_INTR_L2(which)                                           \
+static inline void intrl2_##which##_mask_clear(struct bcm_sf2_priv *priv, \
+                                                u32 mask)               \
+{                                                                       \
+        intrl2_##which##_writel(priv, mask, INTRL2_CPU_MASK_CLEAR);     \
+        priv->irq##which##_mask &= ~(mask);                             \
+}                                                                       \
+static inline void intrl2_##which##_mask_set(struct bcm_sf2_priv *priv, \
+                                                u32 mask)               \
+{                                                                       \
+        intrl2_## which##_writel(priv, mask, INTRL2_CPU_MASK_SET);      \
+        priv->irq##which##_mask |= (mask);                              \
+}                                                                       \
+
+SF2_IO_MACRO(core);
+SF2_IO_MACRO(reg);
+SF2_IO64_MACRO(core);
+SF2_IO_MACRO(intrl2_0);
+SF2_IO_MACRO(intrl2_1);
+SF2_IO_MACRO(fcb);
+SF2_IO_MACRO(acb);
+
+SWITCH_INTR_L2(0);
+SWITCH_INTR_L2(1);
+
+#endif /* __BCM_SF2_H */
diff --git a/drivers/net/dsa/bcm_sf2_regs.h b/drivers/net/dsa/bcm_sf2_regs.h
new file mode 100644
index 000000000000..885c231b03b5
--- /dev/null
+++ b/drivers/net/dsa/bcm_sf2_regs.h
@@ -0,0 +1,227 @@
+/*
+ * Broadcom Starfighter 2 switch register defines
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+#ifndef __BCM_SF2_REGS_H
+#define __BCM_SF2_REGS_H
+
+/* Register set relative to 'REG' */
+#define REG_SWITCH_CNTRL                0x00
+#define  MDIO_MASTER_SEL                (1 << 0)
+
+#define REG_SWITCH_STATUS               0x04
+#define REG_DIR_DATA_WRITE              0x08
+#define REG_DIR_DATA_READ               0x0C
+
+#define REG_SWITCH_REVISION             0x18
+#define  SF2_REV_MASK                   0xffff
+#define  SWITCH_TOP_REV_SHIFT           16
+#define  SWITCH_TOP_REV_MASK            0xffff
+
+#define REG_PHY_REVISION                0x1C
+
+#define REG_SPHY_CNTRL                  0x2C
+#define  IDDQ_BIAS                      (1 << 0)
+#define  EXT_PWR_DOWN                   (1 << 1)
+#define  FORCE_DLL_EN                   (1 << 2)
+#define  IDDQ_GLOBAL_PWR                (1 << 3)
+#define  CK25_DIS                       (1 << 4)
+#define  PHY_RESET                      (1 << 5)
+#define  PHY_PHYAD_SHIFT                8
+#define  PHY_PHYAD_MASK                 0x1F
+
+#define REG_RGMII_0_BASE                0x34
+#define REG_RGMII_CNTRL                 0x00
+#define REG_RGMII_IB_STATUS             0x04
+#define REG_RGMII_RX_CLOCK_DELAY_CNTRL  0x08
+#define REG_RGMII_CNTRL_SIZE            0x0C
+#define REG_RGMII_CNTRL_P(x)            (REG_RGMII_0_BASE + \
+                                        ((x) * REG_RGMII_CNTRL_SIZE))
+/* Relative to REG_RGMII_CNTRL */
+#define  RGMII_MODE_EN                  (1 << 0)
+#define  ID_MODE_DIS                    (1 << 1)
+#define  PORT_MODE_SHIFT                2
+#define  INT_EPHY                       (0 << PORT_MODE_SHIFT)
+#define  INT_GPHY                       (1 << PORT_MODE_SHIFT)
+#define  EXT_EPHY                       (2 << PORT_MODE_SHIFT)
+#define  EXT_GPHY                       (3 << PORT_MODE_SHIFT)
+#define  EXT_REVMII                     (4 << PORT_MODE_SHIFT)
+#define  PORT_MODE_MASK                 0x7
+#define  RVMII_REF_SEL                  (1 << 5)
+#define  RX_PAUSE_EN                    (1 << 6)
+#define  TX_PAUSE_EN                    (1 << 7)
+#define  TX_CLK_STOP_EN                 (1 << 8)
+#define  LPI_COUNT_SHIFT                9
+#define  LPI_COUNT_MASK                 0x3F
+
+/* Register set relative to 'INTRL2_0' and 'INTRL2_1' */
+#define INTRL2_CPU_STATUS               0x00
+#define INTRL2_CPU_SET                  0x04
+#define INTRL2_CPU_CLEAR                0x08
+#define INTRL2_CPU_MASK_STATUS          0x0c
+#define INTRL2_CPU_MASK_SET             0x10
+#define INTRL2_CPU_MASK_CLEAR           0x14
+
+/* Shared INTRL2_0 and INTRL2_ interrupt sources macros */
+#define P_LINK_UP_IRQ(x)                (1 << (0 + (x)))
+#define P_LINK_DOWN_IRQ(x)              (1 << (1 + (x)))
+#define P_ENERGY_ON_IRQ(x)              (1 << (2 + (x)))
+#define P_ENERGY_OFF_IRQ(x)             (1 << (3 + (x)))
+#define P_GPHY_IRQ(x)                   (1 << (4 + (x)))
+#define P_NUM_IRQ                       5
+#define P_IRQ_MASK(x)                   (P_LINK_UP_IRQ((x)) | \
+                                         P_LINK_DOWN_IRQ((x)) | \
+                                         P_ENERGY_ON_IRQ((x)) | \
+                                         P_ENERGY_OFF_IRQ((x)) | \
+                                         P_GPHY_IRQ((x)))
+
+/* INTRL2_0 interrupt sources */
+#define P0_IRQ_OFF                      0
+#define MEM_DOUBLE_IRQ                  (1 << 5)
+#define EEE_LPI_IRQ                     (1 << 6)
+#define P5_CPU_WAKE_IRQ                 (1 << 7)
+#define P8_CPU_WAKE_IRQ                 (1 << 8)
+#define P7_CPU_WAKE_IRQ                 (1 << 9)
+#define IEEE1588_IRQ                    (1 << 10)
+#define MDIO_ERR_IRQ                    (1 << 11)
+#define MDIO_DONE_IRQ                   (1 << 12)
+#define GISB_ERR_IRQ                    (1 << 13)
+#define UBUS_ERR_IRQ                    (1 << 14)
+#define FAILOVER_ON_IRQ                 (1 << 15)
+#define FAILOVER_OFF_IRQ                (1 << 16)
+#define TCAM_SOFT_ERR_IRQ               (1 << 17)
+
+/* INTRL2_1 interrupt sources */
+#define P7_IRQ_OFF                      0
+#define P_IRQ_OFF(x)                    ((6 - (x)) * P_NUM_IRQ)
+
+/* Register set relative to 'CORE' */
+#define CORE_G_PCTL_PORT0               0x00000
+#define CORE_G_PCTL_PORT(x)             (CORE_G_PCTL_PORT0 + (x * 0x4))
+#define CORE_IMP_CTL                    0x00020
+#define  RX_DIS                         (1 << 0)
+#define  TX_DIS                         (1 << 1)
+#define  RX_BCST_EN                     (1 << 2)
+#define  RX_MCST_EN                     (1 << 3)
+#define  RX_UCST_EN                     (1 << 4)
+#define  G_MISTP_STATE_SHIFT            5
+#define  G_MISTP_NO_STP                 (0 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_DIS_STATE              (1 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_BLOCK_STATE            (2 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_LISTEN_STATE           (3 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_LEARN_STATE            (4 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_FWD_STATE              (5 << G_MISTP_STATE_SHIFT)
+#define  G_MISTP_STATE_MASK             0x7
+
+#define CORE_SWMODE                     0x0002c
+#define  SW_FWDG_MODE                   (1 << 0)
+#define  SW_FWDG_EN                     (1 << 1)
+#define  RTRY_LMT_DIS                   (1 << 2)
+
+#define CORE_STS_OVERRIDE_IMP           0x00038
+#define  GMII_SPEED_UP_2G               (1 << 6)
+#define  MII_SW_OR                      (1 << 7)
+
+#define CORE_NEW_CTRL                   0x00084
+#define  IP_MC                          (1 << 0)
+#define  OUTRANGEERR_DISCARD            (1 << 1)
+#define  INRANGEERR_DISCARD             (1 << 2)
+#define  CABLE_DIAG_LEN                 (1 << 3)
+#define  OVERRIDE_AUTO_PD_WAR           (1 << 4)
+#define  EN_AUTO_PD_WAR                 (1 << 5)
+#define  UC_FWD_EN                      (1 << 6)
+#define  MC_FWD_EN                      (1 << 7)
+
+#define CORE_SWITCH_CTRL                0x00088
+#define  MII_DUMB_FWDG_EN               (1 << 6)
+
+#define CORE_SFT_LRN_CTRL               0x000f8
+#define  SW_LEARN_CNTL(x)               (1 << (x))
+
+#define CORE_STS_OVERRIDE_GMIIP_PORT(x) (0x160 + (x) * 4)
+#define  LINK_STS                       (1 << 0)
+#define  DUPLX_MODE                     (1 << 1)
+#define  SPEED_SHIFT                    2
+#define  SPEED_MASK                     0x3
+#define  RXFLOW_CNTL                    (1 << 4)
+#define  TXFLOW_CNTL                    (1 << 5)
+#define  SW_OVERRIDE                    (1 << 6)
+
+#define CORE_WATCHDOG_CTRL              0x001e4
+#define  SOFTWARE_RESET                 (1 << 7)
+#define  EN_CHIP_RST                    (1 << 6)
+#define  EN_SW_RESET                    (1 << 4)
+
+#define CORE_LNKSTS                     0x00400
+#define  LNK_STS_MASK                   0x1ff
+
+#define CORE_SPDSTS                     0x00410
+#define  SPDSTS_10                      0
+#define  SPDSTS_100                     1
+#define  SPDSTS_1000                    2
+#define  SPDSTS_SHIFT                   2
+#define  SPDSTS_MASK                    0x3
+
+#define CORE_DUPSTS                     0x00420
+#define  CORE_DUPSTS_MASK               0x1ff
+
+#define CORE_PAUSESTS                   0x00428
+#define  PAUSESTS_TX_PAUSE_SHIFT        9
+
+#define CORE_GMNCFGCFG                  0x0800
+#define  RST_MIB_CNT                    (1 << 0)
+#define  RXBPDU_EN                      (1 << 1)
+
+#define CORE_IMP0_PRT_ID                0x0804
+
+#define CORE_BRCM_HDR_CTRL              0x0080c
+#define  BRCM_HDR_EN_P8                 (1 << 0)
+#define  BRCM_HDR_EN_P5                 (1 << 1)
+#define  BRCM_HDR_EN_P7                 (1 << 2)
+
+#define CORE_BRCM_HDR_CTRL2             0x0828
+
+#define CORE_HL_PRTC_CTRL               0x0940
+#define  ARP_EN                         (1 << 0)
+#define  RARP_EN                        (1 << 1)
+#define  DHCP_EN                        (1 << 2)
+#define  ICMPV4_EN                      (1 << 3)
+#define  ICMPV6_EN                      (1 << 4)
+#define  ICMPV6_FWD_MODE                (1 << 5)
+#define  IGMP_DIP_EN                    (1 << 8)
+#define  IGMP_RPTLVE_EN                 (1 << 9)
+#define  IGMP_RTPLVE_FWD_MODE           (1 << 10)
+#define  IGMP_QRY_EN                    (1 << 11)
+#define  IGMP_QRY_FWD_MODE              (1 << 12)
+#define  IGMP_UKN_EN                    (1 << 13)
+#define  IGMP_UKN_FWD_MODE              (1 << 14)
+#define  MLD_RPTDONE_EN                 (1 << 15)
+#define  MLD_RPTDONE_FWD_MODE           (1 << 16)
+#define  MLD_QRY_EN                     (1 << 17)
+#define  MLD_QRY_FWD_MODE               (1 << 18)
+
+#define CORE_RST_MIB_CNT_EN             0x0950
+
+#define CORE_BRCM_HDR_RX_DIS            0x0980
+#define CORE_BRCM_HDR_TX_DIS            0x0988
+
+#define CORE_MEM_PSM_VDD_CTRL           0x2380
+#define  P_TXQ_PSM_VDD_SHIFT            2
+#define  P_TXQ_PSM_VDD_MASK             0x3
+#define  P_TXQ_PSM_VDD(x)               (P_TXQ_PSM_VDD_MASK << \
+                                        ((x) * P_TXQ_PSM_VDD_SHIFT))
+
+#define CORE_P0_MIB_OFFSET              0x8000
+#define P_MIB_SIZE                      0x400
+#define CORE_P_MIB_OFFSET(x)            (CORE_P0_MIB_OFFSET + (x) * P_MIB_SIZE)
+
+#define CORE_PORT_VLAN_CTL_PORT(x)      (0xc400 + ((x) * 0x8))
+#define  PORT_VLAN_CTRL_MASK            0x1ff
+
+#endif /* __BCM_SF2_REGS_H */
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-common.h b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
index cc25a3a9e7cf..caade30820d5 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-common.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-common.h
@@ -271,7 +271,6 @@
 #define DMA_PBL_X8_DISABLE              0x00
 #define DMA_PBL_X8_ENABLE               0x01
 
-
 /* MAC register offsets */
 #define MAC_TCR                         0x0000
 #define MAC_RCR                         0x0004
@@ -792,7 +791,6 @@
 #define MTL_Q_DISABLED                  0x00
 #define MTL_Q_ENABLED                   0x02
 
-
 /* MTL traffic class register offsets
  *   Multiple traffic classes can be active.  The first class has registers
  *   that begin at 0x1100.  Each subsequent queue has registers that
@@ -815,7 +813,6 @@
 #define MTL_TSA_SP                      0x00
 #define MTL_TSA_ETS                     0x02
 
-
 /* PCS MMD select register offset
  *  The MMD select register is used for accessing PCS registers
  *  when the underlying APB3 interface is using indirect addressing.
@@ -825,7 +822,6 @@
  */
 #define PCS_MMD_SELECT                  0xff
 
-
 /* Descriptor/Packet entry bit positions and sizes */
 #define RX_PACKET_ERRORS_CRC_INDEX              2
 #define RX_PACKET_ERRORS_CRC_WIDTH              1
@@ -929,7 +925,6 @@
 #define MDIO_AN_COMP_STAT               0x0030
 #endif
 
-
 /* Bit setting and getting macros
  *  The get macro will extract the current bit field value from within
  *  the variable
@@ -957,7 +952,6 @@ do {									\
                               ((0x1 << (_width)) - 1)) << (_index)));   \
 } while (0)
 
-
 /* Bit setting and getting macros based on register fields
  *  The get macro uses the bit field definitions formed using the input
  *  names to extract the current bit field value from within the
@@ -986,7 +980,6 @@ do {									\
                  _prefix##_##_field##_INDEX,                            \
                  _prefix##_##_field##_WIDTH, (_val))
 
-
 /* Macros for reading or writing registers
  *  The ioread macros will get bit fields or full values using the
  *  register definitions formed using the input names
@@ -1014,7 +1007,6 @@ do {									\
         XGMAC_IOWRITE((_pdata), _reg, reg_val);                         \
 } while (0)
 
-
 /* Macros for reading or writing MTL queue or traffic class registers
  *  Similar to the standard read and write macros except that the
  *  base register value is calculated by the queue or traffic class number
@@ -1041,7 +1033,6 @@ do {									\
         XGMAC_MTL_IOWRITE((_pdata), (_n), _reg, reg_val);               \
 } while (0)
 
-
 /* Macros for reading or writing DMA channel registers
  *  Similar to the standard read and write macros except that the
  *  base register value is obtained from the ring
@@ -1066,7 +1057,6 @@ do {									\
         XGMAC_DMA_IOWRITE((_channel), _reg, reg_val);                   \
 } while (0)
 
-
 /* Macros for building, reading or writing register values or bits
  * within the register values of XPCS registers.
  */
@@ -1076,7 +1066,6 @@ do {									\
 #define XPCS_IOREAD(_pdata, _off)                                       \
         ioread32((_pdata)->xpcs_regs + (_off))
 
-
 /* Macros for building, reading or writing register values or bits
  * using MDIO.  Different from above because of the use of standardized
  * Linux include values.  No shifting is performed with the bit
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c b/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c
index 7d6a49b24321..8a50b01c2686 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dcb.c
@@ -120,7 +120,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 static int xgbe_dcb_ieee_getets(struct net_device *netdev,
                                 struct ieee_ets *ets)
 {
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c b/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c
index a3c11355a34d..76479d04b903 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-debugfs.c
@@ -121,7 +121,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 static ssize_t xgbe_common_read(char __user *buffer, size_t count,
                                 loff_t *ppos, unsigned int value)
 {
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c
index 1c5d62e8dab6..6fc5da01437d 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-desc.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-desc.c
@@ -117,7 +117,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 static void xgbe_unmap_skb(struct xgbe_prv_data *, struct xgbe_ring_data *);
 
 static void xgbe_free_ring(struct xgbe_prv_data *pdata,
@@ -524,11 +523,8 @@ static void xgbe_realloc_skb(struct xgbe_channel *channel)
 
                 /* Allocate skb & assign to each rdesc */
                 skb = dev_alloc_skb(pdata->rx_buf_size);
-                if (skb == NULL) {
-                        netdev_alert(pdata->netdev,
-                                     "failed to allocate skb\n");
+                if (skb == NULL)
                         break;
-                }
                 skb_dma = dma_map_single(pdata->dev, skb->data,
                                          pdata->rx_buf_size, DMA_FROM_DEVICE);
                 if (dma_mapping_error(pdata->dev, skb_dma)) {
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
index ea273836d999..9da3a03e8c07 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-dev.c
@@ -122,7 +122,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 static unsigned int xgbe_usec_to_riwt(struct xgbe_prv_data *pdata,
                                       unsigned int usec)
 {
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
index b26d75856553..29554992215a 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-drv.c
@@ -126,7 +126,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 static int xgbe_poll(struct napi_struct *, int);
 static void xgbe_set_rx_mode(struct net_device *);
 
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c
index 46f613028e9c..49508ec98b72 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-ethtool.c
@@ -121,7 +121,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 struct xgbe_stats {
         char stat_string[ETH_GSTRING_LEN];
         int stat_size;
@@ -173,6 +172,7 @@ static const struct xgbe_stats xgbe_gstring_stats[] = {
         XGMAC_MMC_STAT("rx_watchdog_errors", rxwatchdogerror),
         XGMAC_MMC_STAT("rx_pause_frames", rxpauseframes),
 };
+
 #define XGBE_STATS_COUNT        ARRAY_SIZE(xgbe_gstring_stats)
 
 static void xgbe_get_strings(struct net_device *netdev, u32 stringset, u8 *data)
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-main.c b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
index bdf9cfa70e88..f5a8fa03921a 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-main.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-main.c
@@ -128,7 +128,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
 MODULE_LICENSE("Dual BSD/GPL");
 MODULE_VERSION(XGBE_DRV_VERSION);
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
index 6d2221e023f4..363b210560f3 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-mdio.c
@@ -123,7 +123,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 static int xgbe_mdio_read(struct mii_bus *mii, int prtad, int mmd_reg)
 {
         struct xgbe_prv_data *pdata = mii->priv;
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c b/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
index 37e64cfa5718..a1bf9d1cdae1 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
+++ b/drivers/net/ethernet/amd/xgbe/xgbe-ptp.c
@@ -122,7 +122,6 @@
 #include "xgbe.h"
 #include "xgbe-common.h"
 
-
 static cycle_t xgbe_cc_read(const struct cyclecounter *cc)
 {
         struct xgbe_prv_data *pdata = container_of(cc,
diff --git a/drivers/net/ethernet/amd/xgbe/xgbe.h b/drivers/net/ethernet/amd/xgbe/xgbe.h
index e9fe6e6ddcc3..789957d43a13 100644
--- a/drivers/net/ethernet/amd/xgbe/xgbe.h
+++ b/drivers/net/ethernet/amd/xgbe/xgbe.h
@@ -128,7 +128,6 @@
 #include <linux/net_tstamp.h>
 #include <net/dcbnl.h>
 
-
 #define XGBE_DRV_NAME           "amd-xgbe"
 #define XGBE_DRV_VERSION        "1.0.0-a"
 #define XGBE_DRV_DESC           "AMD 10 Gigabit Ethernet Driver"
@@ -199,7 +198,6 @@
         ((_ring)->rdata +                                       \
          ((_idx) & ((_ring)->rdesc_count - 1)))
 
-
 /* Default coalescing parameters */
 #define XGMAC_INIT_DMA_TX_USECS         50
 #define XGMAC_INIT_DMA_TX_FRAMES        25
diff --git a/drivers/net/ethernet/arc/Kconfig b/drivers/net/ethernet/arc/Kconfig
index 514c57fd26f1..89e04fde5f4e 100644
--- a/drivers/net/ethernet/arc/Kconfig
+++ b/drivers/net/ethernet/arc/Kconfig
@@ -17,10 +17,14 @@ config NET_VENDOR_ARC
 
 if NET_VENDOR_ARC
 
-config ARC_EMAC
-        tristate "ARC EMAC support"
+config ARC_EMAC_CORE
+        tristate
         select MII
         select PHYLIB
+
+config ARC_EMAC
+        tristate "ARC EMAC support"
+        select ARC_EMAC_CORE
         depends on OF_IRQ
         depends on OF_NET
         ---help---
diff --git a/drivers/net/ethernet/arc/Makefile b/drivers/net/ethernet/arc/Makefile
index 00c8657637d5..241bb809f351 100644
--- a/drivers/net/ethernet/arc/Makefile
+++ b/drivers/net/ethernet/arc/Makefile
@@ -3,4 +3,5 @@
 #
 
 arc_emac-objs := emac_main.o emac_mdio.o
-obj-$(CONFIG_ARC_EMAC) += arc_emac.o
+obj-$(CONFIG_ARC_EMAC_CORE) += arc_emac.o
+obj-$(CONFIG_ARC_EMAC) += emac_arc.o
diff --git a/drivers/net/ethernet/arc/emac.h b/drivers/net/ethernet/arc/emac.h
index 36cc9bd07c47..eb2ba67ac711 100644
--- a/drivers/net/ethernet/arc/emac.h
+++ b/drivers/net/ethernet/arc/emac.h
@@ -124,6 +124,8 @@ struct buffer_state {
  */
 struct arc_emac_priv {
         /* Devices */
+        const char *drv_name;
+        const char *drv_version;
         struct device *dev;
         struct phy_device *phy_dev;
         struct mii_bus *bus;
@@ -204,7 +206,9 @@ static inline void arc_reg_clr(struct arc_emac_priv *priv, int reg, int mask)
         arc_reg_set(priv, reg, value & ~mask);
 }
 
-int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv);
+int arc_mdio_probe(struct arc_emac_priv *priv);
 int arc_mdio_remove(struct arc_emac_priv *priv);
+int arc_emac_probe(struct net_device *ndev, int interface);
+int arc_emac_remove(struct net_device *ndev);
 
 #endif /* ARC_EMAC_H */
diff --git a/drivers/net/ethernet/arc/emac_arc.c b/drivers/net/ethernet/arc/emac_arc.c
new file mode 100644
index 000000000000..f9cb99bfb511
--- /dev/null
+++ b/drivers/net/ethernet/arc/emac_arc.c
@@ -0,0 +1,95 @@
+/**
+ * emac_arc.c - ARC EMAC specific glue layer
+ *
+ * Copyright (C) 2014 Romain Perier
+ *
+ * Romain Perier  <romain.perier@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/etherdevice.h>
+#include <linux/module.h>
+#include <linux/of_net.h>
+#include <linux/platform_device.h>
+
+#include "emac.h"
+
+#define DRV_NAME    "emac_arc"
+#define DRV_VERSION "1.0"
+
+static int emac_arc_probe(struct platform_device *pdev)
+{
+        struct device *dev = &pdev->dev;
+        struct net_device *ndev;
+        struct arc_emac_priv *priv;
+        int interface, err;
+
+        if (!dev->of_node)
+                return -ENODEV;
+
+        ndev = alloc_etherdev(sizeof(struct arc_emac_priv));
+        if (!ndev)
+                return -ENOMEM;
+        platform_set_drvdata(pdev, ndev);
+        SET_NETDEV_DEV(ndev, dev);
+
+        priv = netdev_priv(ndev);
+        priv->drv_name = DRV_NAME;
+        priv->drv_version = DRV_VERSION;
+
+        interface = of_get_phy_mode(dev->of_node);
+        if (interface < 0)
+                interface = PHY_INTERFACE_MODE_MII;
+
+        priv->clk = devm_clk_get(dev, "hclk");
+        if (IS_ERR(priv->clk)) {
+                dev_err(dev, "failed to retrieve host clock from device tree\n");
+                err = -EINVAL;
+                goto out_netdev;
+        }
+
+        err = arc_emac_probe(ndev, interface);
+out_netdev:
+        if (err)
+                free_netdev(ndev);
+        return err;
+}
+
+static int emac_arc_remove(struct platform_device *pdev)
+{
+        struct net_device *ndev = platform_get_drvdata(pdev);
+        int err;
+
+        err = arc_emac_remove(ndev);
+        free_netdev(ndev);
+        return err;
+}
+
+static const struct of_device_id emac_arc_dt_ids[] = {
+        { .compatible = "snps,arc-emac" },
+        { /* Sentinel */ }
+};
+
+static struct platform_driver emac_arc_driver = {
+        .probe = emac_arc_probe,
+        .remove = emac_arc_remove,
+        .driver = {
+                .name = DRV_NAME,
+                .of_match_table  = emac_arc_dt_ids,
+        },
+};
+
+module_platform_driver(emac_arc_driver);
+
+MODULE_AUTHOR("Romain Perier <romain.perier@gmail.com>");
+MODULE_DESCRIPTION("ARC EMAC platform driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/net/ethernet/arc/emac_main.c b/drivers/net/ethernet/arc/emac_main.c
index fe5cfeace6e3..a7773923a7a0 100644
--- a/drivers/net/ethernet/arc/emac_main.c
+++ b/drivers/net/ethernet/arc/emac_main.c
@@ -26,8 +26,6 @@
 
 #include "emac.h"
 
-#define DRV_NAME        "arc_emac"
-#define DRV_VERSION     "1.0"
 
 /**
  * arc_emac_adjust_link - Adjust the PHY link duplex.
@@ -120,8 +118,10 @@ static int arc_emac_set_settings(struct net_device *ndev,
 static void arc_emac_get_drvinfo(struct net_device *ndev,
                                  struct ethtool_drvinfo *info)
 {
-        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
-        strlcpy(info->version, DRV_VERSION, sizeof(info->version));
+        struct arc_emac_priv *priv = netdev_priv(ndev);
+
+        strlcpy(info->driver, priv->drv_name, sizeof(info->driver));
+        strlcpy(info->version, priv->drv_version, sizeof(info->version));
 }
 
 static const struct ethtool_ops arc_emac_ethtool_ops = {
@@ -671,46 +671,38 @@ static const struct net_device_ops arc_emac_netdev_ops = {
 #endif
 };
 
-static int arc_emac_probe(struct platform_device *pdev)
+int arc_emac_probe(struct net_device *ndev, int interface)
 {
+        struct device *dev = ndev->dev.parent;
         struct resource res_regs;
         struct device_node *phy_node;
         struct arc_emac_priv *priv;
-        struct net_device *ndev;
         const char *mac_addr;
         unsigned int id, clock_frequency, irq;
         int err;
 
-        if (!pdev->dev.of_node)
-                return -ENODEV;
 
         /* Get PHY from device tree */
-        phy_node = of_parse_phandle(pdev->dev.of_node, "phy", 0);
+        phy_node = of_parse_phandle(dev->of_node, "phy", 0);
         if (!phy_node) {
-                dev_err(&pdev->dev, "failed to retrieve phy description from device tree\n");
+                dev_err(dev, "failed to retrieve phy description from device tree\n");
                 return -ENODEV;
         }
 
         /* Get EMAC registers base address from device tree */
-        err = of_address_to_resource(pdev->dev.of_node, 0, &res_regs);
+        err = of_address_to_resource(dev->of_node, 0, &res_regs);
         if (err) {
-                dev_err(&pdev->dev, "failed to retrieve registers base from device tree\n");
+                dev_err(dev, "failed to retrieve registers base from device tree\n");
                 return -ENODEV;
         }
 
         /* Get IRQ from device tree */
-        irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
+        irq = irq_of_parse_and_map(dev->of_node, 0);
         if (!irq) {
-                dev_err(&pdev->dev, "failed to retrieve <irq> value from device tree\n");
+                dev_err(dev, "failed to retrieve <irq> value from device tree\n");
                 return -ENODEV;
         }
 
-        ndev = alloc_etherdev(sizeof(struct arc_emac_priv));
-        if (!ndev)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, ndev);
-        SET_NETDEV_DEV(ndev, &pdev->dev);
 
         ndev->netdev_ops = &arc_emac_netdev_ops;
         ndev->ethtool_ops = &arc_emac_ethtool_ops;
@@ -719,60 +711,57 @@ static int arc_emac_probe(struct platform_device *pdev)
         ndev->flags &= ~IFF_MULTICAST;
 
         priv = netdev_priv(ndev);
-        priv->dev = &pdev->dev;
+        priv->dev = dev;
 
-        priv->regs = devm_ioremap_resource(&pdev->dev, &res_regs);
+        priv->regs = devm_ioremap_resource(dev, &res_regs);
         if (IS_ERR(priv->regs)) {
-                err = PTR_ERR(priv->regs);
-                goto out_netdev;
+                return PTR_ERR(priv->regs);
         }
-        dev_dbg(&pdev->dev, "Registers base address is 0x%p\n", priv->regs);
+        dev_dbg(dev, "Registers base address is 0x%p\n", priv->regs);
 
-        priv->clk = of_clk_get(pdev->dev.of_node, 0);
-        if (IS_ERR(priv->clk)) {
-                /* Get CPU clock frequency from device tree */
-                if (of_property_read_u32(pdev->dev.of_node, "clock-frequency",
-                                        &clock_frequency)) {
-                        dev_err(&pdev->dev, "failed to retrieve <clock-frequency> from device tree\n");
-                        err = -EINVAL;
-                        goto out_netdev;
-                }
-        } else {
+        if (priv->clk) {
                 err = clk_prepare_enable(priv->clk);
                 if (err) {
-                        dev_err(&pdev->dev, "failed to enable clock\n");
-                        goto out_clkget;
+                        dev_err(dev, "failed to enable clock\n");
+                        return err;
                 }
 
                 clock_frequency = clk_get_rate(priv->clk);
+        } else {
+                /* Get CPU clock frequency from device tree */
+                if (of_property_read_u32(dev->of_node, "clock-frequency",
+                                         &clock_frequency)) {
+                        dev_err(dev, "failed to retrieve <clock-frequency> from device tree\n");
+                        return -EINVAL;
+                }
         }
 
         id = arc_reg_get(priv, R_ID);
 
         /* Check for EMAC revision 5 or 7, magic number */
         if (!(id == 0x0005fd02 || id == 0x0007fd02)) {
-                dev_err(&pdev->dev, "ARC EMAC not detected, id=0x%x\n", id);
+                dev_err(dev, "ARC EMAC not detected, id=0x%x\n", id);
                 err = -ENODEV;
                 goto out_clken;
         }
-        dev_info(&pdev->dev, "ARC EMAC detected with id: 0x%x\n", id);
+        dev_info(dev, "ARC EMAC detected with id: 0x%x\n", id);
 
         /* Set poll rate so that it polls every 1 ms */
         arc_reg_set(priv, R_POLLRATE, clock_frequency / 1000000);
 
         ndev->irq = irq;
-        dev_info(&pdev->dev, "IRQ is %d\n", ndev->irq);
+        dev_info(dev, "IRQ is %d\n", ndev->irq);
 
         /* Register interrupt handler for device */
-        err = devm_request_irq(&pdev->dev, ndev->irq, arc_emac_intr, 0,
+        err = devm_request_irq(dev, ndev->irq, arc_emac_intr, 0,
                                ndev->name, ndev);
         if (err) {
-                dev_err(&pdev->dev, "could not allocate IRQ\n");
+                dev_err(dev, "could not allocate IRQ\n");
                 goto out_clken;
         }
 
         /* Get MAC address from device tree */
-        mac_addr = of_get_mac_address(pdev->dev.of_node);
+        mac_addr = of_get_mac_address(dev->of_node);
 
         if (mac_addr)
                 memcpy(ndev->dev_addr, mac_addr, ETH_ALEN);
@@ -780,14 +769,14 @@ static int arc_emac_probe(struct platform_device *pdev)
                 eth_hw_addr_random(ndev);
 
         arc_emac_set_address_internal(ndev);
-        dev_info(&pdev->dev, "MAC address is now %pM\n", ndev->dev_addr);
+        dev_info(dev, "MAC address is now %pM\n", ndev->dev_addr);
 
         /* Do 1 allocation instead of 2 separate ones for Rx and Tx BD rings */
-        priv->rxbd = dmam_alloc_coherent(&pdev->dev, RX_RING_SZ + TX_RING_SZ,
+        priv->rxbd = dmam_alloc_coherent(dev, RX_RING_SZ + TX_RING_SZ,
                                          &priv->rxbd_dma, GFP_KERNEL);
 
         if (!priv->rxbd) {
-                dev_err(&pdev->dev, "failed to allocate data buffers\n");
+                dev_err(dev, "failed to allocate data buffers\n");
                 err = -ENOMEM;
                 goto out_clken;
         }
@@ -795,31 +784,31 @@ static int arc_emac_probe(struct platform_device *pdev)
         priv->txbd = priv->rxbd + RX_BD_NUM;
 
         priv->txbd_dma = priv->rxbd_dma + RX_RING_SZ;
-        dev_dbg(&pdev->dev, "EMAC Device addr: Rx Ring [0x%x], Tx Ring[%x]\n",
+        dev_dbg(dev, "EMAC Device addr: Rx Ring [0x%x], Tx Ring[%x]\n",
                 (unsigned int)priv->rxbd_dma, (unsigned int)priv->txbd_dma);
 
-        err = arc_mdio_probe(pdev, priv);
+        err = arc_mdio_probe(priv);
         if (err) {
-                dev_err(&pdev->dev, "failed to probe MII bus\n");
+                dev_err(dev, "failed to probe MII bus\n");
                 goto out_clken;
         }
 
         priv->phy_dev = of_phy_connect(ndev, phy_node, arc_emac_adjust_link, 0,
-                                       PHY_INTERFACE_MODE_MII);
+                                       interface);
         if (!priv->phy_dev) {
-                dev_err(&pdev->dev, "of_phy_connect() failed\n");
+                dev_err(dev, "of_phy_connect() failed\n");
                 err = -ENODEV;
                 goto out_mdio;
         }
 
-        dev_info(&pdev->dev, "connected to %s phy with id 0x%x\n",
+        dev_info(dev, "connected to %s phy with id 0x%x\n",
                  priv->phy_dev->drv->name, priv->phy_dev->phy_id);
 
         netif_napi_add(ndev, &priv->napi, arc_emac_poll, ARC_EMAC_NAPI_WEIGHT);
 
         err = register_netdev(ndev);
         if (err) {
-                dev_err(&pdev->dev, "failed to register network device\n");
+                dev_err(dev, "failed to register network device\n");
                 goto out_netif_api;
         }
 
@@ -832,19 +821,14 @@ out_netif_api:
 out_mdio:
         arc_mdio_remove(priv);
 out_clken:
-        if (!IS_ERR(priv->clk))
+        if (priv->clk)
                 clk_disable_unprepare(priv->clk);
-out_clkget:
-        if (!IS_ERR(priv->clk))
-                clk_put(priv->clk);
-out_netdev:
-        free_netdev(ndev);
         return err;
 }
+EXPORT_SYMBOL_GPL(arc_emac_probe);
 
-static int arc_emac_remove(struct platform_device *pdev)
+int arc_emac_remove(struct net_device *ndev)
 {
-        struct net_device *ndev = platform_get_drvdata(pdev);
         struct arc_emac_priv *priv = netdev_priv(ndev);
 
         phy_disconnect(priv->phy_dev);
@@ -855,31 +839,12 @@ static int arc_emac_remove(struct platform_device *pdev)
 
         if (!IS_ERR(priv->clk)) {
                 clk_disable_unprepare(priv->clk);
-                clk_put(priv->clk);
         }
 
-        free_netdev(ndev);
 
         return 0;
 }
-
-static const struct of_device_id arc_emac_dt_ids[] = {
-        { .compatible = "snps,arc-emac" },
-        { /* Sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, arc_emac_dt_ids);
-
-static struct platform_driver arc_emac_driver = {
-        .probe = arc_emac_probe,
-        .remove = arc_emac_remove,
-        .driver = {
-                .name = DRV_NAME,
-                .owner = THIS_MODULE,
-                .of_match_table  = arc_emac_dt_ids,
-                },
-};
-
-module_platform_driver(arc_emac_driver);
+EXPORT_SYMBOL_GPL(arc_emac_remove);
 
 MODULE_AUTHOR("Alexey Brodkin <abrodkin@synopsys.com>");
 MODULE_DESCRIPTION("ARC EMAC driver");
diff --git a/drivers/net/ethernet/arc/emac_mdio.c b/drivers/net/ethernet/arc/emac_mdio.c
index 26ba2423f33a..d5ee986936da 100644
--- a/drivers/net/ethernet/arc/emac_mdio.c
+++ b/drivers/net/ethernet/arc/emac_mdio.c
@@ -100,7 +100,6 @@ static int arc_mdio_write(struct mii_bus *bus, int phy_addr,
 
 /**
  * arc_mdio_probe - MDIO probe function.
- * @pdev:       Pointer to platform device.
  * @priv:       Pointer to ARC EMAC private data structure.
  *
  * returns:     0 on success, -ENOMEM when mdiobus_alloc
@@ -108,7 +107,7 @@ static int arc_mdio_write(struct mii_bus *bus, int phy_addr,
  *
  * Sets up and registers the MDIO interface.
  */
-int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv)
+int arc_mdio_probe(struct arc_emac_priv *priv)
 {
         struct mii_bus *bus;
         int error;
@@ -124,9 +123,9 @@ int arc_mdio_probe(struct platform_device *pdev, struct arc_emac_priv *priv)
         bus->read = &arc_mdio_read;
         bus->write = &arc_mdio_write;
 
-        snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
+        snprintf(bus->id, MII_BUS_ID_SIZE, "%s", bus->name);
 
-        error = of_mdiobus_register(bus, pdev->dev.of_node);
+        error = of_mdiobus_register(bus, priv->dev->of_node);
         if (error) {
                 dev_err(priv->dev, "cannot register MDIO bus %s\n", bus->name);
                 mdiobus_free(bus);
diff --git a/drivers/net/ethernet/broadcom/Kconfig b/drivers/net/ethernet/broadcom/Kconfig
index d8d07a818b89..c3e260c21734 100644
--- a/drivers/net/ethernet/broadcom/Kconfig
+++ b/drivers/net/ethernet/broadcom/Kconfig
@@ -122,6 +122,7 @@ config TIGON3
 config BNX2X
         tristate "Broadcom NetXtremeII 10Gb support"
         depends on PCI
+        select PTP_1588_CLOCK
         select FW_LOADER
         select ZLIB_INFLATE
         select LIBCRC32C
diff --git a/drivers/net/ethernet/broadcom/bcmsysport.c b/drivers/net/ethernet/broadcom/bcmsysport.c
index 6f4e18644bd4..662cf2222873 100644
--- a/drivers/net/ethernet/broadcom/bcmsysport.c
+++ b/drivers/net/ethernet/broadcom/bcmsysport.c
@@ -139,6 +139,15 @@ static int bcm_sysport_set_rx_csum(struct net_device *dev,
         else
                 reg &= ~RXCHK_SKIP_FCS;
 
+        /* If Broadcom tags are enabled (e.g: using a switch), make
+         * sure we tell the RXCHK hardware to expect a 4-bytes Broadcom
+         * tag after the Ethernet MAC Source Address.
+         */
+        if (netdev_uses_dsa(dev))
+                reg |= RXCHK_BRCM_TAG_EN;
+        else
+                reg &= ~RXCHK_BRCM_TAG_EN;
+
         rxchk_writel(priv, reg, RXCHK_CONTROL);
 
         return 0;
@@ -1062,16 +1071,19 @@ static void bcm_sysport_adj_link(struct net_device *dev)
         if (!phydev->pause)
                 cmd_bits |= CMD_RX_PAUSE_IGNORE | CMD_TX_PAUSE_IGNORE;
 
-        if (changed) {
+        if (!changed)
+                return;
+
+        if (phydev->link) {
                 reg = umac_readl(priv, UMAC_CMD);
                 reg &= ~((CMD_SPEED_MASK << CMD_SPEED_SHIFT) |
                         CMD_HD_EN | CMD_RX_PAUSE_IGNORE |
                         CMD_TX_PAUSE_IGNORE);
                 reg |= cmd_bits;
                 umac_writel(priv, reg, UMAC_CMD);
-
-                phy_print_status(priv->phydev);
         }
+
+        phy_print_status(priv->phydev);
 }
 
 static int bcm_sysport_init_tx_ring(struct bcm_sysport_priv *priv,
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
index d777fae86988..86e94517a536 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
@@ -20,13 +20,17 @@
 #include <linux/types.h>
 #include <linux/pci_regs.h>
 
+#include <linux/ptp_clock_kernel.h>
+#include <linux/net_tstamp.h>
+#include <linux/clocksource.h>
+
 /* compilation time flags */
 
 /* define this to make the driver freeze on error to allow getting debug info
  * (you will need to reboot afterwards) */
 /* #define BNX2X_STOP_ON_ERROR */
 
-#define DRV_MODULE_VERSION      "1.78.19-0"
+#define DRV_MODULE_VERSION      "1.710.51-0"
 #define DRV_MODULE_RELDATE      "2014/02/10"
 #define BNX2X_BC_VER            0x040200
 
@@ -70,6 +74,7 @@ enum bnx2x_int_mode {
 #define BNX2X_MSG_SP                    0x0100000 /* was: NETIF_MSG_INTR */
 #define BNX2X_MSG_FP                    0x0200000 /* was: NETIF_MSG_INTR */
 #define BNX2X_MSG_IOV                   0x0800000
+#define BNX2X_MSG_PTP                   0x1000000
 #define BNX2X_MSG_IDLE                  0x2000000 /* used for idle check*/
 #define BNX2X_MSG_ETHTOOL               0x4000000
 #define BNX2X_MSG_DCB                   0x8000000
@@ -1587,10 +1592,11 @@ struct bnx2x {
 #define USING_SINGLE_MSIX_FLAG          (1 << 20)
 #define BC_SUPPORTS_DCBX_MSG_NON_PMF    (1 << 21)
 #define IS_VF_FLAG                      (1 << 22)
-#define INTERRUPTS_ENABLED_FLAG         (1 << 23)
-#define BC_SUPPORTS_RMMOD_CMD           (1 << 24)
-#define HAS_PHYS_PORT_ID                (1 << 25)
-#define AER_ENABLED                     (1 << 26)
+#define BC_SUPPORTS_RMMOD_CMD           (1 << 23)
+#define HAS_PHYS_PORT_ID                (1 << 24)
+#define AER_ENABLED                     (1 << 25)
+#define PTP_SUPPORTED                   (1 << 26)
+#define TX_TIMESTAMPING_EN              (1 << 27)
 
 #define BP_NOMCP(bp)                    ((bp)->flags & NO_MCP_FLAG)
 
@@ -1684,13 +1690,9 @@ struct bnx2x {
 #define BNX2X_STATE_ERROR               0xf000
 
 #define BNX2X_MAX_PRIORITY              8
-#define BNX2X_MAX_ENTRIES_PER_PRI       16
-#define BNX2X_MAX_COS                   3
-#define BNX2X_MAX_TX_COS                2
         int                     num_queues;
         uint                    num_ethernet_queues;
         uint                    num_cnic_queues;
-        int                     num_napi_queues;
         int                     disable_tpa;
 
         u32                     rx_mode;
@@ -1933,6 +1935,19 @@ struct bnx2x {
 
         u8                                      phys_port_id[ETH_ALEN];
 
+        /* PTP related context */
+        struct ptp_clock *ptp_clock;
+        struct ptp_clock_info ptp_clock_info;
+        struct work_struct ptp_task;
+        struct cyclecounter cyclecounter;
+        struct timecounter timecounter;
+        bool timecounter_init_done;
+        struct sk_buff *ptp_tx_skb;
+        unsigned long ptp_tx_start;
+        bool hwtstamp_ioctl_called;
+        u16 tx_type;
+        u16 rx_filter;
+
         struct bnx2x_link_report_data           vf_link_vars;
 };
 
@@ -2559,4 +2574,11 @@ void bnx2x_update_mng_version(struct bnx2x *bp);
 
 #define E1H_MAX_MF_SB_COUNT (HC_SB_MAX_SB_E1X/(E1HVN_MAX * PORT_MAX))
 
+void bnx2x_init_ptp(struct bnx2x *bp);
+int bnx2x_configure_ptp_filters(struct bnx2x *bp);
+void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb);
+
+#define BNX2X_MAX_PHC_DRIFT 31000000
+#define BNX2X_PTP_TX_TIMEOUT
+
 #endif /* bnx2x.h */
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index 4ccc806b1150..6dc32aee96bf 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -21,6 +21,7 @@
 #include <linux/if_vlan.h>
 #include <linux/interrupt.h>
 #include <linux/ip.h>
+#include <linux/crash_dump.h>
 #include <net/tcp.h>
 #include <net/ipv6.h>
 #include <net/ip6_checksum.h>
@@ -64,7 +65,7 @@ static int bnx2x_calc_num_queues(struct bnx2x *bp)
         int nq = bnx2x_num_queues ? : netif_get_num_default_rss_queues();
 
         /* Reduce memory usage in kdump environment by using only one queue */
-        if (reset_devices)
+        if (is_kdump_kernel())
                 nq = 1;
 
         nq = clamp(nq, 1, BNX2X_MAX_QUEUES(bp));
@@ -1063,6 +1064,11 @@ reuse_rx:
 
                 skb_record_rx_queue(skb, fp->rx_queue);
 
+                /* Check if this packet was timestamped */
+                if (unlikely(cqe->fast_path_cqe.type_error_flags &
+                             (1 << ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT)))
+                        bnx2x_set_rx_ts(bp, skb);
+
                 if (le16_to_cpu(cqe_fp->pars_flags.flags) &
                     PARSING_FLAGS_VLAN)
                         __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q),
@@ -2078,6 +2084,10 @@ int bnx2x_rss(struct bnx2x *bp, struct bnx2x_rss_config_obj *rss_obj,
                         __set_bit(BNX2X_RSS_IPV4_UDP, &params.rss_flags);
                 if (rss_obj->udp_rss_v6)
                         __set_bit(BNX2X_RSS_IPV6_UDP, &params.rss_flags);
+
+                if (!CHIP_IS_E1x(bp))
+                        /* valid only for TUNN_MODE_GRE tunnel mode */
+                        __set_bit(BNX2X_RSS_GRE_INNER_HDRS, &params.rss_flags);
         } else {
                 __set_bit(BNX2X_RSS_MODE_DISABLED, &params.rss_flags);
         }
@@ -2800,7 +2810,11 @@ int bnx2x_nic_load(struct bnx2x *bp, int load_mode)
         /* Initialize Rx filter. */
         bnx2x_set_rx_mode_inner(bp);
 
-        /* Start the Tx */
+        if (bp->flags & PTP_SUPPORTED) {
+                bnx2x_init_ptp(bp);
+                bnx2x_configure_ptp_filters(bp);
+        }
+        /* Start Tx */
         switch (load_mode) {
         case LOAD_NORMAL:
                 /* Tx queue should be only re-enabled */
@@ -3437,26 +3451,6 @@ exit_lbl:
 }
 #endif
 
-static void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data,
-                                 u32 xmit_type)
-{
-        struct ipv6hdr *ipv6;
-
-        *parsing_data |= (skb_shinfo(skb)->gso_size <<
-                              ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
-                              ETH_TX_PARSE_BD_E2_LSO_MSS;
-
-        if (xmit_type & XMIT_GSO_ENC_V6)
-                ipv6 = inner_ipv6_hdr(skb);
-        else if (xmit_type & XMIT_GSO_V6)
-                ipv6 = ipv6_hdr(skb);
-        else
-                ipv6 = NULL;
-
-        if (ipv6 && ipv6->nexthdr == NEXTHDR_IPV6)
-                *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
-}
-
 /**
  * bnx2x_set_pbd_gso - update PBD in GSO case.
  *
@@ -3466,7 +3460,6 @@ static void bnx2x_set_pbd_gso_e2(struct sk_buff *skb, u32 *parsing_data,
  */
 static void bnx2x_set_pbd_gso(struct sk_buff *skb,
                               struct eth_tx_parse_bd_e1x *pbd,
-                              struct eth_tx_start_bd *tx_start_bd,
                               u32 xmit_type)
 {
         pbd->lso_mss = cpu_to_le16(skb_shinfo(skb)->gso_size);
@@ -3479,9 +3472,6 @@ static void bnx2x_set_pbd_gso(struct sk_buff *skb,
                         bswab16(~csum_tcpudp_magic(ip_hdr(skb)->saddr,
                                                    ip_hdr(skb)->daddr,
                                                    0, IPPROTO_TCP, 0));
-
-                /* GSO on 57710/57711 needs FW to calculate IP checksum */
-                tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM;
         } else {
                 pbd->tcp_pseudo_csum =
                         bswab16(~csum_ipv6_magic(&ipv6_hdr(skb)->saddr,
@@ -3653,18 +3643,23 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
                            (__force u32)iph->tot_len -
                            (__force u32)iph->frag_off;
 
+                outerip_len = iph->ihl << 1;
+
                 pbd2->fw_ip_csum_wo_len_flags_frag =
                         bswab16(csum_fold((__force __wsum)csum));
         } else {
                 pbd2->fw_ip_hdr_to_payload_w =
                         hlen_w - ((sizeof(struct ipv6hdr)) >> 1);
+                pbd_e2->data.tunnel_data.flags |=
+                        ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER;
         }
 
         pbd2->tcp_send_seq = bswab32(inner_tcp_hdr(skb)->seq);
 
         pbd2->tcp_flags = pbd_tcp_flags(inner_tcp_hdr(skb));
 
-        if (xmit_type & XMIT_GSO_V4) {
+        /* inner IP header info */
+        if (xmit_type & XMIT_CSUM_ENC_V4) {
                 pbd2->hw_ip_id = bswab16(inner_ip_hdr(skb)->id);
 
                 pbd_e2->data.tunnel_data.pseudo_csum =
@@ -3672,8 +3667,6 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
                                         inner_ip_hdr(skb)->saddr,
                                         inner_ip_hdr(skb)->daddr,
                                         0, IPPROTO_TCP, 0));
-
-                outerip_len = ip_hdr(skb)->ihl << 1;
         } else {
                 pbd_e2->data.tunnel_data.pseudo_csum =
                         bswab16(~csum_ipv6_magic(
@@ -3686,8 +3679,6 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
 
         *global_data |=
                 outerip_off |
-                (!!(xmit_type & XMIT_CSUM_V6) <<
-                        ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT) |
                 (outerip_len <<
                         ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT) |
                 ((skb->protocol == cpu_to_be16(ETH_P_8021Q)) <<
@@ -3699,6 +3690,23 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
         }
 }
 
+static inline void bnx2x_set_ipv6_ext_e2(struct sk_buff *skb, u32 *parsing_data,
+                                         u32 xmit_type)
+{
+        struct ipv6hdr *ipv6;
+
+        if (!(xmit_type & (XMIT_GSO_ENC_V6 | XMIT_GSO_V6)))
+                return;
+
+        if (xmit_type & XMIT_GSO_ENC_V6)
+                ipv6 = inner_ipv6_hdr(skb);
+        else /* XMIT_GSO_V6 */
+                ipv6 = ipv6_hdr(skb);
+
+        if (ipv6->nexthdr == NEXTHDR_IPV6)
+                *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR;
+}
+
 /* called with netif_tx_lock
  * bnx2x_tx_int() runs without netif_tx_lock unless it needs to call
  * netif_wake_queue()
@@ -3831,6 +3839,20 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
 
         tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
 
+        if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
+                if (!(bp->flags & TX_TIMESTAMPING_EN)) {
+                        BNX2X_ERR("Tx timestamping was not enabled, this packet will not be timestamped\n");
+                } else if (bp->ptp_tx_skb) {
+                        BNX2X_ERR("The device supports only a single outstanding packet to timestamp, this packet will not be timestamped\n");
+                } else {
+                        skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
+                        /* schedule check for Tx timestamp */
+                        bp->ptp_tx_skb = skb_get(skb);
+                        bp->ptp_tx_start = jiffies;
+                        schedule_work(&bp->ptp_task);
+                }
+        }
+
         /* header nbd: indirectly zero other flags! */
         tx_start_bd->general_data = 1 << ETH_TX_START_BD_HDR_NBDS_SHIFT;
 
@@ -3852,12 +3874,16 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                 /* when transmitting in a vf, start bd must hold the ethertype
                  * for fw to enforce it
                  */
+#ifndef BNX2X_STOP_ON_ERROR
                 if (IS_VF(bp))
+#endif
                         tx_start_bd->vlan_or_ethertype =
                                 cpu_to_le16(ntohs(eth->h_proto));
+#ifndef BNX2X_STOP_ON_ERROR
                 else
                         /* used by FW for packet accounting */
                         tx_start_bd->vlan_or_ethertype = cpu_to_le16(pkt_prod);
+#endif
         }
 
         nbd = 2; /* start_bd + pbd + frags (updated when pages are mapped) */
@@ -3915,6 +3941,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                                                      xmit_type);
                 }
 
+                bnx2x_set_ipv6_ext_e2(skb, &pbd_e2_parsing_data, xmit_type);
                 /* Add the macs to the parsing BD if this is a vf or if
                  * Tx Switching is enabled.
                  */
@@ -3929,11 +3956,22 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                                               &pbd_e2->data.mac_addr.dst_mid,
                                               &pbd_e2->data.mac_addr.dst_lo,
                                               eth->h_dest);
-                } else if (bp->flags & TX_SWITCHING) {
-                        bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi,
-                                              &pbd_e2->data.mac_addr.dst_mid,
-                                              &pbd_e2->data.mac_addr.dst_lo,
-                                              eth->h_dest);
+                } else {
+                        if (bp->flags & TX_SWITCHING)
+                                bnx2x_set_fw_mac_addr(
+                                                &pbd_e2->data.mac_addr.dst_hi,
+                                                &pbd_e2->data.mac_addr.dst_mid,
+                                                &pbd_e2->data.mac_addr.dst_lo,
+                                                eth->h_dest);
+#ifdef BNX2X_STOP_ON_ERROR
+                        /* Enforce security is always set in Stop on Error -
+                         * source mac should be present in the parsing BD
+                         */
+                        bnx2x_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi,
+                                              &pbd_e2->data.mac_addr.src_mid,
+                                              &pbd_e2->data.mac_addr.src_lo,
+                                              eth->h_source);
+#endif
                 }
 
                 SET_FLAG(pbd_e2_parsing_data,
@@ -3980,10 +4018,12 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                                                  bd_prod);
                 }
                 if (!CHIP_IS_E1x(bp))
-                        bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data,
-                                             xmit_type);
+                        pbd_e2_parsing_data |=
+                                (skb_shinfo(skb)->gso_size <<
+                                 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) &
+                                 ETH_TX_PARSE_BD_E2_LSO_MSS;
                 else
-                        bnx2x_set_pbd_gso(skb, pbd_e1x, first_bd, xmit_type);
+                        bnx2x_set_pbd_gso(skb, pbd_e1x, xmit_type);
         }
 
         /* Set the PBD's parsing_data field if not zero
@@ -4771,11 +4811,15 @@ netdev_features_t bnx2x_fix_features(struct net_device *dev,
         struct bnx2x *bp = netdev_priv(dev);
 
         /* TPA requires Rx CSUM offloading */
-        if (!(features & NETIF_F_RXCSUM) || bp->disable_tpa) {
+        if (!(features & NETIF_F_RXCSUM)) {
                 features &= ~NETIF_F_LRO;
                 features &= ~NETIF_F_GRO;
         }
 
+        /* Note: do not disable SW GRO in kernel when HW GRO is off */
+        if (bp->disable_tpa)
+                features &= ~NETIF_F_LRO;
+
         return features;
 }
 
@@ -4814,6 +4858,10 @@ int bnx2x_set_features(struct net_device *dev, netdev_features_t features)
         if ((changes & GRO_ENABLE_FLAG) && (flags & TPA_ENABLE_FLAG))
                 changes &= ~GRO_ENABLE_FLAG;
 
+        /* if GRO is changed while HW TPA is off, don't force a reload */
+        if ((changes & GRO_ENABLE_FLAG) && bp->disable_tpa)
+                changes &= ~GRO_ENABLE_FLAG;
+
         if (changes)
                 bnx2x_reload = true;
 
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
index 571427c7226b..ac63e16829ef 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.h
@@ -932,8 +932,9 @@ static inline int bnx2x_func_start(struct bnx2x *bp)
         else /* CHIP_IS_E1X */
                 start_params->network_cos_mode = FW_WRR;
 
-        start_params->gre_tunnel_mode = L2GRE_TUNNEL;
-        start_params->gre_tunnel_rss = GRE_INNER_HEADERS_RSS;
+        start_params->tunnel_mode       = TUNN_MODE_GRE;
+        start_params->gre_tunnel_type   = IPGRE_TUNNEL;
+        start_params->inner_gre_rss_en  = 1;
 
         return bnx2x_func_state_change(bp, &func_params);
 }
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
index fb26bc4c42a1..6e4294ed1fc9 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dcb.c
@@ -2092,7 +2092,6 @@ static void bnx2x_dcbnl_get_pfc_cfg(struct net_device *netdev, int prio,
 static u8 bnx2x_dcbnl_set_all(struct net_device *netdev)
 {
         struct bnx2x *bp = netdev_priv(netdev);
-        int rc = 0;
 
         DP(BNX2X_MSG_DCB, "SET-ALL\n");
 
@@ -2110,9 +2109,7 @@ static u8 bnx2x_dcbnl_set_all(struct net_device *netdev)
                                        1);
                 bnx2x_dcbx_init(bp, true);
         }
-        DP(BNX2X_MSG_DCB, "set_dcbx_params done (%d)\n", rc);
-        if (rc)
-                return 1;
+        DP(BNX2X_MSG_DCB, "set_dcbx_params done\n");
 
         return 0;
 }
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dump.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dump.h
index 12eb4baee9f6..741aa130c19f 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dump.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_dump.h
@@ -40,7 +40,7 @@ struct	dump_header {
         u32 dump_meta_data; /* OR of CHIP and PATH. */
 };
 
-#define BNX2X_DUMP_VERSION 0x50acff01
+#define  BNX2X_DUMP_VERSION 0x61111111
 struct reg_addr {
         u32 addr;
         u32 size;
@@ -1464,7 +1464,6 @@ static const struct reg_addr reg_addrs[] = {
         { 0x180398, 1, 0x1c, 0x924},
         { 0x1803a0, 5, 0x1c, 0x924},
         { 0x1803b4, 2, 0x18, 0x924},
-        { 0x180400, 256, 0x3, 0xfff},
         { 0x181000, 4, 0x1f, 0x93c},
         { 0x181010, 1020, 0x1f, 0x38},
         { 0x182000, 4, 0x18, 0x924},
@@ -1576,7 +1575,6 @@ static const struct reg_addr reg_addrs[] = {
         { 0x200398, 1, 0x1c, 0x924},
         { 0x2003a0, 1, 0x1c, 0x924},
         { 0x2003a8, 2, 0x1c, 0x924},
-        { 0x200400, 256, 0x3, 0xfff},
         { 0x202000, 4, 0x1f, 0x1927},
         { 0x202010, 2044, 0x1f, 0x1007},
         { 0x204000, 4, 0x18, 0x924},
@@ -1688,7 +1686,6 @@ static const struct reg_addr reg_addrs[] = {
         { 0x280398, 1, 0x1c, 0x924},
         { 0x2803a0, 1, 0x1c, 0x924},
         { 0x2803a8, 2, 0x1c, 0x924},
-        { 0x280400, 256, 0x3, 0xfff},
         { 0x282000, 4, 0x1f, 0x9e4},
         { 0x282010, 2044, 0x1f, 0x1c0},
         { 0x284000, 4, 0x18, 0x924},
@@ -1800,7 +1797,6 @@ static const struct reg_addr reg_addrs[] = {
         { 0x300398, 1, 0x1c, 0x924},
         { 0x3003a0, 1, 0x1c, 0x924},
         { 0x3003a8, 2, 0x1c, 0x924},
-        { 0x300400, 256, 0x3, 0xfff},
         { 0x302000, 4, 0x1f, 0xf24},
         { 0x302010, 2044, 0x1f, 0xe00},
         { 0x304000, 4, 0x18, 0x924},
@@ -2206,10 +2202,10 @@ static const struct wreg_addr wreg_addr_e3b0 = {
         0x1b0c00, 128, 2, read_reg_e3b0, 0x1f, 0x1fff};
 
 static const unsigned int dump_num_registers[NUM_CHIPS][NUM_PRESETS] = {
-        {20782, 18567, 27975, 19729, 18311, 27719, 20836, 32391, 41799, 20812,
-         26247, 35655, 19074},
-        {32774, 19297, 33277, 31721, 19041, 33021, 32828, 33121, 47101, 32804,
-         26977, 40957, 35895},
+        {19758, 17543, 26951, 18705, 17287, 26695, 19812, 31367, 40775, 19788,
+         25223, 34631, 19074},
+        {31750, 18273, 32253, 30697, 18017, 31997, 31804, 32097, 46077, 31780,
+         25953, 39933, 35895},
         {36527, 17928, 33697, 35474, 18700, 34466, 36581, 31752, 47521, 36557,
          25608, 41377, 43903},
         {45239, 17936, 34387, 44186, 18708, 35156, 45293, 31760, 48211, 45269,
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
index 92fee842f954..0b173ed20ae9 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
@@ -3481,6 +3481,46 @@ static int bnx2x_set_channels(struct net_device *dev,
         return bnx2x_nic_load(bp, LOAD_NORMAL);
 }
 
+static int bnx2x_get_ts_info(struct net_device *dev,
+                             struct ethtool_ts_info *info)
+{
+        struct bnx2x *bp = netdev_priv(dev);
+
+        if (bp->flags & PTP_SUPPORTED) {
+                info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
+                                        SOF_TIMESTAMPING_RX_SOFTWARE |
+                                        SOF_TIMESTAMPING_SOFTWARE |
+                                        SOF_TIMESTAMPING_TX_HARDWARE |
+                                        SOF_TIMESTAMPING_RX_HARDWARE |
+                                        SOF_TIMESTAMPING_RAW_HARDWARE;
+
+                if (bp->ptp_clock)
+                        info->phc_index = ptp_clock_index(bp->ptp_clock);
+                else
+                        info->phc_index = -1;
+
+                info->rx_filters = (1 << HWTSTAMP_FILTER_NONE) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V1_L4_SYNC) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_L4_SYNC) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_L2_SYNC) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_EVENT) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_SYNC) |
+                                   (1 << HWTSTAMP_FILTER_PTP_V2_DELAY_REQ);
+
+                info->tx_types = (1 << HWTSTAMP_TX_OFF)|(1 << HWTSTAMP_TX_ON);
+
+                return 0;
+        }
+
+        return ethtool_op_get_ts_info(dev, info);
+}
+
 static const struct ethtool_ops bnx2x_ethtool_ops = {
         .get_settings           = bnx2x_get_settings,
         .set_settings           = bnx2x_set_settings,
@@ -3522,7 +3562,7 @@ static const struct ethtool_ops bnx2x_ethtool_ops = {
         .get_module_eeprom      = bnx2x_get_module_eeprom,
         .get_eee                = bnx2x_get_eee,
         .set_eee                = bnx2x_set_eee,
-        .get_ts_info            = ethtool_op_get_ts_info,
+        .get_ts_info            = bnx2x_get_ts_info,
 };
 
 static const struct ethtool_ops bnx2x_vf_ethtool_ops = {
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
index 95dc36543548..7636e3c18771 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_fw_defs.h
@@ -10,170 +10,170 @@
 #ifndef BNX2X_FW_DEFS_H
 #define BNX2X_FW_DEFS_H
 
-#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[148].base)
+#define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base)
 #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
-        (IRO[147].base + ((assertListEntry) * IRO[147].m1))
+        (IRO[151].base + ((assertListEntry) * IRO[151].m1))
 #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \
-        (IRO[153].base + (((pfId)>>1) * IRO[153].m1) + (((pfId)&1) * \
-        IRO[153].m2))
+        (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \
+        IRO[157].m2))
 #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \
-        (IRO[154].base + (((pfId)>>1) * IRO[154].m1) + (((pfId)&1) * \
-        IRO[154].m2))
+        (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \
+        IRO[158].m2))
 #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \
-        (IRO[159].base + ((funcId) * IRO[159].m1))
+        (IRO[163].base + ((funcId) * IRO[163].m1))
 #define CSTORM_FUNC_EN_OFFSET(funcId) \
-        (IRO[149].base + ((funcId) * IRO[149].m1))
+        (IRO[153].base + ((funcId) * IRO[153].m1))
 #define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \
-        (IRO[139].base + ((hcIndex) * IRO[139].m1) + ((sbId) * IRO[139].m2))
+        (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2))
 #define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \
-        (IRO[138].base + (((hcIndex)>>2) * IRO[138].m1) + (((hcIndex)&3) \
-        * IRO[138].m2) + ((sbId) * IRO[138].m3))
-#define CSTORM_IGU_MODE_OFFSET (IRO[157].base)
+        (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \
+        * IRO[142].m2) + ((sbId) * IRO[142].m3))
+#define CSTORM_IGU_MODE_OFFSET (IRO[161].base)
 #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
-        (IRO[317].base + ((pfId) * IRO[317].m1))
+        (IRO[323].base + ((pfId) * IRO[323].m1))
 #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
-        (IRO[318].base + ((pfId) * IRO[318].m1))
+        (IRO[324].base + ((pfId) * IRO[324].m1))
 #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \
-        (IRO[310].base + ((pfId) * IRO[310].m1) + ((iscsiEqId) * IRO[310].m2))
+        (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2))
 #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \
-        (IRO[312].base + ((pfId) * IRO[312].m1) + ((iscsiEqId) * IRO[312].m2))
+        (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2))
 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \
-        (IRO[311].base + ((pfId) * IRO[311].m1) + ((iscsiEqId) * IRO[311].m2))
+        (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2))
 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \
-        (IRO[313].base + ((pfId) * IRO[313].m1) + ((iscsiEqId) * IRO[313].m2))
+        (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2))
 #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \
-        (IRO[309].base + ((pfId) * IRO[309].m1) + ((iscsiEqId) * IRO[309].m2))
-#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
         (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2))
+#define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \
+        (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2))
 #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \
-        (IRO[314].base + ((pfId) * IRO[314].m1) + ((iscsiEqId) * IRO[314].m2))
+        (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2))
 #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
-        (IRO[316].base + ((pfId) * IRO[316].m1))
+        (IRO[322].base + ((pfId) * IRO[322].m1))
 #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
-        (IRO[308].base + ((pfId) * IRO[308].m1))
+        (IRO[314].base + ((pfId) * IRO[314].m1))
 #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
-        (IRO[307].base + ((pfId) * IRO[307].m1))
+        (IRO[313].base + ((pfId) * IRO[313].m1))
 #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
-        (IRO[306].base + ((pfId) * IRO[306].m1))
+        (IRO[312].base + ((pfId) * IRO[312].m1))
 #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
-        (IRO[151].base + ((funcId) * IRO[151].m1))
+        (IRO[155].base + ((funcId) * IRO[155].m1))
 #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \
-        (IRO[142].base + ((pfId) * IRO[142].m1))
+        (IRO[146].base + ((pfId) * IRO[146].m1))
 #define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \
-        (IRO[143].base + ((pfId) * IRO[143].m1))
+        (IRO[147].base + ((pfId) * IRO[147].m1))
 #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \
-        (IRO[141].base + ((pfId) * IRO[141].m1))
-#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[141].size)
+        (IRO[145].base + ((pfId) * IRO[145].m1))
+#define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size)
 #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \
-        (IRO[144].base + ((pfId) * IRO[144].m1))
-#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[144].size)
+        (IRO[148].base + ((pfId) * IRO[148].m1))
+#define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size)
 #define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \
-        (IRO[136].base + ((sbId) * IRO[136].m1) + ((hcIndex) * IRO[136].m2))
+        (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2))
 #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \
-        (IRO[133].base + ((sbId) * IRO[133].m1))
+        (IRO[137].base + ((sbId) * IRO[137].m1))
 #define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \
-        (IRO[134].base + ((sbId) * IRO[134].m1))
+        (IRO[138].base + ((sbId) * IRO[138].m1))
 #define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \
-        (IRO[135].base + ((sbId) * IRO[135].m1) + ((hcIndex) * IRO[135].m2))
+        (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2))
 #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \
-        (IRO[132].base + ((sbId) * IRO[132].m1))
-#define CSTORM_STATUS_BLOCK_SIZE (IRO[132].size)
+        (IRO[136].base + ((sbId) * IRO[136].m1))
+#define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size)
 #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \
-        (IRO[137].base + ((sbId) * IRO[137].m1))
-#define CSTORM_SYNC_BLOCK_SIZE (IRO[137].size)
+        (IRO[141].base + ((sbId) * IRO[141].m1))
+#define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size)
 #define CSTORM_VF_PF_CHANNEL_STATE_OFFSET(vfId) \
-        (IRO[155].base + ((vfId) * IRO[155].m1))
+        (IRO[159].base + ((vfId) * IRO[159].m1))
 #define CSTORM_VF_PF_CHANNEL_VALID_OFFSET(vfId) \
-        (IRO[156].base + ((vfId) * IRO[156].m1))
+        (IRO[160].base + ((vfId) * IRO[160].m1))
 #define CSTORM_VF_TO_PF_OFFSET(funcId) \
-        (IRO[150].base + ((funcId) * IRO[150].m1))
+        (IRO[154].base + ((funcId) * IRO[154].m1))
 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \
-        (IRO[203].base + ((pfId) * IRO[203].m1))
+        (IRO[207].base + ((pfId) * IRO[207].m1))
 #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base)
 #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \
         (IRO[101].base + ((assertListEntry) * IRO[101].m1))
 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \
-        (IRO[201].base + ((pfId) * IRO[201].m1))
+        (IRO[205].base + ((pfId) * IRO[205].m1))
 #define TSTORM_FUNC_EN_OFFSET(funcId) \
-        (IRO[103].base + ((funcId) * IRO[103].m1))
+        (IRO[107].base + ((funcId) * IRO[107].m1))
 #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
-        (IRO[272].base + ((pfId) * IRO[272].m1))
+        (IRO[278].base + ((pfId) * IRO[278].m1))
 #define TSTORM_ISCSI_L2_ISCSI_OOO_CID_TABLE_OFFSET(pfId) \
-        (IRO[273].base + ((pfId) * IRO[273].m1))
+        (IRO[279].base + ((pfId) * IRO[279].m1))
 #define TSTORM_ISCSI_L2_ISCSI_OOO_CLIENT_ID_TABLE_OFFSET(pfId) \
-        (IRO[274].base + ((pfId) * IRO[274].m1))
+        (IRO[280].base + ((pfId) * IRO[280].m1))
 #define TSTORM_ISCSI_L2_ISCSI_OOO_PROD_OFFSET(pfId) \
-        (IRO[275].base + ((pfId) * IRO[275].m1))
+        (IRO[281].base + ((pfId) * IRO[281].m1))
 #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
-        (IRO[271].base + ((pfId) * IRO[271].m1))
+        (IRO[277].base + ((pfId) * IRO[277].m1))
 #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
-        (IRO[270].base + ((pfId) * IRO[270].m1))
+        (IRO[276].base + ((pfId) * IRO[276].m1))
 #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
-        (IRO[269].base + ((pfId) * IRO[269].m1))
+        (IRO[275].base + ((pfId) * IRO[275].m1))
 #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
-        (IRO[268].base + ((pfId) * IRO[268].m1))
+        (IRO[274].base + ((pfId) * IRO[274].m1))
 #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \
-        (IRO[278].base + ((pfId) * IRO[278].m1))
+        (IRO[284].base + ((pfId) * IRO[284].m1))
 #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
-        (IRO[264].base + ((pfId) * IRO[264].m1))
+        (IRO[270].base + ((pfId) * IRO[270].m1))
 #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
-        (IRO[265].base + ((pfId) * IRO[265].m1))
+        (IRO[271].base + ((pfId) * IRO[271].m1))
 #define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \
-        (IRO[266].base + ((pfId) * IRO[266].m1))
+        (IRO[272].base + ((pfId) * IRO[272].m1))
 #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \
-        (IRO[267].base + ((pfId) * IRO[267].m1))
+        (IRO[273].base + ((pfId) * IRO[273].m1))
 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \
-        (IRO[202].base + ((pfId) * IRO[202].m1))
+        (IRO[206].base + ((pfId) * IRO[206].m1))
 #define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
-        (IRO[105].base + ((funcId) * IRO[105].m1))
+        (IRO[109].base + ((funcId) * IRO[109].m1))
 #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \
-        (IRO[217].base + ((pfId) * IRO[217].m1))
+        (IRO[223].base + ((pfId) * IRO[223].m1))
 #define TSTORM_VF_TO_PF_OFFSET(funcId) \
-        (IRO[104].base + ((funcId) * IRO[104].m1))
-#define USTORM_AGG_DATA_OFFSET (IRO[206].base)
-#define USTORM_AGG_DATA_SIZE (IRO[206].size)
-#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[177].base)
+        (IRO[108].base + ((funcId) * IRO[108].m1))
+#define USTORM_AGG_DATA_OFFSET (IRO[212].base)
+#define USTORM_AGG_DATA_SIZE (IRO[212].size)
+#define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base)
 #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \
-        (IRO[176].base + ((assertListEntry) * IRO[176].m1))
+        (IRO[180].base + ((assertListEntry) * IRO[180].m1))
 #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \
-        (IRO[183].base + ((portId) * IRO[183].m1))
+        (IRO[187].base + ((portId) * IRO[187].m1))
 #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \
-        (IRO[319].base + ((pfId) * IRO[319].m1))
+        (IRO[325].base + ((pfId) * IRO[325].m1))
 #define USTORM_FUNC_EN_OFFSET(funcId) \
-        (IRO[178].base + ((funcId) * IRO[178].m1))
+        (IRO[182].base + ((funcId) * IRO[182].m1))
 #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \
-        (IRO[283].base + ((pfId) * IRO[283].m1))
+        (IRO[289].base + ((pfId) * IRO[289].m1))
 #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \
-        (IRO[284].base + ((pfId) * IRO[284].m1))
+        (IRO[290].base + ((pfId) * IRO[290].m1))
 #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \
-        (IRO[288].base + ((pfId) * IRO[288].m1))
+        (IRO[294].base + ((pfId) * IRO[294].m1))
 #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \
-        (IRO[285].base + ((pfId) * IRO[285].m1))
+        (IRO[291].base + ((pfId) * IRO[291].m1))
 #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
-        (IRO[281].base + ((pfId) * IRO[281].m1))
+        (IRO[287].base + ((pfId) * IRO[287].m1))
 #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
-        (IRO[280].base + ((pfId) * IRO[280].m1))
+        (IRO[286].base + ((pfId) * IRO[286].m1))
 #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
-        (IRO[279].base + ((pfId) * IRO[279].m1))
+        (IRO[285].base + ((pfId) * IRO[285].m1))
 #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
-        (IRO[282].base + ((pfId) * IRO[282].m1))
+        (IRO[288].base + ((pfId) * IRO[288].m1))
 #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \
-        (IRO[286].base + ((pfId) * IRO[286].m1))
+        (IRO[292].base + ((pfId) * IRO[292].m1))
 #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \
-        (IRO[287].base + ((pfId) * IRO[287].m1))
+        (IRO[293].base + ((pfId) * IRO[293].m1))
 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \
-        (IRO[182].base + ((pfId) * IRO[182].m1))
+        (IRO[186].base + ((pfId) * IRO[186].m1))
 #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
-        (IRO[180].base + ((funcId) * IRO[180].m1))
+        (IRO[184].base + ((funcId) * IRO[184].m1))
 #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \
-        (IRO[209].base + ((portId) * IRO[209].m1) + ((clientId) * \
-        IRO[209].m2))
+        (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \
+        IRO[215].m2))
 #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \
-        (IRO[210].base + ((qzoneId) * IRO[210].m1))
-#define USTORM_TPA_BTR_OFFSET (IRO[207].base)
-#define USTORM_TPA_BTR_SIZE (IRO[207].size)
+        (IRO[216].base + ((qzoneId) * IRO[216].m1))
+#define USTORM_TPA_BTR_OFFSET (IRO[213].base)
+#define USTORM_TPA_BTR_SIZE (IRO[213].size)
 #define USTORM_VF_TO_PF_OFFSET(funcId) \
-        (IRO[179].base + ((funcId) * IRO[179].m1))
+        (IRO[183].base + ((funcId) * IRO[183].m1))
 #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base)
 #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base)
 #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base)
@@ -186,39 +186,39 @@
 #define XSTORM_FUNC_EN_OFFSET(funcId) \
         (IRO[47].base + ((funcId) * IRO[47].m1))
 #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \
-        (IRO[296].base + ((pfId) * IRO[296].m1))
+        (IRO[302].base + ((pfId) * IRO[302].m1))
 #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \
-        (IRO[299].base + ((pfId) * IRO[299].m1))
+        (IRO[305].base + ((pfId) * IRO[305].m1))
 #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \
-        (IRO[300].base + ((pfId) * IRO[300].m1))
+        (IRO[306].base + ((pfId) * IRO[306].m1))
 #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \
-        (IRO[301].base + ((pfId) * IRO[301].m1))
+        (IRO[307].base + ((pfId) * IRO[307].m1))
 #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \
-        (IRO[302].base + ((pfId) * IRO[302].m1))
+        (IRO[308].base + ((pfId) * IRO[308].m1))
 #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \
-        (IRO[303].base + ((pfId) * IRO[303].m1))
+        (IRO[309].base + ((pfId) * IRO[309].m1))
 #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \
-        (IRO[304].base + ((pfId) * IRO[304].m1))
+        (IRO[310].base + ((pfId) * IRO[310].m1))
 #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \
-        (IRO[305].base + ((pfId) * IRO[305].m1))
+        (IRO[311].base + ((pfId) * IRO[311].m1))
 #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \
-        (IRO[295].base + ((pfId) * IRO[295].m1))
+        (IRO[301].base + ((pfId) * IRO[301].m1))
 #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \
-        (IRO[294].base + ((pfId) * IRO[294].m1))
+        (IRO[300].base + ((pfId) * IRO[300].m1))
 #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \
-        (IRO[293].base + ((pfId) * IRO[293].m1))
+        (IRO[299].base + ((pfId) * IRO[299].m1))
 #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \
-        (IRO[298].base + ((pfId) * IRO[298].m1))
+        (IRO[304].base + ((pfId) * IRO[304].m1))
 #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \
-        (IRO[297].base + ((pfId) * IRO[297].m1))
+        (IRO[303].base + ((pfId) * IRO[303].m1))
 #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \
-        (IRO[292].base + ((pfId) * IRO[292].m1))
+        (IRO[298].base + ((pfId) * IRO[298].m1))
 #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \
-        (IRO[291].base + ((pfId) * IRO[291].m1))
+        (IRO[297].base + ((pfId) * IRO[297].m1))
 #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \
-        (IRO[290].base + ((pfId) * IRO[290].m1))
+        (IRO[296].base + ((pfId) * IRO[296].m1))
 #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \
-        (IRO[289].base + ((pfId) * IRO[289].m1))
+        (IRO[295].base + ((pfId) * IRO[295].m1))
 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \
         (IRO[44].base + ((pfId) * IRO[44].m1))
 #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \
@@ -231,16 +231,19 @@
 #define XSTORM_SPQ_PROD_OFFSET(funcId) \
         (IRO[31].base + ((funcId) * IRO[31].m1))
 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \
-        (IRO[211].base + ((portId) * IRO[211].m1))
+        (IRO[217].base + ((portId) * IRO[217].m1))
 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \
-        (IRO[212].base + ((portId) * IRO[212].m1))
+        (IRO[218].base + ((portId) * IRO[218].m1))
 #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \
-        (IRO[214].base + (((pfId)>>1) * IRO[214].m1) + (((pfId)&1) * \
-        IRO[214].m2))
+        (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \
+        IRO[220].m2))
 #define XSTORM_VF_TO_PF_OFFSET(funcId) \
         (IRO[48].base + ((funcId) * IRO[48].m1))
 #define COMMON_ASM_INVALID_ASSERT_OPCODE 0x0
 
+/* eth hsi version */
+#define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2)
+
 /* Ethernet Ring parameters */
 #define X_ETH_LOCAL_RING_SIZE 13
 #define FIRST_BD_IN_PKT 0
@@ -356,6 +359,7 @@
 #define XSEMI_CLK1_RESUL_CHIP (1e-3)
 
 #define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6))
+#define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6))
 
 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/
 
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
index c4daa068f1db..3e0621acdf05 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
@@ -2881,8 +2881,8 @@ struct afex_stats {
 };
 
 #define BCM_5710_FW_MAJOR_VERSION                       7
-#define BCM_5710_FW_MINOR_VERSION                       8
-#define BCM_5710_FW_REVISION_VERSION            19
+#define BCM_5710_FW_MINOR_VERSION                       10
+#define BCM_5710_FW_REVISION_VERSION            51
 #define BCM_5710_FW_ENGINEERING_VERSION         0
 #define BCM_5710_FW_COMPILE_FLAGS                       1
 
@@ -3451,6 +3451,7 @@ enum classify_rule {
         CLASSIFY_RULE_OPCODE_MAC,
         CLASSIFY_RULE_OPCODE_VLAN,
         CLASSIFY_RULE_OPCODE_PAIR,
+        CLASSIFY_RULE_OPCODE_VXLAN,
         MAX_CLASSIFY_RULE
 };
 
@@ -3480,7 +3481,8 @@ struct client_init_general_data {
         u8 func_id;
         u8 cos;
         u8 traffic_type;
-        u32 reserved0;
+        u8 fp_hsi_ver;
+        u8 reserved0[3];
 };
 
 
@@ -3550,7 +3552,9 @@ struct client_init_rx_data {
         __le16 rx_cos_mask;
         __le16 silent_vlan_value;
         __le16 silent_vlan_mask;
-        __le32 reserved6[2];
+        u8 handle_ptp_pkts_flg;
+        u8 reserved6[3];
+        __le32 reserved7;
 };
 
 /*
@@ -3581,7 +3585,7 @@ struct client_init_tx_data {
         u8 tunnel_lso_inc_ip_id;
         u8 refuse_outband_vlan_flg;
         u8 tunnel_non_lso_pcsum_location;
-        u8 reserved1;
+        u8 tunnel_non_lso_outer_ip_csum_location;
 };
 
 /*
@@ -3619,7 +3623,9 @@ struct client_update_ramrod_data {
         u8 refuse_outband_vlan_change_flg;
         u8 tx_switching_flg;
         u8 tx_switching_change_flg;
-        __le32 reserved1;
+        u8 handle_ptp_pkts_flg;
+        u8 handle_ptp_pkts_change_flg;
+        __le16 reserved1;
         __le32 echo;
 };
 
@@ -3639,6 +3645,11 @@ struct double_regpair {
         u32 regpair1_hi;
 };
 
+/* 2nd parse bd type used in ethernet tx BDs */
+enum eth_2nd_parse_bd_type {
+        ETH_2ND_PARSE_BD_TYPE_LSO_TUNNEL,
+        MAX_ETH_2ND_PARSE_BD_TYPE
+};
 
 /*
  * Ethernet address typesm used in ethernet tx BDs
@@ -3724,12 +3735,25 @@ struct eth_classify_vlan_cmd {
 };
 
 /*
+ * Command for adding/removing a VXLAN classification rule
+ */
+struct eth_classify_vxlan_cmd {
+        struct eth_classify_cmd_header header;
+        __le32 vni;
+        __le16 inner_mac_lsb;
+        __le16 inner_mac_mid;
+        __le16 inner_mac_msb;
+        __le16 reserved1;
+};
+
+/*
  * union for eth classification rule
  */
 union eth_classify_rule_cmd {
         struct eth_classify_mac_cmd mac;
         struct eth_classify_vlan_cmd vlan;
         struct eth_classify_pair_cmd pair;
+        struct eth_classify_vxlan_cmd vxlan;
 };
 
 /*
@@ -3835,8 +3859,10 @@ struct eth_fast_path_rx_cqe {
 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4
 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5)
 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5
-#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6)
-#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_PTP_PKT (0x1<<6)
+#define ETH_FAST_PATH_RX_CQE_PTP_PKT_SHIFT 6
+#define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x1<<7)
+#define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 7
         u8 status_flags;
 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0)
 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0
@@ -3907,6 +3933,13 @@ struct eth_filter_rules_ramrod_data {
         struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT];
 };
 
+/* Hsi version */
+enum eth_fp_hsi_ver {
+        ETH_FP_HSI_VER_0,
+        ETH_FP_HSI_VER_1,
+        ETH_FP_HSI_VER_2,
+        MAX_ETH_FP_HSI_VER
+};
 
 /*
  * parameters for eth classification configuration ramrod
@@ -3955,29 +3988,17 @@ struct eth_mac_addresses {
 
 /* tunneling related data */
 struct eth_tunnel_data {
-#if defined(__BIG_ENDIAN)
-        __le16 dst_mid;
-        __le16 dst_lo;
-#elif defined(__LITTLE_ENDIAN)
         __le16 dst_lo;
         __le16 dst_mid;
-#endif
-#if defined(__BIG_ENDIAN)
-        __le16 reserved0;
-        __le16 dst_hi;
-#elif defined(__LITTLE_ENDIAN)
         __le16 dst_hi;
-        __le16 reserved0;
-#endif
-#if defined(__BIG_ENDIAN)
-        u8 reserved1;
-        u8 ip_hdr_start_inner_w;
-        __le16 pseudo_csum;
-#elif defined(__LITTLE_ENDIAN)
+        __le16 fw_ip_hdr_csum;
         __le16 pseudo_csum;
         u8 ip_hdr_start_inner_w;
-        u8 reserved1;
-#endif
+        u8 flags;
+#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0)
+#define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0
+#define ETH_TUNNEL_DATA_RESERVED (0x7F<<1)
+#define ETH_TUNNEL_DATA_RESERVED_SHIFT 1
 };
 
 /* union for mac addresses and for tunneling data.
@@ -4064,31 +4085,41 @@ enum eth_rss_mode {
  */
 struct eth_rss_update_ramrod_data {
         u8 rss_engine_id;
-        u8 capabilities;
+        u8 rss_mode;
+        __le16 capabilities;
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0)
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1)
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2)
 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3)
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4)
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5)
-#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5
-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6)
-#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7)
-#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY (0x1<<3)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_VXLAN_CAPABILITY_SHIFT 3
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<4)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 4
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<5)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 5
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<6)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 6
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY (0x1<<7)
+#define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_VXLAN_CAPABILITY_SHIFT 7
+#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<8)
+#define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 8
+#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY (0x1<<9)
+#define ETH_RSS_UPDATE_RAMROD_DATA_NVGRE_KEY_ENTROPY_CAPABILITY_SHIFT 9
+#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY (0x1<<10)
+#define ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY_SHIFT 10
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<11)
+#define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 11
+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED (0xF<<12)
+#define ETH_RSS_UPDATE_RAMROD_DATA_RESERVED_SHIFT 12
         u8 rss_result_mask;
-        u8 rss_mode;
-        __le16 udp_4tuple_dst_port_mask;
-        __le16 udp_4tuple_dst_port_value;
+        u8 reserved3;
+        __le16 reserved4;
         u8 indirection_table[T_ETH_INDIRECTION_TABLE_SIZE];
         __le32 rss_key[T_ETH_RSS_KEY];
         __le32 echo;
-        __le32 reserved3;
+        __le32 reserved5;
 };
 
 
@@ -4260,10 +4291,10 @@ enum eth_tunnel_lso_inc_ip_id {
 /* In case tunnel exist and L4 checksum offload,
  * the pseudo checksum location, on packet or on BD.
  */
-enum eth_tunnel_non_lso_pcsum_location {
-        PCSUM_ON_PKT,
-        PCSUM_ON_BD,
-        MAX_ETH_TUNNEL_NON_LSO_PCSUM_LOCATION
+enum eth_tunnel_non_lso_csum_location {
+        CSUM_ON_PKT,
+        CSUM_ON_BD,
+        MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION
 };
 
 /*
@@ -4310,8 +4341,10 @@ struct eth_tx_start_bd {
         __le16 vlan_or_ethertype;
         struct eth_tx_bd_flags bd_flags;
         u8 general_data;
-#define ETH_TX_START_BD_HDR_NBDS (0xF<<0)
+#define ETH_TX_START_BD_HDR_NBDS (0x7<<0)
 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0
+#define ETH_TX_START_BD_NO_ADDED_TAGS (0x1<<3)
+#define ETH_TX_START_BD_NO_ADDED_TAGS_SHIFT 3
 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4)
 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4
 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5)
@@ -4387,8 +4420,8 @@ struct eth_tx_parse_2nd_bd {
         __le16 global_data;
 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0)
 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0
-#define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER (0x1<<4)
-#define ETH_TX_PARSE_2ND_BD_IP_HDR_TYPE_OUTER_SHIFT 4
+#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4)
+#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4
 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5)
 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5
 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6)
@@ -4397,9 +4430,14 @@ struct eth_tx_parse_2nd_bd {
 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7
 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8)
 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8
-#define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x7<<13)
-#define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 13
-        __le16 reserved1;
+#define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13)
+#define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13
+        u8 bd_type;
+#define ETH_TX_PARSE_2ND_BD_TYPE (0xF<<0)
+#define ETH_TX_PARSE_2ND_BD_TYPE_SHIFT 0
+#define ETH_TX_PARSE_2ND_BD_RESERVED2 (0xF<<4)
+#define ETH_TX_PARSE_2ND_BD_RESERVED2_SHIFT 4
+        u8 reserved3;
         u8 tcp_flags;
 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0)
 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0
@@ -4417,7 +4455,7 @@ struct eth_tx_parse_2nd_bd {
 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6
 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7)
 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7
-        u8 reserved2;
+        u8 reserved4;
         u8 tunnel_udp_hdr_start_w;
         u8 fw_ip_hdr_to_payload_w;
         __le16 fw_ip_csum_wo_len_flags_frag;
@@ -5205,10 +5243,18 @@ struct function_start_data {
         u8 path_id;
         u8 network_cos_mode;
         u8 dmae_cmd_id;
-        u8 gre_tunnel_mode;
-        u8 gre_tunnel_rss;
-        u8 nvgre_clss_en;
-        __le16 reserved1[2];
+        u8 tunnel_mode;
+        u8 gre_tunnel_type;
+        u8 tunn_clss_en;
+        u8 inner_gre_rss_en;
+        u8 sd_accept_mf_clss_fail;
+        __le16 vxlan_dst_port;
+        __le16 sd_accept_mf_clss_fail_ethtype;
+        __le16 sd_vlan_eth_type;
+        u8 sd_vlan_force_pri_flg;
+        u8 sd_vlan_force_pri_val;
+        u8 sd_accept_mf_clss_fail_match_ethtype;
+        u8 no_added_tags;
 };
 
 struct function_update_data {
@@ -5225,12 +5271,20 @@ struct function_update_data {
         u8 tx_switch_suspend_change_flg;
         u8 tx_switch_suspend;
         u8 echo;
+        u8 update_tunn_cfg_flg;
+        u8 tunnel_mode;
+        u8 gre_tunnel_type;
+        u8 tunn_clss_en;
+        u8 inner_gre_rss_en;
+        __le16 vxlan_dst_port;
+        u8 sd_vlan_force_pri_change_flg;
+        u8 sd_vlan_force_pri_flg;
+        u8 sd_vlan_force_pri_val;
+        u8 sd_vlan_tag_change_flg;
+        u8 sd_vlan_eth_type_change_flg;
         u8 reserved1;
-        u8 update_gre_cfg_flg;
-        u8 gre_tunnel_mode;
-        u8 gre_tunnel_rss;
-        u8 nvgre_clss_en;
-        u32 reserved3;
+        __le16 sd_vlan_tag;
+        __le16 sd_vlan_eth_type;
 };
 
 /*
@@ -5259,17 +5313,9 @@ struct fw_version {
 #define __FW_VERSION_RESERVED_SHIFT 4
 };
 
-/* GRE RSS Mode */
-enum gre_rss_mode {
-        GRE_OUTER_HEADERS_RSS,
-        GRE_INNER_HEADERS_RSS,
-        NVGRE_KEY_ENTROPY_RSS,
-        MAX_GRE_RSS_MODE
-};
 
 /* GRE Tunnel Mode */
 enum gre_tunnel_type {
-        NO_GRE_TUNNEL,
         NVGRE_TUNNEL,
         L2GRE_TUNNEL,
         IPGRE_TUNNEL,
@@ -5442,6 +5488,7 @@ enum ip_ver {
  * Malicious VF error ID
  */
 enum malicious_vf_error_id {
+        MALICIOUS_VF_NO_ERROR,
         VF_PF_CHANNEL_NOT_READY,
         ETH_ILLEGAL_BD_LENGTHS,
         ETH_PACKET_TOO_SHORT,
@@ -5602,6 +5649,16 @@ struct protocol_common_spe {
         union protocol_common_specific_data data;
 };
 
+/* The data for the Set Timesync Ramrod */
+struct set_timesync_ramrod_data {
+        u8 drift_adjust_cmd;
+        u8 offset_cmd;
+        u8 add_sub_drift_adjust_value;
+        u8 drift_adjust_value;
+        u32 drift_adjust_period;
+        struct regpair offset_delta;
+};
+
 /*
  * The send queue element
  */
@@ -5724,10 +5781,38 @@ struct tstorm_vf_zone_data {
         struct regpair reserved;
 };
 
+/* Add or Subtract Value for Set Timesync Ramrod */
+enum ts_add_sub_value {
+        TS_SUB_VALUE,
+        TS_ADD_VALUE,
+        MAX_TS_ADD_SUB_VALUE
+};
 
-/*
- * zone A per-queue data
- */
+/* Drift-Adjust Commands for Set Timesync Ramrod */
+enum ts_drift_adjust_cmd {
+        TS_DRIFT_ADJUST_KEEP,
+        TS_DRIFT_ADJUST_SET,
+        TS_DRIFT_ADJUST_RESET,
+        MAX_TS_DRIFT_ADJUST_CMD
+};
+
+/* Offset Commands for Set Timesync Ramrod */
+enum ts_offset_cmd {
+        TS_OFFSET_KEEP,
+        TS_OFFSET_INC,
+        TS_OFFSET_DEC,
+        MAX_TS_OFFSET_CMD
+};
+
+/* Tunnel Mode */
+enum tunnel_mode {
+        TUNN_MODE_NONE,
+        TUNN_MODE_VXLAN,
+        TUNN_MODE_GRE,
+        MAX_TUNNEL_MODE
+};
+
+ /* zone A per-queue data */
 struct ustorm_queue_zone_data {
         struct ustorm_eth_rx_producers eth_rx_producers;
         struct regpair reserved[3];
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
index d1c093dcb054..32e2444ab5e1 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c
@@ -41,6 +41,7 @@
 #include <linux/ethtool.h>
 #include <linux/mii.h>
 #include <linux/if_vlan.h>
+#include <linux/crash_dump.h>
 #include <net/ip.h>
 #include <net/ipv6.h>
 #include <net/tcp.h>
@@ -63,7 +64,6 @@
 #include "bnx2x_vfpf.h"
 #include "bnx2x_dcb.h"
 #include "bnx2x_sp.h"
-
 #include <linux/firmware.h>
 #include "bnx2x_fw_file_hdr.h"
 /* FW files */
@@ -290,6 +290,8 @@ static int bnx2x_set_storm_rx_mode(struct bnx2x *bp);
 * General service functions
 ****************************************************************************/
 
+static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr);
+
 static void __storm_memset_dma_mapping(struct bnx2x *bp,
                                        u32 addr, dma_addr_t mapping)
 {
@@ -523,6 +525,7 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
          * as long as this code is called both from syscall context and
          * from ndo_set_rx_mode() flow that may be called from BH.
          */
+
         spin_lock_bh(&bp->dmae_lock);
 
         /* reset completion */
@@ -551,7 +554,9 @@ int bnx2x_issue_dmae_with_comp(struct bnx2x *bp, struct dmae_command *dmae,
         }
 
 unlock:
+
         spin_unlock_bh(&bp->dmae_lock);
+
         return rc;
 }
 
@@ -646,119 +651,98 @@ static void bnx2x_write_dmae_phys_len(struct bnx2x *bp, dma_addr_t phys_addr,
         bnx2x_write_dmae(bp, phys_addr + offset, addr + offset, len);
 }
 
+enum storms {
+           XSTORM,
+           TSTORM,
+           CSTORM,
+           USTORM,
+           MAX_STORMS
+};
+
+#define STORMS_NUM 4
+#define REGS_IN_ENTRY 4
+
+static inline int bnx2x_get_assert_list_entry(struct bnx2x *bp,
+                                              enum storms storm,
+                                              int entry)
+{
+        switch (storm) {
+        case XSTORM:
+                return XSTORM_ASSERT_LIST_OFFSET(entry);
+        case TSTORM:
+                return TSTORM_ASSERT_LIST_OFFSET(entry);
+        case CSTORM:
+                return CSTORM_ASSERT_LIST_OFFSET(entry);
+        case USTORM:
+                return USTORM_ASSERT_LIST_OFFSET(entry);
+        case MAX_STORMS:
+        default:
+                BNX2X_ERR("unknown storm\n");
+        }
+        return -EINVAL;
+}
+
 static int bnx2x_mc_assert(struct bnx2x *bp)
 {
         char last_idx;
-        int i, rc = 0;
-        u32 row0, row1, row2, row3;
-
-        /* XSTORM */
-        last_idx = REG_RD8(bp, BAR_XSTRORM_INTMEM +
-                           XSTORM_ASSERT_LIST_INDEX_OFFSET);
-        if (last_idx)
-                BNX2X_ERR("XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
-
-        /* print the asserts */
-        for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
-
-                row0 = REG_RD(bp, BAR_XSTRORM_INTMEM +
-                              XSTORM_ASSERT_LIST_OFFSET(i));
-                row1 = REG_RD(bp, BAR_XSTRORM_INTMEM +
-                              XSTORM_ASSERT_LIST_OFFSET(i) + 4);
-                row2 = REG_RD(bp, BAR_XSTRORM_INTMEM +
-                              XSTORM_ASSERT_LIST_OFFSET(i) + 8);
-                row3 = REG_RD(bp, BAR_XSTRORM_INTMEM +
-                              XSTORM_ASSERT_LIST_OFFSET(i) + 12);
-
-                if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
-                        BNX2X_ERR("XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
-                                  i, row3, row2, row1, row0);
-                        rc++;
-                } else {
-                        break;
-                }
-        }
-
-        /* TSTORM */
-        last_idx = REG_RD8(bp, BAR_TSTRORM_INTMEM +
-                           TSTORM_ASSERT_LIST_INDEX_OFFSET);
-        if (last_idx)
-                BNX2X_ERR("TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
-
-        /* print the asserts */
-        for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
-
-                row0 = REG_RD(bp, BAR_TSTRORM_INTMEM +
-                              TSTORM_ASSERT_LIST_OFFSET(i));
-                row1 = REG_RD(bp, BAR_TSTRORM_INTMEM +
-                              TSTORM_ASSERT_LIST_OFFSET(i) + 4);
-                row2 = REG_RD(bp, BAR_TSTRORM_INTMEM +
-                              TSTORM_ASSERT_LIST_OFFSET(i) + 8);
-                row3 = REG_RD(bp, BAR_TSTRORM_INTMEM +
-                              TSTORM_ASSERT_LIST_OFFSET(i) + 12);
-
-                if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
-                        BNX2X_ERR("TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
-                                  i, row3, row2, row1, row0);
-                        rc++;
-                } else {
-                        break;
-                }
-        }
+        int i, j, rc = 0;
+        enum storms storm;
+        u32 regs[REGS_IN_ENTRY];
+        u32 bar_storm_intmem[STORMS_NUM] = {
+                BAR_XSTRORM_INTMEM,
+                BAR_TSTRORM_INTMEM,
+                BAR_CSTRORM_INTMEM,
+                BAR_USTRORM_INTMEM
+        };
+        u32 storm_assert_list_index[STORMS_NUM] = {
+                XSTORM_ASSERT_LIST_INDEX_OFFSET,
+                TSTORM_ASSERT_LIST_INDEX_OFFSET,
+                CSTORM_ASSERT_LIST_INDEX_OFFSET,
+                USTORM_ASSERT_LIST_INDEX_OFFSET
+        };
+        char *storms_string[STORMS_NUM] = {
+                "XSTORM",
+                "TSTORM",
+                "CSTORM",
+                "USTORM"
+        };
 
-        /* CSTORM */
-        last_idx = REG_RD8(bp, BAR_CSTRORM_INTMEM +
-                           CSTORM_ASSERT_LIST_INDEX_OFFSET);
-        if (last_idx)
-                BNX2X_ERR("CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
-
-        /* print the asserts */
-        for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
-
-                row0 = REG_RD(bp, BAR_CSTRORM_INTMEM +
-                              CSTORM_ASSERT_LIST_OFFSET(i));
-                row1 = REG_RD(bp, BAR_CSTRORM_INTMEM +
-                              CSTORM_ASSERT_LIST_OFFSET(i) + 4);
-                row2 = REG_RD(bp, BAR_CSTRORM_INTMEM +
-                              CSTORM_ASSERT_LIST_OFFSET(i) + 8);
-                row3 = REG_RD(bp, BAR_CSTRORM_INTMEM +
-                              CSTORM_ASSERT_LIST_OFFSET(i) + 12);
-
-                if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
-                        BNX2X_ERR("CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
-                                  i, row3, row2, row1, row0);
-                        rc++;
-                } else {
-                        break;
+        for (storm = XSTORM; storm < MAX_STORMS; storm++) {
+                last_idx = REG_RD8(bp, bar_storm_intmem[storm] +
+                                   storm_assert_list_index[storm]);
+                if (last_idx)
+                        BNX2X_ERR("%s_ASSERT_LIST_INDEX 0x%x\n",
+                                  storms_string[storm], last_idx);
+
+                /* print the asserts */
+                for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
+                        /* read a single assert entry */
+                        for (j = 0; j < REGS_IN_ENTRY; j++)
+                                regs[j] = REG_RD(bp, bar_storm_intmem[storm] +
+                                          bnx2x_get_assert_list_entry(bp,
+                                                                      storm,
+                                                                      i) +
+                                          sizeof(u32) * j);
+
+                        /* log entry if it contains a valid assert */
+                        if (regs[0] != COMMON_ASM_INVALID_ASSERT_OPCODE) {
+                                BNX2X_ERR("%s_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
+                                          storms_string[storm], i, regs[3],
+                                          regs[2], regs[1], regs[0]);
+                                rc++;
+                        } else {
+                                break;
+                        }
                 }
         }
 
-        /* USTORM */
-        last_idx = REG_RD8(bp, BAR_USTRORM_INTMEM +
-                           USTORM_ASSERT_LIST_INDEX_OFFSET);
-        if (last_idx)
-                BNX2X_ERR("USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx);
-
-        /* print the asserts */
-        for (i = 0; i < STROM_ASSERT_ARRAY_SIZE; i++) {
-
-                row0 = REG_RD(bp, BAR_USTRORM_INTMEM +
-                              USTORM_ASSERT_LIST_OFFSET(i));
-                row1 = REG_RD(bp, BAR_USTRORM_INTMEM +
-                              USTORM_ASSERT_LIST_OFFSET(i) + 4);
-                row2 = REG_RD(bp, BAR_USTRORM_INTMEM +
-                              USTORM_ASSERT_LIST_OFFSET(i) + 8);
-                row3 = REG_RD(bp, BAR_USTRORM_INTMEM +
-                              USTORM_ASSERT_LIST_OFFSET(i) + 12);
-
-                if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) {
-                        BNX2X_ERR("USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n",
-                                  i, row3, row2, row1, row0);
-                        rc++;
-                } else {
-                        break;
-                }
-        }
+        BNX2X_ERR("Chip Revision: %s, FW Version: %d_%d_%d\n",
+                  CHIP_IS_E1(bp) ? "everest1" :
+                  CHIP_IS_E1H(bp) ? "everest1h" :
+                  CHIP_IS_E2(bp) ? "everest2" : "everest3",
+                  BCM_5710_FW_MAJOR_VERSION,
+                  BCM_5710_FW_MINOR_VERSION,
+                  BCM_5710_FW_REVISION_VERSION);
 
         return rc;
 }
@@ -983,6 +967,12 @@ void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
                 u32 *sb_data_p;
                 struct bnx2x_fp_txdata txdata;
 
+                if (!bp->fp)
+                        break;
+
+                if (!fp->rx_cons_sb)
+                        continue;
+
                 /* Rx */
                 BNX2X_ERR("fp%d: rx_bd_prod(0x%x)  rx_bd_cons(0x%x)  rx_comp_prod(0x%x)  rx_comp_cons(0x%x)  *rx_cons_sb(0x%x)\n",
                           i, fp->rx_bd_prod, fp->rx_bd_cons,
@@ -995,7 +985,14 @@ void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
                 /* Tx */
                 for_each_cos_in_tx_queue(fp, cos)
                 {
+                        if (!fp->txdata_ptr[cos])
+                                break;
+
                         txdata = *fp->txdata_ptr[cos];
+
+                        if (!txdata.tx_cons_sb)
+                                continue;
+
                         BNX2X_ERR("fp%d: tx_pkt_prod(0x%x)  tx_pkt_cons(0x%x)  tx_bd_prod(0x%x)  tx_bd_cons(0x%x)  *tx_cons_sb(0x%x)\n",
                                   i, txdata.tx_pkt_prod,
                                   txdata.tx_pkt_cons, txdata.tx_bd_prod,
@@ -1097,6 +1094,12 @@ void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
         for_each_valid_rx_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
 
+                if (!bp->fp)
+                        break;
+
+                if (!fp->rx_cons_sb)
+                        continue;
+
                 start = RX_BD(le16_to_cpu(*fp->rx_cons_sb) - 10);
                 end = RX_BD(le16_to_cpu(*fp->rx_cons_sb) + 503);
                 for (j = start; j != end; j = RX_BD(j + 1)) {
@@ -1130,9 +1133,19 @@ void bnx2x_panic_dump(struct bnx2x *bp, bool disable_int)
         /* Tx */
         for_each_valid_tx_queue(bp, i) {
                 struct bnx2x_fastpath *fp = &bp->fp[i];
+
+                if (!bp->fp)
+                        break;
+
                 for_each_cos_in_tx_queue(fp, cos) {
                         struct bnx2x_fp_txdata *txdata = fp->txdata_ptr[cos];
 
+                        if (!fp->txdata_ptr[cos])
+                                break;
+
+                        if (!txdata->tx_cons_sb)
+                                continue;
+
                         start = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) - 10);
                         end = TX_BD(le16_to_cpu(*txdata->tx_cons_sb) + 245);
                         for (j = start; j != end; j = TX_BD(j + 1)) {
@@ -2071,8 +2084,6 @@ int bnx2x_get_gpio(struct bnx2x *bp, int gpio_num, u8 port)
         else
                 value = 0;
 
-        DP(NETIF_MSG_LINK, "pin %d  value 0x%x\n", gpio_num, value);
-
         return value;
 }
 
@@ -4678,7 +4689,7 @@ static bool bnx2x_check_blocks_with_parity2(struct bnx2x *bp, u32 sig,
         for (i = 0; sig; i++) {
                 cur_bit = (0x1UL << i);
                 if (sig & cur_bit) {
-                        res |= true; /* Each bit is real error! */
+                        res = true; /* Each bit is real error! */
                         if (print) {
                                 switch (cur_bit) {
                                 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR:
@@ -4757,21 +4768,21 @@ static bool bnx2x_check_blocks_with_parity3(struct bnx2x *bp, u32 sig,
                                         _print_next_block((*par_num)++,
                                                           "MCP ROM");
                                 *global = true;
-                                res |= true;
+                                res = true;
                                 break;
                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY:
                                 if (print)
                                         _print_next_block((*par_num)++,
                                                           "MCP UMP RX");
                                 *global = true;
-                                res |= true;
+                                res = true;
                                 break;
                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY:
                                 if (print)
                                         _print_next_block((*par_num)++,
                                                           "MCP UMP TX");
                                 *global = true;
-                                res |= true;
+                                res = true;
                                 break;
                         case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY:
                                 if (print)
@@ -4803,7 +4814,7 @@ static bool bnx2x_check_blocks_with_parity4(struct bnx2x *bp, u32 sig,
         for (i = 0; sig; i++) {
                 cur_bit = (0x1UL << i);
                 if (sig & cur_bit) {
-                        res |= true; /* Each bit is real error! */
+                        res = true; /* Each bit is real error! */
                         if (print) {
                                 switch (cur_bit) {
                                 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR:
@@ -5452,6 +5463,14 @@ static void bnx2x_eq_int(struct bnx2x *bp)
                                 break;
 
                         goto next_spqe;
+
+                case EVENT_RING_OPCODE_SET_TIMESYNC:
+                        DP(BNX2X_MSG_SP | BNX2X_MSG_PTP,
+                           "got set_timesync ramrod completion\n");
+                        if (f_obj->complete_cmd(bp, f_obj,
+                                                BNX2X_F_CMD_SET_TIMESYNC))
+                                break;
+                        goto next_spqe;
                 }
 
                 switch (opcode | bp->state) {
@@ -6102,7 +6121,7 @@ static int bnx2x_fill_accept_flags(struct bnx2x *bp, u32 rx_mode,
         }
 
         /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */
-        if (bp->rx_mode != BNX2X_RX_MODE_NONE) {
+        if (rx_mode != BNX2X_RX_MODE_NONE) {
                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, rx_accept_flags);
                 __set_bit(BNX2X_ACCEPT_ANY_VLAN, tx_accept_flags);
         }
@@ -7662,7 +7681,11 @@ static inline int bnx2x_func_switch_update(struct bnx2x *bp, int suspend)
         func_params.cmd = BNX2X_F_CMD_SWITCH_UPDATE;
 
         /* Function parameters */
-        switch_update_params->suspend = suspend;
+        __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+                  &switch_update_params->changes);
+        if (suspend)
+                __set_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
+                          &switch_update_params->changes);
 
         rc = bnx2x_func_state_change(bp, &func_params);
 
@@ -9025,7 +9048,7 @@ static int bnx2x_func_wait_started(struct bnx2x *bp)
                 struct bnx2x_func_state_params func_params = {NULL};
 
                 DP(NETIF_MSG_IFDOWN,
-                   "Hmmm... Unexpected function state! Forcing STARTED-->TX_ST0PPED-->STARTED\n");
+                   "Hmmm... Unexpected function state! Forcing STARTED-->TX_STOPPED-->STARTED\n");
 
                 func_params.f_obj = &bp->func_obj;
                 __set_bit(RAMROD_DRV_CLR_ONLY,
@@ -9044,6 +9067,48 @@ static int bnx2x_func_wait_started(struct bnx2x *bp)
         return 0;
 }
 
+static void bnx2x_disable_ptp(struct bnx2x *bp)
+{
+        int port = BP_PORT(bp);
+
+        /* Disable sending PTP packets to host */
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
+               NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
+
+        /* Reset PTP event detection rules */
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
+               NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
+               NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
+        REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
+               NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
+        REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
+               NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
+
+        /* Disable the PTP feature */
+        REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
+               NIG_REG_P0_PTP_EN, 0x0);
+}
+
+/* Called during unload, to stop PTP-related stuff */
+void bnx2x_stop_ptp(struct bnx2x *bp)
+{
+        /* Cancel PTP work queue. Should be done after the Tx queues are
+         * drained to prevent additional scheduling.
+         */
+        cancel_work_sync(&bp->ptp_task);
+
+        if (bp->ptp_tx_skb) {
+                dev_kfree_skb_any(bp->ptp_tx_skb);
+                bp->ptp_tx_skb = NULL;
+        }
+
+        /* Disable PTP in HW */
+        bnx2x_disable_ptp(bp);
+
+        DP(BNX2X_MSG_PTP, "PTP stop ended successfully\n");
+}
+
 void bnx2x_chip_cleanup(struct bnx2x *bp, int unload_mode, bool keep_link)
 {
         int port = BP_PORT(bp);
@@ -9162,6 +9227,13 @@ unload_error:
 #endif
         }
 
+        /* stop_ptp should be after the Tx queues are drained to prevent
+         * scheduling to the cancelled PTP work queue. It should also be after
+         * function stop ramrod is sent, since as part of this ramrod FW access
+         * PTP registers.
+         */
+        bnx2x_stop_ptp(bp);
+
         /* Disable HW interrupts, NAPI */
         bnx2x_netif_stop(bp, 1);
         /* Delete all NAPI objects */
@@ -11900,7 +11972,7 @@ static int bnx2x_init_bp(struct bnx2x *bp)
         bp->disable_tpa = disable_tpa;
         bp->disable_tpa |= IS_MF_STORAGE_SD(bp) || IS_MF_FCOE_AFEX(bp);
         /* Reduce memory usage in kdump environment by disabling TPA */
-        bp->disable_tpa |= reset_devices;
+        bp->disable_tpa |= is_kdump_kernel();
 
         /* Set TPA flags */
         if (bp->disable_tpa) {
@@ -11976,6 +12048,9 @@ static int bnx2x_init_bp(struct bnx2x *bp)
 
         bp->dump_preset_idx = 1;
 
+        if (CHIP_IS_E3B0(bp))
+                bp->flags |= PTP_SUPPORTED;
+
         return rc;
 }
 
@@ -12308,13 +12383,17 @@ static int bnx2x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
         struct bnx2x *bp = netdev_priv(dev);
         struct mii_ioctl_data *mdio = if_mii(ifr);
 
-        DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
-           mdio->phy_id, mdio->reg_num, mdio->val_in);
-
         if (!netif_running(dev))
                 return -EAGAIN;
 
-        return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
+        switch (cmd) {
+        case SIOCSHWTSTAMP:
+                return bnx2x_hwtstamp_ioctl(bp, ifr);
+        default:
+                DP(NETIF_MSG_LINK, "ioctl: phy id 0x%x, reg 0x%x, val_in 0x%x\n",
+                   mdio->phy_id, mdio->reg_num, mdio->val_in);
+                return mdio_mii_ioctl(&bp->mdio, mdio, cmd);
+        }
 }
 
 #ifdef CONFIG_NET_POLL_CONTROLLER
@@ -12958,6 +13037,191 @@ static int set_is_vf(int chip_id)
         }
 }
 
+/* nig_tsgen registers relative address */
+#define tsgen_ctrl 0x0
+#define tsgen_freecount 0x10
+#define tsgen_synctime_t0 0x20
+#define tsgen_offset_t0 0x28
+#define tsgen_drift_t0 0x30
+#define tsgen_synctime_t1 0x58
+#define tsgen_offset_t1 0x60
+#define tsgen_drift_t1 0x68
+
+/* FW workaround for setting drift */
+static int bnx2x_send_update_drift_ramrod(struct bnx2x *bp, int drift_dir,
+                                          int best_val, int best_period)
+{
+        struct bnx2x_func_state_params func_params = {NULL};
+        struct bnx2x_func_set_timesync_params *set_timesync_params =
+                &func_params.params.set_timesync;
+
+        /* Prepare parameters for function state transitions */
+        __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
+        __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
+
+        func_params.f_obj = &bp->func_obj;
+        func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
+
+        /* Function parameters */
+        set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_SET;
+        set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
+        set_timesync_params->add_sub_drift_adjust_value =
+                drift_dir ? TS_ADD_VALUE : TS_SUB_VALUE;
+        set_timesync_params->drift_adjust_value = best_val;
+        set_timesync_params->drift_adjust_period = best_period;
+
+        return bnx2x_func_state_change(bp, &func_params);
+}
+
+static int bnx2x_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
+{
+        struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
+        int rc;
+        int drift_dir = 1;
+        int val, period, period1, period2, dif, dif1, dif2;
+        int best_dif = BNX2X_MAX_PHC_DRIFT, best_period = 0, best_val = 0;
+
+        DP(BNX2X_MSG_PTP, "PTP adjfreq called, ppb = %d\n", ppb);
+
+        if (!netif_running(bp->dev)) {
+                DP(BNX2X_MSG_PTP,
+                   "PTP adjfreq called while the interface is down\n");
+                return -EFAULT;
+        }
+
+        if (ppb < 0) {
+                ppb = -ppb;
+                drift_dir = 0;
+        }
+
+        if (ppb == 0) {
+                best_val = 1;
+                best_period = 0x1FFFFFF;
+        } else if (ppb >= BNX2X_MAX_PHC_DRIFT) {
+                best_val = 31;
+                best_period = 1;
+        } else {
+                /* Changed not to allow val = 8, 16, 24 as these values
+                 * are not supported in workaround.
+                 */
+                for (val = 0; val <= 31; val++) {
+                        if ((val & 0x7) == 0)
+                                continue;
+                        period1 = val * 1000000 / ppb;
+                        period2 = period1 + 1;
+                        if (period1 != 0)
+                                dif1 = ppb - (val * 1000000 / period1);
+                        else
+                                dif1 = BNX2X_MAX_PHC_DRIFT;
+                        if (dif1 < 0)
+                                dif1 = -dif1;
+                        dif2 = ppb - (val * 1000000 / period2);
+                        if (dif2 < 0)
+                                dif2 = -dif2;
+                        dif = (dif1 < dif2) ? dif1 : dif2;
+                        period = (dif1 < dif2) ? period1 : period2;
+                        if (dif < best_dif) {
+                                best_dif = dif;
+                                best_val = val;
+                                best_period = period;
+                        }
+                }
+        }
+
+        rc = bnx2x_send_update_drift_ramrod(bp, drift_dir, best_val,
+                                            best_period);
+        if (rc) {
+                BNX2X_ERR("Failed to set drift\n");
+                return -EFAULT;
+        }
+
+        DP(BNX2X_MSG_PTP, "Configrued val = %d, period = %d\n", best_val,
+           best_period);
+
+        return 0;
+}
+
+static int bnx2x_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
+{
+        struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
+        u64 now;
+
+        DP(BNX2X_MSG_PTP, "PTP adjtime called, delta = %llx\n", delta);
+
+        now = timecounter_read(&bp->timecounter);
+        now += delta;
+        /* Re-init the timecounter */
+        timecounter_init(&bp->timecounter, &bp->cyclecounter, now);
+
+        return 0;
+}
+
+static int bnx2x_ptp_gettime(struct ptp_clock_info *ptp, struct timespec *ts)
+{
+        struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
+        u64 ns;
+        u32 remainder;
+
+        ns = timecounter_read(&bp->timecounter);
+
+        DP(BNX2X_MSG_PTP, "PTP gettime called, ns = %llu\n", ns);
+
+        ts->tv_sec = div_u64_rem(ns, 1000000000ULL, &remainder);
+        ts->tv_nsec = remainder;
+
+        return 0;
+}
+
+static int bnx2x_ptp_settime(struct ptp_clock_info *ptp,
+                             const struct timespec *ts)
+{
+        struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
+        u64 ns;
+
+        ns = ts->tv_sec * 1000000000ULL;
+        ns += ts->tv_nsec;
+
+        DP(BNX2X_MSG_PTP, "PTP settime called, ns = %llu\n", ns);
+
+        /* Re-init the timecounter */
+        timecounter_init(&bp->timecounter, &bp->cyclecounter, ns);
+
+        return 0;
+}
+
+/* Enable (or disable) ancillary features of the phc subsystem */
+static int bnx2x_ptp_enable(struct ptp_clock_info *ptp,
+                            struct ptp_clock_request *rq, int on)
+{
+        struct bnx2x *bp = container_of(ptp, struct bnx2x, ptp_clock_info);
+
+        BNX2X_ERR("PHC ancillary features are not supported\n");
+        return -ENOTSUPP;
+}
+
+void bnx2x_register_phc(struct bnx2x *bp)
+{
+        /* Fill the ptp_clock_info struct and register PTP clock*/
+        bp->ptp_clock_info.owner = THIS_MODULE;
+        snprintf(bp->ptp_clock_info.name, 16, "%s", bp->dev->name);
+        bp->ptp_clock_info.max_adj = BNX2X_MAX_PHC_DRIFT; /* In PPB */
+        bp->ptp_clock_info.n_alarm = 0;
+        bp->ptp_clock_info.n_ext_ts = 0;
+        bp->ptp_clock_info.n_per_out = 0;
+        bp->ptp_clock_info.pps = 0;
+        bp->ptp_clock_info.adjfreq = bnx2x_ptp_adjfreq;
+        bp->ptp_clock_info.adjtime = bnx2x_ptp_adjtime;
+        bp->ptp_clock_info.gettime = bnx2x_ptp_gettime;
+        bp->ptp_clock_info.settime = bnx2x_ptp_settime;
+        bp->ptp_clock_info.enable = bnx2x_ptp_enable;
+
+        bp->ptp_clock = ptp_clock_register(&bp->ptp_clock_info, &bp->pdev->dev);
+        if (IS_ERR(bp->ptp_clock)) {
+                bp->ptp_clock = NULL;
+                BNX2X_ERR("PTP clock registeration failed\n");
+        }
+}
+
 static int bnx2x_init_one(struct pci_dev *pdev,
                                     const struct pci_device_id *ent)
 {
@@ -13129,6 +13393,8 @@ static int bnx2x_init_one(struct pci_dev *pdev,
                        "Unknown",
                        dev->base_addr, bp->pdev->irq, dev->dev_addr);
 
+        bnx2x_register_phc(bp);
+
         return 0;
 
 init_one_exit:
@@ -13155,6 +13421,11 @@ static void __bnx2x_remove(struct pci_dev *pdev,
                            struct bnx2x *bp,
                            bool remove_netdev)
 {
+        if (bp->ptp_clock) {
+                ptp_clock_unregister(bp->ptp_clock);
+                bp->ptp_clock = NULL;
+        }
+
         /* Delete storage MAC address */
         if (!NO_FCOE(bp)) {
                 rtnl_lock();
@@ -14136,3 +14407,332 @@ int bnx2x_pretend_func(struct bnx2x *bp, u16 pretend_func_val)
         REG_RD(bp, pretend_reg);
         return 0;
 }
+
+static void bnx2x_ptp_task(struct work_struct *work)
+{
+        struct bnx2x *bp = container_of(work, struct bnx2x, ptp_task);
+        int port = BP_PORT(bp);
+        u32 val_seq;
+        u64 timestamp, ns;
+        struct skb_shared_hwtstamps shhwtstamps;
+
+        /* Read Tx timestamp registers */
+        val_seq = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
+                         NIG_REG_P0_TLLH_PTP_BUF_SEQID);
+        if (val_seq & 0x10000) {
+                /* There is a valid timestamp value */
+                timestamp = REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_MSB :
+                                   NIG_REG_P0_TLLH_PTP_BUF_TS_MSB);
+                timestamp <<= 32;
+                timestamp |= REG_RD(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_TS_LSB :
+                                    NIG_REG_P0_TLLH_PTP_BUF_TS_LSB);
+                /* Reset timestamp register to allow new timestamp */
+                REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
+                       NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
+                ns = timecounter_cyc2time(&bp->timecounter, timestamp);
+
+                memset(&shhwtstamps, 0, sizeof(shhwtstamps));
+                shhwtstamps.hwtstamp = ns_to_ktime(ns);
+                skb_tstamp_tx(bp->ptp_tx_skb, &shhwtstamps);
+                dev_kfree_skb_any(bp->ptp_tx_skb);
+                bp->ptp_tx_skb = NULL;
+
+                DP(BNX2X_MSG_PTP, "Tx timestamp, timestamp cycles = %llu, ns = %llu\n",
+                   timestamp, ns);
+        } else {
+                DP(BNX2X_MSG_PTP, "There is no valid Tx timestamp yet\n");
+                /* Reschedule to keep checking for a valid timestamp value */
+                schedule_work(&bp->ptp_task);
+        }
+}
+
+void bnx2x_set_rx_ts(struct bnx2x *bp, struct sk_buff *skb)
+{
+        int port = BP_PORT(bp);
+        u64 timestamp, ns;
+
+        timestamp = REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB :
+                            NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB);
+        timestamp <<= 32;
+        timestamp |= REG_RD(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB :
+                            NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB);
+
+        /* Reset timestamp register to allow new timestamp */
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
+               NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
+
+        ns = timecounter_cyc2time(&bp->timecounter, timestamp);
+
+        skb_hwtstamps(skb)->hwtstamp = ns_to_ktime(ns);
+
+        DP(BNX2X_MSG_PTP, "Rx timestamp, timestamp cycles = %llu, ns = %llu\n",
+           timestamp, ns);
+}
+
+/* Read the PHC */
+static cycle_t bnx2x_cyclecounter_read(const struct cyclecounter *cc)
+{
+        struct bnx2x *bp = container_of(cc, struct bnx2x, cyclecounter);
+        int port = BP_PORT(bp);
+        u32 wb_data[2];
+        u64 phc_cycles;
+
+        REG_RD_DMAE(bp, port ? NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t1 :
+                    NIG_REG_TIMESYNC_GEN_REG + tsgen_synctime_t0, wb_data, 2);
+        phc_cycles = wb_data[1];
+        phc_cycles = (phc_cycles << 32) + wb_data[0];
+
+        DP(BNX2X_MSG_PTP, "PHC read cycles = %llu\n", phc_cycles);
+
+        return phc_cycles;
+}
+
+static void bnx2x_init_cyclecounter(struct bnx2x *bp)
+{
+        memset(&bp->cyclecounter, 0, sizeof(bp->cyclecounter));
+        bp->cyclecounter.read = bnx2x_cyclecounter_read;
+        bp->cyclecounter.mask = CLOCKSOURCE_MASK(64);
+        bp->cyclecounter.shift = 1;
+        bp->cyclecounter.mult = 1;
+}
+
+static int bnx2x_send_reset_timesync_ramrod(struct bnx2x *bp)
+{
+        struct bnx2x_func_state_params func_params = {NULL};
+        struct bnx2x_func_set_timesync_params *set_timesync_params =
+                &func_params.params.set_timesync;
+
+        /* Prepare parameters for function state transitions */
+        __set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags);
+        __set_bit(RAMROD_RETRY, &func_params.ramrod_flags);
+
+        func_params.f_obj = &bp->func_obj;
+        func_params.cmd = BNX2X_F_CMD_SET_TIMESYNC;
+
+        /* Function parameters */
+        set_timesync_params->drift_adjust_cmd = TS_DRIFT_ADJUST_RESET;
+        set_timesync_params->offset_cmd = TS_OFFSET_KEEP;
+
+        return bnx2x_func_state_change(bp, &func_params);
+}
+
+int bnx2x_enable_ptp_packets(struct bnx2x *bp)
+{
+        struct bnx2x_queue_state_params q_params;
+        int rc, i;
+
+        /* send queue update ramrod to enable PTP packets */
+        memset(&q_params, 0, sizeof(q_params));
+        __set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags);
+        q_params.cmd = BNX2X_Q_CMD_UPDATE;
+        __set_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
+                  &q_params.params.update.update_flags);
+        __set_bit(BNX2X_Q_UPDATE_PTP_PKTS,
+                  &q_params.params.update.update_flags);
+
+        /* send the ramrod on all the queues of the PF */
+        for_each_eth_queue(bp, i) {
+                struct bnx2x_fastpath *fp = &bp->fp[i];
+
+                /* Set the appropriate Queue object */
+                q_params.q_obj = &bnx2x_sp_obj(bp, fp).q_obj;
+
+                /* Update the Queue state */
+                rc = bnx2x_queue_state_change(bp, &q_params);
+                if (rc) {
+                        BNX2X_ERR("Failed to enable PTP packets\n");
+                        return rc;
+                }
+        }
+
+        return 0;
+}
+
+int bnx2x_configure_ptp_filters(struct bnx2x *bp)
+{
+        int port = BP_PORT(bp);
+        int rc;
+
+        if (!bp->hwtstamp_ioctl_called)
+                return 0;
+
+        switch (bp->tx_type) {
+        case HWTSTAMP_TX_ON:
+                bp->flags |= TX_TIMESTAMPING_EN;
+                REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
+                       NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x6AA);
+                REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
+                       NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3EEE);
+                break;
+        case HWTSTAMP_TX_ONESTEP_SYNC:
+                BNX2X_ERR("One-step timestamping is not supported\n");
+                return -ERANGE;
+        }
+
+        switch (bp->rx_filter) {
+        case HWTSTAMP_FILTER_NONE:
+                break;
+        case HWTSTAMP_FILTER_ALL:
+        case HWTSTAMP_FILTER_SOME:
+                bp->rx_filter = HWTSTAMP_FILTER_NONE;
+                break;
+        case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
+        case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
+        case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
+                bp->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
+                /* Initialize PTP detection for UDP/IPv4 events */
+                REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
+                       NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EE);
+                REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
+                       NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFE);
+                break;
+        case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
+        case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
+        case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
+                bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L4_EVENT;
+                /* Initialize PTP detection for UDP/IPv4 or UDP/IPv6 events */
+                REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
+                       NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7EA);
+                REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
+                       NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FEE);
+                break;
+        case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
+        case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
+        case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
+                bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
+                /* Initialize PTP detection L2 events */
+                REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
+                       NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6BF);
+                REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
+                       NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EFF);
+
+                break;
+        case HWTSTAMP_FILTER_PTP_V2_EVENT:
+        case HWTSTAMP_FILTER_PTP_V2_SYNC:
+        case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
+                bp->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
+                /* Initialize PTP detection L2, UDP/IPv4 or UDP/IPv6 events */
+                REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
+                       NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x6AA);
+                REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
+                       NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3EEE);
+                break;
+        }
+
+        /* Indicate to FW that this PF expects recorded PTP packets */
+        rc = bnx2x_enable_ptp_packets(bp);
+        if (rc)
+                return rc;
+
+        /* Enable sending PTP packets to host */
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
+               NIG_REG_P0_LLH_PTP_TO_HOST, 0x1);
+
+        return 0;
+}
+
+static int bnx2x_hwtstamp_ioctl(struct bnx2x *bp, struct ifreq *ifr)
+{
+        struct hwtstamp_config config;
+        int rc;
+
+        DP(BNX2X_MSG_PTP, "HWTSTAMP IOCTL called\n");
+
+        if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
+                return -EFAULT;
+
+        DP(BNX2X_MSG_PTP, "Requested tx_type: %d, requested rx_filters = %d\n",
+           config.tx_type, config.rx_filter);
+
+        if (config.flags) {
+                BNX2X_ERR("config.flags is reserved for future use\n");
+                return -EINVAL;
+        }
+
+        bp->hwtstamp_ioctl_called = 1;
+        bp->tx_type = config.tx_type;
+        bp->rx_filter = config.rx_filter;
+
+        rc = bnx2x_configure_ptp_filters(bp);
+        if (rc)
+                return rc;
+
+        config.rx_filter = bp->rx_filter;
+
+        return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
+                -EFAULT : 0;
+}
+
+/* Configrues HW for PTP */
+static int bnx2x_configure_ptp(struct bnx2x *bp)
+{
+        int rc, port = BP_PORT(bp);
+        u32 wb_data[2];
+
+        /* Reset PTP event detection rules - will be configured in the IOCTL */
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_PARAM_MASK :
+               NIG_REG_P0_LLH_PTP_PARAM_MASK, 0x7FF);
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_RULE_MASK :
+               NIG_REG_P0_LLH_PTP_RULE_MASK, 0x3FFF);
+        REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_PARAM_MASK :
+               NIG_REG_P0_TLLH_PTP_PARAM_MASK, 0x7FF);
+        REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_RULE_MASK :
+               NIG_REG_P0_TLLH_PTP_RULE_MASK, 0x3FFF);
+
+        /* Disable PTP packets to host - will be configured in the IOCTL*/
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_TO_HOST :
+               NIG_REG_P0_LLH_PTP_TO_HOST, 0x0);
+
+        /* Enable the PTP feature */
+        REG_WR(bp, port ? NIG_REG_P1_PTP_EN :
+               NIG_REG_P0_PTP_EN, 0x3F);
+
+        /* Enable the free-running counter */
+        wb_data[0] = 0;
+        wb_data[1] = 0;
+        REG_WR_DMAE(bp, NIG_REG_TIMESYNC_GEN_REG + tsgen_ctrl, wb_data, 2);
+
+        /* Reset drift register (offset register is not reset) */
+        rc = bnx2x_send_reset_timesync_ramrod(bp);
+        if (rc) {
+                BNX2X_ERR("Failed to reset PHC drift register\n");
+                return -EFAULT;
+        }
+
+        /* Reset possibly old timestamps */
+        REG_WR(bp, port ? NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID :
+               NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID, 0x10000);
+        REG_WR(bp, port ? NIG_REG_P1_TLLH_PTP_BUF_SEQID :
+               NIG_REG_P0_TLLH_PTP_BUF_SEQID, 0x10000);
+
+        return 0;
+}
+
+/* Called during load, to initialize PTP-related stuff */
+void bnx2x_init_ptp(struct bnx2x *bp)
+{
+        int rc;
+
+        /* Configure PTP in HW */
+        rc = bnx2x_configure_ptp(bp);
+        if (rc) {
+                BNX2X_ERR("Stopping PTP initialization\n");
+                return;
+        }
+
+        /* Init work queue for Tx timestamping */
+        INIT_WORK(&bp->ptp_task, bnx2x_ptp_task);
+
+        /* Init cyclecounter and timecounter. This is done only in the first
+         * load. If done in every load, PTP application will fail when doing
+         * unload / load (e.g. MTU change) while it is running.
+         */
+        if (!bp->timecounter_init_done) {
+                bnx2x_init_cyclecounter(bp);
+                timecounter_init(&bp->timecounter, &bp->cyclecounter,
+                                 ktime_to_ns(ktime_get_real()));
+                bp->timecounter_init_done = 1;
+        }
+
+        DP(BNX2X_MSG_PTP, "PTP initialization ended successfully\n");
+}
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
index 2beb5430b876..b0779d773343 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_reg.h
@@ -2182,6 +2182,45 @@
 #define NIG_REG_P0_HWPFC_ENABLE                          0x18078
 #define NIG_REG_P0_LLH_FUNC_MEM2                                 0x18480
 #define NIG_REG_P0_LLH_FUNC_MEM2_ENABLE                  0x18440
+/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Writing a 1 to bit 16
+ * will clear the buffer.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_SEQID                        0x1875c
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_LSB                       0x18754
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_LLH_PTP_HOST_BUF_TS_MSB                       0x18758
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P0_LLH_PTP_PARAM_MASK                            0x187a0
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
+ * packets only and require that the packet is IPv4 for the rules to match.
+ * Note that rules 4-7 are for IPv6 packets only and require that the packet
+ * is IPv6 for the rules to match.
+ */
+#define NIG_REG_P0_LLH_PTP_RULE_MASK                             0x187a4
+/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
+#define NIG_REG_P0_LLH_PTP_TO_HOST                               0x187ac
 /* [RW 1] Input enable for RX MAC interface. */
 #define NIG_REG_P0_MAC_IN_EN                                     0x185ac
 /* [RW 1] Output enable for TX MAC interface */
@@ -2194,6 +2233,17 @@
  * priority field is extracted from the outer-most VLAN in receive packet.
  * Only COS 0 and COS 1 are supported in E2. */
 #define NIG_REG_P0_PKT_PRIORITY_TO_COS                           0x18054
+/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
+ * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
+ * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
+ * frame format in timesync event detection on RX side. Bit 3 enables
+ * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
+ * detection on TX side. Bit 5 enables V2 frame format in timesync event
+ * detection on TX side. Note that for HW to detect PTP packet and extract
+ * data from the packet, at least one of the version bits of that traffic
+ * direction has to be enabled.
+ */
+#define NIG_REG_P0_PTP_EN                                        0x18788
 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
  * priority is mapped to COS 0 when the corresponding mask bit is 1. More
  * than one bit may be set; allowing multiple priorities to be mapped to one
@@ -2300,7 +2350,46 @@
  * Ethernet header. */
 #define NIG_REG_P1_HDRS_AFTER_BASIC                              0x1818c
 #define NIG_REG_P1_LLH_FUNC_MEM2                                 0x184c0
-#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE                  0x18460
+#define NIG_REG_P1_LLH_FUNC_MEM2_ENABLE                  0x18460a
+/* [RW 17] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. Bits [15:0] return the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Writing a 1 to bit 16
+ * will clear the buffer.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_SEQID                        0x18774
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_LSB                       0x1876c
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * the host. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_LLH_PTP_HOST_BUF_TS_MSB                       0x18770
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P1_LLH_PTP_PARAM_MASK                            0x187c8
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules. Note that rules 0-3 are for IPv4
+ * packets only and require that the packet is IPv4 for the rules to match.
+ * Note that rules 4-7 are for IPv6 packets only and require that the packet
+ * is IPv6 for the rules to match.
+ */
+#define NIG_REG_P1_LLH_PTP_RULE_MASK                             0x187cc
+/* [RW 1] Set to 1 to enable PTP packets to be forwarded to the host. */
+#define NIG_REG_P1_LLH_PTP_TO_HOST                               0x187d4
 /* [RW 32] Specify the client number to be assigned to each priority of the
  * strict priority arbiter. This register specifies bits 31:0 of the 36-bit
  * value. Priority 0 is the highest priority. Bits [3:0] are for priority 0
@@ -2342,6 +2431,17 @@
  * priority field is extracted from the outer-most VLAN in receive packet.
  * Only COS 0 and COS 1 are supported in E2. */
 #define NIG_REG_P1_PKT_PRIORITY_TO_COS                           0x181a8
+/* [RW 6] Enable for TimeSync feature. Bits [2:0] are for RX side. Bits
+ * [5:3] are for TX side. Bit 0 enables TimeSync on RX side. Bit 1 enables
+ * V1 frame format in timesync event detection on RX side. Bit 2 enables V2
+ * frame format in timesync event detection on RX side. Bit 3 enables
+ * TimeSync on TX side. Bit 4 enables V1 frame format in timesync event
+ * detection on TX side. Bit 5 enables V2 frame format in timesync event
+ * detection on TX side. Note that for HW to detect PTP packet and extract
+ * data from the packet, at least one of the version bits of that traffic
+ * direction has to be enabled.
+ */
+#define NIG_REG_P1_PTP_EN                                        0x187b0
 /* [RW 16] Bit-map indicating which SAFC/PFC priorities to map to COS 0. A
  * priority is mapped to COS 0 when the corresponding mask bit is 1. More
  * than one bit may be set; allowing multiple priorities to be mapped to one
@@ -2361,6 +2461,78 @@
 #define NIG_REG_P1_RX_MACFIFO_EMPTY                              0x1858c
 /* [R 1] TLLH FIFO is empty. */
 #define NIG_REG_P1_TLLH_FIFO_EMPTY                               0x18338
+/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Bit 17 indicates that
+ * the sequence ID is valid and it is waiting for the TX timestamp value.
+ * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
+ * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_SEQID                            0x187e0
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_TS_LSB                           0x187d8
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P0_TLLH_PTP_BUF_TS_MSB                           0x187dc
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P0_TLLH_PTP_PARAM_MASK                           0x187f0
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules.
+ */
+#define NIG_REG_P0_TLLH_PTP_RULE_MASK                            0x187f4
+/* [RW 19] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * TX side. Bits [15:0] reflect the sequence ID of the packet. Bit 16
+ * indicates the validity of the data in the buffer. Bit 17 indicates that
+ * the sequence ID is valid and it is waiting for the TX timestamp value.
+ * Bit 18 indicates whether the timestamp is from a SW request (value of 1)
+ * or HW request (value of 0). Writing a 1 to bit 16 will clear the buffer.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_SEQID                            0x187ec
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the lower 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_TS_LSB                           0x187e4
+/* [R 32] Packet TimeSync information that is buffered in 1-deep FIFOs for
+ * MCP. This location returns the upper 32 bits of timestamp value.
+ */
+#define NIG_REG_P1_TLLH_PTP_BUF_TS_MSB                           0x187e8
+/* [RW 11] Mask register for the various parameters used in determining PTP
+ * packet presence. Set each bit to 1 to mask out the particular parameter.
+ * 0-IPv4 DA 0 of 224.0.1.129. 1-IPv4 DA 1 of 224.0.0.107. 2-IPv6 DA 0 of
+ * 0xFF0*:0:0:0:0:0:0:181. 3-IPv6 DA 1 of 0xFF02:0:0:0:0:0:0:6B. 4-UDP
+ * destination port 0 of 319. 5-UDP destination port 1 of 320. 6-MAC
+ * Ethertype 0 of 0x88F7. 7-configurable MAC Ethertype 1. 8-MAC DA 0 of
+ * 0x01-1B-19-00-00-00. 9-MAC DA 1 of 0x01-80-C2-00-00-0E. 10-configurable
+ * MAC DA 2. The reset default is set to mask out all parameters.
+ */
+#define NIG_REG_P1_TLLH_PTP_PARAM_MASK                           0x187f8
+/* [RW 14] Mask regiser for the rules used in detecting PTP packets. Set
+ * each bit to 1 to mask out that particular rule. 0-{IPv4 DA 0; UDP DP 0} .
+ * 1-{IPv4 DA 0; UDP DP 1} . 2-{IPv4 DA 1; UDP DP 0} . 3-{IPv4 DA 1; UDP DP
+ * 1} . 4-{IPv6 DA 0; UDP DP 0} . 5-{IPv6 DA 0; UDP DP 1} . 6-{IPv6 DA 1;
+ * UDP DP 0} . 7-{IPv6 DA 1; UDP DP 1} . 8-{MAC DA 0; Ethertype 0} . 9-{MAC
+ * DA 1; Ethertype 0} . 10-{MAC DA 0; Ethertype 1} . 11-{MAC DA 1; Ethertype
+ * 1} . 12-{MAC DA 2; Ethertype 0} . 13-{MAC DA 2; Ethertype 1} . The reset
+ * default is to mask out all of the rules.
+ */
+#define NIG_REG_P1_TLLH_PTP_RULE_MASK                            0x187fc
 /* [RW 32] Specify which of the credit registers the client is to be mapped
  * to. This register specifies bits 31:0 of the 36-bit value. Bits[3:0] are
  * for client 0; bits [35:32] are for client 8. For clients that are not
@@ -2513,6 +2685,10 @@
    swap is equal to SPIO pin that inputs from ifmux_serdes_swap. If 1 then
    ort swap is equal to ~nig_registers_port_swap.port_swap */
 #define NIG_REG_STRAP_OVERRIDE                                   0x10398
+/* [WB 64] Addresses for TimeSync related registers in the timesync
+ * generator sub-module.
+ */
+#define NIG_REG_TIMESYNC_GEN_REG                                 0x18800
 /* [RW 1] output enable for RX_XCM0 IF */
 #define NIG_REG_XCM0_OUT_EN                                      0x100f0
 /* [RW 1] output enable for RX_XCM1 IF */
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
index b1936044767a..19d0c1152434 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c
@@ -4019,6 +4019,7 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
         struct bnx2x_raw_obj *r = &o->raw;
         struct eth_rss_update_ramrod_data *data =
                 (struct eth_rss_update_ramrod_data *)(r->rdata);
+        u16 caps = 0;
         u8 rss_mode = 0;
         int rc;
 
@@ -4042,28 +4043,34 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
 
         /* RSS capabilities */
         if (test_bit(BNX2X_RSS_IPV4, &p->rss_flags))
-                data->capabilities |=
-                        ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
+                caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY;
 
         if (test_bit(BNX2X_RSS_IPV4_TCP, &p->rss_flags))
-                data->capabilities |=
-                        ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
+                caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY;
 
         if (test_bit(BNX2X_RSS_IPV4_UDP, &p->rss_flags))
-                data->capabilities |=
-                        ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
+                caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY;
 
         if (test_bit(BNX2X_RSS_IPV6, &p->rss_flags))
-                data->capabilities |=
-                        ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
+                caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY;
 
         if (test_bit(BNX2X_RSS_IPV6_TCP, &p->rss_flags))
-                data->capabilities |=
-                        ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
+                caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY;
 
         if (test_bit(BNX2X_RSS_IPV6_UDP, &p->rss_flags))
-                data->capabilities |=
-                        ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
+                caps |= ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY;
+
+        if (test_bit(BNX2X_RSS_GRE_INNER_HDRS, &p->rss_flags))
+                caps |= ETH_RSS_UPDATE_RAMROD_DATA_GRE_INNER_HDRS_CAPABILITY;
+
+        /* RSS keys */
+        if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
+                memcpy(&data->rss_key[0], &p->rss_key[0],
+                       sizeof(data->rss_key));
+                caps |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
+        }
+
+        data->capabilities = cpu_to_le16(caps);
 
         /* Hashing mask */
         data->rss_result_mask = p->rss_result_mask;
@@ -4084,13 +4091,6 @@ static int bnx2x_setup_rss(struct bnx2x *bp,
         if (netif_msg_ifup(bp))
                 bnx2x_debug_print_ind_table(bp, p);
 
-        /* RSS keys */
-        if (test_bit(BNX2X_RSS_SET_SRCH, &p->rss_flags)) {
-                memcpy(&data->rss_key[0], &p->rss_key[0],
-                       sizeof(data->rss_key));
-                data->capabilities |= ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY;
-        }
-
         /* No need for an explicit memory barrier here as long as we
          * ensure the ordering of writing to the SPQ element
          * and updating of the SPQ producer which involves a memory
@@ -4336,6 +4336,8 @@ static void bnx2x_q_fill_init_general_data(struct bnx2x *bp,
                 test_bit(BNX2X_Q_FLG_FCOE, flags) ?
                 LLFC_TRAFFIC_TYPE_FCOE : LLFC_TRAFFIC_TYPE_NW;
 
+        gen_data->fp_hsi_ver = ETH_FP_HSI_VERSION;
+
         DP(BNX2X_MSG_SP, "flags: active %d, cos %d, stats en %d\n",
            gen_data->activate_flg, gen_data->cos, gen_data->statistics_en_flg);
 }
@@ -4357,12 +4359,13 @@ static void bnx2x_q_fill_init_tx_data(struct bnx2x_queue_sp_obj *o,
                 test_bit(BNX2X_Q_FLG_ANTI_SPOOF, flags);
         tx_data->force_default_pri_flg =
                 test_bit(BNX2X_Q_FLG_FORCE_DEFAULT_PRI, flags);
-
+        tx_data->refuse_outband_vlan_flg =
+                test_bit(BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN, flags);
         tx_data->tunnel_lso_inc_ip_id =
                 test_bit(BNX2X_Q_FLG_TUN_INC_INNER_IP_ID, flags);
         tx_data->tunnel_non_lso_pcsum_location =
-                test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? PCSUM_ON_PKT :
-                                                                  PCSUM_ON_BD;
+                test_bit(BNX2X_Q_FLG_PCSUM_ON_PKT, flags) ? CSUM_ON_PKT :
+                                                            CSUM_ON_BD;
 
         tx_data->tx_status_block_id = params->fw_sb_id;
         tx_data->tx_sb_index_number = params->sb_cq_index;
@@ -4722,6 +4725,12 @@ static void bnx2x_q_fill_update_data(struct bnx2x *bp,
         data->tx_switching_change_flg =
                 test_bit(BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
                          &params->update_flags);
+
+        /* PTP */
+        data->handle_ptp_pkts_flg =
+                test_bit(BNX2X_Q_UPDATE_PTP_PKTS, &params->update_flags);
+        data->handle_ptp_pkts_change_flg =
+                test_bit(BNX2X_Q_UPDATE_PTP_PKTS_CHNG, &params->update_flags);
 }
 
 static inline int bnx2x_q_send_update(struct bnx2x *bp,
@@ -5376,6 +5385,10 @@ static int bnx2x_func_chk_transition(struct bnx2x *bp,
                          (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
                         next_state = BNX2X_F_STATE_STARTED;
 
+                else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
+                         (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
+                        next_state = BNX2X_F_STATE_STARTED;
+
                 else if (cmd == BNX2X_F_CMD_TX_STOP)
                         next_state = BNX2X_F_STATE_TX_STOPPED;
 
@@ -5385,6 +5398,10 @@ static int bnx2x_func_chk_transition(struct bnx2x *bp,
                     (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
                         next_state = BNX2X_F_STATE_TX_STOPPED;
 
+                else if ((cmd == BNX2X_F_CMD_SET_TIMESYNC) &&
+                         (!test_bit(BNX2X_F_CMD_STOP, &o->pending)))
+                        next_state = BNX2X_F_STATE_TX_STOPPED;
+
                 else if (cmd == BNX2X_F_CMD_TX_START)
                         next_state = BNX2X_F_STATE_STARTED;
 
@@ -5652,8 +5669,11 @@ static inline int bnx2x_func_send_start(struct bnx2x *bp,
         rdata->sd_vlan_tag      = cpu_to_le16(start_params->sd_vlan_tag);
         rdata->path_id          = BP_PATH(bp);
         rdata->network_cos_mode = start_params->network_cos_mode;
-        rdata->gre_tunnel_mode  = start_params->gre_tunnel_mode;
-        rdata->gre_tunnel_rss   = start_params->gre_tunnel_rss;
+        rdata->tunnel_mode      = start_params->tunnel_mode;
+        rdata->gre_tunnel_type  = start_params->gre_tunnel_type;
+        rdata->inner_gre_rss_en = start_params->inner_gre_rss_en;
+        rdata->vxlan_dst_port   = cpu_to_le16(4789);
+        rdata->sd_vlan_eth_type = cpu_to_le16(0x8100);
 
         /* No need for an explicit memory barrier here as long we would
          * need to ensure the ordering of writing to the SPQ element
@@ -5680,8 +5700,28 @@ static inline int bnx2x_func_send_switch_update(struct bnx2x *bp,
         memset(rdata, 0, sizeof(*rdata));
 
         /* Fill the ramrod data with provided parameters */
-        rdata->tx_switch_suspend_change_flg = 1;
-        rdata->tx_switch_suspend = switch_update_params->suspend;
+        if (test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+                     &switch_update_params->changes)) {
+                rdata->tx_switch_suspend_change_flg = 1;
+                rdata->tx_switch_suspend =
+                        test_bit(BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
+                                 &switch_update_params->changes);
+        }
+
+        if (test_bit(BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
+                     &switch_update_params->changes)) {
+                rdata->update_tunn_cfg_flg = 1;
+                if (test_bit(BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
+                             &switch_update_params->changes))
+                        rdata->tunn_clss_en = 1;
+                if (test_bit(BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
+                             &switch_update_params->changes))
+                        rdata->inner_gre_rss_en = 1;
+                rdata->tunnel_mode = switch_update_params->tunnel_mode;
+                rdata->gre_tunnel_type = switch_update_params->gre_tunnel_type;
+                rdata->vxlan_dst_port = cpu_to_le16(4789);
+        }
+
         rdata->echo = SWITCH_UPDATE;
 
         /* No need for an explicit memory barrier here as long as we
@@ -5817,6 +5857,42 @@ static inline int bnx2x_func_send_tx_start(struct bnx2x *bp,
                              U64_LO(data_mapping), NONE_CONNECTION_TYPE);
 }
 
+static inline
+int bnx2x_func_send_set_timesync(struct bnx2x *bp,
+                                 struct bnx2x_func_state_params *params)
+{
+        struct bnx2x_func_sp_obj *o = params->f_obj;
+        struct set_timesync_ramrod_data *rdata =
+                (struct set_timesync_ramrod_data *)o->rdata;
+        dma_addr_t data_mapping = o->rdata_mapping;
+        struct bnx2x_func_set_timesync_params *set_timesync_params =
+                &params->params.set_timesync;
+
+        memset(rdata, 0, sizeof(*rdata));
+
+        /* Fill the ramrod data with provided parameters */
+        rdata->drift_adjust_cmd = set_timesync_params->drift_adjust_cmd;
+        rdata->offset_cmd = set_timesync_params->offset_cmd;
+        rdata->add_sub_drift_adjust_value =
+                set_timesync_params->add_sub_drift_adjust_value;
+        rdata->drift_adjust_value = set_timesync_params->drift_adjust_value;
+        rdata->drift_adjust_period = set_timesync_params->drift_adjust_period;
+        rdata->offset_delta.lo =
+                cpu_to_le32(U64_LO(set_timesync_params->offset_delta));
+        rdata->offset_delta.hi =
+                cpu_to_le32(U64_HI(set_timesync_params->offset_delta));
+
+        DP(BNX2X_MSG_SP, "Set timesync command params: drift_cmd = %d, offset_cmd = %d, add_sub_drift = %d, drift_val = %d, drift_period = %d, offset_lo = %d, offset_hi = %d\n",
+           rdata->drift_adjust_cmd, rdata->offset_cmd,
+           rdata->add_sub_drift_adjust_value, rdata->drift_adjust_value,
+           rdata->drift_adjust_period, rdata->offset_delta.lo,
+           rdata->offset_delta.hi);
+
+        return bnx2x_sp_post(bp, RAMROD_CMD_ID_COMMON_SET_TIMESYNC, 0,
+                             U64_HI(data_mapping),
+                             U64_LO(data_mapping), NONE_CONNECTION_TYPE);
+}
+
 static int bnx2x_func_send_cmd(struct bnx2x *bp,
                                struct bnx2x_func_state_params *params)
 {
@@ -5839,6 +5915,8 @@ static int bnx2x_func_send_cmd(struct bnx2x *bp,
                 return bnx2x_func_send_tx_start(bp, params);
         case BNX2X_F_CMD_SWITCH_UPDATE:
                 return bnx2x_func_send_switch_update(bp, params);
+        case BNX2X_F_CMD_SET_TIMESYNC:
+                return bnx2x_func_send_set_timesync(bp, params);
         default:
                 BNX2X_ERR("Unknown command: %d\n", params->cmd);
                 return -EINVAL;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
index 718ecd294661..21c8f6fb89e5 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h
@@ -711,6 +711,7 @@ enum {
         BNX2X_RSS_IPV6,
         BNX2X_RSS_IPV6_TCP,
         BNX2X_RSS_IPV6_UDP,
+        BNX2X_RSS_GRE_INNER_HDRS,
 };
 
 struct bnx2x_config_rss_params {
@@ -769,7 +770,9 @@ enum {
         BNX2X_Q_UPDATE_SILENT_VLAN_REM_CHNG,
         BNX2X_Q_UPDATE_SILENT_VLAN_REM,
         BNX2X_Q_UPDATE_TX_SWITCHING_CHNG,
-        BNX2X_Q_UPDATE_TX_SWITCHING
+        BNX2X_Q_UPDATE_TX_SWITCHING,
+        BNX2X_Q_UPDATE_PTP_PKTS_CHNG,
+        BNX2X_Q_UPDATE_PTP_PKTS,
 };
 
 /* Allowed Queue states */
@@ -831,6 +834,7 @@ enum {
         BNX2X_Q_FLG_ANTI_SPOOF,
         BNX2X_Q_FLG_SILENT_VLAN_REM,
         BNX2X_Q_FLG_FORCE_DEFAULT_PRI,
+        BNX2X_Q_FLG_REFUSE_OUTBAND_VLAN,
         BNX2X_Q_FLG_PCSUM_ON_PKT,
         BNX2X_Q_FLG_TUN_INC_INNER_IP_ID
 };
@@ -851,6 +855,10 @@ enum bnx2x_q_type {
 #define BNX2X_MULTI_TX_COS                      3 /* Maximum possible */
 
 #define MAC_PAD (ALIGN(ETH_ALEN, sizeof(u32)) - ETH_ALEN)
+/* DMAE channel to be used by FW for timesync workaroun. A driver that sends
+ * timesync-related ramrods must not use this DMAE command ID.
+ */
+#define FW_DMAE_CMD_ID 6
 
 struct bnx2x_queue_init_params {
         struct {
@@ -1085,6 +1093,16 @@ struct bnx2x_queue_sp_obj {
 };
 
 /********************** Function state update *********************************/
+
+/* UPDATE command options */
+enum {
+        BNX2X_F_UPDATE_TX_SWITCH_SUSPEND_CHNG,
+        BNX2X_F_UPDATE_TX_SWITCH_SUSPEND,
+        BNX2X_F_UPDATE_TUNNEL_CFG_CHNG,
+        BNX2X_F_UPDATE_TUNNEL_CLSS_EN,
+        BNX2X_F_UPDATE_TUNNEL_INNER_GRE_RSS_EN,
+};
+
 /* Allowed Function states */
 enum bnx2x_func_state {
         BNX2X_F_STATE_RESET,
@@ -1105,6 +1123,7 @@ enum bnx2x_func_cmd {
         BNX2X_F_CMD_TX_STOP,
         BNX2X_F_CMD_TX_START,
         BNX2X_F_CMD_SWITCH_UPDATE,
+        BNX2X_F_CMD_SET_TIMESYNC,
         BNX2X_F_CMD_MAX,
 };
 
@@ -1146,18 +1165,25 @@ struct bnx2x_func_start_params {
         /* Function cos mode */
         u8 network_cos_mode;
 
-        /* NVGRE classification enablement */
-        u8 nvgre_clss_en;
+        /* TUNN_MODE_NONE/TUNN_MODE_VXLAN/TUNN_MODE_GRE */
+        u8 tunnel_mode;
 
-        /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
-        u8 gre_tunnel_mode;
+        /* tunneling classification enablement */
+        u8 tunn_clss_en;
 
-        /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */
-        u8 gre_tunnel_rss;
+        /* NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */
+        u8 gre_tunnel_type;
+
+        /* Enables Inner GRE RSS on the function, depends on the client RSS
+         * capailities
+         */
+        u8 inner_gre_rss_en;
 };
 
 struct bnx2x_func_switch_update_params {
-        u8 suspend;
+        unsigned long changes; /* BNX2X_F_UPDATE_XX bits */
+        u8 tunnel_mode;
+        u8 gre_tunnel_type;
 };
 
 struct bnx2x_func_afex_update_params {
@@ -1172,6 +1198,7 @@ struct bnx2x_func_afex_viflists_params {
         u8 afex_vif_list_command;
         u8 func_to_clear;
 };
+
 struct bnx2x_func_tx_start_params {
         struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES];
         u8 dcb_enabled;
@@ -1179,6 +1206,24 @@ struct bnx2x_func_tx_start_params {
         u8 dont_add_pri_0_en;
 };
 
+struct bnx2x_func_set_timesync_params {
+        /* Reset, set or keep the current drift value */
+        u8 drift_adjust_cmd;
+
+        /* Dec, inc or keep the current offset */
+        u8 offset_cmd;
+
+        /* Drift value direction */
+        u8 add_sub_drift_adjust_value;
+
+        /* Drift, period and offset values to be used according to the commands
+         * above.
+         */
+        u8 drift_adjust_value;
+        u32 drift_adjust_period;
+        u64 offset_delta;
+};
+
 struct bnx2x_func_state_params {
         struct bnx2x_func_sp_obj *f_obj;
 
@@ -1197,6 +1242,7 @@ struct bnx2x_func_state_params {
                 struct bnx2x_func_afex_update_params afex_update;
                 struct bnx2x_func_afex_viflists_params afex_viflists;
                 struct bnx2x_func_tx_start_params tx_start;
+                struct bnx2x_func_set_timesync_params set_timesync;
         } params;
 };
 
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
index 662310c5f4e9..c88b20af87df 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c
@@ -1125,7 +1125,7 @@ static int bnx2x_ari_enabled(struct pci_dev *dev)
         return dev->bus->self && dev->bus->self->ari_enabled;
 }
 
-static void
+static int
 bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
 {
         int sb_id;
@@ -1150,6 +1150,7 @@ bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
                    GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR));
         }
         DP(BNX2X_MSG_IOV, "vf_sbs_pool is %d\n", BP_VFDB(bp)->vf_sbs_pool);
+        return BP_VFDB(bp)->vf_sbs_pool;
 }
 
 static void __bnx2x_iov_free_vfdb(struct bnx2x *bp)
@@ -1314,15 +1315,17 @@ int bnx2x_iov_init_one(struct bnx2x *bp, int int_mode_param,
         }
 
         /* re-read the IGU CAM for VFs - index and abs_vfid must be set */
-        bnx2x_get_vf_igu_cam_info(bp);
+        if (!bnx2x_get_vf_igu_cam_info(bp)) {
+                BNX2X_ERR("No entries in IGU CAM for vfs\n");
+                err = -EINVAL;
+                goto failed;
+        }
 
         /* allocate the queue arrays for all VFs */
         bp->vfdb->vfqs = kzalloc(
                 BNX2X_MAX_NUM_VF_QUEUES * sizeof(struct bnx2x_vf_queue),
                 GFP_KERNEL);
 
-        DP(BNX2X_MSG_IOV, "bp->vfdb->vfqs was %p\n", bp->vfdb->vfqs);
-
         if (!bp->vfdb->vfqs) {
                 BNX2X_ERR("failed to allocate vf queue array\n");
                 err = -ENOMEM;
@@ -1349,9 +1352,7 @@ void bnx2x_iov_remove_one(struct bnx2x *bp)
         if (!IS_SRIOV(bp))
                 return;
 
-        DP(BNX2X_MSG_IOV, "about to call disable sriov\n");
-        pci_disable_sriov(bp->pdev);
-        DP(BNX2X_MSG_IOV, "sriov disabled\n");
+        bnx2x_disable_sriov(bp);
 
         /* disable access to all VFs */
         for (vf_idx = 0; vf_idx < bp->vfdb->sriov.total; vf_idx++) {
@@ -1985,21 +1986,6 @@ void bnx2x_iov_adjust_stats_req(struct bnx2x *bp)
         bp->fw_stats_req->hdr.cmd_num = bp->fw_stats_num + stats_count;
 }
 
-static inline
-struct bnx2x_virtf *__vf_from_stat_id(struct bnx2x *bp, u8 stat_id)
-{
-        int i;
-        struct bnx2x_virtf *vf = NULL;
-
-        for_each_vf(bp, i) {
-                vf = BP_VF(bp, i);
-                if (stat_id >= vf->igu_base_id &&
-                    stat_id < vf->igu_base_id + vf_sb_count(vf))
-                        break;
-        }
-        return vf;
-}
-
 /* VF API helpers */
 static void bnx2x_vf_qtbl_set_q(struct bnx2x *bp, u8 abs_vfid, u8 qid,
                                 u8 enable)
@@ -2362,12 +2348,6 @@ int bnx2x_vf_release(struct bnx2x *bp, struct bnx2x_virtf *vf)
         return rc;
 }
 
-static inline void bnx2x_vf_get_sbdf(struct bnx2x *bp,
-                              struct bnx2x_virtf *vf, u32 *sbdf)
-{
-        *sbdf = vf->devfn | (vf->bus << 8);
-}
-
 void bnx2x_lock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
                               enum channel_tlvs tlv)
 {
@@ -2416,7 +2396,7 @@ void bnx2x_unlock_vf_pf_channel(struct bnx2x *bp, struct bnx2x_virtf *vf,
 
         /* log the unlock */
         DP(BNX2X_MSG_IOV, "VF[%d]: vf pf channel unlocked by %d\n",
-           vf->abs_vfid, vf->op_current);
+           vf->abs_vfid, current_tlv);
 }
 
 static int bnx2x_set_pf_tx_switching(struct bnx2x *bp, bool enable)
@@ -2501,7 +2481,7 @@ int bnx2x_sriov_configure(struct pci_dev *dev, int num_vfs_param)
         bp->requested_nr_virtfn = num_vfs_param;
         if (num_vfs_param == 0) {
                 bnx2x_set_pf_tx_switching(bp, false);
-                pci_disable_sriov(dev);
+                bnx2x_disable_sriov(bp);
                 return 0;
         } else {
                 return bnx2x_enable_sriov(bp);
@@ -2614,6 +2594,12 @@ void bnx2x_pf_set_vfs_vlan(struct bnx2x *bp)
 
 void bnx2x_disable_sriov(struct bnx2x *bp)
 {
+        if (pci_vfs_assigned(bp->pdev)) {
+                DP(BNX2X_MSG_IOV,
+                   "Unloading driver while VFs are assigned - VFs will not be deallocated\n");
+                return;
+        }
+
         pci_disable_sriov(bp->pdev);
 }
 
@@ -2628,7 +2614,7 @@ static int bnx2x_vf_op_prep(struct bnx2x *bp, int vfidx,
         }
 
         if (!IS_SRIOV(bp)) {
-                BNX2X_ERR("sriov is disabled - can't utilize iov-realted functionality\n");
+                BNX2X_ERR("sriov is disabled - can't utilize iov-related functionality\n");
                 return -EINVAL;
         }
 
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h
index ca1055f3d8af..01bafa4ac045 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.h
@@ -299,7 +299,8 @@ struct bnx2x_vfdb {
 #define BP_VFDB(bp)             ((bp)->vfdb)
         /* vf array */
         struct bnx2x_virtf      *vfs;
-#define BP_VF(bp, idx)          (&((bp)->vfdb->vfs[idx]))
+#define BP_VF(bp, idx)          ((BP_VFDB(bp) && (bp)->vfdb->vfs) ? \
+                                        &((bp)->vfdb->vfs[idx]) : NULL)
 #define bnx2x_vf(bp, idx, var)  ((bp)->vfdb->vfs[idx].var)
 
         /* queue array - for all vfs */
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
index ca47665f94bf..d1608297c773 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_stats.c
@@ -137,7 +137,7 @@ static void bnx2x_storm_stats_post(struct bnx2x *bp)
                         cpu_to_le16(bp->stats_counter++);
 
                 DP(BNX2X_MSG_STATS, "Sending statistics ramrod %d\n",
-                        bp->fw_stats_req->hdr.drv_stats_counter);
+                   le16_to_cpu(bp->fw_stats_req->hdr.drv_stats_counter));
 
                 /* adjust the ramrod to include VF queues statistics */
                 bnx2x_iov_adjust_stats_req(bp);
@@ -200,7 +200,7 @@ static void bnx2x_hw_stats_post(struct bnx2x *bp)
         }
 }
 
-static int bnx2x_stats_comp(struct bnx2x *bp)
+static void bnx2x_stats_comp(struct bnx2x *bp)
 {
         u32 *stats_comp = bnx2x_sp(bp, stats_comp);
         int cnt = 10;
@@ -214,7 +214,6 @@ static int bnx2x_stats_comp(struct bnx2x *bp)
                 cnt--;
                 usleep_range(1000, 2000);
         }
-        return 1;
 }
 
 /*
@@ -1630,6 +1629,11 @@ void bnx2x_stats_init(struct bnx2x *bp)
         int /*abs*/port = BP_PORT(bp);
         int mb_idx = BP_FW_MB_IDX(bp);
 
+        if (IS_VF(bp)) {
+                bnx2x_memset_stats(bp);
+                return;
+        }
+
         bp->stats_pending = 0;
         bp->executer_idx = 0;
         bp->stats_counter = 0;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c
index 54e0427a9ee6..b1d9c44aa56c 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_vfpf.c
@@ -583,7 +583,6 @@ int bnx2x_vfpf_setup_q(struct bnx2x *bp, struct bnx2x_fastpath *fp,
         flags |= VFPF_QUEUE_FLG_STATS;
         flags |= VFPF_QUEUE_FLG_CACHE_ALIGN;
         flags |= VFPF_QUEUE_FLG_VLAN;
-        DP(NETIF_MSG_IFUP, "vlan removal enabled\n");
 
         /* Common */
         req->vf_qid = fp_idx;
@@ -952,14 +951,6 @@ static void storm_memset_vf_mbx_valid(struct bnx2x *bp, u16 abs_fid)
         REG_WR8(bp, addr, 1);
 }
 
-static inline void bnx2x_set_vf_mbxs_valid(struct bnx2x *bp)
-{
-        int i;
-
-        for_each_vf(bp, i)
-                storm_memset_vf_mbx_valid(bp, bnx2x_vf(bp, i, abs_vfid));
-}
-
 /* enable vf_pf mailbox (aka vf-pf-channel) */
 void bnx2x_vf_enable_mbx(struct bnx2x *bp, u8 abs_vfid)
 {
diff --git a/drivers/net/ethernet/broadcom/cnic.c b/drivers/net/ethernet/broadcom/cnic.c
index a6a9f284c8dd..23f23c97c2ad 100644
--- a/drivers/net/ethernet/broadcom/cnic.c
+++ b/drivers/net/ethernet/broadcom/cnic.c
@@ -383,7 +383,7 @@ static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
                         break;
 
                 rcu_read_lock();
-                if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
+                if (!rcu_access_pointer(cp->ulp_ops[CNIC_ULP_L4])) {
                         rc = -ENODEV;
                         rcu_read_unlock();
                         break;
@@ -527,7 +527,7 @@ int cnic_unregister_driver(int ulp_type)
         list_for_each_entry(dev, &cnic_dev_list, list) {
                 struct cnic_local *cp = dev->cnic_priv;
 
-                if (rcu_dereference(cp->ulp_ops[ulp_type])) {
+                if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
                         pr_err("%s: Type %d still has devices registered\n",
                                __func__, ulp_type);
                         read_unlock(&cnic_dev_lock);
@@ -575,7 +575,7 @@ static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
                 mutex_unlock(&cnic_lock);
                 return -EAGAIN;
         }
-        if (rcu_dereference(cp->ulp_ops[ulp_type])) {
+        if (rcu_access_pointer(cp->ulp_ops[ulp_type])) {
                 pr_err("%s: Type %d has already been registered to this device\n",
                        __func__, ulp_type);
                 mutex_unlock(&cnic_lock);
diff --git a/drivers/net/ethernet/cisco/enic/enic.h b/drivers/net/ethernet/cisco/enic/enic.h
index 962510f391df..5ba5ad071bb6 100644
--- a/drivers/net/ethernet/cisco/enic/enic.h
+++ b/drivers/net/ethernet/cisco/enic/enic.h
@@ -186,6 +186,7 @@ struct enic {
         ____cacheline_aligned struct vnic_cq cq[ENIC_CQ_MAX];
         unsigned int cq_count;
         struct enic_rfs_flw_tbl rfs_h;
+        u32 rx_copybreak;
 };
 
 static inline struct device *enic_get_dev(struct enic *enic)
diff --git a/drivers/net/ethernet/cisco/enic/enic_ethtool.c b/drivers/net/ethernet/cisco/enic/enic_ethtool.c
index 523c9ceb04c0..85173d620758 100644
--- a/drivers/net/ethernet/cisco/enic/enic_ethtool.c
+++ b/drivers/net/ethernet/cisco/enic/enic_ethtool.c
@@ -379,6 +379,43 @@ static int enic_get_rxnfc(struct net_device *dev, struct ethtool_rxnfc *cmd,
         return ret;
 }
 
+static int enic_get_tunable(struct net_device *dev,
+                            const struct ethtool_tunable *tuna, void *data)
+{
+        struct enic *enic = netdev_priv(dev);
+        int ret = 0;
+
+        switch (tuna->id) {
+        case ETHTOOL_RX_COPYBREAK:
+                *(u32 *)data = enic->rx_copybreak;
+                break;
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+        return ret;
+}
+
+static int enic_set_tunable(struct net_device *dev,
+                            const struct ethtool_tunable *tuna,
+                            const void *data)
+{
+        struct enic *enic = netdev_priv(dev);
+        int ret = 0;
+
+        switch (tuna->id) {
+        case ETHTOOL_RX_COPYBREAK:
+                enic->rx_copybreak = *(u32 *)data;
+                break;
+        default:
+                ret = -EINVAL;
+                break;
+        }
+
+        return ret;
+}
+
 static const struct ethtool_ops enic_ethtool_ops = {
         .get_settings = enic_get_settings,
         .get_drvinfo = enic_get_drvinfo,
@@ -391,6 +428,8 @@ static const struct ethtool_ops enic_ethtool_ops = {
         .get_coalesce = enic_get_coalesce,
         .set_coalesce = enic_set_coalesce,
         .get_rxnfc = enic_get_rxnfc,
+        .get_tunable = enic_get_tunable,
+        .set_tunable = enic_set_tunable,
 };
 
 void enic_set_ethtool_ops(struct net_device *netdev)
diff --git a/drivers/net/ethernet/cisco/enic/enic_main.c b/drivers/net/ethernet/cisco/enic/enic_main.c
index c8832bc1c5f7..929bfe70080a 100644
--- a/drivers/net/ethernet/cisco/enic/enic_main.c
+++ b/drivers/net/ethernet/cisco/enic/enic_main.c
@@ -66,6 +66,8 @@
 #define PCI_DEVICE_ID_CISCO_VIC_ENET_DYN     0x0044  /* enet dynamic vnic */
 #define PCI_DEVICE_ID_CISCO_VIC_ENET_VF      0x0071  /* enet SRIOV VF */
 
+#define RX_COPYBREAK_DEFAULT            256
+
 /* Supported devices */
 static const struct pci_device_id enic_id_table[] = {
         { PCI_VDEVICE(CISCO, PCI_DEVICE_ID_CISCO_VIC_ENET) },
@@ -924,6 +926,7 @@ static void enic_free_rq_buf(struct vnic_rq *rq, struct vnic_rq_buf *buf)
         pci_unmap_single(enic->pdev, buf->dma_addr,
                 buf->len, PCI_DMA_FROMDEVICE);
         dev_kfree_skb_any(buf->os_buf);
+        buf->os_buf = NULL;
 }
 
 static int enic_rq_alloc_buf(struct vnic_rq *rq)
@@ -934,7 +937,24 @@ static int enic_rq_alloc_buf(struct vnic_rq *rq)
         unsigned int len = netdev->mtu + VLAN_ETH_HLEN;
         unsigned int os_buf_index = 0;
         dma_addr_t dma_addr;
+        struct vnic_rq_buf *buf = rq->to_use;
+
+        if (buf->os_buf) {
+                buf = buf->next;
+                rq->to_use = buf;
+                rq->ring.desc_avail--;
+                if ((buf->index & VNIC_RQ_RETURN_RATE) == 0) {
+                        /* Adding write memory barrier prevents compiler and/or
+                         * CPU reordering, thus avoiding descriptor posting
+                         * before descriptor is initialized. Otherwise, hardware
+                         * can read stale descriptor fields.
+                         */
+                        wmb();
+                        iowrite32(buf->index, &rq->ctrl->posted_index);
+                }
 
+                return 0;
+        }
         skb = netdev_alloc_skb_ip_align(netdev, len);
         if (!skb)
                 return -ENOMEM;
@@ -957,6 +977,25 @@ static void enic_intr_update_pkt_size(struct vnic_rx_bytes_counter *pkt_size,
                 pkt_size->small_pkt_bytes_cnt += pkt_len;
 }
 
+static bool enic_rxcopybreak(struct net_device *netdev, struct sk_buff **skb,
+                             struct vnic_rq_buf *buf, u16 len)
+{
+        struct enic *enic = netdev_priv(netdev);
+        struct sk_buff *new_skb;
+
+        if (len > enic->rx_copybreak)
+                return false;
+        new_skb = netdev_alloc_skb_ip_align(netdev, len);
+        if (!new_skb)
+                return false;
+        pci_dma_sync_single_for_cpu(enic->pdev, buf->dma_addr, len,
+                                    DMA_FROM_DEVICE);
+        memcpy(new_skb->data, (*skb)->data, len);
+        *skb = new_skb;
+
+        return true;
+}
+
 static void enic_rq_indicate_buf(struct vnic_rq *rq,
         struct cq_desc *cq_desc, struct vnic_rq_buf *buf,
         int skipped, void *opaque)
@@ -978,9 +1017,6 @@ static void enic_rq_indicate_buf(struct vnic_rq *rq,
                 return;
 
         skb = buf->os_buf;
-        prefetch(skb->data - NET_IP_ALIGN);
-        pci_unmap_single(enic->pdev, buf->dma_addr,
-                buf->len, PCI_DMA_FROMDEVICE);
 
         cq_enet_rq_desc_dec((struct cq_enet_rq_desc *)cq_desc,
                 &type, &color, &q_number, &completed_index,
@@ -1011,6 +1047,13 @@ static void enic_rq_indicate_buf(struct vnic_rq *rq,
                 /* Good receive
                  */
 
+                if (!enic_rxcopybreak(netdev, &skb, buf, bytes_written)) {
+                        buf->os_buf = NULL;
+                        pci_unmap_single(enic->pdev, buf->dma_addr, buf->len,
+                                         PCI_DMA_FROMDEVICE);
+                }
+                prefetch(skb->data - NET_IP_ALIGN);
+
                 skb_put(skb, bytes_written);
                 skb->protocol = eth_type_trans(skb, netdev);
                 skb_record_rx_queue(skb, q_number);
@@ -2531,6 +2574,7 @@ static int enic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 dev_err(dev, "Cannot register net device, aborting\n");
                 goto err_out_dev_deinit;
         }
+        enic->rx_copybreak = RX_COPYBREAK_DEFAULT;
 
         return 0;
 
diff --git a/drivers/net/ethernet/dec/tulip/dmfe.c b/drivers/net/ethernet/dec/tulip/dmfe.c
index 322213d901d5..c8205606c775 100644
--- a/drivers/net/ethernet/dec/tulip/dmfe.c
+++ b/drivers/net/ethernet/dec/tulip/dmfe.c
@@ -328,10 +328,10 @@ static void allocate_rx_buffer(struct net_device *);
 static void update_cr6(u32, void __iomem *);
 static void send_filter_frame(struct DEVICE *);
 static void dm9132_id_table(struct DEVICE *);
-static u16 phy_read(void __iomem *, u8, u8, u32);
-static void phy_write(void __iomem *, u8, u8, u16, u32);
-static void phy_write_1bit(void __iomem *, u32);
-static u16 phy_read_1bit(void __iomem *);
+static u16 dmfe_phy_read(void __iomem *, u8, u8, u32);
+static void dmfe_phy_write(void __iomem *, u8, u8, u16, u32);
+static void dmfe_phy_write_1bit(void __iomem *, u32);
+static u16 dmfe_phy_read_1bit(void __iomem *);
 static u8 dmfe_sense_speed(struct dmfe_board_info *);
 static void dmfe_process_mode(struct dmfe_board_info *);
 static void dmfe_timer(unsigned long);
@@ -770,7 +770,7 @@ static int dmfe_stop(struct DEVICE *dev)
         /* Reset & stop DM910X board */
         dw32(DCR0, DM910X_RESET);
         udelay(100);
-        phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
+        dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
 
         /* free interrupt */
         free_irq(db->pdev->irq, dev);
@@ -1154,7 +1154,7 @@ static void dmfe_timer(unsigned long data)
                 if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
                         db->cr6_data &= ~0x40000;
                         update_cr6(db->cr6_data, ioaddr);
-                        phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
+                        dmfe_phy_write(ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
                         db->cr6_data |= 0x40000;
                         update_cr6(db->cr6_data, ioaddr);
                         db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
@@ -1230,9 +1230,9 @@ static void dmfe_timer(unsigned long data)
         */
 
         /* need a dummy read because of PHY's register latch*/
-        phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
-        link_ok_phy = (phy_read (db->ioaddr,
-                       db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
+        dmfe_phy_read (db->ioaddr, db->phy_addr, 1, db->chip_id);
+        link_ok_phy = (dmfe_phy_read (db->ioaddr,
+                                      db->phy_addr, 1, db->chip_id) & 0x4) ? 1 : 0;
 
         if (link_ok_phy != link_ok) {
                 DMFE_DBUG (0, "PHY and chip report different link status", 0);
@@ -1247,8 +1247,8 @@ static void dmfe_timer(unsigned long data)
                 /* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
                 /* AUTO or force 1M Homerun/Longrun don't need */
                 if ( !(db->media_mode & 0x38) )
-                        phy_write(db->ioaddr, db->phy_addr,
-                                  0, 0x1000, db->chip_id);
+                        dmfe_phy_write(db->ioaddr, db->phy_addr,
+                                       0, 0x1000, db->chip_id);
 
                 /* AUTO mode, if INT phyxcer link failed, select EXT device */
                 if (db->media_mode & DMFE_AUTO) {
@@ -1649,16 +1649,16 @@ static u8 dmfe_sense_speed(struct dmfe_board_info *db)
         /* CR6 bit18=0, select 10/100M */
         update_cr6(db->cr6_data & ~0x40000, ioaddr);
 
-        phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
-        phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
+        phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
+        phy_mode = dmfe_phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
 
         if ( (phy_mode & 0x24) == 0x24 ) {
                 if (db->chip_id == PCI_DM9132_ID)       /* DM9132 */
-                        phy_mode = phy_read(db->ioaddr,
-                                    db->phy_addr, 7, db->chip_id) & 0xf000;
+                        phy_mode = dmfe_phy_read(db->ioaddr,
+                                                 db->phy_addr, 7, db->chip_id) & 0xf000;
                 else                            /* DM9102/DM9102A */
-                        phy_mode = phy_read(db->ioaddr,
-                                    db->phy_addr, 17, db->chip_id) & 0xf000;
+                        phy_mode = dmfe_phy_read(db->ioaddr,
+                                                 db->phy_addr, 17, db->chip_id) & 0xf000;
                 switch (phy_mode) {
                 case 0x1000: db->op_mode = DMFE_10MHF; break;
                 case 0x2000: db->op_mode = DMFE_10MFD; break;
@@ -1695,15 +1695,15 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db)
 
         /* DM9009 Chip: Phyxcer reg18 bit12=0 */
         if (db->chip_id == PCI_DM9009_ID) {
-                phy_reg = phy_read(db->ioaddr,
-                                   db->phy_addr, 18, db->chip_id) & ~0x1000;
+                phy_reg = dmfe_phy_read(db->ioaddr,
+                                        db->phy_addr, 18, db->chip_id) & ~0x1000;
 
-                phy_write(db->ioaddr,
-                          db->phy_addr, 18, phy_reg, db->chip_id);
+                dmfe_phy_write(db->ioaddr,
+                               db->phy_addr, 18, phy_reg, db->chip_id);
         }
 
         /* Phyxcer capability setting */
-        phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
+        phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
 
         if (db->media_mode & DMFE_AUTO) {
                 /* AUTO Mode */
@@ -1724,13 +1724,13 @@ static void dmfe_set_phyxcer(struct dmfe_board_info *db)
                 phy_reg|=db->PHY_reg4;
                 db->media_mode|=DMFE_AUTO;
         }
-        phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
+        dmfe_phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
 
         /* Restart Auto-Negotiation */
         if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
-                phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
+                dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
         if ( !db->chip_type )
-                phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
+                dmfe_phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
 }
 
 
@@ -1762,7 +1762,7 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
         /* 10/100M phyxcer force mode need */
         if ( !(db->media_mode & 0x18)) {
                 /* Forece Mode */
-                phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
+                phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
                 if ( !(phy_reg & 0x1) ) {
                         /* parter without N-Way capability */
                         phy_reg = 0x0;
@@ -1772,12 +1772,12 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
                         case DMFE_100MHF: phy_reg = 0x2000; break;
                         case DMFE_100MFD: phy_reg = 0x2100; break;
                         }
-                        phy_write(db->ioaddr,
-                                  db->phy_addr, 0, phy_reg, db->chip_id);
+                        dmfe_phy_write(db->ioaddr,
+                                       db->phy_addr, 0, phy_reg, db->chip_id);
                         if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
                                 mdelay(20);
-                        phy_write(db->ioaddr,
-                                  db->phy_addr, 0, phy_reg, db->chip_id);
+                        dmfe_phy_write(db->ioaddr,
+                                       db->phy_addr, 0, phy_reg, db->chip_id);
                 }
         }
 }
@@ -1787,8 +1787,8 @@ static void dmfe_process_mode(struct dmfe_board_info *db)
  *      Write a word to Phy register
  */
 
-static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
-                      u16 phy_data, u32 chip_id)
+static void dmfe_phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
+                           u16 phy_data, u32 chip_id)
 {
         u16 i;
 
@@ -1799,34 +1799,34 @@ static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
 
                 /* Send 33 synchronization clock to Phy controller */
                 for (i = 0; i < 35; i++)
-                        phy_write_1bit(ioaddr, PHY_DATA_1);
+                        dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send start command(01) to Phy */
-                phy_write_1bit(ioaddr, PHY_DATA_0);
-                phy_write_1bit(ioaddr, PHY_DATA_1);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send write command(01) to Phy */
-                phy_write_1bit(ioaddr, PHY_DATA_0);
-                phy_write_1bit(ioaddr, PHY_DATA_1);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send Phy address */
                 for (i = 0x10; i > 0; i = i >> 1)
-                        phy_write_1bit(ioaddr,
-                                       phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
+                        dmfe_phy_write_1bit(ioaddr,
+                                            phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
 
                 /* Send register address */
                 for (i = 0x10; i > 0; i = i >> 1)
-                        phy_write_1bit(ioaddr,
-                                       offset & i ? PHY_DATA_1 : PHY_DATA_0);
+                        dmfe_phy_write_1bit(ioaddr,
+                                            offset & i ? PHY_DATA_1 : PHY_DATA_0);
 
                 /* written trasnition */
-                phy_write_1bit(ioaddr, PHY_DATA_1);
-                phy_write_1bit(ioaddr, PHY_DATA_0);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
 
                 /* Write a word data to PHY controller */
                 for ( i = 0x8000; i > 0; i >>= 1)
-                        phy_write_1bit(ioaddr,
-                                       phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
+                        dmfe_phy_write_1bit(ioaddr,
+                                            phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
         }
 }
 
@@ -1835,7 +1835,7 @@ static void phy_write(void __iomem *ioaddr, u8 phy_addr, u8 offset,
  *      Read a word data from phy register
  */
 
-static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
+static u16 dmfe_phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
 {
         int i;
         u16 phy_data;
@@ -1848,33 +1848,33 @@ static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
 
                 /* Send 33 synchronization clock to Phy controller */
                 for (i = 0; i < 35; i++)
-                        phy_write_1bit(ioaddr, PHY_DATA_1);
+                        dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send start command(01) to Phy */
-                phy_write_1bit(ioaddr, PHY_DATA_0);
-                phy_write_1bit(ioaddr, PHY_DATA_1);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
 
                 /* Send read command(10) to Phy */
-                phy_write_1bit(ioaddr, PHY_DATA_1);
-                phy_write_1bit(ioaddr, PHY_DATA_0);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_1);
+                dmfe_phy_write_1bit(ioaddr, PHY_DATA_0);
 
                 /* Send Phy address */
                 for (i = 0x10; i > 0; i = i >> 1)
-                        phy_write_1bit(ioaddr,
-                                       phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
+                        dmfe_phy_write_1bit(ioaddr,
+                                            phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
 
                 /* Send register address */
                 for (i = 0x10; i > 0; i = i >> 1)
-                        phy_write_1bit(ioaddr,
-                                       offset & i ? PHY_DATA_1 : PHY_DATA_0);
+                        dmfe_phy_write_1bit(ioaddr,
+                                            offset & i ? PHY_DATA_1 : PHY_DATA_0);
 
                 /* Skip transition state */
-                phy_read_1bit(ioaddr);
+                dmfe_phy_read_1bit(ioaddr);
 
                 /* read 16bit data */
                 for (phy_data = 0, i = 0; i < 16; i++) {
                         phy_data <<= 1;
-                        phy_data |= phy_read_1bit(ioaddr);
+                        phy_data |= dmfe_phy_read_1bit(ioaddr);
                 }
         }
 
@@ -1886,7 +1886,7 @@ static u16 phy_read(void __iomem *ioaddr, u8 phy_addr, u8 offset, u32 chip_id)
  *      Write one bit data to Phy Controller
  */
 
-static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
+static void dmfe_phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
 {
         dw32(DCR9, phy_data);           /* MII Clock Low */
         udelay(1);
@@ -1901,7 +1901,7 @@ static void phy_write_1bit(void __iomem *ioaddr, u32 phy_data)
  *      Read one bit phy data from PHY controller
  */
 
-static u16 phy_read_1bit(void __iomem *ioaddr)
+static u16 dmfe_phy_read_1bit(void __iomem *ioaddr)
 {
         u16 phy_data;
 
@@ -1995,11 +1995,11 @@ static void dmfe_parse_srom(struct dmfe_board_info * db)
         /* Check DM9801 or DM9802 present or not */
         db->HPNA_present = 0;
         update_cr6(db->cr6_data | 0x40000, db->ioaddr);
-        tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
+        tmp_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
         if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
                 /* DM9801 or DM9802 present */
                 db->HPNA_timer = 8;
-                if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
+                if ( dmfe_phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
                         /* DM9801 HomeRun */
                         db->HPNA_present = 1;
                         dmfe_program_DM9801(db, tmp_reg);
@@ -2025,29 +2025,29 @@ static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
         switch(HPNA_rev) {
         case 0xb900: /* DM9801 E3 */
                 db->HPNA_command |= 0x1000;
-                reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
+                reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
                 reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
-                reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
+                reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
                 break;
         case 0xb901: /* DM9801 E4 */
-                reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
+                reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
                 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
-                reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
+                reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
                 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
                 break;
         case 0xb902: /* DM9801 E5 */
         case 0xb903: /* DM9801 E6 */
         default:
                 db->HPNA_command |= 0x1000;
-                reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
+                reg25 = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
                 reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
-                reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
+                reg17 = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
                 reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
                 break;
         }
-        phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
-        phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
-        phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
+        dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
+        dmfe_phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
+        dmfe_phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
 }
 
 
@@ -2060,10 +2060,10 @@ static void dmfe_program_DM9802(struct dmfe_board_info * db)
         uint phy_reg;
 
         if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
-        phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
-        phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
+        dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
+        phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
         phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
-        phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
+        dmfe_phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
 }
 
 
@@ -2077,7 +2077,7 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
         uint phy_reg;
 
         /* Got remote device status */
-        phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
+        phy_reg = dmfe_phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
         switch(phy_reg) {
         case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
         case 0x20: phy_reg = 0x0900;break; /* LP/HS */
@@ -2087,8 +2087,8 @@ static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
 
         /* Check remote device status match our setting ot not */
         if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
-                phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
-                          db->chip_id);
+                dmfe_phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command,
+                               db->chip_id);
                 db->HPNA_timer=8;
         } else
                 db->HPNA_timer=600;     /* Match, every 10 minutes, check */
diff --git a/drivers/net/ethernet/ec_bhf.c b/drivers/net/ethernet/ec_bhf.c
index 056b44b93477..d1017509b08a 100644
--- a/drivers/net/ethernet/ec_bhf.c
+++ b/drivers/net/ethernet/ec_bhf.c
@@ -1,5 +1,5 @@
  /*
- * drivers/net/ethernet/beckhoff/ec_bhf.c
+ * drivers/net/ethernet/ec_bhf.c
  *
  * Copyright (C) 2014 Darek Marcinkiewicz <reksio@newterm.pl>
  *
@@ -18,9 +18,6 @@
  * Those can be found on Bechhoff CX50xx industrial PCs.
  */
 
-#if 0
-#define DEBUG
-#endif
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/moduleparam.h>
@@ -74,6 +71,8 @@
 
 #define DMA_WINDOW_SIZE_MASK    0xfffffffc
 
+#define ETHERCAT_MASTER_ID      0x14
+
 static struct pci_device_id ids[] = {
         { PCI_DEVICE(0x15ec, 0x5000), },
         { 0, }
@@ -131,7 +130,6 @@ struct bhf_dma {
 
 struct ec_bhf_priv {
         struct net_device *net_dev;
-
         struct pci_dev *dev;
 
         void __iomem *io;
@@ -162,32 +160,6 @@ struct ec_bhf_priv {
 
 #define PRIV_TO_DEV(priv) (&(priv)->dev->dev)
 
-#define ETHERCAT_MASTER_ID      0x14
-
-static void ec_bhf_print_status(struct ec_bhf_priv *priv)
-{
-        struct device *dev = PRIV_TO_DEV(priv);
-
-        dev_dbg(dev, "Frame error counter: %d\n",
-                ioread8(priv->mac_io + MAC_FRAME_ERR_CNT));
-        dev_dbg(dev, "RX error counter: %d\n",
-                ioread8(priv->mac_io + MAC_RX_ERR_CNT));
-        dev_dbg(dev, "CRC error counter: %d\n",
-                ioread8(priv->mac_io + MAC_CRC_ERR_CNT));
-        dev_dbg(dev, "TX frame counter: %d\n",
-                ioread32(priv->mac_io + MAC_TX_FRAME_CNT));
-        dev_dbg(dev, "RX frame counter: %d\n",
-                ioread32(priv->mac_io + MAC_RX_FRAME_CNT));
-        dev_dbg(dev, "TX fifo level: %d\n",
-                ioread8(priv->mac_io + MAC_TX_FIFO_LVL));
-        dev_dbg(dev, "Dropped frames: %d\n",
-                ioread8(priv->mac_io + MAC_DROPPED_FRMS));
-        dev_dbg(dev, "Connected with CCAT slot: %d\n",
-                ioread8(priv->mac_io + MAC_CONNECTED_CCAT_FLAG));
-        dev_dbg(dev, "Link status: %d\n",
-                ioread8(priv->mii_io + MII_LINK_STATUS));
-}
-
 static void ec_bhf_reset(struct ec_bhf_priv *priv)
 {
         iowrite8(0, priv->mac_io + MAC_FRAME_ERR_CNT);
@@ -210,8 +182,6 @@ static void ec_bhf_send_packet(struct ec_bhf_priv *priv, struct tx_desc *desc)
         u32 addr = (u8 *)desc - priv->tx_buf.buf;
 
         iowrite32((ALIGN(len, 8) << 24) | addr, priv->fifo_io + FIFO_TX_REG);
-
-        dev_dbg(PRIV_TO_DEV(priv), "Done sending packet\n");
 }
 
 static int ec_bhf_desc_sent(struct tx_desc *desc)
@@ -244,7 +214,6 @@ static void ec_bhf_add_rx_desc(struct ec_bhf_priv *priv, struct rx_desc *desc)
 static void ec_bhf_process_rx(struct ec_bhf_priv *priv)
 {
         struct rx_desc *desc = &priv->rx_descs[priv->rx_dnext];
-        struct device *dev = PRIV_TO_DEV(priv);
 
         while (ec_bhf_pkt_received(desc)) {
                 int pkt_size = (le16_to_cpu(desc->header.len) &
@@ -253,20 +222,16 @@ static void ec_bhf_process_rx(struct ec_bhf_priv *priv)
                 struct sk_buff *skb;
 
                 skb = netdev_alloc_skb_ip_align(priv->net_dev, pkt_size);
-                dev_dbg(dev, "Received packet, size: %d\n", pkt_size);
-
                 if (skb) {
                         memcpy(skb_put(skb, pkt_size), data, pkt_size);
                         skb->protocol = eth_type_trans(skb, priv->net_dev);
-                        dev_dbg(dev, "Protocol type: %x\n", skb->protocol);
-
                         priv->stat_rx_bytes += pkt_size;
 
                         netif_rx(skb);
                 } else {
-                        dev_err_ratelimited(dev,
-                                "Couldn't allocate a skb_buff for a packet of size %u\n",
-                                pkt_size);
+                        dev_err_ratelimited(PRIV_TO_DEV(priv),
+                                            "Couldn't allocate a skb_buff for a packet of size %u\n",
+                                            pkt_size);
                 }
 
                 desc->header.recv = 0;
@@ -276,7 +241,6 @@ static void ec_bhf_process_rx(struct ec_bhf_priv *priv)
                 priv->rx_dnext = (priv->rx_dnext + 1) % priv->rx_dcount;
                 desc = &priv->rx_descs[priv->rx_dnext];
         }
-
 }
 
 static enum hrtimer_restart ec_bhf_timer_fun(struct hrtimer *timer)
@@ -299,14 +263,7 @@ static int ec_bhf_setup_offsets(struct ec_bhf_priv *priv)
         unsigned block_count, i;
         void __iomem *ec_info;
 
-        dev_dbg(dev, "Info block:\n");
-        dev_dbg(dev, "Type of function: %x\n", (unsigned)ioread16(priv->io));
-        dev_dbg(dev, "Revision of function: %x\n",
-                (unsigned)ioread16(priv->io + INFO_BLOCK_REV));
-
         block_count = ioread8(priv->io + INFO_BLOCK_BLK_CNT);
-        dev_dbg(dev, "Number of function blocks: %x\n", block_count);
-
         for (i = 0; i < block_count; i++) {
                 u16 type = ioread16(priv->io + i * INFO_BLOCK_SIZE +
                                     INFO_BLOCK_TYPE);
@@ -317,29 +274,17 @@ static int ec_bhf_setup_offsets(struct ec_bhf_priv *priv)
                 dev_err(dev, "EtherCAT master with DMA block not found\n");
                 return -ENODEV;
         }
-        dev_dbg(dev, "EtherCAT master with DMA block found at pos: %d\n", i);
 
         ec_info = priv->io + i * INFO_BLOCK_SIZE;
-        dev_dbg(dev, "EtherCAT master revision: %d\n",
-                ioread16(ec_info + INFO_BLOCK_REV));
 
         priv->tx_dma_chan = ioread8(ec_info + INFO_BLOCK_TX_CHAN);
-        dev_dbg(dev, "EtherCAT master tx dma channel: %d\n",
-                priv->tx_dma_chan);
-
         priv->rx_dma_chan = ioread8(ec_info + INFO_BLOCK_RX_CHAN);
-        dev_dbg(dev, "EtherCAT master rx dma channel: %d\n",
-                 priv->rx_dma_chan);
 
         priv->ec_io = priv->io + ioread32(ec_info + INFO_BLOCK_OFFSET);
         priv->mii_io = priv->ec_io + ioread32(priv->ec_io + EC_MII_OFFSET);
         priv->fifo_io = priv->ec_io + ioread32(priv->ec_io + EC_FIFO_OFFSET);
         priv->mac_io = priv->ec_io + ioread32(priv->ec_io + EC_MAC_OFFSET);
 
-        dev_dbg(dev,
-                "EtherCAT block addres: %p, fifo address: %p, mii address: %p, mac address: %p\n",
-                priv->ec_io, priv->fifo_io, priv->mii_io, priv->mac_io);
-
         return 0;
 }
 
@@ -350,8 +295,6 @@ static netdev_tx_t ec_bhf_start_xmit(struct sk_buff *skb,
         struct tx_desc *desc;
         unsigned len;
 
-        dev_dbg(PRIV_TO_DEV(priv), "Starting xmit\n");
-
         desc = &priv->tx_descs[priv->tx_dnext];
 
         skb_copy_and_csum_dev(skb, desc->data);
@@ -366,15 +309,12 @@ static netdev_tx_t ec_bhf_start_xmit(struct sk_buff *skb,
         priv->tx_dnext = (priv->tx_dnext + 1) % priv->tx_dcount;
 
         if (!ec_bhf_desc_sent(&priv->tx_descs[priv->tx_dnext])) {
-                /* Make sure that update updates to tx_dnext are perceived
+                /* Make sure that updates to tx_dnext are perceived
                  * by timer routine.
                  */
                 smp_wmb();
 
                 netif_stop_queue(net_dev);
-
-                dev_dbg(PRIV_TO_DEV(priv), "Stopping netif queue\n");
-                ec_bhf_print_status(priv);
         }
 
         priv->stat_tx_bytes += len;
@@ -397,7 +337,6 @@ static int ec_bhf_alloc_dma_mem(struct ec_bhf_priv *priv,
 
         mask = ioread32(priv->dma_io + offset);
         mask &= DMA_WINDOW_SIZE_MASK;
-        dev_dbg(dev, "Read mask %x for channel %d\n", mask, channel);
 
         /* We want to allocate a chunk of memory that is:
          * - aligned to the mask we just read
@@ -408,12 +347,10 @@ static int ec_bhf_alloc_dma_mem(struct ec_bhf_priv *priv,
         buf->len = min_t(int, ~mask + 1, size);
         buf->alloc_len = 2 * buf->len;
 
-        dev_dbg(dev, "Allocating %d bytes for channel %d",
-                (int)buf->alloc_len, channel);
         buf->alloc = dma_alloc_coherent(dev, buf->alloc_len, &buf->alloc_phys,
                                         GFP_KERNEL);
         if (buf->alloc == NULL) {
-                dev_info(dev, "Failed to allocate buffer\n");
+                dev_err(dev, "Failed to allocate buffer\n");
                 return -ENOMEM;
         }
 
@@ -422,8 +359,6 @@ static int ec_bhf_alloc_dma_mem(struct ec_bhf_priv *priv,
 
         iowrite32(0, priv->dma_io + offset + 4);
         iowrite32(buf->buf_phys, priv->dma_io + offset);
-        dev_dbg(dev, "Buffer: %x and read from dev: %x",
-                (unsigned)buf->buf_phys, ioread32(priv->dma_io + offset));
 
         return 0;
 }
@@ -433,7 +368,7 @@ static void ec_bhf_setup_tx_descs(struct ec_bhf_priv *priv)
         int i = 0;
 
         priv->tx_dcount = priv->tx_buf.len / sizeof(struct tx_desc);
-        priv->tx_descs = (struct tx_desc *) priv->tx_buf.buf;
+        priv->tx_descs = (struct tx_desc *)priv->tx_buf.buf;
         priv->tx_dnext = 0;
 
         for (i = 0; i < priv->tx_dcount; i++)
@@ -445,7 +380,7 @@ static void ec_bhf_setup_rx_descs(struct ec_bhf_priv *priv)
         int i;
 
         priv->rx_dcount = priv->rx_buf.len / sizeof(struct rx_desc);
-        priv->rx_descs = (struct rx_desc *) priv->rx_buf.buf;
+        priv->rx_descs = (struct rx_desc *)priv->rx_buf.buf;
         priv->rx_dnext = 0;
 
         for (i = 0; i < priv->rx_dcount; i++) {
@@ -469,8 +404,6 @@ static int ec_bhf_open(struct net_device *net_dev)
         struct device *dev = PRIV_TO_DEV(priv);
         int err = 0;
 
-        dev_info(dev, "Opening device\n");
-
         ec_bhf_reset(priv);
 
         err = ec_bhf_alloc_dma_mem(priv, &priv->rx_buf, priv->rx_dma_chan,
@@ -481,20 +414,13 @@ static int ec_bhf_open(struct net_device *net_dev)
         }
         ec_bhf_setup_rx_descs(priv);
 
-        dev_info(dev, "RX buffer allocated, address: %x\n",
-                 (unsigned)priv->rx_buf.buf_phys);
-
         err = ec_bhf_alloc_dma_mem(priv, &priv->tx_buf, priv->tx_dma_chan,
                                    FIFO_SIZE * sizeof(struct tx_desc));
         if (err) {
                 dev_err(dev, "Failed to allocate tx buffer\n");
                 goto error_rx_free;
         }
-        dev_dbg(dev, "TX buffer allocated, addres: %x\n",
-                (unsigned)priv->tx_buf.buf_phys);
-
         iowrite8(0, priv->mii_io + MII_MAC_FILT_FLAG);
-
         ec_bhf_setup_tx_descs(priv);
 
         netif_start_queue(net_dev);
@@ -504,10 +430,6 @@ static int ec_bhf_open(struct net_device *net_dev)
         hrtimer_start(&priv->hrtimer, ktime_set(0, polling_frequency),
                       HRTIMER_MODE_REL);
 
-        dev_info(PRIV_TO_DEV(priv), "Device open\n");
-
-        ec_bhf_print_status(priv);
-
         return 0;
 
 error_rx_free:
@@ -640,9 +562,6 @@ static int ec_bhf_probe(struct pci_dev *dev, const struct pci_device_id *id)
 
         memcpy_fromio(net_dev->dev_addr, priv->mii_io + MII_MAC_ADDR, 6);
 
-        dev_dbg(&dev->dev, "CX5020 Ethercat master address: %pM\n",
-                net_dev->dev_addr);
-
         err = register_netdev(net_dev);
         if (err < 0)
                 goto err_free_net_dev;
diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h
index 43e08d0bc3d3..a9f239adc3e3 100644
--- a/drivers/net/ethernet/emulex/benet/be.h
+++ b/drivers/net/ethernet/emulex/benet/be.h
@@ -86,6 +86,8 @@ static inline char *nic_name(struct pci_dev *pdev)
 
 #define BE_MAX_JUMBO_FRAME_SIZE 9018
 #define BE_MIN_MTU              256
+#define BE_MAX_MTU              (BE_MAX_JUMBO_FRAME_SIZE -      \
+                                 (ETH_HLEN + ETH_FCS_LEN))
 
 #define BE_NUM_VLANS_SUPPORTED  64
 #define BE_MAX_EQD              128u
@@ -112,7 +114,6 @@ static inline char *nic_name(struct pci_dev *pdev)
 #define MAX_ROCE_EQS            5
 #define MAX_MSIX_VECTORS        32
 #define MIN_MSIX_VECTORS        1
-#define BE_TX_BUDGET            256
 #define BE_NAPI_WEIGHT          64
 #define MAX_RX_POST             BE_NAPI_WEIGHT /* Frags posted at a time */
 #define RX_FRAGS_REFILL_WM      (RX_Q_LEN - MAX_RX_POST)
@@ -198,7 +199,6 @@ struct be_eq_obj {
 
         u8 idx;                 /* array index */
         u8 msix_idx;
-        u16 tx_budget;
         u16 spurious_intr;
         struct napi_struct napi;
         struct be_adapter *adapter;
@@ -248,6 +248,13 @@ struct be_tx_stats {
         ulong tx_jiffies;
         u32 tx_stops;
         u32 tx_drv_drops;       /* pkts dropped by driver */
+        /* the error counters are described in be_ethtool.c */
+        u32 tx_hdr_parse_err;
+        u32 tx_dma_err;
+        u32 tx_tso_err;
+        u32 tx_spoof_check_err;
+        u32 tx_qinq_err;
+        u32 tx_internal_parity_err;
         struct u64_stats_sync sync;
         struct u64_stats_sync sync_compl;
 };
@@ -316,6 +323,7 @@ struct be_rx_obj {
 struct be_drv_stats {
         u32 be_on_die_temperature;
         u32 eth_red_drops;
+        u32 dma_map_errors;
         u32 rx_drops_no_pbuf;
         u32 rx_drops_no_txpb;
         u32 rx_drops_no_erx_descr;
@@ -613,6 +621,10 @@ extern const struct ethtool_ops be_ethtool_ops;
         for (i = eqo->idx, rxo = &adapter->rx_obj[i]; i < adapter->num_rx_qs;\
                  i += adapter->num_evt_qs, rxo += adapter->num_evt_qs)
 
+#define for_all_tx_queues_on_eq(adapter, eqo, txo, i)                   \
+        for (i = eqo->idx, txo = &adapter->tx_obj[i]; i < adapter->num_tx_qs;\
+                i += adapter->num_evt_qs, txo += adapter->num_evt_qs)
+
 #define is_mcc_eqo(eqo)                 (eqo->idx == 0)
 #define mcc_eqo(adapter)                (&adapter->eq_obj[0])
 
@@ -661,6 +673,18 @@ static inline u32 amap_get(void *ptr, u32 dw_offset, u32 mask, u32 offset)
                         amap_mask(sizeof(((_struct *)0)->field)),       \
                         AMAP_BIT_OFFSET(_struct, field))
 
+#define GET_RX_COMPL_V0_BITS(field, ptr)                                \
+                AMAP_GET_BITS(struct amap_eth_rx_compl_v0, field, ptr)
+
+#define GET_RX_COMPL_V1_BITS(field, ptr)                                \
+                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, field, ptr)
+
+#define GET_TX_COMPL_BITS(field, ptr)                                   \
+                AMAP_GET_BITS(struct amap_eth_tx_compl, field, ptr)
+
+#define SET_TX_WRB_HDR_BITS(field, ptr, val)                            \
+                AMAP_SET_BITS(struct amap_eth_hdr_wrb, field, ptr, val)
+
 #define be_dws_cpu_to_le(wrb, len)      swap_dws(wrb, len)
 #define be_dws_le_to_cpu(wrb, len)      swap_dws(wrb, len)
 static inline void swap_dws(void *wrb, int len)
diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c
index 4370ec1952ac..5be100d1bc0a 100644
--- a/drivers/net/ethernet/emulex/benet/be_cmds.c
+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c
@@ -1681,17 +1681,17 @@ err:
         return status;
 }
 
-void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
+int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
 {
         struct be_dma_mem get_fat_cmd;
         struct be_mcc_wrb *wrb;
         struct be_cmd_req_get_fat *req;
         u32 offset = 0, total_size, buf_size,
                                 log_offset = sizeof(u32), payload_len;
-        int status;
+        int status = 0;
 
         if (buf_len == 0)
-                return;
+                return -EIO;
 
         total_size = buf_len;
 
@@ -1700,10 +1700,9 @@ void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
                                               get_fat_cmd.size,
                                               &get_fat_cmd.dma);
         if (!get_fat_cmd.va) {
-                status = -ENOMEM;
                 dev_err(&adapter->pdev->dev,
                 "Memory allocation failure while retrieving FAT data\n");
-                return;
+                return -ENOMEM;
         }
 
         spin_lock_bh(&adapter->mcc_lock);
@@ -1746,6 +1745,7 @@ err:
         pci_free_consistent(adapter->pdev, get_fat_cmd.size,
                             get_fat_cmd.va, get_fat_cmd.dma);
         spin_unlock_bh(&adapter->mcc_lock);
+        return status;
 }
 
 /* Uses synchronous mcc */
@@ -1771,6 +1771,7 @@ int be_cmd_get_fw_ver(struct be_adapter *adapter)
         status = be_mcc_notify_wait(adapter);
         if (!status) {
                 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
+
                 strcpy(adapter->fw_ver, resp->firmware_version_string);
                 strcpy(adapter->fw_on_flash, resp->fw_on_flash_version_string);
         }
@@ -2018,6 +2019,9 @@ int be_cmd_query_fw_cfg(struct be_adapter *adapter)
                 adapter->function_mode = le32_to_cpu(resp->function_mode);
                 adapter->function_caps = le32_to_cpu(resp->function_caps);
                 adapter->asic_rev = le32_to_cpu(resp->asic_revision) & 0xFF;
+                dev_info(&adapter->pdev->dev,
+                         "FW config: function_mode=0x%x, function_caps=0x%x\n",
+                         adapter->function_mode, adapter->function_caps);
         }
 
         mutex_unlock(&adapter->mbox_lock);
diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.h b/drivers/net/ethernet/emulex/benet/be_cmds.h
index 5284b825bba2..0e1186856aa6 100644
--- a/drivers/net/ethernet/emulex/benet/be_cmds.h
+++ b/drivers/net/ethernet/emulex/benet/be_cmds.h
@@ -2101,7 +2101,7 @@ int be_cmd_get_die_temperature(struct be_adapter *adapter);
 int be_cmd_get_cntl_attributes(struct be_adapter *adapter);
 int be_cmd_req_native_mode(struct be_adapter *adapter);
 int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size);
-void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
+int be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf);
 int be_cmd_get_fn_privileges(struct be_adapter *adapter, u32 *privilege,
                              u32 domain);
 int be_cmd_set_fn_privileges(struct be_adapter *adapter, u32 privileges,
diff --git a/drivers/net/ethernet/emulex/benet/be_ethtool.c b/drivers/net/ethernet/emulex/benet/be_ethtool.c
index 0cd3311409a8..2fd38261bedb 100644
--- a/drivers/net/ethernet/emulex/benet/be_ethtool.c
+++ b/drivers/net/ethernet/emulex/benet/be_ethtool.c
@@ -78,6 +78,11 @@ static const struct be_ethtool_stat et_stats[] = {
          * fifo must never overflow.
          */
         {DRVSTAT_INFO(rxpp_fifo_overflow_drop)},
+        /* Received packets dropped when the RX block runs out of space in
+         * one of its input FIFOs. This could happen due a long burst of
+         * minimum-sized (64b) frames in the receive path.
+         * This counter may also be erroneously incremented rarely.
+         */
         {DRVSTAT_INFO(rx_input_fifo_overflow_drop)},
         {DRVSTAT_INFO(rx_ip_checksum_errs)},
         {DRVSTAT_INFO(rx_tcp_checksum_errs)},
@@ -114,6 +119,8 @@ static const struct be_ethtool_stat et_stats[] = {
          * is more than 9018 bytes
          */
         {DRVSTAT_INFO(rx_drops_mtu)},
+        /* Number of dma mapping errors */
+        {DRVSTAT_INFO(dma_map_errors)},
         /* Number of packets dropped due to random early drop function */
         {DRVSTAT_INFO(eth_red_drops)},
         {DRVSTAT_INFO(be_on_die_temperature)},
@@ -152,6 +159,34 @@ static const struct be_ethtool_stat et_rx_stats[] = {
  */
 static const struct be_ethtool_stat et_tx_stats[] = {
         {DRVSTAT_TX_INFO(tx_compl)}, /* If moving this member see above note */
+        /* This counter is incremented when the HW encounters an error while
+         * parsing the packet header of an outgoing TX request. This counter is
+         * applicable only for BE2, BE3 and Skyhawk based adapters.
+         */
+        {DRVSTAT_TX_INFO(tx_hdr_parse_err)},
+        /* This counter is incremented when an error occurs in the DMA
+         * operation associated with the TX request from the host to the device.
+         */
+        {DRVSTAT_TX_INFO(tx_dma_err)},
+        /* This counter is incremented when MAC or VLAN spoof checking is
+         * enabled on the interface and the TX request fails the spoof check
+         * in HW.
+         */
+        {DRVSTAT_TX_INFO(tx_spoof_check_err)},
+        /* This counter is incremented when the HW encounters an error while
+         * performing TSO offload. This counter is applicable only for Lancer
+         * adapters.
+         */
+        {DRVSTAT_TX_INFO(tx_tso_err)},
+        /* This counter is incremented when the HW detects Q-in-Q style VLAN
+         * tagging in a packet and such tagging is not expected on the outgoing
+         * interface. This counter is applicable only for Lancer adapters.
+         */
+        {DRVSTAT_TX_INFO(tx_qinq_err)},
+        /* This counter is incremented when the HW detects parity errors in the
+         * packet data. This counter is applicable only for Lancer adapters.
+         */
+        {DRVSTAT_TX_INFO(tx_internal_parity_err)},
         {DRVSTAT_TX_INFO(tx_bytes)},
         {DRVSTAT_TX_INFO(tx_pkts)},
         /* Number of skbs queued for trasmission by the driver */
diff --git a/drivers/net/ethernet/emulex/benet/be_hw.h b/drivers/net/ethernet/emulex/benet/be_hw.h
index 8840c64aaeca..295ee0835ba0 100644
--- a/drivers/net/ethernet/emulex/benet/be_hw.h
+++ b/drivers/net/ethernet/emulex/benet/be_hw.h
@@ -315,6 +315,18 @@ struct be_eth_hdr_wrb {
         u32 dw[4];
 };
 
+/********* Tx Compl Status Encoding *********/
+#define BE_TX_COMP_HDR_PARSE_ERR        0x2
+#define BE_TX_COMP_NDMA_ERR             0x3
+#define BE_TX_COMP_ACL_ERR              0x5
+
+#define LANCER_TX_COMP_LSO_ERR                  0x1
+#define LANCER_TX_COMP_HSW_DROP_MAC_ERR         0x3
+#define LANCER_TX_COMP_HSW_DROP_VLAN_ERR        0x5
+#define LANCER_TX_COMP_QINQ_ERR                 0x7
+#define LANCER_TX_COMP_PARITY_ERR               0xb
+#define LANCER_TX_COMP_DMA_ERR                  0xd
+
 /* TX Compl Queue Descriptor */
 
 /* Pseudo amap definition for eth_tx_compl in which each bit of the
diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c
index 93ff8ef39352..5b26c4c9ab2b 100644
--- a/drivers/net/ethernet/emulex/benet/be_main.c
+++ b/drivers/net/ethernet/emulex/benet/be_main.c
@@ -738,38 +738,37 @@ static void wrb_fill_hdr(struct be_adapter *adapter, struct be_eth_hdr_wrb *hdr,
 
         memset(hdr, 0, sizeof(*hdr));
 
-        AMAP_SET_BITS(struct amap_eth_hdr_wrb, crc, hdr, 1);
+        SET_TX_WRB_HDR_BITS(crc, hdr, 1);
 
         if (skb_is_gso(skb)) {
-                AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso, hdr, 1);
-                AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso_mss,
-                        hdr, skb_shinfo(skb)->gso_size);
+                SET_TX_WRB_HDR_BITS(lso, hdr, 1);
+                SET_TX_WRB_HDR_BITS(lso_mss, hdr, skb_shinfo(skb)->gso_size);
                 if (skb_is_gso_v6(skb) && !lancer_chip(adapter))
-                        AMAP_SET_BITS(struct amap_eth_hdr_wrb, lso6, hdr, 1);
+                        SET_TX_WRB_HDR_BITS(lso6, hdr, 1);
         } else if (skb->ip_summed == CHECKSUM_PARTIAL) {
                 if (skb->encapsulation) {
-                        AMAP_SET_BITS(struct amap_eth_hdr_wrb, ipcs, hdr, 1);
+                        SET_TX_WRB_HDR_BITS(ipcs, hdr, 1);
                         proto = skb_inner_ip_proto(skb);
                 } else {
                         proto = skb_ip_proto(skb);
                 }
                 if (proto == IPPROTO_TCP)
-                        AMAP_SET_BITS(struct amap_eth_hdr_wrb, tcpcs, hdr, 1);
+                        SET_TX_WRB_HDR_BITS(tcpcs, hdr, 1);
                 else if (proto == IPPROTO_UDP)
-                        AMAP_SET_BITS(struct amap_eth_hdr_wrb, udpcs, hdr, 1);
+                        SET_TX_WRB_HDR_BITS(udpcs, hdr, 1);
         }
 
         if (vlan_tx_tag_present(skb)) {
-                AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan, hdr, 1);
+                SET_TX_WRB_HDR_BITS(vlan, hdr, 1);
                 vlan_tag = be_get_tx_vlan_tag(adapter, skb);
-                AMAP_SET_BITS(struct amap_eth_hdr_wrb, vlan_tag, hdr, vlan_tag);
+                SET_TX_WRB_HDR_BITS(vlan_tag, hdr, vlan_tag);
         }
 
         /* To skip HW VLAN tagging: evt = 1, compl = 0 */
-        AMAP_SET_BITS(struct amap_eth_hdr_wrb, complete, hdr, !skip_hw_vlan);
-        AMAP_SET_BITS(struct amap_eth_hdr_wrb, event, hdr, 1);
-        AMAP_SET_BITS(struct amap_eth_hdr_wrb, num_wrb, hdr, wrb_cnt);
-        AMAP_SET_BITS(struct amap_eth_hdr_wrb, len, hdr, len);
+        SET_TX_WRB_HDR_BITS(complete, hdr, !skip_hw_vlan);
+        SET_TX_WRB_HDR_BITS(event, hdr, 1);
+        SET_TX_WRB_HDR_BITS(num_wrb, hdr, wrb_cnt);
+        SET_TX_WRB_HDR_BITS(len, hdr, len);
 }
 
 static void unmap_tx_frag(struct device *dev, struct be_eth_wrb *wrb,
@@ -850,6 +849,7 @@ dma_err:
                 unmap_tx_frag(dev, wrb, map_single);
                 map_single = false;
                 copied -= wrb->frag_len;
+                adapter->drv_stats.dma_map_errors++;
                 queue_head_inc(txq);
         }
         return 0;
@@ -1073,15 +1073,15 @@ static netdev_tx_t be_xmit(struct sk_buff *skb, struct net_device *netdev)
 static int be_change_mtu(struct net_device *netdev, int new_mtu)
 {
         struct be_adapter *adapter = netdev_priv(netdev);
-        if (new_mtu < BE_MIN_MTU ||
-            new_mtu > (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN))) {
-                dev_info(&adapter->pdev->dev,
-                         "MTU must be between %d and %d bytes\n",
-                         BE_MIN_MTU,
-                         (BE_MAX_JUMBO_FRAME_SIZE - (ETH_HLEN + ETH_FCS_LEN)));
+        struct device *dev = &adapter->pdev->dev;
+
+        if (new_mtu < BE_MIN_MTU || new_mtu > BE_MAX_MTU) {
+                dev_info(dev, "MTU must be between %d and %d bytes\n",
+                         BE_MIN_MTU, BE_MAX_MTU);
                 return -EINVAL;
         }
-        dev_info(&adapter->pdev->dev, "MTU changed from %d to %d bytes\n",
+
+        dev_info(dev, "MTU changed from %d to %d bytes\n",
                  netdev->mtu, new_mtu);
         netdev->mtu = new_mtu;
         return 0;
@@ -1683,7 +1683,7 @@ static void be_rx_compl_process(struct be_rx_obj *rxo, struct napi_struct *napi,
         if (netdev->features & NETIF_F_RXHASH)
                 skb_set_hash(skb, rxcp->rss_hash, PKT_HASH_TYPE_L3);
 
-        skb->encapsulation = rxcp->tunneled;
+        skb->csum_level = rxcp->tunneled;
         skb_mark_napi_id(skb, napi);
 
         if (rxcp->vlanf)
@@ -1741,7 +1741,7 @@ static void be_rx_compl_process_gro(struct be_rx_obj *rxo,
         if (adapter->netdev->features & NETIF_F_RXHASH)
                 skb_set_hash(skb, rxcp->rss_hash, PKT_HASH_TYPE_L3);
 
-        skb->encapsulation = rxcp->tunneled;
+        skb->csum_level = rxcp->tunneled;
         skb_mark_napi_id(skb, napi);
 
         if (rxcp->vlanf)
@@ -1753,65 +1753,46 @@ static void be_rx_compl_process_gro(struct be_rx_obj *rxo,
 static void be_parse_rx_compl_v1(struct be_eth_rx_compl *compl,
                                  struct be_rx_compl_info *rxcp)
 {
-        rxcp->pkt_size =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, pktsize, compl);
-        rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, vtp, compl);
-        rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, err, compl);
-        rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, tcpf, compl);
-        rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, udpf, compl);
-        rxcp->ip_csum =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ipcksm, compl);
-        rxcp->l4_csum =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, l4_cksm, compl);
-        rxcp->ipv6 =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, ip_version, compl);
-        rxcp->num_rcvd =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, numfrags, compl);
-        rxcp->pkt_type =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, cast_enc, compl);
-        rxcp->rss_hash =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, rsshash, compl);
+        rxcp->pkt_size = GET_RX_COMPL_V1_BITS(pktsize, compl);
+        rxcp->vlanf = GET_RX_COMPL_V1_BITS(vtp, compl);
+        rxcp->err = GET_RX_COMPL_V1_BITS(err, compl);
+        rxcp->tcpf = GET_RX_COMPL_V1_BITS(tcpf, compl);
+        rxcp->udpf = GET_RX_COMPL_V1_BITS(udpf, compl);
+        rxcp->ip_csum = GET_RX_COMPL_V1_BITS(ipcksm, compl);
+        rxcp->l4_csum = GET_RX_COMPL_V1_BITS(l4_cksm, compl);
+        rxcp->ipv6 = GET_RX_COMPL_V1_BITS(ip_version, compl);
+        rxcp->num_rcvd = GET_RX_COMPL_V1_BITS(numfrags, compl);
+        rxcp->pkt_type = GET_RX_COMPL_V1_BITS(cast_enc, compl);
+        rxcp->rss_hash = GET_RX_COMPL_V1_BITS(rsshash, compl);
         if (rxcp->vlanf) {
-                rxcp->qnq = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, qnq,
-                                          compl);
-                rxcp->vlan_tag = AMAP_GET_BITS(struct amap_eth_rx_compl_v1,
-                                               vlan_tag, compl);
+                rxcp->qnq = GET_RX_COMPL_V1_BITS(qnq, compl);
+                rxcp->vlan_tag = GET_RX_COMPL_V1_BITS(vlan_tag, compl);
         }
-        rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v1, port, compl);
+        rxcp->port = GET_RX_COMPL_V1_BITS(port, compl);
         rxcp->tunneled =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v1, tunneled, compl);
+                GET_RX_COMPL_V1_BITS(tunneled, compl);
 }
 
 static void be_parse_rx_compl_v0(struct be_eth_rx_compl *compl,
                                  struct be_rx_compl_info *rxcp)
 {
-        rxcp->pkt_size =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v0, pktsize, compl);
-        rxcp->vlanf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, vtp, compl);
-        rxcp->err = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, err, compl);
-        rxcp->tcpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, tcpf, compl);
-        rxcp->udpf = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, udpf, compl);
-        rxcp->ip_csum =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ipcksm, compl);
-        rxcp->l4_csum =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v0, l4_cksm, compl);
-        rxcp->ipv6 =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v0, ip_version, compl);
-        rxcp->num_rcvd =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v0, numfrags, compl);
-        rxcp->pkt_type =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v0, cast_enc, compl);
-        rxcp->rss_hash =
-                AMAP_GET_BITS(struct amap_eth_rx_compl_v0, rsshash, compl);
+        rxcp->pkt_size = GET_RX_COMPL_V0_BITS(pktsize, compl);
+        rxcp->vlanf = GET_RX_COMPL_V0_BITS(vtp, compl);
+        rxcp->err = GET_RX_COMPL_V0_BITS(err, compl);
+        rxcp->tcpf = GET_RX_COMPL_V0_BITS(tcpf, compl);
+        rxcp->udpf = GET_RX_COMPL_V0_BITS(udpf, compl);
+        rxcp->ip_csum = GET_RX_COMPL_V0_BITS(ipcksm, compl);
+        rxcp->l4_csum = GET_RX_COMPL_V0_BITS(l4_cksm, compl);
+        rxcp->ipv6 = GET_RX_COMPL_V0_BITS(ip_version, compl);
+        rxcp->num_rcvd = GET_RX_COMPL_V0_BITS(numfrags, compl);
+        rxcp->pkt_type = GET_RX_COMPL_V0_BITS(cast_enc, compl);
+        rxcp->rss_hash = GET_RX_COMPL_V0_BITS(rsshash, compl);
         if (rxcp->vlanf) {
-                rxcp->qnq = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, qnq,
-                                          compl);
-                rxcp->vlan_tag = AMAP_GET_BITS(struct amap_eth_rx_compl_v0,
-                                               vlan_tag, compl);
+                rxcp->qnq = GET_RX_COMPL_V0_BITS(qnq, compl);
+                rxcp->vlan_tag = GET_RX_COMPL_V0_BITS(vlan_tag, compl);
         }
-        rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, port, compl);
-        rxcp->ip_frag = AMAP_GET_BITS(struct amap_eth_rx_compl_v0,
-                                      ip_frag, compl);
+        rxcp->port = GET_RX_COMPL_V0_BITS(port, compl);
+        rxcp->ip_frag = GET_RX_COMPL_V0_BITS(ip_frag, compl);
 }
 
 static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
@@ -1897,7 +1878,7 @@ static void be_post_rx_frags(struct be_rx_obj *rxo, gfp_t gfp)
                         if (dma_mapping_error(dev, page_dmaaddr)) {
                                 put_page(pagep);
                                 pagep = NULL;
-                                rx_stats(rxo)->rx_post_fail++;
+                                adapter->drv_stats.dma_map_errors++;
                                 break;
                         }
                         page_offset = 0;
@@ -1991,7 +1972,7 @@ static u16 be_tx_compl_process(struct be_adapter *adapter,
                 queue_tail_inc(txq);
         } while (cur_index != last_index);
 
-        dev_kfree_skb_any(sent_skb);
+        dev_consume_skb_any(sent_skb);
         return num_wrbs;
 }
 
@@ -2091,9 +2072,7 @@ static void be_tx_compl_clean(struct be_adapter *adapter)
                         num_wrbs = 0;
                         txq = &txo->q;
                         while ((txcp = be_tx_compl_get(&txo->cq))) {
-                                end_idx =
-                                        AMAP_GET_BITS(struct amap_eth_tx_compl,
-                                                      wrb_index, txcp);
+                                end_idx = GET_TX_COMPL_BITS(wrb_index, txcp);
                                 num_wrbs += be_tx_compl_process(adapter, txo,
                                                                 end_idx);
                                 cmpl++;
@@ -2164,7 +2143,6 @@ static int be_evt_queues_create(struct be_adapter *adapter)
                 napi_hash_add(&eqo->napi);
                 aic = &adapter->aic_obj[i];
                 eqo->adapter = adapter;
-                eqo->tx_budget = BE_TX_BUDGET;
                 eqo->idx = i;
                 aic->max_eqd = BE_MAX_EQD;
                 aic->enable = true;
@@ -2443,20 +2421,63 @@ loop_continue:
         return work_done;
 }
 
-static bool be_process_tx(struct be_adapter *adapter, struct be_tx_obj *txo,
-                          int budget, int idx)
+static inline void be_update_tx_err(struct be_tx_obj *txo, u32 status)
+{
+        switch (status) {
+        case BE_TX_COMP_HDR_PARSE_ERR:
+                tx_stats(txo)->tx_hdr_parse_err++;
+                break;
+        case BE_TX_COMP_NDMA_ERR:
+                tx_stats(txo)->tx_dma_err++;
+                break;
+        case BE_TX_COMP_ACL_ERR:
+                tx_stats(txo)->tx_spoof_check_err++;
+                break;
+        }
+}
+
+static inline void lancer_update_tx_err(struct be_tx_obj *txo, u32 status)
+{
+        switch (status) {
+        case LANCER_TX_COMP_LSO_ERR:
+                tx_stats(txo)->tx_tso_err++;
+                break;
+        case LANCER_TX_COMP_HSW_DROP_MAC_ERR:
+        case LANCER_TX_COMP_HSW_DROP_VLAN_ERR:
+                tx_stats(txo)->tx_spoof_check_err++;
+                break;
+        case LANCER_TX_COMP_QINQ_ERR:
+                tx_stats(txo)->tx_qinq_err++;
+                break;
+        case LANCER_TX_COMP_PARITY_ERR:
+                tx_stats(txo)->tx_internal_parity_err++;
+                break;
+        case LANCER_TX_COMP_DMA_ERR:
+                tx_stats(txo)->tx_dma_err++;
+                break;
+        }
+}
+
+static void be_process_tx(struct be_adapter *adapter, struct be_tx_obj *txo,
+                          int idx)
 {
         struct be_eth_tx_compl *txcp;
-        int num_wrbs = 0, work_done;
+        int num_wrbs = 0, work_done = 0;
+        u32 compl_status;
+        u16 last_idx;
 
-        for (work_done = 0; work_done < budget; work_done++) {
-                txcp = be_tx_compl_get(&txo->cq);
-                if (!txcp)
-                        break;
-                num_wrbs += be_tx_compl_process(adapter, txo,
-                                                AMAP_GET_BITS(struct
-                                                              amap_eth_tx_compl,
-                                                              wrb_index, txcp));
+        while ((txcp = be_tx_compl_get(&txo->cq))) {
+                last_idx = GET_TX_COMPL_BITS(wrb_index, txcp);
+                num_wrbs += be_tx_compl_process(adapter, txo, last_idx);
+                work_done++;
+
+                compl_status = GET_TX_COMPL_BITS(status, txcp);
+                if (compl_status) {
+                        if (lancer_chip(adapter))
+                                lancer_update_tx_err(txo, compl_status);
+                        else
+                                be_update_tx_err(txo, compl_status);
+                }
         }
 
         if (work_done) {
@@ -2474,7 +2495,6 @@ static bool be_process_tx(struct be_adapter *adapter, struct be_tx_obj *txo,
                 tx_stats(txo)->tx_compl += work_done;
                 u64_stats_update_end(&tx_stats(txo)->sync_compl);
         }
-        return (work_done < budget); /* Done */
 }
 
 int be_poll(struct napi_struct *napi, int budget)
@@ -2483,17 +2503,12 @@ int be_poll(struct napi_struct *napi, int budget)
         struct be_adapter *adapter = eqo->adapter;
         int max_work = 0, work, i, num_evts;
         struct be_rx_obj *rxo;
-        bool tx_done;
+        struct be_tx_obj *txo;
 
         num_evts = events_get(eqo);
 
-        /* Process all TXQs serviced by this EQ */
-        for (i = eqo->idx; i < adapter->num_tx_qs; i += adapter->num_evt_qs) {
-                tx_done = be_process_tx(adapter, &adapter->tx_obj[i],
-                                        eqo->tx_budget, i);
-                if (!tx_done)
-                        max_work = budget;
-        }
+        for_all_tx_queues_on_eq(adapter, eqo, txo, i)
+                be_process_tx(adapter, txo, i);
 
         if (be_lock_napi(eqo)) {
                 /* This loop will iterate twice for EQ0 in which
@@ -3309,10 +3324,20 @@ static void BEx_get_resources(struct be_adapter *adapter,
          */
         if (BE2_chip(adapter) || use_sriov ||  (adapter->port_num > 1) ||
             !be_physfn(adapter) || (be_is_mc(adapter) &&
-            !(adapter->function_caps & BE_FUNCTION_CAPS_RSS)))
+            !(adapter->function_caps & BE_FUNCTION_CAPS_RSS))) {
                 res->max_tx_qs = 1;
-        else
+        } else if (adapter->function_caps & BE_FUNCTION_CAPS_SUPER_NIC) {
+                struct be_resources super_nic_res = {0};
+
+                /* On a SuperNIC profile, the driver needs to use the
+                 * GET_PROFILE_CONFIG cmd to query the per-function TXQ limits
+                 */
+                be_cmd_get_profile_config(adapter, &super_nic_res, 0);
+                /* Some old versions of BE3 FW don't report max_tx_qs value */
+                res->max_tx_qs = super_nic_res.max_tx_qs ? : BE3_MAX_TX_QS;
+        } else {
                 res->max_tx_qs = BE3_MAX_TX_QS;
+        }
 
         if ((adapter->function_caps & BE_FUNCTION_CAPS_RSS) &&
             !use_sriov && be_physfn(adapter))
@@ -3413,16 +3438,16 @@ static int be_get_resources(struct be_adapter *adapter)
                 if (be_roce_supported(adapter))
                         res.max_evt_qs /= 2;
                 adapter->res = res;
-
-                dev_info(dev, "Max: txqs %d, rxqs %d, rss %d, eqs %d, vfs %d\n",
-                         be_max_txqs(adapter), be_max_rxqs(adapter),
-                         be_max_rss(adapter), be_max_eqs(adapter),
-                         be_max_vfs(adapter));
-                dev_info(dev, "Max: uc-macs %d, mc-macs %d, vlans %d\n",
-                         be_max_uc(adapter), be_max_mc(adapter),
-                         be_max_vlans(adapter));
         }
 
+        dev_info(dev, "Max: txqs %d, rxqs %d, rss %d, eqs %d, vfs %d\n",
+                 be_max_txqs(adapter), be_max_rxqs(adapter),
+                 be_max_rss(adapter), be_max_eqs(adapter),
+                 be_max_vfs(adapter));
+        dev_info(dev, "Max: uc-macs %d, mc-macs %d, vlans %d\n",
+                 be_max_uc(adapter), be_max_mc(adapter),
+                 be_max_vlans(adapter));
+
         return 0;
 }
 
@@ -3633,6 +3658,7 @@ static int be_setup(struct be_adapter *adapter)
                 goto err;
 
         be_cmd_get_fw_ver(adapter);
+        dev_info(dev, "FW version is %s\n", adapter->fw_ver);
 
         if (BE2_chip(adapter) && fw_major_num(adapter->fw_ver) < 4) {
                 dev_err(dev, "Firmware on card is old(%s), IRQs may not work.",
@@ -4052,6 +4078,7 @@ static int lancer_fw_download(struct be_adapter *adapter,
 {
 #define LANCER_FW_DOWNLOAD_CHUNK      (32 * 1024)
 #define LANCER_FW_DOWNLOAD_LOCATION   "/prg"
+        struct device *dev = &adapter->pdev->dev;
         struct be_dma_mem flash_cmd;
         const u8 *data_ptr = NULL;
         u8 *dest_image_ptr = NULL;
@@ -4064,21 +4091,16 @@ static int lancer_fw_download(struct be_adapter *adapter,
         u8 change_status;
 
         if (!IS_ALIGNED(fw->size, sizeof(u32))) {
-                dev_err(&adapter->pdev->dev,
-                        "FW Image not properly aligned. "
-                        "Length must be 4 byte aligned.\n");
-                status = -EINVAL;
-                goto lancer_fw_exit;
+                dev_err(dev, "FW image size should be multiple of 4\n");
+                return -EINVAL;
         }
 
         flash_cmd.size = sizeof(struct lancer_cmd_req_write_object)
                                 + LANCER_FW_DOWNLOAD_CHUNK;
-        flash_cmd.va = dma_alloc_coherent(&adapter->pdev->dev, flash_cmd.size,
+        flash_cmd.va = dma_alloc_coherent(dev, flash_cmd.size,
                                           &flash_cmd.dma, GFP_KERNEL);
-        if (!flash_cmd.va) {
-                status = -ENOMEM;
-                goto lancer_fw_exit;
-        }
+        if (!flash_cmd.va)
+                return -ENOMEM;
 
         dest_image_ptr = flash_cmd.va +
                                 sizeof(struct lancer_cmd_req_write_object);
@@ -4113,35 +4135,27 @@ static int lancer_fw_download(struct be_adapter *adapter,
                                                  &add_status);
         }
 
-        dma_free_coherent(&adapter->pdev->dev, flash_cmd.size, flash_cmd.va,
-                          flash_cmd.dma);
+        dma_free_coherent(dev, flash_cmd.size, flash_cmd.va, flash_cmd.dma);
         if (status) {
-                dev_err(&adapter->pdev->dev,
-                        "Firmware load error. "
-                        "Status code: 0x%x Additional Status: 0x%x\n",
-                        status, add_status);
-                goto lancer_fw_exit;
+                dev_err(dev, "Firmware load error\n");
+                return be_cmd_status(status);
         }
 
+        dev_info(dev, "Firmware flashed successfully\n");
+
         if (change_status == LANCER_FW_RESET_NEEDED) {
-                dev_info(&adapter->pdev->dev,
-                         "Resetting adapter to activate new FW\n");
+                dev_info(dev, "Resetting adapter to activate new FW\n");
                 status = lancer_physdev_ctrl(adapter,
                                              PHYSDEV_CONTROL_FW_RESET_MASK);
                 if (status) {
-                        dev_err(&adapter->pdev->dev,
-                                "Adapter busy for FW reset.\n"
-                                "New FW will not be active.\n");
-                        goto lancer_fw_exit;
+                        dev_err(dev, "Adapter busy, could not reset FW\n");
+                        dev_err(dev, "Reboot server to activate new FW\n");
                 }
         } else if (change_status != LANCER_NO_RESET_NEEDED) {
-                dev_err(&adapter->pdev->dev,
-                        "System reboot required for new FW to be active\n");
+                dev_info(dev, "Reboot server to activate new FW\n");
         }
 
-        dev_info(&adapter->pdev->dev, "Firmware flashed successfully\n");
-lancer_fw_exit:
-        return status;
+        return 0;
 }
 
 #define UFI_TYPE2               2
@@ -4506,6 +4520,7 @@ static int be_map_pci_bars(struct be_adapter *adapter)
         return 0;
 
 pci_map_err:
+        dev_err(&adapter->pdev->dev, "Error in mapping PCI BARs\n");
         be_unmap_pci_bars(adapter);
         return -ENOMEM;
 }
@@ -4822,6 +4837,8 @@ static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id)
         struct net_device *netdev;
         char port_name;
 
+        dev_info(&pdev->dev, "%s version is %s\n", DRV_NAME, DRV_VER);
+
         status = pci_enable_device(pdev);
         if (status)
                 goto do_none;
diff --git a/drivers/net/ethernet/intel/e1000/e1000_ethtool.c b/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
index cca5bca44e73..9b50272824a1 100644
--- a/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
+++ b/drivers/net/ethernet/intel/e1000/e1000_ethtool.c
@@ -1,35 +1,30 @@
 /*******************************************************************************
-
-  Intel PRO/1000 Linux driver
-  Copyright(c) 1999 - 2006 Intel Corporation.
-
-  This program is free software; you can redistribute it and/or modify it
-  under the terms and conditions of the GNU General Public License,
-  version 2, as published by the Free Software Foundation.
-
-  This program is distributed in the hope it will be useful, but WITHOUT
-  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
-  more details.
-
-  You should have received a copy of the GNU General Public License along with
-  this program; if not, write to the Free Software Foundation, Inc.,
-  51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
-
-  The full GNU General Public License is included in this distribution in
-  the file called "COPYING".
-
-  Contact Information:
-  Linux NICS <linux.nics@intel.com>
-  e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
-  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
-
-*******************************************************************************/
+ * Intel PRO/1000 Linux driver
+ * Copyright(c) 1999 - 2006 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * The full GNU General Public License is included in this distribution in
+ * the file called "COPYING".
+ *
+ * Contact Information:
+ * Linux NICS <linux.nics@intel.com>
+ * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
+ * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
+ *
+ ******************************************************************************/
 
 /* ethtool support for e1000 */
 
 #include "e1000.h"
-#include <asm/uaccess.h>
+#include <linux/uaccess.h>
 
 enum {NETDEV_STATS, E1000_STATS};
 
@@ -42,7 +37,7 @@ struct e1000_stats {
 
 #define E1000_STAT(m)           E1000_STATS, \
                                 sizeof(((struct e1000_adapter *)0)->m), \
-                                offsetof(struct e1000_adapter, m)
+                                offsetof(struct e1000_adapter, m)
 #define E1000_NETDEV_STAT(m)    NETDEV_STATS, \
                                 sizeof(((struct net_device *)0)->m), \
                                 offsetof(struct net_device, m)
@@ -104,6 +99,7 @@ static const char e1000_gstrings_test[][ETH_GSTRING_LEN] = {
         "Interrupt test (offline)", "Loopback test  (offline)",
         "Link test   (on/offline)"
 };
+
 #define E1000_TEST_LEN  ARRAY_SIZE(e1000_gstrings_test)
 
 static int e1000_get_settings(struct net_device *netdev,
@@ -113,7 +109,6 @@ static int e1000_get_settings(struct net_device *netdev,
         struct e1000_hw *hw = &adapter->hw;
 
         if (hw->media_type == e1000_media_type_copper) {
-
                 ecmd->supported = (SUPPORTED_10baseT_Half |
                                    SUPPORTED_10baseT_Full |
                                    SUPPORTED_100baseT_Half |
@@ -155,9 +150,8 @@ static int e1000_get_settings(struct net_device *netdev,
         }
 
         if (er32(STATUS) & E1000_STATUS_LU) {
-
                 e1000_get_speed_and_duplex(hw, &adapter->link_speed,
-                                                   &adapter->link_duplex);
+                                           &adapter->link_duplex);
                 ethtool_cmd_speed_set(ecmd, adapter->link_speed);
 
                 /* unfortunately FULL_DUPLEX != DUPLEX_FULL
@@ -247,9 +241,9 @@ static int e1000_set_settings(struct net_device *netdev,
         if (netif_running(adapter->netdev)) {
                 e1000_down(adapter);
                 e1000_up(adapter);
-        } else
+        } else {
                 e1000_reset(adapter);
-
+        }
         clear_bit(__E1000_RESETTING, &adapter->flags);
         return 0;
 }
@@ -279,11 +273,11 @@ static void e1000_get_pauseparam(struct net_device *netdev,
         pause->autoneg =
                 (adapter->fc_autoneg ? AUTONEG_ENABLE : AUTONEG_DISABLE);
 
-        if (hw->fc == E1000_FC_RX_PAUSE)
+        if (hw->fc == E1000_FC_RX_PAUSE) {
                 pause->rx_pause = 1;
-        else if (hw->fc == E1000_FC_TX_PAUSE)
+        } else if (hw->fc == E1000_FC_TX_PAUSE) {
                 pause->tx_pause = 1;
-        else if (hw->fc == E1000_FC_FULL) {
+        } else if (hw->fc == E1000_FC_FULL) {
                 pause->rx_pause = 1;
                 pause->tx_pause = 1;
         }
@@ -316,8 +310,9 @@ static int e1000_set_pauseparam(struct net_device *netdev,
                 if (netif_running(adapter->netdev)) {
                         e1000_down(adapter);
                         e1000_up(adapter);
-                } else
+                } else {
                         e1000_reset(adapter);
+                }
         } else
                 retval = ((hw->media_type == e1000_media_type_fiber) ?
                           e1000_setup_link(hw) : e1000_force_mac_fc(hw));
@@ -329,12 +324,14 @@ static int e1000_set_pauseparam(struct net_device *netdev,
 static u32 e1000_get_msglevel(struct net_device *netdev)
 {
         struct e1000_adapter *adapter = netdev_priv(netdev);
+
         return adapter->msg_enable;
 }
 
 static void e1000_set_msglevel(struct net_device *netdev, u32 data)
 {
         struct e1000_adapter *adapter = netdev_priv(netdev);
+
         adapter->msg_enable = data;
 }
 
@@ -526,7 +523,7 @@ static int e1000_set_eeprom(struct net_device *netdev,
                  * only the first byte of the word is being modified
                  */
                 ret_val = e1000_read_eeprom(hw, last_word, 1,
-                                  &eeprom_buff[last_word - first_word]);
+                                            &eeprom_buff[last_word - first_word]);
         }
 
         /* Device's eeprom is always little-endian, word addressable */
@@ -618,13 +615,12 @@ static int e1000_set_ringparam(struct net_device *netdev,
         adapter->tx_ring = txdr;
         adapter->rx_ring = rxdr;
 
-        rxdr->count = max(ring->rx_pending,(u32)E1000_MIN_RXD);
-        rxdr->count = min(rxdr->count,(u32)(mac_type < e1000_82544 ?
+        rxdr->count = max(ring->rx_pending, (u32)E1000_MIN_RXD);
+        rxdr->count = min(rxdr->count, (u32)(mac_type < e1000_82544 ?
                           E1000_MAX_RXD : E1000_MAX_82544_RXD));
         rxdr->count = ALIGN(rxdr->count, REQ_RX_DESCRIPTOR_MULTIPLE);
-
-        txdr->count = max(ring->tx_pending,(u32)E1000_MIN_TXD);
-        txdr->count = min(txdr->count,(u32)(mac_type < e1000_82544 ?
+        txdr->count = max(ring->tx_pending, (u32)E1000_MIN_TXD);
+        txdr->count = min(txdr->count, (u32)(mac_type < e1000_82544 ?
                           E1000_MAX_TXD : E1000_MAX_82544_TXD));
         txdr->count = ALIGN(txdr->count, REQ_TX_DESCRIPTOR_MULTIPLE);
 
@@ -680,8 +676,9 @@ static bool reg_pattern_test(struct e1000_adapter *adapter, u64 *data, int reg,
                              u32 mask, u32 write)
 {
         struct e1000_hw *hw = &adapter->hw;
-        static const u32 test[] =
-                {0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF};
+        static const u32 test[] = {
+                0x5A5A5A5A, 0xA5A5A5A5, 0x00000000, 0xFFFFFFFF
+        };
         u8 __iomem *address = hw->hw_addr + reg;
         u32 read;
         int i;
@@ -793,8 +790,8 @@ static int e1000_reg_test(struct e1000_adapter *adapter, u64 *data)
                 REG_PATTERN_TEST(TIDV, 0x0000FFFF, 0x0000FFFF);
                 value = E1000_RAR_ENTRIES;
                 for (i = 0; i < value; i++) {
-                        REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2), 0x8003FFFF,
-                                         0xFFFFFFFF);
+                        REG_PATTERN_TEST(RA + (((i << 1) + 1) << 2),
+                                         0x8003FFFF, 0xFFFFFFFF);
                 }
         } else {
                 REG_SET_AND_CHECK(RCTL, 0xFFFFFFFF, 0x01FFFFFF);
@@ -877,7 +874,6 @@ static int e1000_intr_test(struct e1000_adapter *adapter, u64 *data)
 
         /* Test each interrupt */
         for (; i < 10; i++) {
-
                 /* Interrupt to test */
                 mask = 1 << i;
 
@@ -1149,8 +1145,7 @@ static void e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter)
          */
         e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
         phy_reg |= M88E1000_EPSCR_TX_CLK_25;
-        e1000_write_phy_reg(hw,
-                M88E1000_EXT_PHY_SPEC_CTRL, phy_reg);
+        e1000_write_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, phy_reg);
 
         /* In addition, because of the s/w reset above, we need to enable
          * CRS on TX.  This must be set for both full and half duplex
@@ -1158,8 +1153,7 @@ static void e1000_phy_reset_clk_and_crs(struct e1000_adapter *adapter)
          */
         e1000_read_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, &phy_reg);
         phy_reg |= M88E1000_PSCR_ASSERT_CRS_ON_TX;
-        e1000_write_phy_reg(hw,
-                M88E1000_PHY_SPEC_CTRL, phy_reg);
+        e1000_write_phy_reg(hw, M88E1000_PHY_SPEC_CTRL, phy_reg);
 }
 
 static int e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
@@ -1216,7 +1210,7 @@ static int e1000_nonintegrated_phy_loopback(struct e1000_adapter *adapter)
         /* Check Phy Configuration */
         e1000_read_phy_reg(hw, PHY_CTRL, &phy_reg);
         if (phy_reg != 0x4100)
-                 return 9;
+                return 9;
 
         e1000_read_phy_reg(hw, M88E1000_EXT_PHY_SPEC_CTRL, &phy_reg);
         if (phy_reg != 0x0070)
@@ -1261,7 +1255,7 @@ static int e1000_integrated_phy_loopback(struct e1000_adapter *adapter)
                         E1000_CTRL_FD); /* Force Duplex to FULL */
 
         if (hw->media_type == e1000_media_type_copper &&
-           hw->phy_type == e1000_phy_m88)
+            hw->phy_type == e1000_phy_m88)
                 ctrl_reg |= E1000_CTRL_ILOS; /* Invert Loss of Signal */
         else {
                 /* Set the ILOS bit on the fiber Nic is half
@@ -1299,7 +1293,7 @@ static int e1000_set_phy_loopback(struct e1000_adapter *adapter)
                          * attempt this 10 times.
                          */
                         while (e1000_nonintegrated_phy_loopback(adapter) &&
-                              count++ < 10);
+                               count++ < 10);
                         if (count < 11)
                                 return 0;
                 }
@@ -1348,8 +1342,9 @@ static int e1000_setup_loopback_test(struct e1000_adapter *adapter)
                         ew32(RCTL, rctl);
                         return 0;
                 }
-        } else if (hw->media_type == e1000_media_type_copper)
+        } else if (hw->media_type == e1000_media_type_copper) {
                 return e1000_set_phy_loopback(adapter);
+        }
 
         return 7;
 }
@@ -1395,9 +1390,9 @@ static int e1000_check_lbtest_frame(struct sk_buff *skb,
                                     unsigned int frame_size)
 {
         frame_size &= ~1;
-        if (*(skb->data + 3) == 0xFF) {
-                if ((*(skb->data + frame_size / 2 + 10) == 0xBE) &&
-                   (*(skb->data + frame_size / 2 + 12) == 0xAF)) {
+        if (skb->data[3] == 0xFF) {
+                if (skb->data[frame_size / 2 + 10] == 0xBE &&
+                    skb->data[frame_size / 2 + 12] == 0xAF) {
                         return 0;
                 }
         }
@@ -1410,7 +1405,7 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
         struct e1000_tx_ring *txdr = &adapter->test_tx_ring;
         struct e1000_rx_ring *rxdr = &adapter->test_rx_ring;
         struct pci_dev *pdev = adapter->pdev;
-        int i, j, k, l, lc, good_cnt, ret_val=0;
+        int i, j, k, l, lc, good_cnt, ret_val = 0;
         unsigned long time;
 
         ew32(RDT, rxdr->count - 1);
@@ -1429,12 +1424,13 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
         for (j = 0; j <= lc; j++) { /* loop count loop */
                 for (i = 0; i < 64; i++) { /* send the packets */
                         e1000_create_lbtest_frame(txdr->buffer_info[i].skb,
-                                        1024);
+                                                  1024);
                         dma_sync_single_for_device(&pdev->dev,
                                                    txdr->buffer_info[k].dma,
                                                    txdr->buffer_info[k].length,
                                                    DMA_TO_DEVICE);
-                        if (unlikely(++k == txdr->count)) k = 0;
+                        if (unlikely(++k == txdr->count))
+                                k = 0;
                 }
                 ew32(TDT, k);
                 E1000_WRITE_FLUSH();
@@ -1452,7 +1448,8 @@ static int e1000_run_loopback_test(struct e1000_adapter *adapter)
                                         1024);
                         if (!ret_val)
                                 good_cnt++;
-                        if (unlikely(++l == rxdr->count)) l = 0;
+                        if (unlikely(++l == rxdr->count))
+                                l = 0;
                         /* time + 20 msecs (200 msecs on 2.4) is more than
                          * enough time to complete the receives, if it's
                          * exceeded, break and error off
@@ -1494,6 +1491,7 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
         *data = 0;
         if (hw->media_type == e1000_media_type_internal_serdes) {
                 int i = 0;
+
                 hw->serdes_has_link = false;
 
                 /* On some blade server designs, link establishment
@@ -1512,9 +1510,8 @@ static int e1000_link_test(struct e1000_adapter *adapter, u64 *data)
                 if (hw->autoneg)  /* if auto_neg is set wait for it */
                         msleep(4000);
 
-                if (!(er32(STATUS) & E1000_STATUS_LU)) {
+                if (!(er32(STATUS) & E1000_STATUS_LU))
                         *data = 1;
-                }
         }
         return *data;
 }
@@ -1665,8 +1662,7 @@ static void e1000_get_wol(struct net_device *netdev,
         struct e1000_adapter *adapter = netdev_priv(netdev);
         struct e1000_hw *hw = &adapter->hw;
 
-        wol->supported = WAKE_UCAST | WAKE_MCAST |
-                         WAKE_BCAST | WAKE_MAGIC;
+        wol->supported = WAKE_UCAST | WAKE_MCAST | WAKE_BCAST | WAKE_MAGIC;
         wol->wolopts = 0;
 
         /* this function will set ->supported = 0 and return 1 if wol is not
@@ -1819,6 +1815,7 @@ static int e1000_set_coalesce(struct net_device *netdev,
 static int e1000_nway_reset(struct net_device *netdev)
 {
         struct e1000_adapter *adapter = netdev_priv(netdev);
+
         if (netif_running(netdev))
                 e1000_reinit_locked(adapter);
         return 0;
@@ -1830,22 +1827,29 @@ static void e1000_get_ethtool_stats(struct net_device *netdev,
         struct e1000_adapter *adapter = netdev_priv(netdev);
         int i;
         char *p = NULL;
+        const struct e1000_stats *stat = e1000_gstrings_stats;
 
         e1000_update_stats(adapter);
         for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
-                switch (e1000_gstrings_stats[i].type) {
+                switch (stat->type) {
                 case NETDEV_STATS:
-                        p = (char *) netdev +
-                                        e1000_gstrings_stats[i].stat_offset;
+                        p = (char *)netdev + stat->stat_offset;
                         break;
                 case E1000_STATS:
-                        p = (char *) adapter +
-                                        e1000_gstrings_stats[i].stat_offset;
+                        p = (char *)adapter + stat->stat_offset;
+                        break;
+                default:
+                        WARN_ONCE(1, "Invalid E1000 stat type: %u index %d\n",
+                                  stat->type, i);
                         break;
                 }
 
-                data[i] = (e1000_gstrings_stats[i].sizeof_stat ==
-                        sizeof(u64)) ? *(u64 *)p : *(u32 *)p;
+                if (stat->sizeof_stat == sizeof(u64))
+                        data[i] = *(u64 *)p;
+                else
+                        data[i] = *(u32 *)p;
+
+                stat++;
         }
 /* BUG_ON(i != E1000_STATS_LEN); */
 }
@@ -1858,8 +1862,7 @@ static void e1000_get_strings(struct net_device *netdev, u32 stringset,
 
         switch (stringset) {
         case ETH_SS_TEST:
-                memcpy(data, *e1000_gstrings_test,
-                        sizeof(e1000_gstrings_test));
+                memcpy(data, e1000_gstrings_test, sizeof(e1000_gstrings_test));
                 break;
         case ETH_SS_STATS:
                 for (i = 0; i < E1000_GLOBAL_STATS_LEN; i++) {
diff --git a/drivers/net/ethernet/intel/i40e/i40e.h b/drivers/net/ethernet/intel/i40e/i40e.h
index 801da392a20e..f1e33f896439 100644
--- a/drivers/net/ethernet/intel/i40e/i40e.h
+++ b/drivers/net/ethernet/intel/i40e/i40e.h
@@ -144,6 +144,8 @@ enum i40e_state_t {
         __I40E_PTP_TX_IN_PROGRESS,
         __I40E_BAD_EEPROM,
         __I40E_DOWN_REQUESTED,
+        __I40E_FD_FLUSH_REQUESTED,
+        __I40E_RESET_FAILED,
 };
 
 enum i40e_interrupt_policy {
@@ -250,6 +252,11 @@ struct i40e_pf {
         u16 fdir_pf_active_filters;
         u16 fd_sb_cnt_idx;
         u16 fd_atr_cnt_idx;
+        unsigned long fd_flush_timestamp;
+        u32 fd_flush_cnt;
+        u32 fd_add_err;
+        u32 fd_atr_cnt;
+        u32 fd_tcp_rule;
 
 #ifdef CONFIG_I40E_VXLAN
         __be16  vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
@@ -310,6 +317,7 @@ struct i40e_pf {
         u32 tx_timeout_count;
         u32 tx_timeout_recovery_level;
         unsigned long tx_timeout_last_recovery;
+        u32 tx_sluggish_count;
         u32 hw_csum_rx_error;
         u32 led_status;
         u16 corer_count; /* Core reset count */
@@ -608,6 +616,7 @@ int i40e_add_del_fdir(struct i40e_vsi *vsi,
 void i40e_fdir_check_and_reenable(struct i40e_pf *pf);
 int i40e_get_current_fd_count(struct i40e_pf *pf);
 int i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf);
+int i40e_get_current_atr_cnt(struct i40e_pf *pf);
 bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features);
 void i40e_set_ethtool_ops(struct net_device *netdev);
 struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
diff --git a/drivers/net/ethernet/intel/i40e/i40e_adminq.c b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
index b29c157b1f57..72f5d25a222f 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_adminq.c
@@ -840,7 +840,8 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
 
         /* bump the tail */
         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
-        i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
+        i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
+                      buff, buff_size);
         (hw->aq.asq.next_to_use)++;
         if (hw->aq.asq.next_to_use == hw->aq.asq.count)
                 hw->aq.asq.next_to_use = 0;
@@ -891,7 +892,7 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
 
         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
                    "AQTX: desc and buffer writeback:\n");
-        i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff);
+        i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff, buff_size);
 
         /* update the error if time out occurred */
         if ((!cmd_completed) &&
@@ -987,7 +988,8 @@ i40e_status i40e_clean_arq_element(struct i40e_hw *hw,
                        e->msg_size);
 
         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
-        i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf);
+        i40e_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
+                      hw->aq.arq_buf_size);
 
         /* Restore the original datalen and buffer address in the desc,
          * FW updates datalen to indicate the event message
diff --git a/drivers/net/ethernet/intel/i40e/i40e_common.c b/drivers/net/ethernet/intel/i40e/i40e_common.c
index df43e7c6777c..30056b25d94e 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_common.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_common.c
@@ -75,13 +75,15 @@ static i40e_status i40e_set_mac_type(struct i40e_hw *hw)
  * @mask: debug mask
  * @desc: pointer to admin queue descriptor
  * @buffer: pointer to command buffer
+ * @buf_len: max length of buffer
  *
  * Dumps debug log about adminq command with descriptor contents.
  **/
 void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
-                   void *buffer)
+                   void *buffer, u16 buf_len)
 {
         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
+        u16 len = le16_to_cpu(aq_desc->datalen);
         u8 *aq_buffer = (u8 *)buffer;
         u32 data[4];
         u32 i = 0;
@@ -105,7 +107,9 @@ void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
                 memset(data, 0, sizeof(data));
                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
-                for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
+                if (buf_len < len)
+                        len = buf_len;
+                for (i = 0; i < len; i++) {
                         data[((i % 16) / 4)] |=
                                 ((u32)aq_buffer[i]) << (8 * (i % 4));
                         if ((i % 16) == 15) {
@@ -748,6 +752,8 @@ static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
         switch (hw->phy.link_info.phy_type) {
         case I40E_PHY_TYPE_10GBASE_SR:
         case I40E_PHY_TYPE_10GBASE_LR:
+        case I40E_PHY_TYPE_1000BASE_SX:
+        case I40E_PHY_TYPE_1000BASE_LX:
         case I40E_PHY_TYPE_40GBASE_SR4:
         case I40E_PHY_TYPE_40GBASE_LR4:
                 media = I40E_MEDIA_TYPE_FIBER;
diff --git a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c
index 5a0cabeb35ed..7067f4b9159c 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_debugfs.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_debugfs.c
@@ -1356,6 +1356,9 @@ static ssize_t i40e_dbg_command_write(struct file *filp,
                                  "emp reset count: %d\n", pf->empr_count);
                         dev_info(&pf->pdev->dev,
                                  "pf reset count: %d\n", pf->pfr_count);
+                        dev_info(&pf->pdev->dev,
+                                 "pf tx sluggish count: %d\n",
+                                 pf->tx_sluggish_count);
                 } else if (strncmp(&cmd_buf[5], "port", 4) == 0) {
                         struct i40e_aqc_query_port_ets_config_resp *bw_data;
                         struct i40e_dcbx_config *cfg =
diff --git a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
index e8ba7470700a..1dda467ae1ac 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_ethtool.c
@@ -145,6 +145,7 @@ static struct i40e_stats i40e_gstrings_stats[] = {
         I40E_PF_STAT("rx_jabber", stats.rx_jabber),
         I40E_PF_STAT("VF_admin_queue_requests", vf_aq_requests),
         I40E_PF_STAT("rx_hwtstamp_cleared", rx_hwtstamp_cleared),
+        I40E_PF_STAT("fdir_flush_cnt", fd_flush_cnt),
         I40E_PF_STAT("fdir_atr_match", stats.fd_atr_match),
         I40E_PF_STAT("fdir_sb_match", stats.fd_sb_match),
 
@@ -312,7 +313,10 @@ static int i40e_get_settings(struct net_device *netdev,
                 break;
         case I40E_PHY_TYPE_10GBASE_SR:
         case I40E_PHY_TYPE_10GBASE_LR:
+        case I40E_PHY_TYPE_1000BASE_SX:
+        case I40E_PHY_TYPE_1000BASE_LX:
                 ecmd->supported = SUPPORTED_10000baseT_Full;
+                ecmd->supported |= SUPPORTED_1000baseT_Full;
                 break;
         case I40E_PHY_TYPE_10GBASE_CR1_CU:
         case I40E_PHY_TYPE_10GBASE_CR1:
@@ -351,7 +355,8 @@ static int i40e_get_settings(struct net_device *netdev,
                 break;
         default:
                 /* if we got here and link is up something bad is afoot */
-                WARN_ON(link_up);
+                netdev_info(netdev, "WARNING: Link is up but PHY type 0x%x is not recognized.\n",
+                            hw_link_info->phy_type);
         }
 
 no_valid_phy_type:
@@ -461,7 +466,8 @@ static int i40e_set_settings(struct net_device *netdev,
 
         if (hw->phy.media_type != I40E_MEDIA_TYPE_BASET &&
             hw->phy.media_type != I40E_MEDIA_TYPE_FIBER &&
-            hw->phy.media_type != I40E_MEDIA_TYPE_BACKPLANE)
+            hw->phy.media_type != I40E_MEDIA_TYPE_BACKPLANE &&
+            hw->phy.link_info.link_info & I40E_AQ_LINK_UP)
                 return -EOPNOTSUPP;
 
         /* get our own copy of the bits to check against */
@@ -492,11 +498,10 @@ static int i40e_set_settings(struct net_device *netdev,
         if (status)
                 return -EAGAIN;
 
-        /* Copy link_speed and abilities to config in case they are not
+        /* Copy abilities to config in case autoneg is not
          * set below
          */
         memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
-        config.link_speed = abilities.link_speed;
         config.abilities = abilities.abilities;
 
         /* Check autoneg */
@@ -533,42 +538,38 @@ static int i40e_set_settings(struct net_device *netdev,
                 return -EINVAL;
 
         if (advertise & ADVERTISED_100baseT_Full)
-                if (!(abilities.link_speed & I40E_LINK_SPEED_100MB)) {
-                        config.link_speed |= I40E_LINK_SPEED_100MB;
-                        change = true;
-                }
+                config.link_speed |= I40E_LINK_SPEED_100MB;
         if (advertise & ADVERTISED_1000baseT_Full ||
             advertise & ADVERTISED_1000baseKX_Full)
-                if (!(abilities.link_speed & I40E_LINK_SPEED_1GB)) {
-                        config.link_speed |= I40E_LINK_SPEED_1GB;
-                        change = true;
-                }
+                config.link_speed |= I40E_LINK_SPEED_1GB;
         if (advertise & ADVERTISED_10000baseT_Full ||
             advertise & ADVERTISED_10000baseKX4_Full ||
             advertise & ADVERTISED_10000baseKR_Full)
-                if (!(abilities.link_speed & I40E_LINK_SPEED_10GB)) {
-                        config.link_speed |= I40E_LINK_SPEED_10GB;
-                        change = true;
-                }
+                config.link_speed |= I40E_LINK_SPEED_10GB;
         if (advertise & ADVERTISED_40000baseKR4_Full ||
             advertise & ADVERTISED_40000baseCR4_Full ||
             advertise & ADVERTISED_40000baseSR4_Full ||
             advertise & ADVERTISED_40000baseLR4_Full)
-                if (!(abilities.link_speed & I40E_LINK_SPEED_40GB)) {
-                        config.link_speed |= I40E_LINK_SPEED_40GB;
-                        change = true;
-                }
+                config.link_speed |= I40E_LINK_SPEED_40GB;
 
-        if (change) {
+        if (change || (abilities.link_speed != config.link_speed)) {
                 /* copy over the rest of the abilities */
                 config.phy_type = abilities.phy_type;
                 config.eee_capability = abilities.eee_capability;
                 config.eeer = abilities.eeer_val;
                 config.low_power_ctrl = abilities.d3_lpan;
 
-                /* If link is up set link and an so changes take effect */
-                if (hw->phy.link_info.link_info & I40E_AQ_LINK_UP)
-                        config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+                /* set link and auto negotiation so changes take effect */
+                config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
+                /* If link is up put link down */
+                if (hw->phy.link_info.link_info & I40E_AQ_LINK_UP) {
+                        /* Tell the OS link is going down, the link will go
+                         * back up when fw says it is ready asynchronously
+                         */
+                        netdev_info(netdev, "PHY settings change requested, NIC Link is going down.\n");
+                        netif_carrier_off(netdev);
+                        netif_tx_stop_all_queues(netdev);
+                }
 
                 /* make the aq call */
                 status = i40e_aq_set_phy_config(hw, &config, NULL);
@@ -685,6 +686,13 @@ static int i40e_set_pauseparam(struct net_device *netdev,
         else
                  return -EINVAL;
 
+        /* Tell the OS link is going down, the link will go back up when fw
+         * says it is ready asynchronously
+         */
+        netdev_info(netdev, "Flow control settings change requested, NIC Link is going down.\n");
+        netif_carrier_off(netdev);
+        netif_tx_stop_all_queues(netdev);
+
         /* Set the fc mode and only restart an if link is up*/
         status = i40e_set_fc(hw, &aq_failures, link_up);
 
@@ -1977,6 +1985,13 @@ static int i40e_del_fdir_entry(struct i40e_vsi *vsi,
         struct i40e_pf *pf = vsi->back;
         int ret = 0;
 
+        if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) ||
+            test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state))
+                return -EBUSY;
+
+        if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
+                return -EBUSY;
+
         ret = i40e_update_ethtool_fdir_entry(vsi, NULL, fsp->location, cmd);
 
         i40e_fdir_check_and_reenable(pf);
@@ -2010,6 +2025,13 @@ static int i40e_add_fdir_ethtool(struct i40e_vsi *vsi,
         if (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)
                 return -ENOSPC;
 
+        if (test_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state) ||
+            test_bit(__I40E_RESET_INTR_RECEIVED, &pf->state))
+                return -EBUSY;
+
+        if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
+                return -EBUSY;
+
         fsp = (struct ethtool_rx_flow_spec *)&cmd->fs;
 
         if (fsp->location >= (pf->hw.func_caps.fd_filters_best_effort +
diff --git a/drivers/net/ethernet/intel/i40e/i40e_main.c b/drivers/net/ethernet/intel/i40e/i40e_main.c
index eddec6ba095b..ed5f1c15fb0f 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_main.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_main.c
@@ -37,9 +37,9 @@ static const char i40e_driver_string[] =
 
 #define DRV_KERN "-k"
 
-#define DRV_VERSION_MAJOR 0
-#define DRV_VERSION_MINOR 4
-#define DRV_VERSION_BUILD 21
+#define DRV_VERSION_MAJOR 1
+#define DRV_VERSION_MINOR 0
+#define DRV_VERSION_BUILD 11
 #define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
              __stringify(DRV_VERSION_MINOR) "." \
              __stringify(DRV_VERSION_BUILD)    DRV_KERN
@@ -1239,8 +1239,11 @@ struct i40e_mac_filter *i40e_put_mac_in_vlan(struct i40e_vsi *vsi, u8 *macaddr,
  * i40e_rm_default_mac_filter - Remove the default MAC filter set by NVM
  * @vsi: the PF Main VSI - inappropriate for any other VSI
  * @macaddr: the MAC address
+ *
+ * Some older firmware configurations set up a default promiscuous VLAN
+ * filter that needs to be removed.
  **/
-static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
+static int i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
 {
         struct i40e_aqc_remove_macvlan_element_data element;
         struct i40e_pf *pf = vsi->back;
@@ -1248,15 +1251,18 @@ static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
 
         /* Only appropriate for the PF main VSI */
         if (vsi->type != I40E_VSI_MAIN)
-                return;
+                return -EINVAL;
 
+        memset(&element, 0, sizeof(element));
         ether_addr_copy(element.mac_addr, macaddr);
         element.vlan_tag = 0;
         element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
         aq_ret = i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
         if (aq_ret)
-                dev_err(&pf->pdev->dev, "Could not remove default MAC-VLAN\n");
+                return -ENOENT;
+
+        return 0;
 }
 
 /**
@@ -1385,18 +1391,30 @@ static int i40e_set_mac(struct net_device *netdev, void *p)
 {
         struct i40e_netdev_priv *np = netdev_priv(netdev);
         struct i40e_vsi *vsi = np->vsi;
+        struct i40e_pf *pf = vsi->back;
+        struct i40e_hw *hw = &pf->hw;
         struct sockaddr *addr = p;
         struct i40e_mac_filter *f;
 
         if (!is_valid_ether_addr(addr->sa_data))
                 return -EADDRNOTAVAIL;
 
-        netdev_info(netdev, "set mac address=%pM\n", addr->sa_data);
+        if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
+                netdev_info(netdev, "already using mac address %pM\n",
+                            addr->sa_data);
+                return 0;
+        }
 
         if (test_bit(__I40E_DOWN, &vsi->back->state) ||
             test_bit(__I40E_RESET_RECOVERY_PENDING, &vsi->back->state))
                 return -EADDRNOTAVAIL;
 
+        if (ether_addr_equal(hw->mac.addr, addr->sa_data))
+                netdev_info(netdev, "returning to hw mac address %pM\n",
+                            hw->mac.addr);
+        else
+                netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
+
         if (vsi->type == I40E_VSI_MAIN) {
                 i40e_status ret;
                 ret = i40e_aq_mac_address_write(&vsi->back->hw,
@@ -1410,25 +1428,34 @@ static int i40e_set_mac(struct net_device *netdev, void *p)
                 }
         }
 
-        f = i40e_find_mac(vsi, addr->sa_data, false, true);
-        if (!f) {
-                /* In order to be sure to not drop any packets, add the
-                 * new address first then delete the old one.
-                 */
-                f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
-                                    false, false);
-                if (!f)
-                        return -ENOMEM;
+        if (ether_addr_equal(netdev->dev_addr, hw->mac.addr)) {
+                struct i40e_aqc_remove_macvlan_element_data element;
 
-                i40e_sync_vsi_filters(vsi);
+                memset(&element, 0, sizeof(element));
+                ether_addr_copy(element.mac_addr, netdev->dev_addr);
+                element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
+                i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
+        } else {
                 i40e_del_filter(vsi, netdev->dev_addr, I40E_VLAN_ANY,
                                 false, false);
-                i40e_sync_vsi_filters(vsi);
         }
 
-        f->is_laa = true;
-        if (!ether_addr_equal(netdev->dev_addr, addr->sa_data))
-                ether_addr_copy(netdev->dev_addr, addr->sa_data);
+        if (ether_addr_equal(addr->sa_data, hw->mac.addr)) {
+                struct i40e_aqc_add_macvlan_element_data element;
+
+                memset(&element, 0, sizeof(element));
+                ether_addr_copy(element.mac_addr, hw->mac.addr);
+                element.flags = cpu_to_le16(I40E_AQC_MACVLAN_ADD_PERFECT_MATCH);
+                i40e_aq_add_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
+        } else {
+                f = i40e_add_filter(vsi, addr->sa_data, I40E_VLAN_ANY,
+                                    false, false);
+                if (f)
+                        f->is_laa = true;
+        }
+
+        i40e_sync_vsi_filters(vsi);
+        ether_addr_copy(netdev->dev_addr, addr->sa_data);
 
         return 0;
 }
@@ -1796,9 +1823,8 @@ int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
                 kfree(add_list);
                 add_list = NULL;
 
-                if (add_happened && (!aq_ret)) {
-                        /* do nothing */;
-                } else if (add_happened && (aq_ret)) {
+                if (add_happened && aq_ret &&
+                    pf->hw.aq.asq_last_status != I40E_AQ_RC_EINVAL) {
                         dev_info(&pf->pdev->dev,
                                  "add filter failed, err %d, aq_err %d\n",
                                  aq_ret, pf->hw.aq.asq_last_status);
@@ -4480,11 +4506,26 @@ static int i40e_up_complete(struct i40e_vsi *vsi)
                 netif_carrier_on(vsi->netdev);
         } else if (vsi->netdev) {
                 i40e_print_link_message(vsi, false);
+                /* need to check for qualified module here*/
+                if ((pf->hw.phy.link_info.link_info &
+                        I40E_AQ_MEDIA_AVAILABLE) &&
+                    (!(pf->hw.phy.link_info.an_info &
+                        I40E_AQ_QUALIFIED_MODULE)))
+                        netdev_err(vsi->netdev,
+                                   "the driver failed to link because an unqualified module was detected.");
         }
 
         /* replay FDIR SB filters */
-        if (vsi->type == I40E_VSI_FDIR)
+        if (vsi->type == I40E_VSI_FDIR) {
+                /* reset fd counters */
+                pf->fd_add_err = pf->fd_atr_cnt = 0;
+                if (pf->fd_tcp_rule > 0) {
+                        pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
+                        dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 exist\n");
+                        pf->fd_tcp_rule = 0;
+                }
                 i40e_fdir_filter_restore(vsi);
+        }
         i40e_service_event_schedule(pf);
 
         return 0;
@@ -5125,6 +5166,7 @@ int i40e_get_current_fd_count(struct i40e_pf *pf)
                       I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
         return fcnt_prog;
 }
+
 /**
  * i40e_fdir_check_and_reenable - Function to reenabe FD ATR or SB if disabled
  * @pf: board private structure
@@ -5133,15 +5175,17 @@ void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
 {
         u32 fcnt_prog, fcnt_avail;
 
+        if (test_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state))
+                return;
+
         /* Check if, FD SB or ATR was auto disabled and if there is enough room
          * to re-enable
          */
-        if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
-            (pf->flags & I40E_FLAG_FD_SB_ENABLED))
-                return;
         fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
         fcnt_avail = pf->fdir_pf_filter_count;
-        if (fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) {
+        if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
+            (pf->fd_add_err == 0) ||
+            (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt)) {
                 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
                     (pf->auto_disable_flags & I40E_FLAG_FD_SB_ENABLED)) {
                         pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
@@ -5158,23 +5202,84 @@ void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
         }
 }
 
+#define I40E_MIN_FD_FLUSH_INTERVAL 10
+/**
+ * i40e_fdir_flush_and_replay - Function to flush all FD filters and replay SB
+ * @pf: board private structure
+ **/
+static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
+{
+        int flush_wait_retry = 50;
+        int reg;
+
+        if (time_after(jiffies, pf->fd_flush_timestamp +
+                                (I40E_MIN_FD_FLUSH_INTERVAL * HZ))) {
+                set_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
+                pf->fd_flush_timestamp = jiffies;
+                pf->auto_disable_flags |= I40E_FLAG_FD_SB_ENABLED;
+                pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
+                /* flush all filters */
+                wr32(&pf->hw, I40E_PFQF_CTL_1,
+                     I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
+                i40e_flush(&pf->hw);
+                pf->fd_flush_cnt++;
+                pf->fd_add_err = 0;
+                do {
+                        /* Check FD flush status every 5-6msec */
+                        usleep_range(5000, 6000);
+                        reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
+                        if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
+                                break;
+                } while (flush_wait_retry--);
+                if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
+                        dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
+                } else {
+                        /* replay sideband filters */
+                        i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
+
+                        pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
+                        pf->auto_disable_flags &= ~I40E_FLAG_FD_ATR_ENABLED;
+                        pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
+                        clear_bit(__I40E_FD_FLUSH_REQUESTED, &pf->state);
+                        dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
+                }
+        }
+}
+
+/**
+ * i40e_get_current_atr_count - Get the count of total FD ATR filters programmed
+ * @pf: board private structure
+ **/
+int i40e_get_current_atr_cnt(struct i40e_pf *pf)
+{
+        return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
+}
+
+/* We can see up to 256 filter programming desc in transit if the filters are
+ * being applied really fast; before we see the first
+ * filter miss error on Rx queue 0. Accumulating enough error messages before
+ * reacting will make sure we don't cause flush too often.
+ */
+#define I40E_MAX_FD_PROGRAM_ERROR 256
+
 /**
  * i40e_fdir_reinit_subtask - Worker thread to reinit FDIR filter table
  * @pf: board private structure
  **/
 static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
 {
-        if (!(pf->flags & I40E_FLAG_FDIR_REQUIRES_REINIT))
-                return;
 
         /* if interface is down do nothing */
         if (test_bit(__I40E_DOWN, &pf->state))
                 return;
+
+        if ((pf->fd_add_err >= I40E_MAX_FD_PROGRAM_ERROR) &&
+            (i40e_get_current_atr_cnt(pf) >= pf->fd_atr_cnt) &&
+            (i40e_get_current_atr_cnt(pf) > pf->fdir_pf_filter_count))
+                i40e_fdir_flush_and_replay(pf);
+
         i40e_fdir_check_and_reenable(pf);
 
-        if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
-            (pf->flags & I40E_FLAG_FD_SB_ENABLED))
-                pf->flags &= ~I40E_FLAG_FDIR_REQUIRES_REINIT;
 }
 
 /**
@@ -5184,7 +5289,7 @@ static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
  **/
 static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
 {
-        if (!vsi)
+        if (!vsi || test_bit(__I40E_DOWN, &vsi->state))
                 return;
 
         switch (vsi->type) {
@@ -5420,6 +5525,13 @@ static void i40e_handle_link_event(struct i40e_pf *pf,
         memcpy(&pf->hw.phy.link_info_old, hw_link_info,
                sizeof(pf->hw.phy.link_info_old));
 
+        /* check for unqualified module, if link is down */
+        if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
+            (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
+            (!(status->link_info & I40E_AQ_LINK_UP)))
+                dev_err(&pf->pdev->dev,
+                        "The driver failed to link because an unqualified module was detected.\n");
+
         /* update link status */
         hw_link_info->phy_type = (enum i40e_aq_phy_type)status->phy_type;
         hw_link_info->link_speed = (enum i40e_aq_link_speed)status->link_speed;
@@ -5456,6 +5568,10 @@ static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
         u32 oldval;
         u32 val;
 
+        /* Do not run clean AQ when PF reset fails */
+        if (test_bit(__I40E_RESET_FAILED, &pf->state))
+                return;
+
         /* check for error indications */
         val = rd32(&pf->hw, pf->hw.aq.arq.len);
         oldval = val;
@@ -5861,19 +5977,20 @@ static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
         ret = i40e_pf_reset(hw);
         if (ret) {
                 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
-                goto end_core_reset;
+                set_bit(__I40E_RESET_FAILED, &pf->state);
+                goto clear_recovery;
         }
         pf->pfr_count++;
 
         if (test_bit(__I40E_DOWN, &pf->state))
-                goto end_core_reset;
+                goto clear_recovery;
         dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
 
         /* rebuild the basics for the AdminQ, HMC, and initial HW switch */
         ret = i40e_init_adminq(&pf->hw);
         if (ret) {
                 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, %d\n", ret);
-                goto end_core_reset;
+                goto clear_recovery;
         }
 
         /* re-verify the eeprom if we just had an EMP reset */
@@ -5991,6 +6108,8 @@ static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit)
         i40e_send_version(pf);
 
 end_core_reset:
+        clear_bit(__I40E_RESET_FAILED, &pf->state);
+clear_recovery:
         clear_bit(__I40E_RESET_RECOVERY_PENDING, &pf->state);
 }
 
@@ -6036,9 +6155,9 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf)
                                 I40E_GL_MDET_TX_EVENT_SHIFT;
                 u8 queue = (reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
                                 I40E_GL_MDET_TX_QUEUE_SHIFT;
-                dev_info(&pf->pdev->dev,
-                         "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
-                         event, queue, pf_num, vf_num);
+                if (netif_msg_tx_err(pf))
+                        dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d pf number 0x%02x vf number 0x%02x\n",
+                                 event, queue, pf_num, vf_num);
                 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
                 mdd_detected = true;
         }
@@ -6050,9 +6169,9 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf)
                                 I40E_GL_MDET_RX_EVENT_SHIFT;
                 u8 queue = (reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
                                 I40E_GL_MDET_RX_QUEUE_SHIFT;
-                dev_info(&pf->pdev->dev,
-                         "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
-                         event, queue, func);
+                if (netif_msg_rx_err(pf))
+                        dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
+                                 event, queue, func);
                 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
                 mdd_detected = true;
         }
@@ -6061,17 +6180,13 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf)
                 reg = rd32(hw, I40E_PF_MDET_TX);
                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
                         wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
-                        dev_info(&pf->pdev->dev,
-                                 "MDD TX event is for this function 0x%08x, requesting PF reset.\n",
-                                 reg);
+                        dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
                         pf_mdd_detected = true;
                 }
                 reg = rd32(hw, I40E_PF_MDET_RX);
                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
                         wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
-                        dev_info(&pf->pdev->dev,
-                                 "MDD RX event is for this function 0x%08x, requesting PF reset.\n",
-                                 reg);
+                        dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
                         pf_mdd_detected = true;
                 }
                 /* Queue belongs to the PF, initiate a reset */
@@ -6088,14 +6203,16 @@ static void i40e_handle_mdd_event(struct i40e_pf *pf)
                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
                         wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
                         vf->num_mdd_events++;
-                        dev_info(&pf->pdev->dev, "MDD TX event on VF %d\n", i);
+                        dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
+                                 i);
                 }
 
                 reg = rd32(hw, I40E_VP_MDET_RX(i));
                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
                         wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
                         vf->num_mdd_events++;
-                        dev_info(&pf->pdev->dev, "MDD RX event on VF %d\n", i);
+                        dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
+                                 i);
                 }
 
                 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
@@ -7086,6 +7203,11 @@ bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
                 }
                 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
                 pf->auto_disable_flags &= ~I40E_FLAG_FD_SB_ENABLED;
+                /* reset fd counters */
+                pf->fd_add_err = pf->fd_atr_cnt = pf->fd_tcp_rule = 0;
+                pf->fdir_pf_active_filters = 0;
+                pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
+                dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
                 /* if ATR was auto disabled it can be re-enabled. */
                 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
                     (pf->auto_disable_flags & I40E_FLAG_FD_ATR_ENABLED))
@@ -7352,7 +7474,7 @@ static const struct net_device_ops i40e_netdev_ops = {
         .ndo_set_vf_rate        = i40e_ndo_set_vf_bw,
         .ndo_get_vf_config      = i40e_ndo_get_vf_config,
         .ndo_set_vf_link_state  = i40e_ndo_set_vf_link_state,
-        .ndo_set_vf_spoofchk    = i40e_ndo_set_vf_spoofck,
+        .ndo_set_vf_spoofchk    = i40e_ndo_set_vf_spoofchk,
 #ifdef CONFIG_I40E_VXLAN
         .ndo_add_vxlan_port     = i40e_add_vxlan_port,
         .ndo_del_vxlan_port     = i40e_del_vxlan_port,
@@ -7421,14 +7543,14 @@ static int i40e_config_netdev(struct i40e_vsi *vsi)
         if (vsi->type == I40E_VSI_MAIN) {
                 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
                 ether_addr_copy(mac_addr, hw->mac.perm_addr);
-                /* The following two steps are necessary to prevent reception
-                 * of tagged packets - by default the NVM loads a MAC-VLAN
-                 * filter that will accept any tagged packet.  This is to
-                 * prevent that during normal operations until a specific
-                 * VLAN tag filter has been set.
+                /* The following steps are necessary to prevent reception
+                 * of tagged packets - some older NVM configurations load a
+                 * default a MAC-VLAN filter that accepts any tagged packet
+                 * which must be replaced by a normal filter.
                  */
-                i40e_rm_default_mac_filter(vsi, mac_addr);
-                i40e_add_filter(vsi, mac_addr, I40E_VLAN_ANY, false, true);
+                if (!i40e_rm_default_mac_filter(vsi, mac_addr))
+                        i40e_add_filter(vsi, mac_addr,
+                                        I40E_VLAN_ANY, false, true);
         } else {
                 /* relate the VSI_VMDQ name to the VSI_MAIN name */
                 snprintf(netdev->name, IFNAMSIZ, "%sv%%d",
@@ -7644,7 +7766,22 @@ static int i40e_add_vsi(struct i40e_vsi *vsi)
                 f_count++;
 
                 if (f->is_laa && vsi->type == I40E_VSI_MAIN) {
-                        i40e_aq_mac_address_write(&vsi->back->hw,
+                        struct i40e_aqc_remove_macvlan_element_data element;
+
+                        memset(&element, 0, sizeof(element));
+                        ether_addr_copy(element.mac_addr, f->macaddr);
+                        element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
+                        ret = i40e_aq_remove_macvlan(hw, vsi->seid,
+                                                     &element, 1, NULL);
+                        if (ret) {
+                                /* some older FW has a different default */
+                                element.flags |=
+                                               I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
+                                i40e_aq_remove_macvlan(hw, vsi->seid,
+                                                       &element, 1, NULL);
+                        }
+
+                        i40e_aq_mac_address_write(hw,
                                                   I40E_AQC_WRITE_TYPE_LAA_WOL,
                                                   f->macaddr, NULL);
                 }
diff --git a/drivers/net/ethernet/intel/i40e/i40e_prototype.h b/drivers/net/ethernet/intel/i40e/i40e_prototype.h
index 949a9a01778b..0988b5c1fe87 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_prototype.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_prototype.h
@@ -52,10 +52,8 @@ i40e_status i40e_asq_send_command(struct i40e_hw *hw,
                                 struct i40e_asq_cmd_details *cmd_details);
 
 /* debug function for adminq */
-void i40e_debug_aq(struct i40e_hw *hw,
-                   enum i40e_debug_mask mask,
-                   void *desc,
-                   void *buffer);
+void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
+                   void *desc, void *buffer, u16 buf_len);
 
 void i40e_idle_aq(struct i40e_hw *hw);
 bool i40e_check_asq_alive(struct i40e_hw *hw);
diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.c b/drivers/net/ethernet/intel/i40e/i40e_txrx.c
index 369848e107f8..be039dd6114d 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.c
@@ -224,15 +224,19 @@ static int i40e_add_del_fdir_udpv4(struct i40e_vsi *vsi,
         ret = i40e_program_fdir_filter(fd_data, raw_packet, pf, add);
         if (ret) {
                 dev_info(&pf->pdev->dev,
-                         "Filter command send failed for PCTYPE %d (ret = %d)\n",
-                         fd_data->pctype, ret);
+                         "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
+                         fd_data->pctype, fd_data->fd_id, ret);
                 err = true;
         } else {
-                dev_info(&pf->pdev->dev,
-                         "Filter OK for PCTYPE %d (ret = %d)\n",
-                         fd_data->pctype, ret);
+                if (add)
+                        dev_info(&pf->pdev->dev,
+                                 "Filter OK for PCTYPE %d loc = %d\n",
+                                 fd_data->pctype, fd_data->fd_id);
+                else
+                        dev_info(&pf->pdev->dev,
+                                 "Filter deleted for PCTYPE %d loc = %d\n",
+                                 fd_data->pctype, fd_data->fd_id);
         }
-
         return err ? -EOPNOTSUPP : 0;
 }
 
@@ -276,10 +280,18 @@ static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
         tcp->source = fd_data->src_port;
 
         if (add) {
+                pf->fd_tcp_rule++;
                 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED) {
                         dev_info(&pf->pdev->dev, "Forcing ATR off, sideband rules for TCP/IPv4 flow being applied\n");
                         pf->flags &= ~I40E_FLAG_FD_ATR_ENABLED;
                 }
+        } else {
+                pf->fd_tcp_rule = (pf->fd_tcp_rule > 0) ?
+                                  (pf->fd_tcp_rule - 1) : 0;
+                if (pf->fd_tcp_rule == 0) {
+                        pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
+                        dev_info(&pf->pdev->dev, "ATR re-enabled due to no sideband TCP/IPv4 rules\n");
+                }
         }
 
         fd_data->pctype = I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
@@ -287,12 +299,17 @@ static int i40e_add_del_fdir_tcpv4(struct i40e_vsi *vsi,
 
         if (ret) {
                 dev_info(&pf->pdev->dev,
-                         "Filter command send failed for PCTYPE %d (ret = %d)\n",
-                         fd_data->pctype, ret);
+                         "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
+                         fd_data->pctype, fd_data->fd_id, ret);
                 err = true;
         } else {
-                dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d (ret = %d)\n",
-                         fd_data->pctype, ret);
+                if (add)
+                        dev_info(&pf->pdev->dev, "Filter OK for PCTYPE %d loc = %d)\n",
+                                 fd_data->pctype, fd_data->fd_id);
+                else
+                        dev_info(&pf->pdev->dev,
+                                 "Filter deleted for PCTYPE %d loc = %d\n",
+                                 fd_data->pctype, fd_data->fd_id);
         }
 
         return err ? -EOPNOTSUPP : 0;
@@ -355,13 +372,18 @@ static int i40e_add_del_fdir_ipv4(struct i40e_vsi *vsi,
 
                 if (ret) {
                         dev_info(&pf->pdev->dev,
-                                 "Filter command send failed for PCTYPE %d (ret = %d)\n",
-                                 fd_data->pctype, ret);
+                                 "PCTYPE:%d, Filter command send failed for fd_id:%d (ret = %d)\n",
+                                 fd_data->pctype, fd_data->fd_id, ret);
                         err = true;
                 } else {
-                        dev_info(&pf->pdev->dev,
-                                 "Filter OK for PCTYPE %d (ret = %d)\n",
-                                 fd_data->pctype, ret);
+                        if (add)
+                                dev_info(&pf->pdev->dev,
+                                         "Filter OK for PCTYPE %d loc = %d\n",
+                                         fd_data->pctype, fd_data->fd_id);
+                        else
+                                dev_info(&pf->pdev->dev,
+                                         "Filter deleted for PCTYPE %d loc = %d\n",
+                                         fd_data->pctype, fd_data->fd_id);
                 }
         }
 
@@ -443,8 +465,14 @@ static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 
         if (error == (0x1 << I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
-                dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
-                         rx_desc->wb.qword0.hi_dword.fd_id);
+                if ((rx_desc->wb.qword0.hi_dword.fd_id != 0) ||
+                    (I40E_DEBUG_FD & pf->hw.debug_mask))
+                        dev_warn(&pdev->dev, "ntuple filter loc = %d, could not be added\n",
+                                 rx_desc->wb.qword0.hi_dword.fd_id);
+
+                pf->fd_add_err++;
+                /* store the current atr filter count */
+                pf->fd_atr_cnt = i40e_get_current_atr_cnt(pf);
 
                 /* filter programming failed most likely due to table full */
                 fcnt_prog = i40e_get_cur_guaranteed_fd_count(pf);
@@ -454,29 +482,21 @@ static void i40e_fd_handle_status(struct i40e_ring *rx_ring,
                  * FD ATR/SB and then re-enable it when there is room.
                  */
                 if (fcnt_prog >= (fcnt_avail - I40E_FDIR_BUFFER_FULL_MARGIN)) {
-                        /* Turn off ATR first */
-                        if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
+                        if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
                             !(pf->auto_disable_flags &
-                              I40E_FLAG_FD_ATR_ENABLED)) {
-                                dev_warn(&pdev->dev, "FD filter space full, ATR for further flows will be turned off\n");
-                                pf->auto_disable_flags |=
-                                                       I40E_FLAG_FD_ATR_ENABLED;
-                                pf->flags |= I40E_FLAG_FDIR_REQUIRES_REINIT;
-                        } else if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
-                                   !(pf->auto_disable_flags &
                                      I40E_FLAG_FD_SB_ENABLED)) {
                                 dev_warn(&pdev->dev, "FD filter space full, new ntuple rules will not be added\n");
                                 pf->auto_disable_flags |=
                                                         I40E_FLAG_FD_SB_ENABLED;
-                                pf->flags |= I40E_FLAG_FDIR_REQUIRES_REINIT;
                         }
                 } else {
-                        dev_info(&pdev->dev, "FD filter programming error\n");
+                        dev_info(&pdev->dev,
+                                "FD filter programming failed due to incorrect filter parameters\n");
                 }
         } else if (error ==
                           (0x1 << I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
                 if (I40E_DEBUG_FD & pf->hw.debug_mask)
-                        dev_info(&pdev->dev, "ntuple filter loc = %d, could not be removed\n",
+                        dev_info(&pdev->dev, "ntuple filter fd_id = %d, could not be removed\n",
                                  rx_desc->wb.qword0.hi_dword.fd_id);
         }
 }
@@ -587,6 +607,7 @@ static u32 i40e_get_tx_pending(struct i40e_ring *ring)
 static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
 {
         u32 tx_pending = i40e_get_tx_pending(tx_ring);
+        struct i40e_pf *pf = tx_ring->vsi->back;
         bool ret = false;
 
         clear_check_for_tx_hang(tx_ring);
@@ -603,10 +624,17 @@ static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
          * pending but without time to complete it yet.
          */
         if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
-            tx_pending) {
+            (tx_pending >= I40E_MIN_DESC_PENDING)) {
                 /* make sure it is true for two checks in a row */
                 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
                                        &tx_ring->state);
+        } else if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
+                   (tx_pending < I40E_MIN_DESC_PENDING) &&
+                   (tx_pending > 0)) {
+                if (I40E_DEBUG_FLOW & pf->hw.debug_mask)
+                        dev_info(tx_ring->dev, "HW needs some more descs to do a cacheline flush. tx_pending %d, queue %d",
+                                 tx_pending, tx_ring->queue_index);
+                pf->tx_sluggish_count++;
         } else {
                 /* update completed stats and disarm the hang check */
                 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
@@ -1213,7 +1241,6 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
         ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
                       (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 
-        skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
         skb->ip_summed = CHECKSUM_NONE;
 
         /* Rx csum enabled and ip headers found? */
@@ -1287,6 +1314,7 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
         }
 
         skb->ip_summed = CHECKSUM_UNNECESSARY;
+        skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 
         return;
 
diff --git a/drivers/net/ethernet/intel/i40e/i40e_txrx.h b/drivers/net/ethernet/intel/i40e/i40e_txrx.h
index 73f4fa425697..d7a625a6a14f 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_txrx.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_txrx.h
@@ -121,6 +121,7 @@ enum i40e_dyn_idx_t {
 /* Tx Descriptors needed, worst case */
 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
+#define I40E_MIN_DESC_PENDING   4
 
 #define I40E_TX_FLAGS_CSUM              (u32)(1)
 #define I40E_TX_FLAGS_HW_VLAN           (u32)(1 << 1)
diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
index 3ac6a0d2f143..4eeed267e4b7 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.c
@@ -73,7 +73,7 @@ static inline bool i40e_vc_isvalid_queue_id(struct i40e_vf *vf, u8 vsi_id,
 {
         struct i40e_pf *pf = vf->pf;
 
-        return qid < pf->vsi[vsi_id]->num_queue_pairs;
+        return qid < pf->vsi[vsi_id]->alloc_queue_pairs;
 }
 
 /**
@@ -350,6 +350,7 @@ static int i40e_config_vsi_rx_queue(struct i40e_vf *vf, u16 vsi_idx,
         rx_ctx.lrxqthresh = 2;
         rx_ctx.crcstrip = 1;
         rx_ctx.prefena = 1;
+        rx_ctx.l2tsel = 1;
 
         /* clear the context in the HMC */
         ret = i40e_clear_lan_rx_queue_context(hw, pf_queue_id);
@@ -468,7 +469,7 @@ static void i40e_enable_vf_mappings(struct i40e_vf *vf)
         wr32(hw, I40E_VPLAN_MAPENA(vf->vf_id), reg);
 
         /* map PF queues to VF queues */
-        for (j = 0; j < pf->vsi[vf->lan_vsi_index]->num_queue_pairs; j++) {
+        for (j = 0; j < pf->vsi[vf->lan_vsi_index]->alloc_queue_pairs; j++) {
                 u16 qid = i40e_vc_get_pf_queue_id(vf, vf->lan_vsi_index, j);
                 reg = (qid & I40E_VPLAN_QTABLE_QINDEX_MASK);
                 wr32(hw, I40E_VPLAN_QTABLE(total_queue_pairs, vf->vf_id), reg);
@@ -477,7 +478,7 @@ static void i40e_enable_vf_mappings(struct i40e_vf *vf)
 
         /* map PF queues to VSI */
         for (j = 0; j < 7; j++) {
-                if (j * 2 >= pf->vsi[vf->lan_vsi_index]->num_queue_pairs) {
+                if (j * 2 >= pf->vsi[vf->lan_vsi_index]->alloc_queue_pairs) {
                         reg = 0x07FF07FF;       /* unused */
                 } else {
                         u16 qid = i40e_vc_get_pf_queue_id(vf, vf->lan_vsi_index,
@@ -584,7 +585,7 @@ static int i40e_alloc_vf_res(struct i40e_vf *vf)
         ret = i40e_alloc_vsi_res(vf, I40E_VSI_SRIOV);
         if (ret)
                 goto error_alloc;
-        total_queue_pairs += pf->vsi[vf->lan_vsi_index]->num_queue_pairs;
+        total_queue_pairs += pf->vsi[vf->lan_vsi_index]->alloc_queue_pairs;
         set_bit(I40E_VIRTCHNL_VF_CAP_PRIVILEGE, &vf->vf_caps);
 
         /* store the total qps number for the runtime
@@ -706,35 +707,6 @@ complete_reset:
         wr32(hw, I40E_VFGEN_RSTAT1(vf->vf_id), I40E_VFR_VFACTIVE);
         i40e_flush(hw);
 }
-
-/**
- * i40e_vfs_are_assigned
- * @pf: pointer to the pf structure
- *
- * Determine if any VFs are assigned to VMs
- **/
-static bool i40e_vfs_are_assigned(struct i40e_pf *pf)
-{
-        struct pci_dev *pdev = pf->pdev;
-        struct pci_dev *vfdev;
-
-        /* loop through all the VFs to see if we own any that are assigned */
-        vfdev = pci_get_device(PCI_VENDOR_ID_INTEL, I40E_DEV_ID_VF , NULL);
-        while (vfdev) {
-                /* if we don't own it we don't care */
-                if (vfdev->is_virtfn && pci_physfn(vfdev) == pdev) {
-                        /* if it is assigned we cannot release it */
-                        if (vfdev->dev_flags & PCI_DEV_FLAGS_ASSIGNED)
-                                return true;
-                }
-
-                vfdev = pci_get_device(PCI_VENDOR_ID_INTEL,
-                                       I40E_DEV_ID_VF,
-                                       vfdev);
-        }
-
-        return false;
-}
 #ifdef CONFIG_PCI_IOV
 
 /**
@@ -842,7 +814,7 @@ void i40e_free_vfs(struct i40e_pf *pf)
          * assigned. Setting the number of VFs to 0 through sysfs is caught
          * before this function ever gets called.
          */
-        if (!i40e_vfs_are_assigned(pf)) {
+        if (!pci_vfs_assigned(pf->pdev)) {
                 pci_disable_sriov(pf->pdev);
                 /* Acknowledge VFLR for all VFS. Without this, VFs will fail to
                  * work correctly when SR-IOV gets re-enabled.
@@ -979,7 +951,7 @@ int i40e_pci_sriov_configure(struct pci_dev *pdev, int num_vfs)
         if (num_vfs)
                 return i40e_pci_sriov_enable(pdev, num_vfs);
 
-        if (!i40e_vfs_are_assigned(pf)) {
+        if (!pci_vfs_assigned(pf->pdev)) {
                 i40e_free_vfs(pf);
         } else {
                 dev_warn(&pdev->dev, "Unable to free VFs because some are assigned to VMs.\n");
@@ -1123,7 +1095,7 @@ static int i40e_vc_get_vf_resources_msg(struct i40e_vf *vf)
                 vfres->vsi_res[i].vsi_id = vf->lan_vsi_index;
                 vfres->vsi_res[i].vsi_type = I40E_VSI_SRIOV;
                 vfres->vsi_res[i].num_queue_pairs =
-                    pf->vsi[vf->lan_vsi_index]->num_queue_pairs;
+                    pf->vsi[vf->lan_vsi_index]->alloc_queue_pairs;
                 memcpy(vfres->vsi_res[i].default_mac_addr,
                        vf->default_lan_addr.addr, ETH_ALEN);
                 i++;
@@ -1209,6 +1181,7 @@ static int i40e_vc_config_queues_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
         struct i40e_virtchnl_vsi_queue_config_info *qci =
             (struct i40e_virtchnl_vsi_queue_config_info *)msg;
         struct i40e_virtchnl_queue_pair_info *qpi;
+        struct i40e_pf *pf = vf->pf;
         u16 vsi_id, vsi_queue_id;
         i40e_status aq_ret = 0;
         int i;
@@ -1242,6 +1215,8 @@ static int i40e_vc_config_queues_msg(struct i40e_vf *vf, u8 *msg, u16 msglen)
                         goto error_param;
                 }
         }
+        /* set vsi num_queue_pairs in use to num configured by vf */
+        pf->vsi[vf->lan_vsi_index]->num_queue_pairs = qci->num_queue_pairs;
 
 error_param:
         /* send the response to the vf */
@@ -2094,7 +2069,6 @@ int i40e_ndo_set_vf_mac(struct net_device *netdev, int vf_id, u8 *mac)
         /* Force the VF driver stop so it has to reload with new MAC address */
         i40e_vc_disable_vf(pf, vf);
         dev_info(&pf->pdev->dev, "Reload the VF driver to make this change effective.\n");
-        ret = 0;
 
 error_param:
         return ret;
@@ -2419,7 +2393,7 @@ error_out:
  *
  * Enable or disable VF spoof checking
  **/
-int i40e_ndo_set_vf_spoofck(struct net_device *netdev, int vf_id, bool enable)
+int i40e_ndo_set_vf_spoofchk(struct net_device *netdev, int vf_id, bool enable)
 {
         struct i40e_netdev_priv *np = netdev_priv(netdev);
         struct i40e_vsi *vsi = np->vsi;
diff --git a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h
index 63e7e0d81ad2..0adc61e1052d 100644
--- a/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h
+++ b/drivers/net/ethernet/intel/i40e/i40e_virtchnl_pf.h
@@ -122,7 +122,7 @@ int i40e_ndo_set_vf_bw(struct net_device *netdev, int vf_id, int min_tx_rate,
 int i40e_ndo_get_vf_config(struct net_device *netdev,
                            int vf_id, struct ifla_vf_info *ivi);
 int i40e_ndo_set_vf_link_state(struct net_device *netdev, int vf_id, int link);
-int i40e_ndo_set_vf_spoofck(struct net_device *netdev, int vf_id, bool enable);
+int i40e_ndo_set_vf_spoofchk(struct net_device *netdev, int vf_id, bool enable);
 
 void i40e_vc_notify_link_state(struct i40e_pf *pf);
 void i40e_vc_notify_reset(struct i40e_pf *pf);
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
index 003006033614..f206be917842 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_adminq.c
@@ -788,7 +788,8 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
 
         /* bump the tail */
         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQTX: desc and buffer:\n");
-        i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring, buff);
+        i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc_on_ring,
+                        buff, buff_size);
         (hw->aq.asq.next_to_use)++;
         if (hw->aq.asq.next_to_use == hw->aq.asq.count)
                 hw->aq.asq.next_to_use = 0;
@@ -842,7 +843,8 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
 
         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE,
                    "AQTX: desc and buffer writeback:\n");
-        i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff);
+        i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, buff,
+                        buff_size);
 
         /* update the error if time out occurred */
         if ((!cmd_completed) &&
@@ -938,7 +940,8 @@ i40e_status i40evf_clean_arq_element(struct i40e_hw *hw,
                 hw->aq.nvm_busy = false;
 
         i40e_debug(hw, I40E_DEBUG_AQ_MESSAGE, "AQRX: desc and buffer:\n");
-        i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf);
+        i40evf_debug_aq(hw, I40E_DEBUG_AQ_COMMAND, (void *)desc, e->msg_buf,
+                        hw->aq.arq_buf_size);
 
         /* Restore the original datalen and buffer address in the desc,
          * FW updates datalen to indicate the event message
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_common.c b/drivers/net/ethernet/intel/i40evf/i40e_common.c
index 4ea90bf239bb..952560551964 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_common.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_common.c
@@ -75,13 +75,15 @@ i40e_status i40e_set_mac_type(struct i40e_hw *hw)
  * @mask: debug mask
  * @desc: pointer to admin queue descriptor
  * @buffer: pointer to command buffer
+ * @buf_len: max length of buffer
  *
  * Dumps debug log about adminq command with descriptor contents.
  **/
 void i40evf_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
-                   void *buffer)
+                   void *buffer, u16 buf_len)
 {
         struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
+        u16 len = le16_to_cpu(aq_desc->datalen);
         u8 *aq_buffer = (u8 *)buffer;
         u32 data[4];
         u32 i = 0;
@@ -105,7 +107,9 @@ void i40evf_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
         if ((buffer != NULL) && (aq_desc->datalen != 0)) {
                 memset(data, 0, sizeof(data));
                 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
-                for (i = 0; i < le16_to_cpu(aq_desc->datalen); i++) {
+                if (buf_len < len)
+                        len = buf_len;
+                for (i = 0; i < len; i++) {
                         data[((i % 16) / 4)] |=
                                 ((u32)aq_buffer[i]) << (8 * (i % 4));
                         if ((i % 16) == 15) {
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h
index 849edcc2e398..9173834825ac 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_prototype.h
+++ b/drivers/net/ethernet/intel/i40evf/i40e_prototype.h
@@ -53,10 +53,8 @@ i40e_status i40evf_asq_send_command(struct i40e_hw *hw,
 bool i40evf_asq_done(struct i40e_hw *hw);
 
 /* debug function for adminq */
-void i40evf_debug_aq(struct i40e_hw *hw,
-                   enum i40e_debug_mask mask,
-                   void *desc,
-                   void *buffer);
+void i40evf_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask,
+                     void *desc, void *buffer, u16 buf_len);
 
 void i40e_idle_aq(struct i40e_hw *hw);
 void i40evf_resume_aq(struct i40e_hw *hw);
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
index 95a3ec236b49..04c7c1557a0c 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.c
@@ -163,11 +163,13 @@ static bool i40e_check_tx_hang(struct i40e_ring *tx_ring)
          * pending but without time to complete it yet.
          */
         if ((tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) &&
-            tx_pending) {
+            (tx_pending >= I40E_MIN_DESC_PENDING)) {
                 /* make sure it is true for two checks in a row */
                 ret = test_and_set_bit(__I40E_HANG_CHECK_ARMED,
                                        &tx_ring->state);
-        } else {
+        } else if (!(tx_ring->tx_stats.tx_done_old == tx_ring->stats.packets) ||
+                   !(tx_pending < I40E_MIN_DESC_PENDING) ||
+                   !(tx_pending > 0)) {
                 /* update completed stats and disarm the hang check */
                 tx_ring->tx_stats.tx_done_old = tx_ring->stats.packets;
                 clear_bit(__I40E_HANG_CHECK_ARMED, &tx_ring->state);
@@ -744,7 +746,6 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
         ipv6_tunnel = (rx_ptype > I40E_RX_PTYPE_GRENAT6_MAC_PAY3) &&
                       (rx_ptype < I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4);
 
-        skb->encapsulation = ipv4_tunnel || ipv6_tunnel;
         skb->ip_summed = CHECKSUM_NONE;
 
         /* Rx csum enabled and ip headers found? */
@@ -818,6 +819,7 @@ static inline void i40e_rx_checksum(struct i40e_vsi *vsi,
         }
 
         skb->ip_summed = CHECKSUM_UNNECESSARY;
+        skb->csum_level = ipv4_tunnel || ipv6_tunnel;
 
         return;
 
diff --git a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h
index 8bc6858163b0..f6dcf9dd9290 100644
--- a/drivers/net/ethernet/intel/i40evf/i40e_txrx.h
+++ b/drivers/net/ethernet/intel/i40evf/i40e_txrx.h
@@ -121,6 +121,7 @@ enum i40e_dyn_idx_t {
 /* Tx Descriptors needed, worst case */
 #define TXD_USE_COUNT(S) DIV_ROUND_UP((S), I40E_MAX_DATA_PER_TXD)
 #define DESC_NEEDED (MAX_SKB_FRAGS + 4)
+#define I40E_MIN_DESC_PENDING   4
 
 #define I40E_TX_FLAGS_CSUM              (u32)(1)
 #define I40E_TX_FLAGS_HW_VLAN           (u32)(1 << 1)
diff --git a/drivers/net/ethernet/intel/i40evf/i40evf_main.c b/drivers/net/ethernet/intel/i40evf/i40evf_main.c
index 38429fae4fcf..c51bc7a33bc5 100644
--- a/drivers/net/ethernet/intel/i40evf/i40evf_main.c
+++ b/drivers/net/ethernet/intel/i40evf/i40evf_main.c
@@ -36,7 +36,7 @@ char i40evf_driver_name[] = "i40evf";
 static const char i40evf_driver_string[] =
         "Intel(R) XL710/X710 Virtual Function Network Driver";
 
-#define DRV_VERSION "0.9.40"
+#define DRV_VERSION "1.0.5"
 const char i40evf_driver_version[] = DRV_VERSION;
 static const char i40evf_copyright[] =
         "Copyright (c) 2013 - 2014 Intel Corporation.";
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.c b/drivers/net/ethernet/intel/igb/e1000_82575.c
index 236a6183a865..051ea94bdcd3 100644
--- a/drivers/net/ethernet/intel/igb/e1000_82575.c
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c
@@ -2548,11 +2548,13 @@ s32 igb_read_emi_reg(struct e1000_hw *hw, u16 addr, u16 *data)
 /**
  *  igb_set_eee_i350 - Enable/disable EEE support
  *  @hw: pointer to the HW structure
+ *  @adv1G: boolean flag enabling 1G EEE advertisement
+ *  @adv100m: boolean flag enabling 100M EEE advertisement
  *
  *  Enable/disable EEE based on setting in dev_spec structure.
  *
  **/
-s32 igb_set_eee_i350(struct e1000_hw *hw)
+s32 igb_set_eee_i350(struct e1000_hw *hw, bool adv1G, bool adv100M)
 {
         u32 ipcnfg, eeer;
 
@@ -2566,7 +2568,16 @@ s32 igb_set_eee_i350(struct e1000_hw *hw)
         if (!(hw->dev_spec._82575.eee_disable)) {
                 u32 eee_su = rd32(E1000_EEE_SU);
 
-                ipcnfg |= (E1000_IPCNFG_EEE_1G_AN | E1000_IPCNFG_EEE_100M_AN);
+                if (adv100M)
+                        ipcnfg |= E1000_IPCNFG_EEE_100M_AN;
+                else
+                        ipcnfg &= ~E1000_IPCNFG_EEE_100M_AN;
+
+                if (adv1G)
+                        ipcnfg |= E1000_IPCNFG_EEE_1G_AN;
+                else
+                        ipcnfg &= ~E1000_IPCNFG_EEE_1G_AN;
+
                 eeer |= (E1000_EEER_TX_LPI_EN | E1000_EEER_RX_LPI_EN |
                         E1000_EEER_LPI_FC);
 
@@ -2593,11 +2604,13 @@ out:
 /**
  *  igb_set_eee_i354 - Enable/disable EEE support
  *  @hw: pointer to the HW structure
+ *  @adv1G: boolean flag enabling 1G EEE advertisement
+ *  @adv100m: boolean flag enabling 100M EEE advertisement
  *
  *  Enable/disable EEE legacy mode based on setting in dev_spec structure.
  *
  **/
-s32 igb_set_eee_i354(struct e1000_hw *hw)
+s32 igb_set_eee_i354(struct e1000_hw *hw, bool adv1G, bool adv100M)
 {
         struct e1000_phy_info *phy = &hw->phy;
         s32 ret_val = 0;
@@ -2636,8 +2649,16 @@ s32 igb_set_eee_i354(struct e1000_hw *hw)
                 if (ret_val)
                         goto out;
 
-                phy_data |= E1000_EEE_ADV_100_SUPPORTED |
-                            E1000_EEE_ADV_1000_SUPPORTED;
+                if (adv100M)
+                        phy_data |= E1000_EEE_ADV_100_SUPPORTED;
+                else
+                        phy_data &= ~E1000_EEE_ADV_100_SUPPORTED;
+
+                if (adv1G)
+                        phy_data |= E1000_EEE_ADV_1000_SUPPORTED;
+                else
+                        phy_data &= ~E1000_EEE_ADV_1000_SUPPORTED;
+
                 ret_val = igb_write_xmdio_reg(hw, E1000_EEE_ADV_ADDR_I354,
                                                 E1000_EEE_ADV_DEV_I354,
                                                 phy_data);
diff --git a/drivers/net/ethernet/intel/igb/e1000_82575.h b/drivers/net/ethernet/intel/igb/e1000_82575.h
index b407c55738fa..2154aea7aa7e 100644
--- a/drivers/net/ethernet/intel/igb/e1000_82575.h
+++ b/drivers/net/ethernet/intel/igb/e1000_82575.h
@@ -263,8 +263,8 @@ void igb_vmdq_set_loopback_pf(struct e1000_hw *, bool);
 void igb_vmdq_set_replication_pf(struct e1000_hw *, bool);
 u16 igb_rxpbs_adjust_82580(u32 data);
 s32 igb_read_emi_reg(struct e1000_hw *, u16 addr, u16 *data);
-s32 igb_set_eee_i350(struct e1000_hw *);
-s32 igb_set_eee_i354(struct e1000_hw *);
+s32 igb_set_eee_i350(struct e1000_hw *, bool adv1G, bool adv100M);
+s32 igb_set_eee_i354(struct e1000_hw *, bool adv1G, bool adv100M);
 s32 igb_get_eee_status_i354(struct e1000_hw *hw, bool *status);
 
 #define E1000_I2C_THERMAL_SENSOR_ADDR   0xF8
diff --git a/drivers/net/ethernet/intel/igb/igb_ethtool.c b/drivers/net/ethernet/intel/igb/igb_ethtool.c
index c737d1f40838..02cfd3b14762 100644
--- a/drivers/net/ethernet/intel/igb/igb_ethtool.c
+++ b/drivers/net/ethernet/intel/igb/igb_ethtool.c
@@ -2675,6 +2675,7 @@ static int igb_set_eee(struct net_device *netdev,
         struct igb_adapter *adapter = netdev_priv(netdev);
         struct e1000_hw *hw = &adapter->hw;
         struct ethtool_eee eee_curr;
+        bool adv1g_eee = true, adv100m_eee = true;
         s32 ret_val;
 
         if ((hw->mac.type < e1000_i350) ||
@@ -2701,12 +2702,14 @@ static int igb_set_eee(struct net_device *netdev,
                         return -EINVAL;
                 }
 
-                if (edata->advertised &
-                    ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL)) {
+                if (!edata->advertised || (edata->advertised &
+                    ~(ADVERTISE_100_FULL | ADVERTISE_1000_FULL))) {
                         dev_err(&adapter->pdev->dev,
-                                "EEE Advertisement supports only 100Tx and or 100T full duplex\n");
+                                "EEE Advertisement supports only 100Tx and/or 100T full duplex\n");
                         return -EINVAL;
                 }
+                adv100m_eee = !!(edata->advertised & ADVERTISE_100_FULL);
+                adv1g_eee = !!(edata->advertised & ADVERTISE_1000_FULL);
 
         } else if (!edata->eee_enabled) {
                 dev_err(&adapter->pdev->dev,
@@ -2718,10 +2721,6 @@ static int igb_set_eee(struct net_device *netdev,
         if (hw->dev_spec._82575.eee_disable != !edata->eee_enabled) {
                 hw->dev_spec._82575.eee_disable = !edata->eee_enabled;
                 adapter->flags |= IGB_FLAG_EEE;
-                if (hw->mac.type == e1000_i350)
-                        igb_set_eee_i350(hw);
-                else
-                        igb_set_eee_i354(hw);
 
                 /* reset link */
                 if (netif_running(netdev))
@@ -2730,6 +2729,17 @@ static int igb_set_eee(struct net_device *netdev,
                         igb_reset(adapter);
         }
 
+        if (hw->mac.type == e1000_i354)
+                ret_val = igb_set_eee_i354(hw, adv1g_eee, adv100m_eee);
+        else
+                ret_val = igb_set_eee_i350(hw, adv1g_eee, adv100m_eee);
+
+        if (ret_val) {
+                dev_err(&adapter->pdev->dev,
+                        "Problem setting EEE advertisement options\n");
+                return -EINVAL;
+        }
+
         return 0;
 }
 
diff --git a/drivers/net/ethernet/intel/igb/igb_main.c b/drivers/net/ethernet/intel/igb/igb_main.c
index cb14bbdfb056..6cf0c17ad9c4 100644
--- a/drivers/net/ethernet/intel/igb/igb_main.c
+++ b/drivers/net/ethernet/intel/igb/igb_main.c
@@ -2012,10 +2012,10 @@ void igb_reset(struct igb_adapter *adapter)
                 case e1000_i350:
                 case e1000_i210:
                 case e1000_i211:
-                        igb_set_eee_i350(hw);
+                        igb_set_eee_i350(hw, true, true);
                         break;
                 case e1000_i354:
-                        igb_set_eee_i354(hw);
+                        igb_set_eee_i354(hw, true, true);
                         break;
                 default:
                         break;
@@ -2619,7 +2619,7 @@ static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 case e1000_i210:
                 case e1000_i211:
                         /* Enable EEE for internal copper PHY devices */
-                        err = igb_set_eee_i350(hw);
+                        err = igb_set_eee_i350(hw, true, true);
                         if ((!err) &&
                             (!hw->dev_spec._82575.eee_disable)) {
                                 adapter->eee_advert =
@@ -2630,7 +2630,7 @@ static int igb_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 case e1000_i354:
                         if ((rd32(E1000_CTRL_EXT) &
                             E1000_CTRL_EXT_LINK_MODE_SGMII)) {
-                                err = igb_set_eee_i354(hw);
+                                err = igb_set_eee_i354(hw, true, true);
                                 if ((!err) &&
                                         (!hw->dev_spec._82575.eee_disable)) {
                                         adapter->eee_advert =
@@ -4813,6 +4813,41 @@ static void igb_tx_olinfo_status(struct igb_ring *tx_ring,
         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
 }
 
+static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
+{
+        struct net_device *netdev = tx_ring->netdev;
+
+        netif_stop_subqueue(netdev, tx_ring->queue_index);
+
+        /* Herbert's original patch had:
+         *  smp_mb__after_netif_stop_queue();
+         * but since that doesn't exist yet, just open code it.
+         */
+        smp_mb();
+
+        /* We need to check again in a case another CPU has just
+         * made room available.
+         */
+        if (igb_desc_unused(tx_ring) < size)
+                return -EBUSY;
+
+        /* A reprieve! */
+        netif_wake_subqueue(netdev, tx_ring->queue_index);
+
+        u64_stats_update_begin(&tx_ring->tx_syncp2);
+        tx_ring->tx_stats.restart_queue2++;
+        u64_stats_update_end(&tx_ring->tx_syncp2);
+
+        return 0;
+}
+
+static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
+{
+        if (igb_desc_unused(tx_ring) >= size)
+                return 0;
+        return __igb_maybe_stop_tx(tx_ring, size);
+}
+
 static void igb_tx_map(struct igb_ring *tx_ring,
                        struct igb_tx_buffer *first,
                        const u8 hdr_len)
@@ -4915,13 +4950,17 @@ static void igb_tx_map(struct igb_ring *tx_ring,
 
         tx_ring->next_to_use = i;
 
-        writel(i, tx_ring->tail);
+        /* Make sure there is space in the ring for the next send. */
+        igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
 
-        /* we need this if more than one processor can write to our tail
-         * at a time, it synchronizes IO on IA64/Altix systems
-         */
-        mmiowb();
+        if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
+                writel(i, tx_ring->tail);
 
+                /* we need this if more than one processor can write to our tail
+                 * at a time, it synchronizes IO on IA64/Altix systems
+                 */
+                mmiowb();
+        }
         return;
 
 dma_error:
@@ -4941,41 +4980,6 @@ dma_error:
         tx_ring->next_to_use = i;
 }
 
-static int __igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
-{
-        struct net_device *netdev = tx_ring->netdev;
-
-        netif_stop_subqueue(netdev, tx_ring->queue_index);
-
-        /* Herbert's original patch had:
-         *  smp_mb__after_netif_stop_queue();
-         * but since that doesn't exist yet, just open code it.
-         */
-        smp_mb();
-
-        /* We need to check again in a case another CPU has just
-         * made room available.
-         */
-        if (igb_desc_unused(tx_ring) < size)
-                return -EBUSY;
-
-        /* A reprieve! */
-        netif_wake_subqueue(netdev, tx_ring->queue_index);
-
-        u64_stats_update_begin(&tx_ring->tx_syncp2);
-        tx_ring->tx_stats.restart_queue2++;
-        u64_stats_update_end(&tx_ring->tx_syncp2);
-
-        return 0;
-}
-
-static inline int igb_maybe_stop_tx(struct igb_ring *tx_ring, const u16 size)
-{
-        if (igb_desc_unused(tx_ring) >= size)
-                return 0;
-        return __igb_maybe_stop_tx(tx_ring, size);
-}
-
 netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
                                 struct igb_ring *tx_ring)
 {
@@ -5046,9 +5050,6 @@ netdev_tx_t igb_xmit_frame_ring(struct sk_buff *skb,
 
         igb_tx_map(tx_ring, first, hdr_len);
 
-        /* Make sure there is space in the ring for the next send. */
-        igb_maybe_stop_tx(tx_ring, DESC_NEEDED);
-
         return NETDEV_TX_OK;
 
 out_drop:
@@ -6768,113 +6769,6 @@ static bool igb_is_non_eop(struct igb_ring *rx_ring,
 }
 
 /**
- *  igb_get_headlen - determine size of header for LRO/GRO
- *  @data: pointer to the start of the headers
- *  @max_len: total length of section to find headers in
- *
- *  This function is meant to determine the length of headers that will
- *  be recognized by hardware for LRO, and GRO offloads.  The main
- *  motivation of doing this is to only perform one pull for IPv4 TCP
- *  packets so that we can do basic things like calculating the gso_size
- *  based on the average data per packet.
- **/
-static unsigned int igb_get_headlen(unsigned char *data,
-                                    unsigned int max_len)
-{
-        union {
-                unsigned char *network;
-                /* l2 headers */
-                struct ethhdr *eth;
-                struct vlan_hdr *vlan;
-                /* l3 headers */
-                struct iphdr *ipv4;
-                struct ipv6hdr *ipv6;
-        } hdr;
-        __be16 protocol;
-        u8 nexthdr = 0; /* default to not TCP */
-        u8 hlen;
-
-        /* this should never happen, but better safe than sorry */
-        if (max_len < ETH_HLEN)
-                return max_len;
-
-        /* initialize network frame pointer */
-        hdr.network = data;
-
-        /* set first protocol and move network header forward */
-        protocol = hdr.eth->h_proto;
-        hdr.network += ETH_HLEN;
-
-        /* handle any vlan tag if present */
-        if (protocol == htons(ETH_P_8021Q)) {
-                if ((hdr.network - data) > (max_len - VLAN_HLEN))
-                        return max_len;
-
-                protocol = hdr.vlan->h_vlan_encapsulated_proto;
-                hdr.network += VLAN_HLEN;
-        }
-
-        /* handle L3 protocols */
-        if (protocol == htons(ETH_P_IP)) {
-                if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
-                        return max_len;
-
-                /* access ihl as a u8 to avoid unaligned access on ia64 */
-                hlen = (hdr.network[0] & 0x0F) << 2;
-
-                /* verify hlen meets minimum size requirements */
-                if (hlen < sizeof(struct iphdr))
-                        return hdr.network - data;
-
-                /* record next protocol if header is present */
-                if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
-                        nexthdr = hdr.ipv4->protocol;
-        } else if (protocol == htons(ETH_P_IPV6)) {
-                if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
-                        return max_len;
-
-                /* record next protocol */
-                nexthdr = hdr.ipv6->nexthdr;
-                hlen = sizeof(struct ipv6hdr);
-        } else {
-                return hdr.network - data;
-        }
-
-        /* relocate pointer to start of L4 header */
-        hdr.network += hlen;
-
-        /* finally sort out TCP */
-        if (nexthdr == IPPROTO_TCP) {
-                if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
-                        return max_len;
-
-                /* access doff as a u8 to avoid unaligned access on ia64 */
-                hlen = (hdr.network[12] & 0xF0) >> 2;
-
-                /* verify hlen meets minimum size requirements */
-                if (hlen < sizeof(struct tcphdr))
-                        return hdr.network - data;
-
-                hdr.network += hlen;
-        } else if (nexthdr == IPPROTO_UDP) {
-                if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
-                        return max_len;
-
-                hdr.network += sizeof(struct udphdr);
-        }
-
-        /* If everything has gone correctly hdr.network should be the
-         * data section of the packet and will be the end of the header.
-         * If not then it probably represents the end of the last recognized
-         * header.
-         */
-        if ((hdr.network - data) < max_len)
-                return hdr.network - data;
-        else
-                return max_len;
-}
-
-/**
  *  igb_pull_tail - igb specific version of skb_pull_tail
  *  @rx_ring: rx descriptor ring packet is being transacted on
  *  @rx_desc: pointer to the EOP Rx descriptor
@@ -6918,7 +6812,7 @@ static void igb_pull_tail(struct igb_ring *rx_ring,
         /* we need the header to contain the greater of either ETH_HLEN or
          * 60 bytes if the skb->len is less than 60 for skb_pad.
          */
-        pull_len = igb_get_headlen(va, IGB_RX_HDR_LEN);
+        pull_len = eth_get_headlen(va, IGB_RX_HDR_LEN);
 
         /* align pull length to size of long to optimize memcpy performance */
         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
index 2d9451e39686..ae36fd61a3aa 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_lib.c
@@ -1086,6 +1086,11 @@ static void ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
                         return;
         }
 
+        /* At this point, we do not have MSI-X capabilities. We need to
+         * reconfigure or disable various features which require MSI-X
+         * capability.
+         */
+
         /* disable DCB if number of TCs exceeds 1 */
         if (netdev_get_num_tc(adapter->netdev) > 1) {
                 e_err(probe, "num TCs exceeds number of queues - disabling DCB\n");
@@ -1107,6 +1112,9 @@ static void ixgbe_set_interrupt_capability(struct ixgbe_adapter *adapter)
         /* disable RSS */
         adapter->ring_feature[RING_F_RSS].limit = 1;
 
+        /* recalculate number of queues now that many features have been
+         * changed or disabled.
+         */
         ixgbe_set_num_queues(adapter);
         adapter->num_q_vectors = 1;
 
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
index 87bd53fdd209..166dc0015a5e 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
@@ -1521,120 +1521,6 @@ void ixgbe_alloc_rx_buffers(struct ixgbe_ring *rx_ring, u16 cleaned_count)
                 ixgbe_release_rx_desc(rx_ring, i);
 }
 
-/**
- * ixgbe_get_headlen - determine size of header for RSC/LRO/GRO/FCOE
- * @data: pointer to the start of the headers
- * @max_len: total length of section to find headers in
- *
- * This function is meant to determine the length of headers that will
- * be recognized by hardware for LRO, GRO, and RSC offloads.  The main
- * motivation of doing this is to only perform one pull for IPv4 TCP
- * packets so that we can do basic things like calculating the gso_size
- * based on the average data per packet.
- **/
-static unsigned int ixgbe_get_headlen(unsigned char *data,
-                                      unsigned int max_len)
-{
-        union {
-                unsigned char *network;
-                /* l2 headers */
-                struct ethhdr *eth;
-                struct vlan_hdr *vlan;
-                /* l3 headers */
-                struct iphdr *ipv4;
-                struct ipv6hdr *ipv6;
-        } hdr;
-        __be16 protocol;
-        u8 nexthdr = 0; /* default to not TCP */
-        u8 hlen;
-
-        /* this should never happen, but better safe than sorry */
-        if (max_len < ETH_HLEN)
-                return max_len;
-
-        /* initialize network frame pointer */
-        hdr.network = data;
-
-        /* set first protocol and move network header forward */
-        protocol = hdr.eth->h_proto;
-        hdr.network += ETH_HLEN;
-
-        /* handle any vlan tag if present */
-        if (protocol == htons(ETH_P_8021Q)) {
-                if ((hdr.network - data) > (max_len - VLAN_HLEN))
-                        return max_len;
-
-                protocol = hdr.vlan->h_vlan_encapsulated_proto;
-                hdr.network += VLAN_HLEN;
-        }
-
-        /* handle L3 protocols */
-        if (protocol == htons(ETH_P_IP)) {
-                if ((hdr.network - data) > (max_len - sizeof(struct iphdr)))
-                        return max_len;
-
-                /* access ihl as a u8 to avoid unaligned access on ia64 */
-                hlen = (hdr.network[0] & 0x0F) << 2;
-
-                /* verify hlen meets minimum size requirements */
-                if (hlen < sizeof(struct iphdr))
-                        return hdr.network - data;
-
-                /* record next protocol if header is present */
-                if (!(hdr.ipv4->frag_off & htons(IP_OFFSET)))
-                        nexthdr = hdr.ipv4->protocol;
-        } else if (protocol == htons(ETH_P_IPV6)) {
-                if ((hdr.network - data) > (max_len - sizeof(struct ipv6hdr)))
-                        return max_len;
-
-                /* record next protocol */
-                nexthdr = hdr.ipv6->nexthdr;
-                hlen = sizeof(struct ipv6hdr);
-#ifdef IXGBE_FCOE
-        } else if (protocol == htons(ETH_P_FCOE)) {
-                if ((hdr.network - data) > (max_len - FCOE_HEADER_LEN))
-                        return max_len;
-                hlen = FCOE_HEADER_LEN;
-#endif
-        } else {
-                return hdr.network - data;
-        }
-
-        /* relocate pointer to start of L4 header */
-        hdr.network += hlen;
-
-        /* finally sort out TCP/UDP */
-        if (nexthdr == IPPROTO_TCP) {
-                if ((hdr.network - data) > (max_len - sizeof(struct tcphdr)))
-                        return max_len;
-
-                /* access doff as a u8 to avoid unaligned access on ia64 */
-                hlen = (hdr.network[12] & 0xF0) >> 2;
-
-                /* verify hlen meets minimum size requirements */
-                if (hlen < sizeof(struct tcphdr))
-                        return hdr.network - data;
-
-                hdr.network += hlen;
-        } else if (nexthdr == IPPROTO_UDP) {
-                if ((hdr.network - data) > (max_len - sizeof(struct udphdr)))
-                        return max_len;
-
-                hdr.network += sizeof(struct udphdr);
-        }
-
-        /*
-         * If everything has gone correctly hdr.network should be the
-         * data section of the packet and will be the end of the header.
-         * If not then it probably represents the end of the last recognized
-         * header.
-         */
-        if ((hdr.network - data) < max_len)
-                return hdr.network - data;
-        else
-                return max_len;
-}
-
 static void ixgbe_set_rsc_gso_size(struct ixgbe_ring *ring,
                                    struct sk_buff *skb)
 {
@@ -1793,7 +1679,7 @@ static void ixgbe_pull_tail(struct ixgbe_ring *rx_ring,
          * we need the header to contain the greater of either ETH_HLEN or
          * 60 bytes if the skb->len is less than 60 for skb_pad.
          */
-        pull_len = ixgbe_get_headlen(va, IXGBE_RX_HDR_SIZE);
+        pull_len = eth_get_headlen(va, IXGBE_RX_HDR_SIZE);
 
         /* align pull length to size of long to optimize memcpy performance */
         skb_copy_to_linear_data(skb, va, ALIGN(pull_len, sizeof(long)));
@@ -6319,25 +6205,55 @@ static void ixgbe_watchdog_link_is_down(struct ixgbe_adapter *adapter)
         ixgbe_ping_all_vfs(adapter);
 }
 
+static bool ixgbe_ring_tx_pending(struct ixgbe_adapter *adapter)
+{
+        int i;
+
+        for (i = 0; i < adapter->num_tx_queues; i++) {
+                struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
+
+                if (tx_ring->next_to_use != tx_ring->next_to_clean)
+                        return true;
+        }
+
+        return false;
+}
+
+static bool ixgbe_vf_tx_pending(struct ixgbe_adapter *adapter)
+{
+        struct ixgbe_hw *hw = &adapter->hw;
+        struct ixgbe_ring_feature *vmdq = &adapter->ring_feature[RING_F_VMDQ];
+        u32 q_per_pool = __ALIGN_MASK(1, ~vmdq->mask);
+
+        int i, j;
+
+        if (!adapter->num_vfs)
+                return false;
+
+        for (i = 0; i < adapter->num_vfs; i++) {
+                for (j = 0; j < q_per_pool; j++) {
+                        u32 h, t;
+
+                        h = IXGBE_READ_REG(hw, IXGBE_PVFTDHN(q_per_pool, i, j));
+                        t = IXGBE_READ_REG(hw, IXGBE_PVFTDTN(q_per_pool, i, j));
+
+                        if (h != t)
+                                return true;
+                }
+        }
+
+        return false;
+}
+
 /**
  * ixgbe_watchdog_flush_tx - flush queues on link down
  * @adapter: pointer to the device adapter structure
  **/
 static void ixgbe_watchdog_flush_tx(struct ixgbe_adapter *adapter)
 {
-        int i;
-        int some_tx_pending = 0;
-
         if (!netif_carrier_ok(adapter->netdev)) {
-                for (i = 0; i < adapter->num_tx_queues; i++) {
-                        struct ixgbe_ring *tx_ring = adapter->tx_ring[i];
-                        if (tx_ring->next_to_use != tx_ring->next_to_clean) {
-                                some_tx_pending = 1;
-                                break;
-                        }
-                }
-
-                if (some_tx_pending) {
+                if (ixgbe_ring_tx_pending(adapter) ||
+                    ixgbe_vf_tx_pending(adapter)) {
                         /* We've lost link, so the controller stops DMA,
                          * but we've got queued Tx work that's never going
                          * to get done, so reset controller to flush Tx.
@@ -6837,6 +6753,36 @@ static void ixgbe_tx_olinfo_status(union ixgbe_adv_tx_desc *tx_desc,
         tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
 }
 
+static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
+{
+        netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
+
+        /* Herbert's original patch had:
+         *  smp_mb__after_netif_stop_queue();
+         * but since that doesn't exist yet, just open code it.
+         */
+        smp_mb();
+
+        /* We need to check again in a case another CPU has just
+         * made room available.
+         */
+        if (likely(ixgbe_desc_unused(tx_ring) < size))
+                return -EBUSY;
+
+        /* A reprieve! - use start_queue because it doesn't call schedule */
+        netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
+        ++tx_ring->tx_stats.restart_queue;
+        return 0;
+}
+
+static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
+{
+        if (likely(ixgbe_desc_unused(tx_ring) >= size))
+                return 0;
+
+        return __ixgbe_maybe_stop_tx(tx_ring, size);
+}
+
 #define IXGBE_TXD_CMD (IXGBE_TXD_CMD_EOP | \
                        IXGBE_TXD_CMD_RS)
 
@@ -6958,8 +6904,12 @@ static void ixgbe_tx_map(struct ixgbe_ring *tx_ring,
 
         tx_ring->next_to_use = i;
 
-        /* notify HW of packet */
-        ixgbe_write_tail(tx_ring, i);
+        ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
+
+        if (netif_xmit_stopped(txring_txq(tx_ring)) || !skb->xmit_more) {
+                /* notify HW of packet */
+                ixgbe_write_tail(tx_ring, i);
+        }
 
         return;
 dma_error:
@@ -7067,32 +7017,6 @@ static void ixgbe_atr(struct ixgbe_ring *ring,
                                               input, common, ring->queue_index);
 }
 
-static int __ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
-{
-        netif_stop_subqueue(tx_ring->netdev, tx_ring->queue_index);
-        /* Herbert's original patch had:
-         *  smp_mb__after_netif_stop_queue();
-         * but since that doesn't exist yet, just open code it. */
-        smp_mb();
-
-        /* We need to check again in a case another CPU has just
-         * made room available. */
-        if (likely(ixgbe_desc_unused(tx_ring) < size))
-                return -EBUSY;
-
-        /* A reprieve! - use start_queue because it doesn't call schedule */
-        netif_start_subqueue(tx_ring->netdev, tx_ring->queue_index);
-        ++tx_ring->tx_stats.restart_queue;
-        return 0;
-}
-
-static inline int ixgbe_maybe_stop_tx(struct ixgbe_ring *tx_ring, u16 size)
-{
-        if (likely(ixgbe_desc_unused(tx_ring) >= size))
-                return 0;
-        return __ixgbe_maybe_stop_tx(tx_ring, size);
-}
-
 static u16 ixgbe_select_queue(struct net_device *dev, struct sk_buff *skb,
                               void *accel_priv, select_queue_fallback_t fallback)
 {
@@ -7261,8 +7185,6 @@ xmit_fcoe:
 #endif /* IXGBE_FCOE */
         ixgbe_tx_map(tx_ring, first, hdr_len);
 
-        ixgbe_maybe_stop_tx(tx_ring, DESC_NEEDED);
-
         return NETDEV_TX_OK;
 
 out_drop:
@@ -7735,39 +7657,13 @@ static int ixgbe_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
                              const unsigned char *addr,
                              u16 flags)
 {
-        struct ixgbe_adapter *adapter = netdev_priv(dev);
-        int err;
-
-        if (!(adapter->flags & IXGBE_FLAG_SRIOV_ENABLED))
-                return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
-
-        /* Hardware does not support aging addresses so if a
-         * ndm_state is given only allow permanent addresses
-         */
-        if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
-                pr_info("%s: FDB only supports static addresses\n",
-                        ixgbe_driver_name);
-                return -EINVAL;
-        }
-
+        /* guarantee we can provide a unique filter for the unicast address */
         if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr)) {
-                u32 rar_uc_entries = IXGBE_MAX_PF_MACVLANS;
-
-                if (netdev_uc_count(dev) < rar_uc_entries)
-                        err = dev_uc_add_excl(dev, addr);
-                else
-                        err = -ENOMEM;
-        } else if (is_multicast_ether_addr(addr)) {
-                err = dev_mc_add_excl(dev, addr);
-        } else {
-                err = -EINVAL;
+                if (IXGBE_MAX_PF_MACVLANS <= netdev_uc_count(dev))
+                        return -ENOMEM;
         }
 
-        /* Only return duplicate errors if NLM_F_EXCL is set */
-        if (err == -EEXIST && !(flags & NLM_F_EXCL))
-                err = 0;
-
-        return err;
+        return ndo_dflt_fdb_add(ndm, tb, dev, addr, flags);
 }
 
 static int ixgbe_ndo_bridge_setlink(struct net_device *dev,
@@ -7830,9 +7726,17 @@ static void *ixgbe_fwd_add(struct net_device *pdev, struct net_device *vdev)
 {
         struct ixgbe_fwd_adapter *fwd_adapter = NULL;
         struct ixgbe_adapter *adapter = netdev_priv(pdev);
+        int used_pools = adapter->num_vfs + adapter->num_rx_pools;
         unsigned int limit;
         int pool, err;
 
+        /* Hardware has a limited number of available pools. Each VF, and the
+         * PF require a pool. Check to ensure we don't attempt to use more
+         * then the available number of pools.
+         */
+        if (used_pools >= IXGBE_MAX_VF_FUNCTIONS)
+                return ERR_PTR(-EINVAL);
+
 #ifdef CONFIG_RPS
         if (vdev->num_rx_queues != vdev->num_tx_queues) {
                 netdev_info(pdev, "%s: Only supports a single queue count for TX and RX\n",
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
index c14d4d89672f..706fc69aa0c5 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.c
@@ -250,13 +250,15 @@ static int ixgbe_pci_sriov_enable(struct pci_dev *dev, int num_vfs)
         if (err)
                 return err;
 
-        /* While the SR-IOV capability structure reports total VFs to be
-         * 64 we limit the actual number that can be allocated to 63 so
-         * that some transmit/receive resources can be reserved to the
-         * PF.  The PCI bus driver already checks for other values out of
-         * range.
+        /* While the SR-IOV capability structure reports total VFs to be 64,
+         * we have to limit the actual number allocated based on two factors.
+         * First, we reserve some transmit/receive resources for the PF.
+         * Second, VMDQ also uses the same pools that SR-IOV does. We need to
+         * account for this, so that we don't accidentally allocate more VFs
+         * than we have available pools. The PCI bus driver already checks for
+         * other values out of range.
          */
-        if (num_vfs > IXGBE_MAX_VFS_DRV_LIMIT)
+        if ((num_vfs + adapter->num_rx_pools) > IXGBE_MAX_VF_FUNCTIONS)
                 return -EPERM;
 
         adapter->num_vfs = num_vfs;
diff --git a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
index e6b07c2a01fe..dfd55d83bc03 100644
--- a/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
+++ b/drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
@@ -2194,6 +2194,8 @@ enum {
 #define IXGBE_VFLRE(_i)         ((((_i) & 1) ? 0x001C0 : 0x00600))
 #define IXGBE_VFLREC(_i)                (0x00700 + ((_i) * 4))
 /* Translated register #defines */
+#define IXGBE_PVFTDH(P)         (0x06010 + (0x40 * (P)))
+#define IXGBE_PVFTDT(P)         (0x06018 + (0x40 * (P)))
 #define IXGBE_PVFTDWBAL(P)      (0x06038 + (0x40 * (P)))
 #define IXGBE_PVFTDWBAH(P)      (0x0603C + (0x40 * (P)))
 
@@ -2202,6 +2204,11 @@ enum {
 #define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \
                 (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index)))
 
+#define IXGBE_PVFTDHN(q_per_pool, vf_number, vf_q_index) \
+                (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index)))
+#define IXGBE_PVFTDTN(q_per_pool, vf_number, vf_q_index) \
+                (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index)))
+
 enum ixgbe_fdir_pballoc_type {
         IXGBE_FDIR_PBALLOC_NONE = 0,
         IXGBE_FDIR_PBALLOC_64K  = 1,
diff --git a/drivers/net/ethernet/intel/ixgbevf/vf.c b/drivers/net/ethernet/intel/ixgbevf/vf.c
index 4d44d64ae387..9cddd56d02c3 100644
--- a/drivers/net/ethernet/intel/ixgbevf/vf.c
+++ b/drivers/net/ethernet/intel/ixgbevf/vf.c
@@ -434,6 +434,21 @@ static s32 ixgbevf_check_mac_link_vf(struct ixgbe_hw *hw,
         if (!(links_reg & IXGBE_LINKS_UP))
                 goto out;
 
+        /* for SFP+ modules and DA cables on 82599 it can take up to 500usecs
+         * before the link status is correct
+         */
+        if (mac->type == ixgbe_mac_82599_vf) {
+                int i;
+
+                for (i = 0; i < 5; i++) {
+                        udelay(100);
+                        links_reg = IXGBE_READ_REG(hw, IXGBE_VFLINKS);
+
+                        if (!(links_reg & IXGBE_LINKS_UP))
+                                goto out;
+                }
+        }
+
         switch (links_reg & IXGBE_LINKS_SPEED_82599) {
         case IXGBE_LINKS_SPEED_10G_82599:
                 *speed = IXGBE_LINK_SPEED_10GB_FULL;
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_rx.c b/drivers/net/ethernet/mellanox/mlx4/en_rx.c
index 9c909d23f14c..14686b6f4bc5 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_rx.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_rx.c
@@ -588,6 +588,8 @@ static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
                 skb_copy_to_linear_data(skb, va, length);
                 skb->tail += length;
         } else {
+                unsigned int pull_len;
+
                 /* Move relevant fragments to skb */
                 used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
                                                         skb, length);
@@ -597,16 +599,17 @@ static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
                 }
                 skb_shinfo(skb)->nr_frags = used_frags;
 
+                pull_len = eth_get_headlen(va, SMALL_PACKET_SIZE);
                 /* Copy headers into the skb linear buffer */
-                memcpy(skb->data, va, HEADER_COPY_SIZE);
-                skb->tail += HEADER_COPY_SIZE;
+                memcpy(skb->data, va, pull_len);
+                skb->tail += pull_len;
 
                 /* Skip headers in first fragment */
-                skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
+                skb_shinfo(skb)->frags[0].page_offset += pull_len;
 
                 /* Adjust size of first fragment */
-                skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
-                skb->data_len = length - HEADER_COPY_SIZE;
+                skb_frag_size_sub(&skb_shinfo(skb)->frags[0], pull_len);
+                skb->data_len = length - pull_len;
         }
         return skb;
 }
@@ -769,7 +772,7 @@ int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int bud
                                         gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
 
                                         if (l2_tunnel)
-                                                gro_skb->encapsulation = 1;
+                                                gro_skb->csum_level = 1;
                                         if ((cqe->vlan_my_qpn &
                                             cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
                                             (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
@@ -823,8 +826,8 @@ int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int bud
                 skb->protocol = eth_type_trans(skb, dev);
                 skb_record_rx_queue(skb, cq->ring);
 
-                if (l2_tunnel)
-                        skb->encapsulation = 1;
+                if (l2_tunnel && ip_summed == CHECKSUM_UNNECESSARY)
+                        skb->csum_level = 1;
 
                 if (dev->features & NETIF_F_RXHASH)
                         skb_set_hash(skb,
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_tx.c b/drivers/net/ethernet/mellanox/mlx4/en_tx.c
index dae3da6d8dd0..bc8f51c77d80 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_tx.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_tx.c
@@ -319,7 +319,7 @@ static u32 mlx4_en_free_tx_desc(struct mlx4_en_priv *priv,
                         }
                 }
         }
-        dev_kfree_skb_any(skb);
+        dev_consume_skb_any(skb);
         return tx_info->nr_txbb;
 }
 
diff --git a/drivers/net/ethernet/nvidia/forcedeth.c b/drivers/net/ethernet/nvidia/forcedeth.c
index 925b296d8ab8..f39cae620f61 100644
--- a/drivers/net/ethernet/nvidia/forcedeth.c
+++ b/drivers/net/ethernet/nvidia/forcedeth.c
@@ -1481,7 +1481,7 @@ static int phy_init(struct net_device *dev)
         }
 
         /* phy vendor specific configuration */
-        if ((np->phy_oui == PHY_OUI_CICADA)) {
+        if (np->phy_oui == PHY_OUI_CICADA) {
                 if (init_cicada(dev, np, phyinterface)) {
                         netdev_info(dev, "%s: phy init failed\n",
                                     pci_name(np->pci_dev));
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
index b84f5ea3d659..e56c1bb36141 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
@@ -39,8 +39,8 @@
 
 #define _QLCNIC_LINUX_MAJOR 5
 #define _QLCNIC_LINUX_MINOR 3
-#define _QLCNIC_LINUX_SUBVERSION 61
-#define QLCNIC_LINUX_VERSIONID  "5.3.61"
+#define _QLCNIC_LINUX_SUBVERSION 62
+#define QLCNIC_LINUX_VERSIONID  "5.3.62"
 #define QLCNIC_DRV_IDC_VER  0x01
 #define QLCNIC_DRIVER_VERSION  ((_QLCNIC_LINUX_MAJOR << 16) |\
                  (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
@@ -540,6 +540,8 @@ struct qlcnic_hardware_context {
         u8 lb_mode;
         u16 vxlan_port;
         struct device *hwmon_dev;
+        u32 post_mode;
+        bool run_post;
 };
 
 struct qlcnic_adapter_stats {
@@ -2283,6 +2285,7 @@ extern const struct ethtool_ops qlcnic_ethtool_failed_ops;
 
 #define PCI_DEVICE_ID_QLOGIC_QLE824X            0x8020
 #define PCI_DEVICE_ID_QLOGIC_QLE834X            0x8030
+#define PCI_DEVICE_ID_QLOGIC_QLE8830            0x8830
 #define PCI_DEVICE_ID_QLOGIC_VF_QLE834X 0x8430
 #define PCI_DEVICE_ID_QLOGIC_QLE844X            0x8040
 #define PCI_DEVICE_ID_QLOGIC_VF_QLE844X 0x8440
@@ -2307,6 +2310,7 @@ static inline bool qlcnic_83xx_check(struct qlcnic_adapter *adapter)
         bool status;
 
         status = ((device == PCI_DEVICE_ID_QLOGIC_QLE834X) ||
+                  (device == PCI_DEVICE_ID_QLOGIC_QLE8830) ||
                   (device == PCI_DEVICE_ID_QLOGIC_QLE844X) ||
                   (device == PCI_DEVICE_ID_QLOGIC_VF_QLE844X) ||
                   (device == PCI_DEVICE_ID_QLOGIC_VF_QLE834X)) ? true : false;
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
index 476e4998ef99..840bf36b5e9d 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.c
@@ -35,6 +35,35 @@ static void qlcnic_83xx_get_beacon_state(struct qlcnic_adapter *);
 #define QLC_SKIP_INACTIVE_PCI_REGS      7
 #define QLC_MAX_LEGACY_FUNC_SUPP        8
 
+/* 83xx Module type */
+#define QLC_83XX_MODULE_FIBRE_10GBASE_LRM       0x1 /* 10GBase-LRM */
+#define QLC_83XX_MODULE_FIBRE_10GBASE_LR        0x2 /* 10GBase-LR */
+#define QLC_83XX_MODULE_FIBRE_10GBASE_SR        0x3 /* 10GBase-SR */
+#define QLC_83XX_MODULE_DA_10GE_PASSIVE_CP      0x4 /* 10GE passive
+                                                     * copper(compliant)
+                                                     */
+#define QLC_83XX_MODULE_DA_10GE_ACTIVE_CP       0x5 /* 10GE active limiting
+                                                     * copper(compliant)
+                                                     */
+#define QLC_83XX_MODULE_DA_10GE_LEGACY_CP       0x6 /* 10GE passive copper
+                                                     * (legacy, best effort)
+                                                     */
+#define QLC_83XX_MODULE_FIBRE_1000BASE_SX       0x7 /* 1000Base-SX */
+#define QLC_83XX_MODULE_FIBRE_1000BASE_LX       0x8 /* 1000Base-LX */
+#define QLC_83XX_MODULE_FIBRE_1000BASE_CX       0x9 /* 1000Base-CX */
+#define QLC_83XX_MODULE_TP_1000BASE_T           0xa /* 1000Base-T*/
+#define QLC_83XX_MODULE_DA_1GE_PASSIVE_CP       0xb /* 1GE passive copper
+                                                     * (legacy, best effort)
+                                                     */
+#define QLC_83XX_MODULE_UNKNOWN                 0xf /* Unknown module type */
+
+/* Port types */
+#define QLC_83XX_10_CAPABLE      BIT_8
+#define QLC_83XX_100_CAPABLE     BIT_9
+#define QLC_83XX_1G_CAPABLE      BIT_10
+#define QLC_83XX_10G_CAPABLE     BIT_11
+#define QLC_83XX_AUTONEG_ENABLE  BIT_15
+
 static const struct qlcnic_mailbox_metadata qlcnic_83xx_mbx_tbl[] = {
         {QLCNIC_CMD_CONFIGURE_IP_ADDR, 6, 1},
         {QLCNIC_CMD_CONFIG_INTRPT, 18, 34},
@@ -667,6 +696,7 @@ void qlcnic_83xx_write_crb(struct qlcnic_adapter *adapter, char *buf,
 
 int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
 {
+        struct qlcnic_hardware_context *ahw = adapter->ahw;
         int status;
 
         status = qlcnic_83xx_get_port_config(adapter);
@@ -674,13 +704,20 @@ int qlcnic_83xx_get_port_info(struct qlcnic_adapter *adapter)
                 dev_err(&adapter->pdev->dev,
                         "Get Port Info failed\n");
         } else {
-                if (QLC_83XX_SFP_10G_CAPABLE(adapter->ahw->port_config))
-                        adapter->ahw->port_type = QLCNIC_XGBE;
-                else
-                        adapter->ahw->port_type = QLCNIC_GBE;
 
-                if (QLC_83XX_AUTONEG(adapter->ahw->port_config))
-                        adapter->ahw->link_autoneg = AUTONEG_ENABLE;
+                if (ahw->port_config & QLC_83XX_10G_CAPABLE) {
+                        ahw->port_type = QLCNIC_XGBE;
+                } else if (ahw->port_config & QLC_83XX_10_CAPABLE ||
+                           ahw->port_config & QLC_83XX_100_CAPABLE ||
+                           ahw->port_config & QLC_83XX_1G_CAPABLE) {
+                        ahw->port_type = QLCNIC_GBE;
+                } else {
+                        ahw->port_type = QLCNIC_XGBE;
+                }
+
+                if (QLC_83XX_AUTONEG(ahw->port_config))
+                        ahw->link_autoneg = AUTONEG_ENABLE;
+
         }
         return status;
 }
@@ -2664,7 +2701,7 @@ static int qlcnic_83xx_poll_flash_status_reg(struct qlcnic_adapter *adapter)
                     QLC_83XX_FLASH_STATUS_READY)
                         break;
 
-                msleep(QLC_83XX_FLASH_STATUS_REG_POLL_DELAY);
+                usleep_range(1000, 1100);
         } while (--retries);
 
         if (!retries)
@@ -3176,22 +3213,33 @@ int qlcnic_83xx_test_link(struct qlcnic_adapter *adapter)
                         break;
                 }
                 config = cmd.rsp.arg[3];
-                if (QLC_83XX_SFP_PRESENT(config)) {
-                        switch (ahw->module_type) {
-                        case LINKEVENT_MODULE_OPTICAL_UNKNOWN:
-                        case LINKEVENT_MODULE_OPTICAL_SRLR:
-                        case LINKEVENT_MODULE_OPTICAL_LRM:
-                        case LINKEVENT_MODULE_OPTICAL_SFP_1G:
-                                ahw->supported_type = PORT_FIBRE;
-                                break;
-                        case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLE:
-                        case LINKEVENT_MODULE_TWINAX_UNSUPPORTED_CABLELEN:
-                        case LINKEVENT_MODULE_TWINAX:
-                                ahw->supported_type = PORT_TP;
-                                break;
-                        default:
-                                ahw->supported_type = PORT_OTHER;
-                        }
+                switch (QLC_83XX_SFP_MODULE_TYPE(config)) {
+                case QLC_83XX_MODULE_FIBRE_10GBASE_LRM:
+                case QLC_83XX_MODULE_FIBRE_10GBASE_LR:
+                case QLC_83XX_MODULE_FIBRE_10GBASE_SR:
+                        ahw->supported_type = PORT_FIBRE;
+                        ahw->port_type = QLCNIC_XGBE;
+                        break;
+                case QLC_83XX_MODULE_FIBRE_1000BASE_SX:
+                case QLC_83XX_MODULE_FIBRE_1000BASE_LX:
+                case QLC_83XX_MODULE_FIBRE_1000BASE_CX:
+                        ahw->supported_type = PORT_FIBRE;
+                        ahw->port_type = QLCNIC_GBE;
+                        break;
+                case QLC_83XX_MODULE_TP_1000BASE_T:
+                        ahw->supported_type = PORT_TP;
+                        ahw->port_type = QLCNIC_GBE;
+                        break;
+                case QLC_83XX_MODULE_DA_10GE_PASSIVE_CP:
+                case QLC_83XX_MODULE_DA_10GE_ACTIVE_CP:
+                case QLC_83XX_MODULE_DA_10GE_LEGACY_CP:
+                case QLC_83XX_MODULE_DA_1GE_PASSIVE_CP:
+                        ahw->supported_type = PORT_DA;
+                        ahw->port_type = QLCNIC_XGBE;
+                        break;
+                default:
+                        ahw->supported_type = PORT_OTHER;
+                        ahw->port_type = QLCNIC_XGBE;
                 }
                 if (config & 1)
                         err = 1;
@@ -3204,9 +3252,9 @@ out:
 int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
                              struct ethtool_cmd *ecmd)
 {
+        struct qlcnic_hardware_context *ahw = adapter->ahw;
         u32 config = 0;
         int status = 0;
-        struct qlcnic_hardware_context *ahw = adapter->ahw;
 
         if (!test_bit(__QLCNIC_MAINTENANCE_MODE, &adapter->state)) {
                 /* Get port configuration info */
@@ -3229,20 +3277,41 @@ int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
                 ecmd->autoneg = AUTONEG_DISABLE;
         }
 
-        if (ahw->port_type == QLCNIC_XGBE) {
-                ecmd->supported = SUPPORTED_10000baseT_Full;
-                ecmd->advertising = ADVERTISED_10000baseT_Full;
+        ecmd->supported = (SUPPORTED_10baseT_Full |
+                           SUPPORTED_100baseT_Full |
+                           SUPPORTED_1000baseT_Full |
+                           SUPPORTED_10000baseT_Full |
+                           SUPPORTED_Autoneg);
+
+        if (ecmd->autoneg == AUTONEG_ENABLE) {
+                if (ahw->port_config & QLC_83XX_10_CAPABLE)
+                        ecmd->advertising |= SUPPORTED_10baseT_Full;
+                if (ahw->port_config & QLC_83XX_100_CAPABLE)
+                        ecmd->advertising |= SUPPORTED_100baseT_Full;
+                if (ahw->port_config & QLC_83XX_1G_CAPABLE)
+                        ecmd->advertising |= SUPPORTED_1000baseT_Full;
+                if (ahw->port_config & QLC_83XX_10G_CAPABLE)
+                        ecmd->advertising |= SUPPORTED_10000baseT_Full;
+                if (ahw->port_config & QLC_83XX_AUTONEG_ENABLE)
+                        ecmd->advertising |= ADVERTISED_Autoneg;
         } else {
-                ecmd->supported = (SUPPORTED_10baseT_Half |
-                                   SUPPORTED_10baseT_Full |
-                                   SUPPORTED_100baseT_Half |
-                                   SUPPORTED_100baseT_Full |
-                                   SUPPORTED_1000baseT_Half |
-                                   SUPPORTED_1000baseT_Full);
-                ecmd->advertising = (ADVERTISED_100baseT_Half |
-                                     ADVERTISED_100baseT_Full |
-                                     ADVERTISED_1000baseT_Half |
-                                     ADVERTISED_1000baseT_Full);
+                switch (ahw->link_speed) {
+                case SPEED_10:
+                        ecmd->advertising = SUPPORTED_10baseT_Full;
+                        break;
+                case SPEED_100:
+                        ecmd->advertising = SUPPORTED_100baseT_Full;
+                        break;
+                case SPEED_1000:
+                        ecmd->advertising = SUPPORTED_1000baseT_Full;
+                        break;
+                case SPEED_10000:
+                        ecmd->advertising = SUPPORTED_10000baseT_Full;
+                        break;
+                default:
+                        break;
+                }
+
         }
 
         switch (ahw->supported_type) {
@@ -3258,6 +3327,12 @@ int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
                 ecmd->port = PORT_TP;
                 ecmd->transceiver = XCVR_INTERNAL;
                 break;
+        case PORT_DA:
+                ecmd->supported |= SUPPORTED_FIBRE;
+                ecmd->advertising |= ADVERTISED_FIBRE;
+                ecmd->port = PORT_DA;
+                ecmd->transceiver = XCVR_EXTERNAL;
+                break;
         default:
                 ecmd->supported |= SUPPORTED_FIBRE;
                 ecmd->advertising |= ADVERTISED_FIBRE;
@@ -3272,35 +3347,60 @@ int qlcnic_83xx_get_settings(struct qlcnic_adapter *adapter,
 int qlcnic_83xx_set_settings(struct qlcnic_adapter *adapter,
                              struct ethtool_cmd *ecmd)
 {
-        int status = 0;
+        struct qlcnic_hardware_context *ahw = adapter->ahw;
         u32 config = adapter->ahw->port_config;
+        int status = 0;
 
-        if (ecmd->autoneg)
-                adapter->ahw->port_config |= BIT_15;
-
-        switch (ethtool_cmd_speed(ecmd)) {
-        case SPEED_10:
-                adapter->ahw->port_config |= BIT_8;
-                break;
-        case SPEED_100:
-                adapter->ahw->port_config |= BIT_9;
-                break;
-        case SPEED_1000:
-                adapter->ahw->port_config |= BIT_10;
-                break;
-        case SPEED_10000:
-                adapter->ahw->port_config |= BIT_11;
-                break;
-        default:
-                return -EINVAL;
+        /* 83xx devices do not support Half duplex */
+        if (ecmd->duplex == DUPLEX_HALF) {
+                        netdev_info(adapter->netdev,
+                                    "Half duplex mode not supported\n");
+                        return -EINVAL;
         }
 
+        if (ecmd->autoneg) {
+                ahw->port_config |= QLC_83XX_AUTONEG_ENABLE;
+                ahw->port_config |= (QLC_83XX_100_CAPABLE |
+                                     QLC_83XX_1G_CAPABLE |
+                                     QLC_83XX_10G_CAPABLE);
+        } else { /* force speed */
+                ahw->port_config &= ~QLC_83XX_AUTONEG_ENABLE;
+                switch (ethtool_cmd_speed(ecmd)) {
+                case SPEED_10:
+                        ahw->port_config &= ~(QLC_83XX_100_CAPABLE |
+                                              QLC_83XX_1G_CAPABLE |
+                                              QLC_83XX_10G_CAPABLE);
+                        ahw->port_config |= QLC_83XX_10_CAPABLE;
+                        break;
+                case SPEED_100:
+                        ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
+                                              QLC_83XX_1G_CAPABLE |
+                                              QLC_83XX_10G_CAPABLE);
+                        ahw->port_config |= QLC_83XX_100_CAPABLE;
+                        break;
+                case SPEED_1000:
+                        ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
+                                              QLC_83XX_100_CAPABLE |
+                                              QLC_83XX_10G_CAPABLE);
+                        ahw->port_config |= QLC_83XX_1G_CAPABLE;
+                        break;
+                case SPEED_10000:
+                        ahw->port_config &= ~(QLC_83XX_10_CAPABLE |
+                                              QLC_83XX_100_CAPABLE |
+                                              QLC_83XX_1G_CAPABLE);
+                        ahw->port_config |= QLC_83XX_10G_CAPABLE;
+                        break;
+                default:
+                        return -EINVAL;
+                }
+        }
         status = qlcnic_83xx_set_port_config(adapter);
         if (status) {
-                dev_info(&adapter->pdev->dev,
-                         "Failed to Set Link Speed and autoneg.\n");
-                adapter->ahw->port_config = config;
+                netdev_info(adapter->netdev,
+                            "Failed to Set Link Speed and autoneg.\n");
+                ahw->port_config = config;
         }
+
         return status;
 }
 
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h
index 2bf101a47d02..f3346a3779d3 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_hw.h
@@ -83,6 +83,7 @@
 /* Firmware image definitions */
 #define QLC_83XX_BOOTLOADER_FLASH_ADDR  0x10000
 #define QLC_83XX_FW_FILE_NAME           "83xx_fw.bin"
+#define QLC_83XX_POST_FW_FILE_NAME      "83xx_post_fw.bin"
 #define QLC_84XX_FW_FILE_NAME           "84xx_fw.bin"
 #define QLC_83XX_BOOT_FROM_FLASH        0
 #define QLC_83XX_BOOT_FROM_FILE         0x12345678
@@ -360,7 +361,6 @@ enum qlcnic_83xx_states {
 #define QLC_83XX_SFP_MODULE_TYPE(data)          (((data) >> 4) & 0x1F)
 #define QLC_83XX_SFP_CU_LENGTH(data)            (LSB((data) >> 16))
 #define QLC_83XX_SFP_TX_FAULT(data)             ((data) & BIT_10)
-#define QLC_83XX_SFP_10G_CAPABLE(data)          ((data) & BIT_11)
 #define QLC_83XX_LINK_STATS(data)               ((data) & BIT_0)
 #define QLC_83XX_CURRENT_LINK_SPEED(data)       (((data) >> 3) & 7)
 #define QLC_83XX_LINK_PAUSE(data)               (((data) >> 6) & 3)
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
index 86783e1afcf7..9a2cfe4efac6 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c
@@ -2075,6 +2075,121 @@ static void qlcnic_83xx_init_hw(struct qlcnic_adapter *p_dev)
                 dev_err(&p_dev->pdev->dev, "%s: failed\n", __func__);
 }
 
+/* POST FW related definations*/
+#define QLC_83XX_POST_SIGNATURE_REG     0x41602014
+#define QLC_83XX_POST_MODE_REG          0x41602018
+#define QLC_83XX_POST_FAST_MODE         0
+#define QLC_83XX_POST_MEDIUM_MODE       1
+#define QLC_83XX_POST_SLOW_MODE         2
+
+/* POST Timeout values in milliseconds */
+#define QLC_83XX_POST_FAST_MODE_TIMEOUT 690
+#define QLC_83XX_POST_MED_MODE_TIMEOUT  2930
+#define QLC_83XX_POST_SLOW_MODE_TIMEOUT 7500
+
+/* POST result values */
+#define QLC_83XX_POST_PASS                      0xfffffff0
+#define QLC_83XX_POST_ASIC_STRESS_TEST_FAIL     0xffffffff
+#define QLC_83XX_POST_DDR_TEST_FAIL             0xfffffffe
+#define QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL     0xfffffffc
+#define QLC_83XX_POST_FLASH_TEST_FAIL           0xfffffff8
+
+static int qlcnic_83xx_run_post(struct qlcnic_adapter *adapter)
+{
+        struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
+        struct device *dev = &adapter->pdev->dev;
+        int timeout, count, ret = 0;
+        u32 signature;
+
+        /* Set timeout values with extra 2 seconds of buffer */
+        switch (adapter->ahw->post_mode) {
+        case QLC_83XX_POST_FAST_MODE:
+                timeout = QLC_83XX_POST_FAST_MODE_TIMEOUT + 2000;
+                break;
+        case QLC_83XX_POST_MEDIUM_MODE:
+                timeout = QLC_83XX_POST_MED_MODE_TIMEOUT + 2000;
+                break;
+        case QLC_83XX_POST_SLOW_MODE:
+                timeout = QLC_83XX_POST_SLOW_MODE_TIMEOUT + 2000;
+                break;
+        default:
+                return -EINVAL;
+        }
+
+        strncpy(fw_info->fw_file_name, QLC_83XX_POST_FW_FILE_NAME,
+                QLC_FW_FILE_NAME_LEN);
+
+        ret = request_firmware(&fw_info->fw, fw_info->fw_file_name, dev);
+        if (ret) {
+                dev_err(dev, "POST firmware can not be loaded, skipping POST\n");
+                return 0;
+        }
+
+        ret = qlcnic_83xx_copy_fw_file(adapter);
+        if (ret)
+                return ret;
+
+        /* clear QLC_83XX_POST_SIGNATURE_REG register */
+        qlcnic_ind_wr(adapter, QLC_83XX_POST_SIGNATURE_REG, 0);
+
+        /* Set POST mode */
+        qlcnic_ind_wr(adapter, QLC_83XX_POST_MODE_REG,
+                      adapter->ahw->post_mode);
+
+        QLC_SHARED_REG_WR32(adapter, QLCNIC_FW_IMG_VALID,
+                            QLC_83XX_BOOT_FROM_FILE);
+
+        qlcnic_83xx_start_hw(adapter);
+
+        count = 0;
+        do {
+                msleep(100);
+                count += 100;
+
+                signature = qlcnic_ind_rd(adapter, QLC_83XX_POST_SIGNATURE_REG);
+                if (signature == QLC_83XX_POST_PASS)
+                        break;
+        } while (timeout > count);
+
+        if (timeout <= count) {
+                dev_err(dev, "POST timed out, signature = 0x%08x\n", signature);
+                return -EIO;
+        }
+
+        switch (signature) {
+        case QLC_83XX_POST_PASS:
+                dev_info(dev, "POST passed, Signature = 0x%08x\n", signature);
+                break;
+        case QLC_83XX_POST_ASIC_STRESS_TEST_FAIL:
+                dev_err(dev, "POST failed, Test case : ASIC STRESS TEST, Signature = 0x%08x\n",
+                        signature);
+                ret = -EIO;
+                break;
+        case QLC_83XX_POST_DDR_TEST_FAIL:
+                dev_err(dev, "POST failed, Test case : DDT TEST, Signature = 0x%08x\n",
+                        signature);
+                ret = -EIO;
+                break;
+        case QLC_83XX_POST_ASIC_MEMORY_TEST_FAIL:
+                dev_err(dev, "POST failed, Test case : ASIC MEMORY TEST, Signature = 0x%08x\n",
+                        signature);
+                ret = -EIO;
+                break;
+        case QLC_83XX_POST_FLASH_TEST_FAIL:
+                dev_err(dev, "POST failed, Test case : FLASH TEST, Signature = 0x%08x\n",
+                        signature);
+                ret = -EIO;
+                break;
+        default:
+                dev_err(dev, "POST failed, Test case : INVALID, Signature = 0x%08x\n",
+                        signature);
+                ret = -EIO;
+                break;
+        }
+
+        return ret;
+}
+
 static int qlcnic_83xx_load_fw_image_from_host(struct qlcnic_adapter *adapter)
 {
         struct qlc_83xx_fw_info *fw_info = adapter->ahw->fw_info;
@@ -2119,8 +2234,27 @@ static int qlcnic_83xx_restart_hw(struct qlcnic_adapter *adapter)
 
         if (qlcnic_83xx_copy_bootloader(adapter))
                 return err;
+
+        /* Check if POST needs to be run */
+        if (adapter->ahw->run_post) {
+                err = qlcnic_83xx_run_post(adapter);
+                if (err)
+                        return err;
+
+                /* No need to run POST in next reset sequence */
+                adapter->ahw->run_post = false;
+
+                /* Again reset the adapter to load regular firmware  */
+                qlcnic_83xx_stop_hw(adapter);
+                qlcnic_83xx_init_hw(adapter);
+
+                err = qlcnic_83xx_copy_bootloader(adapter);
+                if (err)
+                        return err;
+        }
+
         /* Boot either flash image or firmware image from host file system */
-        if (qlcnic_load_fw_file) {
+        if (qlcnic_load_fw_file == 1) {
                 if (qlcnic_83xx_load_fw_image_from_host(adapter))
                         return err;
         } else {
@@ -2284,6 +2418,7 @@ static int qlcnic_83xx_get_fw_info(struct qlcnic_adapter *adapter)
                 fw_info = ahw->fw_info;
                 switch (pdev->device) {
                 case PCI_DEVICE_ID_QLOGIC_QLE834X:
+                case PCI_DEVICE_ID_QLOGIC_QLE8830:
                         strncpy(fw_info->fw_file_name, QLC_83XX_FW_FILE_NAME,
                                 QLC_FW_FILE_NAME_LEN);
                         break;
@@ -2328,6 +2463,25 @@ int qlcnic_83xx_init(struct qlcnic_adapter *adapter, int pci_using_dac)
         adapter->rx_mac_learn = false;
         ahw->msix_supported = !!qlcnic_use_msi_x;
 
+        /* Check if POST needs to be run */
+        switch (qlcnic_load_fw_file) {
+        case 2:
+                ahw->post_mode = QLC_83XX_POST_FAST_MODE;
+                ahw->run_post = true;
+                break;
+        case 3:
+                ahw->post_mode = QLC_83XX_POST_MEDIUM_MODE;
+                ahw->run_post = true;
+                break;
+        case 4:
+                ahw->post_mode = QLC_83XX_POST_SLOW_MODE;
+                ahw->run_post = true;
+                break;
+        default:
+                ahw->run_post = false;
+                break;
+        }
+
         qlcnic_83xx_init_rings(adapter);
 
         err = qlcnic_83xx_init_mailbox_work(adapter);
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
index 851cb4a80d50..8102673cb37f 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
@@ -341,7 +341,7 @@ qlcnic_pcie_sem_lock(struct qlcnic_adapter *adapter, int sem, u32 id_reg)
                         }
                         return -EIO;
                 }
-                msleep(1);
+                usleep_range(1000, 1500);
         }
 
         if (id_reg)
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
index c4262c23ed7c..be41e4c77b65 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
@@ -537,7 +537,7 @@ int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
         QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0xc, 0);
         QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x8, 0);
         QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0xc, 0);
-        msleep(1);
+        usleep_range(1000, 1500);
 
         QLC_SHARED_REG_WR32(adapter, QLCNIC_PEG_HALT_STATUS1, 0);
         QLC_SHARED_REG_WR32(adapter, QLCNIC_PEG_HALT_STATUS2, 0);
@@ -1198,7 +1198,7 @@ qlcnic_load_firmware(struct qlcnic_adapter *adapter)
                         flashaddr += 8;
                 }
         }
-        msleep(1);
+        usleep_range(1000, 1500);
 
         QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x18, 0x1020);
         QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0x80001e);
@@ -1295,7 +1295,7 @@ next:
                 rc = qlcnic_validate_firmware(adapter);
                 if (rc != 0) {
                         release_firmware(adapter->fw);
-                        msleep(1);
+                        usleep_range(1000, 1500);
                         goto next;
                 }
         }
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
index e45bf09af0c9..18e5de72e9b4 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_io.c
@@ -1753,7 +1753,7 @@ qlcnic_83xx_process_rcv(struct qlcnic_adapter *adapter,
 
         if (qlcnic_encap_length(sts_data[1]) &&
             skb->ip_summed == CHECKSUM_UNNECESSARY) {
-                skb->encapsulation = 1;
+                skb->csum_level = 1;
                 adapter->stats.encap_rx_csummed++;
         }
 
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
index cf08b2de071e..f5e29f7bdae3 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
@@ -52,7 +52,7 @@ MODULE_PARM_DESC(auto_fw_reset, "Auto firmware reset (0=disabled, 1=enabled)");
 module_param_named(auto_fw_reset, qlcnic_auto_fw_reset, int, 0644);
 
 int qlcnic_load_fw_file;
-MODULE_PARM_DESC(load_fw_file, "Load firmware from (0=flash, 1=file)");
+MODULE_PARM_DESC(load_fw_file, "Load firmware from (0=flash, 1=file, 2=POST in fast mode, 3= POST in medium mode, 4=POST in slow mode)");
 module_param_named(load_fw_file, qlcnic_load_fw_file, int, 0444);
 
 static int qlcnic_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
@@ -111,6 +111,7 @@ static u32 qlcnic_vlan_tx_check(struct qlcnic_adapter *adapter)
 static const struct pci_device_id qlcnic_pci_tbl[] = {
         ENTRY(PCI_DEVICE_ID_QLOGIC_QLE824X),
         ENTRY(PCI_DEVICE_ID_QLOGIC_QLE834X),
+        ENTRY(PCI_DEVICE_ID_QLOGIC_QLE8830),
         ENTRY(PCI_DEVICE_ID_QLOGIC_VF_QLE834X),
         ENTRY(PCI_DEVICE_ID_QLOGIC_QLE844X),
         ENTRY(PCI_DEVICE_ID_QLOGIC_VF_QLE844X),
@@ -228,6 +229,11 @@ static const struct qlcnic_board_info qlcnic_boards[] = {
           PCI_DEVICE_ID_QLOGIC_QLE834X,
           0x0, 0x0, "8300 Series 1/10GbE Controller" },
         { PCI_VENDOR_ID_QLOGIC,
+          PCI_DEVICE_ID_QLOGIC_QLE8830,
+          0x0,
+          0x0,
+          "8830 Series 1/10GbE Controller" },
+        { PCI_VENDOR_ID_QLOGIC,
           PCI_DEVICE_ID_QLOGIC_QLE824X,
           PCI_VENDOR_ID_QLOGIC,
           0x203,
@@ -1131,6 +1137,7 @@ static void qlcnic_get_bar_length(u32 dev_id, ulong *bar)
                 *bar = QLCNIC_82XX_BAR0_LENGTH;
                 break;
         case PCI_DEVICE_ID_QLOGIC_QLE834X:
+        case PCI_DEVICE_ID_QLOGIC_QLE8830:
         case PCI_DEVICE_ID_QLOGIC_QLE844X:
         case PCI_DEVICE_ID_QLOGIC_VF_QLE834X:
         case PCI_DEVICE_ID_QLOGIC_VF_QLE844X:
@@ -2474,6 +2481,7 @@ qlcnic_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
                 ahw->reg_tbl = (u32 *) qlcnic_reg_tbl;
                 break;
         case PCI_DEVICE_ID_QLOGIC_QLE834X:
+        case PCI_DEVICE_ID_QLOGIC_QLE8830:
         case PCI_DEVICE_ID_QLOGIC_QLE844X:
                 qlcnic_83xx_register_map(ahw);
                 break;
diff --git a/drivers/net/ethernet/realtek/r8169.c b/drivers/net/ethernet/realtek/r8169.c
index 91652e7235e4..02dd92ac1764 100644
--- a/drivers/net/ethernet/realtek/r8169.c
+++ b/drivers/net/ethernet/realtek/r8169.c
@@ -52,6 +52,10 @@
 #define FIRMWARE_8106E_2        "rtl_nic/rtl8106e-2.fw"
 #define FIRMWARE_8168G_2        "rtl_nic/rtl8168g-2.fw"
 #define FIRMWARE_8168G_3        "rtl_nic/rtl8168g-3.fw"
+#define FIRMWARE_8168H_1        "rtl_nic/rtl8168h-1.fw"
+#define FIRMWARE_8168H_2        "rtl_nic/rtl8168h-2.fw"
+#define FIRMWARE_8107E_1        "rtl_nic/rtl8107e-1.fw"
+#define FIRMWARE_8107E_2        "rtl_nic/rtl8107e-2.fw"
 
 #ifdef RTL8169_DEBUG
 #define assert(expr) \
@@ -147,6 +151,10 @@ enum mac_version {
         RTL_GIGA_MAC_VER_42,
         RTL_GIGA_MAC_VER_43,
         RTL_GIGA_MAC_VER_44,
+        RTL_GIGA_MAC_VER_45,
+        RTL_GIGA_MAC_VER_46,
+        RTL_GIGA_MAC_VER_47,
+        RTL_GIGA_MAC_VER_48,
         RTL_GIGA_MAC_NONE   = 0xff,
 };
 
@@ -282,6 +290,18 @@ static const struct {
         [RTL_GIGA_MAC_VER_44] =
                 _R("RTL8411",           RTL_TD_1, FIRMWARE_8411_2,
                                                         JUMBO_9K, false),
+        [RTL_GIGA_MAC_VER_45] =
+                _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_1,
+                                                        JUMBO_9K, false),
+        [RTL_GIGA_MAC_VER_46] =
+                _R("RTL8168h/8111h",    RTL_TD_1, FIRMWARE_8168H_2,
+                                                        JUMBO_9K, false),
+        [RTL_GIGA_MAC_VER_47] =
+                _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_1,
+                                                        JUMBO_1K, false),
+        [RTL_GIGA_MAC_VER_48] =
+                _R("RTL8107e",          RTL_TD_1, FIRMWARE_8107E_2,
+                                                        JUMBO_1K, false),
 };
 #undef _R
 
@@ -410,6 +430,7 @@ enum rtl8168_8101_registers {
 #define EPHYAR_DATA_MASK                0xffff
         DLLPR                   = 0xd0,
 #define PFM_EN                          (1 << 6)
+#define TX_10M_PS_EN                    (1 << 7)
         DBG_REG                 = 0xd1,
 #define FIX_NAK_1                       (1 << 4)
 #define FIX_NAK_2                       (1 << 3)
@@ -429,6 +450,8 @@ enum rtl8168_8101_registers {
 #define EFUSEAR_REG_MASK                0x03ff
 #define EFUSEAR_REG_SHIFT               8
 #define EFUSEAR_DATA_MASK               0xff
+        MISC_1                  = 0xf2,
+#define PFM_D3COLD_EN                   (1 << 6)
 };
 
 enum rtl8168_registers {
@@ -447,6 +470,7 @@ enum rtl8168_registers {
 #define ERIAR_MASK_SHIFT                12
 #define ERIAR_MASK_0001                 (0x1 << ERIAR_MASK_SHIFT)
 #define ERIAR_MASK_0011                 (0x3 << ERIAR_MASK_SHIFT)
+#define ERIAR_MASK_0100                 (0x4 << ERIAR_MASK_SHIFT)
 #define ERIAR_MASK_0101                 (0x5 << ERIAR_MASK_SHIFT)
 #define ERIAR_MASK_1111                 (0xf << ERIAR_MASK_SHIFT)
         EPHY_RXER_NUM           = 0x7c,
@@ -598,6 +622,9 @@ enum rtl_register_content {
 
         /* DumpCounterCommand */
         CounterDump     = 0x8,
+
+        /* magic enable v2 */
+        MagicPacket_v2  = (1 << 16),    /* Wake up when receives a Magic Packet */
 };
 
 enum rtl_desc_bit {
@@ -823,6 +850,10 @@ MODULE_FIRMWARE(FIRMWARE_8106E_1);
 MODULE_FIRMWARE(FIRMWARE_8106E_2);
 MODULE_FIRMWARE(FIRMWARE_8168G_2);
 MODULE_FIRMWARE(FIRMWARE_8168G_3);
+MODULE_FIRMWARE(FIRMWARE_8168H_1);
+MODULE_FIRMWARE(FIRMWARE_8168H_2);
+MODULE_FIRMWARE(FIRMWARE_8107E_1);
+MODULE_FIRMWARE(FIRMWARE_8107E_2);
 
 static void rtl_lock_work(struct rtl8169_private *tp)
 {
@@ -1514,8 +1545,17 @@ static u32 __rtl8169_get_wol(struct rtl8169_private *tp)
         options = RTL_R8(Config3);
         if (options & LinkUp)
                 wolopts |= WAKE_PHY;
-        if (options & MagicPacket)
-                wolopts |= WAKE_MAGIC;
+        switch (tp->mac_version) {
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+                if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
+                        wolopts |= WAKE_MAGIC;
+                break;
+        default:
+                if (options & MagicPacket)
+                        wolopts |= WAKE_MAGIC;
+                break;
+        }
 
         options = RTL_R8(Config5);
         if (options & UWF)
@@ -1543,24 +1583,48 @@ static void rtl8169_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
 static void __rtl8169_set_wol(struct rtl8169_private *tp, u32 wolopts)
 {
         void __iomem *ioaddr = tp->mmio_addr;
-        unsigned int i;
+        unsigned int i, tmp;
         static const struct {
                 u32 opt;
                 u16 reg;
                 u8  mask;
         } cfg[] = {
                 { WAKE_PHY,   Config3, LinkUp },
-                { WAKE_MAGIC, Config3, MagicPacket },
                 { WAKE_UCAST, Config5, UWF },
                 { WAKE_BCAST, Config5, BWF },
                 { WAKE_MCAST, Config5, MWF },
-                { WAKE_ANY,   Config5, LanWake }
+                { WAKE_ANY,   Config5, LanWake },
+                { WAKE_MAGIC, Config3, MagicPacket }
         };
         u8 options;
 
         RTL_W8(Cfg9346, Cfg9346_Unlock);
 
-        for (i = 0; i < ARRAY_SIZE(cfg); i++) {
+        switch (tp->mac_version) {
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+                tmp = ARRAY_SIZE(cfg) - 1;
+                if (wolopts & WAKE_MAGIC)
+                        rtl_w1w0_eri(tp,
+                                     0x0dc,
+                                     ERIAR_MASK_0100,
+                                     MagicPacket_v2,
+                                     0x0000,
+                                     ERIAR_EXGMAC);
+                else
+                        rtl_w1w0_eri(tp,
+                                     0x0dc,
+                                     ERIAR_MASK_0100,
+                                     0x0000,
+                                     MagicPacket_v2,
+                                     ERIAR_EXGMAC);
+                break;
+        default:
+                tmp = ARRAY_SIZE(cfg);
+                break;
+        }
+
+        for (i = 0; i < tmp; i++) {
                 options = RTL_R8(cfg[i].reg) & ~cfg[i].mask;
                 if (wolopts & cfg[i].opt)
                         options |= cfg[i].mask;
@@ -2044,6 +2108,10 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
                 u32 val;
                 int mac_version;
         } mac_info[] = {
+                /* 8168H family. */
+                { 0x7cf00000, 0x54100000,       RTL_GIGA_MAC_VER_46 },
+                { 0x7cf00000, 0x54000000,       RTL_GIGA_MAC_VER_45 },
+
                 /* 8168G family. */
                 { 0x7cf00000, 0x5c800000,       RTL_GIGA_MAC_VER_44 },
                 { 0x7cf00000, 0x50900000,       RTL_GIGA_MAC_VER_42 },
@@ -2139,6 +2207,14 @@ static void rtl8169_get_mac_version(struct rtl8169_private *tp,
                 tp->mac_version = tp->mii.supports_gmii ?
                                   RTL_GIGA_MAC_VER_42 :
                                   RTL_GIGA_MAC_VER_43;
+        } else if (tp->mac_version == RTL_GIGA_MAC_VER_45) {
+                tp->mac_version = tp->mii.supports_gmii ?
+                                  RTL_GIGA_MAC_VER_45 :
+                                  RTL_GIGA_MAC_VER_47;
+        } else if (tp->mac_version == RTL_GIGA_MAC_VER_46) {
+                tp->mac_version = tp->mii.supports_gmii ?
+                                  RTL_GIGA_MAC_VER_46 :
+                                  RTL_GIGA_MAC_VER_48;
         }
 }
 
@@ -3464,6 +3540,189 @@ static void rtl8168g_2_hw_phy_config(struct rtl8169_private *tp)
         rtl_apply_firmware(tp);
 }
 
+static void rtl8168h_1_hw_phy_config(struct rtl8169_private *tp)
+{
+        u16 dout_tapbin;
+        u32 data;
+
+        rtl_apply_firmware(tp);
+
+        /* CHN EST parameters adjust - giga master */
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x809b);
+        rtl_w1w0_phy(tp, 0x14, 0x8000, 0xf800);
+        rtl_writephy(tp, 0x13, 0x80a2);
+        rtl_w1w0_phy(tp, 0x14, 0x8000, 0xff00);
+        rtl_writephy(tp, 0x13, 0x80a4);
+        rtl_w1w0_phy(tp, 0x14, 0x8500, 0xff00);
+        rtl_writephy(tp, 0x13, 0x809c);
+        rtl_w1w0_phy(tp, 0x14, 0xbd00, 0xff00);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* CHN EST parameters adjust - giga slave */
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x80ad);
+        rtl_w1w0_phy(tp, 0x14, 0x7000, 0xf800);
+        rtl_writephy(tp, 0x13, 0x80b4);
+        rtl_w1w0_phy(tp, 0x14, 0x5000, 0xff00);
+        rtl_writephy(tp, 0x13, 0x80ac);
+        rtl_w1w0_phy(tp, 0x14, 0x4000, 0xff00);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* CHN EST parameters adjust - fnet */
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x808e);
+        rtl_w1w0_phy(tp, 0x14, 0x1200, 0xff00);
+        rtl_writephy(tp, 0x13, 0x8090);
+        rtl_w1w0_phy(tp, 0x14, 0xe500, 0xff00);
+        rtl_writephy(tp, 0x13, 0x8092);
+        rtl_w1w0_phy(tp, 0x14, 0x9f00, 0xff00);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* enable R-tune & PGA-retune function */
+        dout_tapbin = 0;
+        rtl_writephy(tp, 0x1f, 0x0a46);
+        data = rtl_readphy(tp, 0x13);
+        data &= 3;
+        data <<= 2;
+        dout_tapbin |= data;
+        data = rtl_readphy(tp, 0x12);
+        data &= 0xc000;
+        data >>= 14;
+        dout_tapbin |= data;
+        dout_tapbin = ~(dout_tapbin^0x08);
+        dout_tapbin <<= 12;
+        dout_tapbin &= 0xf000;
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x827a);
+        rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
+        rtl_writephy(tp, 0x13, 0x827b);
+        rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
+        rtl_writephy(tp, 0x13, 0x827c);
+        rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
+        rtl_writephy(tp, 0x13, 0x827d);
+        rtl_w1w0_phy(tp, 0x14, dout_tapbin, 0xf000);
+
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x0811);
+        rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0a42);
+        rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* enable GPHY 10M */
+        rtl_writephy(tp, 0x1f, 0x0a44);
+        rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* SAR ADC performance */
+        rtl_writephy(tp, 0x1f, 0x0bca);
+        rtl_w1w0_phy(tp, 0x17, 0x4000, 0x3000);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x803f);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
+        rtl_writephy(tp, 0x13, 0x8047);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
+        rtl_writephy(tp, 0x13, 0x804f);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
+        rtl_writephy(tp, 0x13, 0x8057);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
+        rtl_writephy(tp, 0x13, 0x805f);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
+        rtl_writephy(tp, 0x13, 0x8067);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
+        rtl_writephy(tp, 0x13, 0x806f);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x3000);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* disable phy pfm mode */
+        rtl_writephy(tp, 0x1f, 0x0a44);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* Check ALDPS bit, disable it if enabled */
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        if (rtl_readphy(tp, 0x10) & 0x0004)
+                rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
+
+        rtl_writephy(tp, 0x1f, 0x0000);
+}
+
+static void rtl8168h_2_hw_phy_config(struct rtl8169_private *tp)
+{
+        u16 ioffset_p3, ioffset_p2, ioffset_p1, ioffset_p0;
+        u16 rlen;
+        u32 data;
+
+        rtl_apply_firmware(tp);
+
+        /* CHIN EST parameter update */
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x808a);
+        rtl_w1w0_phy(tp, 0x14, 0x000a, 0x003f);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* enable R-tune & PGA-retune function */
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        rtl_writephy(tp, 0x13, 0x0811);
+        rtl_w1w0_phy(tp, 0x14, 0x0800, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0a42);
+        rtl_w1w0_phy(tp, 0x16, 0x0002, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* enable GPHY 10M */
+        rtl_writephy(tp, 0x1f, 0x0a44);
+        rtl_w1w0_phy(tp, 0x11, 0x0800, 0x0000);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        r8168_mac_ocp_write(tp, 0xdd02, 0x807d);
+        data = r8168_mac_ocp_read(tp, 0xdd02);
+        ioffset_p3 = ((data & 0x80)>>7);
+        ioffset_p3 <<= 3;
+
+        data = r8168_mac_ocp_read(tp, 0xdd00);
+        ioffset_p3 |= ((data & (0xe000))>>13);
+        ioffset_p2 = ((data & (0x1e00))>>9);
+        ioffset_p1 = ((data & (0x01e0))>>5);
+        ioffset_p0 = ((data & 0x0010)>>4);
+        ioffset_p0 <<= 3;
+        ioffset_p0 |= (data & (0x07));
+        data = (ioffset_p3<<12)|(ioffset_p2<<8)|(ioffset_p1<<4)|(ioffset_p0);
+
+        if ((ioffset_p3 != 0x0F) || (ioffset_p2 != 0x0F) ||
+            (ioffset_p1 != 0x0F) || (ioffset_p0 == 0x0F)) {
+                rtl_writephy(tp, 0x1f, 0x0bcf);
+                rtl_writephy(tp, 0x16, data);
+                rtl_writephy(tp, 0x1f, 0x0000);
+        }
+
+        /* Modify rlen (TX LPF corner frequency) level */
+        rtl_writephy(tp, 0x1f, 0x0bcd);
+        data = rtl_readphy(tp, 0x16);
+        data &= 0x000f;
+        rlen = 0;
+        if (data > 3)
+                rlen = data - 3;
+        data = rlen | (rlen<<4) | (rlen<<8) | (rlen<<12);
+        rtl_writephy(tp, 0x17, data);
+        rtl_writephy(tp, 0x1f, 0x0bcd);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* disable phy pfm mode */
+        rtl_writephy(tp, 0x1f, 0x0a44);
+        rtl_w1w0_phy(tp, 0x14, 0x0000, 0x0080);
+        rtl_writephy(tp, 0x1f, 0x0000);
+
+        /* Check ALDPS bit, disable it if enabled */
+        rtl_writephy(tp, 0x1f, 0x0a43);
+        if (rtl_readphy(tp, 0x10) & 0x0004)
+                rtl_w1w0_phy(tp, 0x10, 0x0000, 0x0004);
+
+        rtl_writephy(tp, 0x1f, 0x0000);
+}
+
 static void rtl8102e_hw_phy_config(struct rtl8169_private *tp)
 {
         static const struct phy_reg phy_reg_init[] = {
@@ -3654,6 +3913,14 @@ static void rtl_hw_phy_config(struct net_device *dev)
         case RTL_GIGA_MAC_VER_44:
                 rtl8168g_2_hw_phy_config(tp);
                 break;
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_47:
+                rtl8168h_1_hw_phy_config(tp);
+                break;
+        case RTL_GIGA_MAC_VER_46:
+        case RTL_GIGA_MAC_VER_48:
+                rtl8168h_2_hw_phy_config(tp);
+                break;
 
         case RTL_GIGA_MAC_VER_41:
         default:
@@ -3865,6 +4132,10 @@ static void rtl_init_mdio_ops(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_42:
         case RTL_GIGA_MAC_VER_43:
         case RTL_GIGA_MAC_VER_44:
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+        case RTL_GIGA_MAC_VER_47:
+        case RTL_GIGA_MAC_VER_48:
                 ops->write      = r8168g_mdio_write;
                 ops->read       = r8168g_mdio_read;
                 break;
@@ -3919,6 +4190,10 @@ static void rtl_wol_suspend_quirk(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_42:
         case RTL_GIGA_MAC_VER_43:
         case RTL_GIGA_MAC_VER_44:
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+        case RTL_GIGA_MAC_VER_47:
+        case RTL_GIGA_MAC_VER_48:
                 RTL_W32(RxConfig, RTL_R32(RxConfig) |
                         AcceptBroadcast | AcceptMulticast | AcceptMyPhys);
                 break;
@@ -3987,6 +4262,10 @@ static void r810x_pll_power_up(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_13:
         case RTL_GIGA_MAC_VER_16:
                 break;
+        case RTL_GIGA_MAC_VER_47:
+        case RTL_GIGA_MAC_VER_48:
+                RTL_W8(PMCH, RTL_R8(PMCH) | 0xC0);
+                break;
         default:
                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
                 break;
@@ -4087,6 +4366,8 @@ static void r8168_pll_power_down(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_31:
         case RTL_GIGA_MAC_VER_32:
         case RTL_GIGA_MAC_VER_33:
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
                 RTL_W8(PMCH, RTL_R8(PMCH) & ~0x80);
                 break;
         case RTL_GIGA_MAC_VER_40:
@@ -4111,6 +4392,10 @@ static void r8168_pll_power_up(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_33:
                 RTL_W8(PMCH, RTL_R8(PMCH) | 0x80);
                 break;
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+                RTL_W8(PMCH, RTL_R8(PMCH) | 0xC0);
+                break;
         case RTL_GIGA_MAC_VER_40:
         case RTL_GIGA_MAC_VER_41:
                 rtl_w1w0_eri(tp, 0x1a8, ERIAR_MASK_1111, 0xfc000000,
@@ -4153,6 +4438,8 @@ static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_37:
         case RTL_GIGA_MAC_VER_39:
         case RTL_GIGA_MAC_VER_43:
+        case RTL_GIGA_MAC_VER_47:
+        case RTL_GIGA_MAC_VER_48:
                 ops->down       = r810x_pll_power_down;
                 ops->up         = r810x_pll_power_up;
                 break;
@@ -4182,6 +4469,8 @@ static void rtl_init_pll_power_ops(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_41:
         case RTL_GIGA_MAC_VER_42:
         case RTL_GIGA_MAC_VER_44:
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
                 ops->down       = r8168_pll_power_down;
                 ops->up         = r8168_pll_power_up;
                 break;
@@ -4232,6 +4521,10 @@ static void rtl_init_rxcfg(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_42:
         case RTL_GIGA_MAC_VER_43:
         case RTL_GIGA_MAC_VER_44:
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+        case RTL_GIGA_MAC_VER_47:
+        case RTL_GIGA_MAC_VER_48:
                 RTL_W32(RxConfig, RX128_INT_EN | RX_DMA_BURST | RX_EARLY_OFF);
                 break;
         default:
@@ -4393,6 +4686,10 @@ static void rtl_init_jumbo_ops(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_42:
         case RTL_GIGA_MAC_VER_43:
         case RTL_GIGA_MAC_VER_44:
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+        case RTL_GIGA_MAC_VER_47:
+        case RTL_GIGA_MAC_VER_48:
         default:
                 ops->disable    = NULL;
                 ops->enable     = NULL;
@@ -4495,15 +4792,19 @@ static void rtl8169_hw_reset(struct rtl8169_private *tp)
             tp->mac_version == RTL_GIGA_MAC_VER_31) {
                 rtl_udelay_loop_wait_low(tp, &rtl_npq_cond, 20, 42*42);
         } else if (tp->mac_version == RTL_GIGA_MAC_VER_34 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_35 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_36 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_37 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_40 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_41 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_42 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_43 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_44 ||
-                   tp->mac_version == RTL_GIGA_MAC_VER_38) {
+                   tp->mac_version == RTL_GIGA_MAC_VER_35 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_36 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_37 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_38 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_40 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_41 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_42 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_43 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_44 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_45 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_46 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_47 ||
+                   tp->mac_version == RTL_GIGA_MAC_VER_48) {
                 RTL_W8(ChipCmd, RTL_R8(ChipCmd) | StopReq);
                 rtl_udelay_loop_wait_high(tp, &rtl_txcfg_empty_cond, 100, 666);
         } else {
@@ -5330,6 +5631,105 @@ static void rtl_hw_start_8411_2(struct rtl8169_private *tp)
         rtl_ephy_init(tp, e_info_8411_2, ARRAY_SIZE(e_info_8411_2));
 }
 
+static void rtl_hw_start_8168h_1(struct rtl8169_private *tp)
+{
+        void __iomem *ioaddr = tp->mmio_addr;
+        struct pci_dev *pdev = tp->pci_dev;
+        u16 rg_saw_cnt;
+        u32 data;
+        static const struct ephy_info e_info_8168h_1[] = {
+                { 0x1e, 0x0800, 0x0001 },
+                { 0x1d, 0x0000, 0x0800 },
+                { 0x05, 0xffff, 0x2089 },
+                { 0x06, 0xffff, 0x5881 },
+                { 0x04, 0xffff, 0x154a },
+                { 0x01, 0xffff, 0x068b }
+        };
+
+        /* disable aspm and clock request before access ephy */
+        RTL_W8(Config2, RTL_R8(Config2) & ~ClkReqEn);
+        RTL_W8(Config5, RTL_R8(Config5) & ~ASPM_en);
+        rtl_ephy_init(tp, e_info_8168h_1, ARRAY_SIZE(e_info_8168h_1));
+
+        RTL_W32(TxConfig, RTL_R32(TxConfig) | TXCFG_AUTO_FIFO);
+
+        rtl_eri_write(tp, 0xc8, ERIAR_MASK_0101, 0x00080002, ERIAR_EXGMAC);
+        rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, 0x38, ERIAR_EXGMAC);
+        rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, 0x48, ERIAR_EXGMAC);
+        rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, 0x00100006, ERIAR_EXGMAC);
+
+        rtl_csi_access_enable_1(tp);
+
+        rtl_tx_performance_tweak(pdev, 0x5 << MAX_READ_REQUEST_SHIFT);
+
+        rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x00, 0x01, ERIAR_EXGMAC);
+        rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_0001, 0x01, 0x00, ERIAR_EXGMAC);
+
+        rtl_w1w0_eri(tp, 0xdc, ERIAR_MASK_1111, 0x0010, 0x00, ERIAR_EXGMAC);
+
+        rtl_w1w0_eri(tp, 0xd4, ERIAR_MASK_1111, 0x1f00, 0x00, ERIAR_EXGMAC);
+
+        rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87, ERIAR_EXGMAC);
+
+        RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb);
+        RTL_W32(MISC, RTL_R32(MISC) & ~RXDV_GATED_EN);
+        RTL_W8(MaxTxPacketSize, EarlySize);
+
+        rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+        rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000, ERIAR_EXGMAC);
+
+        /* Adjust EEE LED frequency */
+        RTL_W8(EEE_LED, RTL_R8(EEE_LED) & ~0x07);
+
+        RTL_W8(DLLPR, RTL_R8(DLLPR) & ~PFM_EN);
+        RTL_W8(DLLPR, RTL_R8(MISC_1) & ~PFM_D3COLD_EN);
+
+        RTL_W8(DLLPR, RTL_R8(DLLPR) & ~TX_10M_PS_EN);
+
+        rtl_w1w0_eri(tp, 0x1b0, ERIAR_MASK_0011, 0x0000, 0x1000, ERIAR_EXGMAC);
+
+        rtl_pcie_state_l2l3_enable(tp, false);
+
+        rtl_writephy(tp, 0x1f, 0x0c42);
+        rg_saw_cnt = rtl_readphy(tp, 0x13);
+        rtl_writephy(tp, 0x1f, 0x0000);
+        if (rg_saw_cnt > 0) {
+                u16 sw_cnt_1ms_ini;
+
+                sw_cnt_1ms_ini = 16000000/rg_saw_cnt;
+                sw_cnt_1ms_ini &= 0x0fff;
+                data = r8168_mac_ocp_read(tp, 0xd412);
+                data &= 0x0fff;
+                data |= sw_cnt_1ms_ini;
+                r8168_mac_ocp_write(tp, 0xd412, data);
+        }
+
+        data = r8168_mac_ocp_read(tp, 0xe056);
+        data &= 0xf0;
+        data |= 0x07;
+        r8168_mac_ocp_write(tp, 0xe056, data);
+
+        data = r8168_mac_ocp_read(tp, 0xe052);
+        data &= 0x8008;
+        data |= 0x6000;
+        r8168_mac_ocp_write(tp, 0xe052, data);
+
+        data = r8168_mac_ocp_read(tp, 0xe0d6);
+        data &= 0x01ff;
+        data |= 0x017f;
+        r8168_mac_ocp_write(tp, 0xe0d6, data);
+
+        data = r8168_mac_ocp_read(tp, 0xd420);
+        data &= 0x0fff;
+        data |= 0x047f;
+        r8168_mac_ocp_write(tp, 0xd420, data);
+
+        r8168_mac_ocp_write(tp, 0xe63e, 0x0001);
+        r8168_mac_ocp_write(tp, 0xe63e, 0x0000);
+        r8168_mac_ocp_write(tp, 0xc094, 0x0000);
+        r8168_mac_ocp_write(tp, 0xc09e, 0x0000);
+}
+
 static void rtl_hw_start_8168(struct net_device *dev)
 {
         struct rtl8169_private *tp = netdev_priv(dev);
@@ -5440,6 +5840,11 @@ static void rtl_hw_start_8168(struct net_device *dev)
                 rtl_hw_start_8411_2(tp);
                 break;
 
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+                rtl_hw_start_8168h_1(tp);
+                break;
+
         default:
                 printk(KERN_ERR PFX "%s: unknown chipset (mac_version = %d).\n",
                         dev->name, tp->mac_version);
@@ -5655,6 +6060,10 @@ static void rtl_hw_start_8101(struct net_device *dev)
         case RTL_GIGA_MAC_VER_43:
                 rtl_hw_start_8168g_2(tp);
                 break;
+        case RTL_GIGA_MAC_VER_47:
+        case RTL_GIGA_MAC_VER_48:
+                rtl_hw_start_8168h_1(tp);
+                break;
         }
 
         RTL_W8(Cfg9346, Cfg9346_Lock);
@@ -5895,7 +6304,7 @@ static int rtl8169_xmit_frags(struct rtl8169_private *tp, struct sk_buff *skb,
 {
         struct skb_shared_info *info = skb_shinfo(skb);
         unsigned int cur_frag, entry;
-        struct TxDesc * uninitialized_var(txd);
+        struct TxDesc *uninitialized_var(txd);
         struct device *d = &tp->pci_dev->dev;
 
         entry = tp->cur_tx;
@@ -7110,6 +7519,10 @@ static void rtl_hw_initialize(struct rtl8169_private *tp)
         case RTL_GIGA_MAC_VER_42:
         case RTL_GIGA_MAC_VER_43:
         case RTL_GIGA_MAC_VER_44:
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+        case RTL_GIGA_MAC_VER_47:
+        case RTL_GIGA_MAC_VER_48:
                 rtl_hw_init_8168g(tp);
                 break;
 
@@ -7255,8 +7668,19 @@ rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         RTL_W8(Cfg9346, Cfg9346_Unlock);
         RTL_W8(Config1, RTL_R8(Config1) | PMEnable);
         RTL_W8(Config5, RTL_R8(Config5) & (BWF | MWF | UWF | LanWake | PMEStatus));
-        if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
-                tp->features |= RTL_FEATURE_WOL;
+        switch (tp->mac_version) {
+        case RTL_GIGA_MAC_VER_45:
+        case RTL_GIGA_MAC_VER_46:
+                if (rtl_eri_read(tp, 0xdc, ERIAR_EXGMAC) & MagicPacket_v2)
+                        tp->features |= RTL_FEATURE_WOL;
+                if ((RTL_R8(Config3) & LinkUp) != 0)
+                        tp->features |= RTL_FEATURE_WOL;
+                break;
+        default:
+                if ((RTL_R8(Config3) & (LinkUp | MagicPacket)) != 0)
+                        tp->features |= RTL_FEATURE_WOL;
+                break;
+        }
         if ((RTL_R8(Config5) & (UWF | BWF | MWF)) != 0)
                 tp->features |= RTL_FEATURE_WOL;
         tp->features |= rtl_try_msi(tp, cfg);
@@ -7283,6 +7707,18 @@ rtl_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
         u64_stats_init(&tp->tx_stats.syncp);
 
         /* Get MAC address */
+        if (tp->mac_version == RTL_GIGA_MAC_VER_45 ||
+            tp->mac_version == RTL_GIGA_MAC_VER_46 ||
+            tp->mac_version == RTL_GIGA_MAC_VER_47 ||
+            tp->mac_version == RTL_GIGA_MAC_VER_48) {
+                u16 mac_addr[3];
+
+                *(u32 *)&mac_addr[0] = rtl_eri_read(tp, 0xE0, ERIAR_EXGMAC);
+                *(u16 *)&mac_addr[2] = rtl_eri_read(tp, 0xE4, ERIAR_EXGMAC);
+
+                if (is_valid_ether_addr((u8 *)mac_addr))
+                        rtl_rar_set(tp, (u8 *)mac_addr);
+        }
         for (i = 0; i < ETH_ALEN; i++)
                 dev->dev_addr[i] = RTL_R8(MAC0 + i);
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index ec632e666c56..ddc6115720a3 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -17,6 +17,7 @@
 
 #include <linux/mfd/syscon.h>
 #include <linux/of.h>
+#include <linux/of_address.h>
 #include <linux/of_net.h>
 #include <linux/phy.h>
 #include <linux/regmap.h>
@@ -30,6 +31,12 @@
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
 
+#define EMAC_SPLITTER_CTRL_REG                  0x0
+#define EMAC_SPLITTER_CTRL_SPEED_MASK           0x3
+#define EMAC_SPLITTER_CTRL_SPEED_10             0x2
+#define EMAC_SPLITTER_CTRL_SPEED_100            0x3
+#define EMAC_SPLITTER_CTRL_SPEED_1000           0x0
+
 struct socfpga_dwmac {
         int     interface;
         u32     reg_offset;
@@ -37,14 +44,46 @@ struct socfpga_dwmac {
         struct  device *dev;
         struct regmap *sys_mgr_base_addr;
         struct reset_control *stmmac_rst;
+        void __iomem *splitter_base;
 };
 
+static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
+{
+        struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
+        void __iomem *splitter_base = dwmac->splitter_base;
+        u32 val;
+
+        if (!splitter_base)
+                return;
+
+        val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
+        val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
+
+        switch (speed) {
+        case 1000:
+                val |= EMAC_SPLITTER_CTRL_SPEED_1000;
+                break;
+        case 100:
+                val |= EMAC_SPLITTER_CTRL_SPEED_100;
+                break;
+        case 10:
+                val |= EMAC_SPLITTER_CTRL_SPEED_10;
+                break;
+        default:
+                return;
+        }
+
+        writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
+}
+
 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
 {
         struct device_node *np = dev->of_node;
         struct regmap *sys_mgr_base_addr;
         u32 reg_offset, reg_shift;
         int ret;
+        struct device_node *np_splitter;
+        struct resource res_splitter;
 
         dwmac->stmmac_rst = devm_reset_control_get(dev,
                                                   STMMAC_RESOURCE_NAME);
@@ -73,6 +112,20 @@ static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *
                 return -EINVAL;
         }
 
+        np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
+        if (np_splitter) {
+                if (of_address_to_resource(np_splitter, 0, &res_splitter)) {
+                        dev_info(dev, "Missing emac splitter address\n");
+                        return -EINVAL;
+                }
+
+                dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
+                if (!dwmac->splitter_base) {
+                        dev_info(dev, "Failed to mapping emac splitter\n");
+                        return -EINVAL;
+                }
+        }
+
         dwmac->reg_offset = reg_offset;
         dwmac->reg_shift = reg_shift;
         dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
@@ -91,6 +144,7 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
 
         switch (phymode) {
         case PHY_INTERFACE_MODE_RGMII:
+        case PHY_INTERFACE_MODE_RGMII_ID:
                 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
                 break;
         case PHY_INTERFACE_MODE_MII:
@@ -102,6 +156,13 @@ static int socfpga_dwmac_setup(struct socfpga_dwmac *dwmac)
                 return -EINVAL;
         }
 
+        /* Overwrite val to GMII if splitter core is enabled. The phymode here
+         * is the actual phy mode on phy hardware, but phy interface from
+         * EMAC core is GMII.
+         */
+        if (dwmac->splitter_base)
+                val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
+
         regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
         ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
         ctrl |= val << reg_shift;
@@ -196,4 +257,5 @@ const struct stmmac_of_data socfpga_gmac_data = {
         .setup = socfpga_dwmac_probe,
         .init = socfpga_dwmac_init,
         .exit = socfpga_dwmac_exit,
+        .fix_mac_speed = socfpga_dwmac_fix_mac_speed,
 };
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index cf4f38db1c0a..3a08a1f78c73 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -261,11 +261,11 @@ static int stmmac_ethtool_getsettings(struct net_device *dev,
                 ethtool_cmd_speed_set(cmd, priv->xstats.pcs_speed);
 
                 /* Get and convert ADV/LP_ADV from the HW AN registers */
-                if (priv->hw->mac->get_adv)
-                        priv->hw->mac->get_adv(priv->hw, &adv);
-                else
+                if (!priv->hw->mac->get_adv)
                         return -EOPNOTSUPP;     /* should never happen indeed */
 
+                priv->hw->mac->get_adv(priv->hw, &adv);
+
                 /* Encoding of PSE bits is defined in 802.3z, 37.2.1.4 */
 
                 if (adv.pause & STMMAC_PCS_PAUSE)
@@ -340,19 +340,17 @@ static int stmmac_ethtool_setsettings(struct net_device *dev,
                 if (cmd->autoneg != AUTONEG_ENABLE)
                         return -EINVAL;
 
-                if (cmd->autoneg == AUTONEG_ENABLE) {
-                        mask &= (ADVERTISED_1000baseT_Half |
+                mask &= (ADVERTISED_1000baseT_Half |
                         ADVERTISED_1000baseT_Full |
                         ADVERTISED_100baseT_Half |
                         ADVERTISED_100baseT_Full |
                         ADVERTISED_10baseT_Half |
                         ADVERTISED_10baseT_Full);
 
-                        spin_lock(&priv->lock);
-                        if (priv->hw->mac->ctrl_ane)
-                                priv->hw->mac->ctrl_ane(priv->hw, 1);
-                        spin_unlock(&priv->lock);
-                }
+                spin_lock(&priv->lock);
+                if (priv->hw->mac->ctrl_ane)
+                        priv->hw->mac->ctrl_ane(priv->hw, 1);
+                spin_unlock(&priv->lock);
 
                 return 0;
         }
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 6e6ee226de04..9dbb02d9d9c2 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -834,7 +834,7 @@ static int stmmac_init_phy(struct net_device *dev)
         /* Stop Advertising 1000BASE Capability if interface is not GMII */
         if ((interface == PHY_INTERFACE_MODE_MII) ||
             (interface == PHY_INTERFACE_MODE_RMII) ||
-                (max_speed < 1000 &&  max_speed > 0))
+                (max_speed < 1000 && max_speed > 0))
                 phydev->advertising &= ~(SUPPORTED_1000baseT_Half |
                                          SUPPORTED_1000baseT_Full);
 
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
index a5b1e1b776fe..8dd040827c69 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_mdio.c
@@ -253,7 +253,7 @@ int stmmac_mdio_register(struct net_device *ndev)
                         }
 
                         /*
-                         * If we're  going to bind the MAC to this PHY bus,
+                         * If we're going to bind the MAC to this PHY bus,
                          * and no PHY number was provided to the MAC,
                          * use the one probed here.
                          */
diff --git a/drivers/net/ethernet/sun/sungem.c b/drivers/net/ethernet/sun/sungem.c
index f7415b6bf141..fef5dec2cffe 100644
--- a/drivers/net/ethernet/sun/sungem.c
+++ b/drivers/net/ethernet/sun/sungem.c
@@ -115,7 +115,7 @@ static const struct pci_device_id gem_pci_tbl[] = {
 
 MODULE_DEVICE_TABLE(pci, gem_pci_tbl);
 
-static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
+static u16 __sungem_phy_read(struct gem *gp, int phy_addr, int reg)
 {
         u32 cmd;
         int limit = 10000;
@@ -141,18 +141,18 @@ static u16 __phy_read(struct gem *gp, int phy_addr, int reg)
         return cmd & MIF_FRAME_DATA;
 }
 
-static inline int _phy_read(struct net_device *dev, int mii_id, int reg)
+static inline int _sungem_phy_read(struct net_device *dev, int mii_id, int reg)
 {
         struct gem *gp = netdev_priv(dev);
-        return __phy_read(gp, mii_id, reg);
+        return __sungem_phy_read(gp, mii_id, reg);
 }
 
-static inline u16 phy_read(struct gem *gp, int reg)
+static inline u16 sungem_phy_read(struct gem *gp, int reg)
 {
-        return __phy_read(gp, gp->mii_phy_addr, reg);
+        return __sungem_phy_read(gp, gp->mii_phy_addr, reg);
 }
 
-static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
+static void __sungem_phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
 {
         u32 cmd;
         int limit = 10000;
@@ -174,15 +174,15 @@ static void __phy_write(struct gem *gp, int phy_addr, int reg, u16 val)
         }
 }
 
-static inline void _phy_write(struct net_device *dev, int mii_id, int reg, int val)
+static inline void _sungem_phy_write(struct net_device *dev, int mii_id, int reg, int val)
 {
         struct gem *gp = netdev_priv(dev);
-        __phy_write(gp, mii_id, reg, val & 0xffff);
+        __sungem_phy_write(gp, mii_id, reg, val & 0xffff);
 }
 
-static inline void phy_write(struct gem *gp, int reg, u16 val)
+static inline void sungem_phy_write(struct gem *gp, int reg, u16 val)
 {
-        __phy_write(gp, gp->mii_phy_addr, reg, val);
+        __sungem_phy_write(gp, gp->mii_phy_addr, reg, val);
 }
 
 static inline void gem_enable_ints(struct gem *gp)
@@ -1687,9 +1687,9 @@ static void gem_init_phy(struct gem *gp)
                         /* Some PHYs used by apple have problem getting back to us,
                          * we do an additional reset here
                          */
-                        phy_write(gp, MII_BMCR, BMCR_RESET);
+                        sungem_phy_write(gp, MII_BMCR, BMCR_RESET);
                         msleep(20);
-                        if (phy_read(gp, MII_BMCR) != 0xffff)
+                        if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
                                 break;
                         if (i == 2)
                                 netdev_warn(gp->dev, "GMAC PHY not responding !\n");
@@ -2012,7 +2012,7 @@ static int gem_check_invariants(struct gem *gp)
 
                 for (i = 0; i < 32; i++) {
                         gp->mii_phy_addr = i;
-                        if (phy_read(gp, MII_BMCR) != 0xffff)
+                        if (sungem_phy_read(gp, MII_BMCR) != 0xffff)
                                 break;
                 }
                 if (i == 32) {
@@ -2696,13 +2696,13 @@ static int gem_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
                 /* Fallthrough... */
 
         case SIOCGMIIREG:               /* Read MII PHY register. */
-                data->val_out = __phy_read(gp, data->phy_id & 0x1f,
+                data->val_out = __sungem_phy_read(gp, data->phy_id & 0x1f,
                                            data->reg_num & 0x1f);
                 rc = 0;
                 break;
 
         case SIOCSMIIREG:               /* Write MII PHY register. */
-                __phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
+                __sungem_phy_write(gp, data->phy_id & 0x1f, data->reg_num & 0x1f,
                             data->val_in);
                 rc = 0;
                 break;
@@ -2933,8 +2933,8 @@ static int gem_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
 
         /* Fill up the mii_phy structure (even if we won't use it) */
         gp->phy_mii.dev = dev;
-        gp->phy_mii.mdio_read = _phy_read;
-        gp->phy_mii.mdio_write = _phy_write;
+        gp->phy_mii.mdio_read = _sungem_phy_read;
+        gp->phy_mii.mdio_write = _sungem_phy_write;
 #ifdef CONFIG_PPC_PMAC
         gp->phy_mii.platform_data = gp->of_node;
 #endif
diff --git a/drivers/net/ethernet/ti/cpsw.c b/drivers/net/ethernet/ti/cpsw.c
index 999fb72688d2..03b409988566 100644
--- a/drivers/net/ethernet/ti/cpsw.c
+++ b/drivers/net/ethernet/ti/cpsw.c
@@ -2232,18 +2232,24 @@ static int cpsw_probe(struct platform_device *pdev)
         }
 
         while ((res = platform_get_resource(priv->pdev, IORESOURCE_IRQ, k))) {
-                for (i = res->start; i <= res->end; i++) {
-                        if (devm_request_irq(&pdev->dev, i, cpsw_interrupt, 0,
-                                             dev_name(&pdev->dev), priv)) {
-                                dev_err(priv->dev, "error attaching irq\n");
-                                goto clean_ale_ret;
-                        }
-                        priv->irqs_table[k] = i;
-                        priv->num_irqs = k + 1;
+                if (k >= ARRAY_SIZE(priv->irqs_table)) {
+                        ret = -EINVAL;
+                        goto clean_ale_ret;
                 }
+
+                ret = devm_request_irq(&pdev->dev, res->start, cpsw_interrupt,
+                                       0, dev_name(&pdev->dev), priv);
+                if (ret < 0) {
+                        dev_err(priv->dev, "error attaching irq (%d)\n", ret);
+                        goto clean_ale_ret;
+                }
+
+                priv->irqs_table[k] = res->start;
                 k++;
         }
 
+        priv->num_irqs = k;
+
         ndev->features |= NETIF_F_HW_VLAN_CTAG_FILTER;
 
         ndev->netdev_ops = &cpsw_netdev_ops;
diff --git a/drivers/net/hyperv/hyperv_net.h b/drivers/net/hyperv/hyperv_net.h
index d5e07def6a59..2f48f790c9b4 100644
--- a/drivers/net/hyperv/hyperv_net.h
+++ b/drivers/net/hyperv/hyperv_net.h
@@ -591,7 +591,7 @@ struct nvsp_message {
 
 #define NETVSC_RECEIVE_BUFFER_ID                0xcafe
 
-#define NETVSC_PACKET_SIZE                      2048
+#define NETVSC_PACKET_SIZE                      4096
 
 #define VRSS_SEND_TAB_SIZE 16
 
@@ -642,7 +642,7 @@ struct netvsc_device {
         int ring_size;
 
         /* The primary channel callback buffer */
-        unsigned char cb_buffer[NETVSC_PACKET_SIZE];
+        unsigned char *cb_buffer;
         /* The sub channel callback buffer */
         unsigned char *sub_cb_buf;
 };
diff --git a/drivers/net/hyperv/netvsc.c b/drivers/net/hyperv/netvsc.c
index 66979cf7fca6..977984bc238a 100644
--- a/drivers/net/hyperv/netvsc.c
+++ b/drivers/net/hyperv/netvsc.c
@@ -42,6 +42,12 @@ static struct netvsc_device *alloc_net_device(struct hv_device *device)
         if (!net_device)
                 return NULL;
 
+        net_device->cb_buffer = kzalloc(NETVSC_PACKET_SIZE, GFP_KERNEL);
+        if (!net_device->cb_buffer) {
+                kfree(net_device);
+                return NULL;
+        }
+
         init_waitqueue_head(&net_device->wait_drain);
         net_device->start_remove = false;
         net_device->destroy = false;
@@ -52,6 +58,12 @@ static struct netvsc_device *alloc_net_device(struct hv_device *device)
         return net_device;
 }
 
+static void free_netvsc_device(struct netvsc_device *nvdev)
+{
+        kfree(nvdev->cb_buffer);
+        kfree(nvdev);
+}
+
 static struct netvsc_device *get_outbound_net_device(struct hv_device *device)
 {
         struct netvsc_device *net_device;
@@ -551,7 +563,7 @@ int netvsc_device_remove(struct hv_device *device)
         if (net_device->sub_cb_buf)
                 vfree(net_device->sub_cb_buf);
 
-        kfree(net_device);
+        free_netvsc_device(net_device);
         return 0;
 }
 
@@ -1042,10 +1054,8 @@ int netvsc_device_add(struct hv_device *device, void *additional_info)
         struct net_device *ndev;
 
         net_device = alloc_net_device(device);
-        if (!net_device) {
-                ret = -ENOMEM;
-                goto cleanup;
-        }
+        if (!net_device)
+                return -ENOMEM;
 
         net_device->ring_size = ring_size;
 
@@ -1093,7 +1103,7 @@ close:
         vmbus_close(device->channel);
 
 cleanup:
-        kfree(net_device);
+        free_netvsc_device(net_device);
 
         return ret;
 }
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 65de0cab8d07..14afa4f24424 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -159,8 +159,6 @@ config MDIO_OCTEON
 config MDIO_SUN4I
         tristate "Allwinner sun4i MDIO interface support"
         depends on ARCH_SUNXI
-        select REGULATOR
-        select REGULATOR_FIXED_VOLTAGE
         help
           This driver supports the MDIO interface found in the network
           interface units of the Allwinner SoC that have an EMAC (A10,
@@ -205,6 +203,14 @@ config MDIO_BUS_MUX_MMIOREG
 
           Currently, only 8-bit registers are supported.
 
+config MDIO_BCM_UNIMAC
+        tristate "Broadcom UniMAC MDIO bus controller"
+        help
+          This module provides a driver for the Broadcom UniMAC MDIO busses.
+          This hardware can be found in the Broadcom GENET Ethernet MAC
+          controllers as well as some Broadcom Ethernet switches such as the
+          Starfighter 2 switches.
+
 endif # PHYLIB
 
 config MICREL_KS8995MA
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 7dc3d5b304cf..eb3b18b5978b 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -34,3 +34,4 @@ obj-$(CONFIG_MDIO_BUS_MUX_MMIOREG) += mdio-mux-mmioreg.o
 obj-$(CONFIG_MDIO_SUN4I)        += mdio-sun4i.o
 obj-$(CONFIG_MDIO_MOXART)       += mdio-moxart.o
 obj-$(CONFIG_AMD_XGBE_PHY)      += amd-xgbe-phy.o
+obj-$(CONFIG_MDIO_BCM_UNIMAC)   += mdio-bcm-unimac.o
diff --git a/drivers/net/phy/amd-xgbe-phy.c b/drivers/net/phy/amd-xgbe-phy.c
index f3230eef41fd..c456559f6e7f 100644
--- a/drivers/net/phy/amd-xgbe-phy.c
+++ b/drivers/net/phy/amd-xgbe-phy.c
@@ -75,7 +75,6 @@
 #include <linux/of_device.h>
 #include <linux/uaccess.h>
 
-
 MODULE_AUTHOR("Tom Lendacky <thomas.lendacky@amd.com>");
 MODULE_LICENSE("Dual BSD/GPL");
 MODULE_VERSION("1.0.0-a");
@@ -100,9 +99,11 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #ifndef MDIO_PMA_10GBR_PMD_CTRL
 #define MDIO_PMA_10GBR_PMD_CTRL         0x0096
 #endif
+
 #ifndef MDIO_PMA_10GBR_FEC_CTRL
 #define MDIO_PMA_10GBR_FEC_CTRL         0x00ab
 #endif
+
 #ifndef MDIO_AN_XNP
 #define MDIO_AN_XNP                     0x0016
 #endif
@@ -110,14 +111,23 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #ifndef MDIO_AN_INTMASK
 #define MDIO_AN_INTMASK                 0x8001
 #endif
+
 #ifndef MDIO_AN_INT
 #define MDIO_AN_INT                     0x8002
 #endif
 
+#ifndef MDIO_AN_KR_CTRL
+#define MDIO_AN_KR_CTRL                 0x8003
+#endif
+
 #ifndef MDIO_CTRL1_SPEED1G
 #define MDIO_CTRL1_SPEED1G              (MDIO_CTRL1_SPEED10G & ~BMCR_SPEED100)
 #endif
 
+#ifndef MDIO_KR_CTRL_PDETECT
+#define MDIO_KR_CTRL_PDETECT            0x01
+#endif
+
 /* SerDes integration register offsets */
 #define SIR0_KR_RT_1                    0x002c
 #define SIR0_STATUS                     0x0040
@@ -161,7 +171,6 @@ MODULE_DESCRIPTION("AMD 10GbE (amd-xgbe) PHY driver");
 #define SPEED_1000_TXAMP                0xf
 #define SPEED_1000_WORD                 0x1
 
-
 /* SerDes RxTx register offsets */
 #define RXTX_REG20                      0x0050
 #define RXTX_REG114                     0x01c8
@@ -255,7 +264,6 @@ do {									\
         XSIR1_IOWRITE((_priv), _reg, reg_val);                          \
 } while (0)
 
-
 /* Macros for reading or writing SerDes RxTx registers
  *  The ioread macros will get bit fields or full values using the
  *  register definitions formed using the input names
@@ -283,7 +291,6 @@ do {									\
         XRXTX_IOWRITE((_priv), _reg, reg_val);                          \
 } while (0)
 
-
 enum amd_xgbe_phy_an {
         AMD_XGBE_AN_READY = 0,
         AMD_XGBE_AN_START,
@@ -331,7 +338,6 @@ struct amd_xgbe_phy_priv {
 
         /* Maintain link status for re-starting auto-negotiation */
         unsigned int link;
-        enum amd_xgbe_phy_mode mode;
         unsigned int speed_set;
 
         /* Auto-negotiation state machine support */
@@ -342,6 +348,7 @@ struct amd_xgbe_phy_priv {
         enum amd_xgbe_phy_rx kx_state;
         struct work_struct an_work;
         struct workqueue_struct *an_workqueue;
+        unsigned int parallel_detect;
 };
 
 static int amd_xgbe_an_enable_kr_training(struct phy_device *phydev)
@@ -468,8 +475,6 @@ static int amd_xgbe_phy_xgmii_mode(struct phy_device *phydev)
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
-        priv->mode = AMD_XGBE_MODE_KR;
-
         return 0;
 }
 
@@ -518,8 +523,6 @@ static int amd_xgbe_phy_gmii_2500_mode(struct phy_device *phydev)
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
-        priv->mode = AMD_XGBE_MODE_KX;
-
         return 0;
 }
 
@@ -568,18 +571,43 @@ static int amd_xgbe_phy_gmii_mode(struct phy_device *phydev)
 
         amd_xgbe_phy_serdes_complete_ratechange(phydev);
 
-        priv->mode = AMD_XGBE_MODE_KX;
+        return 0;
+}
+
+static int amd_xgbe_phy_cur_mode(struct phy_device *phydev,
+                                 enum amd_xgbe_phy_mode *mode)
+{
+        int ret;
+
+        ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
+        if (ret < 0)
+                return ret;
+
+        if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
+                *mode = AMD_XGBE_MODE_KR;
+        else
+                *mode = AMD_XGBE_MODE_KX;
 
         return 0;
 }
 
+static bool amd_xgbe_phy_in_kr_mode(struct phy_device *phydev)
+{
+        enum amd_xgbe_phy_mode mode;
+
+        if (amd_xgbe_phy_cur_mode(phydev, &mode))
+                return false;
+
+        return (mode == AMD_XGBE_MODE_KR);
+}
+
 static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         int ret;
 
         /* If we are in KR switch to KX, and vice-versa */
-        if (priv->mode == AMD_XGBE_MODE_KR) {
+        if (amd_xgbe_phy_in_kr_mode(phydev)) {
                 if (priv->speed_set == AMD_XGBE_PHY_SPEEDSET_1000_10000)
                         ret = amd_xgbe_phy_gmii_mode(phydev);
                 else
@@ -591,15 +619,20 @@ static int amd_xgbe_phy_switch_mode(struct phy_device *phydev)
         return ret;
 }
 
-static enum amd_xgbe_phy_an amd_xgbe_an_switch_mode(struct phy_device *phydev)
+static int amd_xgbe_phy_set_mode(struct phy_device *phydev,
+                                 enum amd_xgbe_phy_mode mode)
 {
+        enum amd_xgbe_phy_mode cur_mode;
         int ret;
 
-        ret = amd_xgbe_phy_switch_mode(phydev);
-        if (ret < 0)
-                return AMD_XGBE_AN_ERROR;
+        ret = amd_xgbe_phy_cur_mode(phydev, &cur_mode);
+        if (ret)
+                return ret;
 
-        return AMD_XGBE_AN_START;
+        if (mode != cur_mode)
+                ret = amd_xgbe_phy_switch_mode(phydev);
+
+        return ret;
 }
 
 static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
@@ -610,8 +643,8 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_training(struct phy_device *phydev,
 
         *state = AMD_XGBE_RX_COMPLETE;
 
-        /* If we're in KX mode then we're done */
-        if (priv->mode == AMD_XGBE_MODE_KX)
+        /* If we're not in KR mode then we're done */
+        if (!amd_xgbe_phy_in_kr_mode(phydev))
                 return AMD_XGBE_AN_EVENT;
 
         /* Enable/Disable FEC */
@@ -669,7 +702,6 @@ static enum amd_xgbe_phy_an amd_xgbe_an_tx_xnp(struct phy_device *phydev,
 static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
                                                enum amd_xgbe_phy_rx *state)
 {
-        struct amd_xgbe_phy_priv *priv = phydev->priv;
         unsigned int link_support;
         int ret, ad_reg, lp_reg;
 
@@ -679,9 +711,9 @@ static enum amd_xgbe_phy_an amd_xgbe_an_rx_bpa(struct phy_device *phydev,
                 return AMD_XGBE_AN_ERROR;
 
         /* Check for a supported mode, otherwise restart in a different one */
-        link_support = (priv->mode == AMD_XGBE_MODE_KR) ? 0x80 : 0x20;
+        link_support = amd_xgbe_phy_in_kr_mode(phydev) ? 0x80 : 0x20;
         if (!(ret & link_support))
-                return amd_xgbe_an_switch_mode(phydev);
+                return AMD_XGBE_AN_INCOMPAT_LINK;
 
         /* Check Extended Next Page support */
         ad_reg = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_ADVERTISE);
@@ -722,7 +754,7 @@ static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
         int ret;
 
         /* Be sure we aren't looping trying to negotiate */
-        if (priv->mode == AMD_XGBE_MODE_KR) {
+        if (amd_xgbe_phy_in_kr_mode(phydev)) {
                 if (priv->kr_state != AMD_XGBE_RX_READY)
                         return AMD_XGBE_AN_NO_LINK;
                 priv->kr_state = AMD_XGBE_RX_BPA;
@@ -785,6 +817,13 @@ static enum amd_xgbe_phy_an amd_xgbe_an_start(struct phy_device *phydev)
         /* Enable and start auto-negotiation */
         phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_INT, 0);
 
+        ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL);
+        if (ret < 0)
+                return AMD_XGBE_AN_ERROR;
+
+        ret |= MDIO_KR_CTRL_PDETECT;
+        phy_write_mmd(phydev, MDIO_MMD_AN, MDIO_AN_KR_CTRL, ret);
+
         ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_CTRL1);
         if (ret < 0)
                 return AMD_XGBE_AN_ERROR;
@@ -825,8 +864,8 @@ static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
         enum amd_xgbe_phy_rx *state;
         int ret;
 
-        state = (priv->mode == AMD_XGBE_MODE_KR) ? &priv->kr_state
-                                                 : &priv->kx_state;
+        state = amd_xgbe_phy_in_kr_mode(phydev) ? &priv->kr_state
+                                                : &priv->kx_state;
 
         switch (*state) {
         case AMD_XGBE_RX_BPA:
@@ -846,7 +885,13 @@ static enum amd_xgbe_phy_an amd_xgbe_an_page_received(struct phy_device *phydev)
 
 static enum amd_xgbe_phy_an amd_xgbe_an_incompat_link(struct phy_device *phydev)
 {
-        return amd_xgbe_an_switch_mode(phydev);
+        int ret;
+
+        ret = amd_xgbe_phy_switch_mode(phydev);
+        if (ret)
+                return AMD_XGBE_AN_ERROR;
+
+        return AMD_XGBE_AN_START;
 }
 
 static void amd_xgbe_an_state_machine(struct work_struct *work)
@@ -859,6 +904,10 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
         int sleep;
         unsigned int an_supported = 0;
 
+        /* Start in KX mode */
+        if (amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX))
+                priv->an_state = AMD_XGBE_AN_ERROR;
+
         while (1) {
                 mutex_lock(&priv->an_mutex);
 
@@ -866,8 +915,9 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
 
                 switch (priv->an_state) {
                 case AMD_XGBE_AN_START:
-                        priv->an_state = amd_xgbe_an_start(phydev);
                         an_supported = 0;
+                        priv->parallel_detect = 0;
+                        priv->an_state = amd_xgbe_an_start(phydev);
                         break;
 
                 case AMD_XGBE_AN_EVENT:
@@ -884,6 +934,7 @@ static void amd_xgbe_an_state_machine(struct work_struct *work)
                         break;
 
                 case AMD_XGBE_AN_COMPLETE:
+                        priv->parallel_detect = an_supported ? 0 : 1;
                         netdev_info(phydev->attached_dev, "%s successful\n",
                                     an_supported ? "Auto negotiation"
                                                  : "Parallel detection");
@@ -1018,7 +1069,6 @@ static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         u32 mmd_mask = phydev->c45_ids.devices_in_package;
-        int ret;
 
         if (phydev->autoneg != AUTONEG_ENABLE)
                 return amd_xgbe_phy_setup_forced(phydev);
@@ -1027,11 +1077,6 @@ static int amd_xgbe_phy_config_aneg(struct phy_device *phydev)
         if (!(mmd_mask & MDIO_DEVS_AN))
                 return -EINVAL;
 
-        /* Get the current speed mode */
-        ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-        if (ret < 0)
-                return ret;
-
         /* Start/Restart the auto-negotiation state machine */
         mutex_lock(&priv->an_mutex);
         priv->an_result = AMD_XGBE_AN_READY;
@@ -1121,18 +1166,14 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
 {
         struct amd_xgbe_phy_priv *priv = phydev->priv;
         u32 mmd_mask = phydev->c45_ids.devices_in_package;
-        int ret, mode, ad_ret, lp_ret;
+        int ret, ad_ret, lp_ret;
 
         ret = amd_xgbe_phy_update_link(phydev);
         if (ret)
                 return ret;
 
-        mode = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-        if (mode < 0)
-                return mode;
-        mode &= MDIO_PCS_CTRL2_TYPE;
-
-        if (phydev->autoneg == AUTONEG_ENABLE) {
+        if ((phydev->autoneg == AUTONEG_ENABLE) &&
+            !priv->parallel_detect) {
                 if (!(mmd_mask & MDIO_DEVS_AN))
                         return -EINVAL;
 
@@ -1163,40 +1204,39 @@ static int amd_xgbe_phy_read_status(struct phy_device *phydev)
                 ad_ret &= lp_ret;
                 if (ad_ret & 0x80) {
                         phydev->speed = SPEED_10000;
-                        if (mode != MDIO_PCS_CTRL2_10GBR) {
-                                ret = amd_xgbe_phy_xgmii_mode(phydev);
-                                if (ret < 0)
-                                        return ret;
-                        }
+                        ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KR);
+                        if (ret)
+                                return ret;
                 } else {
-                        int (*mode_fcn)(struct phy_device *);
-
-                        if (priv->speed_set ==
-                            AMD_XGBE_PHY_SPEEDSET_1000_10000) {
+                        switch (priv->speed_set) {
+                        case AMD_XGBE_PHY_SPEEDSET_1000_10000:
                                 phydev->speed = SPEED_1000;
-                                mode_fcn = amd_xgbe_phy_gmii_mode;
-                        } else {
+                                break;
+
+                        case AMD_XGBE_PHY_SPEEDSET_2500_10000:
                                 phydev->speed = SPEED_2500;
-                                mode_fcn = amd_xgbe_phy_gmii_2500_mode;
+                                break;
                         }
 
-                        if (mode == MDIO_PCS_CTRL2_10GBR) {
-                                ret = mode_fcn(phydev);
-                                if (ret < 0)
-                                        return ret;
-                        }
+                        ret = amd_xgbe_phy_set_mode(phydev, AMD_XGBE_MODE_KX);
+                        if (ret)
+                                return ret;
                 }
 
                 phydev->duplex = DUPLEX_FULL;
         } else {
-                if (mode == MDIO_PCS_CTRL2_10GBR) {
+                if (amd_xgbe_phy_in_kr_mode(phydev)) {
                         phydev->speed = SPEED_10000;
                 } else {
-                        if (priv->speed_set ==
-                            AMD_XGBE_PHY_SPEEDSET_1000_10000)
+                        switch (priv->speed_set) {
+                        case AMD_XGBE_PHY_SPEEDSET_1000_10000:
                                 phydev->speed = SPEED_1000;
-                        else
+                                break;
+
+                        case AMD_XGBE_PHY_SPEEDSET_2500_10000:
                                 phydev->speed = SPEED_2500;
+                                break;
+                        }
                 }
                 phydev->duplex = DUPLEX_FULL;
                 phydev->pause = 0;
@@ -1329,14 +1369,6 @@ static int amd_xgbe_phy_probe(struct phy_device *phydev)
 
         priv->link = 1;
 
-        ret = phy_read_mmd(phydev, MDIO_MMD_PCS, MDIO_CTRL2);
-        if (ret < 0)
-                goto err_sir1;
-        if ((ret & MDIO_PCS_CTRL2_TYPE) == MDIO_PCS_CTRL2_10GBR)
-                priv->mode = AMD_XGBE_MODE_KR;
-        else
-                priv->mode = AMD_XGBE_MODE_KX;
-
         mutex_init(&priv->an_mutex);
         INIT_WORK(&priv->an_work, amd_xgbe_an_state_machine);
         priv->an_workqueue = create_singlethread_workqueue(wq_name);
diff --git a/drivers/net/phy/bcm7xxx.c b/drivers/net/phy/bcm7xxx.c
index fdce1ea28790..09dd6e1dc6e1 100644
--- a/drivers/net/phy/bcm7xxx.c
+++ b/drivers/net/phy/bcm7xxx.c
@@ -14,6 +14,7 @@
 #include <linux/delay.h>
 #include <linux/bitops.h>
 #include <linux/brcmphy.h>
+#include <linux/mdio.h>
 
 /* Broadcom BCM7xxx internal PHY registers */
 #define MII_BCM7XXX_CHANNEL_WIDTH       0x2000
@@ -146,6 +147,53 @@ static int bcm7xxx_28nm_afe_config_init(struct phy_device *phydev)
         return 0;
 }
 
+static int bcm7xxx_apd_enable(struct phy_device *phydev)
+{
+        int val;
+
+        /* Enable powering down of the DLL during auto-power down */
+        val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_SCR3);
+        if (val < 0)
+                return val;
+
+        val |= BCM54XX_SHD_SCR3_DLLAPD_DIS;
+        bcm54xx_shadow_write(phydev, BCM54XX_SHD_SCR3, val);
+
+        /* Enable auto-power down */
+        val = bcm54xx_shadow_read(phydev, BCM54XX_SHD_APD);
+        if (val < 0)
+                return val;
+
+        val |= BCM54XX_SHD_APD_EN;
+        return bcm54xx_shadow_write(phydev, BCM54XX_SHD_APD, val);
+}
+
+static int bcm7xxx_eee_enable(struct phy_device *phydev)
+{
+        int val;
+
+        val = phy_read_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
+                                    MDIO_MMD_AN, phydev->addr);
+        if (val < 0)
+                return val;
+
+        /* Enable general EEE feature at the PHY level */
+        val |= LPI_FEATURE_EN | LPI_FEATURE_EN_DIG1000X;
+
+        phy_write_mmd_indirect(phydev, BRCM_CL45VEN_EEE_CONTROL,
+                               MDIO_MMD_AN, phydev->addr, val);
+
+        /* Advertise supported modes */
+        val = phy_read_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
+                                    MDIO_MMD_AN, phydev->addr);
+
+        val |= (MDIO_AN_EEE_ADV_100TX | MDIO_AN_EEE_ADV_1000T);
+        phy_write_mmd_indirect(phydev, MDIO_AN_EEE_ADV,
+                               MDIO_MMD_AN, phydev->addr, val);
+
+        return 0;
+}
+
 static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
 {
         int ret;
@@ -154,7 +202,15 @@ static int bcm7xxx_28nm_config_init(struct phy_device *phydev)
         if (ret)
                 return ret;
 
-        return bcm7xxx_28nm_afe_config_init(phydev);
+        ret = bcm7xxx_28nm_afe_config_init(phydev);
+        if (ret)
+                return ret;
+
+        ret = bcm7xxx_eee_enable(phydev);
+        if (ret)
+                return ret;
+
+        return bcm7xxx_apd_enable(phydev);
 }
 
 static int bcm7xxx_28nm_resume(struct phy_device *phydev)
@@ -263,44 +319,28 @@ static int bcm7xxx_dummy_config_init(struct phy_device *phydev)
         return 0;
 }
 
+#define BCM7XXX_28NM_GPHY(_oui, _name)                                  \
+{                                                                       \
+        .phy_id         = (_oui),                                       \
+        .phy_id_mask    = 0xfffffff0,                                   \
+        .name           = _name,                                        \
+        .features       = PHY_GBIT_FEATURES |                           \
+                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,       \
+        .flags          = PHY_IS_INTERNAL,                              \
+        .config_init    = bcm7xxx_28nm_afe_config_init,                 \
+        .config_aneg    = genphy_config_aneg,                           \
+        .read_status    = genphy_read_status,                           \
+        .resume         = bcm7xxx_28nm_resume,                          \
+        .driver         = { .owner = THIS_MODULE },                     \
+}
+
 static struct phy_driver bcm7xxx_driver[] = {
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7250, "Broadcom BCM7250"),
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7364, "Broadcom BCM7364"),
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7366, "Broadcom BCM7366"),
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7439, "Broadcom BCM7439"),
+        BCM7XXX_28NM_GPHY(PHY_ID_BCM7445, "Broadcom BCM7445"),
 {
-        .phy_id         = PHY_ID_BCM7366,
-        .phy_id_mask    = 0xfffffff0,
-        .name           = "Broadcom BCM7366",
-        .features       = PHY_GBIT_FEATURES |
-                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
-        .flags          = PHY_IS_INTERNAL,
-        .config_init    = bcm7xxx_28nm_afe_config_init,
-        .config_aneg    = genphy_config_aneg,
-        .read_status    = genphy_read_status,
-        .resume         = bcm7xxx_28nm_resume,
-        .driver         = { .owner = THIS_MODULE },
-}, {
-        .phy_id         = PHY_ID_BCM7439,
-        .phy_id_mask    = 0xfffffff0,
-        .name           = "Broadcom BCM7439",
-        .features       = PHY_GBIT_FEATURES |
-                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
-        .flags          = PHY_IS_INTERNAL,
-        .config_init    = bcm7xxx_28nm_afe_config_init,
-        .config_aneg    = genphy_config_aneg,
-        .read_status    = genphy_read_status,
-        .resume         = bcm7xxx_28nm_resume,
-        .driver         = { .owner = THIS_MODULE },
-}, {
-        .phy_id         = PHY_ID_BCM7445,
-        .phy_id_mask    = 0xfffffff0,
-        .name           = "Broadcom BCM7445",
-        .features       = PHY_GBIT_FEATURES |
-                          SUPPORTED_Pause | SUPPORTED_Asym_Pause,
-        .flags          = PHY_IS_INTERNAL,
-        .config_init    = bcm7xxx_28nm_config_init,
-        .config_aneg    = genphy_config_aneg,
-        .read_status    = genphy_read_status,
-        .resume         = bcm7xxx_28nm_afe_config_init,
-        .driver         = { .owner = THIS_MODULE },
-}, {
         .phy_id         = PHY_BCM_OUI_4,
         .phy_id_mask    = 0xffff0000,
         .name           = "Broadcom BCM7XXX 40nm",
@@ -329,6 +369,8 @@ static struct phy_driver bcm7xxx_driver[] = {
 } };
 
 static struct mdio_device_id __maybe_unused bcm7xxx_tbl[] = {
+        { PHY_ID_BCM7250, 0xfffffff0, },
+        { PHY_ID_BCM7364, 0xfffffff0, },
         { PHY_ID_BCM7366, 0xfffffff0, },
         { PHY_ID_BCM7439, 0xfffffff0, },
         { PHY_ID_BCM7445, 0xfffffff0, },
diff --git a/drivers/net/phy/broadcom.c b/drivers/net/phy/broadcom.c
index 34088d60da74..854f2c9a7b2b 100644
--- a/drivers/net/phy/broadcom.c
+++ b/drivers/net/phy/broadcom.c
@@ -25,132 +25,10 @@
 #define BRCM_PHY_REV(phydev) \
         ((phydev)->drv->phy_id & ~((phydev)->drv->phy_id_mask))
 
-/*
- * Broadcom LED source encodings.  These are used in BCM5461, BCM5481,
- * BCM5482, and possibly some others.
- */
-#define BCM_LED_SRC_LINKSPD1    0x0
-#define BCM_LED_SRC_LINKSPD2    0x1
-#define BCM_LED_SRC_XMITLED     0x2
-#define BCM_LED_SRC_ACTIVITYLED 0x3
-#define BCM_LED_SRC_FDXLED      0x4
-#define BCM_LED_SRC_SLAVE       0x5
-#define BCM_LED_SRC_INTR        0x6
-#define BCM_LED_SRC_QUALITY     0x7
-#define BCM_LED_SRC_RCVLED      0x8
-#define BCM_LED_SRC_MULTICOLOR1 0xa
-#define BCM_LED_SRC_OPENSHORT   0xb
-#define BCM_LED_SRC_OFF         0xe     /* Tied high */
-#define BCM_LED_SRC_ON          0xf     /* Tied low */
-
-
-/*
- * BCM5482: Shadow registers
- * Shadow values go into bits [14:10] of register 0x1c to select a shadow
- * register to access.
- */
-/* 00101: Spare Control Register 3 */
-#define BCM54XX_SHD_SCR3                0x05
-#define  BCM54XX_SHD_SCR3_DEF_CLK125    0x0001
-#define  BCM54XX_SHD_SCR3_DLLAPD_DIS    0x0002
-#define  BCM54XX_SHD_SCR3_TRDDAPD       0x0004
-
-/* 01010: Auto Power-Down */
-#define BCM54XX_SHD_APD                 0x0a
-#define  BCM54XX_SHD_APD_EN             0x0020
-
-#define BCM5482_SHD_LEDS1       0x0d    /* 01101: LED Selector 1 */
-                                        /* LED3 / ~LINKSPD[2] selector */
-#define BCM5482_SHD_LEDS1_LED3(src)     ((src & 0xf) << 4)
-                                        /* LED1 / ~LINKSPD[1] selector */
-#define BCM5482_SHD_LEDS1_LED1(src)     ((src & 0xf) << 0)
-#define BCM54XX_SHD_RGMII_MODE  0x0b    /* 01011: RGMII Mode Selector */
-#define BCM5482_SHD_SSD         0x14    /* 10100: Secondary SerDes control */
-#define BCM5482_SHD_SSD_LEDM    0x0008  /* SSD LED Mode enable */
-#define BCM5482_SHD_SSD_EN      0x0001  /* SSD enable */
-#define BCM5482_SHD_MODE        0x1f    /* 11111: Mode Control Register */
-#define BCM5482_SHD_MODE_1000BX 0x0001  /* Enable 1000BASE-X registers */
-
-
-/*
- * EXPANSION SHADOW ACCESS REGISTERS.  (PHY REG 0x15, 0x16, and 0x17)
- */
-#define MII_BCM54XX_EXP_AADJ1CH0                0x001f
-#define  MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN  0x0200
-#define  MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF    0x0100
-#define MII_BCM54XX_EXP_AADJ1CH3                0x601f
-#define  MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ      0x0002
-#define MII_BCM54XX_EXP_EXP08                   0x0F08
-#define  MII_BCM54XX_EXP_EXP08_RJCT_2MHZ        0x0001
-#define  MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE   0x0200
-#define MII_BCM54XX_EXP_EXP75                   0x0f75
-#define  MII_BCM54XX_EXP_EXP75_VDACCTRL         0x003c
-#define  MII_BCM54XX_EXP_EXP75_CM_OSC           0x0001
-#define MII_BCM54XX_EXP_EXP96                   0x0f96
-#define  MII_BCM54XX_EXP_EXP96_MYST             0x0010
-#define MII_BCM54XX_EXP_EXP97                   0x0f97
-#define  MII_BCM54XX_EXP_EXP97_MYST             0x0c0c
-
-/*
- * BCM5482: Secondary SerDes registers
- */
-#define BCM5482_SSD_1000BX_CTL          0x00    /* 1000BASE-X Control */
-#define BCM5482_SSD_1000BX_CTL_PWRDOWN  0x0800  /* Power-down SSD */
-#define BCM5482_SSD_SGMII_SLAVE         0x15    /* SGMII Slave Register */
-#define BCM5482_SSD_SGMII_SLAVE_EN      0x0002  /* Slave mode enable */
-#define BCM5482_SSD_SGMII_SLAVE_AD      0x0001  /* Slave auto-detection */
-
-
-/*****************************************************************************/
-/* Fast Ethernet Transceiver definitions. */
-/*****************************************************************************/
-
-#define MII_BRCM_FET_INTREG             0x1a    /* Interrupt register */
-#define MII_BRCM_FET_IR_MASK            0x0100  /* Mask all interrupts */
-#define MII_BRCM_FET_IR_LINK_EN         0x0200  /* Link status change enable */
-#define MII_BRCM_FET_IR_SPEED_EN        0x0400  /* Link speed change enable */
-#define MII_BRCM_FET_IR_DUPLEX_EN       0x0800  /* Duplex mode change enable */
-#define MII_BRCM_FET_IR_ENABLE          0x4000  /* Interrupt enable */
-
-#define MII_BRCM_FET_BRCMTEST           0x1f    /* Brcm test register */
-#define MII_BRCM_FET_BT_SRE             0x0080  /* Shadow register enable */
-
-
-/*** Shadow register definitions ***/
-
-#define MII_BRCM_FET_SHDW_MISCCTRL      0x10    /* Shadow misc ctrl */
-#define MII_BRCM_FET_SHDW_MC_FAME       0x4000  /* Force Auto MDIX enable */
-
-#define MII_BRCM_FET_SHDW_AUXMODE4      0x1a    /* Auxiliary mode 4 */
-#define MII_BRCM_FET_SHDW_AM4_LED_MASK  0x0003
-#define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001
-
-#define MII_BRCM_FET_SHDW_AUXSTAT2      0x1b    /* Auxiliary status 2 */
-#define MII_BRCM_FET_SHDW_AS2_APDE      0x0020  /* Auto power down enable */
-
-
 MODULE_DESCRIPTION("Broadcom PHY driver");
 MODULE_AUTHOR("Maciej W. Rozycki");
 MODULE_LICENSE("GPL");
 
-/*
- * Indirect register access functions for the 1000BASE-T/100BASE-TX/10BASE-T
- * 0x1c shadow registers.
- */
-static int bcm54xx_shadow_read(struct phy_device *phydev, u16 shadow)
-{
-        phy_write(phydev, MII_BCM54XX_SHD, MII_BCM54XX_SHD_VAL(shadow));
-        return MII_BCM54XX_SHD_DATA(phy_read(phydev, MII_BCM54XX_SHD));
-}
-
-static int bcm54xx_shadow_write(struct phy_device *phydev, u16 shadow, u16 val)
-{
-        return phy_write(phydev, MII_BCM54XX_SHD,
-                         MII_BCM54XX_SHD_WRITE |
-                         MII_BCM54XX_SHD_VAL(shadow) |
-                         MII_BCM54XX_SHD_DATA(val));
-}
-
 /* Indirect register access functions for the Expansion Registers */
 static int bcm54xx_exp_read(struct phy_device *phydev, u16 regnum)
 {
diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c
index c301e4cb37ca..87648b306551 100644
--- a/drivers/net/phy/dp83640.c
+++ b/drivers/net/phy/dp83640.c
@@ -721,7 +721,7 @@ static inline u16 exts_chan_to_edata(int ch)
 }
 
 static int decode_evnt(struct dp83640_private *dp83640,
-                       void *data, u16 ests)
+                       void *data, int len, u16 ests)
 {
         struct phy_txts *phy_txts;
         struct ptp_clock_event event;
@@ -729,6 +729,16 @@ static int decode_evnt(struct dp83640_private *dp83640,
         int words = (ests >> EVNT_TS_LEN_SHIFT) & EVNT_TS_LEN_MASK;
         u16 ext_status = 0;
 
+        /* calculate length of the event timestamp status message */
+        if (ests & MULT_EVNT)
+                parsed = (words + 2) * sizeof(u16);
+        else
+                parsed = (words + 1) * sizeof(u16);
+
+        /* check if enough data is available */
+        if (len < parsed)
+                return len;
+
         if (ests & MULT_EVNT) {
                 ext_status = *(u16 *) data;
                 data += sizeof(ext_status);
@@ -747,10 +757,7 @@ static int decode_evnt(struct dp83640_private *dp83640,
                 dp83640->edata.ns_lo = phy_txts->ns_lo;
         }
 
-        if (ext_status) {
-                parsed = words + 2;
-        } else {
-                parsed = words + 1;
+        if (!ext_status) {
                 i = ((ests >> EVNT_NUM_SHIFT) & EVNT_NUM_MASK) - EXT_EVENT;
                 ext_status = exts_chan_to_edata(i);
         }
@@ -768,7 +775,7 @@ static int decode_evnt(struct dp83640_private *dp83640,
                 }
         }
 
-        return parsed * sizeof(u16);
+        return parsed;
 }
 
 static int match(struct sk_buff *skb, unsigned int type, struct rxts *rxts)
@@ -905,9 +912,9 @@ static void decode_status_frame(struct dp83640_private *dp83640,
                         decode_txts(dp83640, phy_txts);
                         size = sizeof(*phy_txts);
 
-                } else if (PSF_EVNT == type && len >= sizeof(*phy_txts)) {
+                } else if (PSF_EVNT == type) {
 
-                        size = decode_evnt(dp83640, ptr, ests);
+                        size = decode_evnt(dp83640, ptr, len, ests);
 
                 } else {
                         size = 0;
@@ -1141,7 +1148,7 @@ static void dp83640_remove(struct phy_device *phydev)
                 kfree_skb(skb);
 
         while ((skb = skb_dequeue(&dp83640->tx_queue)) != NULL)
-                skb_complete_tx_timestamp(skb, NULL);
+                kfree_skb(skb);
 
         clock = dp83640_clock_get(dp83640->clock);
 
@@ -1398,7 +1405,7 @@ static void dp83640_txtstamp(struct phy_device *phydev,
 
         case HWTSTAMP_TX_ONESTEP_SYNC:
                 if (is_sync(skb, type)) {
-                        skb_complete_tx_timestamp(skb, NULL);
+                        kfree_skb(skb);
                         return;
                 }
                 /* fall through */
@@ -1409,7 +1416,7 @@ static void dp83640_txtstamp(struct phy_device *phydev,
 
         case HWTSTAMP_TX_OFF:
         default:
-                skb_complete_tx_timestamp(skb, NULL);
+                kfree_skb(skb);
                 break;
         }
 }
diff --git a/drivers/net/phy/fixed.c b/drivers/net/phy/fixed.c
index d60d875cb445..5b19fbbda6d4 100644
--- a/drivers/net/phy/fixed.c
+++ b/drivers/net/phy/fixed.c
@@ -124,6 +124,17 @@ static int fixed_mdio_read(struct mii_bus *bus, int phy_addr, int reg_num)
         if (reg_num >= MII_REGS_NUM)
                 return -1;
 
+        /* We do not support emulating Clause 45 over Clause 22 register reads
+         * return an error instead of bogus data.
+         */
+        switch (reg_num) {
+        case MII_MMD_CTRL:
+        case MII_MMD_DATA:
+                return -1;
+        default:
+                break;
+        }
+
         list_for_each_entry(fp, &fmb->phys, node) {
                 if (fp->addr == phy_addr) {
                         /* Issue callback if user registered it. */
diff --git a/drivers/net/phy/mdio-bcm-unimac.c b/drivers/net/phy/mdio-bcm-unimac.c
new file mode 100644
index 000000000000..5b643e588e8f
--- /dev/null
+++ b/drivers/net/phy/mdio-bcm-unimac.c
@@ -0,0 +1,213 @@
+/*
+ * Broadcom UniMAC MDIO bus controller driver
+ *
+ * Copyright (C) 2014, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/phy.h>
+#include <linux/platform_device.h>
+#include <linux/sched.h>
+#include <linux/module.h>
+#include <linux/io.h>
+#include <linux/delay.h>
+
+#include <linux/of.h>
+#include <linux/of_platform.h>
+#include <linux/of_mdio.h>
+
+#define MDIO_CMD                0x00
+#define  MDIO_START_BUSY        (1 << 29)
+#define  MDIO_READ_FAIL         (1 << 28)
+#define  MDIO_RD                (2 << 26)
+#define  MDIO_WR                (1 << 26)
+#define  MDIO_PMD_SHIFT         21
+#define  MDIO_PMD_MASK          0x1F
+#define  MDIO_REG_SHIFT         16
+#define  MDIO_REG_MASK          0x1F
+
+#define MDIO_CFG                0x04
+#define  MDIO_C22               (1 << 0)
+#define  MDIO_C45               0
+#define  MDIO_CLK_DIV_SHIFT     4
+#define  MDIO_CLK_DIV_MASK      0x3F
+#define  MDIO_SUPP_PREAMBLE     (1 << 12)
+
+struct unimac_mdio_priv {
+        struct mii_bus          *mii_bus;
+        void __iomem            *base;
+};
+
+static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
+{
+        u32 reg;
+
+        reg = __raw_readl(priv->base + MDIO_CMD);
+        reg |= MDIO_START_BUSY;
+        __raw_writel(reg, priv->base + MDIO_CMD);
+}
+
+static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
+{
+        return __raw_readl(priv->base + MDIO_CMD) & MDIO_START_BUSY;
+}
+
+static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
+{
+        struct unimac_mdio_priv *priv = bus->priv;
+        unsigned int timeout = 1000;
+        u32 cmd;
+
+        /* Prepare the read operation */
+        cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
+        __raw_writel(cmd, priv->base + MDIO_CMD);
+
+        /* Start MDIO transaction */
+        unimac_mdio_start(priv);
+
+        do {
+                if (!unimac_mdio_busy(priv))
+                        break;
+
+                usleep_range(1000, 2000);
+        } while (timeout--);
+
+        if (!timeout)
+                return -ETIMEDOUT;
+
+        cmd = __raw_readl(priv->base + MDIO_CMD);
+        if (cmd & MDIO_READ_FAIL)
+                return -EIO;
+
+        return cmd & 0xffff;
+}
+
+static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
+                             int reg, u16 val)
+{
+        struct unimac_mdio_priv *priv = bus->priv;
+        unsigned int timeout = 1000;
+        u32 cmd;
+
+        /* Prepare the write operation */
+        cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
+                (reg << MDIO_REG_SHIFT) | (0xffff & val);
+        __raw_writel(cmd, priv->base + MDIO_CMD);
+
+        unimac_mdio_start(priv);
+
+        do {
+                if (!unimac_mdio_busy(priv))
+                        break;
+
+                usleep_range(1000, 2000);
+        } while (timeout--);
+
+        if (!timeout)
+                return -ETIMEDOUT;
+
+        return 0;
+}
+
+static int unimac_mdio_probe(struct platform_device *pdev)
+{
+        struct unimac_mdio_priv *priv;
+        struct device_node *np;
+        struct mii_bus *bus;
+        struct resource *r;
+        int ret;
+
+        np = pdev->dev.of_node;
+
+        priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
+        if (!priv)
+                return -ENOMEM;
+
+        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+        /* Just ioremap, as this MDIO block is usually integrated into an
+         * Ethernet MAC controller register range
+         */
+        priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
+        if (!priv->base) {
+                dev_err(&pdev->dev, "failed to remap register\n");
+                return -ENOMEM;
+        }
+
+        priv->mii_bus = mdiobus_alloc();
+        if (!priv->mii_bus)
+                return -ENOMEM;
+
+        bus = priv->mii_bus;
+        bus->priv = priv;
+        bus->name = "unimac MII bus";
+        bus->parent = &pdev->dev;
+        bus->read = unimac_mdio_read;
+        bus->write = unimac_mdio_write;
+        snprintf(bus->id, MII_BUS_ID_SIZE, "%s", pdev->name);
+
+        bus->irq = kcalloc(PHY_MAX_ADDR, sizeof(int), GFP_KERNEL);
+        if (!bus->irq) {
+                ret = -ENOMEM;
+                goto out_mdio_free;
+        }
+
+        ret = of_mdiobus_register(bus, np);
+        if (ret) {
+                dev_err(&pdev->dev, "MDIO bus registration failed\n");
+                goto out_mdio_irq;
+        }
+
+        platform_set_drvdata(pdev, priv);
+
+        dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus at 0x%p\n", priv->base);
+
+        return 0;
+
+out_mdio_irq:
+        kfree(bus->irq);
+out_mdio_free:
+        mdiobus_free(bus);
+        return ret;
+}
+
+static int unimac_mdio_remove(struct platform_device *pdev)
+{
+        struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
+
+        mdiobus_unregister(priv->mii_bus);
+        kfree(priv->mii_bus->irq);
+        mdiobus_free(priv->mii_bus);
+
+        return 0;
+}
+
+static struct of_device_id unimac_mdio_ids[] = {
+        { .compatible = "brcm,genet-mdio-v4", },
+        { .compatible = "brcm,genet-mdio-v3", },
+        { .compatible = "brcm,genet-mdio-v2", },
+        { .compatible = "brcm,genet-mdio-v1", },
+        { .compatible = "brcm,unimac-mdio", },
+        { /* sentinel */ },
+};
+
+static struct platform_driver unimac_mdio_driver = {
+        .driver = {
+                .name = "unimac-mdio",
+                .owner = THIS_MODULE,
+                .of_match_table = unimac_mdio_ids,
+        },
+        .probe  = unimac_mdio_probe,
+        .remove = unimac_mdio_remove,
+};
+module_platform_driver(unimac_mdio_driver);
+
+MODULE_AUTHOR("Broadcom Corporation");
+MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
+MODULE_LICENSE("GPL");
+MODULE_ALIAS("platform:unimac-mdio");
diff --git a/drivers/net/phy/mdio_bus.c b/drivers/net/phy/mdio_bus.c
index 4eaadcfcb0fe..50051f271b10 100644
--- a/drivers/net/phy/mdio_bus.c
+++ b/drivers/net/phy/mdio_bus.c
@@ -553,8 +553,14 @@ static ssize_t
 phy_interface_show(struct device *dev, struct device_attribute *attr, char *buf)
 {
         struct phy_device *phydev = to_phy_device(dev);
+        const char *mode = NULL;
 
-        return sprintf(buf, "%s\n", phy_modes(phydev->interface));
+        if (phy_is_internal(phydev))
+                mode = "internal";
+        else
+                mode = phy_modes(phydev->interface);
+
+        return sprintf(buf, "%s\n", mode);
 }
 static DEVICE_ATTR_RO(phy_interface);
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index a854d38c231d..1dfffdc9dfc3 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -955,7 +955,7 @@ static inline void mmd_phy_indirect(struct mii_bus *bus, int prtad, int devad,
  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
  * 3) Read  reg 14 // Read MMD data
  */
-static int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
+int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
                                  int devad, int addr)
 {
         struct phy_driver *phydrv = phydev->drv;
@@ -971,6 +971,7 @@ static int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
         }
         return value;
 }
+EXPORT_SYMBOL(phy_read_mmd_indirect);
 
 /**
  * phy_write_mmd_indirect - writes data to the MMD registers
@@ -988,7 +989,7 @@ static int phy_read_mmd_indirect(struct phy_device *phydev, int prtad,
  * 3) Write reg 13 // MMD Data Command for MMD DEVAD
  * 3) Write reg 14 // Write MMD data
  */
-static void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
+void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
                                    int devad, int addr, u32 data)
 {
         struct phy_driver *phydrv = phydev->drv;
@@ -1002,6 +1003,7 @@ static void phy_write_mmd_indirect(struct phy_device *phydev, int prtad,
                 phydrv->write_mmd_indirect(phydev, prtad, devad, addr, data);
         }
 }
+EXPORT_SYMBOL(phy_write_mmd_indirect);
 
 /**
  * phy_init_eee - init and check the EEE feature
@@ -1017,12 +1019,14 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
 {
         /* According to 802.3az,the EEE is supported only in full duplex-mode.
          * Also EEE feature is active when core is operating with MII, GMII
-         * or RGMII.
+         * or RGMII. Internal PHYs are also allowed to proceed and should
+         * return an error if they do not support EEE.
          */
         if ((phydev->duplex == DUPLEX_FULL) &&
             ((phydev->interface == PHY_INTERFACE_MODE_MII) ||
             (phydev->interface == PHY_INTERFACE_MODE_GMII) ||
-            (phydev->interface == PHY_INTERFACE_MODE_RGMII))) {
+            (phydev->interface == PHY_INTERFACE_MODE_RGMII) ||
+             phy_is_internal(phydev))) {
                 int eee_lp, eee_cap, eee_adv;
                 u32 lp, cap, adv;
                 int status;
diff --git a/drivers/net/phy/phy_device.c b/drivers/net/phy/phy_device.c
index ca5ec3e18d36..3fc91e89f5a5 100644
--- a/drivers/net/phy/phy_device.c
+++ b/drivers/net/phy/phy_device.c
@@ -230,13 +230,13 @@ static int get_phy_c45_ids(struct mii_bus *bus, int addr, u32 *phy_id,
         for (i = 1;
              i < num_ids && c45_ids->devices_in_package == 0;
              i++) {
-                reg_addr = MII_ADDR_C45 | i << 16 | 6;
+                reg_addr = MII_ADDR_C45 | i << 16 | MDIO_DEVS2;
                 phy_reg = mdiobus_read(bus, addr, reg_addr);
                 if (phy_reg < 0)
                         return -EIO;
                 c45_ids->devices_in_package = (phy_reg & 0xffff) << 16;
 
-                reg_addr = MII_ADDR_C45 | i << 16 | 5;
+                reg_addr = MII_ADDR_C45 | i << 16 | MDIO_DEVS1;
                 phy_reg = mdiobus_read(bus, addr, reg_addr);
                 if (phy_reg < 0)
                         return -EIO;
diff --git a/drivers/net/sungem_phy.c b/drivers/net/sungem_phy.c
index ae7cd7f3656d..92578d72e4ee 100644
--- a/drivers/net/sungem_phy.c
+++ b/drivers/net/sungem_phy.c
@@ -47,22 +47,22 @@ static const int phy_BCM5400_link_table[8][3] = {
         { 1, 0, 1 },    /* 1000BT */
 };
 
-static inline int __phy_read(struct mii_phy* phy, int id, int reg)
+static inline int __sungem_phy_read(struct mii_phy* phy, int id, int reg)
 {
         return phy->mdio_read(phy->dev, id, reg);
 }
 
-static inline void __phy_write(struct mii_phy* phy, int id, int reg, int val)
+static inline void __sungem_phy_write(struct mii_phy* phy, int id, int reg, int val)
 {
         phy->mdio_write(phy->dev, id, reg, val);
 }
 
-static inline int phy_read(struct mii_phy* phy, int reg)
+static inline int sungem_phy_read(struct mii_phy* phy, int reg)
 {
         return phy->mdio_read(phy->dev, phy->mii_id, reg);
 }
 
-static inline void phy_write(struct mii_phy* phy, int reg, int val)
+static inline void sungem_phy_write(struct mii_phy* phy, int reg, int val)
 {
         phy->mdio_write(phy->dev, phy->mii_id, reg, val);
 }
@@ -72,21 +72,21 @@ static int reset_one_mii_phy(struct mii_phy* phy, int phy_id)
         u16 val;
         int limit = 10000;
 
-        val = __phy_read(phy, phy_id, MII_BMCR);
+        val = __sungem_phy_read(phy, phy_id, MII_BMCR);
         val &= ~(BMCR_ISOLATE | BMCR_PDOWN);
         val |= BMCR_RESET;
-        __phy_write(phy, phy_id, MII_BMCR, val);
+        __sungem_phy_write(phy, phy_id, MII_BMCR, val);
 
         udelay(100);
 
         while (--limit) {
-                val = __phy_read(phy, phy_id, MII_BMCR);
+                val = __sungem_phy_read(phy, phy_id, MII_BMCR);
                 if ((val & BMCR_RESET) == 0)
                         break;
                 udelay(10);
         }
         if ((val & BMCR_ISOLATE) && limit > 0)
-                __phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
+                __sungem_phy_write(phy, phy_id, MII_BMCR, val & ~BMCR_ISOLATE);
 
         return limit <= 0;
 }
@@ -95,19 +95,19 @@ static int bcm5201_init(struct mii_phy* phy)
 {
         u16 data;
 
-        data = phy_read(phy, MII_BCM5201_MULTIPHY);
+        data = sungem_phy_read(phy, MII_BCM5201_MULTIPHY);
         data &= ~MII_BCM5201_MULTIPHY_SUPERISOLATE;
-        phy_write(phy, MII_BCM5201_MULTIPHY, data);
+        sungem_phy_write(phy, MII_BCM5201_MULTIPHY, data);
 
-        phy_write(phy, MII_BCM5201_INTERRUPT, 0);
+        sungem_phy_write(phy, MII_BCM5201_INTERRUPT, 0);
 
         return 0;
 }
 
 static int bcm5201_suspend(struct mii_phy* phy)
 {
-        phy_write(phy, MII_BCM5201_INTERRUPT, 0);
-        phy_write(phy, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
+        sungem_phy_write(phy, MII_BCM5201_INTERRUPT, 0);
+        sungem_phy_write(phy, MII_BCM5201_MULTIPHY, MII_BCM5201_MULTIPHY_SUPERISOLATE);
 
         return 0;
 }
@@ -116,20 +116,20 @@ static int bcm5221_init(struct mii_phy* phy)
 {
         u16 data;
 
-        data = phy_read(phy, MII_BCM5221_TEST);
-        phy_write(phy, MII_BCM5221_TEST,
+        data = sungem_phy_read(phy, MII_BCM5221_TEST);
+        sungem_phy_write(phy, MII_BCM5221_TEST,
                 data | MII_BCM5221_TEST_ENABLE_SHADOWS);
 
-        data = phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
-        phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
+        data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
+        sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
                 data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
 
-        data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
-        phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
+        data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
+        sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
                 data | MII_BCM5221_SHDOW_AUX_MODE4_CLKLOPWR);
 
-        data = phy_read(phy, MII_BCM5221_TEST);
-        phy_write(phy, MII_BCM5221_TEST,
+        data = sungem_phy_read(phy, MII_BCM5221_TEST);
+        sungem_phy_write(phy, MII_BCM5221_TEST,
                 data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
 
         return 0;
@@ -139,12 +139,12 @@ static int bcm5221_suspend(struct mii_phy* phy)
 {
         u16 data;
 
-        data = phy_read(phy, MII_BCM5221_TEST);
-        phy_write(phy, MII_BCM5221_TEST,
+        data = sungem_phy_read(phy, MII_BCM5221_TEST);
+        sungem_phy_write(phy, MII_BCM5221_TEST,
                 data | MII_BCM5221_TEST_ENABLE_SHADOWS);
 
-        data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
-        phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
+        data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
+        sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
                   data | MII_BCM5221_SHDOW_AUX_MODE4_IDDQMODE);
 
         return 0;
@@ -154,20 +154,20 @@ static int bcm5241_init(struct mii_phy* phy)
 {
         u16 data;
 
-        data = phy_read(phy, MII_BCM5221_TEST);
-        phy_write(phy, MII_BCM5221_TEST,
+        data = sungem_phy_read(phy, MII_BCM5221_TEST);
+        sungem_phy_write(phy, MII_BCM5221_TEST,
                 data | MII_BCM5221_TEST_ENABLE_SHADOWS);
 
-        data = phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
-        phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
+        data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_STAT2);
+        sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_STAT2,
                 data | MII_BCM5221_SHDOW_AUX_STAT2_APD);
 
-        data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
-        phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
+        data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
+        sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
                 data & ~MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
 
-        data = phy_read(phy, MII_BCM5221_TEST);
-        phy_write(phy, MII_BCM5221_TEST,
+        data = sungem_phy_read(phy, MII_BCM5221_TEST);
+        sungem_phy_write(phy, MII_BCM5221_TEST,
                 data & ~MII_BCM5221_TEST_ENABLE_SHADOWS);
 
         return 0;
@@ -177,12 +177,12 @@ static int bcm5241_suspend(struct mii_phy* phy)
 {
         u16 data;
 
-        data = phy_read(phy, MII_BCM5221_TEST);
-        phy_write(phy, MII_BCM5221_TEST,
+        data = sungem_phy_read(phy, MII_BCM5221_TEST);
+        sungem_phy_write(phy, MII_BCM5221_TEST,
                 data | MII_BCM5221_TEST_ENABLE_SHADOWS);
 
-        data = phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
-        phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
+        data = sungem_phy_read(phy, MII_BCM5221_SHDOW_AUX_MODE4);
+        sungem_phy_write(phy, MII_BCM5221_SHDOW_AUX_MODE4,
                   data | MII_BCM5241_SHDOW_AUX_MODE4_STANDBYPWR);
 
         return 0;
@@ -193,26 +193,26 @@ static int bcm5400_init(struct mii_phy* phy)
         u16 data;
 
         /* Configure for gigabit full duplex */
-        data = phy_read(phy, MII_BCM5400_AUXCONTROL);
+        data = sungem_phy_read(phy, MII_BCM5400_AUXCONTROL);
         data |= MII_BCM5400_AUXCONTROL_PWR10BASET;
-        phy_write(phy, MII_BCM5400_AUXCONTROL, data);
+        sungem_phy_write(phy, MII_BCM5400_AUXCONTROL, data);
 
-        data = phy_read(phy, MII_BCM5400_GB_CONTROL);
+        data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
         data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
-        phy_write(phy, MII_BCM5400_GB_CONTROL, data);
+        sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
 
         udelay(100);
 
         /* Reset and configure cascaded 10/100 PHY */
         (void)reset_one_mii_phy(phy, 0x1f);
 
-        data = __phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
+        data = __sungem_phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
         data |= MII_BCM5201_MULTIPHY_SERIALMODE;
-        __phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
+        __sungem_phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
 
-        data = phy_read(phy, MII_BCM5400_AUXCONTROL);
+        data = sungem_phy_read(phy, MII_BCM5400_AUXCONTROL);
         data &= ~MII_BCM5400_AUXCONTROL_PWR10BASET;
-        phy_write(phy, MII_BCM5400_AUXCONTROL, data);
+        sungem_phy_write(phy, MII_BCM5400_AUXCONTROL, data);
 
         return 0;
 }
@@ -220,7 +220,7 @@ static int bcm5400_init(struct mii_phy* phy)
 static int bcm5400_suspend(struct mii_phy* phy)
 {
 #if 0 /* Commented out in Darwin... someone has those dawn docs ? */
-        phy_write(phy, MII_BMCR, BMCR_PDOWN);
+        sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
 #endif
         return 0;
 }
@@ -230,7 +230,7 @@ static int bcm5401_init(struct mii_phy* phy)
         u16 data;
         int rev;
 
-        rev = phy_read(phy, MII_PHYSID2) & 0x000f;
+        rev = sungem_phy_read(phy, MII_PHYSID2) & 0x000f;
         if (rev == 0 || rev == 3) {
                 /* Some revisions of 5401 appear to need this
                  * initialisation sequence to disable, according
@@ -243,32 +243,32 @@ static int bcm5401_init(struct mii_phy* phy)
                  * Note: This should (and does) match tg3_init_5401phy_dsp
                  *       in the tg3.c driver. -DaveM
                  */
-                phy_write(phy, 0x18, 0x0c20);
-                phy_write(phy, 0x17, 0x0012);
-                phy_write(phy, 0x15, 0x1804);
-                phy_write(phy, 0x17, 0x0013);
-                phy_write(phy, 0x15, 0x1204);
-                phy_write(phy, 0x17, 0x8006);
-                phy_write(phy, 0x15, 0x0132);
-                phy_write(phy, 0x17, 0x8006);
-                phy_write(phy, 0x15, 0x0232);
-                phy_write(phy, 0x17, 0x201f);
-                phy_write(phy, 0x15, 0x0a20);
+                sungem_phy_write(phy, 0x18, 0x0c20);
+                sungem_phy_write(phy, 0x17, 0x0012);
+                sungem_phy_write(phy, 0x15, 0x1804);
+                sungem_phy_write(phy, 0x17, 0x0013);
+                sungem_phy_write(phy, 0x15, 0x1204);
+                sungem_phy_write(phy, 0x17, 0x8006);
+                sungem_phy_write(phy, 0x15, 0x0132);
+                sungem_phy_write(phy, 0x17, 0x8006);
+                sungem_phy_write(phy, 0x15, 0x0232);
+                sungem_phy_write(phy, 0x17, 0x201f);
+                sungem_phy_write(phy, 0x15, 0x0a20);
         }
 
         /* Configure for gigabit full duplex */
-        data = phy_read(phy, MII_BCM5400_GB_CONTROL);
+        data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
         data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
-        phy_write(phy, MII_BCM5400_GB_CONTROL, data);
+        sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
 
         udelay(10);
 
         /* Reset and configure cascaded 10/100 PHY */
         (void)reset_one_mii_phy(phy, 0x1f);
 
-        data = __phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
+        data = __sungem_phy_read(phy, 0x1f, MII_BCM5201_MULTIPHY);
         data |= MII_BCM5201_MULTIPHY_SERIALMODE;
-        __phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
+        __sungem_phy_write(phy, 0x1f, MII_BCM5201_MULTIPHY, data);
 
         return 0;
 }
@@ -276,7 +276,7 @@ static int bcm5401_init(struct mii_phy* phy)
 static int bcm5401_suspend(struct mii_phy* phy)
 {
 #if 0 /* Commented out in Darwin... someone has those dawn docs ? */
-        phy_write(phy, MII_BMCR, BMCR_PDOWN);
+        sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
 #endif
         return 0;
 }
@@ -288,19 +288,19 @@ static int bcm5411_init(struct mii_phy* phy)
         /* Here's some more Apple black magic to setup
          * some voltage stuffs.
          */
-        phy_write(phy, 0x1c, 0x8c23);
-        phy_write(phy, 0x1c, 0x8ca3);
-        phy_write(phy, 0x1c, 0x8c23);
+        sungem_phy_write(phy, 0x1c, 0x8c23);
+        sungem_phy_write(phy, 0x1c, 0x8ca3);
+        sungem_phy_write(phy, 0x1c, 0x8c23);
 
         /* Here, Apple seems to want to reset it, do
          * it as well
          */
-        phy_write(phy, MII_BMCR, BMCR_RESET);
-        phy_write(phy, MII_BMCR, 0x1340);
+        sungem_phy_write(phy, MII_BMCR, BMCR_RESET);
+        sungem_phy_write(phy, MII_BMCR, 0x1340);
 
-        data = phy_read(phy, MII_BCM5400_GB_CONTROL);
+        data = sungem_phy_read(phy, MII_BCM5400_GB_CONTROL);
         data |= MII_BCM5400_GB_CONTROL_FULLDUPLEXCAP;
-        phy_write(phy, MII_BCM5400_GB_CONTROL, data);
+        sungem_phy_write(phy, MII_BCM5400_GB_CONTROL, data);
 
         udelay(10);
 
@@ -321,7 +321,7 @@ static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
         phy->advertising = advertise;
 
         /* Setup standard advertise */
-        adv = phy_read(phy, MII_ADVERTISE);
+        adv = sungem_phy_read(phy, MII_ADVERTISE);
         adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
         if (advertise & ADVERTISED_10baseT_Half)
                 adv |= ADVERTISE_10HALF;
@@ -331,12 +331,12 @@ static int genmii_setup_aneg(struct mii_phy *phy, u32 advertise)
                 adv |= ADVERTISE_100HALF;
         if (advertise & ADVERTISED_100baseT_Full)
                 adv |= ADVERTISE_100FULL;
-        phy_write(phy, MII_ADVERTISE, adv);
+        sungem_phy_write(phy, MII_ADVERTISE, adv);
 
         /* Start/Restart aneg */
-        ctl = phy_read(phy, MII_BMCR);
+        ctl = sungem_phy_read(phy, MII_BMCR);
         ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
-        phy_write(phy, MII_BMCR, ctl);
+        sungem_phy_write(phy, MII_BMCR, ctl);
 
         return 0;
 }
@@ -350,11 +350,11 @@ static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
         phy->duplex = fd;
         phy->pause = 0;
 
-        ctl = phy_read(phy, MII_BMCR);
+        ctl = sungem_phy_read(phy, MII_BMCR);
         ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_ANENABLE);
 
         /* First reset the PHY */
-        phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
+        sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
 
         /* Select speed & duplex */
         switch(speed) {
@@ -369,7 +369,7 @@ static int genmii_setup_forced(struct mii_phy *phy, int speed, int fd)
         }
         if (fd == DUPLEX_FULL)
                 ctl |= BMCR_FULLDPLX;
-        phy_write(phy, MII_BMCR, ctl);
+        sungem_phy_write(phy, MII_BMCR, ctl);
 
         return 0;
 }
@@ -378,8 +378,8 @@ static int genmii_poll_link(struct mii_phy *phy)
 {
         u16 status;
 
-        (void)phy_read(phy, MII_BMSR);
-        status = phy_read(phy, MII_BMSR);
+        (void)sungem_phy_read(phy, MII_BMSR);
+        status = sungem_phy_read(phy, MII_BMSR);
         if ((status & BMSR_LSTATUS) == 0)
                 return 0;
         if (phy->autoneg && !(status & BMSR_ANEGCOMPLETE))
@@ -392,7 +392,7 @@ static int genmii_read_link(struct mii_phy *phy)
         u16 lpa;
 
         if (phy->autoneg) {
-                lpa = phy_read(phy, MII_LPA);
+                lpa = sungem_phy_read(phy, MII_LPA);
 
                 if (lpa & (LPA_10FULL | LPA_100FULL))
                         phy->duplex = DUPLEX_FULL;
@@ -413,7 +413,7 @@ static int genmii_read_link(struct mii_phy *phy)
 
 static int generic_suspend(struct mii_phy* phy)
 {
-        phy_write(phy, MII_BMCR, BMCR_PDOWN);
+        sungem_phy_write(phy, MII_BMCR, BMCR_PDOWN);
 
         return 0;
 }
@@ -423,27 +423,27 @@ static int bcm5421_init(struct mii_phy* phy)
         u16 data;
         unsigned int id;
 
-        id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2));
+        id = (sungem_phy_read(phy, MII_PHYSID1) << 16 | sungem_phy_read(phy, MII_PHYSID2));
 
         /* Revision 0 of 5421 needs some fixups */
         if (id == 0x002060e0) {
                 /* This is borrowed from MacOS
                  */
-                phy_write(phy, 0x18, 0x1007);
-                data = phy_read(phy, 0x18);
-                phy_write(phy, 0x18, data | 0x0400);
-                phy_write(phy, 0x18, 0x0007);
-                data = phy_read(phy, 0x18);
-                phy_write(phy, 0x18, data | 0x0800);
-                phy_write(phy, 0x17, 0x000a);
-                data = phy_read(phy, 0x15);
-                phy_write(phy, 0x15, data | 0x0200);
+                sungem_phy_write(phy, 0x18, 0x1007);
+                data = sungem_phy_read(phy, 0x18);
+                sungem_phy_write(phy, 0x18, data | 0x0400);
+                sungem_phy_write(phy, 0x18, 0x0007);
+                data = sungem_phy_read(phy, 0x18);
+                sungem_phy_write(phy, 0x18, data | 0x0800);
+                sungem_phy_write(phy, 0x17, 0x000a);
+                data = sungem_phy_read(phy, 0x15);
+                sungem_phy_write(phy, 0x15, data | 0x0200);
         }
 
         /* Pick up some init code from OF for K2 version */
         if ((id & 0xfffffff0) == 0x002062e0) {
-                phy_write(phy, 4, 0x01e1);
-                phy_write(phy, 9, 0x0300);
+                sungem_phy_write(phy, 4, 0x01e1);
+                sungem_phy_write(phy, 9, 0x0300);
         }
 
         /* Check if we can enable automatic low power */
@@ -455,9 +455,9 @@ static int bcm5421_init(struct mii_phy* phy)
                         can_low_power = 0;
                 if (can_low_power) {
                         /* Enable automatic low-power */
-                        phy_write(phy, 0x1c, 0x9002);
-                        phy_write(phy, 0x1c, 0xa821);
-                        phy_write(phy, 0x1c, 0x941d);
+                        sungem_phy_write(phy, 0x1c, 0x9002);
+                        sungem_phy_write(phy, 0x1c, 0xa821);
+                        sungem_phy_write(phy, 0x1c, 0x941d);
                 }
         }
 #endif /* CONFIG_PPC_PMAC */
@@ -476,7 +476,7 @@ static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
         phy->advertising = advertise;
 
         /* Setup standard advertise */
-        adv = phy_read(phy, MII_ADVERTISE);
+        adv = sungem_phy_read(phy, MII_ADVERTISE);
         adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
         if (advertise & ADVERTISED_10baseT_Half)
                 adv |= ADVERTISE_10HALF;
@@ -490,21 +490,21 @@ static int bcm54xx_setup_aneg(struct mii_phy *phy, u32 advertise)
                 adv |= ADVERTISE_PAUSE_CAP;
         if (advertise & ADVERTISED_Asym_Pause)
                 adv |= ADVERTISE_PAUSE_ASYM;
-        phy_write(phy, MII_ADVERTISE, adv);
+        sungem_phy_write(phy, MII_ADVERTISE, adv);
 
         /* Setup 1000BT advertise */
-        adv = phy_read(phy, MII_1000BASETCONTROL);
+        adv = sungem_phy_read(phy, MII_1000BASETCONTROL);
         adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP|MII_1000BASETCONTROL_HALFDUPLEXCAP);
         if (advertise & SUPPORTED_1000baseT_Half)
                 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
         if (advertise & SUPPORTED_1000baseT_Full)
                 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
-        phy_write(phy, MII_1000BASETCONTROL, adv);
+        sungem_phy_write(phy, MII_1000BASETCONTROL, adv);
 
         /* Start/Restart aneg */
-        ctl = phy_read(phy, MII_BMCR);
+        ctl = sungem_phy_read(phy, MII_BMCR);
         ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
-        phy_write(phy, MII_BMCR, ctl);
+        sungem_phy_write(phy, MII_BMCR, ctl);
 
         return 0;
 }
@@ -518,11 +518,11 @@ static int bcm54xx_setup_forced(struct mii_phy *phy, int speed, int fd)
         phy->duplex = fd;
         phy->pause = 0;
 
-        ctl = phy_read(phy, MII_BMCR);
+        ctl = sungem_phy_read(phy, MII_BMCR);
         ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
 
         /* First reset the PHY */
-        phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
+        sungem_phy_write(phy, MII_BMCR, ctl | BMCR_RESET);
 
         /* Select speed & duplex */
         switch(speed) {
@@ -539,7 +539,7 @@ static int bcm54xx_setup_forced(struct mii_phy *phy, int speed, int fd)
 
         // XXX Should we set the sungem to GII now on 1000BT ?
 
-        phy_write(phy, MII_BMCR, ctl);
+        sungem_phy_write(phy, MII_BMCR, ctl);
 
         return 0;
 }
@@ -550,7 +550,7 @@ static int bcm54xx_read_link(struct mii_phy *phy)
         u16 val;
 
         if (phy->autoneg) {
-                val = phy_read(phy, MII_BCM5400_AUXSTATUS);
+                val = sungem_phy_read(phy, MII_BCM5400_AUXSTATUS);
                 link_mode = ((val & MII_BCM5400_AUXSTATUS_LINKMODE_MASK) >>
                              MII_BCM5400_AUXSTATUS_LINKMODE_SHIFT);
                 phy->duplex = phy_BCM5400_link_table[link_mode][0] ?
@@ -559,7 +559,7 @@ static int bcm54xx_read_link(struct mii_phy *phy)
                                 SPEED_1000 :
                                 (phy_BCM5400_link_table[link_mode][1] ?
                                  SPEED_100 : SPEED_10);
-                val = phy_read(phy, MII_LPA);
+                val = sungem_phy_read(phy, MII_LPA);
                 phy->pause = (phy->duplex == DUPLEX_FULL) &&
                         ((val & LPA_PAUSE) != 0);
         }
@@ -575,19 +575,19 @@ static int marvell88e1111_init(struct mii_phy* phy)
         u16 rev;
 
         /* magic init sequence for rev 0 */
-        rev = phy_read(phy, MII_PHYSID2) & 0x000f;
+        rev = sungem_phy_read(phy, MII_PHYSID2) & 0x000f;
         if (rev == 0) {
-                phy_write(phy, 0x1d, 0x000a);
-                phy_write(phy, 0x1e, 0x0821);
+                sungem_phy_write(phy, 0x1d, 0x000a);
+                sungem_phy_write(phy, 0x1e, 0x0821);
 
-                phy_write(phy, 0x1d, 0x0006);
-                phy_write(phy, 0x1e, 0x8600);
+                sungem_phy_write(phy, 0x1d, 0x0006);
+                sungem_phy_write(phy, 0x1e, 0x8600);
 
-                phy_write(phy, 0x1d, 0x000b);
-                phy_write(phy, 0x1e, 0x0100);
+                sungem_phy_write(phy, 0x1d, 0x000b);
+                sungem_phy_write(phy, 0x1e, 0x0100);
 
-                phy_write(phy, 0x1d, 0x0004);
-                phy_write(phy, 0x1e, 0x4850);
+                sungem_phy_write(phy, 0x1d, 0x0004);
+                sungem_phy_write(phy, 0x1e, 0x4850);
         }
         return 0;
 }
@@ -600,8 +600,8 @@ static int bcm5421_poll_link(struct mii_phy* phy)
         int mode;
 
         /* find out in what mode we are */
-        phy_write(phy, MII_NCONFIG, 0x1000);
-        phy_reg = phy_read(phy, MII_NCONFIG);
+        sungem_phy_write(phy, MII_NCONFIG, 0x1000);
+        phy_reg = sungem_phy_read(phy, MII_NCONFIG);
 
         mode = (phy_reg & BCM5421_MODE_MASK) >> 5;
 
@@ -609,8 +609,8 @@ static int bcm5421_poll_link(struct mii_phy* phy)
                 return genmii_poll_link(phy);
 
         /* try to find out whether we have a link */
-        phy_write(phy, MII_NCONFIG, 0x2000);
-        phy_reg = phy_read(phy, MII_NCONFIG);
+        sungem_phy_write(phy, MII_NCONFIG, 0x2000);
+        phy_reg = sungem_phy_read(phy, MII_NCONFIG);
 
         if (phy_reg & 0x0020)
                 return 0;
@@ -624,8 +624,8 @@ static int bcm5421_read_link(struct mii_phy* phy)
         int mode;
 
         /* find out in what mode we are */
-        phy_write(phy, MII_NCONFIG, 0x1000);
-        phy_reg = phy_read(phy, MII_NCONFIG);
+        sungem_phy_write(phy, MII_NCONFIG, 0x1000);
+        phy_reg = sungem_phy_read(phy, MII_NCONFIG);
 
         mode = (phy_reg & BCM5421_MODE_MASK ) >> 5;
 
@@ -635,8 +635,8 @@ static int bcm5421_read_link(struct mii_phy* phy)
         phy->speed = SPEED_1000;
 
         /* find out whether we are running half- or full duplex */
-        phy_write(phy, MII_NCONFIG, 0x2000);
-        phy_reg = phy_read(phy, MII_NCONFIG);
+        sungem_phy_write(phy, MII_NCONFIG, 0x2000);
+        phy_reg = sungem_phy_read(phy, MII_NCONFIG);
 
         if ( (phy_reg & 0x0080) >> 7)
                 phy->duplex |=  DUPLEX_HALF;
@@ -649,14 +649,14 @@ static int bcm5421_read_link(struct mii_phy* phy)
 static int bcm5421_enable_fiber(struct mii_phy* phy, int autoneg)
 {
         /* enable fiber mode */
-        phy_write(phy, MII_NCONFIG, 0x9020);
+        sungem_phy_write(phy, MII_NCONFIG, 0x9020);
         /* LEDs active in both modes, autosense prio = fiber */
-        phy_write(phy, MII_NCONFIG, 0x945f);
+        sungem_phy_write(phy, MII_NCONFIG, 0x945f);
 
         if (!autoneg) {
                 /* switch off fibre autoneg */
-                phy_write(phy, MII_NCONFIG, 0xfc01);
-                phy_write(phy, 0x0b, 0x0004);
+                sungem_phy_write(phy, MII_NCONFIG, 0xfc01);
+                sungem_phy_write(phy, 0x0b, 0x0004);
         }
 
         phy->autoneg = autoneg;
@@ -673,8 +673,8 @@ static int bcm5461_poll_link(struct mii_phy* phy)
         int mode;
 
         /* find out in what mode we are */
-        phy_write(phy, MII_NCONFIG, 0x7c00);
-        phy_reg = phy_read(phy, MII_NCONFIG);
+        sungem_phy_write(phy, MII_NCONFIG, 0x7c00);
+        phy_reg = sungem_phy_read(phy, MII_NCONFIG);
 
         mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
 
@@ -682,8 +682,8 @@ static int bcm5461_poll_link(struct mii_phy* phy)
                 return genmii_poll_link(phy);
 
         /* find out whether we have a link */
-        phy_write(phy, MII_NCONFIG, 0x7000);
-        phy_reg = phy_read(phy, MII_NCONFIG);
+        sungem_phy_write(phy, MII_NCONFIG, 0x7000);
+        phy_reg = sungem_phy_read(phy, MII_NCONFIG);
 
         if (phy_reg & BCM5461_FIBER_LINK)
                 return 1;
@@ -699,8 +699,8 @@ static int bcm5461_read_link(struct mii_phy* phy)
         int mode;
 
         /* find out in what mode we are */
-        phy_write(phy, MII_NCONFIG, 0x7c00);
-        phy_reg = phy_read(phy, MII_NCONFIG);
+        sungem_phy_write(phy, MII_NCONFIG, 0x7c00);
+        phy_reg = sungem_phy_read(phy, MII_NCONFIG);
 
         mode = (phy_reg & BCM5461_MODE_MASK ) >> 1;
 
@@ -711,8 +711,8 @@ static int bcm5461_read_link(struct mii_phy* phy)
         phy->speed = SPEED_1000;
 
         /* find out whether we are running half- or full duplex */
-        phy_write(phy, MII_NCONFIG, 0x7000);
-        phy_reg = phy_read(phy, MII_NCONFIG);
+        sungem_phy_write(phy, MII_NCONFIG, 0x7000);
+        phy_reg = sungem_phy_read(phy, MII_NCONFIG);
 
         if (phy_reg & BCM5461_FIBER_DUPLEX)
                 phy->duplex |=  DUPLEX_FULL;
@@ -725,15 +725,15 @@ static int bcm5461_read_link(struct mii_phy* phy)
 static int bcm5461_enable_fiber(struct mii_phy* phy, int autoneg)
 {
         /* select fiber mode, enable 1000 base-X registers */
-        phy_write(phy, MII_NCONFIG, 0xfc0b);
+        sungem_phy_write(phy, MII_NCONFIG, 0xfc0b);
 
         if (autoneg) {
                 /* enable fiber with no autonegotiation */
-                phy_write(phy, MII_ADVERTISE, 0x01e0);
-                phy_write(phy, MII_BMCR, 0x1140);
+                sungem_phy_write(phy, MII_ADVERTISE, 0x01e0);
+                sungem_phy_write(phy, MII_BMCR, 0x1140);
         } else {
                 /* enable fiber with autonegotiation */
-                phy_write(phy, MII_BMCR, 0x0140);
+                sungem_phy_write(phy, MII_BMCR, 0x0140);
         }
 
         phy->autoneg = autoneg;
@@ -752,7 +752,7 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
         phy->advertising = advertise;
 
         /* Setup standard advertise */
-        adv = phy_read(phy, MII_ADVERTISE);
+        adv = sungem_phy_read(phy, MII_ADVERTISE);
         adv &= ~(ADVERTISE_ALL | ADVERTISE_100BASE4);
         if (advertise & ADVERTISED_10baseT_Half)
                 adv |= ADVERTISE_10HALF;
@@ -766,7 +766,7 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
                 adv |= ADVERTISE_PAUSE_CAP;
         if (advertise & ADVERTISED_Asym_Pause)
                 adv |= ADVERTISE_PAUSE_ASYM;
-        phy_write(phy, MII_ADVERTISE, adv);
+        sungem_phy_write(phy, MII_ADVERTISE, adv);
 
         /* Setup 1000BT advertise & enable crossover detect
          * XXX How do we advertise 1000BT ? Darwin source is
@@ -774,7 +774,7 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
          * write to control... Someone has specs for those
          * beasts ?
          */
-        adv = phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
+        adv = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
         adv |= MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX;
         adv &= ~(MII_1000BASETCONTROL_FULLDUPLEXCAP |
                         MII_1000BASETCONTROL_HALFDUPLEXCAP);
@@ -782,12 +782,12 @@ static int marvell_setup_aneg(struct mii_phy *phy, u32 advertise)
                 adv |= MII_1000BASETCONTROL_HALFDUPLEXCAP;
         if (advertise & SUPPORTED_1000baseT_Full)
                 adv |= MII_1000BASETCONTROL_FULLDUPLEXCAP;
-        phy_write(phy, MII_1000BASETCONTROL, adv);
+        sungem_phy_write(phy, MII_1000BASETCONTROL, adv);
 
         /* Start/Restart aneg */
-        ctl = phy_read(phy, MII_BMCR);
+        ctl = sungem_phy_read(phy, MII_BMCR);
         ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
-        phy_write(phy, MII_BMCR, ctl);
+        sungem_phy_write(phy, MII_BMCR, ctl);
 
         return 0;
 }
@@ -801,7 +801,7 @@ static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
         phy->duplex = fd;
         phy->pause = 0;
 
-        ctl = phy_read(phy, MII_BMCR);
+        ctl = sungem_phy_read(phy, MII_BMCR);
         ctl &= ~(BMCR_FULLDPLX|BMCR_SPEED100|BMCR_SPD2|BMCR_ANENABLE);
         ctl |= BMCR_RESET;
 
@@ -824,7 +824,7 @@ static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
         /* Disable crossover. Again, the way Apple does it is strange,
          * though I don't assume they are wrong ;)
          */
-        ctl2 = phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
+        ctl2 = sungem_phy_read(phy, MII_M1011_PHY_SPEC_CONTROL);
         ctl2 &= ~(MII_M1011_PHY_SPEC_CONTROL_MANUAL_MDIX |
                 MII_M1011_PHY_SPEC_CONTROL_AUTO_MDIX |
                 MII_1000BASETCONTROL_FULLDUPLEXCAP |
@@ -833,11 +833,11 @@ static int marvell_setup_forced(struct mii_phy *phy, int speed, int fd)
                 ctl2 |= (fd == DUPLEX_FULL) ?
                         MII_1000BASETCONTROL_FULLDUPLEXCAP :
                         MII_1000BASETCONTROL_HALFDUPLEXCAP;
-        phy_write(phy, MII_1000BASETCONTROL, ctl2);
+        sungem_phy_write(phy, MII_1000BASETCONTROL, ctl2);
 
         // XXX Should we set the sungem to GII now on 1000BT ?
 
-        phy_write(phy, MII_BMCR, ctl);
+        sungem_phy_write(phy, MII_BMCR, ctl);
 
         return 0;
 }
@@ -847,7 +847,7 @@ static int marvell_read_link(struct mii_phy *phy)
         u16 status, pmask;
 
         if (phy->autoneg) {
-                status = phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
+                status = sungem_phy_read(phy, MII_M1011_PHY_SPEC_STATUS);
                 if ((status & MII_M1011_PHY_SPEC_STATUS_RESOLVED) == 0)
                         return -EAGAIN;
                 if (status & MII_M1011_PHY_SPEC_STATUS_1000)
@@ -1174,7 +1174,7 @@ int sungem_phy_probe(struct mii_phy *phy, int mii_id)
                 goto fail;
 
         /* Read ID and find matching entry */
-        id = (phy_read(phy, MII_PHYSID1) << 16 | phy_read(phy, MII_PHYSID2));
+        id = (sungem_phy_read(phy, MII_PHYSID1) << 16 | sungem_phy_read(phy, MII_PHYSID2));
         printk(KERN_DEBUG KBUILD_MODNAME ": " "PHY ID: %x, addr: %x\n",
                id, mii_id);
         for (i=0; (def = mii_phy_table[i]) != NULL; i++)
diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c
index ef10302ec936..2277c3679a51 100644
--- a/drivers/net/team/team.c
+++ b/drivers/net/team/team.c
@@ -1003,7 +1003,6 @@ static int team_port_enter(struct team *team, struct team_port *port)
         int err = 0;
 
         dev_hold(team->dev);
-        port->dev->priv_flags |= IFF_TEAM_PORT;
         if (team->ops.port_enter) {
                 err = team->ops.port_enter(team, port);
                 if (err) {
@@ -1016,7 +1015,6 @@ static int team_port_enter(struct team *team, struct team_port *port)
         return 0;
 
 err_port_enter:
-        port->dev->priv_flags &= ~IFF_TEAM_PORT;
         dev_put(team->dev);
 
         return err;
@@ -1026,7 +1024,6 @@ static void team_port_leave(struct team *team, struct team_port *port)
 {
         if (team->ops.port_leave)
                 team->ops.port_leave(team, port);
-        port->dev->priv_flags &= ~IFF_TEAM_PORT;
         dev_put(team->dev);
 }
 
@@ -1075,6 +1072,25 @@ static void team_port_disable_netpoll(struct team_port *port)
 }
 #endif
 
+static int team_upper_dev_link(struct net_device *dev,
+                               struct net_device *port_dev)
+{
+        int err;
+
+        err = netdev_master_upper_dev_link(port_dev, dev);
+        if (err)
+                return err;
+        port_dev->priv_flags |= IFF_TEAM_PORT;
+        return 0;
+}
+
+static void team_upper_dev_unlink(struct net_device *dev,
+                                  struct net_device *port_dev)
+{
+        netdev_upper_dev_unlink(port_dev, dev);
+        port_dev->priv_flags &= ~IFF_TEAM_PORT;
+}
+
 static void __team_port_change_port_added(struct team_port *port, bool linkup);
 static int team_dev_type_check_change(struct net_device *dev,
                                       struct net_device *port_dev);
@@ -1161,13 +1177,6 @@ static int team_port_add(struct team *team, struct net_device *port_dev)
                 goto err_enable_netpoll;
         }
 
-        err = netdev_master_upper_dev_link(port_dev, dev);
-        if (err) {
-                netdev_err(dev, "Device %s failed to set upper link\n",
-                           portname);
-                goto err_set_upper_link;
-        }
-
         err = netdev_rx_handler_register(port_dev, team_handle_frame,
                                          port);
         if (err) {
@@ -1176,6 +1185,13 @@ static int team_port_add(struct team *team, struct net_device *port_dev)
                 goto err_handler_register;
         }
 
+        err = team_upper_dev_link(dev, port_dev);
+        if (err) {
+                netdev_err(dev, "Device %s failed to set upper link\n",
+                           portname);
+                goto err_set_upper_link;
+        }
+
         err = __team_option_inst_add_port(team, port);
         if (err) {
                 netdev_err(dev, "Device %s failed to add per-port options\n",
@@ -1195,12 +1211,12 @@ static int team_port_add(struct team *team, struct net_device *port_dev)
         return 0;
 
 err_option_port_add:
+        team_upper_dev_unlink(dev, port_dev);
+
+err_set_upper_link:
         netdev_rx_handler_unregister(port_dev);
 
 err_handler_register:
-        netdev_upper_dev_unlink(port_dev, dev);
-
-err_set_upper_link:
         team_port_disable_netpoll(port);
 
 err_enable_netpoll:
@@ -1239,8 +1255,8 @@ static int team_port_del(struct team *team, struct net_device *port_dev)
 
         team_port_disable(team, port);
         list_del_rcu(&port->list);
+        team_upper_dev_unlink(dev, port_dev);
         netdev_rx_handler_unregister(port_dev);
-        netdev_upper_dev_unlink(port_dev, dev);
         team_port_disable_netpoll(port);
         vlan_vids_del_by_dev(port_dev, dev);
         dev_uc_unsync(port_dev, dev);
diff --git a/drivers/net/usb/r8152.c b/drivers/net/usb/r8152.c
index 87f710476217..f95e678cb69d 100644
--- a/drivers/net/usb/r8152.c
+++ b/drivers/net/usb/r8152.c
@@ -424,7 +424,7 @@ enum rtl_register_content {
         FULL_DUP        = 0x01,
 };
 
-#define RTL8152_MAX_TX          10
+#define RTL8152_MAX_TX          4
 #define RTL8152_MAX_RX          10
 #define INTBUFSIZE              2
 #define CRC_SIZE                4
@@ -607,9 +607,9 @@ enum tx_csum_stat {
  * The RTL chips use a 64 element hash table based on the Ethernet CRC.
  */
 static const int multicast_filter_limit = 32;
-static unsigned int rx_buf_sz = 16384;
+static unsigned int agg_buf_sz = 16384;
 
-#define RTL_LIMITED_TSO_SIZE    (rx_buf_sz - sizeof(struct tx_desc) - \
+#define RTL_LIMITED_TSO_SIZE    (agg_buf_sz - sizeof(struct tx_desc) - \
                                  VLAN_ETH_HLEN - VLAN_HLEN)
 
 static
@@ -623,8 +623,8 @@ int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
                 return -ENOMEM;
 
         ret = usb_control_msg(tp->udev, usb_rcvctrlpipe(tp->udev, 0),
-                               RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
-                               value, index, tmp, size, 500);
+                              RTL8152_REQ_GET_REGS, RTL8152_REQT_READ,
+                              value, index, tmp, size, 500);
 
         memcpy(data, tmp, size);
         kfree(tmp);
@@ -643,8 +643,8 @@ int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
                 return -ENOMEM;
 
         ret = usb_control_msg(tp->udev, usb_sndctrlpipe(tp->udev, 0),
-                               RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
-                               value, index, tmp, size, 500);
+                              RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE,
+                              value, index, tmp, size, 500);
 
         kfree(tmp);
 
@@ -652,7 +652,7 @@ int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data)
 }
 
 static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
-                                void *data, u16 type)
+                            void *data, u16 type)
 {
         u16 limit = 64;
         int ret = 0;
@@ -692,7 +692,7 @@ static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size,
 }
 
 static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
-                                u16 size, void *data, u16 type)
+                             u16 size, void *data, u16 type)
 {
         int ret;
         u16 byteen_start, byteen_end, byen;
@@ -726,8 +726,8 @@ static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
                 while (size) {
                         if (size > limit) {
                                 ret = set_registers(tp, index,
-                                        type | BYTE_EN_DWORD,
-                                        limit, data);
+                                                    type | BYTE_EN_DWORD,
+                                                    limit, data);
                                 if (ret < 0)
                                         goto error1;
 
@@ -736,8 +736,8 @@ static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen,
                                 size -= limit;
                         } else {
                                 ret = set_registers(tp, index,
-                                        type | BYTE_EN_DWORD,
-                                        size, data);
+                                                    type | BYTE_EN_DWORD,
+                                                    size, data);
                                 if (ret < 0)
                                         goto error1;
 
@@ -972,36 +972,8 @@ void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val)
         usb_autopm_put_interface(tp->intf);
 }
 
-static
-int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
-
-static inline void set_ethernet_addr(struct r8152 *tp)
-{
-        struct net_device *dev = tp->netdev;
-        int ret;
-        u8 node_id[8] = {0};
-
-        if (tp->version == RTL_VER_01)
-                ret = pla_ocp_read(tp, PLA_IDR, sizeof(node_id), node_id);
-        else
-                ret = pla_ocp_read(tp, PLA_BACKUP, sizeof(node_id), node_id);
-
-        if (ret < 0) {
-                netif_notice(tp, probe, dev, "inet addr fail\n");
-        } else {
-                if (tp->version != RTL_VER_01) {
-                        ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
-                                       CRWECR_CONFIG);
-                        pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES,
-                                      sizeof(node_id), node_id);
-                        ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR,
-                                       CRWECR_NORAML);
-                }
-
-                memcpy(dev->dev_addr, node_id, dev->addr_len);
-                memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
-        }
-}
+static int
+r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags);
 
 static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
 {
@@ -1020,6 +992,37 @@ static int rtl8152_set_mac_address(struct net_device *netdev, void *p)
         return 0;
 }
 
+static int set_ethernet_addr(struct r8152 *tp)
+{
+        struct net_device *dev = tp->netdev;
+        struct sockaddr sa;
+        int ret;
+
+        if (tp->version == RTL_VER_01)
+                ret = pla_ocp_read(tp, PLA_IDR, 8, sa.sa_data);
+        else
+                ret = pla_ocp_read(tp, PLA_BACKUP, 8, sa.sa_data);
+
+        if (ret < 0) {
+                netif_err(tp, probe, dev, "Get ether addr fail\n");
+        } else if (!is_valid_ether_addr(sa.sa_data)) {
+                netif_err(tp, probe, dev, "Invalid ether addr %pM\n",
+                          sa.sa_data);
+                eth_hw_addr_random(dev);
+                ether_addr_copy(sa.sa_data, dev->dev_addr);
+                ret = rtl8152_set_mac_address(dev, &sa);
+                netif_info(tp, probe, dev, "Random ether addr %pM\n",
+                           sa.sa_data);
+        } else {
+                if (tp->version == RTL_VER_01)
+                        ether_addr_copy(dev->dev_addr, sa.sa_data);
+                else
+                        ret = rtl8152_set_mac_address(dev, &sa);
+        }
+
+        return ret;
+}
+
 static void read_bulk_callback(struct urb *urb)
 {
         struct net_device *netdev;
@@ -1248,13 +1251,13 @@ static int alloc_all_mem(struct r8152 *tp)
         skb_queue_head_init(&tp->tx_queue);
 
         for (i = 0; i < RTL8152_MAX_RX; i++) {
-                buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
+                buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
                 if (!buf)
                         goto err1;
 
                 if (buf != rx_agg_align(buf)) {
                         kfree(buf);
-                        buf = kmalloc_node(rx_buf_sz + RX_ALIGN, GFP_KERNEL,
+                        buf = kmalloc_node(agg_buf_sz + RX_ALIGN, GFP_KERNEL,
                                            node);
                         if (!buf)
                                 goto err1;
@@ -1274,13 +1277,13 @@ static int alloc_all_mem(struct r8152 *tp)
         }
 
         for (i = 0; i < RTL8152_MAX_TX; i++) {
-                buf = kmalloc_node(rx_buf_sz, GFP_KERNEL, node);
+                buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node);
                 if (!buf)
                         goto err1;
 
                 if (buf != tx_agg_align(buf)) {
                         kfree(buf);
-                        buf = kmalloc_node(rx_buf_sz + TX_ALIGN, GFP_KERNEL,
+                        buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL,
                                            node);
                         if (!buf)
                                 goto err1;
@@ -1311,8 +1314,8 @@ static int alloc_all_mem(struct r8152 *tp)
 
         tp->intr_interval = (int)ep_intr->desc.bInterval;
         usb_fill_int_urb(tp->intr_urb, tp->udev, usb_rcvintpipe(tp->udev, 3),
-                     tp->intr_buff, INTBUFSIZE, intr_callback,
-                     tp, tp->intr_interval);
+                         tp->intr_buff, INTBUFSIZE, intr_callback,
+                         tp, tp->intr_interval);
 
         return 0;
 
@@ -1354,8 +1357,7 @@ static inline __be16 get_protocol(struct sk_buff *skb)
         return protocol;
 }
 
-/*
- * r8152_csum_workaround()
+/* r8152_csum_workaround()
  * The hw limites the value the transport offset. When the offset is out of the
  * range, calculate the checksum by sw.
  */
@@ -1398,8 +1400,7 @@ drop:
         }
 }
 
-/*
- * msdn_giant_send_check()
+/* msdn_giant_send_check()
  * According to the document of microsoft, the TCP Pseudo Header excludes the
  * packet length for IPv6 TCP large packets.
  */
@@ -1518,8 +1519,9 @@ static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
         spin_unlock(&tx_queue->lock);
 
         tx_data = agg->head;
-        agg->skb_num = agg->skb_len = 0;
-        remain = rx_buf_sz;
+        agg->skb_num = 0;
+        agg->skb_len = 0;
+        remain = agg_buf_sz;
 
         while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) {
                 struct tx_desc *tx_desc;
@@ -1566,7 +1568,7 @@ static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg)
 
                 dev_kfree_skb_any(skb);
 
-                remain = rx_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
+                remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head);
         }
 
         if (!skb_queue_empty(&skb_head)) {
@@ -1772,8 +1774,8 @@ static
 int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags)
 {
         usb_fill_bulk_urb(agg->urb, tp->udev, usb_rcvbulkpipe(tp->udev, 1),
-                      agg->head, rx_buf_sz,
-                      (usb_complete_t)read_bulk_callback, agg);
+                          agg->head, agg_buf_sz,
+                          (usb_complete_t)read_bulk_callback, agg);
 
         return usb_submit_urb(agg->urb, mem_flags);
 }
@@ -1835,18 +1837,22 @@ static void _rtl8152_set_rx_mode(struct net_device *netdev)
                 /* Unconditionally log net taps. */
                 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n");
                 ocp_data |= RCR_AM | RCR_AAP;
-                mc_filter[1] = mc_filter[0] = 0xffffffff;
+                mc_filter[1] = 0xffffffff;
+                mc_filter[0] = 0xffffffff;
         } else if ((netdev_mc_count(netdev) > multicast_filter_limit) ||
                    (netdev->flags & IFF_ALLMULTI)) {
                 /* Too many to filter perfectly -- accept all multicasts. */
                 ocp_data |= RCR_AM;
-                mc_filter[1] = mc_filter[0] = 0xffffffff;
+                mc_filter[1] = 0xffffffff;
+                mc_filter[0] = 0xffffffff;
         } else {
                 struct netdev_hw_addr *ha;
 
-                mc_filter[1] = mc_filter[0] = 0;
+                mc_filter[1] = 0;
+                mc_filter[0] = 0;
                 netdev_for_each_mc_addr(ha, netdev) {
                         int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26;
+
                         mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31);
                         ocp_data |= RCR_AM;
                 }
@@ -1861,7 +1867,7 @@ static void _rtl8152_set_rx_mode(struct net_device *netdev)
 }
 
 static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
-                                        struct net_device *netdev)
+                                      struct net_device *netdev)
 {
         struct r8152 *tp = netdev_priv(netdev);
 
@@ -1877,8 +1883,9 @@ static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb,
                         usb_mark_last_busy(tp->udev);
                         tasklet_schedule(&tp->tl);
                 }
-        } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen)
+        } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) {
                 netif_stop_queue(netdev);
+        }
 
         return NETDEV_TX_OK;
 }
@@ -1903,7 +1910,7 @@ static void rtl8152_nic_reset(struct r8152 *tp)
         for (i = 0; i < 1000; i++) {
                 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
                         break;
-                udelay(100);
+                usleep_range(100, 400);
         }
 }
 
@@ -1911,8 +1918,8 @@ static void set_tx_qlen(struct r8152 *tp)
 {
         struct net_device *netdev = tp->netdev;
 
-        tp->tx_qlen = rx_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
-                                   sizeof(struct tx_desc));
+        tp->tx_qlen = agg_buf_sz / (netdev->mtu + VLAN_ETH_HLEN + VLAN_HLEN +
+                                    sizeof(struct tx_desc));
 }
 
 static inline u8 rtl8152_get_speed(struct r8152 *tp)
@@ -2861,8 +2868,7 @@ static int rtl8152_close(struct net_device *netdev)
         if (res < 0) {
                 rtl_drop_queued_tx(tp);
         } else {
-                /*
-                 * The autosuspend may have been enabled and wouldn't
+                /* The autosuspend may have been enabled and wouldn't
                  * be disable when autoresume occurs, because the
                  * netif_running() would be false.
                  */
@@ -3085,8 +3091,9 @@ static int rtl8152_resume(struct usb_interface *intf)
                 } else {
                         tp->rtl_ops.up(tp);
                         rtl8152_set_speed(tp, AUTONEG_ENABLE,
-                                tp->mii.supports_gmii ? SPEED_1000 : SPEED_100,
-                                DUPLEX_FULL);
+                                          tp->mii.supports_gmii ?
+                                          SPEED_1000 : SPEED_100,
+                                          DUPLEX_FULL);
                 }
                 tp->speed = 0;
                 netif_carrier_off(tp->netdev);
@@ -3147,8 +3154,8 @@ static void rtl8152_get_drvinfo(struct net_device *netdev,
 {
         struct r8152 *tp = netdev_priv(netdev);
 
-        strncpy(info->driver, MODULENAME, ETHTOOL_BUSINFO_LEN);
-        strncpy(info->version, DRIVER_VERSION, ETHTOOL_BUSINFO_LEN);
+        strlcpy(info->driver, MODULENAME, sizeof(info->driver));
+        strlcpy(info->version, DRIVER_VERSION, sizeof(info->version));
         usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info));
 }
 
diff --git a/drivers/net/virtio_net.c b/drivers/net/virtio_net.c
index 59caa06f34a6..9359a13d285a 100644
--- a/drivers/net/virtio_net.c
+++ b/drivers/net/virtio_net.c
@@ -934,7 +934,6 @@ static netdev_tx_t start_xmit(struct sk_buff *skb, struct net_device *dev)
                 dev_kfree_skb_any(skb);
                 return NETDEV_TX_OK;
         }
-        virtqueue_kick(sq->vq);
 
         /* Don't wait up for transmitted skbs to be freed. */
         skb_orphan(skb);
@@ -954,6 +953,9 @@ static netdev_tx_t start_xmit(struct sk_buff *skb, struct net_device *dev)
                 }
         }
 
+        if (__netif_subqueue_stopped(dev, qnum) || !skb->xmit_more)
+                virtqueue_kick(sq->vq);
+
         return NETDEV_TX_OK;
 }
 
diff --git a/drivers/net/vxlan.c b/drivers/net/vxlan.c
index beb377b2d4b7..53c3ec19807c 100644
--- a/drivers/net/vxlan.c
+++ b/drivers/net/vxlan.c
@@ -1158,8 +1158,6 @@ static int vxlan_udp_encap_recv(struct sock *sk, struct sk_buff *skb)
         if (!vs)
                 goto drop;
 
-        skb_pop_rcv_encapsulation(skb);
-
         vs->rcv(vs, skb, vxh->vx_vni);
         return 0;
 
@@ -2372,6 +2370,8 @@ static struct socket *vxlan_create_sock(struct net *net, bool ipv6,
         /* Disable multicast loopback */
         inet_sk(sock->sk)->mc_loop = 0;
 
+        udp_set_convert_csum(sock->sk, true);
+
         return sock;
 }
 
diff --git a/drivers/net/wan/dlci.c b/drivers/net/wan/dlci.c
index 43c9960dce1c..ae6ecf401189 100644
--- a/drivers/net/wan/dlci.c
+++ b/drivers/net/wan/dlci.c
@@ -192,8 +192,10 @@ static netdev_tx_t dlci_transmit(struct sk_buff *skb, struct net_device *dev)
 {
         struct dlci_local *dlp = netdev_priv(dev);
 
-        if (skb)
-                dlp->slave->netdev_ops->ndo_start_xmit(skb, dlp->slave);
+        if (skb) {
+                struct netdev_queue *txq = skb_get_tx_queue(dev, skb);
+                netdev_start_xmit(skb, dlp->slave, txq, false);
+        }
         return NETDEV_TX_OK;
 }
 
diff --git a/drivers/usb/gadget/function/f_ncm.c b/drivers/usb/gadget/function/f_ncm.c
index bcdc882cd415..146f48cc65d7 100644
--- a/drivers/usb/gadget/function/f_ncm.c
+++ b/drivers/usb/gadget/function/f_ncm.c
@@ -1101,7 +1101,15 @@ static void ncm_tx_tasklet(unsigned long data)
         /* Only send if data is available. */
         if (ncm->skb_tx_data) {
                 ncm->timer_force_tx = true;
+
+                /* XXX This allowance of a NULL skb argument to ndo_start_xmit
+                 * XXX is not sane.  The gadget layer should be redesigned so
+                 * XXX that the dev->wrap() invocations to build SKBs is transparent
+                 * XXX and performed in some way outside of the ndo_start_xmit
+                 * XXX interface.
+                 */
                 ncm->netdev->netdev_ops->ndo_start_xmit(NULL, ncm->netdev);
+
                 ncm->timer_force_tx = false;
         }
 }