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-rw-r--r--drivers/gpu/drm/nouveau/nouveau_bo.c33
1 files changed, 8 insertions, 25 deletions
diff --git a/drivers/gpu/drm/nouveau/nouveau_bo.c b/drivers/gpu/drm/nouveau/nouveau_bo.c
index 198d36909590..e4623e9a7be3 100644
--- a/drivers/gpu/drm/nouveau/nouveau_bo.c
+++ b/drivers/gpu/drm/nouveau/nouveau_bo.c
@@ -798,25 +798,25 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
798 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem) 798 struct ttm_mem_reg *old_mem, struct ttm_mem_reg *new_mem)
799{ 799{
800 struct nouveau_mem *node = old_mem->mm_node; 800 struct nouveau_mem *node = old_mem->mm_node;
801 struct nouveau_bo *nvbo = nouveau_bo(bo);
802 u64 length = (new_mem->num_pages << PAGE_SHIFT); 801 u64 length = (new_mem->num_pages << PAGE_SHIFT);
803 u64 src_offset = node->vma[0].offset; 802 u64 src_offset = node->vma[0].offset;
804 u64 dst_offset = node->vma[1].offset; 803 u64 dst_offset = node->vma[1].offset;
804 int src_tiled = !!node->memtype;
805 int dst_tiled = !!((struct nouveau_mem *)new_mem->mm_node)->memtype;
805 int ret; 806 int ret;
806 807
807 while (length) { 808 while (length) {
808 u32 amount, stride, height; 809 u32 amount, stride, height;
809 810
811 ret = RING_SPACE(chan, 18 + 6 * (src_tiled + dst_tiled));
812 if (ret)
813 return ret;
814
810 amount = min(length, (u64)(4 * 1024 * 1024)); 815 amount = min(length, (u64)(4 * 1024 * 1024));
811 stride = 16 * 4; 816 stride = 16 * 4;
812 height = amount / stride; 817 height = amount / stride;
813 818
814 if (old_mem->mem_type == TTM_PL_VRAM && 819 if (src_tiled) {
815 nouveau_bo_tile_layout(nvbo)) {
816 ret = RING_SPACE(chan, 8);
817 if (ret)
818 return ret;
819
820 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7); 820 BEGIN_NV04(chan, NvSubCopy, 0x0200, 7);
821 OUT_RING (chan, 0); 821 OUT_RING (chan, 0);
822 OUT_RING (chan, 0); 822 OUT_RING (chan, 0);
@@ -826,19 +826,10 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
826 OUT_RING (chan, 0); 826 OUT_RING (chan, 0);
827 OUT_RING (chan, 0); 827 OUT_RING (chan, 0);
828 } else { 828 } else {
829 ret = RING_SPACE(chan, 2);
830 if (ret)
831 return ret;
832
833 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1); 829 BEGIN_NV04(chan, NvSubCopy, 0x0200, 1);
834 OUT_RING (chan, 1); 830 OUT_RING (chan, 1);
835 } 831 }
836 if (new_mem->mem_type == TTM_PL_VRAM && 832 if (dst_tiled) {
837 nouveau_bo_tile_layout(nvbo)) {
838 ret = RING_SPACE(chan, 8);
839 if (ret)
840 return ret;
841
842 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7); 833 BEGIN_NV04(chan, NvSubCopy, 0x021c, 7);
843 OUT_RING (chan, 0); 834 OUT_RING (chan, 0);
844 OUT_RING (chan, 0); 835 OUT_RING (chan, 0);
@@ -848,18 +839,10 @@ nv50_bo_move_m2mf(struct nouveau_channel *chan, struct ttm_buffer_object *bo,
848 OUT_RING (chan, 0); 839 OUT_RING (chan, 0);
849 OUT_RING (chan, 0); 840 OUT_RING (chan, 0);
850 } else { 841 } else {
851 ret = RING_SPACE(chan, 2);
852 if (ret)
853 return ret;
854
855 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1); 842 BEGIN_NV04(chan, NvSubCopy, 0x021c, 1);
856 OUT_RING (chan, 1); 843 OUT_RING (chan, 1);
857 } 844 }
858 845
859 ret = RING_SPACE(chan, 14);
860 if (ret)
861 return ret;
862
863 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2); 846 BEGIN_NV04(chan, NvSubCopy, 0x0238, 2);
864 OUT_RING (chan, upper_32_bits(src_offset)); 847 OUT_RING (chan, upper_32_bits(src_offset));
865 OUT_RING (chan, upper_32_bits(dst_offset)); 848 OUT_RING (chan, upper_32_bits(dst_offset));