378 files changed, 17595 insertions, 5083 deletions

diff --git a/drivers/acpi/apei/cper.c b/drivers/acpi/apei/cper.c
index fefc2ca7cc3e..33dc6a004802 100644
--- a/drivers/acpi/apei/cper.c
+++ b/drivers/acpi/apei/cper.c
@@ -250,10 +250,6 @@ static const char *cper_pcie_port_type_strs[] = {
 static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie,
                             const struct acpi_hest_generic_data *gdata)
 {
-#ifdef CONFIG_ACPI_APEI_PCIEAER
-        struct pci_dev *dev;
-#endif
-
         if (pcie->validation_bits & CPER_PCIE_VALID_PORT_TYPE)
                 printk("%s""port_type: %d, %s\n", pfx, pcie->port_type,
                        pcie->port_type < ARRAY_SIZE(cper_pcie_port_type_strs) ?
@@ -285,20 +281,6 @@ static void cper_print_pcie(const char *pfx, const struct cper_sec_pcie *pcie,
                 printk(
         "%s""bridge: secondary_status: 0x%04x, control: 0x%04x\n",
         pfx, pcie->bridge.secondary_status, pcie->bridge.control);
-#ifdef CONFIG_ACPI_APEI_PCIEAER
-        dev = pci_get_domain_bus_and_slot(pcie->device_id.segment,
-                        pcie->device_id.bus, pcie->device_id.function);
-        if (!dev) {
-                pr_err("PCI AER Cannot get PCI device %04x:%02x:%02x.%d\n",
-                        pcie->device_id.segment, pcie->device_id.bus,
-                        pcie->device_id.slot, pcie->device_id.function);
-                return;
-        }
-        if (pcie->validation_bits & CPER_PCIE_VALID_AER_INFO)
-                cper_print_aer(pfx, dev, gdata->error_severity,
-                                (struct aer_capability_regs *) pcie->aer_info);
-        pci_dev_put(dev);
-#endif
 }
 
 static const char *apei_estatus_section_flag_strs[] = {
diff --git a/drivers/acpi/apei/ghes.c b/drivers/acpi/apei/ghes.c
index d668a8ae602b..fcd7d91cec34 100644
--- a/drivers/acpi/apei/ghes.c
+++ b/drivers/acpi/apei/ghes.c
@@ -454,7 +454,9 @@ static void ghes_do_proc(struct ghes *ghes,
                                 aer_severity = cper_severity_to_aer(sev);
                                 aer_recover_queue(pcie_err->device_id.segment,
                                                   pcie_err->device_id.bus,
-                                                  devfn, aer_severity);
+                                                  devfn, aer_severity,
+                                                  (struct aer_capability_regs *)
+                                                  pcie_err->aer_info);
                         }
 
                 }
@@ -917,13 +919,14 @@ static int ghes_probe(struct platform_device *ghes_dev)
                 break;
         case ACPI_HEST_NOTIFY_EXTERNAL:
                 /* External interrupt vector is GSI */
-                if (acpi_gsi_to_irq(generic->notify.vector, &ghes->irq)) {
+                rc = acpi_gsi_to_irq(generic->notify.vector, &ghes->irq);
+                if (rc) {
                         pr_err(GHES_PFX "Failed to map GSI to IRQ for generic hardware error source: %d\n",
                                generic->header.source_id);
                         goto err_edac_unreg;
                 }
-                if (request_irq(ghes->irq, ghes_irq_func,
-                                0, "GHES IRQ", ghes)) {
+                rc = request_irq(ghes->irq, ghes_irq_func, 0, "GHES IRQ", ghes);
+                if (rc) {
                         pr_err(GHES_PFX "Failed to register IRQ for generic hardware error source: %d\n",
                                generic->header.source_id);
                         goto err_edac_unreg;
diff --git a/drivers/acpi/device_pm.c b/drivers/acpi/device_pm.c
index bc493aa3af19..318fa32a141e 100644
--- a/drivers/acpi/device_pm.c
+++ b/drivers/acpi/device_pm.c
@@ -278,11 +278,13 @@ int acpi_bus_init_power(struct acpi_device *device)
                 if (result)
                         return result;
         } else if (state == ACPI_STATE_UNKNOWN) {
-                /* No power resources and missing _PSC? Try to force D0. */
+                /*
+                 * No power resources and missing _PSC?  Cross fingers and make
+                 * it D0 in hope that this is what the BIOS put the device into.
+                 * [We tried to force D0 here by executing _PS0, but that broke
+                 * Toshiba P870-303 in a nasty way.]
+                 */
                 state = ACPI_STATE_D0;
-                result = acpi_dev_pm_explicit_set(device, state);
-                if (result)
-                        return result;
         }
         device->power.state = state;
         return 0;
diff --git a/drivers/acpi/scan.c b/drivers/acpi/scan.c
index 44225cb15f3a..b14ac46948c9 100644
--- a/drivers/acpi/scan.c
+++ b/drivers/acpi/scan.c
@@ -1017,11 +1017,8 @@ acpi_bus_driver_init(struct acpi_device *device, struct acpi_driver *driver)
                 return -ENOSYS;
 
         result = driver->ops.add(device);
-        if (result) {
-                device->driver = NULL;
-                device->driver_data = NULL;
+        if (result)
                 return result;
-        }
 
         device->driver = driver;
 
diff --git a/drivers/acpi/video.c b/drivers/acpi/video.c
index 5b32e15a65ce..440eadf2d32c 100644
--- a/drivers/acpi/video.c
+++ b/drivers/acpi/video.c
@@ -458,12 +458,28 @@ static struct dmi_system_id video_dmi_table[] __initdata = {
         },
         {
          .callback = video_ignore_initial_backlight,
+         .ident = "HP Pavilion g6 Notebook PC",
+         .matches = {
+                 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
+                 DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion g6 Notebook PC"),
+                },
+        },
+        {
+         .callback = video_ignore_initial_backlight,
          .ident = "HP 1000 Notebook PC",
          .matches = {
                 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
                 DMI_MATCH(DMI_PRODUCT_NAME, "HP 1000 Notebook PC"),
                 },
         },
+        {
+         .callback = video_ignore_initial_backlight,
+         .ident = "HP Pavilion m4",
+         .matches = {
+                DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
+                DMI_MATCH(DMI_PRODUCT_NAME, "HP Pavilion m4 Notebook PC"),
+                },
+        },
         {}
 };
 
@@ -1706,6 +1722,9 @@ static int acpi_video_bus_add(struct acpi_device *device)
         int error;
         acpi_status status;
 
+        if (device->handler)
+                return -EINVAL;
+
         status = acpi_walk_namespace(ACPI_TYPE_DEVICE,
                                 device->parent->handle, 1,
                                 acpi_video_bus_match, NULL,
diff --git a/drivers/ata/acard-ahci.c b/drivers/ata/acard-ahci.c
index 4e94ba29cb8d..9d0cf019ce59 100644
--- a/drivers/ata/acard-ahci.c
+++ b/drivers/ata/acard-ahci.c
@@ -2,7 +2,7 @@
 /*
  *  acard-ahci.c - ACard AHCI SATA support
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/ahci.c b/drivers/ata/ahci.c
index 251e57d38942..2b50dfdf1cfc 100644
--- a/drivers/ata/ahci.c
+++ b/drivers/ata/ahci.c
@@ -1,7 +1,7 @@
 /*
  *  ahci.c - AHCI SATA support
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
@@ -423,6 +423,8 @@ static const struct pci_device_id ahci_pci_tbl[] = {
           .driver_data = board_ahci_yes_fbs },                  /* 88se9125 */
         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x917a),
           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
+        { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9172),
+          .driver_data = board_ahci_yes_fbs },                  /* 88se9172 */
         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x9192),
           .driver_data = board_ahci_yes_fbs },                  /* 88se9172 on some Gigabyte */
         { PCI_DEVICE(PCI_VENDOR_ID_MARVELL_EXT, 0x91a3),
diff --git a/drivers/ata/ahci.h b/drivers/ata/ahci.h
index b830e6c9fe49..10b14d45cfd2 100644
--- a/drivers/ata/ahci.h
+++ b/drivers/ata/ahci.h
@@ -1,7 +1,7 @@
 /*
  *  ahci.h - Common AHCI SATA definitions and declarations
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/ata_piix.c b/drivers/ata/ata_piix.c
index 2f48123d74c4..9a8a674e8fac 100644
--- a/drivers/ata/ata_piix.c
+++ b/drivers/ata/ata_piix.c
@@ -1,7 +1,7 @@
 /*
  *    ata_piix.c - Intel PATA/SATA controllers
  *
- *    Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *    Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
@@ -151,6 +151,7 @@ enum piix_controller_ids {
         piix_pata_vmw,                  /* PIIX4 for VMware, spurious DMA_ERR */
         ich8_sata_snb,
         ich8_2port_sata_snb,
+        ich8_2port_sata_byt,
 };
 
 struct piix_map_db {
@@ -334,6 +335,9 @@ static const struct pci_device_id piix_pci_tbl[] = {
         { 0x8086, 0x8d60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_sata_snb },
         /* SATA Controller IDE (Wellsburg) */
         { 0x8086, 0x8d68, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata },
+        /* SATA Controller IDE (BayTrail) */
+        { 0x8086, 0x0F20, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
+        { 0x8086, 0x0F21, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich8_2port_sata_byt },
 
         { }     /* terminate list */
 };
@@ -441,6 +445,7 @@ static const struct piix_map_db *piix_map_db_table[] = {
         [tolapai_sata]          = &tolapai_map_db,
         [ich8_sata_snb]         = &ich8_map_db,
         [ich8_2port_sata_snb]   = &ich8_2port_map_db,
+        [ich8_2port_sata_byt]   = &ich8_2port_map_db,
 };
 
 static struct pci_bits piix_enable_bits[] = {
@@ -1254,6 +1259,16 @@ static struct ata_port_info piix_port_info[] = {
                 .udma_mask      = ATA_UDMA6,
                 .port_ops       = &piix_sata_ops,
         },
+
+        [ich8_2port_sata_byt] =
+        {
+                .flags          = PIIX_SATA_FLAGS | PIIX_FLAG_SIDPR | PIIX_FLAG_PIO16,
+                .pio_mask       = ATA_PIO4,
+                .mwdma_mask     = ATA_MWDMA2,
+                .udma_mask      = ATA_UDMA6,
+                .port_ops       = &piix_sata_ops,
+        },
+
 };
 
 #define AHCI_PCI_BAR 5
diff --git a/drivers/ata/libahci.c b/drivers/ata/libahci.c
index 34c82167b962..a70ff154f586 100644
--- a/drivers/ata/libahci.c
+++ b/drivers/ata/libahci.c
@@ -1,7 +1,7 @@
 /*
  *  libahci.c - Common AHCI SATA low-level routines
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/libata-core.c b/drivers/ata/libata-core.c
index 63c743baf920..f2184276539d 100644
--- a/drivers/ata/libata-core.c
+++ b/drivers/ata/libata-core.c
@@ -1,7 +1,7 @@
 /*
  *  libata-core.c - helper library for ATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
@@ -1602,6 +1602,12 @@ unsigned ata_exec_internal_sg(struct ata_device *dev,
         qc->tf = *tf;
         if (cdb)
                 memcpy(qc->cdb, cdb, ATAPI_CDB_LEN);
+
+        /* some SATA bridges need us to indicate data xfer direction */
+        if (tf->protocol == ATAPI_PROT_DMA && (dev->flags & ATA_DFLAG_DMADIR) &&
+            dma_dir == DMA_FROM_DEVICE)
+                qc->tf.feature |= ATAPI_DMADIR;
+
         qc->flags |= ATA_QCFLAG_RESULT_TF;
         qc->dma_dir = dma_dir;
         if (dma_dir != DMA_NONE) {
diff --git a/drivers/ata/libata-eh.c b/drivers/ata/libata-eh.c
index f9476fb3ac43..c69fcce505c0 100644
--- a/drivers/ata/libata-eh.c
+++ b/drivers/ata/libata-eh.c
@@ -1,7 +1,7 @@
 /*
  *  libata-eh.c - libata error handling
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/libata-scsi.c b/drivers/ata/libata-scsi.c
index dd310b27b24c..0101af541436 100644
--- a/drivers/ata/libata-scsi.c
+++ b/drivers/ata/libata-scsi.c
@@ -1,7 +1,7 @@
 /*
  *  libata-scsi.c - helper library for ATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/libata-sff.c b/drivers/ata/libata-sff.c
index d8af325a6bda..b603720b877d 100644
--- a/drivers/ata/libata-sff.c
+++ b/drivers/ata/libata-sff.c
@@ -1,7 +1,7 @@
 /*
  *  libata-sff.c - helper library for PCI IDE BMDMA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/pdc_adma.c b/drivers/ata/pdc_adma.c
index 505333340ad5..8ea6e6afd041 100644
--- a/drivers/ata/pdc_adma.c
+++ b/drivers/ata/pdc_adma.c
@@ -1,7 +1,7 @@
 /*
  *  pdc_adma.c - Pacific Digital Corporation ADMA
  *
- *  Maintained by:  Mark Lord <mlord@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *
  *  Copyright 2005 Mark Lord
  *
diff --git a/drivers/ata/sata_promise.c b/drivers/ata/sata_promise.c
index fb0dd87f8893..958ba2a420c3 100644
--- a/drivers/ata/sata_promise.c
+++ b/drivers/ata/sata_promise.c
@@ -1,7 +1,7 @@
 /*
  *  sata_promise.c - Promise SATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Mikael Pettersson <mikpe@it.uu.se>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
diff --git a/drivers/ata/sata_rcar.c b/drivers/ata/sata_rcar.c
index 4799868bd733..249c8a289bfd 100644
--- a/drivers/ata/sata_rcar.c
+++ b/drivers/ata/sata_rcar.c
@@ -549,6 +549,7 @@ static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
 
         /* start host DMA transaction */
         dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
+        dmactl &= ~ATAPI_CONTROL1_STOP;
         dmactl |= ATAPI_CONTROL1_START;
         iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
 }
@@ -618,17 +619,16 @@ static struct ata_port_operations sata_rcar_port_ops = {
         .bmdma_status           = sata_rcar_bmdma_status,
 };
 
-static int sata_rcar_serr_interrupt(struct ata_port *ap)
+static void sata_rcar_serr_interrupt(struct ata_port *ap)
 {
         struct sata_rcar_priv *priv = ap->host->private_data;
         struct ata_eh_info *ehi = &ap->link.eh_info;
         int freeze = 0;
-        int handled = 0;
         u32 serror;
 
         serror = ioread32(priv->base + SCRSERR_REG);
         if (!serror)
-                return 0;
+                return;
 
         DPRINTK("SError @host_intr: 0x%x\n", serror);
 
@@ -641,7 +641,6 @@ static int sata_rcar_serr_interrupt(struct ata_port *ap)
                 ata_ehi_push_desc(ehi, "%s", "hotplug");
 
                 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
-                handled = 1;
         }
 
         /* freeze or abort */
@@ -649,11 +648,9 @@ static int sata_rcar_serr_interrupt(struct ata_port *ap)
                 ata_port_freeze(ap);
         else
                 ata_port_abort(ap);
-
-        return handled;
 }
 
-static int sata_rcar_ata_interrupt(struct ata_port *ap)
+static void sata_rcar_ata_interrupt(struct ata_port *ap)
 {
         struct ata_queued_cmd *qc;
         int handled = 0;
@@ -662,7 +659,9 @@ static int sata_rcar_ata_interrupt(struct ata_port *ap)
         if (qc)
                 handled |= ata_bmdma_port_intr(ap, qc);
 
-        return handled;
+        /* be sure to clear ATA interrupt */
+        if (!handled)
+                sata_rcar_check_status(ap);
 }
 
 static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
@@ -677,20 +676,21 @@ static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
         spin_lock_irqsave(&host->lock, flags);
 
         sataintstat = ioread32(priv->base + SATAINTSTAT_REG);
+        sataintstat &= SATA_RCAR_INT_MASK;
         if (!sataintstat)
                 goto done;
         /* ack */
-        iowrite32(sataintstat & ~SATA_RCAR_INT_MASK,
-                 priv->base + SATAINTSTAT_REG);
+        iowrite32(~sataintstat & 0x7ff, priv->base + SATAINTSTAT_REG);
 
         ap = host->ports[0];
 
         if (sataintstat & SATAINTSTAT_ATA)
-                handled |= sata_rcar_ata_interrupt(ap);
+                sata_rcar_ata_interrupt(ap);
 
         if (sataintstat & SATAINTSTAT_SERR)
-                handled |= sata_rcar_serr_interrupt(ap);
+                sata_rcar_serr_interrupt(ap);
 
+        handled = 1;
 done:
         spin_unlock_irqrestore(&host->lock, flags);
 
diff --git a/drivers/ata/sata_sil.c b/drivers/ata/sata_sil.c
index a7b31672c4b7..0ae3ca4bf5c0 100644
--- a/drivers/ata/sata_sil.c
+++ b/drivers/ata/sata_sil.c
@@ -1,7 +1,7 @@
 /*
  *  sata_sil.c - Silicon Image SATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/sata_sx4.c b/drivers/ata/sata_sx4.c
index 7b7127a58f51..9947010afc0f 100644
--- a/drivers/ata/sata_sx4.c
+++ b/drivers/ata/sata_sx4.c
@@ -1,7 +1,7 @@
 /*
  *  sata_sx4.c - Promise SATA
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                  Please ALWAYS copy linux-ide@vger.kernel.org
  *                  on emails.
  *
diff --git a/drivers/ata/sata_via.c b/drivers/ata/sata_via.c
index 5913ea9d57b2..87f056e54a9d 100644
--- a/drivers/ata/sata_via.c
+++ b/drivers/ata/sata_via.c
@@ -1,7 +1,7 @@
 /*
  *  sata_via.c - VIA Serial ATA controllers
  *
- *  Maintained by:  Jeff Garzik <jgarzik@pobox.com>
+ *  Maintained by:  Tejun Heo <tj@kernel.org>
  *                 Please ALWAYS copy linux-ide@vger.kernel.org
  *                 on emails.
  *
diff --git a/drivers/base/regmap/regcache-rbtree.c b/drivers/base/regmap/regcache-rbtree.c
index aa0875f6f1b7..02f490bad30f 100644
--- a/drivers/base/regmap/regcache-rbtree.c
+++ b/drivers/base/regmap/regcache-rbtree.c
@@ -143,7 +143,7 @@ static int rbtree_show(struct seq_file *s, void *ignored)
         int registers = 0;
         int this_registers, average;
 
-        map->lock(map);
+        map->lock(map->lock_arg);
 
         mem_size = sizeof(*rbtree_ctx);
         mem_size += BITS_TO_LONGS(map->cache_present_nbits) * sizeof(long);
@@ -170,7 +170,7 @@ static int rbtree_show(struct seq_file *s, void *ignored)
         seq_printf(s, "%d nodes, %d registers, average %d registers, used %zu bytes\n",
                    nodes, registers, average, mem_size);
 
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return 0;
 }
@@ -391,8 +391,6 @@ static int regcache_rbtree_sync(struct regmap *map, unsigned int min,
         for (node = rb_first(&rbtree_ctx->root); node; node = rb_next(node)) {
                 rbnode = rb_entry(node, struct regcache_rbtree_node, node);
 
-                if (rbnode->base_reg < min)
-                        continue;
                 if (rbnode->base_reg > max)
                         break;
                 if (rbnode->base_reg + rbnode->blklen < min)
diff --git a/drivers/base/regmap/regcache.c b/drivers/base/regmap/regcache.c
index 75923f2396bd..507ee2da0f6e 100644
--- a/drivers/base/regmap/regcache.c
+++ b/drivers/base/regmap/regcache.c
@@ -270,7 +270,7 @@ int regcache_sync(struct regmap *map)
 
         BUG_ON(!map->cache_ops || !map->cache_ops->sync);
 
-        map->lock(map);
+        map->lock(map->lock_arg);
         /* Remember the initial bypass state */
         bypass = map->cache_bypass;
         dev_dbg(map->dev, "Syncing %s cache\n",
@@ -306,7 +306,7 @@ out:
         trace_regcache_sync(map->dev, name, "stop");
         /* Restore the bypass state */
         map->cache_bypass = bypass;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return ret;
 }
@@ -333,7 +333,7 @@ int regcache_sync_region(struct regmap *map, unsigned int min,
 
         BUG_ON(!map->cache_ops || !map->cache_ops->sync);
 
-        map->lock(map);
+        map->lock(map->lock_arg);
 
         /* Remember the initial bypass state */
         bypass = map->cache_bypass;
@@ -352,7 +352,7 @@ out:
         trace_regcache_sync(map->dev, name, "stop region");
         /* Restore the bypass state */
         map->cache_bypass = bypass;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 
         return ret;
 }
@@ -372,11 +372,11 @@ EXPORT_SYMBOL_GPL(regcache_sync_region);
  */
 void regcache_cache_only(struct regmap *map, bool enable)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         WARN_ON(map->cache_bypass && enable);
         map->cache_only = enable;
         trace_regmap_cache_only(map->dev, enable);
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_cache_only);
 
@@ -391,9 +391,9 @@ EXPORT_SYMBOL_GPL(regcache_cache_only);
  */
 void regcache_mark_dirty(struct regmap *map)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         map->cache_dirty = true;
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_mark_dirty);
 
@@ -410,11 +410,11 @@ EXPORT_SYMBOL_GPL(regcache_mark_dirty);
  */
 void regcache_cache_bypass(struct regmap *map, bool enable)
 {
-        map->lock(map);
+        map->lock(map->lock_arg);
         WARN_ON(map->cache_only && enable);
         map->cache_bypass = enable;
         trace_regmap_cache_bypass(map->dev, enable);
-        map->unlock(map);
+        map->unlock(map->lock_arg);
 }
 EXPORT_SYMBOL_GPL(regcache_cache_bypass);
 
diff --git a/drivers/base/regmap/regmap-debugfs.c b/drivers/base/regmap/regmap-debugfs.c
index 23b701f5fd2f..975719bc3450 100644
--- a/drivers/base/regmap/regmap-debugfs.c
+++ b/drivers/base/regmap/regmap-debugfs.c
@@ -265,6 +265,7 @@ static ssize_t regmap_map_write_file(struct file *file,
         char *start = buf;
         unsigned long reg, value;
         struct regmap *map = file->private_data;
+        int ret;
 
         buf_size = min(count, (sizeof(buf)-1));
         if (copy_from_user(buf, user_buf, buf_size))
@@ -282,7 +283,9 @@ static ssize_t regmap_map_write_file(struct file *file,
         /* Userspace has been fiddling around behind the kernel's back */
         add_taint(TAINT_USER, LOCKDEP_NOW_UNRELIABLE);
 
-        regmap_write(map, reg, value);
+        ret = regmap_write(map, reg, value);
+        if (ret < 0)
+                return ret;
         return buf_size;
 }
 #else
diff --git a/drivers/block/cciss.c b/drivers/block/cciss.c
index 6374dc103521..62b6c2cc80b5 100644
--- a/drivers/block/cciss.c
+++ b/drivers/block/cciss.c
@@ -168,8 +168,6 @@ static irqreturn_t do_cciss_msix_intr(int irq, void *dev_id);
 static int cciss_open(struct block_device *bdev, fmode_t mode);
 static int cciss_unlocked_open(struct block_device *bdev, fmode_t mode);
 static void cciss_release(struct gendisk *disk, fmode_t mode);
-static int do_ioctl(struct block_device *bdev, fmode_t mode,
-                    unsigned int cmd, unsigned long arg);
 static int cciss_ioctl(struct block_device *bdev, fmode_t mode,
                        unsigned int cmd, unsigned long arg);
 static int cciss_getgeo(struct block_device *bdev, struct hd_geometry *geo);
@@ -235,7 +233,7 @@ static const struct block_device_operations cciss_fops = {
         .owner = THIS_MODULE,
         .open = cciss_unlocked_open,
         .release = cciss_release,
-        .ioctl = do_ioctl,
+        .ioctl = cciss_ioctl,
         .getgeo = cciss_getgeo,
 #ifdef CONFIG_COMPAT
         .compat_ioctl = cciss_compat_ioctl,
@@ -1143,16 +1141,6 @@ static void cciss_release(struct gendisk *disk, fmode_t mode)
         mutex_unlock(&cciss_mutex);
 }
 
-static int do_ioctl(struct block_device *bdev, fmode_t mode,
-                    unsigned cmd, unsigned long arg)
-{
-        int ret;
-        mutex_lock(&cciss_mutex);
-        ret = cciss_ioctl(bdev, mode, cmd, arg);
-        mutex_unlock(&cciss_mutex);
-        return ret;
-}
-
 #ifdef CONFIG_COMPAT
 
 static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
@@ -1179,7 +1167,7 @@ static int cciss_compat_ioctl(struct block_device *bdev, fmode_t mode,
         case CCISS_REGNEWD:
         case CCISS_RESCANDISK:
         case CCISS_GETLUNINFO:
-                return do_ioctl(bdev, mode, cmd, arg);
+                return cciss_ioctl(bdev, mode, cmd, arg);
 
         case CCISS_PASSTHRU32:
                 return cciss_ioctl32_passthru(bdev, mode, cmd, arg);
@@ -1219,7 +1207,7 @@ static int cciss_ioctl32_passthru(struct block_device *bdev, fmode_t mode,
         if (err)
                 return -EFAULT;
 
-        err = do_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
+        err = cciss_ioctl(bdev, mode, CCISS_PASSTHRU, (unsigned long)p);
         if (err)
                 return err;
         err |=
@@ -1261,7 +1249,7 @@ static int cciss_ioctl32_big_passthru(struct block_device *bdev, fmode_t mode,
         if (err)
                 return -EFAULT;
 
-        err = do_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
+        err = cciss_ioctl(bdev, mode, CCISS_BIG_PASSTHRU, (unsigned long)p);
         if (err)
                 return err;
         err |=
@@ -1311,11 +1299,14 @@ static int cciss_getpciinfo(ctlr_info_t *h, void __user *argp)
 static int cciss_getintinfo(ctlr_info_t *h, void __user *argp)
 {
         cciss_coalint_struct intinfo;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         intinfo.delay = readl(&h->cfgtable->HostWrite.CoalIntDelay);
         intinfo.count = readl(&h->cfgtable->HostWrite.CoalIntCount);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user
             (argp, &intinfo, sizeof(cciss_coalint_struct)))
                 return -EFAULT;
@@ -1356,12 +1347,15 @@ static int cciss_setintinfo(ctlr_info_t *h, void __user *argp)
 static int cciss_getnodename(ctlr_info_t *h, void __user *argp)
 {
         NodeName_type NodeName;
+        unsigned long flags;
         int i;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         for (i = 0; i < 16; i++)
                 NodeName[i] = readb(&h->cfgtable->ServerName[i]);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, NodeName, sizeof(NodeName_type)))
                 return -EFAULT;
         return 0;
@@ -1398,10 +1392,13 @@ static int cciss_setnodename(ctlr_info_t *h, void __user *argp)
 static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
 {
         Heartbeat_type heartbeat;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         heartbeat = readl(&h->cfgtable->HeartBeat);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, &heartbeat, sizeof(Heartbeat_type)))
                 return -EFAULT;
         return 0;
@@ -1410,10 +1407,13 @@ static int cciss_getheartbeat(ctlr_info_t *h, void __user *argp)
 static int cciss_getbustypes(ctlr_info_t *h, void __user *argp)
 {
         BusTypes_type BusTypes;
+        unsigned long flags;
 
         if (!argp)
                 return -EINVAL;
+        spin_lock_irqsave(&h->lock, flags);
         BusTypes = readl(&h->cfgtable->BusTypes);
+        spin_unlock_irqrestore(&h->lock, flags);
         if (copy_to_user(argp, &BusTypes, sizeof(BusTypes_type)))
                 return -EFAULT;
         return 0;
diff --git a/drivers/block/mtip32xx/mtip32xx.c b/drivers/block/mtip32xx/mtip32xx.c
index 847107ef0cce..20dd52a2f92f 100644
--- a/drivers/block/mtip32xx/mtip32xx.c
+++ b/drivers/block/mtip32xx/mtip32xx.c
@@ -3002,7 +3002,8 @@ static int mtip_hw_debugfs_init(struct driver_data *dd)
 
 static void mtip_hw_debugfs_exit(struct driver_data *dd)
 {
-        debugfs_remove_recursive(dd->dfs_node);
+        if (dd->dfs_node)
+                debugfs_remove_recursive(dd->dfs_node);
 }
 
 
@@ -3863,7 +3864,7 @@ static void mtip_make_request(struct request_queue *queue, struct bio *bio)
         struct driver_data *dd = queue->queuedata;
         struct scatterlist *sg;
         struct bio_vec *bvec;
-        int nents = 0;
+        int i, nents = 0;
         int tag = 0, unaligned = 0;
 
         if (unlikely(dd->dd_flag & MTIP_DDF_STOP_IO)) {
@@ -3921,11 +3922,12 @@ static void mtip_make_request(struct request_queue *queue, struct bio *bio)
                 }
 
                 /* Create the scatter list for this bio. */
-                bio_for_each_segment(bvec, bio, nents) {
+                bio_for_each_segment(bvec, bio, i) {
                         sg_set_page(&sg[nents],
                                         bvec->bv_page,
                                         bvec->bv_len,
                                         bvec->bv_offset);
+                        nents++;
                 }
 
                 /* Issue the read/write. */
diff --git a/drivers/block/nvme-core.c b/drivers/block/nvme-core.c
index 8efdfaa44a59..ce79a590b45b 100644
--- a/drivers/block/nvme-core.c
+++ b/drivers/block/nvme-core.c
@@ -629,7 +629,7 @@ static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
         struct nvme_command *cmnd;
         struct nvme_iod *iod;
         enum dma_data_direction dma_dir;
-        int cmdid, length, result = -ENOMEM;
+        int cmdid, length, result;
         u16 control;
         u32 dsmgmt;
         int psegs = bio_phys_segments(ns->queue, bio);
@@ -640,6 +640,7 @@ static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
                         return result;
         }
 
+        result = -ENOMEM;
         iod = nvme_alloc_iod(psegs, bio->bi_size, GFP_ATOMIC);
         if (!iod)
                 goto nomem;
@@ -977,6 +978,8 @@ static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
 
                 if (timeout && !time_after(now, info[cmdid].timeout))
                         continue;
+                if (info[cmdid].ctx == CMD_CTX_CANCELLED)
+                        continue;
                 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d\n", cmdid);
                 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
                 fn(nvmeq->dev, ctx, &cqe);
@@ -1206,7 +1209,7 @@ struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
 
         if (addr & 3)
                 return ERR_PTR(-EINVAL);
-        if (!length)
+        if (!length || length > INT_MAX - PAGE_SIZE)
                 return ERR_PTR(-EINVAL);
 
         offset = offset_in_page(addr);
@@ -1227,7 +1230,8 @@ struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
         sg_init_table(sg, count);
         for (i = 0; i < count; i++) {
                 sg_set_page(&sg[i], pages[i],
-                                min_t(int, length, PAGE_SIZE - offset), offset);
+                            min_t(unsigned, length, PAGE_SIZE - offset),
+                            offset);
                 length -= (PAGE_SIZE - offset);
                 offset = 0;
         }
@@ -1435,7 +1439,7 @@ static int nvme_user_admin_cmd(struct nvme_dev *dev,
                 nvme_free_iod(dev, iod);
         }
 
-        if (!status && copy_to_user(&ucmd->result, &cmd.result,
+        if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
                                                         sizeof(cmd.result)))
                 status = -EFAULT;
 
@@ -1633,7 +1637,8 @@ static int set_queue_count(struct nvme_dev *dev, int count)
 
 static int nvme_setup_io_queues(struct nvme_dev *dev)
 {
-        int result, cpu, i, nr_io_queues, db_bar_size, q_depth;
+        struct pci_dev *pdev = dev->pci_dev;
+        int result, cpu, i, nr_io_queues, db_bar_size, q_depth, q_count;
 
         nr_io_queues = num_online_cpus();
         result = set_queue_count(dev, nr_io_queues);
@@ -1642,14 +1647,14 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
         if (result < nr_io_queues)
                 nr_io_queues = result;
 
+        q_count = nr_io_queues;
         /* Deregister the admin queue's interrupt */
         free_irq(dev->entry[0].vector, dev->queues[0]);
 
         db_bar_size = 4096 + ((nr_io_queues + 1) << (dev->db_stride + 3));
         if (db_bar_size > 8192) {
                 iounmap(dev->bar);
-                dev->bar = ioremap(pci_resource_start(dev->pci_dev, 0),
-                                                                db_bar_size);
+                dev->bar = ioremap(pci_resource_start(pdev, 0), db_bar_size);
                 dev->dbs = ((void __iomem *)dev->bar) + 4096;
                 dev->queues[0]->q_db = dev->dbs;
         }
@@ -1657,19 +1662,36 @@ static int nvme_setup_io_queues(struct nvme_dev *dev)
         for (i = 0; i < nr_io_queues; i++)
                 dev->entry[i].entry = i;
         for (;;) {
-                result = pci_enable_msix(dev->pci_dev, dev->entry,
-                                                                nr_io_queues);
+                result = pci_enable_msix(pdev, dev->entry, nr_io_queues);
                 if (result == 0) {
                         break;
                 } else if (result > 0) {
                         nr_io_queues = result;
                         continue;
                 } else {
-                        nr_io_queues = 1;
+                        nr_io_queues = 0;
                         break;
                 }
         }
 
+        if (nr_io_queues == 0) {
+                nr_io_queues = q_count;
+                for (;;) {
+                        result = pci_enable_msi_block(pdev, nr_io_queues);
+                        if (result == 0) {
+                                for (i = 0; i < nr_io_queues; i++)
+                                        dev->entry[i].vector = i + pdev->irq;
+                                break;
+                        } else if (result > 0) {
+                                nr_io_queues = result;
+                                continue;
+                        } else {
+                                nr_io_queues = 1;
+                                break;
+                        }
+                }
+        }
+
         result = queue_request_irq(dev, dev->queues[0], "nvme admin");
         /* XXX: handle failure here */
 
@@ -1850,7 +1872,10 @@ static void nvme_free_dev(struct kref *kref)
 {
         struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
         nvme_dev_remove(dev);
-        pci_disable_msix(dev->pci_dev);
+        if (dev->pci_dev->msi_enabled)
+                pci_disable_msi(dev->pci_dev);
+        else if (dev->pci_dev->msix_enabled)
+                pci_disable_msix(dev->pci_dev);
         iounmap(dev->bar);
         nvme_release_instance(dev);
         nvme_release_prp_pools(dev);
@@ -1923,8 +1948,14 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
         INIT_LIST_HEAD(&dev->namespaces);
         dev->pci_dev = pdev;
         pci_set_drvdata(pdev, dev);
-        dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
-        dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
+
+        if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(64)))
+                dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(64));
+        else if (!dma_set_mask(&pdev->dev, DMA_BIT_MASK(32)))
+                dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
+        else
+                goto disable;
+
         result = nvme_set_instance(dev);
         if (result)
                 goto disable;
@@ -1977,7 +2008,10 @@ static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  unmap:
         iounmap(dev->bar);
  disable_msix:
-        pci_disable_msix(pdev);
+        if (dev->pci_dev->msi_enabled)
+                pci_disable_msi(dev->pci_dev);
+        else if (dev->pci_dev->msix_enabled)
+                pci_disable_msix(dev->pci_dev);
         nvme_release_instance(dev);
         nvme_release_prp_pools(dev);
  disable:
diff --git a/drivers/block/nvme-scsi.c b/drivers/block/nvme-scsi.c
index fed54b039893..102de2f52b5c 100644
--- a/drivers/block/nvme-scsi.c
+++ b/drivers/block/nvme-scsi.c
@@ -44,7 +44,6 @@
 #include <linux/sched.h>
 #include <linux/slab.h>
 #include <linux/types.h>
-#include <linux/version.h>
 #include <scsi/sg.h>
 #include <scsi/scsi.h>
 
@@ -1654,7 +1653,7 @@ static void nvme_trans_modesel_save_bd(struct nvme_ns *ns, u8 *parm_list,
         }
 }
 
-static u16 nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
+static int nvme_trans_modesel_get_mp(struct nvme_ns *ns, struct sg_io_hdr *hdr,
                                         u8 *mode_page, u8 page_code)
 {
         int res = SNTI_TRANSLATION_SUCCESS;
diff --git a/drivers/block/pktcdvd.c b/drivers/block/pktcdvd.c
index 3c08983e600a..f5d0ea11d9fd 100644
--- a/drivers/block/pktcdvd.c
+++ b/drivers/block/pktcdvd.c
@@ -83,7 +83,8 @@
 
 #define MAX_SPEED 0xffff
 
-#define ZONE(sector, pd) (((sector) + (pd)->offset) & ~((pd)->settings.size - 1))
+#define ZONE(sector, pd) (((sector) + (pd)->offset) & \
+                        ~(sector_t)((pd)->settings.size - 1))
 
 static DEFINE_MUTEX(pktcdvd_mutex);
 static struct pktcdvd_device *pkt_devs[MAX_WRITERS];
diff --git a/drivers/block/rbd.c b/drivers/block/rbd.c
index d6d314027b5d..3063452e55da 100644
--- a/drivers/block/rbd.c
+++ b/drivers/block/rbd.c
@@ -519,8 +519,8 @@ static const struct block_device_operations rbd_bd_ops = {
 };
 
 /*
- * Initialize an rbd client instance.
- * We own *ceph_opts.
+ * Initialize an rbd client instance.  Success or not, this function
+ * consumes ceph_opts.
  */
 static struct rbd_client *rbd_client_create(struct ceph_options *ceph_opts)
 {
@@ -675,7 +675,8 @@ static int parse_rbd_opts_token(char *c, void *private)
 
 /*
  * Get a ceph client with specific addr and configuration, if one does
- * not exist create it.
+ * not exist create it.  Either way, ceph_opts is consumed by this
+ * function.
  */
 static struct rbd_client *rbd_get_client(struct ceph_options *ceph_opts)
 {
@@ -4697,8 +4698,10 @@ out:
         return ret;
 }
 
-/* Undo whatever state changes are made by v1 or v2 image probe */
-
+/*
+ * Undo whatever state changes are made by v1 or v2 header info
+ * call.
+ */
 static void rbd_dev_unprobe(struct rbd_device *rbd_dev)
 {
         struct rbd_image_header *header;
@@ -4902,9 +4905,10 @@ static int rbd_dev_image_probe(struct rbd_device *rbd_dev, bool mapping)
         int tmp;
 
         /*
-         * Get the id from the image id object.  If it's not a
-         * format 2 image, we'll get ENOENT back, and we'll assume
-         * it's a format 1 image.
+         * Get the id from the image id object.  Unless there's an
+         * error, rbd_dev->spec->image_id will be filled in with
+         * a dynamically-allocated string, and rbd_dev->image_format
+         * will be set to either 1 or 2.
          */
         ret = rbd_dev_image_id(rbd_dev);
         if (ret)
@@ -4992,7 +4996,6 @@ static ssize_t rbd_add(struct bus_type *bus,
                 rc = PTR_ERR(rbdc);
                 goto err_out_args;
         }
-        ceph_opts = NULL;       /* rbd_dev client now owns this */
 
         /* pick the pool */
         osdc = &rbdc->client->osdc;
@@ -5027,18 +5030,18 @@ static ssize_t rbd_add(struct bus_type *bus,
         rbd_dev->mapping.read_only = read_only;
 
         rc = rbd_dev_device_setup(rbd_dev);
-        if (!rc)
-                return count;
+        if (rc) {
+                rbd_dev_image_release(rbd_dev);
+                goto err_out_module;
+        }
+
+        return count;
 
-        rbd_dev_image_release(rbd_dev);
 err_out_rbd_dev:
         rbd_dev_destroy(rbd_dev);
 err_out_client:
         rbd_put_client(rbdc);
 err_out_args:
-        if (ceph_opts)
-                ceph_destroy_options(ceph_opts);
-        kfree(rbd_opts);
         rbd_spec_put(spec);
 err_out_module:
         module_put(THIS_MODULE);
diff --git a/drivers/bluetooth/Kconfig b/drivers/bluetooth/Kconfig
index fdfd61a2d523..11a6104a1e4f 100644
--- a/drivers/bluetooth/Kconfig
+++ b/drivers/bluetooth/Kconfig
@@ -201,7 +201,7 @@ config BT_MRVL
           The core driver to support Marvell Bluetooth devices.
 
           This driver is required if you want to support
-          Marvell Bluetooth devices, such as 8688/8787/8797.
+          Marvell Bluetooth devices, such as 8688/8787/8797/8897.
 
           Say Y here to compile Marvell Bluetooth driver
           into the kernel or say M to compile it as module.
@@ -214,7 +214,7 @@ config BT_MRVL_SDIO
           The driver for Marvell Bluetooth chipsets with SDIO interface.
 
           This driver is required if you want to use Marvell Bluetooth
-          devices with SDIO interface. Currently SD8688/SD8787/SD8797
+          devices with SDIO interface. Currently SD8688/SD8787/SD8797/SD8897
           chipsets are supported.
 
           Say Y here to compile support for Marvell BT-over-SDIO driver
diff --git a/drivers/bluetooth/btmrvl_sdio.c b/drivers/bluetooth/btmrvl_sdio.c
index c63488c54f4a..13693b7a0d5c 100644
--- a/drivers/bluetooth/btmrvl_sdio.c
+++ b/drivers/bluetooth/btmrvl_sdio.c
@@ -82,6 +82,23 @@ static const struct btmrvl_sdio_card_reg btmrvl_reg_87xx = {
         .io_port_2 = 0x7a,
 };
 
+static const struct btmrvl_sdio_card_reg btmrvl_reg_88xx = {
+        .cfg = 0x00,
+        .host_int_mask = 0x02,
+        .host_intstatus = 0x03,
+        .card_status = 0x50,
+        .sq_read_base_addr_a0 = 0x60,
+        .sq_read_base_addr_a1 = 0x61,
+        .card_revision = 0xbc,
+        .card_fw_status0 = 0xc0,
+        .card_fw_status1 = 0xc1,
+        .card_rx_len = 0xc2,
+        .card_rx_unit = 0xc3,
+        .io_port_0 = 0xd8,
+        .io_port_1 = 0xd9,
+        .io_port_2 = 0xda,
+};
+
 static const struct btmrvl_sdio_device btmrvl_sdio_sd8688 = {
         .helper         = "mrvl/sd8688_helper.bin",
         .firmware       = "mrvl/sd8688.bin",
@@ -103,6 +120,13 @@ static const struct btmrvl_sdio_device btmrvl_sdio_sd8797 = {
         .sd_blksz_fw_dl = 256,
 };
 
+static const struct btmrvl_sdio_device btmrvl_sdio_sd8897 = {
+        .helper         = NULL,
+        .firmware       = "mrvl/sd8897_uapsta.bin",
+        .reg            = &btmrvl_reg_88xx,
+        .sd_blksz_fw_dl = 256,
+};
+
 static const struct sdio_device_id btmrvl_sdio_ids[] = {
         /* Marvell SD8688 Bluetooth device */
         { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x9105),
@@ -116,6 +140,9 @@ static const struct sdio_device_id btmrvl_sdio_ids[] = {
         /* Marvell SD8797 Bluetooth device */
         { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x912A),
                         .driver_data = (unsigned long) &btmrvl_sdio_sd8797 },
+        /* Marvell SD8897 Bluetooth device */
+        { SDIO_DEVICE(SDIO_VENDOR_ID_MARVELL, 0x912E),
+                        .driver_data = (unsigned long) &btmrvl_sdio_sd8897 },
 
         { }     /* Terminating entry */
 };
@@ -1194,3 +1221,4 @@ MODULE_FIRMWARE("mrvl/sd8688_helper.bin");
 MODULE_FIRMWARE("mrvl/sd8688.bin");
 MODULE_FIRMWARE("mrvl/sd8787_uapsta.bin");
 MODULE_FIRMWARE("mrvl/sd8797_uapsta.bin");
+MODULE_FIRMWARE("mrvl/sd8897_uapsta.bin");
diff --git a/drivers/bus/Kconfig b/drivers/bus/Kconfig
index b05ecab915c4..5286e2d333b0 100644
--- a/drivers/bus/Kconfig
+++ b/drivers/bus/Kconfig
@@ -26,4 +26,11 @@ config OMAP_INTERCONNECT
 
         help
           Driver to enable OMAP interconnect error handling driver.
+
+config ARM_CCI
+        bool "ARM CCI driver support"
+        depends on ARM
+        help
+          Driver supporting the CCI cache coherent interconnect for ARM
+          platforms.
 endmenu
diff --git a/drivers/bus/Makefile b/drivers/bus/Makefile
index 3c7b53c12091..670cea443802 100644
--- a/drivers/bus/Makefile
+++ b/drivers/bus/Makefile
@@ -7,3 +7,5 @@ obj-$(CONFIG_OMAP_OCP2SCP)	+= omap-ocp2scp.o
 
 # Interconnect bus driver for OMAP SoCs.
 obj-$(CONFIG_OMAP_INTERCONNECT) += omap_l3_smx.o omap_l3_noc.o
+# CCI cache coherent interconnect for ARM platforms
+obj-$(CONFIG_ARM_CCI)           += arm-cci.o
diff --git a/drivers/bus/arm-cci.c b/drivers/bus/arm-cci.c
new file mode 100644
index 000000000000..733288967d4d
--- /dev/null
+++ b/drivers/bus/arm-cci.c
@@ -0,0 +1,533 @@
+/*
+ * CCI cache coherent interconnect driver
+ *
+ * Copyright (C) 2013 ARM Ltd.
+ * Author: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/arm-cci.h>
+#include <linux/io.h>
+#include <linux/module.h>
+#include <linux/of_address.h>
+#include <linux/slab.h>
+
+#include <asm/cacheflush.h>
+#include <asm/smp_plat.h>
+
+#define CCI_PORT_CTRL           0x0
+#define CCI_CTRL_STATUS         0xc
+
+#define CCI_ENABLE_SNOOP_REQ    0x1
+#define CCI_ENABLE_DVM_REQ      0x2
+#define CCI_ENABLE_REQ          (CCI_ENABLE_SNOOP_REQ | CCI_ENABLE_DVM_REQ)
+
+struct cci_nb_ports {
+        unsigned int nb_ace;
+        unsigned int nb_ace_lite;
+};
+
+enum cci_ace_port_type {
+        ACE_INVALID_PORT = 0x0,
+        ACE_PORT,
+        ACE_LITE_PORT,
+};
+
+struct cci_ace_port {
+        void __iomem *base;
+        unsigned long phys;
+        enum cci_ace_port_type type;
+        struct device_node *dn;
+};
+
+static struct cci_ace_port *ports;
+static unsigned int nb_cci_ports;
+
+static void __iomem *cci_ctrl_base;
+static unsigned long cci_ctrl_phys;
+
+struct cpu_port {
+        u64 mpidr;
+        u32 port;
+};
+
+/*
+ * Use the port MSB as valid flag, shift can be made dynamic
+ * by computing number of bits required for port indexes.
+ * Code disabling CCI cpu ports runs with D-cache invalidated
+ * and SCTLR bit clear so data accesses must be kept to a minimum
+ * to improve performance; for now shift is left static to
+ * avoid one more data access while disabling the CCI port.
+ */
+#define PORT_VALID_SHIFT        31
+#define PORT_VALID              (0x1 << PORT_VALID_SHIFT)
+
+static inline void init_cpu_port(struct cpu_port *port, u32 index, u64 mpidr)
+{
+        port->port = PORT_VALID | index;
+        port->mpidr = mpidr;
+}
+
+static inline bool cpu_port_is_valid(struct cpu_port *port)
+{
+        return !!(port->port & PORT_VALID);
+}
+
+static inline bool cpu_port_match(struct cpu_port *port, u64 mpidr)
+{
+        return port->mpidr == (mpidr & MPIDR_HWID_BITMASK);
+}
+
+static struct cpu_port cpu_port[NR_CPUS];
+
+/**
+ * __cci_ace_get_port - Function to retrieve the port index connected to
+ *                      a cpu or device.
+ *
+ * @dn: device node of the device to look-up
+ * @type: port type
+ *
+ * Return value:
+ *      - CCI port index if success
+ *      - -ENODEV if failure
+ */
+static int __cci_ace_get_port(struct device_node *dn, int type)
+{
+        int i;
+        bool ace_match;
+        struct device_node *cci_portn;
+
+        cci_portn = of_parse_phandle(dn, "cci-control-port", 0);
+        for (i = 0; i < nb_cci_ports; i++) {
+                ace_match = ports[i].type == type;
+                if (ace_match && cci_portn == ports[i].dn)
+                        return i;
+        }
+        return -ENODEV;
+}
+
+int cci_ace_get_port(struct device_node *dn)
+{
+        return __cci_ace_get_port(dn, ACE_LITE_PORT);
+}
+EXPORT_SYMBOL_GPL(cci_ace_get_port);
+
+static void __init cci_ace_init_ports(void)
+{
+        int port, ac, cpu;
+        u64 hwid;
+        const u32 *cell;
+        struct device_node *cpun, *cpus;
+
+        cpus = of_find_node_by_path("/cpus");
+        if (WARN(!cpus, "Missing cpus node, bailing out\n"))
+                return;
+
+        if (WARN_ON(of_property_read_u32(cpus, "#address-cells", &ac)))
+                ac = of_n_addr_cells(cpus);
+
+        /*
+         * Port index look-up speeds up the function disabling ports by CPU,
+         * since the logical to port index mapping is done once and does
+         * not change after system boot.
+         * The stashed index array is initialized for all possible CPUs
+         * at probe time.
+         */
+        for_each_child_of_node(cpus, cpun) {
+                if (of_node_cmp(cpun->type, "cpu"))
+                        continue;
+                cell = of_get_property(cpun, "reg", NULL);
+                if (WARN(!cell, "%s: missing reg property\n", cpun->full_name))
+                        continue;
+
+                hwid = of_read_number(cell, ac);
+                cpu = get_logical_index(hwid & MPIDR_HWID_BITMASK);
+
+                if (cpu < 0 || !cpu_possible(cpu))
+                        continue;
+                port = __cci_ace_get_port(cpun, ACE_PORT);
+                if (port < 0)
+                        continue;
+
+                init_cpu_port(&cpu_port[cpu], port, cpu_logical_map(cpu));
+        }
+
+        for_each_possible_cpu(cpu) {
+                WARN(!cpu_port_is_valid(&cpu_port[cpu]),
+                        "CPU %u does not have an associated CCI port\n",
+                        cpu);
+        }
+}
+/*
+ * Functions to enable/disable a CCI interconnect slave port
+ *
+ * They are called by low-level power management code to disable slave
+ * interfaces snoops and DVM broadcast.
+ * Since they may execute with cache data allocation disabled and
+ * after the caches have been cleaned and invalidated the functions provide
+ * no explicit locking since they may run with D-cache disabled, so normal
+ * cacheable kernel locks based on ldrex/strex may not work.
+ * Locking has to be provided by BSP implementations to ensure proper
+ * operations.
+ */
+
+/**
+ * cci_port_control() - function to control a CCI port
+ *
+ * @port: index of the port to setup
+ * @enable: if true enables the port, if false disables it
+ */
+static void notrace cci_port_control(unsigned int port, bool enable)
+{
+        void __iomem *base = ports[port].base;
+
+        writel_relaxed(enable ? CCI_ENABLE_REQ : 0, base + CCI_PORT_CTRL);
+        /*
+         * This function is called from power down procedures
+         * and must not execute any instruction that might
+         * cause the processor to be put in a quiescent state
+         * (eg wfi). Hence, cpu_relax() can not be added to this
+         * read loop to optimize power, since it might hide possibly
+         * disruptive operations.
+         */
+        while (readl_relaxed(cci_ctrl_base + CCI_CTRL_STATUS) & 0x1)
+                        ;
+}
+
+/**
+ * cci_disable_port_by_cpu() - function to disable a CCI port by CPU
+ *                             reference
+ *
+ * @mpidr: mpidr of the CPU whose CCI port should be disabled
+ *
+ * Disabling a CCI port for a CPU implies disabling the CCI port
+ * controlling that CPU cluster. Code disabling CPU CCI ports
+ * must make sure that the CPU running the code is the last active CPU
+ * in the cluster ie all other CPUs are quiescent in a low power state.
+ *
+ * Return:
+ *      0 on success
+ *      -ENODEV on port look-up failure
+ */
+int notrace cci_disable_port_by_cpu(u64 mpidr)
+{
+        int cpu;
+        bool is_valid;
+        for (cpu = 0; cpu < nr_cpu_ids; cpu++) {
+                is_valid = cpu_port_is_valid(&cpu_port[cpu]);
+                if (is_valid && cpu_port_match(&cpu_port[cpu], mpidr)) {
+                        cci_port_control(cpu_port[cpu].port, false);
+                        return 0;
+                }
+        }
+        return -ENODEV;
+}
+EXPORT_SYMBOL_GPL(cci_disable_port_by_cpu);
+
+/**
+ * cci_enable_port_for_self() - enable a CCI port for calling CPU
+ *
+ * Enabling a CCI port for the calling CPU implies enabling the CCI
+ * port controlling that CPU's cluster. Caller must make sure that the
+ * CPU running the code is the first active CPU in the cluster and all
+ * other CPUs are quiescent in a low power state  or waiting for this CPU
+ * to complete the CCI initialization.
+ *
+ * Because this is called when the MMU is still off and with no stack,
+ * the code must be position independent and ideally rely on callee
+ * clobbered registers only.  To achieve this we must code this function
+ * entirely in assembler.
+ *
+ * On success this returns with the proper CCI port enabled.  In case of
+ * any failure this never returns as the inability to enable the CCI is
+ * fatal and there is no possible recovery at this stage.
+ */
+asmlinkage void __naked cci_enable_port_for_self(void)
+{
+        asm volatile ("\n"
+"       .arch armv7-a\n"
+"       mrc     p15, 0, r0, c0, c0, 5   @ get MPIDR value \n"
+"       and     r0, r0, #"__stringify(MPIDR_HWID_BITMASK)" \n"
+"       adr     r1, 5f \n"
+"       ldr     r2, [r1] \n"
+"       add     r1, r1, r2              @ &cpu_port \n"
+"       add     ip, r1, %[sizeof_cpu_port] \n"
+
+        /* Loop over the cpu_port array looking for a matching MPIDR */
+"1:     ldr     r2, [r1, %[offsetof_cpu_port_mpidr_lsb]] \n"
+"       cmp     r2, r0                  @ compare MPIDR \n"
+"       bne     2f \n"
+
+        /* Found a match, now test port validity */
+"       ldr     r3, [r1, %[offsetof_cpu_port_port]] \n"
+"       tst     r3, #"__stringify(PORT_VALID)" \n"
+"       bne     3f \n"
+
+        /* no match, loop with the next cpu_port entry */
+"2:     add     r1, r1, %[sizeof_struct_cpu_port] \n"
+"       cmp     r1, ip                  @ done? \n"
+"       blo     1b \n"
+
+        /* CCI port not found -- cheaply try to stall this CPU */
+"cci_port_not_found: \n"
+"       wfi \n"
+"       wfe \n"
+"       b       cci_port_not_found \n"
+
+        /* Use matched port index to look up the corresponding ports entry */
+"3:     bic     r3, r3, #"__stringify(PORT_VALID)" \n"
+"       adr     r0, 6f \n"
+"       ldmia   r0, {r1, r2} \n"
+"       sub     r1, r1, r0              @ virt - phys \n"
+"       ldr     r0, [r0, r2]            @ *(&ports) \n"
+"       mov     r2, %[sizeof_struct_ace_port] \n"
+"       mla     r0, r2, r3, r0          @ &ports[index] \n"
+"       sub     r0, r0, r1              @ virt_to_phys() \n"
+
+        /* Enable the CCI port */
+"       ldr     r0, [r0, %[offsetof_port_phys]] \n"
+"       mov     r3, #"__stringify(CCI_ENABLE_REQ)" \n"
+"       str     r3, [r0, #"__stringify(CCI_PORT_CTRL)"] \n"
+
+        /* poll the status reg for completion */
+"       adr     r1, 7f \n"
+"       ldr     r0, [r1] \n"
+"       ldr     r0, [r0, r1]            @ cci_ctrl_base \n"
+"4:     ldr     r1, [r0, #"__stringify(CCI_CTRL_STATUS)"] \n"
+"       tst     r1, #1 \n"
+"       bne     4b \n"
+
+"       mov     r0, #0 \n"
+"       bx      lr \n"
+
+"       .align  2 \n"
+"5:     .word   cpu_port - . \n"
+"6:     .word   . \n"
+"       .word   ports - 6b \n"
+"7:     .word   cci_ctrl_phys - . \n"
+        : :
+        [sizeof_cpu_port] "i" (sizeof(cpu_port)),
+#ifndef __ARMEB__
+        [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)),
+#else
+        [offsetof_cpu_port_mpidr_lsb] "i" (offsetof(struct cpu_port, mpidr)+4),
+#endif
+        [offsetof_cpu_port_port] "i" (offsetof(struct cpu_port, port)),
+        [sizeof_struct_cpu_port] "i" (sizeof(struct cpu_port)),
+        [sizeof_struct_ace_port] "i" (sizeof(struct cci_ace_port)),
+        [offsetof_port_phys] "i" (offsetof(struct cci_ace_port, phys)) );
+
+        unreachable();
+}
+
+/**
+ * __cci_control_port_by_device() - function to control a CCI port by device
+ *                                  reference
+ *
+ * @dn: device node pointer of the device whose CCI port should be
+ *      controlled
+ * @enable: if true enables the port, if false disables it
+ *
+ * Return:
+ *      0 on success
+ *      -ENODEV on port look-up failure
+ */
+int notrace __cci_control_port_by_device(struct device_node *dn, bool enable)
+{
+        int port;
+
+        if (!dn)
+                return -ENODEV;
+
+        port = __cci_ace_get_port(dn, ACE_LITE_PORT);
+        if (WARN_ONCE(port < 0, "node %s ACE lite port look-up failure\n",
+                                dn->full_name))
+                return -ENODEV;
+        cci_port_control(port, enable);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_device);
+
+/**
+ * __cci_control_port_by_index() - function to control a CCI port by port index
+ *
+ * @port: port index previously retrieved with cci_ace_get_port()
+ * @enable: if true enables the port, if false disables it
+ *
+ * Return:
+ *      0 on success
+ *      -ENODEV on port index out of range
+ *      -EPERM if operation carried out on an ACE PORT
+ */
+int notrace __cci_control_port_by_index(u32 port, bool enable)
+{
+        if (port >= nb_cci_ports || ports[port].type == ACE_INVALID_PORT)
+                return -ENODEV;
+        /*
+         * CCI control for ports connected to CPUS is extremely fragile
+         * and must be made to go through a specific and controlled
+         * interface (ie cci_disable_port_by_cpu(); control by general purpose
+         * indexing is therefore disabled for ACE ports.
+         */
+        if (ports[port].type == ACE_PORT)
+                return -EPERM;
+
+        cci_port_control(port, enable);
+        return 0;
+}
+EXPORT_SYMBOL_GPL(__cci_control_port_by_index);
+
+static const struct cci_nb_ports cci400_ports = {
+        .nb_ace = 2,
+        .nb_ace_lite = 3
+};
+
+static const struct of_device_id arm_cci_matches[] = {
+        {.compatible = "arm,cci-400", .data = &cci400_ports },
+        {},
+};
+
+static const struct of_device_id arm_cci_ctrl_if_matches[] = {
+        {.compatible = "arm,cci-400-ctrl-if", },
+        {},
+};
+
+static int __init cci_probe(void)
+{
+        struct cci_nb_ports const *cci_config;
+        int ret, i, nb_ace = 0, nb_ace_lite = 0;
+        struct device_node *np, *cp;
+        struct resource res;
+        const char *match_str;
+        bool is_ace;
+
+        np = of_find_matching_node(NULL, arm_cci_matches);
+        if (!np)
+                return -ENODEV;
+
+        cci_config = of_match_node(arm_cci_matches, np)->data;
+        if (!cci_config)
+                return -ENODEV;
+
+        nb_cci_ports = cci_config->nb_ace + cci_config->nb_ace_lite;
+
+        ports = kcalloc(sizeof(*ports), nb_cci_ports, GFP_KERNEL);
+        if (!ports)
+                return -ENOMEM;
+
+        ret = of_address_to_resource(np, 0, &res);
+        if (!ret) {
+                cci_ctrl_base = ioremap(res.start, resource_size(&res));
+                cci_ctrl_phys = res.start;
+        }
+        if (ret || !cci_ctrl_base) {
+                WARN(1, "unable to ioremap CCI ctrl\n");
+                ret = -ENXIO;
+                goto memalloc_err;
+        }
+
+        for_each_child_of_node(np, cp) {
+                if (!of_match_node(arm_cci_ctrl_if_matches, cp))
+                        continue;
+
+                i = nb_ace + nb_ace_lite;
+
+                if (i >= nb_cci_ports)
+                        break;
+
+                if (of_property_read_string(cp, "interface-type",
+                                        &match_str)) {
+                        WARN(1, "node %s missing interface-type property\n",
+                                  cp->full_name);
+                        continue;
+                }
+                is_ace = strcmp(match_str, "ace") == 0;
+                if (!is_ace && strcmp(match_str, "ace-lite")) {
+                        WARN(1, "node %s containing invalid interface-type property, skipping it\n",
+                                        cp->full_name);
+                        continue;
+                }
+
+                ret = of_address_to_resource(cp, 0, &res);
+                if (!ret) {
+                        ports[i].base = ioremap(res.start, resource_size(&res));
+                        ports[i].phys = res.start;
+                }
+                if (ret || !ports[i].base) {
+                        WARN(1, "unable to ioremap CCI port %d\n", i);
+                        continue;
+                }
+
+                if (is_ace) {
+                        if (WARN_ON(nb_ace >= cci_config->nb_ace))
+                                continue;
+                        ports[i].type = ACE_PORT;
+                        ++nb_ace;
+                } else {
+                        if (WARN_ON(nb_ace_lite >= cci_config->nb_ace_lite))
+                                continue;
+                        ports[i].type = ACE_LITE_PORT;
+                        ++nb_ace_lite;
+                }
+                ports[i].dn = cp;
+        }
+
+         /* initialize a stashed array of ACE ports to speed-up look-up */
+        cci_ace_init_ports();
+
+        /*
+         * Multi-cluster systems may need this data when non-coherent, during
+         * cluster power-up/power-down. Make sure it reaches main memory.
+         */
+        sync_cache_w(&cci_ctrl_base);
+        sync_cache_w(&cci_ctrl_phys);
+        sync_cache_w(&ports);
+        sync_cache_w(&cpu_port);
+        __sync_cache_range_w(ports, sizeof(*ports) * nb_cci_ports);
+        pr_info("ARM CCI driver probed\n");
+        return 0;
+
+memalloc_err:
+
+        kfree(ports);
+        return ret;
+}
+
+static int cci_init_status = -EAGAIN;
+static DEFINE_MUTEX(cci_probing);
+
+static int __init cci_init(void)
+{
+        if (cci_init_status != -EAGAIN)
+                return cci_init_status;
+
+        mutex_lock(&cci_probing);
+        if (cci_init_status == -EAGAIN)
+                cci_init_status = cci_probe();
+        mutex_unlock(&cci_probing);
+        return cci_init_status;
+}
+
+/*
+ * To sort out early init calls ordering a helper function is provided to
+ * check if the CCI driver has beed initialized. Function check if the driver
+ * has been initialized, if not it calls the init function that probes
+ * the driver and updates the return value.
+ */
+bool __init cci_probed(void)
+{
+        return cci_init() == 0;
+}
+EXPORT_SYMBOL_GPL(cci_probed);
+
+early_initcall(cci_init);
+MODULE_LICENSE("GPL");
+MODULE_DESCRIPTION("ARM CCI support");
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 137d3e730f86..fa435bcf9f1a 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -27,7 +27,7 @@ obj-$(CONFIG_MACH_LOONGSON1)	+= clk-ls1x.o
 obj-$(CONFIG_ARCH_SUNXI)        += sunxi/
 obj-$(CONFIG_ARCH_U8500)        += ux500/
 obj-$(CONFIG_ARCH_VT8500)       += clk-vt8500.o
-obj-$(CONFIG_ARCH_ZYNQ)         += clk-zynq.o
+obj-$(CONFIG_ARCH_ZYNQ)         += zynq/
 obj-$(CONFIG_ARCH_TEGRA)        += tegra/
 obj-$(CONFIG_PLAT_SAMSUNG)      += samsung/
 
diff --git a/drivers/clk/clk-si5351.c b/drivers/clk/clk-si5351.c
index 892728412e9d..24f553673b72 100644
--- a/drivers/clk/clk-si5351.c
+++ b/drivers/clk/clk-si5351.c
@@ -932,7 +932,7 @@ static unsigned long si5351_clkout_recalc_rate(struct clk_hw *hw,
         unsigned char reg;
         unsigned char rdiv;
 
-        if (hwdata->num > 5)
+        if (hwdata->num <= 5)
                 reg = si5351_msynth_params_address(hwdata->num) + 2;
         else
                 reg = SI5351_CLK6_7_OUTPUT_DIVIDER;
@@ -1477,6 +1477,16 @@ static int si5351_i2c_probe(struct i2c_client *client,
                         return -EINVAL;
                 }
                 drvdata->onecell.clks[n] = clk;
+
+                /* set initial clkout rate */
+                if (pdata->clkout[n].rate != 0) {
+                        int ret;
+                        ret = clk_set_rate(clk, pdata->clkout[n].rate);
+                        if (ret != 0) {
+                                dev_err(&client->dev, "Cannot set rate : %d\n",
+                                        ret);
+                        }
+                }
         }
 
         ret = of_clk_add_provider(client->dev.of_node, of_clk_src_onecell_get,
diff --git a/drivers/clk/clk-u300.c b/drivers/clk/clk-u300.c
index a15f7928fb11..8774e058cb6c 100644
--- a/drivers/clk/clk-u300.c
+++ b/drivers/clk/clk-u300.c
@@ -11,7 +11,349 @@
 #include <linux/io.h>
 #include <linux/clk-provider.h>
 #include <linux/spinlock.h>
-#include <mach/syscon.h>
+#include <linux/of.h>
+
+/* APP side SYSCON registers */
+/* CLK Control Register 16bit (R/W) */
+#define U300_SYSCON_CCR                                         (0x0000)
+#define U300_SYSCON_CCR_I2S1_USE_VCXO                           (0x0040)
+#define U300_SYSCON_CCR_I2S0_USE_VCXO                           (0x0020)
+#define U300_SYSCON_CCR_TURN_VCXO_ON                            (0x0008)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_MASK                 (0x0007)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW_POWER            (0x04)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_LOW                  (0x03)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_INTERMEDIATE         (0x02)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_HIGH                 (0x01)
+#define U300_SYSCON_CCR_CLKING_PERFORMANCE_BEST                 (0x00)
+/* CLK Status Register 16bit (R/W) */
+#define U300_SYSCON_CSR                                         (0x0004)
+#define U300_SYSCON_CSR_PLL208_LOCK_IND                         (0x0002)
+#define U300_SYSCON_CSR_PLL13_LOCK_IND                          (0x0001)
+/* Reset lines for SLOW devices 16bit (R/W) */
+#define U300_SYSCON_RSR                                         (0x0014)
+#define U300_SYSCON_RSR_PPM_RESET_EN                            (0x0200)
+#define U300_SYSCON_RSR_ACC_TMR_RESET_EN                        (0x0100)
+#define U300_SYSCON_RSR_APP_TMR_RESET_EN                        (0x0080)
+#define U300_SYSCON_RSR_RTC_RESET_EN                            (0x0040)
+#define U300_SYSCON_RSR_KEYPAD_RESET_EN                         (0x0020)
+#define U300_SYSCON_RSR_GPIO_RESET_EN                           (0x0010)
+#define U300_SYSCON_RSR_EH_RESET_EN                             (0x0008)
+#define U300_SYSCON_RSR_BTR_RESET_EN                            (0x0004)
+#define U300_SYSCON_RSR_UART_RESET_EN                           (0x0002)
+#define U300_SYSCON_RSR_SLOW_BRIDGE_RESET_EN                    (0x0001)
+/* Reset lines for FAST devices 16bit (R/W) */
+#define U300_SYSCON_RFR                                         (0x0018)
+#define U300_SYSCON_RFR_UART1_RESET_ENABLE                      (0x0080)
+#define U300_SYSCON_RFR_SPI_RESET_ENABLE                        (0x0040)
+#define U300_SYSCON_RFR_MMC_RESET_ENABLE                        (0x0020)
+#define U300_SYSCON_RFR_PCM_I2S1_RESET_ENABLE                   (0x0010)
+#define U300_SYSCON_RFR_PCM_I2S0_RESET_ENABLE                   (0x0008)
+#define U300_SYSCON_RFR_I2C1_RESET_ENABLE                       (0x0004)
+#define U300_SYSCON_RFR_I2C0_RESET_ENABLE                       (0x0002)
+#define U300_SYSCON_RFR_FAST_BRIDGE_RESET_ENABLE                (0x0001)
+/* Reset lines for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_RRR                                         (0x001c)
+#define U300_SYSCON_RRR_CDS_RESET_EN                            (0x4000)
+#define U300_SYSCON_RRR_ISP_RESET_EN                            (0x2000)
+#define U300_SYSCON_RRR_INTCON_RESET_EN                         (0x1000)
+#define U300_SYSCON_RRR_MSPRO_RESET_EN                          (0x0800)
+#define U300_SYSCON_RRR_XGAM_RESET_EN                           (0x0100)
+#define U300_SYSCON_RRR_XGAM_VC_SYNC_RESET_EN                   (0x0080)
+#define U300_SYSCON_RRR_NANDIF_RESET_EN                         (0x0040)
+#define U300_SYSCON_RRR_EMIF_RESET_EN                           (0x0020)
+#define U300_SYSCON_RRR_DMAC_RESET_EN                           (0x0010)
+#define U300_SYSCON_RRR_CPU_RESET_EN                            (0x0008)
+#define U300_SYSCON_RRR_APEX_RESET_EN                           (0x0004)
+#define U300_SYSCON_RRR_AHB_RESET_EN                            (0x0002)
+#define U300_SYSCON_RRR_AAIF_RESET_EN                           (0x0001)
+/* Clock enable for SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CESR                                        (0x0020)
+#define U300_SYSCON_CESR_PPM_CLK_EN                             (0x0200)
+#define U300_SYSCON_CESR_ACC_TMR_CLK_EN                         (0x0100)
+#define U300_SYSCON_CESR_APP_TMR_CLK_EN                         (0x0080)
+#define U300_SYSCON_CESR_KEYPAD_CLK_EN                          (0x0040)
+#define U300_SYSCON_CESR_GPIO_CLK_EN                            (0x0010)
+#define U300_SYSCON_CESR_EH_CLK_EN                              (0x0008)
+#define U300_SYSCON_CESR_BTR_CLK_EN                             (0x0004)
+#define U300_SYSCON_CESR_UART_CLK_EN                            (0x0002)
+#define U300_SYSCON_CESR_SLOW_BRIDGE_CLK_EN                     (0x0001)
+/* Clock enable for FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CEFR                                        (0x0024)
+#define U300_SYSCON_CEFR_UART1_CLK_EN                           (0x0200)
+#define U300_SYSCON_CEFR_I2S1_CORE_CLK_EN                       (0x0100)
+#define U300_SYSCON_CEFR_I2S0_CORE_CLK_EN                       (0x0080)
+#define U300_SYSCON_CEFR_SPI_CLK_EN                             (0x0040)
+#define U300_SYSCON_CEFR_MMC_CLK_EN                             (0x0020)
+#define U300_SYSCON_CEFR_I2S1_CLK_EN                            (0x0010)
+#define U300_SYSCON_CEFR_I2S0_CLK_EN                            (0x0008)
+#define U300_SYSCON_CEFR_I2C1_CLK_EN                            (0x0004)
+#define U300_SYSCON_CEFR_I2C0_CLK_EN                            (0x0002)
+#define U300_SYSCON_CEFR_FAST_BRIDGE_CLK_EN                     (0x0001)
+/* Clock enable for the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CERR                                        (0x0028)
+#define U300_SYSCON_CERR_CDS_CLK_EN                             (0x2000)
+#define U300_SYSCON_CERR_ISP_CLK_EN                             (0x1000)
+#define U300_SYSCON_CERR_MSPRO_CLK_EN                           (0x0800)
+#define U300_SYSCON_CERR_AHB_SUBSYS_BRIDGE_CLK_EN               (0x0400)
+#define U300_SYSCON_CERR_SEMI_CLK_EN                            (0x0200)
+#define U300_SYSCON_CERR_XGAM_CLK_EN                            (0x0100)
+#define U300_SYSCON_CERR_VIDEO_ENC_CLK_EN                       (0x0080)
+#define U300_SYSCON_CERR_NANDIF_CLK_EN                          (0x0040)
+#define U300_SYSCON_CERR_EMIF_CLK_EN                            (0x0020)
+#define U300_SYSCON_CERR_DMAC_CLK_EN                            (0x0010)
+#define U300_SYSCON_CERR_CPU_CLK_EN                             (0x0008)
+#define U300_SYSCON_CERR_APEX_CLK_EN                            (0x0004)
+#define U300_SYSCON_CERR_AHB_CLK_EN                             (0x0002)
+#define U300_SYSCON_CERR_AAIF_CLK_EN                            (0x0001)
+/* Single block clock enable 16bit (-/W) */
+#define U300_SYSCON_SBCER                                       (0x002c)
+#define U300_SYSCON_SBCER_PPM_CLK_EN                            (0x0009)
+#define U300_SYSCON_SBCER_ACC_TMR_CLK_EN                        (0x0008)
+#define U300_SYSCON_SBCER_APP_TMR_CLK_EN                        (0x0007)
+#define U300_SYSCON_SBCER_KEYPAD_CLK_EN                         (0x0006)
+#define U300_SYSCON_SBCER_GPIO_CLK_EN                           (0x0004)
+#define U300_SYSCON_SBCER_EH_CLK_EN                             (0x0003)
+#define U300_SYSCON_SBCER_BTR_CLK_EN                            (0x0002)
+#define U300_SYSCON_SBCER_UART_CLK_EN                           (0x0001)
+#define U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN                    (0x0000)
+#define U300_SYSCON_SBCER_UART1_CLK_EN                          (0x0019)
+#define U300_SYSCON_SBCER_I2S1_CORE_CLK_EN                      (0x0018)
+#define U300_SYSCON_SBCER_I2S0_CORE_CLK_EN                      (0x0017)
+#define U300_SYSCON_SBCER_SPI_CLK_EN                            (0x0016)
+#define U300_SYSCON_SBCER_MMC_CLK_EN                            (0x0015)
+#define U300_SYSCON_SBCER_I2S1_CLK_EN                           (0x0014)
+#define U300_SYSCON_SBCER_I2S0_CLK_EN                           (0x0013)
+#define U300_SYSCON_SBCER_I2C1_CLK_EN                           (0x0012)
+#define U300_SYSCON_SBCER_I2C0_CLK_EN                           (0x0011)
+#define U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN                    (0x0010)
+#define U300_SYSCON_SBCER_CDS_CLK_EN                            (0x002D)
+#define U300_SYSCON_SBCER_ISP_CLK_EN                            (0x002C)
+#define U300_SYSCON_SBCER_MSPRO_CLK_EN                          (0x002B)
+#define U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN              (0x002A)
+#define U300_SYSCON_SBCER_SEMI_CLK_EN                           (0x0029)
+#define U300_SYSCON_SBCER_XGAM_CLK_EN                           (0x0028)
+#define U300_SYSCON_SBCER_VIDEO_ENC_CLK_EN                      (0x0027)
+#define U300_SYSCON_SBCER_NANDIF_CLK_EN                         (0x0026)
+#define U300_SYSCON_SBCER_EMIF_CLK_EN                           (0x0025)
+#define U300_SYSCON_SBCER_DMAC_CLK_EN                           (0x0024)
+#define U300_SYSCON_SBCER_CPU_CLK_EN                            (0x0023)
+#define U300_SYSCON_SBCER_APEX_CLK_EN                           (0x0022)
+#define U300_SYSCON_SBCER_AHB_CLK_EN                            (0x0021)
+#define U300_SYSCON_SBCER_AAIF_CLK_EN                           (0x0020)
+/* Single block clock disable 16bit (-/W) */
+#define U300_SYSCON_SBCDR                                       (0x0030)
+/* Same values as above for SBCER */
+/* Clock force SLOW peripherals 16bit (R/W) */
+#define U300_SYSCON_CFSR                                        (0x003c)
+#define U300_SYSCON_CFSR_PPM_CLK_FORCE_EN                       (0x0200)
+#define U300_SYSCON_CFSR_ACC_TMR_CLK_FORCE_EN                   (0x0100)
+#define U300_SYSCON_CFSR_APP_TMR_CLK_FORCE_EN                   (0x0080)
+#define U300_SYSCON_CFSR_KEYPAD_CLK_FORCE_EN                    (0x0020)
+#define U300_SYSCON_CFSR_GPIO_CLK_FORCE_EN                      (0x0010)
+#define U300_SYSCON_CFSR_EH_CLK_FORCE_EN                        (0x0008)
+#define U300_SYSCON_CFSR_BTR_CLK_FORCE_EN                       (0x0004)
+#define U300_SYSCON_CFSR_UART_CLK_FORCE_EN                      (0x0002)
+#define U300_SYSCON_CFSR_SLOW_BRIDGE_CLK_FORCE_EN               (0x0001)
+/* Clock force FAST peripherals 16bit (R/W) */
+#define U300_SYSCON_CFFR                                        (0x40)
+/* Values not defined. Define if you want to use them. */
+/* Clock force the rest of the peripherals 16bit (R/W) */
+#define U300_SYSCON_CFRR                                        (0x44)
+#define U300_SYSCON_CFRR_CDS_CLK_FORCE_EN                       (0x2000)
+#define U300_SYSCON_CFRR_ISP_CLK_FORCE_EN                       (0x1000)
+#define U300_SYSCON_CFRR_MSPRO_CLK_FORCE_EN                     (0x0800)
+#define U300_SYSCON_CFRR_AHB_SUBSYS_BRIDGE_CLK_FORCE_EN         (0x0400)
+#define U300_SYSCON_CFRR_SEMI_CLK_FORCE_EN                      (0x0200)
+#define U300_SYSCON_CFRR_XGAM_CLK_FORCE_EN                      (0x0100)
+#define U300_SYSCON_CFRR_VIDEO_ENC_CLK_FORCE_EN                 (0x0080)
+#define U300_SYSCON_CFRR_NANDIF_CLK_FORCE_EN                    (0x0040)
+#define U300_SYSCON_CFRR_EMIF_CLK_FORCE_EN                      (0x0020)
+#define U300_SYSCON_CFRR_DMAC_CLK_FORCE_EN                      (0x0010)
+#define U300_SYSCON_CFRR_CPU_CLK_FORCE_EN                       (0x0008)
+#define U300_SYSCON_CFRR_APEX_CLK_FORCE_EN                      (0x0004)
+#define U300_SYSCON_CFRR_AHB_CLK_FORCE_EN                       (0x0002)
+#define U300_SYSCON_CFRR_AAIF_CLK_FORCE_EN                      (0x0001)
+/* PLL208 Frequency Control 16bit (R/W) */
+#define U300_SYSCON_PFCR                                        (0x48)
+#define U300_SYSCON_PFCR_DPLL_MULT_NUM                          (0x000F)
+/* Power Management Control 16bit (R/W) */
+#define U300_SYSCON_PMCR                                        (0x50)
+#define U300_SYSCON_PMCR_DCON_ENABLE                            (0x0002)
+#define U300_SYSCON_PMCR_PWR_MGNT_ENABLE                        (0x0001)
+/* Reset Out 16bit (R/W) */
+#define U300_SYSCON_RCR                                         (0x6c)
+#define U300_SYSCON_RCR_RESOUT0_RST_N_DISABLE                   (0x0001)
+/* EMIF Slew Rate Control 16bit (R/W) */
+#define U300_SYSCON_SRCLR                                       (0x70)
+#define U300_SYSCON_SRCLR_MASK                                  (0x03FF)
+#define U300_SYSCON_SRCLR_VALUE                                 (0x03FF)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_B                       (0x0200)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_5_A                       (0x0100)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_B                       (0x0080)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_4_A                       (0x0040)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_B                       (0x0020)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_3_A                       (0x0010)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_B                       (0x0008)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_2_A                       (0x0004)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_B                       (0x0002)
+#define U300_SYSCON_SRCLR_EMIF_1_SLRC_1_A                       (0x0001)
+/* EMIF Clock Control Register 16bit (R/W) */
+#define U300_SYSCON_ECCR                                        (0x0078)
+#define U300_SYSCON_ECCR_MASK                                   (0x000F)
+#define U300_SYSCON_ECCR_EMIF_1_STATIC_CLK_EN_N_DISABLE         (0x0008)
+#define U300_SYSCON_ECCR_EMIF_1_RET_OUT_CLK_EN_N_DISABLE        (0x0004)
+#define U300_SYSCON_ECCR_EMIF_MEMCLK_RET_EN_N_DISABLE           (0x0002)
+#define U300_SYSCON_ECCR_EMIF_SDRCLK_RET_EN_N_DISABLE           (0x0001)
+/* MMC/MSPRO frequency divider register 0 16bit (R/W) */
+#define U300_SYSCON_MMF0R                                       (0x90)
+#define U300_SYSCON_MMF0R_MASK                                  (0x00FF)
+#define U300_SYSCON_MMF0R_FREQ_0_HIGH_MASK                      (0x00F0)
+#define U300_SYSCON_MMF0R_FREQ_0_LOW_MASK                       (0x000F)
+/* MMC/MSPRO frequency divider register 1 16bit (R/W) */
+#define U300_SYSCON_MMF1R                                       (0x94)
+#define U300_SYSCON_MMF1R_MASK                                  (0x00FF)
+#define U300_SYSCON_MMF1R_FREQ_1_HIGH_MASK                      (0x00F0)
+#define U300_SYSCON_MMF1R_FREQ_1_LOW_MASK                       (0x000F)
+/* Clock control for the MMC and MSPRO blocks 16bit (R/W) */
+#define U300_SYSCON_MMCR                                        (0x9C)
+#define U300_SYSCON_MMCR_MASK                                   (0x0003)
+#define U300_SYSCON_MMCR_MMC_FB_CLK_SEL_ENABLE                  (0x0002)
+#define U300_SYSCON_MMCR_MSPRO_FREQSEL_ENABLE                   (0x0001)
+/* SYS_0_CLK_CONTROL first clock control 16bit (R/W) */
+#define U300_SYSCON_S0CCR                                       (0x120)
+#define U300_SYSCON_S0CCR_FIELD_MASK                            (0x43FF)
+#define U300_SYSCON_S0CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S0CCR_CLOCK_REQ_MONITOR                     (0x2000)
+#define U300_SYSCON_S0CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S0CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S0CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S0CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S0CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S0CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S0CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S0CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S0CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SYS_1_CLK_CONTROL second clock control 16 bit (R/W) */
+#define U300_SYSCON_S1CCR                                       (0x124)
+#define U300_SYSCON_S1CCR_FIELD_MASK                            (0x43FF)
+#define U300_SYSCON_S1CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S1CCR_CLOCK_REQ_MONITOR                     (0x2000)
+#define U300_SYSCON_S1CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S1CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S1CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S1CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S1CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S1CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S1CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S1CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S1CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SYS_2_CLK_CONTROL third clock contol 16 bit (R/W) */
+#define U300_SYSCON_S2CCR                                       (0x128)
+#define U300_SYSCON_S2CCR_FIELD_MASK                            (0xC3FF)
+#define U300_SYSCON_S2CCR_CLK_STEAL                             (0x8000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ                             (0x4000)
+#define U300_SYSCON_S2CCR_CLOCK_REQ_MONITOR                     (0x2000)
+#define U300_SYSCON_S2CCR_CLOCK_INV                             (0x0200)
+#define U300_SYSCON_S2CCR_CLOCK_FREQ_MASK                       (0x01E0)
+#define U300_SYSCON_S2CCR_CLOCK_SELECT_MASK                     (0x001E)
+#define U300_SYSCON_S2CCR_CLOCK_ENABLE                          (0x0001)
+#define U300_SYSCON_S2CCR_SEL_MCLK                              (0x8<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_FSM_CLK                       (0xA<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_48_CLK                      (0xC<<1)
+#define U300_SYSCON_S2CCR_SEL_PLL60_60_CLK                      (0xD<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL208_CLK                    (0xE<<1)
+#define U300_SYSCON_S2CCR_SEL_ACC_PLL13_CLK                     (0x0<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_FSM_CLK                       (0x2<<1)
+#define U300_SYSCON_S2CCR_SEL_RTC_CLK                           (0x4<<1)
+#define U300_SYSCON_S2CCR_SEL_APP_PLL208_CLK                    (0x6<<1)
+/* SC_PLL_IRQ_CONTROL 16bit (R/W) */
+#define U300_SYSCON_PICR                                        (0x0130)
+#define U300_SYSCON_PICR_MASK                                   (0x00FF)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_LOW_ENABLE           (0x0080)
+#define U300_SYSCON_PICR_FORCE_PLL208_LOCK_HIGH_ENABLE          (0x0040)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_LOW_ENABLE            (0x0020)
+#define U300_SYSCON_PICR_FORCE_PLL13_LOCK_HIGH_ENABLE           (0x0010)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_UNLOCK_ENABLE            (0x0008)
+#define U300_SYSCON_PICR_IRQMASK_PLL13_LOCK_ENABLE              (0x0004)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_UNLOCK_ENABLE           (0x0002)
+#define U300_SYSCON_PICR_IRQMASK_PLL208_LOCK_ENABLE             (0x0001)
+/* SC_PLL_IRQ_STATUS 16 bit (R/-) */
+#define U300_SYSCON_PISR                                        (0x0134)
+#define U300_SYSCON_PISR_MASK                                   (0x000F)
+#define U300_SYSCON_PISR_PLL13_UNLOCK_IND                       (0x0008)
+#define U300_SYSCON_PISR_PLL13_LOCK_IND                         (0x0004)
+#define U300_SYSCON_PISR_PLL208_UNLOCK_IND                      (0x0002)
+#define U300_SYSCON_PISR_PLL208_LOCK_IND                        (0x0001)
+/* SC_PLL_IRQ_CLEAR 16 bit (-/W) */
+#define U300_SYSCON_PICLR                                       (0x0138)
+#define U300_SYSCON_PICLR_MASK                                  (0x000F)
+#define U300_SYSCON_PICLR_RWMASK                                (0x0000)
+#define U300_SYSCON_PICLR_PLL13_UNLOCK_SC                       (0x0008)
+#define U300_SYSCON_PICLR_PLL13_LOCK_SC                         (0x0004)
+#define U300_SYSCON_PICLR_PLL208_UNLOCK_SC                      (0x0002)
+#define U300_SYSCON_PICLR_PLL208_LOCK_SC                        (0x0001)
+/* Clock activity observability register 0 */
+#define U300_SYSCON_C0OAR                                       (0x140)
+#define U300_SYSCON_C0OAR_MASK                                  (0xFFFF)
+#define U300_SYSCON_C0OAR_VALUE                                 (0xFFFF)
+#define U300_SYSCON_C0OAR_BT_H_CLK                              (0x8000)
+#define U300_SYSCON_C0OAR_ASPB_P_CLK                            (0x4000)
+#define U300_SYSCON_C0OAR_APP_SEMI_H_CLK                        (0x2000)
+#define U300_SYSCON_C0OAR_APP_SEMI_CLK                          (0x1000)
+#define U300_SYSCON_C0OAR_APP_MMC_MSPRO_CLK                     (0x0800)
+#define U300_SYSCON_C0OAR_APP_I2S1_CLK                          (0x0400)
+#define U300_SYSCON_C0OAR_APP_I2S0_CLK                          (0x0200)
+#define U300_SYSCON_C0OAR_APP_CPU_CLK                           (0x0100)
+#define U300_SYSCON_C0OAR_APP_52_CLK                            (0x0080)
+#define U300_SYSCON_C0OAR_APP_208_CLK                           (0x0040)
+#define U300_SYSCON_C0OAR_APP_104_CLK                           (0x0020)
+#define U300_SYSCON_C0OAR_APEX_CLK                              (0x0010)
+#define U300_SYSCON_C0OAR_AHPB_M_H_CLK                          (0x0008)
+#define U300_SYSCON_C0OAR_AHB_CLK                               (0x0004)
+#define U300_SYSCON_C0OAR_AFPB_P_CLK                            (0x0002)
+#define U300_SYSCON_C0OAR_AAIF_CLK                              (0x0001)
+/* Clock activity observability register 1 */
+#define U300_SYSCON_C1OAR                                       (0x144)
+#define U300_SYSCON_C1OAR_MASK                                  (0x3FFE)
+#define U300_SYSCON_C1OAR_VALUE                                 (0x3FFE)
+#define U300_SYSCON_C1OAR_NFIF_F_CLK                            (0x2000)
+#define U300_SYSCON_C1OAR_MSPRO_CLK                             (0x1000)
+#define U300_SYSCON_C1OAR_MMC_P_CLK                             (0x0800)
+#define U300_SYSCON_C1OAR_MMC_CLK                               (0x0400)
+#define U300_SYSCON_C1OAR_KP_P_CLK                              (0x0200)
+#define U300_SYSCON_C1OAR_I2C1_P_CLK                            (0x0100)
+#define U300_SYSCON_C1OAR_I2C0_P_CLK                            (0x0080)
+#define U300_SYSCON_C1OAR_GPIO_CLK                              (0x0040)
+#define U300_SYSCON_C1OAR_EMIF_MPMC_CLK                         (0x0020)
+#define U300_SYSCON_C1OAR_EMIF_H_CLK                            (0x0010)
+#define U300_SYSCON_C1OAR_EVHIST_CLK                            (0x0008)
+#define U300_SYSCON_C1OAR_PPM_CLK                               (0x0004)
+#define U300_SYSCON_C1OAR_DMA_CLK                               (0x0002)
+/* Clock activity observability register 2 */
+#define U300_SYSCON_C2OAR                                       (0x148)
+#define U300_SYSCON_C2OAR_MASK                                  (0x0FFF)
+#define U300_SYSCON_C2OAR_VALUE                                 (0x0FFF)
+#define U300_SYSCON_C2OAR_XGAM_CDI_CLK                          (0x0800)
+#define U300_SYSCON_C2OAR_XGAM_CLK                              (0x0400)
+#define U300_SYSCON_C2OAR_VC_H_CLK                              (0x0200)
+#define U300_SYSCON_C2OAR_VC_CLK                                (0x0100)
+#define U300_SYSCON_C2OAR_UA_P_CLK                              (0x0080)
+#define U300_SYSCON_C2OAR_TMR1_CLK                              (0x0040)
+#define U300_SYSCON_C2OAR_TMR0_CLK                              (0x0020)
+#define U300_SYSCON_C2OAR_SPI_P_CLK                             (0x0010)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CORE_CLK                     (0x0008)
+#define U300_SYSCON_C2OAR_PCM_I2S1_CLK                          (0x0004)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CORE_CLK                     (0x0002)
+#define U300_SYSCON_C2OAR_PCM_I2S0_CLK                          (0x0001)
+
 
 /*
  * The clocking hierarchy currently looks like this.
@@ -386,6 +728,213 @@ syscon_clk_register(struct device *dev, const char *name,
         return clk;
 }
 
+#define U300_CLK_TYPE_SLOW 0
+#define U300_CLK_TYPE_FAST 1
+#define U300_CLK_TYPE_REST 2
+
+/**
+ * struct u300_clock - defines the bits and pieces for a certain clock
+ * @type: the clock type, slow fast or rest
+ * @id: the bit in the slow/fast/rest register for this clock
+ * @hw_ctrld: whether the clock is hardware controlled
+ * @clk_val: a value to poke in the one-write enable/disable registers
+ */
+struct u300_clock {
+        u8 type;
+        u8 id;
+        bool hw_ctrld;
+        u16 clk_val;
+};
+
+struct u300_clock const __initconst u300_clk_lookup[] = {
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 3,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_CPU_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 4,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_DMAC_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 5,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_EMIF_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 6,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_NANDIF_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 8,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_XGAM_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 9,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_SEMI_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 10,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_REST,
+                .id = 12,
+                .hw_ctrld = false,
+                /* INTCON: cannot be enabled, just taken out of reset */
+                .clk_val = 0xFFFFU,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 0,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 1,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_I2C0_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 2,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_I2C1_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 5,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_MMC_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_FAST,
+                .id = 6,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_SPI_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 0,
+                .hw_ctrld = true,
+                .clk_val = U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 1,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_UART_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 4,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_GPIO_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 6,
+                .hw_ctrld = true,
+                /* No clock enable register bit */
+                .clk_val = 0xFFFFU,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 7,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_APP_TMR_CLK_EN,
+        },
+        {
+                .type = U300_CLK_TYPE_SLOW,
+                .id = 8,
+                .hw_ctrld = false,
+                .clk_val = U300_SYSCON_SBCER_ACC_TMR_CLK_EN,
+        },
+};
+
+static void __init of_u300_syscon_clk_init(struct device_node *np)
+{
+        struct clk *clk = ERR_PTR(-EINVAL);
+        const char *clk_name = np->name;
+        const char *parent_name;
+        void __iomem *res_reg;
+        void __iomem *en_reg;
+        u32 clk_type;
+        u32 clk_id;
+        int i;
+
+        if (of_property_read_u32(np, "clock-type", &clk_type)) {
+                pr_err("%s: syscon clock \"%s\" missing clock-type property\n",
+                       __func__, clk_name);
+                return;
+        }
+        if (of_property_read_u32(np, "clock-id", &clk_id)) {
+                pr_err("%s: syscon clock \"%s\" missing clock-id property\n",
+                       __func__, clk_name);
+                return;
+        }
+        parent_name = of_clk_get_parent_name(np, 0);
+
+        switch (clk_type) {
+        case U300_CLK_TYPE_SLOW:
+                res_reg = syscon_vbase + U300_SYSCON_RSR;
+                en_reg = syscon_vbase + U300_SYSCON_CESR;
+                break;
+        case U300_CLK_TYPE_FAST:
+                res_reg = syscon_vbase + U300_SYSCON_RFR;
+                en_reg = syscon_vbase + U300_SYSCON_CEFR;
+                break;
+        case U300_CLK_TYPE_REST:
+                res_reg = syscon_vbase + U300_SYSCON_RRR;
+                en_reg = syscon_vbase + U300_SYSCON_CERR;
+                break;
+        default:
+                pr_err("unknown clock type %x specified\n", clk_type);
+                return;
+        }
+
+        for (i = 0; i < ARRAY_SIZE(u300_clk_lookup); i++) {
+                const struct u300_clock *u3clk = &u300_clk_lookup[i];
+
+                if (u3clk->type == clk_type && u3clk->id == clk_id)
+                        clk = syscon_clk_register(NULL,
+                                                  clk_name, parent_name,
+                                                  0, u3clk->hw_ctrld,
+                                                  res_reg, u3clk->id,
+                                                  en_reg, u3clk->id,
+                                                  u3clk->clk_val);
+        }
+
+        if (!IS_ERR(clk)) {
+                of_clk_add_provider(np, of_clk_src_simple_get, clk);
+
+                /*
+                 * Some few system clocks - device tree does not
+                 * represent clocks without a corresponding device node.
+                 * for now we add these three clocks here.
+                 */
+                if (clk_type == U300_CLK_TYPE_REST && clk_id == 5)
+                        clk_register_clkdev(clk, NULL, "pl172");
+                if (clk_type == U300_CLK_TYPE_REST && clk_id == 9)
+                        clk_register_clkdev(clk, NULL, "semi");
+                if (clk_type == U300_CLK_TYPE_REST && clk_id == 12)
+                        clk_register_clkdev(clk, NULL, "intcon");
+        }
+}
+
 /**
  * struct clk_mclk - U300 MCLK clock (MMC/SD clock)
  * @hw: corresponding clock hardware entry
@@ -590,10 +1139,41 @@ mclk_clk_register(struct device *dev, const char *name,
         return clk;
 }
 
+static void __init of_u300_syscon_mclk_init(struct device_node *np)
+{
+        struct clk *clk = ERR_PTR(-EINVAL);
+        const char *clk_name = np->name;
+        const char *parent_name;
+
+        parent_name = of_clk_get_parent_name(np, 0);
+        clk = mclk_clk_register(NULL, clk_name, parent_name, false);
+        if (!IS_ERR(clk))
+                of_clk_add_provider(np, of_clk_src_simple_get, clk);
+}
+
+static const __initconst struct of_device_id u300_clk_match[] = {
+        {
+                .compatible = "fixed-clock",
+                .data = of_fixed_clk_setup,
+        },
+        {
+                .compatible = "fixed-factor-clock",
+                .data = of_fixed_factor_clk_setup,
+        },
+        {
+                .compatible = "stericsson,u300-syscon-clk",
+                .data = of_u300_syscon_clk_init,
+        },
+        {
+                .compatible = "stericsson,u300-syscon-mclk",
+                .data = of_u300_syscon_mclk_init,
+        },
+};
+
+
 void __init u300_clk_init(void __iomem *base)
 {
         u16 val;
-        struct clk *clk;
 
         syscon_vbase = base;
 
@@ -610,137 +1190,5 @@ void __init u300_clk_init(void __iomem *base)
         val |= U300_SYSCON_PMCR_PWR_MGNT_ENABLE;
         writew(val, syscon_vbase + U300_SYSCON_PMCR);
 
-        /* These are always available (RTC and PLL13) */
-        clk = clk_register_fixed_rate(NULL, "app_32_clk", NULL,
-                                      CLK_IS_ROOT, 32768);
-        /* The watchdog sits directly on the 32 kHz clock */
-        clk_register_clkdev(clk, NULL, "coh901327_wdog");
-        clk = clk_register_fixed_rate(NULL, "pll13", NULL,
-                                      CLK_IS_ROOT, 13000000);
-
-        /* These derive from PLL208 */
-        clk = clk_register_fixed_rate(NULL, "pll208", NULL,
-                                      CLK_IS_ROOT, 208000000);
-        clk = clk_register_fixed_factor(NULL, "app_208_clk", "pll208",
-                                        0, 1, 1);
-        clk = clk_register_fixed_factor(NULL, "app_104_clk", "pll208",
-                                        0, 1, 2);
-        clk = clk_register_fixed_factor(NULL, "app_52_clk", "pll208",
-                                        0, 1, 4);
-        /* The 52 MHz is divided down to 26 MHz */
-        clk = clk_register_fixed_factor(NULL, "app_26_clk", "app_52_clk",
-                                        0, 1, 2);
-
-        /* Directly on the AMBA interconnect */
-        clk = syscon_clk_register(NULL, "cpu_clk", "app_208_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RRR, 3,
-                                  syscon_vbase + U300_SYSCON_CERR, 3,
-                                  U300_SYSCON_SBCER_CPU_CLK_EN);
-        clk = syscon_clk_register(NULL, "dmac_clk", "app_52_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RRR, 4,
-                                  syscon_vbase + U300_SYSCON_CERR, 4,
-                                  U300_SYSCON_SBCER_DMAC_CLK_EN);
-        clk_register_clkdev(clk, NULL, "dma");
-        clk = syscon_clk_register(NULL, "fsmc_clk", "app_52_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RRR, 6,
-                                  syscon_vbase + U300_SYSCON_CERR, 6,
-                                  U300_SYSCON_SBCER_NANDIF_CLK_EN);
-        clk_register_clkdev(clk, NULL, "fsmc-nand");
-        clk = syscon_clk_register(NULL, "xgam_clk", "app_52_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RRR, 8,
-                                  syscon_vbase + U300_SYSCON_CERR, 8,
-                                  U300_SYSCON_SBCER_XGAM_CLK_EN);
-        clk_register_clkdev(clk, NULL, "xgam");
-        clk = syscon_clk_register(NULL, "semi_clk", "app_104_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RRR, 9,
-                                  syscon_vbase + U300_SYSCON_CERR, 9,
-                                  U300_SYSCON_SBCER_SEMI_CLK_EN);
-        clk_register_clkdev(clk, NULL, "semi");
-
-        /* AHB bridge clocks */
-        clk = syscon_clk_register(NULL, "ahb_subsys_clk", "app_52_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RRR, 10,
-                                  syscon_vbase + U300_SYSCON_CERR, 10,
-                                  U300_SYSCON_SBCER_AHB_SUBSYS_BRIDGE_CLK_EN);
-        clk = syscon_clk_register(NULL, "intcon_clk", "ahb_subsys_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RRR, 12,
-                                  syscon_vbase + U300_SYSCON_CERR, 12,
-                                  /* Cannot be enabled, just taken out of reset */
-                                  0xFFFFU);
-        clk_register_clkdev(clk, NULL, "intcon");
-        clk = syscon_clk_register(NULL, "emif_clk", "ahb_subsys_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RRR, 5,
-                                  syscon_vbase + U300_SYSCON_CERR, 5,
-                                  U300_SYSCON_SBCER_EMIF_CLK_EN);
-        clk_register_clkdev(clk, NULL, "pl172");
-
-        /* FAST bridge clocks */
-        clk = syscon_clk_register(NULL, "fast_clk", "app_26_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RFR, 0,
-                                  syscon_vbase + U300_SYSCON_CEFR, 0,
-                                  U300_SYSCON_SBCER_FAST_BRIDGE_CLK_EN);
-        clk = syscon_clk_register(NULL, "i2c0_p_clk", "fast_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RFR, 1,
-                                  syscon_vbase + U300_SYSCON_CEFR, 1,
-                                  U300_SYSCON_SBCER_I2C0_CLK_EN);
-        clk_register_clkdev(clk, NULL, "stu300.0");
-        clk = syscon_clk_register(NULL, "i2c1_p_clk", "fast_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RFR, 2,
-                                  syscon_vbase + U300_SYSCON_CEFR, 2,
-                                  U300_SYSCON_SBCER_I2C1_CLK_EN);
-        clk_register_clkdev(clk, NULL, "stu300.1");
-        clk = syscon_clk_register(NULL, "mmc_p_clk", "fast_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RFR, 5,
-                                  syscon_vbase + U300_SYSCON_CEFR, 5,
-                                  U300_SYSCON_SBCER_MMC_CLK_EN);
-        clk_register_clkdev(clk, "apb_pclk", "mmci");
-        clk = syscon_clk_register(NULL, "spi_p_clk", "fast_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RFR, 6,
-                                  syscon_vbase + U300_SYSCON_CEFR, 6,
-                                  U300_SYSCON_SBCER_SPI_CLK_EN);
-        /* The SPI has no external clock for the outward bus, uses the pclk */
-        clk_register_clkdev(clk, NULL, "pl022");
-        clk_register_clkdev(clk, "apb_pclk", "pl022");
-
-        /* SLOW bridge clocks */
-        clk = syscon_clk_register(NULL, "slow_clk", "pll13", 0, true,
-                                  syscon_vbase + U300_SYSCON_RSR, 0,
-                                  syscon_vbase + U300_SYSCON_CESR, 0,
-                                  U300_SYSCON_SBCER_SLOW_BRIDGE_CLK_EN);
-        clk = syscon_clk_register(NULL, "uart0_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 1,
-                                  syscon_vbase + U300_SYSCON_CESR, 1,
-                                  U300_SYSCON_SBCER_UART_CLK_EN);
-        /* Same clock is used for APB and outward bus */
-        clk_register_clkdev(clk, NULL, "uart0");
-        clk_register_clkdev(clk, "apb_pclk", "uart0");
-        clk = syscon_clk_register(NULL, "gpio_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 4,
-                                  syscon_vbase + U300_SYSCON_CESR, 4,
-                                  U300_SYSCON_SBCER_GPIO_CLK_EN);
-        clk_register_clkdev(clk, NULL, "u300-gpio");
-        clk = syscon_clk_register(NULL, "keypad_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 5,
-                                  syscon_vbase + U300_SYSCON_CESR, 6,
-                                  U300_SYSCON_SBCER_KEYPAD_CLK_EN);
-        clk_register_clkdev(clk, NULL, "coh901461-keypad");
-        clk = syscon_clk_register(NULL, "rtc_clk", "slow_clk", 0, true,
-                                  syscon_vbase + U300_SYSCON_RSR, 6,
-                                  /* No clock enable register bit */
-                                  NULL, 0, 0xFFFFU);
-        clk_register_clkdev(clk, NULL, "rtc-coh901331");
-        clk = syscon_clk_register(NULL, "app_tmr_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 7,
-                                  syscon_vbase + U300_SYSCON_CESR, 7,
-                                  U300_SYSCON_SBCER_APP_TMR_CLK_EN);
-        clk_register_clkdev(clk, NULL, "apptimer");
-        clk = syscon_clk_register(NULL, "acc_tmr_clk", "slow_clk", 0, false,
-                                  syscon_vbase + U300_SYSCON_RSR, 8,
-                                  syscon_vbase + U300_SYSCON_CESR, 8,
-                                  U300_SYSCON_SBCER_ACC_TMR_CLK_EN);
-        clk_register_clkdev(clk, NULL, "timer");
-
-        /* Then this special MMC/SD clock */
-        clk = mclk_clk_register(NULL, "mmc_clk", "mmc_p_clk", false);
-        clk_register_clkdev(clk, NULL, "mmci");
+        of_clk_init(u300_clk_match);
 }
diff --git a/drivers/clk/clk-vt8500.c b/drivers/clk/clk-vt8500.c
index debf688afa8e..553ac35bcc91 100644
--- a/drivers/clk/clk-vt8500.c
+++ b/drivers/clk/clk-vt8500.c
@@ -183,7 +183,7 @@ static int vt8500_dclk_set_rate(struct clk_hw *hw, unsigned long rate,
         writel(divisor, cdev->div_reg);
         vt8500_pmc_wait_busy();
 
-        spin_lock_irqsave(cdev->lock, flags);
+        spin_unlock_irqrestore(cdev->lock, flags);
 
         return 0;
 }
diff --git a/drivers/clk/clk-zynq.c b/drivers/clk/clk-zynq.c
deleted file mode 100644
index 32062977f453..000000000000
--- a/drivers/clk/clk-zynq.c
+++ /dev/null
@@ -1,378 +0,0 @@
-/*
- * Copyright (c) 2012 National Instruments
- *
- * Josh Cartwright <josh.cartwright@ni.com>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms and conditions of the GNU General Public License,
- * version 2, as published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program.  If not, see <http://www.gnu.org/licenses/>.
- */
-#include <linux/io.h>
-#include <linux/of.h>
-#include <linux/slab.h>
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/zynq.h>
-
-static void __iomem *slcr_base;
-
-struct zynq_pll_clk {
-        struct clk_hw   hw;
-        void __iomem    *pll_ctrl;
-        void __iomem    *pll_cfg;
-};
-
-#define to_zynq_pll_clk(hw)     container_of(hw, struct zynq_pll_clk, hw)
-
-#define CTRL_PLL_FDIV(x)        ((x) >> 12)
-
-static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
-                                          unsigned long parent_rate)
-{
-        struct zynq_pll_clk *pll = to_zynq_pll_clk(hw);
-        return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl));
-}
-
-static const struct clk_ops zynq_pll_clk_ops = {
-        .recalc_rate    = zynq_pll_recalc_rate,
-};
-
-static void __init zynq_pll_clk_setup(struct device_node *np)
-{
-        struct clk_init_data init;
-        struct zynq_pll_clk *pll;
-        const char *parent_name;
-        struct clk *clk;
-        u32 regs[2];
-        int ret;
-
-        ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs));
-        if (WARN_ON(ret))
-                return;
-
-        pll = kzalloc(sizeof(*pll), GFP_KERNEL);
-        if (WARN_ON(!pll))
-                return;
-
-        pll->pll_ctrl = slcr_base + regs[0];
-        pll->pll_cfg  = slcr_base + regs[1];
-
-        of_property_read_string(np, "clock-output-names", &init.name);
-
-        init.ops = &zynq_pll_clk_ops;
-        parent_name = of_clk_get_parent_name(np, 0);
-        init.parent_names = &parent_name;
-        init.num_parents = 1;
-
-        pll->hw.init = &init;
-
-        clk = clk_register(NULL, &pll->hw);
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        ret = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-        if (WARN_ON(ret))
-                return;
-}
-CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup);
-
-struct zynq_periph_clk {
-        struct clk_hw           hw;
-        struct clk_onecell_data onecell_data;
-        struct clk              *gates[2];
-        void __iomem            *clk_ctrl;
-        spinlock_t              clkact_lock;
-};
-
-#define to_zynq_periph_clk(hw)  container_of(hw, struct zynq_periph_clk, hw)
-
-static const u8 periph_clk_parent_map[] = {
-        0, 0, 1, 2
-};
-#define PERIPH_CLK_CTRL_SRC(x)  (periph_clk_parent_map[((x) & 0x30) >> 4])
-#define PERIPH_CLK_CTRL_DIV(x)  (((x) & 0x3F00) >> 8)
-
-static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw,
-                                             unsigned long parent_rate)
-{
-        struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
-        return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl));
-}
-
-static u8 zynq_periph_get_parent(struct clk_hw *hw)
-{
-        struct zynq_periph_clk *periph = to_zynq_periph_clk(hw);
-        return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl));
-}
-
-static const struct clk_ops zynq_periph_clk_ops = {
-        .recalc_rate    = zynq_periph_recalc_rate,
-        .get_parent     = zynq_periph_get_parent,
-};
-
-static void __init zynq_periph_clk_setup(struct device_node *np)
-{
-        struct zynq_periph_clk *periph;
-        const char *parent_names[3];
-        struct clk_init_data init;
-        int clk_num = 0, err;
-        const char *name;
-        struct clk *clk;
-        u32 reg;
-        int i;
-
-        err = of_property_read_u32(np, "reg", &reg);
-        if (WARN_ON(err))
-                return;
-
-        periph = kzalloc(sizeof(*periph), GFP_KERNEL);
-        if (WARN_ON(!periph))
-                return;
-
-        periph->clk_ctrl = slcr_base + reg;
-        spin_lock_init(&periph->clkact_lock);
-
-        init.name = np->name;
-        init.ops = &zynq_periph_clk_ops;
-        for (i = 0; i < ARRAY_SIZE(parent_names); i++)
-                parent_names[i] = of_clk_get_parent_name(np, i);
-        init.parent_names = parent_names;
-        init.num_parents = ARRAY_SIZE(parent_names);
-
-        periph->hw.init = &init;
-
-        clk = clk_register(NULL, &periph->hw);
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-        if (WARN_ON(err))
-                return;
-
-        err = of_property_read_string_index(np, "clock-output-names", 0,
-                                            &name);
-        if (WARN_ON(err))
-                return;
-
-        periph->gates[0] = clk_register_gate(NULL, name, np->name, 0,
-                                             periph->clk_ctrl, 0, 0,
-                                             &periph->clkact_lock);
-        if (WARN_ON(IS_ERR(periph->gates[0])))
-                return;
-        clk_num++;
-
-        /* some periph clks have 2 downstream gates */
-        err = of_property_read_string_index(np, "clock-output-names", 1,
-                                            &name);
-        if (err != -ENODATA) {
-                periph->gates[1] = clk_register_gate(NULL, name, np->name, 0,
-                                                     periph->clk_ctrl, 1, 0,
-                                                     &periph->clkact_lock);
-                if (WARN_ON(IS_ERR(periph->gates[1])))
-                        return;
-                clk_num++;
-        }
-
-        periph->onecell_data.clks = periph->gates;
-        periph->onecell_data.clk_num = clk_num;
-
-        err = of_clk_add_provider(np, of_clk_src_onecell_get,
-                                  &periph->onecell_data);
-        if (WARN_ON(err))
-                return;
-}
-CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup);
-
-/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
- * derivative rates depend on CLK_621_TRUE
- */
-
-struct zynq_cpu_clk {
-        struct clk_hw           hw;
-        struct clk_onecell_data onecell_data;
-        struct clk              *subclks[4];
-        void __iomem            *clk_ctrl;
-        spinlock_t              clkact_lock;
-};
-
-#define to_zynq_cpu_clk(hw)     container_of(hw, struct zynq_cpu_clk, hw)
-
-static const u8 zynq_cpu_clk_parent_map[] = {
-        1, 1, 2, 0
-};
-#define CPU_CLK_SRCSEL(x)       (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)])
-#define CPU_CLK_CTRL_DIV(x)     (((x) & 0x3F00) >> 8)
-
-static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw)
-{
-        struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
-        return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl));
-}
-
-static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw,
-                                              unsigned long parent_rate)
-{
-        struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw);
-        return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl));
-}
-
-static const struct clk_ops zynq_cpu_clk_ops = {
-        .get_parent     = zynq_cpu_clk_get_parent,
-        .recalc_rate    = zynq_cpu_clk_recalc_rate,
-};
-
-struct zynq_cpu_subclk {
-        struct clk_hw   hw;
-        void __iomem    *clk_621;
-        enum {
-                CPU_SUBCLK_6X4X,
-                CPU_SUBCLK_3X2X,
-                CPU_SUBCLK_2X,
-                CPU_SUBCLK_1X,
-        } which;
-};
-
-#define CLK_621_TRUE(x) ((x) & 1)
-
-#define to_zynq_cpu_subclk(hw)  container_of(hw, struct zynq_cpu_subclk, hw);
-
-static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw,
-                                                 unsigned long parent_rate)
-{
-        unsigned long uninitialized_var(rate);
-        struct zynq_cpu_subclk *subclk;
-        bool is_621;
-
-        subclk = to_zynq_cpu_subclk(hw)
-        is_621 = CLK_621_TRUE(ioread32(subclk->clk_621));
-
-        switch (subclk->which) {
-        case CPU_SUBCLK_6X4X:
-                rate = parent_rate;
-                break;
-        case CPU_SUBCLK_3X2X:
-                rate = parent_rate / 2;
-                break;
-        case CPU_SUBCLK_2X:
-                rate = parent_rate / (is_621 ? 3 : 2);
-                break;
-        case CPU_SUBCLK_1X:
-                rate = parent_rate / (is_621 ? 6 : 4);
-                break;
-        };
-
-        return rate;
-}
-
-static const struct clk_ops zynq_cpu_subclk_ops = {
-        .recalc_rate    = zynq_cpu_subclk_recalc_rate,
-};
-
-static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which,
-                                         void __iomem *clk_621)
-{
-        struct zynq_cpu_subclk *subclk;
-        struct clk_init_data init;
-        struct clk *clk;
-        int err;
-
-        err = of_property_read_string_index(np, "clock-output-names",
-                                            which, &init.name);
-        if (WARN_ON(err))
-                goto err_read_output_name;
-
-        subclk = kzalloc(sizeof(*subclk), GFP_KERNEL);
-        if (!subclk)
-                goto err_subclk_alloc;
-
-        subclk->clk_621 = clk_621;
-        subclk->which = which;
-
-        init.ops = &zynq_cpu_subclk_ops;
-        init.parent_names = &np->name;
-        init.num_parents = 1;
-
-        subclk->hw.init = &init;
-
-        clk = clk_register(NULL, &subclk->hw);
-        if (WARN_ON(IS_ERR(clk)))
-                goto err_clk_register;
-
-        return clk;
-
-err_clk_register:
-        kfree(subclk);
-err_subclk_alloc:
-err_read_output_name:
-        return ERR_PTR(-EINVAL);
-}
-
-static void __init zynq_cpu_clk_setup(struct device_node *np)
-{
-        struct zynq_cpu_clk *cpuclk;
-        const char *parent_names[3];
-        struct clk_init_data init;
-        void __iomem *clk_621;
-        struct clk *clk;
-        u32 reg[2];
-        int err;
-        int i;
-
-        err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg));
-        if (WARN_ON(err))
-                return;
-
-        cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL);
-        if (WARN_ON(!cpuclk))
-                return;
-
-        cpuclk->clk_ctrl = slcr_base + reg[0];
-        clk_621 = slcr_base + reg[1];
-        spin_lock_init(&cpuclk->clkact_lock);
-
-        init.name = np->name;
-        init.ops = &zynq_cpu_clk_ops;
-        for (i = 0; i < ARRAY_SIZE(parent_names); i++)
-                parent_names[i] = of_clk_get_parent_name(np, i);
-        init.parent_names = parent_names;
-        init.num_parents = ARRAY_SIZE(parent_names);
-
-        cpuclk->hw.init = &init;
-
-        clk = clk_register(NULL, &cpuclk->hw);
-        if (WARN_ON(IS_ERR(clk)))
-                return;
-
-        err = of_clk_add_provider(np, of_clk_src_simple_get, clk);
-        if (WARN_ON(err))
-                return;
-
-        for (i = 0; i < 4; i++) {
-                cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621);
-                if (WARN_ON(IS_ERR(cpuclk->subclks[i])))
-                        return;
-        }
-
-        cpuclk->onecell_data.clks = cpuclk->subclks;
-        cpuclk->onecell_data.clk_num = i;
-
-        err = of_clk_add_provider(np, of_clk_src_onecell_get,
-                                  &cpuclk->onecell_data);
-        if (WARN_ON(err))
-                return;
-}
-CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup);
-
-void __init xilinx_zynq_clocks_init(void __iomem *slcr)
-{
-        slcr_base = slcr;
-        of_clk_init(NULL);
-}
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 57323fd15ec9..0b0f3e729cf7 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -1,8 +1,23 @@
-config MVEBU_CLK_CORE
-       bool
+config MVEBU_CLK_COMMON
+        bool
 
 config MVEBU_CLK_CPU
-       bool
+        bool
 
-config MVEBU_CLK_GATING
-       bool
+config ARMADA_370_CLK
+        bool
+        select MVEBU_CLK_COMMON
+        select MVEBU_CLK_CPU
+
+config ARMADA_XP_CLK
+        bool
+        select MVEBU_CLK_COMMON
+        select MVEBU_CLK_CPU
+
+config DOVE_CLK
+        bool
+        select MVEBU_CLK_COMMON
+
+config KIRKWOOD_CLK
+        bool
+        select MVEBU_CLK_COMMON
diff --git a/drivers/clk/mvebu/Makefile b/drivers/clk/mvebu/Makefile
index 58df3dc49363..1c7e70c63fb2 100644
--- a/drivers/clk/mvebu/Makefile
+++ b/drivers/clk/mvebu/Makefile
@@ -1,3 +1,7 @@
-obj-$(CONFIG_MVEBU_CLK_CORE)    += clk.o clk-core.o
+obj-$(CONFIG_MVEBU_CLK_COMMON)  += common.o
 obj-$(CONFIG_MVEBU_CLK_CPU)     += clk-cpu.o
-obj-$(CONFIG_MVEBU_CLK_GATING)  += clk-gating-ctrl.o
+
+obj-$(CONFIG_ARMADA_370_CLK)    += armada-370.o
+obj-$(CONFIG_ARMADA_XP_CLK)     += armada-xp.o
+obj-$(CONFIG_DOVE_CLK)          += dove.o
+obj-$(CONFIG_KIRKWOOD_CLK)      += kirkwood.o
diff --git a/drivers/clk/mvebu/armada-370.c b/drivers/clk/mvebu/armada-370.c
new file mode 100644
index 000000000000..079960e7c304
--- /dev/null
+++ b/drivers/clk/mvebu/armada-370.c
@@ -0,0 +1,176 @@
+/*
+ * Marvell Armada 370 SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+#define SARL                            0       /* Low part [0:31] */
+#define  SARL_A370_PCLK_FREQ_OPT        11
+#define  SARL_A370_PCLK_FREQ_OPT_MASK   0xF
+#define  SARL_A370_FAB_FREQ_OPT         15
+#define  SARL_A370_FAB_FREQ_OPT_MASK    0x1F
+#define  SARL_A370_TCLK_FREQ_OPT        20
+#define  SARL_A370_TCLK_FREQ_OPT_MASK   0x1
+
+enum { A370_CPU_TO_NBCLK, A370_CPU_TO_HCLK, A370_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst a370_coreclk_ratios[] = {
+        { .id = A370_CPU_TO_NBCLK, .name = "nbclk" },
+        { .id = A370_CPU_TO_HCLK, .name = "hclk" },
+        { .id = A370_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+static const u32 __initconst a370_tclk_freqs[] = {
+        16600000,
+        20000000,
+};
+
+static u32 __init a370_get_tclk_freq(void __iomem *sar)
+{
+        u8 tclk_freq_select = 0;
+
+        tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
+                            SARL_A370_TCLK_FREQ_OPT_MASK);
+        return a370_tclk_freqs[tclk_freq_select];
+}
+
+static const u32 __initconst a370_cpu_freqs[] = {
+        400000000,
+        533000000,
+        667000000,
+        800000000,
+        1000000000,
+        1067000000,
+        1200000000,
+};
+
+static u32 __init a370_get_cpu_freq(void __iomem *sar)
+{
+        u32 cpu_freq;
+        u8 cpu_freq_select = 0;
+
+        cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
+                           SARL_A370_PCLK_FREQ_OPT_MASK);
+        if (cpu_freq_select >= ARRAY_SIZE(a370_cpu_freqs)) {
+                pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
+                cpu_freq = 0;
+        } else
+                cpu_freq = a370_cpu_freqs[cpu_freq_select];
+
+        return cpu_freq;
+}
+
+static const int __initconst a370_nbclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 2}, {2, 2},
+        {1, 2}, {1, 2}, {1, 1}, {2, 3},
+        {0, 1}, {1, 2}, {2, 4}, {0, 1},
+        {1, 2}, {0, 1}, {0, 1}, {2, 2},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {2, 3}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_hclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 6}, {2, 3},
+        {1, 3}, {1, 4}, {1, 2}, {2, 6},
+        {0, 1}, {1, 6}, {2, 10}, {0, 1},
+        {1, 4}, {0, 1}, {0, 1}, {2, 5},
+        {0, 1}, {0, 1}, {0, 1}, {1, 2},
+        {2, 6}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst a370_dramclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 3}, {2, 3},
+        {1, 3}, {1, 2}, {1, 2}, {2, 6},
+        {0, 1}, {1, 3}, {2, 5}, {0, 1},
+        {1, 4}, {0, 1}, {0, 1}, {2, 5},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {2, 3}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init a370_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
+                SARL_A370_FAB_FREQ_OPT_MASK);
+
+        switch (id) {
+        case A370_CPU_TO_NBCLK:
+                *mult = a370_nbclk_ratios[opt][0];
+                *div = a370_nbclk_ratios[opt][1];
+                break;
+        case A370_CPU_TO_HCLK:
+                *mult = a370_hclk_ratios[opt][0];
+                *div = a370_hclk_ratios[opt][1];
+                break;
+        case A370_CPU_TO_DRAMCLK:
+                *mult = a370_dramclk_ratios[opt][0];
+                *div = a370_dramclk_ratios[opt][1];
+                break;
+        }
+}
+
+static const struct coreclk_soc_desc a370_coreclks = {
+        .get_tclk_freq = a370_get_tclk_freq,
+        .get_cpu_freq = a370_get_cpu_freq,
+        .get_clk_ratio = a370_get_clk_ratio,
+        .ratios = a370_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(a370_coreclk_ratios),
+};
+
+static void __init a370_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &a370_coreclks);
+}
+CLK_OF_DECLARE(a370_core_clk, "marvell,armada-370-core-clock",
+               a370_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst a370_gating_desc[] = {
+        { "audio", NULL, 0, 0 },
+        { "pex0_en", NULL, 1, 0 },
+        { "pex1_en", NULL,  2, 0 },
+        { "ge1", NULL, 3, 0 },
+        { "ge0", NULL, 4, 0 },
+        { "pex0", "pex0_en", 5, 0 },
+        { "pex1", "pex1_en", 9, 0 },
+        { "sata0", NULL, 15, 0 },
+        { "sdio", NULL, 17, 0 },
+        { "tdm", NULL, 25, 0 },
+        { "ddr", NULL, 28, CLK_IGNORE_UNUSED },
+        { "sata1", NULL, 30, 0 },
+        { }
+};
+
+static void __init a370_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, a370_gating_desc);
+}
+CLK_OF_DECLARE(a370_clk_gating, "marvell,armada-370-gating-clock",
+               a370_clk_gating_init);
diff --git a/drivers/clk/mvebu/armada-xp.c b/drivers/clk/mvebu/armada-xp.c
new file mode 100644
index 000000000000..13b62ceb3407
--- /dev/null
+++ b/drivers/clk/mvebu/armada-xp.c
@@ -0,0 +1,210 @@
+/*
+ * Marvell Armada XP SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Armada XP Sample At Reset is a 64 bit bitfiled split in two
+ * register of 32 bits
+ */
+
+#define SARL                            0       /* Low part [0:31] */
+#define  SARL_AXP_PCLK_FREQ_OPT         21
+#define  SARL_AXP_PCLK_FREQ_OPT_MASK    0x7
+#define  SARL_AXP_FAB_FREQ_OPT          24
+#define  SARL_AXP_FAB_FREQ_OPT_MASK     0xF
+#define SARH                            4       /* High part [32:63] */
+#define  SARH_AXP_PCLK_FREQ_OPT         (52-32)
+#define  SARH_AXP_PCLK_FREQ_OPT_MASK    0x1
+#define  SARH_AXP_PCLK_FREQ_OPT_SHIFT   3
+#define  SARH_AXP_FAB_FREQ_OPT          (51-32)
+#define  SARH_AXP_FAB_FREQ_OPT_MASK     0x1
+#define  SARH_AXP_FAB_FREQ_OPT_SHIFT    4
+
+enum { AXP_CPU_TO_NBCLK, AXP_CPU_TO_HCLK, AXP_CPU_TO_DRAMCLK };
+
+static const struct coreclk_ratio __initconst axp_coreclk_ratios[] = {
+        { .id = AXP_CPU_TO_NBCLK, .name = "nbclk" },
+        { .id = AXP_CPU_TO_HCLK, .name = "hclk" },
+        { .id = AXP_CPU_TO_DRAMCLK, .name = "dramclk" },
+};
+
+/* Armada XP TCLK frequency is fixed to 250MHz */
+static u32 __init axp_get_tclk_freq(void __iomem *sar)
+{
+        return 250000000;
+}
+
+static const u32 __initconst axp_cpu_freqs[] = {
+        1000000000,
+        1066000000,
+        1200000000,
+        1333000000,
+        1500000000,
+        1666000000,
+        1800000000,
+        2000000000,
+        667000000,
+        0,
+        800000000,
+        1600000000,
+};
+
+static u32 __init axp_get_cpu_freq(void __iomem *sar)
+{
+        u32 cpu_freq;
+        u8 cpu_freq_select = 0;
+
+        cpu_freq_select = ((readl(sar + SARL) >> SARL_AXP_PCLK_FREQ_OPT) &
+                           SARL_AXP_PCLK_FREQ_OPT_MASK);
+        /*
+         * The upper bit is not contiguous to the other ones and
+         * located in the high part of the SAR registers
+         */
+        cpu_freq_select |= (((readl(sar + SARH) >> SARH_AXP_PCLK_FREQ_OPT) &
+             SARH_AXP_PCLK_FREQ_OPT_MASK) << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
+        if (cpu_freq_select >= ARRAY_SIZE(axp_cpu_freqs)) {
+                pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
+                cpu_freq = 0;
+        } else
+                cpu_freq = axp_cpu_freqs[cpu_freq_select];
+
+        return cpu_freq;
+}
+
+static const int __initconst axp_nbclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 2}, {2, 2},
+        {1, 2}, {1, 2}, {1, 1}, {2, 3},
+        {0, 1}, {1, 2}, {2, 4}, {0, 1},
+        {1, 2}, {0, 1}, {0, 1}, {2, 2},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {2, 3}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_hclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 6}, {2, 3},
+        {1, 3}, {1, 4}, {1, 2}, {2, 6},
+        {0, 1}, {1, 6}, {2, 10}, {0, 1},
+        {1, 4}, {0, 1}, {0, 1}, {2, 5},
+        {0, 1}, {0, 1}, {0, 1}, {1, 2},
+        {2, 6}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static const int __initconst axp_dramclk_ratios[32][2] = {
+        {0, 1}, {1, 2}, {2, 3}, {2, 3},
+        {1, 3}, {1, 2}, {1, 2}, {2, 6},
+        {0, 1}, {1, 3}, {2, 5}, {0, 1},
+        {1, 4}, {0, 1}, {0, 1}, {2, 5},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {2, 3}, {0, 1}, {0, 1}, {0, 1},
+        {0, 1}, {0, 1}, {0, 1}, {1, 1},
+        {0, 1}, {0, 1}, {0, 1}, {0, 1},
+};
+
+static void __init axp_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        u32 opt = ((readl(sar + SARL) >> SARL_AXP_FAB_FREQ_OPT) &
+              SARL_AXP_FAB_FREQ_OPT_MASK);
+        /*
+         * The upper bit is not contiguous to the other ones and
+         * located in the high part of the SAR registers
+         */
+        opt |= (((readl(sar + SARH) >> SARH_AXP_FAB_FREQ_OPT) &
+                 SARH_AXP_FAB_FREQ_OPT_MASK) << SARH_AXP_FAB_FREQ_OPT_SHIFT);
+
+        switch (id) {
+        case AXP_CPU_TO_NBCLK:
+                *mult = axp_nbclk_ratios[opt][0];
+                *div = axp_nbclk_ratios[opt][1];
+                break;
+        case AXP_CPU_TO_HCLK:
+                *mult = axp_hclk_ratios[opt][0];
+                *div = axp_hclk_ratios[opt][1];
+                break;
+        case AXP_CPU_TO_DRAMCLK:
+                *mult = axp_dramclk_ratios[opt][0];
+                *div = axp_dramclk_ratios[opt][1];
+                break;
+        }
+}
+
+static const struct coreclk_soc_desc axp_coreclks = {
+        .get_tclk_freq = axp_get_tclk_freq,
+        .get_cpu_freq = axp_get_cpu_freq,
+        .get_clk_ratio = axp_get_clk_ratio,
+        .ratios = axp_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(axp_coreclk_ratios),
+};
+
+static void __init axp_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &axp_coreclks);
+}
+CLK_OF_DECLARE(axp_core_clk, "marvell,armada-xp-core-clock",
+               axp_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst axp_gating_desc[] = {
+        { "audio", NULL, 0, 0 },
+        { "ge3", NULL, 1, 0 },
+        { "ge2", NULL,  2, 0 },
+        { "ge1", NULL, 3, 0 },
+        { "ge0", NULL, 4, 0 },
+        { "pex00", NULL, 5, 0 },
+        { "pex01", NULL, 6, 0 },
+        { "pex02", NULL, 7, 0 },
+        { "pex03", NULL, 8, 0 },
+        { "pex10", NULL, 9, 0 },
+        { "pex11", NULL, 10, 0 },
+        { "pex12", NULL, 11, 0 },
+        { "pex13", NULL, 12, 0 },
+        { "bp", NULL, 13, 0 },
+        { "sata0lnk", NULL, 14, 0 },
+        { "sata0", "sata0lnk", 15, 0 },
+        { "lcd", NULL, 16, 0 },
+        { "sdio", NULL, 17, 0 },
+        { "usb0", NULL, 18, 0 },
+        { "usb1", NULL, 19, 0 },
+        { "usb2", NULL, 20, 0 },
+        { "xor0", NULL, 22, 0 },
+        { "crypto", NULL, 23, 0 },
+        { "tdm", NULL, 25, 0 },
+        { "pex20", NULL, 26, 0 },
+        { "pex30", NULL, 27, 0 },
+        { "xor1", NULL, 28, 0 },
+        { "sata1lnk", NULL, 29, 0 },
+        { "sata1", "sata1lnk", 30, 0 },
+        { }
+};
+
+static void __init axp_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, axp_gating_desc);
+}
+CLK_OF_DECLARE(axp_clk_gating, "marvell,armada-xp-gating-clock",
+               axp_clk_gating_init);
diff --git a/drivers/clk/mvebu/clk-core.c b/drivers/clk/mvebu/clk-core.c
deleted file mode 100644
index 0a53edbae8b8..000000000000
--- a/drivers/clk/mvebu/clk-core.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/of_address.h>
-#include <linux/io.h>
-#include <linux/of.h>
-#include "clk-core.h"
-
-struct core_ratio {
-        int id;
-        const char *name;
-};
-
-struct core_clocks {
-        u32 (*get_tclk_freq)(void __iomem *sar);
-        u32 (*get_cpu_freq)(void __iomem *sar);
-        void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
-        const struct core_ratio *ratios;
-        int num_ratios;
-};
-
-static struct clk_onecell_data clk_data;
-
-static void __init mvebu_clk_core_setup(struct device_node *np,
-                                 struct core_clocks *coreclk)
-{
-        const char *tclk_name = "tclk";
-        const char *cpuclk_name = "cpuclk";
-        void __iomem *base;
-        unsigned long rate;
-        int n;
-
-        base = of_iomap(np, 0);
-        if (WARN_ON(!base))
-                return;
-
-        /*
-         * Allocate struct for TCLK, cpu clk, and core ratio clocks
-         */
-        clk_data.clk_num = 2 + coreclk->num_ratios;
-        clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
-                                GFP_KERNEL);
-        if (WARN_ON(!clk_data.clks))
-                return;
-
-        /*
-         * Register TCLK
-         */
-        of_property_read_string_index(np, "clock-output-names", 0,
-                                      &tclk_name);
-        rate = coreclk->get_tclk_freq(base);
-        clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
-                                                   CLK_IS_ROOT, rate);
-        WARN_ON(IS_ERR(clk_data.clks[0]));
-
-        /*
-         * Register CPU clock
-         */
-        of_property_read_string_index(np, "clock-output-names", 1,
-                                      &cpuclk_name);
-        rate = coreclk->get_cpu_freq(base);
-        clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
-                                                   CLK_IS_ROOT, rate);
-        WARN_ON(IS_ERR(clk_data.clks[1]));
-
-        /*
-         * Register fixed-factor clocks derived from CPU clock
-         */
-        for (n = 0; n < coreclk->num_ratios; n++) {
-                const char *rclk_name = coreclk->ratios[n].name;
-                int mult, div;
-
-                of_property_read_string_index(np, "clock-output-names",
-                                              2+n, &rclk_name);
-                coreclk->get_clk_ratio(base, coreclk->ratios[n].id,
-                                       &mult, &div);
-                clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
-                                       cpuclk_name, 0, mult, div);
-                WARN_ON(IS_ERR(clk_data.clks[2+n]));
-        };
-
-        /*
-         * SAR register isn't needed anymore
-         */
-        iounmap(base);
-
-        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
-}
-
-#ifdef CONFIG_MACH_ARMADA_370_XP
-/*
- * Armada 370/XP Sample At Reset is a 64 bit bitfiled split in two
- * register of 32 bits
- */
-
-#define SARL                                0   /* Low part [0:31] */
-#define     SARL_AXP_PCLK_FREQ_OPT          21
-#define     SARL_AXP_PCLK_FREQ_OPT_MASK     0x7
-#define     SARL_A370_PCLK_FREQ_OPT         11
-#define     SARL_A370_PCLK_FREQ_OPT_MASK    0xF
-#define     SARL_AXP_FAB_FREQ_OPT           24
-#define     SARL_AXP_FAB_FREQ_OPT_MASK      0xF
-#define     SARL_A370_FAB_FREQ_OPT          15
-#define     SARL_A370_FAB_FREQ_OPT_MASK     0x1F
-#define     SARL_A370_TCLK_FREQ_OPT         20
-#define     SARL_A370_TCLK_FREQ_OPT_MASK    0x1
-#define SARH                                4   /* High part [32:63] */
-#define     SARH_AXP_PCLK_FREQ_OPT          (52-32)
-#define     SARH_AXP_PCLK_FREQ_OPT_MASK     0x1
-#define     SARH_AXP_PCLK_FREQ_OPT_SHIFT    3
-#define     SARH_AXP_FAB_FREQ_OPT           (51-32)
-#define     SARH_AXP_FAB_FREQ_OPT_MASK      0x1
-#define     SARH_AXP_FAB_FREQ_OPT_SHIFT     4
-
-static const u32 __initconst armada_370_tclk_frequencies[] = {
-        16600000,
-        20000000,
-};
-
-static u32 __init armada_370_get_tclk_freq(void __iomem *sar)
-{
-        u8 tclk_freq_select = 0;
-
-        tclk_freq_select = ((readl(sar) >> SARL_A370_TCLK_FREQ_OPT) &
-                            SARL_A370_TCLK_FREQ_OPT_MASK);
-        return armada_370_tclk_frequencies[tclk_freq_select];
-}
-
-static const u32 __initconst armada_370_cpu_frequencies[] = {
-        400000000,
-        533000000,
-        667000000,
-        800000000,
-        1000000000,
-        1067000000,
-        1200000000,
-};
-
-static u32 __init armada_370_get_cpu_freq(void __iomem *sar)
-{
-        u32 cpu_freq;
-        u8 cpu_freq_select = 0;
-
-        cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
-                           SARL_A370_PCLK_FREQ_OPT_MASK);
-        if (cpu_freq_select >= ARRAY_SIZE(armada_370_cpu_frequencies)) {
-                pr_err("CPU freq select unsupported %d\n", cpu_freq_select);
-                cpu_freq = 0;
-        } else
-                cpu_freq = armada_370_cpu_frequencies[cpu_freq_select];
-
-        return cpu_freq;
-}
-
-enum { A370_XP_NBCLK, A370_XP_HCLK, A370_XP_DRAMCLK };
-
-static const struct core_ratio __initconst armada_370_xp_core_ratios[] = {
-        { .id = A370_XP_NBCLK,   .name = "nbclk" },
-        { .id = A370_XP_HCLK,    .name = "hclk" },
-        { .id = A370_XP_DRAMCLK, .name = "dramclk" },
-};
-
-static const int __initconst armada_370_xp_nbclk_ratios[32][2] = {
-        {0, 1}, {1, 2}, {2, 2}, {2, 2},
-        {1, 2}, {1, 2}, {1, 1}, {2, 3},
-        {0, 1}, {1, 2}, {2, 4}, {0, 1},
-        {1, 2}, {0, 1}, {0, 1}, {2, 2},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {2, 3}, {0, 1}, {0, 1}, {0, 1},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_hclk_ratios[32][2] = {
-        {0, 1}, {1, 2}, {2, 6}, {2, 3},
-        {1, 3}, {1, 4}, {1, 2}, {2, 6},
-        {0, 1}, {1, 6}, {2, 10}, {0, 1},
-        {1, 4}, {0, 1}, {0, 1}, {2, 5},
-        {0, 1}, {0, 1}, {0, 1}, {1, 2},
-        {2, 6}, {0, 1}, {0, 1}, {0, 1},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static const int __initconst armada_370_xp_dramclk_ratios[32][2] = {
-        {0, 1}, {1, 2}, {2, 3}, {2, 3},
-        {1, 3}, {1, 2}, {1, 2}, {2, 6},
-        {0, 1}, {1, 3}, {2, 5}, {0, 1},
-        {1, 4}, {0, 1}, {0, 1}, {2, 5},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {2, 3}, {0, 1}, {0, 1}, {0, 1},
-        {0, 1}, {0, 1}, {0, 1}, {1, 1},
-        {0, 1}, {0, 1}, {0, 1}, {0, 1},
-};
-
-static void __init armada_370_xp_get_clk_ratio(u32 opt,
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        switch (id) {
-        case A370_XP_NBCLK:
-                *mult = armada_370_xp_nbclk_ratios[opt][0];
-                *div = armada_370_xp_nbclk_ratios[opt][1];
-                break;
-        case A370_XP_HCLK:
-                *mult = armada_370_xp_hclk_ratios[opt][0];
-                *div = armada_370_xp_hclk_ratios[opt][1];
-                break;
-        case A370_XP_DRAMCLK:
-                *mult = armada_370_xp_dramclk_ratios[opt][0];
-                *div = armada_370_xp_dramclk_ratios[opt][1];
-                break;
-        }
-}
-
-static void __init armada_370_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        u32 opt = ((readl(sar) >> SARL_A370_FAB_FREQ_OPT) &
-                SARL_A370_FAB_FREQ_OPT_MASK);
-
-        armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-
-static const struct core_clocks armada_370_core_clocks = {
-        .get_tclk_freq = armada_370_get_tclk_freq,
-        .get_cpu_freq = armada_370_get_cpu_freq,
-        .get_clk_ratio = armada_370_get_clk_ratio,
-        .ratios = armada_370_xp_core_ratios,
-        .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-static const u32 __initconst armada_xp_cpu_frequencies[] = {
-        1000000000,
-        1066000000,
-        1200000000,
-        1333000000,
-        1500000000,
-        1666000000,
-        1800000000,
-        2000000000,
-        667000000,
-        0,
-        800000000,
-        1600000000,
-};
-
-/* For Armada XP TCLK frequency is fix: 250MHz */
-static u32 __init armada_xp_get_tclk_freq(void __iomem *sar)
-{
-        return 250 * 1000 * 1000;
-}
-
-static u32 __init armada_xp_get_cpu_freq(void __iomem *sar)
-{
-        u32 cpu_freq;
-        u8 cpu_freq_select = 0;
-
-        cpu_freq_select = ((readl(sar) >> SARL_AXP_PCLK_FREQ_OPT) &
-                           SARL_AXP_PCLK_FREQ_OPT_MASK);
-        /*
-         * The upper bit is not contiguous to the other ones and
-         * located in the high part of the SAR registers
-         */
-        cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) &
-                             SARH_AXP_PCLK_FREQ_OPT_MASK)
-                            << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
-        if (cpu_freq_select >= ARRAY_SIZE(armada_xp_cpu_frequencies)) {
-                pr_err("CPU freq select unsupported: %d\n", cpu_freq_select);
-                cpu_freq = 0;
-        } else
-                cpu_freq = armada_xp_cpu_frequencies[cpu_freq_select];
-
-        return cpu_freq;
-}
-
-static void __init armada_xp_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-
-        u32 opt = ((readl(sar) >> SARL_AXP_FAB_FREQ_OPT) &
-              SARL_AXP_FAB_FREQ_OPT_MASK);
-        /*
-         * The upper bit is not contiguous to the other ones and
-         * located in the high part of the SAR registers
-         */
-        opt |= (((readl(sar+4) >> SARH_AXP_FAB_FREQ_OPT) &
-                SARH_AXP_FAB_FREQ_OPT_MASK)
-               << SARH_AXP_FAB_FREQ_OPT_SHIFT);
-
-        armada_370_xp_get_clk_ratio(opt, sar, id, mult, div);
-}
-
-static const struct core_clocks armada_xp_core_clocks = {
-        .get_tclk_freq = armada_xp_get_tclk_freq,
-        .get_cpu_freq = armada_xp_get_cpu_freq,
-        .get_clk_ratio = armada_xp_get_clk_ratio,
-        .ratios = armada_370_xp_core_ratios,
-        .num_ratios = ARRAY_SIZE(armada_370_xp_core_ratios),
-};
-
-#endif /* CONFIG_MACH_ARMADA_370_XP */
-
-/*
- * Dove PLL sample-at-reset configuration
- *
- * SAR0[8:5]   : CPU frequency
- *               5  = 1000 MHz
- *               6  =  933 MHz
- *               7  =  933 MHz
- *               8  =  800 MHz
- *               9  =  800 MHz
- *               10 =  800 MHz
- *               11 = 1067 MHz
- *               12 =  667 MHz
- *               13 =  533 MHz
- *               14 =  400 MHz
- *               15 =  333 MHz
- *               others reserved.
- *
- * SAR0[11:9]  : CPU to L2 Clock divider ratio
- *               0 = (1/1) * CPU
- *               2 = (1/2) * CPU
- *               4 = (1/3) * CPU
- *               6 = (1/4) * CPU
- *               others reserved.
- *
- * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
- *               0  = (1/1) * CPU
- *               2  = (1/2) * CPU
- *               3  = (2/5) * CPU
- *               4  = (1/3) * CPU
- *               6  = (1/4) * CPU
- *               8  = (1/5) * CPU
- *               10 = (1/6) * CPU
- *               12 = (1/7) * CPU
- *               14 = (1/8) * CPU
- *               15 = (1/10) * CPU
- *               others reserved.
- *
- * SAR0[24:23] : TCLK frequency
- *               0 = 166 MHz
- *               1 = 125 MHz
- *               others reserved.
- */
-#ifdef CONFIG_ARCH_DOVE
-#define SAR_DOVE_CPU_FREQ               5
-#define SAR_DOVE_CPU_FREQ_MASK          0xf
-#define SAR_DOVE_L2_RATIO               9
-#define SAR_DOVE_L2_RATIO_MASK          0x7
-#define SAR_DOVE_DDR_RATIO              12
-#define SAR_DOVE_DDR_RATIO_MASK         0xf
-#define SAR_DOVE_TCLK_FREQ              23
-#define SAR_DOVE_TCLK_FREQ_MASK         0x3
-
-static const u32 __initconst dove_tclk_frequencies[] = {
-        166666667,
-        125000000,
-        0, 0
-};
-
-static u32 __init dove_get_tclk_freq(void __iomem *sar)
-{
-        u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
-                SAR_DOVE_TCLK_FREQ_MASK;
-        return dove_tclk_frequencies[opt];
-}
-
-static const u32 __initconst dove_cpu_frequencies[] = {
-        0, 0, 0, 0, 0,
-        1000000000,
-        933333333, 933333333,
-        800000000, 800000000, 800000000,
-        1066666667,
-        666666667,
-        533333333,
-        400000000,
-        333333333
-};
-
-static u32 __init dove_get_cpu_freq(void __iomem *sar)
-{
-        u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
-                SAR_DOVE_CPU_FREQ_MASK;
-        return dove_cpu_frequencies[opt];
-}
-
-enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
-
-static const struct core_ratio __initconst dove_core_ratios[] = {
-        { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
-        { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static const int __initconst dove_cpu_l2_ratios[8][2] = {
-        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
-        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
-};
-
-static const int __initconst dove_cpu_ddr_ratios[16][2] = {
-        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
-        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
-        { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
-        { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
-};
-
-static void __init dove_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        switch (id) {
-        case DOVE_CPU_TO_L2:
-        {
-                u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
-                        SAR_DOVE_L2_RATIO_MASK;
-                *mult = dove_cpu_l2_ratios[opt][0];
-                *div = dove_cpu_l2_ratios[opt][1];
-                break;
-        }
-        case DOVE_CPU_TO_DDR:
-        {
-                u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
-                        SAR_DOVE_DDR_RATIO_MASK;
-                *mult = dove_cpu_ddr_ratios[opt][0];
-                *div = dove_cpu_ddr_ratios[opt][1];
-                break;
-        }
-        }
-}
-
-static const struct core_clocks dove_core_clocks = {
-        .get_tclk_freq = dove_get_tclk_freq,
-        .get_cpu_freq = dove_get_cpu_freq,
-        .get_clk_ratio = dove_get_clk_ratio,
-        .ratios = dove_core_ratios,
-        .num_ratios = ARRAY_SIZE(dove_core_ratios),
-};
-#endif /* CONFIG_ARCH_DOVE */
-
-/*
- * Kirkwood PLL sample-at-reset configuration
- * (6180 has different SAR layout than other Kirkwood SoCs)
- *
- * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
- *      4  =  600 MHz
- *      6  =  800 MHz
- *      7  = 1000 MHz
- *      9  = 1200 MHz
- *      12 = 1500 MHz
- *      13 = 1600 MHz
- *      14 = 1800 MHz
- *      15 = 2000 MHz
- *      others reserved.
- *
- * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
- *      1 = (1/2) * CPU
- *      3 = (1/3) * CPU
- *      5 = (1/4) * CPU
- *      others reserved.
- *
- * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
- *      2 = (1/2) * CPU
- *      4 = (1/3) * CPU
- *      6 = (1/4) * CPU
- *      7 = (2/9) * CPU
- *      8 = (1/5) * CPU
- *      9 = (1/6) * CPU
- *      others reserved.
- *
- * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
- *      5 = [CPU =  600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
- *      6 = [CPU =  800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
- *      7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
- *      others reserved.
- *
- * SAR0[21] : TCLK frequency
- *      0 = 200 MHz
- *      1 = 166 MHz
- *      others reserved.
- */
-#ifdef CONFIG_ARCH_KIRKWOOD
-#define SAR_KIRKWOOD_CPU_FREQ(x)        \
-        (((x & (1 <<  1)) >>  1) |      \
-         ((x & (1 << 22)) >> 21) |      \
-         ((x & (3 <<  3)) >>  1))
-#define SAR_KIRKWOOD_L2_RATIO(x)        \
-        (((x & (3 <<  9)) >> 9) |       \
-         (((x & (1 << 19)) >> 17)))
-#define SAR_KIRKWOOD_DDR_RATIO          5
-#define SAR_KIRKWOOD_DDR_RATIO_MASK     0xf
-#define SAR_MV88F6180_CLK               2
-#define SAR_MV88F6180_CLK_MASK          0x7
-#define SAR_KIRKWOOD_TCLK_FREQ          21
-#define SAR_KIRKWOOD_TCLK_FREQ_MASK     0x1
-
-enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
-
-static const struct core_ratio __initconst kirkwood_core_ratios[] = {
-        { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
-        { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
-};
-
-static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
-{
-        u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
-                SAR_KIRKWOOD_TCLK_FREQ_MASK;
-        return (opt) ? 166666667 : 200000000;
-}
-
-static const u32 __initconst kirkwood_cpu_frequencies[] = {
-        0, 0, 0, 0,
-        600000000,
-        0,
-        800000000,
-        1000000000,
-        0,
-        1200000000,
-        0, 0,
-        1500000000,
-        1600000000,
-        1800000000,
-        2000000000
-};
-
-static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
-{
-        u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
-        return kirkwood_cpu_frequencies[opt];
-}
-
-static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
-        { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
-        { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
-};
-
-static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
-        { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
-        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
-        { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
-        { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
-};
-
-static void __init kirkwood_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        switch (id) {
-        case KIRKWOOD_CPU_TO_L2:
-        {
-                u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
-                *mult = kirkwood_cpu_l2_ratios[opt][0];
-                *div = kirkwood_cpu_l2_ratios[opt][1];
-                break;
-        }
-        case KIRKWOOD_CPU_TO_DDR:
-        {
-                u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
-                        SAR_KIRKWOOD_DDR_RATIO_MASK;
-                *mult = kirkwood_cpu_ddr_ratios[opt][0];
-                *div = kirkwood_cpu_ddr_ratios[opt][1];
-                break;
-        }
-        }
-}
-
-static const struct core_clocks kirkwood_core_clocks = {
-        .get_tclk_freq = kirkwood_get_tclk_freq,
-        .get_cpu_freq = kirkwood_get_cpu_freq,
-        .get_clk_ratio = kirkwood_get_clk_ratio,
-        .ratios = kirkwood_core_ratios,
-        .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-
-static const u32 __initconst mv88f6180_cpu_frequencies[] = {
-        0, 0, 0, 0, 0,
-        600000000,
-        800000000,
-        1000000000
-};
-
-static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
-{
-        u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
-        return mv88f6180_cpu_frequencies[opt];
-}
-
-static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
-        { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
-        { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
-};
-
-static void __init mv88f6180_get_clk_ratio(
-        void __iomem *sar, int id, int *mult, int *div)
-{
-        switch (id) {
-        case KIRKWOOD_CPU_TO_L2:
-        {
-                /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
-                *mult = 1;
-                *div = 2;
-                break;
-        }
-        case KIRKWOOD_CPU_TO_DDR:
-        {
-                u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
-                        SAR_MV88F6180_CLK_MASK;
-                *mult = mv88f6180_cpu_ddr_ratios[opt][0];
-                *div = mv88f6180_cpu_ddr_ratios[opt][1];
-                break;
-        }
-        }
-}
-
-static const struct core_clocks mv88f6180_core_clocks = {
-        .get_tclk_freq = kirkwood_get_tclk_freq,
-        .get_cpu_freq = mv88f6180_get_cpu_freq,
-        .get_clk_ratio = mv88f6180_get_clk_ratio,
-        .ratios = kirkwood_core_ratios,
-        .num_ratios = ARRAY_SIZE(kirkwood_core_ratios),
-};
-#endif /* CONFIG_ARCH_KIRKWOOD */
-
-static const __initdata struct of_device_id clk_core_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370_XP
-        {
-                .compatible = "marvell,armada-370-core-clock",
-                .data = &armada_370_core_clocks,
-        },
-        {
-                .compatible = "marvell,armada-xp-core-clock",
-                .data = &armada_xp_core_clocks,
-        },
-#endif
-#ifdef CONFIG_ARCH_DOVE
-        {
-                .compatible = "marvell,dove-core-clock",
-                .data = &dove_core_clocks,
-        },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-        {
-                .compatible = "marvell,kirkwood-core-clock",
-                .data = &kirkwood_core_clocks,
-        },
-        {
-                .compatible = "marvell,mv88f6180-core-clock",
-                .data = &mv88f6180_core_clocks,
-        },
-#endif
-
-        { }
-};
-
-void __init mvebu_core_clk_init(void)
-{
-        struct device_node *np;
-
-        for_each_matching_node(np, clk_core_match) {
-                const struct of_device_id *match =
-                        of_match_node(clk_core_match, np);
-                mvebu_clk_core_setup(np, (struct core_clocks *)match->data);
-        }
-}
diff --git a/drivers/clk/mvebu/clk-core.h b/drivers/clk/mvebu/clk-core.h
deleted file mode 100644
index 28b5e02e9885..000000000000
--- a/drivers/clk/mvebu/clk-core.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- *  * Marvell EBU clock core handling defined at reset
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_CORE_H
-#define __MVEBU_CLK_CORE_H
-
-void __init mvebu_core_clk_init(void);
-
-#endif
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.c b/drivers/clk/mvebu/clk-gating-ctrl.c
deleted file mode 100644
index ebf141d4374b..000000000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.c
+++ /dev/null
@@ -1,250 +0,0 @@
-/*
- * Marvell MVEBU clock gating control.
- *
- * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
- * Andrew Lunn <andrew@lunn.ch>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/bitops.h>
-#include <linux/io.h>
-#include <linux/clk.h>
-#include <linux/clkdev.h>
-#include <linux/clk-provider.h>
-#include <linux/clk/mvebu.h>
-#include <linux/of.h>
-#include <linux/of_address.h>
-
-struct mvebu_gating_ctrl {
-        spinlock_t lock;
-        struct clk **gates;
-        int num_gates;
-};
-
-struct mvebu_soc_descr {
-        const char *name;
-        const char *parent;
-        int bit_idx;
-};
-
-#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
-
-static struct clk *mvebu_clk_gating_get_src(
-        struct of_phandle_args *clkspec, void *data)
-{
-        struct mvebu_gating_ctrl *ctrl = (struct mvebu_gating_ctrl *)data;
-        int n;
-
-        if (clkspec->args_count < 1)
-                return ERR_PTR(-EINVAL);
-
-        for (n = 0; n < ctrl->num_gates; n++) {
-                struct clk_gate *gate =
-                        to_clk_gate(__clk_get_hw(ctrl->gates[n]));
-                if (clkspec->args[0] == gate->bit_idx)
-                        return ctrl->gates[n];
-        }
-        return ERR_PTR(-ENODEV);
-}
-
-static void __init mvebu_clk_gating_setup(
-        struct device_node *np, const struct mvebu_soc_descr *descr)
-{
-        struct mvebu_gating_ctrl *ctrl;
-        struct clk *clk;
-        void __iomem *base;
-        const char *default_parent = NULL;
-        int n;
-
-        base = of_iomap(np, 0);
-
-        clk = of_clk_get(np, 0);
-        if (!IS_ERR(clk)) {
-                default_parent = __clk_get_name(clk);
-                clk_put(clk);
-        }
-
-        ctrl = kzalloc(sizeof(struct mvebu_gating_ctrl), GFP_KERNEL);
-        if (WARN_ON(!ctrl))
-                return;
-
-        spin_lock_init(&ctrl->lock);
-
-        /*
-         * Count, allocate, and register clock gates
-         */
-        for (n = 0; descr[n].name;)
-                n++;
-
-        ctrl->num_gates = n;
-        ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
-                              GFP_KERNEL);
-        if (WARN_ON(!ctrl->gates)) {
-                kfree(ctrl);
-                return;
-        }
-
-        for (n = 0; n < ctrl->num_gates; n++) {
-                u8 flags = 0;
-                const char *parent =
-                        (descr[n].parent) ? descr[n].parent : default_parent;
-
-                /*
-                 * On Armada 370, the DDR clock is a special case: it
-                 * isn't taken by any driver, but should anyway be
-                 * kept enabled, so we mark it as IGNORE_UNUSED for
-                 * now.
-                 */
-                if (!strcmp(descr[n].name, "ddr"))
-                        flags |= CLK_IGNORE_UNUSED;
-
-                ctrl->gates[n] = clk_register_gate(NULL, descr[n].name, parent,
-                                   flags, base, descr[n].bit_idx, 0, &ctrl->lock);
-                WARN_ON(IS_ERR(ctrl->gates[n]));
-        }
-        of_clk_add_provider(np, mvebu_clk_gating_get_src, ctrl);
-}
-
-/*
- * SoC specific clock gating control
- */
-
-#ifdef CONFIG_MACH_ARMADA_370
-static const struct mvebu_soc_descr __initconst armada_370_gating_descr[] = {
-        { "audio", NULL, 0 },
-        { "pex0_en", NULL, 1 },
-        { "pex1_en", NULL,  2 },
-        { "ge1", NULL, 3 },
-        { "ge0", NULL, 4 },
-        { "pex0", NULL, 5 },
-        { "pex1", NULL, 9 },
-        { "sata0", NULL, 15 },
-        { "sdio", NULL, 17 },
-        { "tdm", NULL, 25 },
-        { "ddr", NULL, 28 },
-        { "sata1", NULL, 30 },
-        { }
-};
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-static const struct mvebu_soc_descr __initconst armada_xp_gating_descr[] = {
-        { "audio", NULL, 0 },
-        { "ge3", NULL, 1 },
-        { "ge2", NULL,  2 },
-        { "ge1", NULL, 3 },
-        { "ge0", NULL, 4 },
-        { "pex0", NULL, 5 },
-        { "pex1", NULL, 6 },
-        { "pex2", NULL, 7 },
-        { "pex3", NULL, 8 },
-        { "bp", NULL, 13 },
-        { "sata0lnk", NULL, 14 },
-        { "sata0", "sata0lnk", 15 },
-        { "lcd", NULL, 16 },
-        { "sdio", NULL, 17 },
-        { "usb0", NULL, 18 },
-        { "usb1", NULL, 19 },
-        { "usb2", NULL, 20 },
-        { "xor0", NULL, 22 },
-        { "crypto", NULL, 23 },
-        { "tdm", NULL, 25 },
-        { "xor1", NULL, 28 },
-        { "sata1lnk", NULL, 29 },
-        { "sata1", "sata1lnk", 30 },
-        { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-static const struct mvebu_soc_descr __initconst dove_gating_descr[] = {
-        { "usb0", NULL, 0 },
-        { "usb1", NULL, 1 },
-        { "ge", "gephy", 2 },
-        { "sata", NULL, 3 },
-        { "pex0", NULL, 4 },
-        { "pex1", NULL, 5 },
-        { "sdio0", NULL, 8 },
-        { "sdio1", NULL, 9 },
-        { "nand", NULL, 10 },
-        { "camera", NULL, 11 },
-        { "i2s0", NULL, 12 },
-        { "i2s1", NULL, 13 },
-        { "crypto", NULL, 15 },
-        { "ac97", NULL, 21 },
-        { "pdma", NULL, 22 },
-        { "xor0", NULL, 23 },
-        { "xor1", NULL, 24 },
-        { "gephy", NULL, 30 },
-        { }
-};
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-static const struct mvebu_soc_descr __initconst kirkwood_gating_descr[] = {
-        { "ge0", NULL, 0 },
-        { "pex0", NULL, 2 },
-        { "usb0", NULL, 3 },
-        { "sdio", NULL, 4 },
-        { "tsu", NULL, 5 },
-        { "runit", NULL, 7 },
-        { "xor0", NULL, 8 },
-        { "audio", NULL, 9 },
-        { "powersave", "cpuclk", 11 },
-        { "sata0", NULL, 14 },
-        { "sata1", NULL, 15 },
-        { "xor1", NULL, 16 },
-        { "crypto", NULL, 17 },
-        { "pex1", NULL, 18 },
-        { "ge1", NULL, 19 },
-        { "tdm", NULL, 20 },
-        { }
-};
-#endif
-
-static const __initdata struct of_device_id clk_gating_match[] = {
-#ifdef CONFIG_MACH_ARMADA_370
-        {
-                .compatible = "marvell,armada-370-gating-clock",
-                .data = armada_370_gating_descr,
-        },
-#endif
-
-#ifdef CONFIG_MACH_ARMADA_XP
-        {
-                .compatible = "marvell,armada-xp-gating-clock",
-                .data = armada_xp_gating_descr,
-        },
-#endif
-
-#ifdef CONFIG_ARCH_DOVE
-        {
-                .compatible = "marvell,dove-gating-clock",
-                .data = dove_gating_descr,
-        },
-#endif
-
-#ifdef CONFIG_ARCH_KIRKWOOD
-        {
-                .compatible = "marvell,kirkwood-gating-clock",
-                .data = kirkwood_gating_descr,
-        },
-#endif
-
-        { }
-};
-
-void __init mvebu_gating_clk_init(void)
-{
-        struct device_node *np;
-
-        for_each_matching_node(np, clk_gating_match) {
-                const struct of_device_id *match =
-                        of_match_node(clk_gating_match, np);
-                mvebu_clk_gating_setup(np,
-                       (const struct mvebu_soc_descr *)match->data);
-        }
-}
diff --git a/drivers/clk/mvebu/clk-gating-ctrl.h b/drivers/clk/mvebu/clk-gating-ctrl.h
deleted file mode 100644
index 9275d1e51f1b..000000000000
--- a/drivers/clk/mvebu/clk-gating-ctrl.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Marvell EBU gating clock handling
- *
- * Copyright (C) 2012 Marvell
- *
- * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-
-#ifndef __MVEBU_CLK_GATING_H
-#define __MVEBU_CLK_GATING_H
-
-#ifdef CONFIG_MVEBU_CLK_GATING
-void __init mvebu_gating_clk_init(void);
-#else
-void mvebu_gating_clk_init(void) {}
-#endif
-
-#endif
diff --git a/drivers/clk/mvebu/clk.c b/drivers/clk/mvebu/clk.c
deleted file mode 100644
index 29f10fb3006c..000000000000
--- a/drivers/clk/mvebu/clk.c
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Marvell EBU SoC clock handling.
- *
- * Copyright (C) 2012 Marvell
- *
- * Gregory CLEMENT <gregory.clement@free-electrons.com>
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2.  This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
- */
-#include <linux/kernel.h>
-#include <linux/clk-provider.h>
-#include <linux/of.h>
-#include "clk-core.h"
-#include "clk-gating-ctrl.h"
-
-void __init mvebu_clocks_init(void)
-{
-        mvebu_core_clk_init();
-        mvebu_gating_clk_init();
-        of_clk_init(NULL);
-}
diff --git a/drivers/clk/mvebu/common.c b/drivers/clk/mvebu/common.c
new file mode 100644
index 000000000000..adaa4a1821b8
--- /dev/null
+++ b/drivers/clk/mvebu/common.c
@@ -0,0 +1,163 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk.h>
+#include <linux/clkdev.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+
+#include "common.h"
+
+/*
+ * Core Clocks
+ */
+
+static struct clk_onecell_data clk_data;
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+                                const struct coreclk_soc_desc *desc)
+{
+        const char *tclk_name = "tclk";
+        const char *cpuclk_name = "cpuclk";
+        void __iomem *base;
+        unsigned long rate;
+        int n;
+
+        base = of_iomap(np, 0);
+        if (WARN_ON(!base))
+                return;
+
+        /* Allocate struct for TCLK, cpu clk, and core ratio clocks */
+        clk_data.clk_num = 2 + desc->num_ratios;
+        clk_data.clks = kzalloc(clk_data.clk_num * sizeof(struct clk *),
+                                GFP_KERNEL);
+        if (WARN_ON(!clk_data.clks))
+                return;
+
+        /* Register TCLK */
+        of_property_read_string_index(np, "clock-output-names", 0,
+                                      &tclk_name);
+        rate = desc->get_tclk_freq(base);
+        clk_data.clks[0] = clk_register_fixed_rate(NULL, tclk_name, NULL,
+                                                   CLK_IS_ROOT, rate);
+        WARN_ON(IS_ERR(clk_data.clks[0]));
+
+        /* Register CPU clock */
+        of_property_read_string_index(np, "clock-output-names", 1,
+                                      &cpuclk_name);
+        rate = desc->get_cpu_freq(base);
+        clk_data.clks[1] = clk_register_fixed_rate(NULL, cpuclk_name, NULL,
+                                                   CLK_IS_ROOT, rate);
+        WARN_ON(IS_ERR(clk_data.clks[1]));
+
+        /* Register fixed-factor clocks derived from CPU clock */
+        for (n = 0; n < desc->num_ratios; n++) {
+                const char *rclk_name = desc->ratios[n].name;
+                int mult, div;
+
+                of_property_read_string_index(np, "clock-output-names",
+                                              2+n, &rclk_name);
+                desc->get_clk_ratio(base, desc->ratios[n].id, &mult, &div);
+                clk_data.clks[2+n] = clk_register_fixed_factor(NULL, rclk_name,
+                                       cpuclk_name, 0, mult, div);
+                WARN_ON(IS_ERR(clk_data.clks[2+n]));
+        };
+
+        /* SAR register isn't needed anymore */
+        iounmap(base);
+
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+/*
+ * Clock Gating Control
+ */
+
+struct clk_gating_ctrl {
+        spinlock_t lock;
+        struct clk **gates;
+        int num_gates;
+};
+
+#define to_clk_gate(_hw) container_of(_hw, struct clk_gate, hw)
+
+static struct clk *clk_gating_get_src(
+        struct of_phandle_args *clkspec, void *data)
+{
+        struct clk_gating_ctrl *ctrl = (struct clk_gating_ctrl *)data;
+        int n;
+
+        if (clkspec->args_count < 1)
+                return ERR_PTR(-EINVAL);
+
+        for (n = 0; n < ctrl->num_gates; n++) {
+                struct clk_gate *gate =
+                        to_clk_gate(__clk_get_hw(ctrl->gates[n]));
+                if (clkspec->args[0] == gate->bit_idx)
+                        return ctrl->gates[n];
+        }
+        return ERR_PTR(-ENODEV);
+}
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+                                   const struct clk_gating_soc_desc *desc)
+{
+        struct clk_gating_ctrl *ctrl;
+        struct clk *clk;
+        void __iomem *base;
+        const char *default_parent = NULL;
+        int n;
+
+        base = of_iomap(np, 0);
+        if (WARN_ON(!base))
+                return;
+
+        clk = of_clk_get(np, 0);
+        if (!IS_ERR(clk)) {
+                default_parent = __clk_get_name(clk);
+                clk_put(clk);
+        }
+
+        ctrl = kzalloc(sizeof(*ctrl), GFP_KERNEL);
+        if (WARN_ON(!ctrl))
+                return;
+
+        spin_lock_init(&ctrl->lock);
+
+        /* Count, allocate, and register clock gates */
+        for (n = 0; desc[n].name;)
+                n++;
+
+        ctrl->num_gates = n;
+        ctrl->gates = kzalloc(ctrl->num_gates * sizeof(struct clk *),
+                              GFP_KERNEL);
+        if (WARN_ON(!ctrl->gates)) {
+                kfree(ctrl);
+                return;
+        }
+
+        for (n = 0; n < ctrl->num_gates; n++) {
+                const char *parent =
+                        (desc[n].parent) ? desc[n].parent : default_parent;
+                ctrl->gates[n] = clk_register_gate(NULL, desc[n].name, parent,
+                                        desc[n].flags, base, desc[n].bit_idx,
+                                        0, &ctrl->lock);
+                WARN_ON(IS_ERR(ctrl->gates[n]));
+        }
+
+        of_clk_add_provider(np, clk_gating_get_src, ctrl);
+}
diff --git a/drivers/clk/mvebu/common.h b/drivers/clk/mvebu/common.h
new file mode 100644
index 000000000000..f968b4d9df92
--- /dev/null
+++ b/drivers/clk/mvebu/common.h
@@ -0,0 +1,48 @@
+/*
+ * Marvell EBU SoC common clock handling
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __CLK_MVEBU_COMMON_H_
+#define __CLK_MVEBU_COMMON_H_
+
+#include <linux/kernel.h>
+
+struct device_node;
+
+struct coreclk_ratio {
+        int id;
+        const char *name;
+};
+
+struct coreclk_soc_desc {
+        u32 (*get_tclk_freq)(void __iomem *sar);
+        u32 (*get_cpu_freq)(void __iomem *sar);
+        void (*get_clk_ratio)(void __iomem *sar, int id, int *mult, int *div);
+        const struct coreclk_ratio *ratios;
+        int num_ratios;
+};
+
+struct clk_gating_soc_desc {
+        const char *name;
+        const char *parent;
+        int bit_idx;
+        unsigned long flags;
+};
+
+void __init mvebu_coreclk_setup(struct device_node *np,
+                                const struct coreclk_soc_desc *desc);
+
+void __init mvebu_clk_gating_setup(struct device_node *np,
+                                   const struct clk_gating_soc_desc *desc);
+
+#endif
diff --git a/drivers/clk/mvebu/dove.c b/drivers/clk/mvebu/dove.c
new file mode 100644
index 000000000000..79d7aedf03fb
--- /dev/null
+++ b/drivers/clk/mvebu/dove.c
@@ -0,0 +1,194 @@
+/*
+ * Marvell Dove SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Dove PLL sample-at-reset configuration
+ *
+ * SAR0[8:5]   : CPU frequency
+ *               5  = 1000 MHz
+ *               6  =  933 MHz
+ *               7  =  933 MHz
+ *               8  =  800 MHz
+ *               9  =  800 MHz
+ *               10 =  800 MHz
+ *               11 = 1067 MHz
+ *               12 =  667 MHz
+ *               13 =  533 MHz
+ *               14 =  400 MHz
+ *               15 =  333 MHz
+ *               others reserved.
+ *
+ * SAR0[11:9]  : CPU to L2 Clock divider ratio
+ *               0 = (1/1) * CPU
+ *               2 = (1/2) * CPU
+ *               4 = (1/3) * CPU
+ *               6 = (1/4) * CPU
+ *               others reserved.
+ *
+ * SAR0[15:12] : CPU to DDR DRAM Clock divider ratio
+ *               0  = (1/1) * CPU
+ *               2  = (1/2) * CPU
+ *               3  = (2/5) * CPU
+ *               4  = (1/3) * CPU
+ *               6  = (1/4) * CPU
+ *               8  = (1/5) * CPU
+ *               10 = (1/6) * CPU
+ *               12 = (1/7) * CPU
+ *               14 = (1/8) * CPU
+ *               15 = (1/10) * CPU
+ *               others reserved.
+ *
+ * SAR0[24:23] : TCLK frequency
+ *               0 = 166 MHz
+ *               1 = 125 MHz
+ *               others reserved.
+ */
+
+#define SAR_DOVE_CPU_FREQ               5
+#define SAR_DOVE_CPU_FREQ_MASK          0xf
+#define SAR_DOVE_L2_RATIO               9
+#define SAR_DOVE_L2_RATIO_MASK          0x7
+#define SAR_DOVE_DDR_RATIO              12
+#define SAR_DOVE_DDR_RATIO_MASK         0xf
+#define SAR_DOVE_TCLK_FREQ              23
+#define SAR_DOVE_TCLK_FREQ_MASK         0x3
+
+enum { DOVE_CPU_TO_L2, DOVE_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst dove_coreclk_ratios[] = {
+        { .id = DOVE_CPU_TO_L2, .name = "l2clk", },
+        { .id = DOVE_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static const u32 __initconst dove_tclk_freqs[] = {
+        166666667,
+        125000000,
+        0, 0
+};
+
+static u32 __init dove_get_tclk_freq(void __iomem *sar)
+{
+        u32 opt = (readl(sar) >> SAR_DOVE_TCLK_FREQ) &
+                SAR_DOVE_TCLK_FREQ_MASK;
+        return dove_tclk_freqs[opt];
+}
+
+static const u32 __initconst dove_cpu_freqs[] = {
+        0, 0, 0, 0, 0,
+        1000000000,
+        933333333, 933333333,
+        800000000, 800000000, 800000000,
+        1066666667,
+        666666667,
+        533333333,
+        400000000,
+        333333333
+};
+
+static u32 __init dove_get_cpu_freq(void __iomem *sar)
+{
+        u32 opt = (readl(sar) >> SAR_DOVE_CPU_FREQ) &
+                SAR_DOVE_CPU_FREQ_MASK;
+        return dove_cpu_freqs[opt];
+}
+
+static const int __initconst dove_cpu_l2_ratios[8][2] = {
+        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 }
+};
+
+static const int __initconst dove_cpu_ddr_ratios[16][2] = {
+        { 1, 1 }, { 0, 1 }, { 1, 2 }, { 2, 5 },
+        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 0, 1 },
+        { 1, 5 }, { 0, 1 }, { 1, 6 }, { 0, 1 },
+        { 1, 7 }, { 0, 1 }, { 1, 8 }, { 1, 10 }
+};
+
+static void __init dove_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        switch (id) {
+        case DOVE_CPU_TO_L2:
+        {
+                u32 opt = (readl(sar) >> SAR_DOVE_L2_RATIO) &
+                        SAR_DOVE_L2_RATIO_MASK;
+                *mult = dove_cpu_l2_ratios[opt][0];
+                *div = dove_cpu_l2_ratios[opt][1];
+                break;
+        }
+        case DOVE_CPU_TO_DDR:
+        {
+                u32 opt = (readl(sar) >> SAR_DOVE_DDR_RATIO) &
+                        SAR_DOVE_DDR_RATIO_MASK;
+                *mult = dove_cpu_ddr_ratios[opt][0];
+                *div = dove_cpu_ddr_ratios[opt][1];
+                break;
+        }
+        }
+}
+
+static const struct coreclk_soc_desc dove_coreclks = {
+        .get_tclk_freq = dove_get_tclk_freq,
+        .get_cpu_freq = dove_get_cpu_freq,
+        .get_clk_ratio = dove_get_clk_ratio,
+        .ratios = dove_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(dove_coreclk_ratios),
+};
+
+static void __init dove_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &dove_coreclks);
+}
+CLK_OF_DECLARE(dove_core_clk, "marvell,dove-core-clock", dove_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst dove_gating_desc[] = {
+        { "usb0", NULL, 0, 0 },
+        { "usb1", NULL, 1, 0 },
+        { "ge", "gephy", 2, 0 },
+        { "sata", NULL, 3, 0 },
+        { "pex0", NULL, 4, 0 },
+        { "pex1", NULL, 5, 0 },
+        { "sdio0", NULL, 8, 0 },
+        { "sdio1", NULL, 9, 0 },
+        { "nand", NULL, 10, 0 },
+        { "camera", NULL, 11, 0 },
+        { "i2s0", NULL, 12, 0 },
+        { "i2s1", NULL, 13, 0 },
+        { "crypto", NULL, 15, 0 },
+        { "ac97", NULL, 21, 0 },
+        { "pdma", NULL, 22, 0 },
+        { "xor0", NULL, 23, 0 },
+        { "xor1", NULL, 24, 0 },
+        { "gephy", NULL, 30, 0 },
+        { }
+};
+
+static void __init dove_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, dove_gating_desc);
+}
+CLK_OF_DECLARE(dove_clk_gating, "marvell,dove-gating-clock",
+               dove_clk_gating_init);
diff --git a/drivers/clk/mvebu/kirkwood.c b/drivers/clk/mvebu/kirkwood.c
new file mode 100644
index 000000000000..71d24619ccdb
--- /dev/null
+++ b/drivers/clk/mvebu/kirkwood.c
@@ -0,0 +1,247 @@
+/*
+ * Marvell Kirkwood SoC clocks
+ *
+ * Copyright (C) 2012 Marvell
+ *
+ * Gregory CLEMENT <gregory.clement@free-electrons.com>
+ * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
+ * Andrew Lunn <andrew@lunn.ch>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/clk-provider.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include "common.h"
+
+/*
+ * Core Clocks
+ *
+ * Kirkwood PLL sample-at-reset configuration
+ * (6180 has different SAR layout than other Kirkwood SoCs)
+ *
+ * SAR0[4:3,22,1] : CPU frequency (6281,6292,6282)
+ *      4  =  600 MHz
+ *      6  =  800 MHz
+ *      7  = 1000 MHz
+ *      9  = 1200 MHz
+ *      12 = 1500 MHz
+ *      13 = 1600 MHz
+ *      14 = 1800 MHz
+ *      15 = 2000 MHz
+ *      others reserved.
+ *
+ * SAR0[19,10:9] : CPU to L2 Clock divider ratio (6281,6292,6282)
+ *      1 = (1/2) * CPU
+ *      3 = (1/3) * CPU
+ *      5 = (1/4) * CPU
+ *      others reserved.
+ *
+ * SAR0[8:5] : CPU to DDR DRAM Clock divider ratio (6281,6292,6282)
+ *      2 = (1/2) * CPU
+ *      4 = (1/3) * CPU
+ *      6 = (1/4) * CPU
+ *      7 = (2/9) * CPU
+ *      8 = (1/5) * CPU
+ *      9 = (1/6) * CPU
+ *      others reserved.
+ *
+ * SAR0[4:2] : Kirkwood 6180 cpu/l2/ddr clock configuration (6180 only)
+ *      5 = [CPU =  600 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/3) * CPU]
+ *      6 = [CPU =  800 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/4) * CPU]
+ *      7 = [CPU = 1000 MHz, L2 = (1/2) * CPU, DDR = 200 MHz = (1/5) * CPU]
+ *      others reserved.
+ *
+ * SAR0[21] : TCLK frequency
+ *      0 = 200 MHz
+ *      1 = 166 MHz
+ *      others reserved.
+ */
+
+#define SAR_KIRKWOOD_CPU_FREQ(x)        \
+        (((x & (1 <<  1)) >>  1) |      \
+         ((x & (1 << 22)) >> 21) |      \
+         ((x & (3 <<  3)) >>  1))
+#define SAR_KIRKWOOD_L2_RATIO(x)        \
+        (((x & (3 <<  9)) >> 9) |       \
+         (((x & (1 << 19)) >> 17)))
+#define SAR_KIRKWOOD_DDR_RATIO          5
+#define SAR_KIRKWOOD_DDR_RATIO_MASK     0xf
+#define SAR_MV88F6180_CLK               2
+#define SAR_MV88F6180_CLK_MASK          0x7
+#define SAR_KIRKWOOD_TCLK_FREQ          21
+#define SAR_KIRKWOOD_TCLK_FREQ_MASK     0x1
+
+enum { KIRKWOOD_CPU_TO_L2, KIRKWOOD_CPU_TO_DDR };
+
+static const struct coreclk_ratio __initconst kirkwood_coreclk_ratios[] = {
+        { .id = KIRKWOOD_CPU_TO_L2, .name = "l2clk", },
+        { .id = KIRKWOOD_CPU_TO_DDR, .name = "ddrclk", }
+};
+
+static u32 __init kirkwood_get_tclk_freq(void __iomem *sar)
+{
+        u32 opt = (readl(sar) >> SAR_KIRKWOOD_TCLK_FREQ) &
+                SAR_KIRKWOOD_TCLK_FREQ_MASK;
+        return (opt) ? 166666667 : 200000000;
+}
+
+static const u32 __initconst kirkwood_cpu_freqs[] = {
+        0, 0, 0, 0,
+        600000000,
+        0,
+        800000000,
+        1000000000,
+        0,
+        1200000000,
+        0, 0,
+        1500000000,
+        1600000000,
+        1800000000,
+        2000000000
+};
+
+static u32 __init kirkwood_get_cpu_freq(void __iomem *sar)
+{
+        u32 opt = SAR_KIRKWOOD_CPU_FREQ(readl(sar));
+        return kirkwood_cpu_freqs[opt];
+}
+
+static const int __initconst kirkwood_cpu_l2_ratios[8][2] = {
+        { 0, 1 }, { 1, 2 }, { 0, 1 }, { 1, 3 },
+        { 0, 1 }, { 1, 4 }, { 0, 1 }, { 0, 1 }
+};
+
+static const int __initconst kirkwood_cpu_ddr_ratios[16][2] = {
+        { 0, 1 }, { 0, 1 }, { 1, 2 }, { 0, 1 },
+        { 1, 3 }, { 0, 1 }, { 1, 4 }, { 2, 9 },
+        { 1, 5 }, { 1, 6 }, { 0, 1 }, { 0, 1 },
+        { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+};
+
+static void __init kirkwood_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        switch (id) {
+        case KIRKWOOD_CPU_TO_L2:
+        {
+                u32 opt = SAR_KIRKWOOD_L2_RATIO(readl(sar));
+                *mult = kirkwood_cpu_l2_ratios[opt][0];
+                *div = kirkwood_cpu_l2_ratios[opt][1];
+                break;
+        }
+        case KIRKWOOD_CPU_TO_DDR:
+        {
+                u32 opt = (readl(sar) >> SAR_KIRKWOOD_DDR_RATIO) &
+                        SAR_KIRKWOOD_DDR_RATIO_MASK;
+                *mult = kirkwood_cpu_ddr_ratios[opt][0];
+                *div = kirkwood_cpu_ddr_ratios[opt][1];
+                break;
+        }
+        }
+}
+
+static const u32 __initconst mv88f6180_cpu_freqs[] = {
+        0, 0, 0, 0, 0,
+        600000000,
+        800000000,
+        1000000000
+};
+
+static u32 __init mv88f6180_get_cpu_freq(void __iomem *sar)
+{
+        u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) & SAR_MV88F6180_CLK_MASK;
+        return mv88f6180_cpu_freqs[opt];
+}
+
+static const int __initconst mv88f6180_cpu_ddr_ratios[8][2] = {
+        { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 },
+        { 0, 1 }, { 1, 3 }, { 1, 4 }, { 1, 5 }
+};
+
+static void __init mv88f6180_get_clk_ratio(
+        void __iomem *sar, int id, int *mult, int *div)
+{
+        switch (id) {
+        case KIRKWOOD_CPU_TO_L2:
+        {
+                /* mv88f6180 has a fixed 1:2 CPU-to-L2 ratio */
+                *mult = 1;
+                *div = 2;
+                break;
+        }
+        case KIRKWOOD_CPU_TO_DDR:
+        {
+                u32 opt = (readl(sar) >> SAR_MV88F6180_CLK) &
+                        SAR_MV88F6180_CLK_MASK;
+                *mult = mv88f6180_cpu_ddr_ratios[opt][0];
+                *div = mv88f6180_cpu_ddr_ratios[opt][1];
+                break;
+        }
+        }
+}
+
+static const struct coreclk_soc_desc kirkwood_coreclks = {
+        .get_tclk_freq = kirkwood_get_tclk_freq,
+        .get_cpu_freq = kirkwood_get_cpu_freq,
+        .get_clk_ratio = kirkwood_get_clk_ratio,
+        .ratios = kirkwood_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init kirkwood_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &kirkwood_coreclks);
+}
+CLK_OF_DECLARE(kirkwood_core_clk, "marvell,kirkwood-core-clock",
+               kirkwood_coreclk_init);
+
+static const struct coreclk_soc_desc mv88f6180_coreclks = {
+        .get_tclk_freq = kirkwood_get_tclk_freq,
+        .get_cpu_freq = mv88f6180_get_cpu_freq,
+        .get_clk_ratio = mv88f6180_get_clk_ratio,
+        .ratios = kirkwood_coreclk_ratios,
+        .num_ratios = ARRAY_SIZE(kirkwood_coreclk_ratios),
+};
+
+static void __init mv88f6180_coreclk_init(struct device_node *np)
+{
+        mvebu_coreclk_setup(np, &mv88f6180_coreclks);
+}
+CLK_OF_DECLARE(mv88f6180_core_clk, "marvell,mv88f6180-core-clock",
+               mv88f6180_coreclk_init);
+
+/*
+ * Clock Gating Control
+ */
+
+static const struct clk_gating_soc_desc __initconst kirkwood_gating_desc[] = {
+        { "ge0", NULL, 0, 0 },
+        { "pex0", NULL, 2, 0 },
+        { "usb0", NULL, 3, 0 },
+        { "sdio", NULL, 4, 0 },
+        { "tsu", NULL, 5, 0 },
+        { "runit", NULL, 7, 0 },
+        { "xor0", NULL, 8, 0 },
+        { "audio", NULL, 9, 0 },
+        { "powersave", "cpuclk", 11, 0 },
+        { "sata0", NULL, 14, 0 },
+        { "sata1", NULL, 15, 0 },
+        { "xor1", NULL, 16, 0 },
+        { "crypto", NULL, 17, 0 },
+        { "pex1", NULL, 18, 0 },
+        { "ge1", NULL, 19, 0 },
+        { "tdm", NULL, 20, 0 },
+        { }
+};
+
+static void __init kirkwood_clk_gating_init(struct device_node *np)
+{
+        mvebu_clk_gating_setup(np, kirkwood_gating_desc);
+}
+CLK_OF_DECLARE(kirkwood_clk_gating, "marvell,kirkwood-gating-clock",
+               kirkwood_clk_gating_init);
diff --git a/drivers/clk/mxs/clk-imx28.c b/drivers/clk/mxs/clk-imx28.c
index d0e5eed146de..4faf0afc44cd 100644
--- a/drivers/clk/mxs/clk-imx28.c
+++ b/drivers/clk/mxs/clk-imx28.c
@@ -10,6 +10,7 @@
  */
 
 #include <linux/clk.h>
+#include <linux/clk/mxs.h>
 #include <linux/clkdev.h>
 #include <linux/err.h>
 #include <linux/init.h>
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index d0940e69d034..3c1f88868f29 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -791,7 +791,8 @@ struct samsung_gate_clock exynos4210_gate_clks[] __initdata = {
         GATE(smmu_pcie, "smmu_pcie", "aclk133", GATE_IP_FSYS, 18, 0, 0),
         GATE(modemif, "modemif", "aclk100", GATE_IP_PERIL, 28, 0, 0),
         GATE(chipid, "chipid", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
-        GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0, 0, 0),
+        GATE(sysreg, "sysreg", "aclk100", E4210_GATE_IP_PERIR, 0,
+                        CLK_IGNORE_UNUSED, 0),
         GATE(hdmi_cec, "hdmi_cec", "aclk100", E4210_GATE_IP_PERIR, 11, 0, 0),
         GATE(smmu_rotator, "smmu_rotator", "aclk200",
                         E4210_GATE_IP_IMAGE, 4, 0, 0),
@@ -819,7 +820,8 @@ struct samsung_gate_clock exynos4x12_gate_clks[] __initdata = {
         GATE(smmu_mdma, "smmu_mdma", "aclk200", E4X12_GATE_IP_IMAGE, 5, 0, 0),
         GATE(mipi_hsi, "mipi_hsi", "aclk133", GATE_IP_FSYS, 10, 0, 0),
         GATE(chipid, "chipid", "aclk100", E4X12_GATE_IP_PERIR, 0, 0, 0),
-        GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1, 0, 0),
+        GATE(sysreg, "sysreg", "aclk100", E4X12_GATE_IP_PERIR, 1,
+                        CLK_IGNORE_UNUSED, 0),
         GATE(hdmi_cec, "hdmi_cec", "aclk100", E4X12_GATE_IP_PERIR, 11, 0, 0),
         GATE(sclk_mdnie0, "sclk_mdnie0", "div_mdnie0",
                         SRC_MASK_LCD0, 4, CLK_SET_RATE_PARENT, 0),
diff --git a/drivers/clk/socfpga/clk.c b/drivers/clk/socfpga/clk.c
index bd11315cf5ab..5bb848cac6ec 100644
--- a/drivers/clk/socfpga/clk.c
+++ b/drivers/clk/socfpga/clk.c
@@ -24,15 +24,17 @@
 #include <linux/of.h>
 
 /* Clock Manager offsets */
-#define CLKMGR_CTRL    0x0
-#define CLKMGR_BYPASS 0x4
+#define CLKMGR_CTRL     0x0
+#define CLKMGR_BYPASS   0x4
+#define CLKMGR_L4SRC    0x70
+#define CLKMGR_PERPLL_SRC       0xAC
 
 /* Clock bypass bits */
-#define MAINPLL_BYPASS (1<<0)
-#define SDRAMPLL_BYPASS (1<<1)
-#define SDRAMPLL_SRC_BYPASS (1<<2)
-#define PERPLL_BYPASS (1<<3)
-#define PERPLL_SRC_BYPASS (1<<4)
+#define MAINPLL_BYPASS          (1<<0)
+#define SDRAMPLL_BYPASS         (1<<1)
+#define SDRAMPLL_SRC_BYPASS     (1<<2)
+#define PERPLL_BYPASS           (1<<3)
+#define PERPLL_SRC_BYPASS       (1<<4)
 
 #define SOCFPGA_PLL_BG_PWRDWN           0
 #define SOCFPGA_PLL_EXT_ENA             1
@@ -41,6 +43,17 @@
 #define SOCFPGA_PLL_DIVF_SHIFT  3
 #define SOCFPGA_PLL_DIVQ_MASK           0x003F0000
 #define SOCFPGA_PLL_DIVQ_SHIFT  16
+#define SOCFGPA_MAX_PARENTS     3
+
+#define SOCFPGA_L4_MP_CLK               "l4_mp_clk"
+#define SOCFPGA_L4_SP_CLK               "l4_sp_clk"
+#define SOCFPGA_NAND_CLK                "nand_clk"
+#define SOCFPGA_NAND_X_CLK              "nand_x_clk"
+#define SOCFPGA_MMC_CLK                 "mmc_clk"
+#define SOCFPGA_DB_CLK                  "gpio_db_clk"
+
+#define div_mask(width) ((1 << (width)) - 1)
+#define streq(a, b) (strcmp((a), (b)) == 0)
 
 extern void __iomem *clk_mgr_base_addr;
 
@@ -49,6 +62,9 @@ struct socfpga_clk {
         char *parent_name;
         char *clk_name;
         u32 fixed_div;
+        void __iomem *div_reg;
+        u32 width;      /* only valid if div_reg != 0 */
+        u32 shift;      /* only valid if div_reg != 0 */
 };
 #define to_socfpga_clk(p) container_of(p, struct socfpga_clk, hw.hw)
 
@@ -132,8 +148,9 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
 
         socfpga_clk->hw.hw.init = &init;
 
-        if (strcmp(clk_name, "main_pll") || strcmp(clk_name, "periph_pll") ||
-                        strcmp(clk_name, "sdram_pll")) {
+        if (streq(clk_name, "main_pll") ||
+                streq(clk_name, "periph_pll") ||
+                streq(clk_name, "sdram_pll")) {
                 socfpga_clk->hw.bit_idx = SOCFPGA_PLL_EXT_ENA;
                 clk_pll_ops.enable = clk_gate_ops.enable;
                 clk_pll_ops.disable = clk_gate_ops.disable;
@@ -148,6 +165,159 @@ static __init struct clk *socfpga_clk_init(struct device_node *node,
         return clk;
 }
 
+static u8 socfpga_clk_get_parent(struct clk_hw *hwclk)
+{
+        u32 l4_src;
+        u32 perpll_src;
+
+        if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+                l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+                return l4_src &= 0x1;
+        }
+        if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+                l4_src = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+                return !!(l4_src & 2);
+        }
+
+        perpll_src = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+        if (streq(hwclk->init->name, SOCFPGA_MMC_CLK))
+                return perpll_src &= 0x3;
+        if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+                        streq(hwclk->init->name, SOCFPGA_NAND_X_CLK))
+                        return (perpll_src >> 2) & 3;
+
+        /* QSPI clock */
+        return (perpll_src >> 4) & 3;
+
+}
+
+static int socfpga_clk_set_parent(struct clk_hw *hwclk, u8 parent)
+{
+        u32 src_reg;
+
+        if (streq(hwclk->init->name, SOCFPGA_L4_MP_CLK)) {
+                src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+                src_reg &= ~0x1;
+                src_reg |= parent;
+                writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+        } else if (streq(hwclk->init->name, SOCFPGA_L4_SP_CLK)) {
+                src_reg = readl(clk_mgr_base_addr + CLKMGR_L4SRC);
+                src_reg &= ~0x2;
+                src_reg |= (parent << 1);
+                writel(src_reg, clk_mgr_base_addr + CLKMGR_L4SRC);
+        } else {
+                src_reg = readl(clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+                if (streq(hwclk->init->name, SOCFPGA_MMC_CLK)) {
+                        src_reg &= ~0x3;
+                        src_reg |= parent;
+                } else if (streq(hwclk->init->name, SOCFPGA_NAND_CLK) ||
+                        streq(hwclk->init->name, SOCFPGA_NAND_X_CLK)) {
+                        src_reg &= ~0xC;
+                        src_reg |= (parent << 2);
+                } else {/* QSPI clock */
+                        src_reg &= ~0x30;
+                        src_reg |= (parent << 4);
+                }
+                writel(src_reg, clk_mgr_base_addr + CLKMGR_PERPLL_SRC);
+        }
+
+        return 0;
+}
+
+static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk,
+        unsigned long parent_rate)
+{
+        struct socfpga_clk *socfpgaclk = to_socfpga_clk(hwclk);
+        u32 div = 1, val;
+
+        if (socfpgaclk->fixed_div)
+                div = socfpgaclk->fixed_div;
+        else if (socfpgaclk->div_reg) {
+                val = readl(socfpgaclk->div_reg) >> socfpgaclk->shift;
+                val &= div_mask(socfpgaclk->width);
+                if (streq(hwclk->init->name, SOCFPGA_DB_CLK))
+                        div = val + 1;
+                else
+                        div = (1 << val);
+        }
+
+        return parent_rate / div;
+}
+
+static struct clk_ops gateclk_ops = {
+        .recalc_rate = socfpga_clk_recalc_rate,
+        .get_parent = socfpga_clk_get_parent,
+        .set_parent = socfpga_clk_set_parent,
+};
+
+static void __init socfpga_gate_clk_init(struct device_node *node,
+        const struct clk_ops *ops)
+{
+        u32 clk_gate[2];
+        u32 div_reg[3];
+        u32 fixed_div;
+        struct clk *clk;
+        struct socfpga_clk *socfpga_clk;
+        const char *clk_name = node->name;
+        const char *parent_name[SOCFGPA_MAX_PARENTS];
+        struct clk_init_data init;
+        int rc;
+        int i = 0;
+
+        socfpga_clk = kzalloc(sizeof(*socfpga_clk), GFP_KERNEL);
+        if (WARN_ON(!socfpga_clk))
+                return;
+
+        rc = of_property_read_u32_array(node, "clk-gate", clk_gate, 2);
+        if (rc)
+                clk_gate[0] = 0;
+
+        if (clk_gate[0]) {
+                socfpga_clk->hw.reg = clk_mgr_base_addr + clk_gate[0];
+                socfpga_clk->hw.bit_idx = clk_gate[1];
+
+                gateclk_ops.enable = clk_gate_ops.enable;
+                gateclk_ops.disable = clk_gate_ops.disable;
+        }
+
+        rc = of_property_read_u32(node, "fixed-divider", &fixed_div);
+        if (rc)
+                socfpga_clk->fixed_div = 0;
+        else
+                socfpga_clk->fixed_div = fixed_div;
+
+        rc = of_property_read_u32_array(node, "div-reg", div_reg, 3);
+        if (!rc) {
+                socfpga_clk->div_reg = clk_mgr_base_addr + div_reg[0];
+                socfpga_clk->shift = div_reg[1];
+                socfpga_clk->width = div_reg[2];
+        } else {
+                socfpga_clk->div_reg = 0;
+        }
+
+        of_property_read_string(node, "clock-output-names", &clk_name);
+
+        init.name = clk_name;
+        init.ops = ops;
+        init.flags = 0;
+        while (i < SOCFGPA_MAX_PARENTS && (parent_name[i] =
+                        of_clk_get_parent_name(node, i)) != NULL)
+                i++;
+
+        init.parent_names = parent_name;
+        init.num_parents = i;
+        socfpga_clk->hw.hw.init = &init;
+
+        clk = clk_register(NULL, &socfpga_clk->hw.hw);
+        if (WARN_ON(IS_ERR(clk))) {
+                kfree(socfpga_clk);
+                return;
+        }
+        rc = of_clk_add_provider(node, of_clk_src_simple_get, clk);
+        if (WARN_ON(rc))
+                return;
+}
+
 static void __init socfpga_pll_init(struct device_node *node)
 {
         socfpga_clk_init(node, &clk_pll_ops);
@@ -160,6 +330,12 @@ static void __init socfpga_periph_init(struct device_node *node)
 }
 CLK_OF_DECLARE(socfpga_periph, "altr,socfpga-perip-clk", socfpga_periph_init);
 
+static void __init socfpga_gate_init(struct device_node *node)
+{
+        socfpga_gate_clk_init(node, &gateclk_ops);
+}
+CLK_OF_DECLARE(socfpga_gate, "altr,socfpga-gate-clk", socfpga_gate_init);
+
 void __init socfpga_init_clocks(void)
 {
         struct clk *clk;
diff --git a/drivers/clk/tegra/clk-tegra114.c b/drivers/clk/tegra/clk-tegra114.c
index d78e16ee161c..40d939d091bf 100644
--- a/drivers/clk/tegra/clk-tegra114.c
+++ b/drivers/clk/tegra/clk-tegra114.c
@@ -250,6 +250,9 @@
 #define CLK_SOURCE_XUSB_DEV_SRC 0x60c
 #define CLK_SOURCE_EMC 0x19c
 
+/* Tegra CPU clock and reset control regs */
+#define CLK_RST_CONTROLLER_CPU_CMPLX_STATUS     0x470
+
 static int periph_clk_enb_refcnt[CLK_OUT_ENB_NUM * 32];
 
 static void __iomem *clk_base;
@@ -2000,7 +2003,25 @@ static __init void tegra114_periph_clk_init(void __iomem *clk_base)
         }
 }
 
-static struct tegra_cpu_car_ops tegra114_cpu_car_ops;
+/* Tegra114 CPU clock and reset control functions */
+static void tegra114_wait_cpu_in_reset(u32 cpu)
+{
+        unsigned int reg;
+
+        do {
+                reg = readl(clk_base + CLK_RST_CONTROLLER_CPU_CMPLX_STATUS);
+                cpu_relax();
+        } while (!(reg & (1 << cpu)));  /* check CPU been reset or not */
+}
+static void tegra114_disable_cpu_clock(u32 cpu)
+{
+        /* flow controller would take care in the power sequence. */
+}
+
+static struct tegra_cpu_car_ops tegra114_cpu_car_ops = {
+        .wait_for_reset = tegra114_wait_cpu_in_reset,
+        .disable_clock  = tegra114_disable_cpu_clock,
+};
 
 static const struct of_device_id pmc_match[] __initconst = {
         { .compatible = "nvidia,tegra114-pmc" },
diff --git a/drivers/clk/ux500/clk-sysctrl.c b/drivers/clk/ux500/clk-sysctrl.c
index bc7e9bde792b..e364c9d4aa60 100644
--- a/drivers/clk/ux500/clk-sysctrl.c
+++ b/drivers/clk/ux500/clk-sysctrl.c
@@ -145,7 +145,13 @@ static struct clk *clk_reg_sysctrl(struct device *dev,
                 return ERR_PTR(-ENOMEM);
         }
 
-        for (i = 0; i < num_parents; i++) {
+        /* set main clock registers */
+        clk->reg_sel[0] = reg_sel[0];
+        clk->reg_bits[0] = reg_bits[0];
+        clk->reg_mask[0] = reg_mask[0];
+
+        /* handle clocks with more than one parent */
+        for (i = 1; i < num_parents; i++) {
                 clk->reg_sel[i] = reg_sel[i];
                 clk->reg_bits[i] = reg_bits[i];
                 clk->reg_mask[i] = reg_mask[i];
diff --git a/drivers/clk/ux500/u8500_clk.c b/drivers/clk/ux500/u8500_clk.c
index 0b4f35a5ffc2..80069c370a47 100644
--- a/drivers/clk/ux500/u8500_clk.c
+++ b/drivers/clk/ux500/u8500_clk.c
@@ -325,7 +325,7 @@ void u8500_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
         clk = clk_reg_prcc_pclk("p3_pclk0", "per3clk", clkrst3_base,
                                 BIT(0), 0);
         clk_register_clkdev(clk, "fsmc", NULL);
-        clk_register_clkdev(clk, NULL, "smsc911x");
+        clk_register_clkdev(clk, NULL, "smsc911x.0");
 
         clk = clk_reg_prcc_pclk("p3_pclk1", "per3clk", clkrst3_base,
                                 BIT(1), 0);
diff --git a/drivers/clk/zynq/Makefile b/drivers/clk/zynq/Makefile
new file mode 100644
index 000000000000..156d923f4fa9
--- /dev/null
+++ b/drivers/clk/zynq/Makefile
@@ -0,0 +1,3 @@
+# Zynq clock specific Makefile
+
+obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
new file mode 100644
index 000000000000..5c205b60a82a
--- /dev/null
+++ b/drivers/clk/zynq/clkc.c
@@ -0,0 +1,533 @@
+/*
+ * Zynq clock controller
+ *
+ *  Copyright (C) 2012 - 2013 Xilinx
+ *
+ *  Sören Brinkmann <soren.brinkmann@xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include <linux/clk/zynq.h>
+#include <linux/clk-provider.h>
+#include <linux/of.h>
+#include <linux/slab.h>
+#include <linux/string.h>
+#include <linux/io.h>
+
+static void __iomem *zynq_slcr_base_priv;
+
+#define SLCR_ARMPLL_CTRL                (zynq_slcr_base_priv + 0x100)
+#define SLCR_DDRPLL_CTRL                (zynq_slcr_base_priv + 0x104)
+#define SLCR_IOPLL_CTRL                 (zynq_slcr_base_priv + 0x108)
+#define SLCR_PLL_STATUS                 (zynq_slcr_base_priv + 0x10c)
+#define SLCR_ARM_CLK_CTRL               (zynq_slcr_base_priv + 0x120)
+#define SLCR_DDR_CLK_CTRL               (zynq_slcr_base_priv + 0x124)
+#define SLCR_DCI_CLK_CTRL               (zynq_slcr_base_priv + 0x128)
+#define SLCR_APER_CLK_CTRL              (zynq_slcr_base_priv + 0x12c)
+#define SLCR_GEM0_CLK_CTRL              (zynq_slcr_base_priv + 0x140)
+#define SLCR_GEM1_CLK_CTRL              (zynq_slcr_base_priv + 0x144)
+#define SLCR_SMC_CLK_CTRL               (zynq_slcr_base_priv + 0x148)
+#define SLCR_LQSPI_CLK_CTRL             (zynq_slcr_base_priv + 0x14c)
+#define SLCR_SDIO_CLK_CTRL              (zynq_slcr_base_priv + 0x150)
+#define SLCR_UART_CLK_CTRL              (zynq_slcr_base_priv + 0x154)
+#define SLCR_SPI_CLK_CTRL               (zynq_slcr_base_priv + 0x158)
+#define SLCR_CAN_CLK_CTRL               (zynq_slcr_base_priv + 0x15c)
+#define SLCR_CAN_MIOCLK_CTRL            (zynq_slcr_base_priv + 0x160)
+#define SLCR_DBG_CLK_CTRL               (zynq_slcr_base_priv + 0x164)
+#define SLCR_PCAP_CLK_CTRL              (zynq_slcr_base_priv + 0x168)
+#define SLCR_FPGA0_CLK_CTRL             (zynq_slcr_base_priv + 0x170)
+#define SLCR_621_TRUE                   (zynq_slcr_base_priv + 0x1c4)
+#define SLCR_SWDT_CLK_SEL               (zynq_slcr_base_priv + 0x304)
+
+#define NUM_MIO_PINS    54
+
+enum zynq_clk {
+        armpll, ddrpll, iopll,
+        cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
+        ddr2x, ddr3x, dci,
+        lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
+        sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
+        usb0_aper, usb1_aper, gem0_aper, gem1_aper,
+        sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
+        i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
+        smc_aper, swdt, dbg_trc, dbg_apb, clk_max};
+
+static struct clk *ps_clk;
+static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
+
+static DEFINE_SPINLOCK(armpll_lock);
+static DEFINE_SPINLOCK(ddrpll_lock);
+static DEFINE_SPINLOCK(iopll_lock);
+static DEFINE_SPINLOCK(armclk_lock);
+static DEFINE_SPINLOCK(ddrclk_lock);
+static DEFINE_SPINLOCK(dciclk_lock);
+static DEFINE_SPINLOCK(gem0clk_lock);
+static DEFINE_SPINLOCK(gem1clk_lock);
+static DEFINE_SPINLOCK(canclk_lock);
+static DEFINE_SPINLOCK(canmioclk_lock);
+static DEFINE_SPINLOCK(dbgclk_lock);
+static DEFINE_SPINLOCK(aperclk_lock);
+
+static const char dummy_nm[] __initconst = "dummy_name";
+
+static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"};
+static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"};
+static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"};
+static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm};
+static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm};
+static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate",
+        "can0_mio_mux"};
+static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate",
+        "can1_mio_mux"};
+static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div",
+        dummy_nm};
+
+static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"};
+static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"};
+static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"};
+static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"};
+
+static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
+                const char *clk_name, void __iomem *fclk_ctrl_reg,
+                const char **parents)
+{
+        struct clk *clk;
+        char *mux_name;
+        char *div0_name;
+        char *div1_name;
+        spinlock_t *fclk_lock;
+        spinlock_t *fclk_gate_lock;
+        void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8;
+
+        fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL);
+        if (!fclk_lock)
+                goto err;
+        fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL);
+        if (!fclk_gate_lock)
+                goto err;
+        spin_lock_init(fclk_lock);
+        spin_lock_init(fclk_gate_lock);
+
+        mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name);
+        div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name);
+        div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name);
+
+        clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
+                        fclk_ctrl_reg, 4, 2, 0, fclk_lock);
+
+        clk = clk_register_divider(NULL, div0_name, mux_name,
+                        0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
+
+        clk = clk_register_divider(NULL, div1_name, div0_name,
+                        CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        fclk_lock);
+
+        clks[fclk] = clk_register_gate(NULL, clk_name,
+                        div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
+                        0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
+        kfree(mux_name);
+        kfree(div0_name);
+        kfree(div1_name);
+
+        return;
+
+err:
+        clks[fclk] = ERR_PTR(-ENOMEM);
+}
+
+static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
+                enum zynq_clk clk1, const char *clk_name0,
+                const char *clk_name1, void __iomem *clk_ctrl,
+                const char **parents, unsigned int two_gates)
+{
+        struct clk *clk;
+        char *mux_name;
+        char *div_name;
+        spinlock_t *lock;
+
+        lock = kmalloc(sizeof(*lock), GFP_KERNEL);
+        if (!lock)
+                goto err;
+        spin_lock_init(lock);
+
+        mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
+        div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
+
+        clk = clk_register_mux(NULL, mux_name, parents, 4, 0,
+                        clk_ctrl, 4, 2, 0, lock);
+
+        clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
+
+        clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
+                        CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock);
+        if (two_gates)
+                clks[clk1] = clk_register_gate(NULL, clk_name1, div_name,
+                                CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock);
+
+        kfree(mux_name);
+        kfree(div_name);
+
+        return;
+
+err:
+        clks[clk0] = ERR_PTR(-ENOMEM);
+        if (two_gates)
+                clks[clk1] = ERR_PTR(-ENOMEM);
+}
+
+static void __init zynq_clk_setup(struct device_node *np)
+{
+        int i;
+        u32 tmp;
+        int ret;
+        struct clk *clk;
+        char *clk_name;
+        const char *clk_output_name[clk_max];
+        const char *cpu_parents[4];
+        const char *periph_parents[4];
+        const char *swdt_ext_clk_mux_parents[2];
+        const char *can_mio_mux_parents[NUM_MIO_PINS];
+
+        pr_info("Zynq clock init\n");
+
+        /* get clock output names from DT */
+        for (i = 0; i < clk_max; i++) {
+                if (of_property_read_string_index(np, "clock-output-names",
+                                  i, &clk_output_name[i])) {
+                        pr_err("%s: clock output name not in DT\n", __func__);
+                        BUG();
+                }
+        }
+        cpu_parents[0] = clk_output_name[armpll];
+        cpu_parents[1] = clk_output_name[armpll];
+        cpu_parents[2] = clk_output_name[ddrpll];
+        cpu_parents[3] = clk_output_name[iopll];
+        periph_parents[0] = clk_output_name[iopll];
+        periph_parents[1] = clk_output_name[iopll];
+        periph_parents[2] = clk_output_name[armpll];
+        periph_parents[3] = clk_output_name[ddrpll];
+
+        /* ps_clk */
+        ret = of_property_read_u32(np, "ps-clk-frequency", &tmp);
+        if (ret) {
+                pr_warn("ps_clk frequency not specified, using 33 MHz.\n");
+                tmp = 33333333;
+        }
+        ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT,
+                        tmp);
+
+        /* PLLs */
+        clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
+                        SLCR_PLL_STATUS, 0, &armpll_lock);
+        clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
+                        armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0,
+                        &armpll_lock);
+
+        clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
+                        SLCR_PLL_STATUS, 1, &ddrpll_lock);
+        clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
+                        ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0,
+                        &ddrpll_lock);
+
+        clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
+                        SLCR_PLL_STATUS, 2, &iopll_lock);
+        clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
+                        iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0,
+                        &iopll_lock);
+
+        /* CPU clocks */
+        tmp = readl(SLCR_621_TRUE) & 1;
+        clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0,
+                        SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock);
+        clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
+                        SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
+
+        clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x],
+                        "cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
+                        SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
+
+        clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
+                        1, 2);
+        clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
+                        "cpu_3or2x_div", CLK_IGNORE_UNUSED,
+                        SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
+
+        clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
+                        2 + tmp);
+        clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
+                        "cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
+                        26, 0, &armclk_lock);
+
+        clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
+                        4 + 2 * tmp);
+        clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
+                        "cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
+                        0, &armclk_lock);
+
+        /* Timers */
+        swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x];
+        for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) {
+                int idx = of_property_match_string(np, "clock-names",
+                                swdt_ext_clk_input_names[i]);
+                if (idx >= 0)
+                        swdt_ext_clk_mux_parents[i + 1] =
+                                of_clk_get_parent_name(np, idx);
+                else
+                        swdt_ext_clk_mux_parents[i + 1] = dummy_nm;
+        }
+        clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt],
+                        swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT,
+                        SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock);
+
+        /* DDR clocks */
+        clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
+                        SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
+        clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
+                        "ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
+        clk_prepare_enable(clks[ddr2x]);
+        clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
+                        SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
+        clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
+                        "ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
+        clk_prepare_enable(clks[ddr3x]);
+
+        clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
+                        SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
+        clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
+                        CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        &dciclk_lock);
+        clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1",
+                        CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0,
+                        &dciclk_lock);
+        clk_prepare_enable(clks[dci]);
+
+        /* Peripheral clocks */
+        for (i = fclk0; i <= fclk3; i++)
+                zynq_clk_register_fclk(i, clk_output_name[i],
+                                SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0),
+                                periph_parents);
+
+        zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL,
+                        SLCR_LQSPI_CLK_CTRL, periph_parents, 0);
+
+        zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL,
+                        SLCR_SMC_CLK_CTRL, periph_parents, 0);
+
+        zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL,
+                        SLCR_PCAP_CLK_CTRL, periph_parents, 0);
+
+        zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0],
+                        clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL,
+                        periph_parents, 1);
+
+        zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0],
+                        clk_output_name[uart1], SLCR_UART_CLK_CTRL,
+                        periph_parents, 1);
+
+        zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0],
+                        clk_output_name[spi1], SLCR_SPI_CLK_CTRL,
+                        periph_parents, 1);
+
+        for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) {
+                int idx = of_property_match_string(np, "clock-names",
+                                gem0_emio_input_names[i]);
+                if (idx >= 0)
+                        gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
+                                        idx);
+        }
+        clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0,
+                        SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock);
+        clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
+                        SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
+        clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
+                        CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        &gem0clk_lock);
+        clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0,
+                        SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock);
+        clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0],
+                        "gem0_emio_mux", CLK_SET_RATE_PARENT,
+                        SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock);
+
+        for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) {
+                int idx = of_property_match_string(np, "clock-names",
+                                gem1_emio_input_names[i]);
+                if (idx >= 0)
+                        gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
+                                        idx);
+        }
+        clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0,
+                        SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock);
+        clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
+                        SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
+        clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
+                        CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        &gem1clk_lock);
+        clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0,
+                        SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock);
+        clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1],
+                        "gem1_emio_mux", CLK_SET_RATE_PARENT,
+                        SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock);
+
+        tmp = strlen("mio_clk_00x");
+        clk_name = kmalloc(tmp, GFP_KERNEL);
+        for (i = 0; i < NUM_MIO_PINS; i++) {
+                int idx;
+
+                snprintf(clk_name, tmp, "mio_clk_%2.2d", i);
+                idx = of_property_match_string(np, "clock-names", clk_name);
+                if (idx >= 0)
+                        can_mio_mux_parents[i] = of_clk_get_parent_name(np,
+                                                idx);
+                else
+                        can_mio_mux_parents[i] = dummy_nm;
+        }
+        kfree(clk_name);
+        clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0,
+                        SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock);
+        clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
+                        SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
+        clk = clk_register_divider(NULL, "can_div1", "can_div0",
+                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
+                        CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
+                        &canclk_lock);
+        clk = clk_register_gate(NULL, "can0_gate", "can_div1",
+                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
+                        &canclk_lock);
+        clk = clk_register_gate(NULL, "can1_gate", "can_div1",
+                        CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
+                        &canclk_lock);
+        clk = clk_register_mux(NULL, "can0_mio_mux",
+                        can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
+                        SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock);
+        clk = clk_register_mux(NULL, "can1_mio_mux",
+                        can_mio_mux_parents, 54, CLK_SET_RATE_PARENT,
+                        SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock);
+        clks[can0] = clk_register_mux(NULL, clk_output_name[can0],
+                        can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
+                        SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock);
+        clks[can1] = clk_register_mux(NULL, clk_output_name[can1],
+                        can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT,
+                        SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock);
+
+        for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) {
+                int idx = of_property_match_string(np, "clock-names",
+                                dbgtrc_emio_input_names[i]);
+                if (idx >= 0)
+                        dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
+                                        idx);
+        }
+        clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0,
+                        SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock);
+        clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
+                        SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
+                        CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
+        clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0,
+                        SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock);
+        clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
+                        "dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL,
+                        0, 0, &dbgclk_lock);
+        clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb],
+                        clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0,
+                        &dbgclk_lock);
+
+        /* One gated clock for all APER clocks. */
+        clks[dma] = clk_register_gate(NULL, clk_output_name[dma],
+                        clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0,
+                        &aperclk_lock);
+        clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0,
+                        &aperclk_lock);
+        clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0,
+                        &aperclk_lock);
+        clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0,
+                        &aperclk_lock);
+        clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0,
+                        &aperclk_lock);
+        clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0,
+                        &aperclk_lock);
+        clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0,
+                        &aperclk_lock);
+        clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0,
+                        &aperclk_lock);
+        clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0,
+                        &aperclk_lock);
+        clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0,
+                        &aperclk_lock);
+        clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0,
+                        &aperclk_lock);
+        clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0,
+                        &aperclk_lock);
+        clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0,
+                        &aperclk_lock);
+        clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0,
+                        &aperclk_lock);
+        clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0,
+                        &aperclk_lock);
+        clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0,
+                        &aperclk_lock);
+        clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0,
+                        &aperclk_lock);
+        clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper],
+                        clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0,
+                        &aperclk_lock);
+
+        for (i = 0; i < ARRAY_SIZE(clks); i++) {
+                if (IS_ERR(clks[i])) {
+                        pr_err("Zynq clk %d: register failed with %ld\n",
+                               i, PTR_ERR(clks[i]));
+                        BUG();
+                }
+        }
+
+        clk_data.clks = clks;
+        clk_data.clk_num = ARRAY_SIZE(clks);
+        of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
+}
+
+CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
+
+void __init zynq_clock_init(void __iomem *slcr_base)
+{
+        zynq_slcr_base_priv = slcr_base;
+        of_clk_init(NULL);
+}
diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
new file mode 100644
index 000000000000..47e307c25a7b
--- /dev/null
+++ b/drivers/clk/zynq/pll.c
@@ -0,0 +1,235 @@
+/*
+ * Zynq PLL driver
+ *
+ *  Copyright (C) 2013 Xilinx
+ *
+ *  Sören Brinkmann <soren.brinkmann@xilinx.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License v2 as published by
+ * the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+#include <linux/clk/zynq.h>
+#include <linux/clk-provider.h>
+#include <linux/slab.h>
+#include <linux/io.h>
+
+/**
+ * struct zynq_pll
+ * @hw:         Handle between common and hardware-specific interfaces
+ * @pll_ctrl:   PLL control register
+ * @pll_status: PLL status register
+ * @lock:       Register lock
+ * @lockbit:    Indicates the associated PLL_LOCKED bit in the PLL status
+ *              register.
+ */
+struct zynq_pll {
+        struct clk_hw   hw;
+        void __iomem    *pll_ctrl;
+        void __iomem    *pll_status;
+        spinlock_t      *lock;
+        u8              lockbit;
+};
+#define to_zynq_pll(_hw)        container_of(_hw, struct zynq_pll, hw)
+
+/* Register bitfield defines */
+#define PLLCTRL_FBDIV_MASK      0x7f000
+#define PLLCTRL_FBDIV_SHIFT     12
+#define PLLCTRL_BPQUAL_MASK     (1 << 3)
+#define PLLCTRL_PWRDWN_MASK     2
+#define PLLCTRL_PWRDWN_SHIFT    1
+#define PLLCTRL_RESET_MASK      1
+#define PLLCTRL_RESET_SHIFT     0
+
+/**
+ * zynq_pll_round_rate() - Round a clock frequency
+ * @hw:         Handle between common and hardware-specific interfaces
+ * @rate:       Desired clock frequency
+ * @prate:      Clock frequency of parent clock
+ * Returns frequency closest to @rate the hardware can generate.
+ */
+static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate,
+                unsigned long *prate)
+{
+        u32 fbdiv;
+
+        fbdiv = DIV_ROUND_CLOSEST(rate, *prate);
+        if (fbdiv < 13)
+                fbdiv = 13;
+        else if (fbdiv > 66)
+                fbdiv = 66;
+
+        return *prate * fbdiv;
+}
+
+/**
+ * zynq_pll_recalc_rate() - Recalculate clock frequency
+ * @hw:                 Handle between common and hardware-specific interfaces
+ * @parent_rate:        Clock frequency of parent clock
+ * Returns current clock frequency.
+ */
+static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
+                unsigned long parent_rate)
+{
+        struct zynq_pll *clk = to_zynq_pll(hw);
+        u32 fbdiv;
+
+        /*
+         * makes probably sense to redundantly save fbdiv in the struct
+         * zynq_pll to save the IO access.
+         */
+        fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
+                        PLLCTRL_FBDIV_SHIFT;
+
+        return parent_rate * fbdiv;
+}
+
+/**
+ * zynq_pll_is_enabled - Check if a clock is enabled
+ * @hw:         Handle between common and hardware-specific interfaces
+ * Returns 1 if the clock is enabled, 0 otherwise.
+ *
+ * Not sure this is a good idea, but since disabled means bypassed for
+ * this clock implementation we say we are always enabled.
+ */
+static int zynq_pll_is_enabled(struct clk_hw *hw)
+{
+        unsigned long flags = 0;
+        u32 reg;
+        struct zynq_pll *clk = to_zynq_pll(hw);
+
+        spin_lock_irqsave(clk->lock, flags);
+
+        reg = readl(clk->pll_ctrl);
+
+        spin_unlock_irqrestore(clk->lock, flags);
+
+        return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK));
+}
+
+/**
+ * zynq_pll_enable - Enable clock
+ * @hw:         Handle between common and hardware-specific interfaces
+ * Returns 0 on success
+ */
+static int zynq_pll_enable(struct clk_hw *hw)
+{
+        unsigned long flags = 0;
+        u32 reg;
+        struct zynq_pll *clk = to_zynq_pll(hw);
+
+        if (zynq_pll_is_enabled(hw))
+                return 0;
+
+        pr_info("PLL: enable\n");
+
+        /* Power up PLL and wait for lock */
+        spin_lock_irqsave(clk->lock, flags);
+
+        reg = readl(clk->pll_ctrl);
+        reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
+        writel(reg, clk->pll_ctrl);
+        while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
+                ;
+
+        spin_unlock_irqrestore(clk->lock, flags);
+
+        return 0;
+}
+
+/**
+ * zynq_pll_disable - Disable clock
+ * @hw:         Handle between common and hardware-specific interfaces
+ * Returns 0 on success
+ */
+static void zynq_pll_disable(struct clk_hw *hw)
+{
+        unsigned long flags = 0;
+        u32 reg;
+        struct zynq_pll *clk = to_zynq_pll(hw);
+
+        if (!zynq_pll_is_enabled(hw))
+                return;
+
+        pr_info("PLL: shutdown\n");
+
+        /* shut down PLL */
+        spin_lock_irqsave(clk->lock, flags);
+
+        reg = readl(clk->pll_ctrl);
+        reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
+        writel(reg, clk->pll_ctrl);
+
+        spin_unlock_irqrestore(clk->lock, flags);
+}
+
+static const struct clk_ops zynq_pll_ops = {
+        .enable = zynq_pll_enable,
+        .disable = zynq_pll_disable,
+        .is_enabled = zynq_pll_is_enabled,
+        .round_rate = zynq_pll_round_rate,
+        .recalc_rate = zynq_pll_recalc_rate
+};
+
+/**
+ * clk_register_zynq_pll() - Register PLL with the clock framework
+ * @np  Pointer to the DT device node
+ */
+struct clk *clk_register_zynq_pll(const char *name, const char *parent,
+                void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
+                spinlock_t *lock)
+{
+        struct zynq_pll *pll;
+        struct clk *clk;
+        u32 reg;
+        const char *parent_arr[1] = {parent};
+        unsigned long flags = 0;
+        struct clk_init_data initd = {
+                .name = name,
+                .parent_names = parent_arr,
+                .ops = &zynq_pll_ops,
+                .num_parents = 1,
+                .flags = 0
+        };
+
+        pll = kmalloc(sizeof(*pll), GFP_KERNEL);
+        if (!pll) {
+                pr_err("%s: Could not allocate Zynq PLL clk.\n", __func__);
+                return ERR_PTR(-ENOMEM);
+        }
+
+        /* Populate the struct */
+        pll->hw.init = &initd;
+        pll->pll_ctrl = pll_ctrl;
+        pll->pll_status = pll_status;
+        pll->lockbit = lock_index;
+        pll->lock = lock;
+
+        spin_lock_irqsave(pll->lock, flags);
+
+        reg = readl(pll->pll_ctrl);
+        reg &= ~PLLCTRL_BPQUAL_MASK;
+        writel(reg, pll->pll_ctrl);
+
+        spin_unlock_irqrestore(pll->lock, flags);
+
+        clk = clk_register(NULL, &pll->hw);
+        if (WARN_ON(IS_ERR(clk)))
+                goto free_pll;
+
+        return clk;
+
+free_pll:
+        kfree(pll);
+
+        return clk;
+}
diff --git a/drivers/clocksource/cadence_ttc_timer.c b/drivers/clocksource/cadence_ttc_timer.c
index 685bc60e210a..4cbe28c74631 100644
--- a/drivers/clocksource/cadence_ttc_timer.c
+++ b/drivers/clocksource/cadence_ttc_timer.c
@@ -51,6 +51,8 @@
 
 #define TTC_CNT_CNTRL_DISABLE_MASK      0x1
 
+#define TTC_CLK_CNTRL_CSRC_MASK         (1 << 5)        /* clock source */
+
 /*
  * Setup the timers to use pre-scaling, using a fixed value for now that will
  * work across most input frequency, but it may need to be more dynamic
@@ -396,8 +398,9 @@ static void __init ttc_timer_init(struct device_node *timer)
 {
         unsigned int irq;
         void __iomem *timer_baseaddr;
-        struct clk *clk;
+        struct clk *clk_cs, *clk_ce;
         static int initialized;
+        int clksel;
 
         if (initialized)
                 return;
@@ -421,14 +424,24 @@ static void __init ttc_timer_init(struct device_node *timer)
                 BUG();
         }
 
-        clk = of_clk_get_by_name(timer, "cpu_1x");
-        if (IS_ERR(clk)) {
+        clksel = __raw_readl(timer_baseaddr + TTC_CLK_CNTRL_OFFSET);
+        clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
+        clk_cs = of_clk_get(timer, clksel);
+        if (IS_ERR(clk_cs)) {
+                pr_err("ERROR: timer input clock not found\n");
+                BUG();
+        }
+
+        clksel = __raw_readl(timer_baseaddr + 4 + TTC_CLK_CNTRL_OFFSET);
+        clksel = !!(clksel & TTC_CLK_CNTRL_CSRC_MASK);
+        clk_ce = of_clk_get(timer, clksel);
+        if (IS_ERR(clk_ce)) {
                 pr_err("ERROR: timer input clock not found\n");
                 BUG();
         }
 
-        ttc_setup_clocksource(clk, timer_baseaddr);
-        ttc_setup_clockevent(clk, timer_baseaddr + 4, irq);
+        ttc_setup_clocksource(clk_cs, timer_baseaddr);
+        ttc_setup_clockevent(clk_ce, timer_baseaddr + 4, irq);
 
         pr_info("%s #0 at %p, irq=%d\n", timer->name, timer_baseaddr, irq);
 }
diff --git a/drivers/cpufreq/acpi-cpufreq.c b/drivers/cpufreq/acpi-cpufreq.c
index 11b8b4b54ceb..edc089e9d0c4 100644
--- a/drivers/cpufreq/acpi-cpufreq.c
+++ b/drivers/cpufreq/acpi-cpufreq.c
@@ -347,11 +347,11 @@ static u32 get_cur_val(const struct cpumask *mask)
         switch (per_cpu(acfreq_data, cpumask_first(mask))->cpu_feature) {
         case SYSTEM_INTEL_MSR_CAPABLE:
                 cmd.type = SYSTEM_INTEL_MSR_CAPABLE;
-                cmd.addr.msr.reg = MSR_IA32_PERF_STATUS;
+                cmd.addr.msr.reg = MSR_IA32_PERF_CTL;
                 break;
         case SYSTEM_AMD_MSR_CAPABLE:
                 cmd.type = SYSTEM_AMD_MSR_CAPABLE;
-                cmd.addr.msr.reg = MSR_AMD_PERF_STATUS;
+                cmd.addr.msr.reg = MSR_AMD_PERF_CTL;
                 break;
         case SYSTEM_IO_CAPABLE:
                 cmd.type = SYSTEM_IO_CAPABLE;
diff --git a/drivers/cpufreq/cpufreq-cpu0.c b/drivers/cpufreq/cpufreq-cpu0.c
index a64eb8b70444..ad1fde277661 100644
--- a/drivers/cpufreq/cpufreq-cpu0.c
+++ b/drivers/cpufreq/cpufreq-cpu0.c
@@ -45,7 +45,7 @@ static int cpu0_set_target(struct cpufreq_policy *policy,
         struct cpufreq_freqs freqs;
         struct opp *opp;
         unsigned long volt = 0, volt_old = 0, tol = 0;
-        long freq_Hz;
+        long freq_Hz, freq_exact;
         unsigned int index;
         int ret;
 
@@ -60,6 +60,7 @@ static int cpu0_set_target(struct cpufreq_policy *policy,
         freq_Hz = clk_round_rate(cpu_clk, freq_table[index].frequency * 1000);
         if (freq_Hz < 0)
                 freq_Hz = freq_table[index].frequency * 1000;
+        freq_exact = freq_Hz;
         freqs.new = freq_Hz / 1000;
         freqs.old = clk_get_rate(cpu_clk) / 1000;
 
@@ -98,7 +99,7 @@ static int cpu0_set_target(struct cpufreq_policy *policy,
                 }
         }
 
-        ret = clk_set_rate(cpu_clk, freqs.new * 1000);
+        ret = clk_set_rate(cpu_clk, freq_exact);
         if (ret) {
                 pr_err("failed to set clock rate: %d\n", ret);
                 if (cpu_reg)
diff --git a/drivers/cpufreq/cpufreq_governor.c b/drivers/cpufreq/cpufreq_governor.c
index 5af40ad82d23..dc9b72e25c1a 100644
--- a/drivers/cpufreq/cpufreq_governor.c
+++ b/drivers/cpufreq/cpufreq_governor.c
@@ -26,6 +26,7 @@
 #include <linux/tick.h>
 #include <linux/types.h>
 #include <linux/workqueue.h>
+#include <linux/cpu.h>
 
 #include "cpufreq_governor.h"
 
@@ -180,8 +181,10 @@ void gov_queue_work(struct dbs_data *dbs_data, struct cpufreq_policy *policy,
         if (!all_cpus) {
                 __gov_queue_work(smp_processor_id(), dbs_data, delay);
         } else {
+                get_online_cpus();
                 for_each_cpu(i, policy->cpus)
                         __gov_queue_work(i, dbs_data, delay);
+                put_online_cpus();
         }
 }
 EXPORT_SYMBOL_GPL(gov_queue_work);
diff --git a/drivers/cpuidle/cpuidle-calxeda.c b/drivers/cpuidle/cpuidle-calxeda.c
index 223379169cb0..0e6e408c0a63 100644
--- a/drivers/cpuidle/cpuidle-calxeda.c
+++ b/drivers/cpuidle/cpuidle-calxeda.c
@@ -37,20 +37,6 @@
 extern void highbank_set_cpu_jump(int cpu, void *jump_addr);
 extern void *scu_base_addr;
 
-static inline unsigned int get_auxcr(void)
-{
-        unsigned int val;
-        asm("mrc p15, 0, %0, c1, c0, 1  @ get AUXCR" : "=r" (val) : : "cc");
-        return val;
-}
-
-static inline void set_auxcr(unsigned int val)
-{
-        asm volatile("mcr p15, 0, %0, c1, c0, 1 @ set AUXCR"
-          : : "r" (val) : "cc");
-        isb();
-}
-
 static noinline void calxeda_idle_restore(void)
 {
         set_cr(get_cr() | CR_C);
diff --git a/drivers/crypto/caam/caamalg.c b/drivers/crypto/caam/caamalg.c
index 765fdf5ce579..bf416a8391a7 100644
--- a/drivers/crypto/caam/caamalg.c
+++ b/drivers/crypto/caam/caamalg.c
@@ -1154,7 +1154,7 @@ static struct aead_edesc *aead_edesc_alloc(struct aead_request *req,
                 dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
 
         sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
-                                 DMA_BIDIRECTIONAL, assoc_chained);
+                                 DMA_TO_DEVICE, assoc_chained);
         if (likely(req->src == req->dst)) {
                 sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
                                          DMA_BIDIRECTIONAL, src_chained);
@@ -1336,7 +1336,7 @@ static struct aead_edesc *aead_giv_edesc_alloc(struct aead_givcrypt_request
                 dst_nents = sg_count(req->dst, req->cryptlen, &dst_chained);
 
         sgc = dma_map_sg_chained(jrdev, req->assoc, assoc_nents ? : 1,
-                                 DMA_BIDIRECTIONAL, assoc_chained);
+                                 DMA_TO_DEVICE, assoc_chained);
         if (likely(req->src == req->dst)) {
                 sgc = dma_map_sg_chained(jrdev, req->src, src_nents ? : 1,
                                          DMA_BIDIRECTIONAL, src_chained);
diff --git a/drivers/crypto/sahara.c b/drivers/crypto/sahara.c
index a97bb6c1596c..c3dc1c04a5df 100644
--- a/drivers/crypto/sahara.c
+++ b/drivers/crypto/sahara.c
@@ -863,7 +863,7 @@ static struct of_device_id sahara_dt_ids[] = {
         { .compatible = "fsl,imx27-sahara" },
         { /* sentinel */ }
 };
-MODULE_DEVICE_TABLE(platform, sahara_dt_ids);
+MODULE_DEVICE_TABLE(of, sahara_dt_ids);
 
 static int sahara_probe(struct platform_device *pdev)
 {
diff --git a/drivers/dma/coh901318.c b/drivers/dma/coh901318.c
index 3b23061cdb41..9bfaddd57ef1 100644
--- a/drivers/dma/coh901318.c
+++ b/drivers/dma/coh901318.c
@@ -22,6 +22,7 @@
 #include <linux/uaccess.h>
 #include <linux/debugfs.h>
 #include <linux/platform_data/dma-coh901318.h>
+#include <linux/of_dma.h>
 
 #include "coh901318.h"
 #include "dmaengine.h"
@@ -1788,6 +1789,35 @@ bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
 }
 EXPORT_SYMBOL(coh901318_filter_id);
 
+struct coh901318_filter_args {
+        struct coh901318_base *base;
+        unsigned int ch_nr;
+};
+
+static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
+{
+        struct coh901318_filter_args *args = data;
+
+        if (&args->base->dma_slave == chan->device &&
+            args->ch_nr == to_coh901318_chan(chan)->id)
+                return true;
+
+        return false;
+}
+
+static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
+                                        struct of_dma *ofdma)
+{
+        struct coh901318_filter_args args = {
+                .base = ofdma->of_dma_data,
+                .ch_nr = dma_spec->args[0],
+        };
+        dma_cap_mask_t cap;
+        dma_cap_zero(cap);
+        dma_cap_set(DMA_SLAVE, cap);
+
+        return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
+}
 /*
  * DMA channel allocation
  */
@@ -2735,12 +2765,19 @@ static int __init coh901318_probe(struct platform_device *pdev)
         if (err)
                 goto err_register_memcpy;
 
+        err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
+                                         base);
+        if (err)
+                goto err_register_of_dma;
+
         platform_set_drvdata(pdev, base);
         dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%08x\n",
                 (u32) base->virtbase);
 
         return err;
 
+ err_register_of_dma:
+        dma_async_device_unregister(&base->dma_memcpy);
  err_register_memcpy:
         dma_async_device_unregister(&base->dma_slave);
  err_register_slave:
@@ -2752,17 +2789,23 @@ static int coh901318_remove(struct platform_device *pdev)
 {
         struct coh901318_base *base = platform_get_drvdata(pdev);
 
+        of_dma_controller_free(pdev->dev.of_node);
         dma_async_device_unregister(&base->dma_memcpy);
         dma_async_device_unregister(&base->dma_slave);
         coh901318_pool_destroy(&base->pool);
         return 0;
 }
 
+static const struct of_device_id coh901318_dt_match[] = {
+        { .compatible = "stericsson,coh901318" },
+        {},
+};
 
 static struct platform_driver coh901318_driver = {
         .remove = coh901318_remove,
         .driver = {
                 .name   = "coh901318",
+                .of_match_table = coh901318_dt_match,
         },
 };
 
diff --git a/drivers/dma/dmatest.c b/drivers/dma/dmatest.c
index d8ce4ecfef18..e88ded2c8d2f 100644
--- a/drivers/dma/dmatest.c
+++ b/drivers/dma/dmatest.c
@@ -716,8 +716,7 @@ static int dmatest_func(void *data)
                 }
                 dma_async_issue_pending(chan);
 
-                wait_event_freezable_timeout(done_wait,
-                                             done.done || kthread_should_stop(),
+                wait_event_freezable_timeout(done_wait, done.done,
                                              msecs_to_jiffies(params->timeout));
 
                 status = dma_async_is_tx_complete(chan, cookie, NULL, NULL);
@@ -997,7 +996,6 @@ static void stop_threaded_test(struct dmatest_info *info)
 static int __restart_threaded_test(struct dmatest_info *info, bool run)
 {
         struct dmatest_params *params = &info->params;
-        int ret;
 
         /* Stop any running test first */
         __stop_threaded_test(info);
@@ -1012,13 +1010,23 @@ static int __restart_threaded_test(struct dmatest_info *info, bool run)
         memcpy(params, &info->dbgfs_params, sizeof(*params));
 
         /* Run test with new parameters */
-        ret = __run_threaded_test(info);
-        if (ret) {
-                __stop_threaded_test(info);
-                pr_err("dmatest: Can't run test\n");
+        return __run_threaded_test(info);
+}
+
+static bool __is_threaded_test_run(struct dmatest_info *info)
+{
+        struct dmatest_chan *dtc;
+
+        list_for_each_entry(dtc, &info->channels, node) {
+                struct dmatest_thread *thread;
+
+                list_for_each_entry(thread, &dtc->threads, node) {
+                        if (!thread->done)
+                                return true;
+                }
         }
 
-        return ret;
+        return false;
 }
 
 static ssize_t dtf_write_string(void *to, size_t available, loff_t *ppos,
@@ -1091,22 +1099,10 @@ static ssize_t dtf_read_run(struct file *file, char __user *user_buf,
 {
         struct dmatest_info *info = file->private_data;
         char buf[3];
-        struct dmatest_chan *dtc;
-        bool alive = false;
 
         mutex_lock(&info->lock);
-        list_for_each_entry(dtc, &info->channels, node) {
-                struct dmatest_thread *thread;
-
-                list_for_each_entry(thread, &dtc->threads, node) {
-                        if (!thread->done) {
-                                alive = true;
-                                break;
-                        }
-                }
-        }
 
-        if (alive) {
+        if (__is_threaded_test_run(info)) {
                 buf[0] = 'Y';
         } else {
                 __stop_threaded_test(info);
@@ -1132,7 +1128,12 @@ static ssize_t dtf_write_run(struct file *file, const char __user *user_buf,
 
         if (strtobool(buf, &bv) == 0) {
                 mutex_lock(&info->lock);
-                ret = __restart_threaded_test(info, bv);
+
+                if (__is_threaded_test_run(info))
+                        ret = -EBUSY;
+                else
+                        ret = __restart_threaded_test(info, bv);
+
                 mutex_unlock(&info->lock);
         }
 
diff --git a/drivers/dma/edma.c b/drivers/dma/edma.c
index cd7e3280fadd..5f3e532436ee 100644
--- a/drivers/dma/edma.c
+++ b/drivers/dma/edma.c
@@ -24,7 +24,7 @@
 #include <linux/slab.h>
 #include <linux/spinlock.h>
 
-#include <mach/edma.h>
+#include <linux/platform_data/edma.h>
 
 #include "dmaengine.h"
 #include "virt-dma.h"
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index 1734feec47b1..71bf4ec300ea 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -1566,10 +1566,12 @@ static void dma_tc_handle(struct d40_chan *d40c)
                         return;
                 }
 
-                if (d40_queue_start(d40c) == NULL)
+                if (d40_queue_start(d40c) == NULL) {
                         d40c->busy = false;
-                pm_runtime_mark_last_busy(d40c->base->dev);
-                pm_runtime_put_autosuspend(d40c->base->dev);
+
+                        pm_runtime_mark_last_busy(d40c->base->dev);
+                        pm_runtime_put_autosuspend(d40c->base->dev);
+                }
 
                 d40_desc_remove(d40d);
                 d40_desc_done(d40c, d40d);
diff --git a/drivers/firmware/efi/efivars.c b/drivers/firmware/efi/efivars.c
index b623c599e572..8bd1bb6dbe47 100644
--- a/drivers/firmware/efi/efivars.c
+++ b/drivers/firmware/efi/efivars.c
@@ -523,13 +523,11 @@ static void efivar_update_sysfs_entries(struct work_struct *work)
         struct efivar_entry *entry;
         int err;
 
-        entry = kzalloc(sizeof(*entry), GFP_KERNEL);
-        if (!entry)
-                return;
-
         /* Add new sysfs entries */
         while (1) {
-                memset(entry, 0, sizeof(*entry));
+                entry = kzalloc(sizeof(*entry), GFP_KERNEL);
+                if (!entry)
+                        return;
 
                 err = efivar_init(efivar_update_sysfs_entry, entry,
                                   true, false, &efivar_sysfs_list);
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 573c449c49b9..ec1dcdca5b8a 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -109,8 +109,11 @@ config GPIO_MAX730X
 comment "Memory mapped GPIO drivers:"
 
 config GPIO_CLPS711X
-        def_bool y
+        tristate "CLPS711X GPIO support"
         depends on ARCH_CLPS711X
+        select GPIO_GENERIC
+        help
+          Say yes here to support GPIO on CLPS711X SoCs.
 
 config GPIO_GENERIC_PLATFORM
         tristate "Generic memory-mapped GPIO controller support (MMIO platform device)"
@@ -209,6 +212,13 @@ config GPIO_RCAR
         help
           Say yes here to support GPIO on Renesas R-Car SoCs.
 
+config GPIO_SAMSUNG
+        bool
+        depends on PLAT_SAMSUNG
+        help
+          Legacy GPIO support. Use only for platforms without support for
+          pinctrl.
+
 config GPIO_SPEAR_SPICS
         bool "ST SPEAr13xx SPI Chip Select as GPIO support"
         depends on PLAT_SPEAR
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 0cb2d656ad16..ef3e983a2f1e 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -59,7 +59,7 @@ obj-$(CONFIG_GPIO_PXA)		+= gpio-pxa.o
 obj-$(CONFIG_GPIO_RC5T583)      += gpio-rc5t583.o
 obj-$(CONFIG_GPIO_RDC321X)      += gpio-rdc321x.o
 obj-$(CONFIG_GPIO_RCAR)         += gpio-rcar.o
-obj-$(CONFIG_PLAT_SAMSUNG)      += gpio-samsung.o
+obj-$(CONFIG_GPIO_SAMSUNG)      += gpio-samsung.o
 obj-$(CONFIG_ARCH_SA1100)       += gpio-sa1100.o
 obj-$(CONFIG_GPIO_SCH)          += gpio-sch.o
 obj-$(CONFIG_GPIO_SODAVILLE)    += gpio-sodaville.o
diff --git a/drivers/gpio/gpio-clps711x.c b/drivers/gpio/gpio-clps711x.c
index ce63b75b13f5..0edaf2ce9266 100644
--- a/drivers/gpio/gpio-clps711x.c
+++ b/drivers/gpio/gpio-clps711x.c
@@ -1,7 +1,7 @@
 /*
  *  CLPS711X GPIO driver
  *
- *  Copyright (C) 2012 Alexander Shiyan <shc_work@mail.ru>
+ *  Copyright (C) 2012,2013 Alexander Shiyan <shc_work@mail.ru>
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -9,191 +9,91 @@
  * (at your option) any later version.
  */
 
-#include <linux/io.h>
-#include <linux/slab.h>
+#include <linux/err.h>
 #include <linux/gpio.h>
 #include <linux/module.h>
-#include <linux/spinlock.h>
+#include <linux/basic_mmio_gpio.h>
 #include <linux/platform_device.h>
 
-#include <mach/hardware.h>
-
-#define CLPS711X_GPIO_PORTS     5
-#define CLPS711X_GPIO_NAME      "gpio-clps711x"
-
-struct clps711x_gpio {
-        struct gpio_chip        chip[CLPS711X_GPIO_PORTS];
-        spinlock_t              lock;
-};
-
-static void __iomem *clps711x_ports[] = {
-        CLPS711X_VIRT_BASE + PADR,
-        CLPS711X_VIRT_BASE + PBDR,
-        CLPS711X_VIRT_BASE + PCDR,
-        CLPS711X_VIRT_BASE + PDDR,
-        CLPS711X_VIRT_BASE + PEDR,
-};
-
-static void __iomem *clps711x_pdirs[] = {
-        CLPS711X_VIRT_BASE + PADDR,
-        CLPS711X_VIRT_BASE + PBDDR,
-        CLPS711X_VIRT_BASE + PCDDR,
-        CLPS711X_VIRT_BASE + PDDDR,
-        CLPS711X_VIRT_BASE + PEDDR,
-};
-
-#define clps711x_port(x)        clps711x_ports[x->base / 8]
-#define clps711x_pdir(x)        clps711x_pdirs[x->base / 8]
-
-static int gpio_clps711x_get(struct gpio_chip *chip, unsigned offset)
+static int clps711x_gpio_probe(struct platform_device *pdev)
 {
-        return !!(readb(clps711x_port(chip)) & (1 << offset));
-}
+        struct device_node *np = pdev->dev.of_node;
+        void __iomem *dat, *dir;
+        struct bgpio_chip *bgc;
+        struct resource *res;
+        int err, id = np ? of_alias_get_id(np, "gpio") : pdev->id;
 
-static void gpio_clps711x_set(struct gpio_chip *chip, unsigned offset,
-                              int value)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-}
-
-static int gpio_clps711x_dir_in(struct gpio_chip *chip, unsigned offset)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+        if ((id < 0) || (id > 4))
+                return -ENODEV;
 
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) & ~(1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
+        bgc = devm_kzalloc(&pdev->dev, sizeof(*bgc), GFP_KERNEL);
+        if (!bgc)
+                return -ENOMEM;
 
-        return 0;
-}
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+        dat = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(dat))
+                return PTR_ERR(dat);
+
+        res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        dir = devm_ioremap_resource(&pdev->dev, res);
+        if (IS_ERR(dir))
+                return PTR_ERR(dir);
+
+        switch (id) {
+        case 3:
+                /* PORTD is inverted logic for direction register */
+                err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
+                                 NULL, dir, 0);
+                break;
+        default:
+                err = bgpio_init(bgc, &pdev->dev, 1, dat, NULL, NULL,
+                                 dir, NULL, 0);
+                break;
+        }
 
-static int gpio_clps711x_dir_out(struct gpio_chip *chip, unsigned offset,
-                                 int value)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) | (1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-
-        return 0;
-}
+        if (err)
+                return err;
 
-static int gpio_clps711x_dir_in_inv(struct gpio_chip *chip, unsigned offset)
-{
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
+        switch (id) {
+        case 4:
+                /* PORTE is 3 lines only */
+                bgc->gc.ngpio = 3;
+                break;
+        default:
+                break;
+        }
 
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) | (1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
+        bgc->gc.base = id * 8;
+        platform_set_drvdata(pdev, bgc);
 
-        return 0;
+        return gpiochip_add(&bgc->gc);
 }
 
-static int gpio_clps711x_dir_out_inv(struct gpio_chip *chip, unsigned offset,
-                                     int value)
+static int clps711x_gpio_remove(struct platform_device *pdev)
 {
-        int tmp;
-        unsigned long flags;
-        struct clps711x_gpio *gpio = dev_get_drvdata(chip->dev);
-
-        spin_lock_irqsave(&gpio->lock, flags);
-        tmp = readb(clps711x_pdir(chip)) & ~(1 << offset);
-        writeb(tmp, clps711x_pdir(chip));
-        tmp = readb(clps711x_port(chip)) & ~(1 << offset);
-        if (value)
-                tmp |= 1 << offset;
-        writeb(tmp, clps711x_port(chip));
-        spin_unlock_irqrestore(&gpio->lock, flags);
-
-        return 0;
+        struct bgpio_chip *bgc = platform_get_drvdata(pdev);
+
+        return bgpio_remove(bgc);
 }
 
-static struct {
-        char    *name;
-        int     nr;
-        int     inv_dir;
-} clps711x_gpio_ports[] __initconst = {
-        { "PORTA", 8, 0, },
-        { "PORTB", 8, 0, },
-        { "PORTC", 8, 0, },
-        { "PORTD", 8, 1, },
-        { "PORTE", 3, 0, },
+static const struct of_device_id clps711x_gpio_ids[] = {
+        { .compatible = "cirrus,clps711x-gpio" },
+        { }
 };
+MODULE_DEVICE_TABLE(of, clps711x_gpio_ids);
+
+static struct platform_driver clps711x_gpio_driver = {
+        .driver = {
+                .name           = "clps711x-gpio",
+                .owner          = THIS_MODULE,
+                .of_match_table = of_match_ptr(clps711x_gpio_ids),
+        },
+        .probe  = clps711x_gpio_probe,
+        .remove = clps711x_gpio_remove,
+};
+module_platform_driver(clps711x_gpio_driver);
 
-static int __init gpio_clps711x_init(void)
-{
-        int i;
-        struct platform_device *pdev;
-        struct clps711x_gpio *gpio;
-
-        pdev = platform_device_alloc(CLPS711X_GPIO_NAME, 0);
-        if (!pdev) {
-                pr_err("Cannot create platform device: %s\n",
-                       CLPS711X_GPIO_NAME);
-                return -ENOMEM;
-        }
-
-        platform_device_add(pdev);
-
-        gpio = devm_kzalloc(&pdev->dev, sizeof(struct clps711x_gpio),
-                            GFP_KERNEL);
-        if (!gpio) {
-                dev_err(&pdev->dev, "GPIO allocating memory error\n");
-                platform_device_unregister(pdev);
-                return -ENOMEM;
-        }
-
-        platform_set_drvdata(pdev, gpio);
-
-        spin_lock_init(&gpio->lock);
-
-        for (i = 0; i < CLPS711X_GPIO_PORTS; i++) {
-                gpio->chip[i].owner             = THIS_MODULE;
-                gpio->chip[i].dev               = &pdev->dev;
-                gpio->chip[i].label             = clps711x_gpio_ports[i].name;
-                gpio->chip[i].base              = i * 8;
-                gpio->chip[i].ngpio             = clps711x_gpio_ports[i].nr;
-                gpio->chip[i].get               = gpio_clps711x_get;
-                gpio->chip[i].set               = gpio_clps711x_set;
-                if (!clps711x_gpio_ports[i].inv_dir) {
-                        gpio->chip[i].direction_input = gpio_clps711x_dir_in;
-                        gpio->chip[i].direction_output = gpio_clps711x_dir_out;
-                } else {
-                        gpio->chip[i].direction_input = gpio_clps711x_dir_in_inv;
-                        gpio->chip[i].direction_output = gpio_clps711x_dir_out_inv;
-                }
-                WARN_ON(gpiochip_add(&gpio->chip[i]));
-        }
-
-        dev_info(&pdev->dev, "GPIO driver initialized\n");
-
-        return 0;
-}
-arch_initcall(gpio_clps711x_init);
-
-MODULE_LICENSE("GPL v2");
+MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>");
 MODULE_DESCRIPTION("CLPS711X GPIO driver");
diff --git a/drivers/gpio/gpio-rcar.c b/drivers/gpio/gpio-rcar.c
index b4ca450947b8..d173d56dbb8c 100644
--- a/drivers/gpio/gpio-rcar.c
+++ b/drivers/gpio/gpio-rcar.c
@@ -49,6 +49,7 @@ struct gpio_rcar_priv {
 #define POSNEG 0x20
 #define EDGLEVEL 0x24
 #define FILONOFF 0x28
+#define BOTHEDGE 0x4c
 
 static inline u32 gpio_rcar_read(struct gpio_rcar_priv *p, int offs)
 {
@@ -91,7 +92,8 @@ static void gpio_rcar_irq_enable(struct irq_data *d)
 static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
                                                   unsigned int hwirq,
                                                   bool active_high_rising_edge,
-                                                  bool level_trigger)
+                                                  bool level_trigger,
+                                                  bool both)
 {
         unsigned long flags;
 
@@ -108,6 +110,10 @@ static void gpio_rcar_config_interrupt_input_mode(struct gpio_rcar_priv *p,
         /* Configure edge or level trigger in EDGLEVEL */
         gpio_rcar_modify_bit(p, EDGLEVEL, hwirq, !level_trigger);
 
+        /* Select one edge or both edges in BOTHEDGE */
+        if (p->config.has_both_edge_trigger)
+                gpio_rcar_modify_bit(p, BOTHEDGE, hwirq, both);
+
         /* Select "Interrupt Input Mode" in IOINTSEL */
         gpio_rcar_modify_bit(p, IOINTSEL, hwirq, true);
 
@@ -127,16 +133,26 @@ static int gpio_rcar_irq_set_type(struct irq_data *d, unsigned int type)
 
         switch (type & IRQ_TYPE_SENSE_MASK) {
         case IRQ_TYPE_LEVEL_HIGH:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, true,
+                                                      false);
                 break;
         case IRQ_TYPE_LEVEL_LOW:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, true,
+                                                      false);
                 break;
         case IRQ_TYPE_EDGE_RISING:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+                                                      false);
                 break;
         case IRQ_TYPE_EDGE_FALLING:
-                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false);
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, false, false,
+                                                      false);
+                break;
+        case IRQ_TYPE_EDGE_BOTH:
+                if (!p->config.has_both_edge_trigger)
+                        return -EINVAL;
+                gpio_rcar_config_interrupt_input_mode(p, hwirq, true, false,
+                                                      true);
                 break;
         default:
                 return -EINVAL;
@@ -333,7 +349,7 @@ static int gpio_rcar_probe(struct platform_device *pdev)
         }
 
         if (devm_request_irq(&pdev->dev, irq->start,
-                             gpio_rcar_irq_handler, 0, name, p)) {
+                             gpio_rcar_irq_handler, IRQF_SHARED, name, p)) {
                 dev_err(&pdev->dev, "failed to request IRQ\n");
                 ret = -ENOENT;
                 goto err1;
diff --git a/drivers/gpu/drm/drm_irq.c b/drivers/gpu/drm/drm_irq.c
index a6a8643a6a77..8bcce7866d36 100644
--- a/drivers/gpu/drm/drm_irq.c
+++ b/drivers/gpu/drm/drm_irq.c
@@ -1054,7 +1054,7 @@ EXPORT_SYMBOL(drm_vblank_off);
  */
 void drm_vblank_pre_modeset(struct drm_device *dev, int crtc)
 {
-        /* vblank is not initialized (IRQ not installed ?) */
+        /* vblank is not initialized (IRQ not installed ?), or has been freed */
         if (!dev->num_crtcs)
                 return;
         /*
@@ -1076,6 +1076,10 @@ void drm_vblank_post_modeset(struct drm_device *dev, int crtc)
 {
         unsigned long irqflags;
 
+        /* vblank is not initialized (IRQ not installed ?), or has been freed */
+        if (!dev->num_crtcs)
+                return;
+
         if (dev->vblank_inmodeset[crtc]) {
                 spin_lock_irqsave(&dev->vbl_lock, irqflags);
                 dev->vblank_disable_allowed = 1;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_crtc.c b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
index e8894bc9e6d5..c200e4d71e3d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_crtc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_crtc.c
@@ -48,6 +48,8 @@ struct exynos_drm_crtc {
         unsigned int                    pipe;
         unsigned int                    dpms;
         enum exynos_crtc_mode           mode;
+        wait_queue_head_t               pending_flip_queue;
+        atomic_t                        pending_flip;
 };
 
 static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
@@ -61,6 +63,13 @@ static void exynos_drm_crtc_dpms(struct drm_crtc *crtc, int mode)
                 return;
         }
 
+        if (mode > DRM_MODE_DPMS_ON) {
+                /* wait for the completion of page flip. */
+                wait_event(exynos_crtc->pending_flip_queue,
+                                atomic_read(&exynos_crtc->pending_flip) == 0);
+                drm_vblank_off(crtc->dev, exynos_crtc->pipe);
+        }
+
         exynos_drm_fn_encoder(crtc, &mode, exynos_drm_encoder_crtc_dpms);
         exynos_crtc->dpms = mode;
 }
@@ -217,7 +226,6 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
                 ret = drm_vblank_get(dev, exynos_crtc->pipe);
                 if (ret) {
                         DRM_DEBUG("failed to acquire vblank counter\n");
-                        list_del(&event->base.link);
 
                         goto out;
                 }
@@ -225,6 +233,7 @@ static int exynos_drm_crtc_page_flip(struct drm_crtc *crtc,
                 spin_lock_irq(&dev->event_lock);
                 list_add_tail(&event->base.link,
                                 &dev_priv->pageflip_event_list);
+                atomic_set(&exynos_crtc->pending_flip, 1);
                 spin_unlock_irq(&dev->event_lock);
 
                 crtc->fb = fb;
@@ -344,6 +353,8 @@ int exynos_drm_crtc_create(struct drm_device *dev, unsigned int nr)
 
         exynos_crtc->pipe = nr;
         exynos_crtc->dpms = DRM_MODE_DPMS_OFF;
+        init_waitqueue_head(&exynos_crtc->pending_flip_queue);
+        atomic_set(&exynos_crtc->pending_flip, 0);
         exynos_crtc->plane = exynos_plane_init(dev, 1 << nr, true);
         if (!exynos_crtc->plane) {
                 kfree(exynos_crtc);
@@ -398,7 +409,8 @@ void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int crtc)
 {
         struct exynos_drm_private *dev_priv = dev->dev_private;
         struct drm_pending_vblank_event *e, *t;
-        struct timeval now;
+        struct drm_crtc *drm_crtc = dev_priv->crtc[crtc];
+        struct exynos_drm_crtc *exynos_crtc = to_exynos_crtc(drm_crtc);
         unsigned long flags;
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
@@ -411,14 +423,11 @@ void exynos_drm_crtc_finish_pageflip(struct drm_device *dev, int crtc)
                 if (crtc != e->pipe)
                         continue;
 
-                do_gettimeofday(&now);
-                e->event.sequence = 0;
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-
-                list_move_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
+                list_del(&e->base.link);
+                drm_send_vblank_event(dev, -1, e);
                 drm_vblank_put(dev, crtc);
+                atomic_set(&exynos_crtc->pending_flip, 0);
+                wake_up(&exynos_crtc->pending_flip_queue);
         }
 
         spin_unlock_irqrestore(&dev->event_lock, flags);
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
index 68f0045f86b8..8f007aaeffc3 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fbdev.c
@@ -182,7 +182,7 @@ static int exynos_drm_fbdev_create(struct drm_fb_helper *helper,
 
         helper->fb = exynos_drm_framebuffer_init(dev, &mode_cmd,
                         &exynos_gem_obj->base);
-        if (IS_ERR_OR_NULL(helper->fb)) {
+        if (IS_ERR(helper->fb)) {
                 DRM_ERROR("failed to create drm framebuffer.\n");
                 ret = PTR_ERR(helper->fb);
                 goto err_destroy_gem;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimc.c b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
index 773f583fa964..4a1616a18ab7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimc.c
@@ -12,9 +12,9 @@
  *
  */
 #include <linux/kernel.h>
-#include <linux/mfd/syscon.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/mfd/syscon.h>
 #include <linux/regmap.h>
 #include <linux/clk.h>
 #include <linux/pm_runtime.h>
@@ -1845,7 +1845,7 @@ static int fimc_probe(struct platform_device *pdev)
         }
 
         ctx->irq = res->start;
-        ret = request_threaded_irq(ctx->irq, NULL, fimc_irq_handler,
+        ret = devm_request_threaded_irq(dev, ctx->irq, NULL, fimc_irq_handler,
                 IRQF_ONESHOT, "drm_fimc", ctx);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq.\n");
@@ -1854,7 +1854,7 @@ static int fimc_probe(struct platform_device *pdev)
 
         ret = fimc_setup_clocks(ctx);
         if (ret < 0)
-                goto err_free_irq;
+                return ret;
 
         ippdrv = &ctx->ippdrv;
         ippdrv->ops[EXYNOS_DRM_OPS_SRC] = &fimc_src_ops;
@@ -1884,7 +1884,7 @@ static int fimc_probe(struct platform_device *pdev)
                 goto err_pm_dis;
         }
 
-        dev_info(&pdev->dev, "drm fimc registered successfully.\n");
+        dev_info(dev, "drm fimc registered successfully.\n");
 
         return 0;
 
@@ -1892,8 +1892,6 @@ err_pm_dis:
         pm_runtime_disable(dev);
 err_put_clk:
         fimc_put_clocks(ctx);
-err_free_irq:
-        free_irq(ctx->irq, ctx);
 
         return ret;
 }
@@ -1911,8 +1909,6 @@ static int fimc_remove(struct platform_device *pdev)
         pm_runtime_set_suspended(dev);
         pm_runtime_disable(dev);
 
-        free_irq(ctx->irq, ctx);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
index 746b282b343a..97c61dbffd82 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c
@@ -885,7 +885,7 @@ static int fimd_probe(struct platform_device *pdev)
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
 
-        if (pdev->dev.of_node) {
+        if (dev->of_node) {
                 pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
                 if (!pdata) {
                         DRM_ERROR("memory allocation for pdata failed\n");
@@ -899,7 +899,7 @@ static int fimd_probe(struct platform_device *pdev)
                         return ret;
                 }
         } else {
-                pdata = pdev->dev.platform_data;
+                pdata = dev->platform_data;
                 if (!pdata) {
                         DRM_ERROR("no platform data specified\n");
                         return -EINVAL;
@@ -912,7 +912,7 @@ static int fimd_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx)
                 return -ENOMEM;
 
@@ -930,7 +930,7 @@ static int fimd_probe(struct platform_device *pdev)
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
-        ctx->regs = devm_ioremap_resource(&pdev->dev, res);
+        ctx->regs = devm_ioremap_resource(dev, res);
         if (IS_ERR(ctx->regs))
                 return PTR_ERR(ctx->regs);
 
@@ -942,7 +942,7 @@ static int fimd_probe(struct platform_device *pdev)
 
         ctx->irq = res->start;
 
-        ret = devm_request_irq(&pdev->dev, ctx->irq, fimd_irq_handler,
+        ret = devm_request_irq(dev, ctx->irq, fimd_irq_handler,
                                                         0, "drm_fimd", ctx);
         if (ret) {
                 dev_err(dev, "irq request failed.\n");
diff --git a/drivers/gpu/drm/exynos/exynos_drm_g2d.c b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
index 47a493c8a71f..af75434ee4d7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_g2d.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_g2d.c
@@ -1379,7 +1379,7 @@ static int g2d_probe(struct platform_device *pdev)
         struct exynos_drm_subdrv *subdrv;
         int ret;
 
-        g2d = devm_kzalloc(&pdev->dev, sizeof(*g2d), GFP_KERNEL);
+        g2d = devm_kzalloc(dev, sizeof(*g2d), GFP_KERNEL);
         if (!g2d) {
                 dev_err(dev, "failed to allocate driver data\n");
                 return -ENOMEM;
@@ -1417,7 +1417,7 @@ static int g2d_probe(struct platform_device *pdev)
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 
-        g2d->regs = devm_ioremap_resource(&pdev->dev, res);
+        g2d->regs = devm_ioremap_resource(dev, res);
         if (IS_ERR(g2d->regs)) {
                 ret = PTR_ERR(g2d->regs);
                 goto err_put_clk;
@@ -1430,7 +1430,7 @@ static int g2d_probe(struct platform_device *pdev)
                 goto err_put_clk;
         }
 
-        ret = devm_request_irq(&pdev->dev, g2d->irq, g2d_irq_handler, 0,
+        ret = devm_request_irq(dev, g2d->irq, g2d_irq_handler, 0,
                                                                 "drm_g2d", g2d);
         if (ret < 0) {
                 dev_err(dev, "irq request failed\n");
diff --git a/drivers/gpu/drm/exynos/exynos_drm_gsc.c b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
index 7841c3b8a20e..762f40d548b7 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_gsc.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_gsc.c
@@ -1704,7 +1704,7 @@ static int gsc_probe(struct platform_device *pdev)
         }
 
         ctx->irq = res->start;
-        ret = request_threaded_irq(ctx->irq, NULL, gsc_irq_handler,
+        ret = devm_request_threaded_irq(dev, ctx->irq, NULL, gsc_irq_handler,
                 IRQF_ONESHOT, "drm_gsc", ctx);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq.\n");
@@ -1725,7 +1725,7 @@ static int gsc_probe(struct platform_device *pdev)
         ret = gsc_init_prop_list(ippdrv);
         if (ret < 0) {
                 dev_err(dev, "failed to init property list.\n");
-                goto err_get_irq;
+                return ret;
         }
 
         DRM_DEBUG_KMS("%s:id[%d]ippdrv[0x%x]\n", __func__, ctx->id,
@@ -1743,15 +1743,12 @@ static int gsc_probe(struct platform_device *pdev)
                 goto err_ippdrv_register;
         }
 
-        dev_info(&pdev->dev, "drm gsc registered successfully.\n");
+        dev_info(dev, "drm gsc registered successfully.\n");
 
         return 0;
 
 err_ippdrv_register:
-        devm_kfree(dev, ippdrv->prop_list);
         pm_runtime_disable(dev);
-err_get_irq:
-        free_irq(ctx->irq, ctx);
         return ret;
 }
 
@@ -1761,15 +1758,12 @@ static int gsc_remove(struct platform_device *pdev)
         struct gsc_context *ctx = get_gsc_context(dev);
         struct exynos_drm_ippdrv *ippdrv = &ctx->ippdrv;
 
-        devm_kfree(dev, ippdrv->prop_list);
         exynos_drm_ippdrv_unregister(ippdrv);
         mutex_destroy(&ctx->lock);
 
         pm_runtime_set_suspended(dev);
         pm_runtime_disable(dev);
 
-        free_irq(ctx->irq, ctx);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
index ba2f0f1aa05f..437fb947e46d 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_hdmi.c
@@ -442,7 +442,7 @@ static int exynos_drm_hdmi_probe(struct platform_device *pdev)
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx) {
                 DRM_LOG_KMS("failed to alloc common hdmi context.\n");
                 return -ENOMEM;
diff --git a/drivers/gpu/drm/exynos/exynos_drm_ipp.c b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
index 29d2ad314490..be1e88463466 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_ipp.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_ipp.c
@@ -222,7 +222,7 @@ static struct exynos_drm_ippdrv *ipp_find_driver(struct ipp_context *ctx,
                 /* find ipp driver using idr */
                 ippdrv = ipp_find_obj(&ctx->ipp_idr, &ctx->ipp_lock,
                         ipp_id);
-                if (IS_ERR_OR_NULL(ippdrv)) {
+                if (IS_ERR(ippdrv)) {
                         DRM_ERROR("not found ipp%d driver.\n", ipp_id);
                         return ippdrv;
                 }
@@ -388,7 +388,7 @@ static int ipp_find_and_set_property(struct drm_exynos_ipp_property *property)
         DRM_DEBUG_KMS("%s:prop_id[%d]\n", __func__, prop_id);
 
         ippdrv = ipp_find_drv_by_handle(prop_id);
-        if (IS_ERR_OR_NULL(ippdrv)) {
+        if (IS_ERR(ippdrv)) {
                 DRM_ERROR("failed to get ipp driver.\n");
                 return -EINVAL;
         }
@@ -492,7 +492,7 @@ int exynos_drm_ipp_set_property(struct drm_device *drm_dev, void *data,
 
         /* find ipp driver using ipp id */
         ippdrv = ipp_find_driver(ctx, property);
-        if (IS_ERR_OR_NULL(ippdrv)) {
+        if (IS_ERR(ippdrv)) {
                 DRM_ERROR("failed to get ipp driver.\n");
                 return -EINVAL;
         }
@@ -521,19 +521,19 @@ int exynos_drm_ipp_set_property(struct drm_device *drm_dev, void *data,
         c_node->state = IPP_STATE_IDLE;
 
         c_node->start_work = ipp_create_cmd_work();
-        if (IS_ERR_OR_NULL(c_node->start_work)) {
+        if (IS_ERR(c_node->start_work)) {
                 DRM_ERROR("failed to create start work.\n");
                 goto err_clear;
         }
 
         c_node->stop_work = ipp_create_cmd_work();
-        if (IS_ERR_OR_NULL(c_node->stop_work)) {
+        if (IS_ERR(c_node->stop_work)) {
                 DRM_ERROR("failed to create stop work.\n");
                 goto err_free_start;
         }
 
         c_node->event_work = ipp_create_event_work();
-        if (IS_ERR_OR_NULL(c_node->event_work)) {
+        if (IS_ERR(c_node->event_work)) {
                 DRM_ERROR("failed to create event work.\n");
                 goto err_free_stop;
         }
@@ -915,7 +915,7 @@ static int ipp_queue_buf_with_run(struct device *dev,
         DRM_DEBUG_KMS("%s\n", __func__);
 
         ippdrv = ipp_find_drv_by_handle(qbuf->prop_id);
-        if (IS_ERR_OR_NULL(ippdrv)) {
+        if (IS_ERR(ippdrv)) {
                 DRM_ERROR("failed to get ipp driver.\n");
                 return -EFAULT;
         }
@@ -1909,7 +1909,7 @@ static int ipp_probe(struct platform_device *pdev)
         struct exynos_drm_subdrv *subdrv;
         int ret;
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx)
                 return -ENOMEM;
 
@@ -1963,7 +1963,7 @@ static int ipp_probe(struct platform_device *pdev)
                 goto err_cmd_workq;
         }
 
-        dev_info(&pdev->dev, "drm ipp registered successfully.\n");
+        dev_info(dev, "drm ipp registered successfully.\n");
 
         return 0;
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_rotator.c b/drivers/gpu/drm/exynos/exynos_drm_rotator.c
index 947f09f15ad1..9b6c70964d71 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_rotator.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_rotator.c
@@ -666,8 +666,8 @@ static int rotator_probe(struct platform_device *pdev)
                 return rot->irq;
         }
 
-        ret = request_threaded_irq(rot->irq, NULL, rotator_irq_handler,
-                        IRQF_ONESHOT, "drm_rotator", rot);
+        ret = devm_request_threaded_irq(dev, rot->irq, NULL,
+                        rotator_irq_handler, IRQF_ONESHOT, "drm_rotator", rot);
         if (ret < 0) {
                 dev_err(dev, "failed to request irq\n");
                 return ret;
@@ -676,8 +676,7 @@ static int rotator_probe(struct platform_device *pdev)
         rot->clock = devm_clk_get(dev, "rotator");
         if (IS_ERR(rot->clock)) {
                 dev_err(dev, "failed to get clock\n");
-                ret = PTR_ERR(rot->clock);
-                goto err_clk_get;
+                return PTR_ERR(rot->clock);
         }
 
         pm_runtime_enable(dev);
@@ -709,10 +708,7 @@ static int rotator_probe(struct platform_device *pdev)
         return 0;
 
 err_ippdrv_register:
-        devm_kfree(dev, ippdrv->prop_list);
         pm_runtime_disable(dev);
-err_clk_get:
-        free_irq(rot->irq, rot);
         return ret;
 }
 
@@ -722,13 +718,10 @@ static int rotator_remove(struct platform_device *pdev)
         struct rot_context *rot = dev_get_drvdata(dev);
         struct exynos_drm_ippdrv *ippdrv = &rot->ippdrv;
 
-        devm_kfree(dev, ippdrv->prop_list);
         exynos_drm_ippdrv_unregister(ippdrv);
 
         pm_runtime_disable(dev);
 
-        free_irq(rot->irq, rot);
-
         return 0;
 }
 
diff --git a/drivers/gpu/drm/exynos/exynos_drm_vidi.c b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
index 9504b0cd825a..24376c194a5e 100644
--- a/drivers/gpu/drm/exynos/exynos_drm_vidi.c
+++ b/drivers/gpu/drm/exynos/exynos_drm_vidi.c
@@ -594,7 +594,7 @@ static int vidi_probe(struct platform_device *pdev)
 
         DRM_DEBUG_KMS("%s\n", __FILE__);
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx)
                 return -ENOMEM;
 
@@ -612,7 +612,7 @@ static int vidi_probe(struct platform_device *pdev)
 
         platform_set_drvdata(pdev, ctx);
 
-        ret = device_create_file(&pdev->dev, &dev_attr_connection);
+        ret = device_create_file(dev, &dev_attr_connection);
         if (ret < 0)
                 DRM_INFO("failed to create connection sysfs.\n");
 
diff --git a/drivers/gpu/drm/exynos/exynos_hdmi.c b/drivers/gpu/drm/exynos/exynos_hdmi.c
index 6652597586a1..fd1426dca882 100644
--- a/drivers/gpu/drm/exynos/exynos_hdmi.c
+++ b/drivers/gpu/drm/exynos/exynos_hdmi.c
@@ -1946,14 +1946,14 @@ static int hdmi_probe(struct platform_device *pdev)
 
         DRM_DEBUG_KMS("[%d]\n", __LINE__);
 
-        if (pdev->dev.of_node) {
+        if (dev->of_node) {
                 pdata = drm_hdmi_dt_parse_pdata(dev);
                 if (IS_ERR(pdata)) {
                         DRM_ERROR("failed to parse dt\n");
                         return PTR_ERR(pdata);
                 }
         } else {
-                pdata = pdev->dev.platform_data;
+                pdata = dev->platform_data;
         }
 
         if (!pdata) {
@@ -1961,14 +1961,14 @@ static int hdmi_probe(struct platform_device *pdev)
                 return -EINVAL;
         }
 
-        drm_hdmi_ctx = devm_kzalloc(&pdev->dev, sizeof(*drm_hdmi_ctx),
+        drm_hdmi_ctx = devm_kzalloc(dev, sizeof(*drm_hdmi_ctx),
                                                                 GFP_KERNEL);
         if (!drm_hdmi_ctx) {
                 DRM_ERROR("failed to allocate common hdmi context.\n");
                 return -ENOMEM;
         }
 
-        hdata = devm_kzalloc(&pdev->dev, sizeof(struct hdmi_context),
+        hdata = devm_kzalloc(dev, sizeof(struct hdmi_context),
                                                                 GFP_KERNEL);
         if (!hdata) {
                 DRM_ERROR("out of memory\n");
@@ -1985,7 +1985,7 @@ static int hdmi_probe(struct platform_device *pdev)
         if (dev->of_node) {
                 const struct of_device_id *match;
                 match = of_match_node(of_match_ptr(hdmi_match_types),
-                                        pdev->dev.of_node);
+                                        dev->of_node);
                 if (match == NULL)
                         return -ENODEV;
                 hdata->type = (enum hdmi_type)match->data;
@@ -2005,11 +2005,11 @@ static int hdmi_probe(struct platform_device *pdev)
         }
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        hdata->regs = devm_ioremap_resource(&pdev->dev, res);
+        hdata->regs = devm_ioremap_resource(dev, res);
         if (IS_ERR(hdata->regs))
                 return PTR_ERR(hdata->regs);
 
-        ret = devm_gpio_request(&pdev->dev, hdata->hpd_gpio, "HPD");
+        ret = devm_gpio_request(dev, hdata->hpd_gpio, "HPD");
         if (ret) {
                 DRM_ERROR("failed to request HPD gpio\n");
                 return ret;
@@ -2041,7 +2041,7 @@ static int hdmi_probe(struct platform_device *pdev)
 
         hdata->hpd = gpio_get_value(hdata->hpd_gpio);
 
-        ret = request_threaded_irq(hdata->irq, NULL,
+        ret = devm_request_threaded_irq(dev, hdata->irq, NULL,
                         hdmi_irq_thread, IRQF_TRIGGER_RISING |
                         IRQF_TRIGGER_FALLING | IRQF_ONESHOT,
                         "hdmi", drm_hdmi_ctx);
@@ -2070,16 +2070,11 @@ err_ddc:
 static int hdmi_remove(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
-        struct exynos_drm_hdmi_context *ctx = platform_get_drvdata(pdev);
-        struct hdmi_context *hdata = ctx->ctx;
 
         DRM_DEBUG_KMS("[%d] %s\n", __LINE__, __func__);
 
         pm_runtime_disable(dev);
 
-        free_irq(hdata->irq, hdata);
-
-
         /* hdmiphy i2c driver */
         i2c_del_driver(&hdmiphy_driver);
         /* DDC i2c driver */
diff --git a/drivers/gpu/drm/exynos/exynos_mixer.c b/drivers/gpu/drm/exynos/exynos_mixer.c
index ec3e376b7e01..7c197d3820c5 100644
--- a/drivers/gpu/drm/exynos/exynos_mixer.c
+++ b/drivers/gpu/drm/exynos/exynos_mixer.c
@@ -1061,7 +1061,7 @@ static int mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
                 return -ENXIO;
         }
 
-        mixer_res->mixer_regs = devm_ioremap(&pdev->dev, res->start,
+        mixer_res->mixer_regs = devm_ioremap(dev, res->start,
                                                         resource_size(res));
         if (mixer_res->mixer_regs == NULL) {
                 dev_err(dev, "register mapping failed.\n");
@@ -1074,7 +1074,7 @@ static int mixer_resources_init(struct exynos_drm_hdmi_context *ctx,
                 return -ENXIO;
         }
 
-        ret = devm_request_irq(&pdev->dev, res->start, mixer_irq_handler,
+        ret = devm_request_irq(dev, res->start, mixer_irq_handler,
                                                         0, "drm_mixer", ctx);
         if (ret) {
                 dev_err(dev, "request interrupt failed.\n");
@@ -1118,7 +1118,7 @@ static int vp_resources_init(struct exynos_drm_hdmi_context *ctx,
                 return -ENXIO;
         }
 
-        mixer_res->vp_regs = devm_ioremap(&pdev->dev, res->start,
+        mixer_res->vp_regs = devm_ioremap(dev, res->start,
                                                         resource_size(res));
         if (mixer_res->vp_regs == NULL) {
                 dev_err(dev, "register mapping failed.\n");
@@ -1169,14 +1169,14 @@ static int mixer_probe(struct platform_device *pdev)
 
         dev_info(dev, "probe start\n");
 
-        drm_hdmi_ctx = devm_kzalloc(&pdev->dev, sizeof(*drm_hdmi_ctx),
+        drm_hdmi_ctx = devm_kzalloc(dev, sizeof(*drm_hdmi_ctx),
                                                                 GFP_KERNEL);
         if (!drm_hdmi_ctx) {
                 DRM_ERROR("failed to allocate common hdmi context.\n");
                 return -ENOMEM;
         }
 
-        ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
+        ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
         if (!ctx) {
                 DRM_ERROR("failed to alloc mixer context.\n");
                 return -ENOMEM;
@@ -1187,14 +1187,14 @@ static int mixer_probe(struct platform_device *pdev)
         if (dev->of_node) {
                 const struct of_device_id *match;
                 match = of_match_node(of_match_ptr(mixer_match_types),
-                                                          pdev->dev.of_node);
+                                                          dev->of_node);
                 drv = (struct mixer_drv_data *)match->data;
         } else {
                 drv = (struct mixer_drv_data *)
                         platform_get_device_id(pdev)->driver_data;
         }
 
-        ctx->dev = &pdev->dev;
+        ctx->dev = dev;
         ctx->parent_ctx = (void *)drm_hdmi_ctx;
         drm_hdmi_ctx->ctx = (void *)ctx;
         ctx->vp_enabled = drv->is_vp_enabled;
diff --git a/drivers/gpu/drm/gma500/cdv_intel_display.c b/drivers/gpu/drm/gma500/cdv_intel_display.c
index 3cfd0931fbfb..82430ad8ba62 100644
--- a/drivers/gpu/drm/gma500/cdv_intel_display.c
+++ b/drivers/gpu/drm/gma500/cdv_intel_display.c
@@ -1462,7 +1462,7 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
         size_t addr = 0;
         struct gtt_range *gt;
         struct drm_gem_object *obj;
-        int ret;
+        int ret = 0;
 
         /* if we want to turn of the cursor ignore width and height */
         if (!handle) {
@@ -1499,7 +1499,8 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
 
         if (obj->size < width * height * 4) {
                 dev_dbg(dev->dev, "buffer is to small\n");
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto unref_cursor;
         }
 
         gt = container_of(obj, struct gtt_range, gem);
@@ -1508,7 +1509,7 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
         ret = psb_gtt_pin(gt);
         if (ret) {
                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
-                return ret;
+                goto unref_cursor;
         }
 
         addr = gt->offset;      /* Or resource.start ??? */
@@ -1532,9 +1533,14 @@ static int cdv_intel_crtc_cursor_set(struct drm_crtc *crtc,
                                                         struct gtt_range, gem);
                 psb_gtt_unpin(gt);
                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
-                psb_intel_crtc->cursor_obj = obj;
         }
-        return 0;
+
+        psb_intel_crtc->cursor_obj = obj;
+        return ret;
+
+unref_cursor:
+        drm_gem_object_unreference(obj);
+        return ret;
 }
 
 static int cdv_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
@@ -1750,6 +1756,19 @@ static void cdv_intel_crtc_destroy(struct drm_crtc *crtc)
         kfree(psb_intel_crtc);
 }
 
+static void cdv_intel_crtc_disable(struct drm_crtc *crtc)
+{
+        struct gtt_range *gt;
+        struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+        crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+
+        if (crtc->fb) {
+                gt = to_psb_fb(crtc->fb)->gtt;
+                psb_gtt_unpin(gt);
+        }
+}
+
 const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
         .dpms = cdv_intel_crtc_dpms,
         .mode_fixup = cdv_intel_crtc_mode_fixup,
@@ -1757,6 +1776,7 @@ const struct drm_crtc_helper_funcs cdv_intel_helper_funcs = {
         .mode_set_base = cdv_intel_pipe_set_base,
         .prepare = cdv_intel_crtc_prepare,
         .commit = cdv_intel_crtc_commit,
+        .disable = cdv_intel_crtc_disable,
 };
 
 const struct drm_crtc_funcs cdv_intel_crtc_funcs = {
diff --git a/drivers/gpu/drm/gma500/framebuffer.c b/drivers/gpu/drm/gma500/framebuffer.c
index 1534e220097a..8b1b6d923abe 100644
--- a/drivers/gpu/drm/gma500/framebuffer.c
+++ b/drivers/gpu/drm/gma500/framebuffer.c
@@ -121,8 +121,8 @@ static int psbfb_vm_fault(struct vm_area_struct *vma, struct vm_fault *vmf)
         unsigned long address;
         int ret;
         unsigned long pfn;
-        /* FIXME: assumes fb at stolen base which may not be true */
-        unsigned long phys_addr = (unsigned long)dev_priv->stolen_base;
+        unsigned long phys_addr = (unsigned long)dev_priv->stolen_base +
+                                  psbfb->gtt->offset;
 
         page_num = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
         address = (unsigned long)vmf->virtual_address - (vmf->pgoff << PAGE_SHIFT);
diff --git a/drivers/gpu/drm/gma500/psb_intel_display.c b/drivers/gpu/drm/gma500/psb_intel_display.c
index 6e8f42b61ff6..6666493789d1 100644
--- a/drivers/gpu/drm/gma500/psb_intel_display.c
+++ b/drivers/gpu/drm/gma500/psb_intel_display.c
@@ -843,7 +843,7 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
         struct gtt_range *cursor_gt = psb_intel_crtc->cursor_gt;
         struct drm_gem_object *obj;
         void *tmp_dst, *tmp_src;
-        int ret, i, cursor_pages;
+        int ret = 0, i, cursor_pages;
 
         /* if we want to turn of the cursor ignore width and height */
         if (!handle) {
@@ -880,7 +880,8 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
 
         if (obj->size < width * height * 4) {
                 dev_dbg(dev->dev, "buffer is to small\n");
-                return -ENOMEM;
+                ret = -ENOMEM;
+                goto unref_cursor;
         }
 
         gt = container_of(obj, struct gtt_range, gem);
@@ -889,13 +890,14 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
         ret = psb_gtt_pin(gt);
         if (ret) {
                 dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
-                return ret;
+                goto unref_cursor;
         }
 
         if (dev_priv->ops->cursor_needs_phys) {
                 if (cursor_gt == NULL) {
                         dev_err(dev->dev, "No hardware cursor mem available");
-                        return -ENOMEM;
+                        ret = -ENOMEM;
+                        goto unref_cursor;
                 }
 
                 /* Prevent overflow */
@@ -936,9 +938,14 @@ static int psb_intel_crtc_cursor_set(struct drm_crtc *crtc,
                                                         struct gtt_range, gem);
                 psb_gtt_unpin(gt);
                 drm_gem_object_unreference(psb_intel_crtc->cursor_obj);
-                psb_intel_crtc->cursor_obj = obj;
         }
-        return 0;
+
+        psb_intel_crtc->cursor_obj = obj;
+        return ret;
+
+unref_cursor:
+        drm_gem_object_unreference(obj);
+        return ret;
 }
 
 static int psb_intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
@@ -1150,6 +1157,19 @@ static void psb_intel_crtc_destroy(struct drm_crtc *crtc)
         kfree(psb_intel_crtc);
 }
 
+static void psb_intel_crtc_disable(struct drm_crtc *crtc)
+{
+        struct gtt_range *gt;
+        struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
+
+        crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
+
+        if (crtc->fb) {
+                gt = to_psb_fb(crtc->fb)->gtt;
+                psb_gtt_unpin(gt);
+        }
+}
+
 const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
         .dpms = psb_intel_crtc_dpms,
         .mode_fixup = psb_intel_crtc_mode_fixup,
@@ -1157,6 +1177,7 @@ const struct drm_crtc_helper_funcs psb_intel_helper_funcs = {
         .mode_set_base = psb_intel_pipe_set_base,
         .prepare = psb_intel_crtc_prepare,
         .commit = psb_intel_crtc_commit,
+        .disable = psb_intel_crtc_disable,
 };
 
 const struct drm_crtc_funcs psb_intel_crtc_funcs = {
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 9ebe895c17d6..a2e4953b8e8d 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -364,40 +364,64 @@ static const struct pci_device_id pciidlist[] = {		/* aka */
         INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
         INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
         INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
-        INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
+        INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT3 desktop */
         INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
         INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
-        INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
+        INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT3 server */
         INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
         INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
         INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
+        INTEL_VGA_DEVICE(0x040B, &intel_haswell_d_info), /* GT1 reserved */
+        INTEL_VGA_DEVICE(0x041B, &intel_haswell_d_info), /* GT2 reserved */
+        INTEL_VGA_DEVICE(0x042B, &intel_haswell_d_info), /* GT3 reserved */
+        INTEL_VGA_DEVICE(0x040E, &intel_haswell_d_info), /* GT1 reserved */
+        INTEL_VGA_DEVICE(0x041E, &intel_haswell_d_info), /* GT2 reserved */
+        INTEL_VGA_DEVICE(0x042E, &intel_haswell_d_info), /* GT3 reserved */
         INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
         INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
-        INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
+        INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT3 desktop */
         INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
         INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
-        INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
+        INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT3 server */
         INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
         INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
-        INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
+        INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT3 mobile */
+        INTEL_VGA_DEVICE(0x0C0B, &intel_haswell_d_info), /* SDV GT1 reserved */
+        INTEL_VGA_DEVICE(0x0C1B, &intel_haswell_d_info), /* SDV GT2 reserved */
+        INTEL_VGA_DEVICE(0x0C2B, &intel_haswell_d_info), /* SDV GT3 reserved */
+        INTEL_VGA_DEVICE(0x0C0E, &intel_haswell_d_info), /* SDV GT1 reserved */
+        INTEL_VGA_DEVICE(0x0C1E, &intel_haswell_d_info), /* SDV GT2 reserved */
+        INTEL_VGA_DEVICE(0x0C2E, &intel_haswell_d_info), /* SDV GT3 reserved */
         INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
         INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
-        INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
+        INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT3 desktop */
         INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
         INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
-        INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
+        INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT3 server */
         INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
         INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
-        INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
+        INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT3 mobile */
+        INTEL_VGA_DEVICE(0x0A0B, &intel_haswell_d_info), /* ULT GT1 reserved */
+        INTEL_VGA_DEVICE(0x0A1B, &intel_haswell_d_info), /* ULT GT2 reserved */
+        INTEL_VGA_DEVICE(0x0A2B, &intel_haswell_d_info), /* ULT GT3 reserved */
+        INTEL_VGA_DEVICE(0x0A0E, &intel_haswell_m_info), /* ULT GT1 reserved */
+        INTEL_VGA_DEVICE(0x0A1E, &intel_haswell_m_info), /* ULT GT2 reserved */
+        INTEL_VGA_DEVICE(0x0A2E, &intel_haswell_m_info), /* ULT GT3 reserved */
         INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
         INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
-        INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
+        INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT3 desktop */
         INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
         INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
-        INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
+        INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT3 server */
         INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
         INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
-        INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
+        INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT3 mobile */
+        INTEL_VGA_DEVICE(0x0D0B, &intel_haswell_d_info), /* CRW GT1 reserved */
+        INTEL_VGA_DEVICE(0x0D1B, &intel_haswell_d_info), /* CRW GT2 reserved */
+        INTEL_VGA_DEVICE(0x0D2B, &intel_haswell_d_info), /* CRW GT3 reserved */
+        INTEL_VGA_DEVICE(0x0D0E, &intel_haswell_d_info), /* CRW GT1 reserved */
+        INTEL_VGA_DEVICE(0x0D1E, &intel_haswell_d_info), /* CRW GT2 reserved */
+        INTEL_VGA_DEVICE(0x0D2E, &intel_haswell_d_info), /* CRW GT3 reserved */
         INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
         INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index d5dcf7fe1ee9..b9d00dcf9a2d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1943,4 +1943,19 @@ static inline void __user *to_user_ptr(u64 address)
         return (void __user *)(uintptr_t)address;
 }
 
+static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
+{
+        unsigned long j = msecs_to_jiffies(m);
+
+        return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
+}
+
+static inline unsigned long
+timespec_to_jiffies_timeout(const struct timespec *value)
+{
+        unsigned long j = timespec_to_jiffies(value);
+
+        return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
+}
+
 #endif
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 6165535d15f0..970ad17c99ab 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -91,14 +91,11 @@ i915_gem_wait_for_error(struct i915_gpu_error *error)
 {
         int ret;
 
-#define EXIT_COND (!i915_reset_in_progress(error))
+#define EXIT_COND (!i915_reset_in_progress(error) || \
+                   i915_terminally_wedged(error))
         if (EXIT_COND)
                 return 0;
 
-        /* GPU is already declared terminally dead, give up. */
-        if (i915_terminally_wedged(error))
-                return -EIO;
-
         /*
          * Only wait 10 seconds for the gpu reset to complete to avoid hanging
          * userspace. If it takes that long something really bad is going on and
@@ -1003,7 +1000,7 @@ static int __wait_seqno(struct intel_ring_buffer *ring, u32 seqno,
                 wait_forever = false;
         }
 
-        timeout_jiffies = timespec_to_jiffies(&wait_time);
+        timeout_jiffies = timespec_to_jiffies_timeout(&wait_time);
 
         if (WARN_ON(!ring->irq_get(ring)))
                 return -ENODEV;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index efe829919755..56746dcac40f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7937,6 +7937,11 @@ intel_modeset_check_state(struct drm_device *dev)
                 memset(&pipe_config, 0, sizeof(pipe_config));
                 active = dev_priv->display.get_pipe_config(crtc,
                                                            &pipe_config);
+
+                /* hw state is inconsistent with the pipe A quirk */
+                if (crtc->pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
+                        active = crtc->active;
+
                 WARN(crtc->active != active,
                      "crtc active state doesn't match with hw state "
                      "(expected %i, found %i)\n", crtc->active, active);
@@ -8140,6 +8145,21 @@ static void intel_set_config_restore_state(struct drm_device *dev,
         }
 }
 
+static bool
+is_crtc_connector_off(struct drm_crtc *crtc, struct drm_connector *connectors,
+                      int num_connectors)
+{
+        int i;
+
+        for (i = 0; i < num_connectors; i++)
+                if (connectors[i].encoder &&
+                    connectors[i].encoder->crtc == crtc &&
+                    connectors[i].dpms != DRM_MODE_DPMS_ON)
+                        return true;
+
+        return false;
+}
+
 static void
 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
                                       struct intel_set_config *config)
@@ -8147,7 +8167,11 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set,
 
         /* We should be able to check here if the fb has the same properties
          * and then just flip_or_move it */
-        if (set->crtc->fb != set->fb) {
+        if (set->connectors != NULL &&
+            is_crtc_connector_off(set->crtc, *set->connectors,
+                                  set->num_connectors)) {
+                        config->mode_changed = true;
+        } else if (set->crtc->fb != set->fb) {
                 /* If we have no fb then treat it as a full mode set */
                 if (set->crtc->fb == NULL) {
                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
@@ -8157,8 +8181,9 @@ intel_set_config_compute_mode_changes(struct drm_mode_set *set,
                 } else if (set->fb->pixel_format !=
                            set->crtc->fb->pixel_format) {
                         config->mode_changed = true;
-                } else
+                } else {
                         config->fb_changed = true;
+                }
         }
 
         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
@@ -8332,11 +8357,6 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
 
                 ret = intel_set_mode(set->crtc, set->mode,
                                      set->x, set->y, set->fb);
-                if (ret) {
-                        DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
-                                  set->crtc->base.id, ret);
-                        goto fail;
-                }
         } else if (config->fb_changed) {
                 intel_crtc_wait_for_pending_flips(set->crtc);
 
@@ -8344,18 +8364,18 @@ static int intel_crtc_set_config(struct drm_mode_set *set)
                                           set->x, set->y, set->fb);
         }
 
-        intel_set_config_free(config);
-
-        return 0;
-
+        if (ret) {
+                DRM_ERROR("failed to set mode on [CRTC:%d], err = %d\n",
+                          set->crtc->base.id, ret);
 fail:
-        intel_set_config_restore_state(dev, config);
+                intel_set_config_restore_state(dev, config);
 
-        /* Try to restore the config */
-        if (config->mode_changed &&
-            intel_set_mode(save_set.crtc, save_set.mode,
-                           save_set.x, save_set.y, save_set.fb))
-                DRM_ERROR("failed to restore config after modeset failure\n");
+                /* Try to restore the config */
+                if (config->mode_changed &&
+                    intel_set_mode(save_set.crtc, save_set.mode,
+                                   save_set.x, save_set.y, save_set.fb))
+                        DRM_ERROR("failed to restore config after modeset failure\n");
+        }
 
 out_config:
         intel_set_config_free(config);
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 3d704b706a8d..70789b1b5642 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -303,7 +303,7 @@ intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
         if (has_aux_irq)
                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
-                                          msecs_to_jiffies(10));
+                                          msecs_to_jiffies_timeout(10));
         else
                 done = wait_for_atomic(C, 10) == 0;
         if (!done)
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index 5d245031e391..639fe192997c 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -228,7 +228,7 @@ gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
          * need to wake up periodically and check that ourselves. */
         I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
 
-        for (i = 0; i < msecs_to_jiffies(50) + 1; i++) {
+        for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
                 prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
                                 TASK_UNINTERRUPTIBLE);
 
@@ -263,7 +263,8 @@ gmbus_wait_idle(struct drm_i915_private *dev_priv)
         /* Important: The hw handles only the first bit, so set only one! */
         I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
 
-        ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
+        ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
+                                 msecs_to_jiffies_timeout(10));
 
         I915_WRITE(GMBUS4 + reg_offset, 0);
 
diff --git a/drivers/gpu/drm/i915/intel_lvds.c b/drivers/gpu/drm/i915/intel_lvds.c
index f36f1baabd5a..29412cc89c7a 100644
--- a/drivers/gpu/drm/i915/intel_lvds.c
+++ b/drivers/gpu/drm/i915/intel_lvds.c
@@ -815,10 +815,10 @@ static const struct dmi_system_id intel_no_lvds[] = {
         },
         {
                 .callback = intel_no_lvds_dmi_callback,
-                .ident = "Hewlett-Packard HP t5740e Thin Client",
+                .ident = "Hewlett-Packard HP t5740",
                 .matches = {
                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
-                        DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
+                        DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
                 },
         },
         {
diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index d15428404b9a..d4ea6c265ce1 100644
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1776,11 +1776,14 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
          * Assume that the preferred modes are
          * arranged in priority order.
          */
-        intel_ddc_get_modes(connector, intel_sdvo->i2c);
-        if (list_empty(&connector->probed_modes) == false)
-                goto end;
+        intel_ddc_get_modes(connector, &intel_sdvo->ddc);
 
-        /* Fetch modes from VBT */
+        /*
+         * Fetch modes from VBT. For SDVO prefer the VBT mode since some
+         * SDVO->LVDS transcoders can't cope with the EDID mode. Since
+         * drm_mode_probed_add adds the mode at the head of the list we add it
+         * last.
+         */
         if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
                 newmode = drm_mode_duplicate(connector->dev,
                                              dev_priv->sdvo_lvds_vbt_mode);
@@ -1792,7 +1795,6 @@ static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
                 }
         }
 
-end:
         list_for_each_entry(newmode, &connector->probed_modes, head) {
                 if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
                         intel_sdvo->sdvo_lvds_fixed_mode =
@@ -2790,12 +2792,6 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
                         SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
         }
 
-        /* Only enable the hotplug irq if we need it, to work around noisy
-         * hotplug lines.
-         */
-        if (intel_sdvo->hotplug_active)
-                intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C;
-
         intel_encoder->compute_config = intel_sdvo_compute_config;
         intel_encoder->disable = intel_disable_sdvo;
         intel_encoder->mode_set = intel_sdvo_mode_set;
@@ -2814,6 +2810,14 @@ bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
                 goto err_output;
         }
 
+        /* Only enable the hotplug irq if we need it, to work around noisy
+         * hotplug lines.
+         */
+        if (intel_sdvo->hotplug_active) {
+                intel_encoder->hpd_pin =
+                        intel_sdvo->is_sdvob ?  HPD_SDVO_B : HPD_SDVO_C;
+        }
+
         /*
          * Cloning SDVO with anything is often impossible, since the SDVO
          * encoder can request a special input timing mode. And even if that's
diff --git a/drivers/gpu/drm/mgag200/mgag200_mode.c b/drivers/gpu/drm/mgag200/mgag200_mode.c
index 77b8a45fb10a..ee66badc8bb6 100644
--- a/drivers/gpu/drm/mgag200/mgag200_mode.c
+++ b/drivers/gpu/drm/mgag200/mgag200_mode.c
@@ -1034,13 +1034,14 @@ static int mga_crtc_mode_set(struct drm_crtc *crtc,
                         else
                                 hi_pri_lvl = 5;
 
-                        WREG8(0x1fde, 0x06);
-                        WREG8(0x1fdf, hi_pri_lvl);
+                        WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
+                        WREG8(MGAREG_CRTCEXT_DATA, hi_pri_lvl);
                 } else {
+                        WREG8(MGAREG_CRTCEXT_INDEX, 0x06);
                         if (mdev->reg_1e24 >= 0x01)
-                                WREG8(0x1fdf, 0x03);
+                                WREG8(MGAREG_CRTCEXT_DATA, 0x03);
                         else
-                                WREG8(0x1fdf, 0x04);
+                                WREG8(MGAREG_CRTCEXT_DATA, 0x04);
                 }
         }
         return 0;
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
index d0817d94454c..f02fd9f443ff 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/dacnv50.c
@@ -50,11 +50,16 @@ nv50_dac_sense(struct nv50_disp_priv *priv, int or, u32 loadval)
 {
         const u32 doff = (or * 0x800);
         int load = -EINVAL;
+        nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80150000);
+        nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
         nv_wr32(priv, 0x61a00c + doff, 0x00100000 | loadval);
-        udelay(9500);
+        mdelay(9);
+        udelay(500);
         nv_wr32(priv, 0x61a00c + doff, 0x80000000);
         load = (nv_rd32(priv, 0x61a00c + doff) & 0x38000000) >> 27;
         nv_wr32(priv, 0x61a00c + doff, 0x00000000);
+        nv_mask(priv, 0x61a004 + doff, 0x807f0000, 0x80550000);
+        nv_wait(priv, 0x61a004 + doff, 0x80000000, 0x00000000);
         return load;
 }
 
diff --git a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
index 0d36bdc51417..7fdade6e604d 100644
--- a/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
+++ b/drivers/gpu/drm/nouveau/core/engine/disp/hdminv84.c
@@ -55,6 +55,10 @@ nv84_hdmi_ctrl(struct nv50_disp_priv *priv, int head, int or, u32 data)
         nv_wr32(priv, 0x616510 + hoff, 0x00000000);
         nv_mask(priv, 0x616500 + hoff, 0x00000001, 0x00000001);
 
+        nv_mask(priv, 0x6165d0 + hoff, 0x00070001, 0x00010001); /* SPARE, HW_CTS */
+        nv_mask(priv, 0x616568 + hoff, 0x00010101, 0x00000000); /* ACR_CTRL, ?? */
+        nv_mask(priv, 0x616578 + hoff, 0x80000000, 0x80000000); /* ACR_0441_ENABLE */
+
         /* ??? */
         nv_mask(priv, 0x61733c, 0x00100000, 0x00100000); /* RESETF */
         nv_mask(priv, 0x61733c, 0x10000000, 0x10000000); /* LOOKUP_EN */
diff --git a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
index 89bf459d584b..e9b8217d0075 100644
--- a/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
+++ b/drivers/gpu/drm/nouveau/core/engine/fifo/nv50.c
@@ -40,14 +40,13 @@
  * FIFO channel objects
  ******************************************************************************/
 
-void
-nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
+static void
+nv50_fifo_playlist_update_locked(struct nv50_fifo_priv *priv)
 {
         struct nouveau_bar *bar = nouveau_bar(priv);
         struct nouveau_gpuobj *cur;
         int i, p;
 
-        mutex_lock(&nv_subdev(priv)->mutex);
         cur = priv->playlist[priv->cur_playlist];
         priv->cur_playlist = !priv->cur_playlist;
 
@@ -61,6 +60,13 @@ nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
         nv_wr32(priv, 0x0032f4, cur->addr >> 12);
         nv_wr32(priv, 0x0032ec, p);
         nv_wr32(priv, 0x002500, 0x00000101);
+}
+
+void
+nv50_fifo_playlist_update(struct nv50_fifo_priv *priv)
+{
+        mutex_lock(&nv_subdev(priv)->mutex);
+        nv50_fifo_playlist_update_locked(priv);
         mutex_unlock(&nv_subdev(priv)->mutex);
 }
 
@@ -489,7 +495,7 @@ nv50_fifo_init(struct nouveau_object *object)
 
         for (i = 0; i < 128; i++)
                 nv_wr32(priv, 0x002600 + (i * 4), 0x00000000);
-        nv50_fifo_playlist_update(priv);
+        nv50_fifo_playlist_update_locked(priv);
 
         nv_wr32(priv, 0x003200, 0x00000001);
         nv_wr32(priv, 0x003250, 0x00000001);
diff --git a/drivers/gpu/drm/nouveau/core/include/core/class.h b/drivers/gpu/drm/nouveau/core/include/core/class.h
index 0a393f7f055f..5a5961b6a6a3 100644
--- a/drivers/gpu/drm/nouveau/core/include/core/class.h
+++ b/drivers/gpu/drm/nouveau/core/include/core/class.h
@@ -218,7 +218,7 @@ struct nv04_display_class {
 #define NV50_DISP_DAC_PWR_STATE                                      0x00000040
 #define NV50_DISP_DAC_PWR_STATE_ON                                   0x00000000
 #define NV50_DISP_DAC_PWR_STATE_OFF                                  0x00000040
-#define NV50_DISP_DAC_LOAD                                           0x0002000c
+#define NV50_DISP_DAC_LOAD                                           0x00020100
 #define NV50_DISP_DAC_LOAD_VALUE                                     0x00000007
 
 #define NV50_DISP_PIOR_MTHD                                          0x00030000
diff --git a/drivers/gpu/drm/nouveau/nouveau_display.c b/drivers/gpu/drm/nouveau/nouveau_display.c
index 7bf22d4a3d96..f17dc2ab03ec 100644
--- a/drivers/gpu/drm/nouveau/nouveau_display.c
+++ b/drivers/gpu/drm/nouveau/nouveau_display.c
@@ -638,17 +638,8 @@ nouveau_finish_page_flip(struct nouveau_channel *chan,
         }
 
         s = list_first_entry(&fctx->flip, struct nouveau_page_flip_state, head);
-        if (s->event) {
-                struct drm_pending_vblank_event *e = s->event;
-                struct timeval now;
-
-                do_gettimeofday(&now);
-                e->event.sequence = 0;
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-                list_add_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
-        }
+        if (s->event)
+                drm_send_vblank_event(dev, -1, s->event);
 
         list_del(&s->head);
         if (ps)
diff --git a/drivers/gpu/drm/nouveau/nv50_display.c b/drivers/gpu/drm/nouveau/nv50_display.c
index ebf0a683305e..dd5e01f89f28 100644
--- a/drivers/gpu/drm/nouveau/nv50_display.c
+++ b/drivers/gpu/drm/nouveau/nv50_display.c
@@ -1554,7 +1554,9 @@ nv50_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
 {
         struct nv50_disp *disp = nv50_disp(encoder->dev);
         int ret, or = nouveau_encoder(encoder)->or;
-        u32 load = 0;
+        u32 load = nouveau_drm(encoder->dev)->vbios.dactestval;
+        if (load == 0)
+                load = 340;
 
         ret = nv_exec(disp->core, NV50_DISP_DAC_LOAD + or, &load, sizeof(load));
         if (ret || load != 7)
diff --git a/drivers/gpu/drm/omapdrm/omap_drv.c b/drivers/gpu/drm/omapdrm/omap_drv.c
index 9c53c25e5201..826586ffbe83 100644
--- a/drivers/gpu/drm/omapdrm/omap_drv.c
+++ b/drivers/gpu/drm/omapdrm/omap_drv.c
@@ -649,6 +649,9 @@ static void pdev_shutdown(struct platform_device *device)
 
 static int pdev_probe(struct platform_device *device)
 {
+        if (omapdss_is_initialized() == false)
+                return -EPROBE_DEFER;
+
         DBG("%s", device->name);
         return drm_platform_init(&omap_drm_driver, device);
 }
diff --git a/drivers/gpu/drm/qxl/Kconfig b/drivers/gpu/drm/qxl/Kconfig
index 2f1a57e11140..d6c12796023c 100644
--- a/drivers/gpu/drm/qxl/Kconfig
+++ b/drivers/gpu/drm/qxl/Kconfig
@@ -4,6 +4,7 @@ config DRM_QXL
         select FB_SYS_FILLRECT
         select FB_SYS_COPYAREA
         select FB_SYS_IMAGEBLIT
+        select FB_DEFERRED_IO
         select DRM_KMS_HELPER
         select DRM_TTM
         help
diff --git a/drivers/gpu/drm/qxl/qxl_ioctl.c b/drivers/gpu/drm/qxl/qxl_ioctl.c
index 6db7370373ea..a4b71b25fa53 100644
--- a/drivers/gpu/drm/qxl/qxl_ioctl.c
+++ b/drivers/gpu/drm/qxl/qxl_ioctl.c
@@ -151,7 +151,7 @@ static int qxl_execbuffer_ioctl(struct drm_device *dev, void *data,
                 struct qxl_bo *cmd_bo;
                 int release_type;
                 struct drm_qxl_command *commands =
-                        (struct drm_qxl_command *)execbuffer->commands;
+                        (struct drm_qxl_command *)(uintptr_t)execbuffer->commands;
 
                 if (DRM_COPY_FROM_USER(&user_cmd, &commands[cmd_num],
                                        sizeof(user_cmd)))
@@ -193,7 +193,7 @@ static int qxl_execbuffer_ioctl(struct drm_device *dev, void *data,
 
                 for (i = 0 ; i < user_cmd.relocs_num; ++i) {
                         if (DRM_COPY_FROM_USER(&reloc,
-                                               &((struct drm_qxl_reloc *)user_cmd.relocs)[i],
+                                               &((struct drm_qxl_reloc *)(uintptr_t)user_cmd.relocs)[i],
                                                sizeof(reloc))) {
                                 qxl_bo_list_unreserve(&reloc_list, true);
                                 qxl_release_unreserve(qdev, release);
diff --git a/drivers/gpu/drm/qxl/qxl_kms.c b/drivers/gpu/drm/qxl/qxl_kms.c
index 85127ed24cfd..e27ce2a907cf 100644
--- a/drivers/gpu/drm/qxl/qxl_kms.c
+++ b/drivers/gpu/drm/qxl/qxl_kms.c
@@ -128,12 +128,13 @@ int qxl_device_init(struct qxl_device *qdev,
 
         qdev->vram_mapping = io_mapping_create_wc(qdev->vram_base, pci_resource_len(pdev, 0));
         qdev->surface_mapping = io_mapping_create_wc(qdev->surfaceram_base, qdev->surfaceram_size);
-        DRM_DEBUG_KMS("qxl: vram %p-%p(%dM %dk), surface %p-%p(%dM %dk)\n",
-                 (void *)qdev->vram_base, (void *)pci_resource_end(pdev, 0),
+        DRM_DEBUG_KMS("qxl: vram %llx-%llx(%dM %dk), surface %llx-%llx(%dM %dk)\n",
+                 (unsigned long long)qdev->vram_base,
+                 (unsigned long long)pci_resource_end(pdev, 0),
                  (int)pci_resource_len(pdev, 0) / 1024 / 1024,
                  (int)pci_resource_len(pdev, 0) / 1024,
-                 (void *)qdev->surfaceram_base,
-                 (void *)pci_resource_end(pdev, 1),
+                 (unsigned long long)qdev->surfaceram_base,
+                 (unsigned long long)pci_resource_end(pdev, 1),
                  (int)qdev->surfaceram_size / 1024 / 1024,
                  (int)qdev->surfaceram_size / 1024);
 
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 44a7da66e081..8406c8251fbf 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -667,6 +667,8 @@ atombios_digital_setup(struct drm_encoder *encoder, int action)
 int
 atombios_get_encoder_mode(struct drm_encoder *encoder)
 {
+        struct drm_device *dev = encoder->dev;
+        struct radeon_device *rdev = dev->dev_private;
         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
         struct drm_connector *connector;
         struct radeon_connector *radeon_connector;
@@ -693,7 +695,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
         case DRM_MODE_CONNECTOR_DVII:
         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
-                    radeon_audio)
+                    radeon_audio &&
+                    !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
                         return ATOM_ENCODER_MODE_HDMI;
                 else if (radeon_connector->use_digital)
                         return ATOM_ENCODER_MODE_DVI;
@@ -704,7 +707,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
         case DRM_MODE_CONNECTOR_HDMIA:
         default:
                 if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
-                    radeon_audio)
+                    radeon_audio &&
+                    !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
                         return ATOM_ENCODER_MODE_HDMI;
                 else
                         return ATOM_ENCODER_MODE_DVI;
@@ -718,7 +722,8 @@ atombios_get_encoder_mode(struct drm_encoder *encoder)
                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP))
                         return ATOM_ENCODER_MODE_DP;
                 else if (drm_detect_hdmi_monitor(radeon_connector->edid) &&
-                         radeon_audio)
+                         radeon_audio &&
+                         !ASIC_IS_DCE6(rdev)) /* remove once we support DCE6 */
                         return ATOM_ENCODER_MODE_HDMI;
                 else
                         return ATOM_ENCODER_MODE_DVI;
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 8f9e2d31b255..0f89ce3d02b9 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -4754,6 +4754,12 @@ static int evergreen_startup(struct radeon_device *rdev)
                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = r600_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -4923,10 +4929,6 @@ int evergreen_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -4999,8 +5001,7 @@ void evergreen_fini(struct radeon_device *rdev)
 
 void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
 {
-        u32 link_width_cntl, speed_cntl, mask;
-        int ret;
+        u32 link_width_cntl, speed_cntl;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -5015,11 +5016,8 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
         if (ASIC_IS_X2(rdev))
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 7969c0c8ec20..84583302b081 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -2025,6 +2025,12 @@ static int cayman_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = r600_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -2190,10 +2196,6 @@ int cayman_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         ring->ring_obj = NULL;
         r600_ring_init(rdev, ring, 1024 * 1024);
 
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 4973bff37fec..d0314ecbd7c1 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3869,6 +3869,12 @@ static int r100_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r100_irq_set(rdev);
         rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -4024,9 +4030,6 @@ int r100_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index c60350e6872d..b9b776f1e582 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -1382,6 +1382,12 @@ static int r300_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -1516,9 +1522,6 @@ int r300_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 6fce2eb4dd16..4e796ecf9ea4 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -265,6 +265,12 @@ static int r420_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -411,10 +417,6 @@ int r420_init(struct radeon_device *rdev)
         if (r) {
                 return r;
         }
-        r = radeon_irq_kms_init(rdev);
-        if (r) {
-                return r;
-        }
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r) {
diff --git a/drivers/gpu/drm/radeon/r520.c b/drivers/gpu/drm/radeon/r520.c
index f795a4e092cb..e1aece73b370 100644
--- a/drivers/gpu/drm/radeon/r520.c
+++ b/drivers/gpu/drm/radeon/r520.c
@@ -194,6 +194,12 @@ static int r520_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -297,9 +303,6 @@ int r520_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 1a08008c978b..0e5341695922 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1046,6 +1046,24 @@ int r600_mc_wait_for_idle(struct radeon_device *rdev)
         return -1;
 }
 
+uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg)
+{
+        uint32_t r;
+
+        WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg));
+        r = RREG32(R_0028FC_MC_DATA);
+        WREG32(R_0028F8_MC_INDEX, ~C_0028F8_MC_IND_ADDR);
+        return r;
+}
+
+void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
+{
+        WREG32(R_0028F8_MC_INDEX, S_0028F8_MC_IND_ADDR(reg) |
+                S_0028F8_MC_IND_WR_EN(1));
+        WREG32(R_0028FC_MC_DATA, v);
+        WREG32(R_0028F8_MC_INDEX, 0x7F);
+}
+
 static void r600_mc_program(struct radeon_device *rdev)
 {
         struct rv515_mc_save save;
@@ -1181,6 +1199,8 @@ static int r600_mc_init(struct radeon_device *rdev)
 {
         u32 tmp;
         int chansize, numchan;
+        uint32_t h_addr, l_addr;
+        unsigned long long k8_addr;
 
         /* Get VRAM informations */
         rdev->mc.vram_is_ddr = true;
@@ -1221,7 +1241,30 @@ static int r600_mc_init(struct radeon_device *rdev)
         if (rdev->flags & RADEON_IS_IGP) {
                 rs690_pm_info(rdev);
                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
+
+                if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
+                        /* Use K8 direct mapping for fast fb access. */
+                        rdev->fastfb_working = false;
+                        h_addr = G_000012_K8_ADDR_EXT(RREG32_MC(R_000012_MC_MISC_UMA_CNTL));
+                        l_addr = RREG32_MC(R_000011_K8_FB_LOCATION);
+                        k8_addr = ((unsigned long long)h_addr) << 32 | l_addr;
+#if defined(CONFIG_X86_32) && !defined(CONFIG_X86_PAE)
+                        if (k8_addr + rdev->mc.visible_vram_size < 0x100000000ULL)
+#endif
+                        {
+                                /* FastFB shall be used with UMA memory. Here it is simply disabled when sideport
+                                * memory is present.
+                                */
+                                if (rdev->mc.igp_sideport_enabled == false && radeon_fastfb == 1) {
+                                        DRM_INFO("Direct mapping: aper base at 0x%llx, replaced by direct mapping base 0x%llx.\n",
+                                                (unsigned long long)rdev->mc.aper_base, k8_addr);
+                                        rdev->mc.aper_base = (resource_size_t)k8_addr;
+                                        rdev->fastfb_working = true;
+                                }
+                        }
+                }
         }
+
         radeon_update_bandwidth_info(rdev);
         return 0;
 }
@@ -3202,6 +3245,12 @@ static int r600_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = r600_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -3356,10 +3405,6 @@ int r600_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -4631,8 +4676,6 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
 {
         u32 link_width_cntl, lanes, speed_cntl, training_cntl, tmp;
         u16 link_cntl2;
-        u32 mask;
-        int ret;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -4651,11 +4694,8 @@ static void r600_pcie_gen2_enable(struct radeon_device *rdev)
         if (rdev->family <= CHIP_R600)
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL);
diff --git a/drivers/gpu/drm/radeon/r600d.h b/drivers/gpu/drm/radeon/r600d.h
index acb146c06973..79df558f8c40 100644
--- a/drivers/gpu/drm/radeon/r600d.h
+++ b/drivers/gpu/drm/radeon/r600d.h
@@ -1342,6 +1342,14 @@
 #define PACKET3_STRMOUT_BASE_UPDATE                     0x72 /* r7xx */
 #define PACKET3_SURFACE_BASE_UPDATE                     0x73
 
+#define R_000011_K8_FB_LOCATION                 0x11
+#define R_000012_MC_MISC_UMA_CNTL               0x12
+#define   G_000012_K8_ADDR_EXT(x)               (((x) >> 0) & 0xFF)
+#define R_0028F8_MC_INDEX                       0x28F8
+#define         S_0028F8_MC_IND_ADDR(x)                 (((x) & 0x1FF) << 0)
+#define         C_0028F8_MC_IND_ADDR                    0xFFFFFE00
+#define         S_0028F8_MC_IND_WR_EN(x)                (((x) & 0x1) << 9)
+#define R_0028FC_MC_DATA                        0x28FC
 
 #define R_008020_GRBM_SOFT_RESET                0x8020
 #define         S_008020_SOFT_RESET_CP(x)               (((x) & 1) << 0)
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 06b8c19ab19e..a2802b47ee95 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -122,6 +122,10 @@ static void radeon_register_accessor_init(struct radeon_device *rdev)
                 rdev->mc_rreg = &rs600_mc_rreg;
                 rdev->mc_wreg = &rs600_mc_wreg;
         }
+        if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
+                rdev->mc_rreg = &rs780_mc_rreg;
+                rdev->mc_wreg = &rs780_mc_wreg;
+        }
         if (rdev->family >= CHIP_R600) {
                 rdev->pciep_rreg = &r600_pciep_rreg;
                 rdev->pciep_wreg = &r600_pciep_wreg;
diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 2c87365d345f..a72759ede753 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -347,6 +347,8 @@ extern bool r600_gui_idle(struct radeon_device *rdev);
 extern void r600_pm_misc(struct radeon_device *rdev);
 extern void r600_pm_init_profile(struct radeon_device *rdev);
 extern void rs780_pm_init_profile(struct radeon_device *rdev);
+extern uint32_t rs780_mc_rreg(struct radeon_device *rdev, uint32_t reg);
+extern void rs780_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index c2c59fb1ea01..189973836cff 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -467,23 +467,27 @@ bool radeon_card_posted(struct radeon_device *rdev)
 {
         uint32_t reg;
 
+        /* required for EFI mode on macbook2,1 which uses an r5xx asic */
         if (efi_enabled(EFI_BOOT) &&
-            rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE)
+            (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
+            (rdev->family < CHIP_R600))
                 return false;
 
+        if (ASIC_IS_NODCE(rdev))
+                goto check_memsize;
+
         /* first check CRTCs */
-        if (ASIC_IS_DCE41(rdev)) {
+        if (ASIC_IS_DCE4(rdev)) {
                 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
                         RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
-                if (reg & EVERGREEN_CRTC_MASTER_EN)
-                        return true;
-        } else if (ASIC_IS_DCE4(rdev)) {
-                reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
-                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+                        if (rdev->num_crtc >= 4) {
+                                reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
+                                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
+                        }
+                        if (rdev->num_crtc >= 6) {
+                                reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
+                                        RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
+                        }
                 if (reg & EVERGREEN_CRTC_MASTER_EN)
                         return true;
         } else if (ASIC_IS_AVIVO(rdev)) {
@@ -500,6 +504,7 @@ bool radeon_card_posted(struct radeon_device *rdev)
                 }
         }
 
+check_memsize:
         /* then check MEM_SIZE, in case the crtcs are off */
         if (rdev->family >= CHIP_R600)
                 reg = RREG32(R600_CONFIG_MEMSIZE);
diff --git a/drivers/gpu/drm/radeon/radeon_display.c b/drivers/gpu/drm/radeon/radeon_display.c
index e38fd559f1ab..eb18bb7af1cc 100644
--- a/drivers/gpu/drm/radeon/radeon_display.c
+++ b/drivers/gpu/drm/radeon/radeon_display.c
@@ -271,8 +271,6 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
 {
         struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
         struct radeon_unpin_work *work;
-        struct drm_pending_vblank_event *e;
-        struct timeval now;
         unsigned long flags;
         u32 update_pending;
         int vpos, hpos;
@@ -328,14 +326,9 @@ void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id)
         radeon_crtc->unpin_work = NULL;
 
         /* wakeup userspace */
-        if (work->event) {
-                e = work->event;
-                e->event.sequence = drm_vblank_count_and_time(rdev->ddev, crtc_id, &now);
-                e->event.tv_sec = now.tv_sec;
-                e->event.tv_usec = now.tv_usec;
-                list_add_tail(&e->base.link, &e->base.file_priv->event_list);
-                wake_up_interruptible(&e->base.file_priv->event_wait);
-        }
+        if (work->event)
+                drm_send_vblank_event(rdev->ddev, crtc_id, work->event);
+
         spin_unlock_irqrestore(&rdev->ddev->event_lock, flags);
 
         drm_vblank_put(rdev->ddev, radeon_crtc->crtc_id);
diff --git a/drivers/gpu/drm/radeon/rs400.c b/drivers/gpu/drm/radeon/rs400.c
index 73051ce3121e..233a9b9fa1f7 100644
--- a/drivers/gpu/drm/radeon/rs400.c
+++ b/drivers/gpu/drm/radeon/rs400.c
@@ -417,6 +417,12 @@ static int rs400_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r100_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -535,9 +541,6 @@ int rs400_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index 46fa1b07c560..670b555d2ca2 100644
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -923,6 +923,12 @@ static int rs600_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -1047,9 +1053,6 @@ int rs600_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rs690.c b/drivers/gpu/drm/radeon/rs690.c
index ab4c86cfd552..55880d5962c3 100644
--- a/drivers/gpu/drm/radeon/rs690.c
+++ b/drivers/gpu/drm/radeon/rs690.c
@@ -651,6 +651,12 @@ static int rs690_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -776,9 +782,6 @@ int rs690_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rv515.c b/drivers/gpu/drm/radeon/rv515.c
index ffcba730c57c..21c7d7b26e55 100644
--- a/drivers/gpu/drm/radeon/rv515.c
+++ b/drivers/gpu/drm/radeon/rv515.c
@@ -532,6 +532,12 @@ static int rv515_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         rs600_irq_set(rdev);
         rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
         /* 1M ring buffer */
@@ -662,9 +668,6 @@ int rv515_init(struct radeon_device *rdev)
         r = radeon_fence_driver_init(rdev);
         if (r)
                 return r;
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
         /* Memory manager */
         r = radeon_bo_init(rdev);
         if (r)
diff --git a/drivers/gpu/drm/radeon/rv770.c b/drivers/gpu/drm/radeon/rv770.c
index 83f612a9500b..4a62ad2e5399 100644
--- a/drivers/gpu/drm/radeon/rv770.c
+++ b/drivers/gpu/drm/radeon/rv770.c
@@ -862,10 +862,8 @@ int rv770_uvd_resume(struct radeon_device *rdev)
                 chip_id = 0x0100000b;
                 break;
         case CHIP_SUMO:
-                chip_id = 0x0100000c;
-                break;
         case CHIP_SUMO2:
-                chip_id = 0x0100000d;
+                chip_id = 0x0100000c;
                 break;
         case CHIP_PALM:
                 chip_id = 0x0100000e;
@@ -1889,6 +1887,12 @@ static int rv770_startup(struct radeon_device *rdev)
                 rdev->ring[R600_RING_TYPE_UVD_INDEX].ring_size = 0;
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = r600_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -2047,10 +2051,6 @@ int rv770_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         rdev->ring[RADEON_RING_TYPE_GFX_INDEX].ring_obj = NULL;
         r600_ring_init(rdev, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX], 1024 * 1024);
 
@@ -2113,8 +2113,6 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
 {
         u32 link_width_cntl, lanes, speed_cntl, tmp;
         u16 link_cntl2;
-        u32 mask;
-        int ret;
 
         if (radeon_pcie_gen2 == 0)
                 return;
@@ -2129,11 +2127,8 @@ static void rv770_pcie_gen2_enable(struct radeon_device *rdev)
         if (ASIC_IS_X2(rdev))
                 return;
 
-        ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
-        if (ret != 0)
-                return;
-
-        if (!(mask & DRM_PCIE_SPEED_50))
+        if ((rdev->pdev->bus->max_bus_speed != PCIE_SPEED_5_0GT) &&
+                (rdev->pdev->bus->max_bus_speed != PCIE_SPEED_8_0GT))
                 return;
 
         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 5ffade69af25..a1b0da6b5808 100644
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2616,7 +2616,7 @@ static void si_gpu_init(struct radeon_device *rdev)
         default:
                 rdev->config.si.max_shader_engines = 1;
                 rdev->config.si.max_tile_pipes = 4;
-                rdev->config.si.max_cu_per_sh = 2;
+                rdev->config.si.max_cu_per_sh = 5;
                 rdev->config.si.max_sh_per_se = 2;
                 rdev->config.si.max_backends_per_se = 4;
                 rdev->config.si.max_texture_channel_caches = 4;
@@ -5350,6 +5350,12 @@ static int si_startup(struct radeon_device *rdev)
         }
 
         /* Enable IRQ */
+        if (!rdev->irq.installed) {
+                r = radeon_irq_kms_init(rdev);
+                if (r)
+                        return r;
+        }
+
         r = si_irq_init(rdev);
         if (r) {
                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
@@ -5533,10 +5539,6 @@ int si_init(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = radeon_irq_kms_init(rdev);
-        if (r)
-                return r;
-
         ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
         ring->ring_obj = NULL;
         r600_ring_init(rdev, ring, 1024 * 1024);
diff --git a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c b/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
index 7dff49ed66e7..99e2034e49cc 100644
--- a/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
+++ b/drivers/gpu/drm/shmobile/shmob_drm_crtc.c
@@ -451,27 +451,16 @@ void shmob_drm_crtc_finish_page_flip(struct shmob_drm_crtc *scrtc)
 {
         struct drm_pending_vblank_event *event;
         struct drm_device *dev = scrtc->crtc.dev;
-        struct timeval vblanktime;
         unsigned long flags;
 
         spin_lock_irqsave(&dev->event_lock, flags);
         event = scrtc->event;
         scrtc->event = NULL;
+        if (event) {
+                drm_send_vblank_event(dev, 0, event);
+                drm_vblank_put(dev, 0);
+        }
         spin_unlock_irqrestore(&dev->event_lock, flags);
-
-        if (event == NULL)
-                return;
-
-        event->event.sequence = drm_vblank_count_and_time(dev, 0, &vblanktime);
-        event->event.tv_sec = vblanktime.tv_sec;
-        event->event.tv_usec = vblanktime.tv_usec;
-
-        spin_lock_irqsave(&dev->event_lock, flags);
-        list_add_tail(&event->base.link, &event->base.file_priv->event_list);
-        wake_up_interruptible(&event->base.file_priv->event_wait);
-        spin_unlock_irqrestore(&dev->event_lock, flags);
-
-        drm_vblank_put(dev, 0);
 }
 
 static int shmob_drm_crtc_page_flip(struct drm_crtc *crtc,
diff --git a/drivers/gpu/drm/tilcdc/Kconfig b/drivers/gpu/drm/tilcdc/Kconfig
index e461e9972455..7a4d10106906 100644
--- a/drivers/gpu/drm/tilcdc/Kconfig
+++ b/drivers/gpu/drm/tilcdc/Kconfig
@@ -6,6 +6,7 @@ config DRM_TILCDC
         select DRM_GEM_CMA_HELPER
         select VIDEOMODE_HELPERS
         select BACKLIGHT_CLASS_DEVICE
+        select BACKLIGHT_LCD_SUPPORT
         help
           Choose this option if you have an TI SoC with LCDC display
           controller, for example AM33xx in beagle-bone, DA8xx, or
diff --git a/drivers/hid/hid-multitouch.c b/drivers/hid/hid-multitouch.c
index dc3ae5c56f56..d39a5cede0b0 100644
--- a/drivers/hid/hid-multitouch.c
+++ b/drivers/hid/hid-multitouch.c
@@ -264,9 +264,12 @@ static struct mt_class mt_classes[] = {
 static void mt_free_input_name(struct hid_input *hi)
 {
         struct hid_device *hdev = hi->report->device;
+        const char *name = hi->input->name;
 
-        if (hi->input->name != hdev->name)
-                kfree(hi->input->name);
+        if (name != hdev->name) {
+                hi->input->name = hdev->name;
+                kfree(name);
+        }
 }
 
 static ssize_t mt_show_quirks(struct device *dev,
@@ -1040,11 +1043,11 @@ static void mt_remove(struct hid_device *hdev)
         struct hid_input *hi;
 
         sysfs_remove_group(&hdev->dev.kobj, &mt_attribute_group);
-        hid_hw_stop(hdev);
-
         list_for_each_entry(hi, &hdev->inputs, list)
                 mt_free_input_name(hi);
 
+        hid_hw_stop(hdev);
+
         kfree(td);
         hid_set_drvdata(hdev, NULL);
 }
diff --git a/drivers/hwmon/adm1021.c b/drivers/hwmon/adm1021.c
index 7e76922a4ba9..f920619cd6da 100644
--- a/drivers/hwmon/adm1021.c
+++ b/drivers/hwmon/adm1021.c
@@ -331,26 +331,68 @@ static int adm1021_detect(struct i2c_client *client,
         man_id = i2c_smbus_read_byte_data(client, ADM1021_REG_MAN_ID);
         dev_id = i2c_smbus_read_byte_data(client, ADM1021_REG_DEV_ID);
 
+        if (man_id < 0 || dev_id < 0)
+                return -ENODEV;
+
         if (man_id == 0x4d && dev_id == 0x01)
                 type_name = "max1617a";
         else if (man_id == 0x41) {
                 if ((dev_id & 0xF0) == 0x30)
                         type_name = "adm1023";
-                else
+                else if ((dev_id & 0xF0) == 0x00)
                         type_name = "adm1021";
+                else
+                        return -ENODEV;
         } else if (man_id == 0x49)
                 type_name = "thmc10";
         else if (man_id == 0x23)
                 type_name = "gl523sm";
         else if (man_id == 0x54)
                 type_name = "mc1066";
-        /* LM84 Mfr ID in a different place, and it has more unused bits */
-        else if (conv_rate == 0x00
-                 && (config & 0x7F) == 0x00
-                 && (status & 0xAB) == 0x00)
-                type_name = "lm84";
-        else
-                type_name = "max1617";
+        else {
+                int lte, rte, lhi, rhi, llo, rlo;
+
+                /* extra checks for LM84 and MAX1617 to avoid misdetections */
+
+                llo = i2c_smbus_read_byte_data(client, ADM1021_REG_THYST_R(0));
+                rlo = i2c_smbus_read_byte_data(client, ADM1021_REG_THYST_R(1));
+
+                /* fail if any of the additional register reads failed */
+                if (llo < 0 || rlo < 0)
+                        return -ENODEV;
+
+                lte = i2c_smbus_read_byte_data(client, ADM1021_REG_TEMP(0));
+                rte = i2c_smbus_read_byte_data(client, ADM1021_REG_TEMP(1));
+                lhi = i2c_smbus_read_byte_data(client, ADM1021_REG_TOS_R(0));
+                rhi = i2c_smbus_read_byte_data(client, ADM1021_REG_TOS_R(1));
+
+                /*
+                 * Fail for negative temperatures and negative high limits.
+                 * This check also catches read errors on the tested registers.
+                 */
+                if ((s8)lte < 0 || (s8)rte < 0 || (s8)lhi < 0 || (s8)rhi < 0)
+                        return -ENODEV;
+
+                /* fail if all registers hold the same value */
+                if (lte == rte && lte == lhi && lte == rhi && lte == llo
+                    && lte == rlo)
+                        return -ENODEV;
+
+                /*
+                 * LM84 Mfr ID is in a different place,
+                 * and it has more unused bits.
+                 */
+                if (conv_rate == 0x00
+                    && (config & 0x7F) == 0x00
+                    && (status & 0xAB) == 0x00) {
+                        type_name = "lm84";
+                } else {
+                        /* fail if low limits are larger than high limits */
+                        if ((s8)llo > lhi || (s8)rlo > rhi)
+                                return -ENODEV;
+                        type_name = "max1617";
+                }
+        }
 
         pr_debug("Detected chip %s at adapter %d, address 0x%02x.\n",
                  type_name, i2c_adapter_id(adapter), client->addr);
diff --git a/drivers/i2c/busses/i2c-stu300.c b/drivers/i2c/busses/i2c-stu300.c
index 0a6f941133f6..d1a6b204af00 100644
--- a/drivers/i2c/busses/i2c-stu300.c
+++ b/drivers/i2c/busses/i2c-stu300.c
@@ -17,6 +17,7 @@
 #include <linux/clk.h>
 #include <linux/io.h>
 #include <linux/slab.h>
+#include <linux/of_i2c.h>
 
 /* the name of this kernel module */
 #define NAME "stu300"
@@ -867,7 +868,6 @@ stu300_probe(struct platform_device *pdev)
         struct resource *res;
         int bus_nr;
         int ret = 0;
-        char clk_name[] = "I2C0";
 
         dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
         if (!dev) {
@@ -876,8 +876,7 @@ stu300_probe(struct platform_device *pdev)
         }
 
         bus_nr = pdev->id;
-        clk_name[3] += (char)bus_nr;
-        dev->clk = devm_clk_get(&pdev->dev, clk_name);
+        dev->clk = devm_clk_get(&pdev->dev, NULL);
         if (IS_ERR(dev->clk)) {
                 dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
                 return PTR_ERR(dev->clk);
@@ -923,6 +922,7 @@ stu300_probe(struct platform_device *pdev)
         adap->nr = bus_nr;
         adap->algo = &stu300_algo;
         adap->dev.parent = &pdev->dev;
+        adap->dev.of_node = pdev->dev.of_node;
         i2c_set_adapdata(adap, dev);
 
         /* i2c device drivers may be active on return from add_adapter() */
@@ -934,6 +934,10 @@ stu300_probe(struct platform_device *pdev)
         }
 
         platform_set_drvdata(pdev, dev);
+        dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
+                 dev->virtbase, dev->irq);
+        of_i2c_register_devices(adap);
+
         return 0;
 }
 
@@ -978,11 +982,17 @@ stu300_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id stu300_dt_match[] = {
+        { .compatible = "st,ddci2c" },
+        {},
+};
+
 static struct platform_driver stu300_i2c_driver = {
         .driver = {
                 .name   = NAME,
                 .owner  = THIS_MODULE,
                 .pm     = STU300_I2C_PM,
+                .of_match_table = stu300_dt_match,
         },
         .remove         = __exit_p(stu300_remove),
 
diff --git a/drivers/iio/buffer_cb.c b/drivers/iio/buffer_cb.c
index 9201022945e9..9d19ba74f22b 100644
--- a/drivers/iio/buffer_cb.c
+++ b/drivers/iio/buffer_cb.c
@@ -64,7 +64,7 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
         while (chan->indio_dev) {
                 if (chan->indio_dev != indio_dev) {
                         ret = -EINVAL;
-                        goto error_release_channels;
+                        goto error_free_scan_mask;
                 }
                 set_bit(chan->channel->scan_index,
                         cb_buff->buffer.scan_mask);
@@ -73,6 +73,8 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
 
         return cb_buff;
 
+error_free_scan_mask:
+        kfree(cb_buff->buffer.scan_mask);
 error_release_channels:
         iio_channel_release_all(cb_buff->channels);
 error_free_cb_buff:
@@ -100,6 +102,7 @@ EXPORT_SYMBOL_GPL(iio_channel_stop_all_cb);
 
 void iio_channel_release_all_cb(struct iio_cb_buffer *cb_buff)
 {
+        kfree(cb_buff->buffer.scan_mask);
         iio_channel_release_all(cb_buff->channels);
         kfree(cb_buff);
 }
diff --git a/drivers/iio/frequency/adf4350.c b/drivers/iio/frequency/adf4350.c
index a884252ac66b..e76d4ace53ff 100644
--- a/drivers/iio/frequency/adf4350.c
+++ b/drivers/iio/frequency/adf4350.c
@@ -212,7 +212,7 @@ static int adf4350_set_freq(struct adf4350_state *st, unsigned long long freq)
                 (pdata->r2_user_settings & (ADF4350_REG2_PD_POLARITY_POS |
                 ADF4350_REG2_LDP_6ns | ADF4350_REG2_LDF_INT_N |
                 ADF4350_REG2_CHARGE_PUMP_CURR_uA(5000) |
-                ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x9)));
+                ADF4350_REG2_MUXOUT(0x7) | ADF4350_REG2_NOISE_MODE(0x3)));
 
         st->regs[ADF4350_REG3] = pdata->r3_user_settings &
                                  (ADF4350_REG3_12BIT_CLKDIV(0xFFF) |
diff --git a/drivers/iio/inkern.c b/drivers/iio/inkern.c
index 795d100b4c36..98ddc323add0 100644
--- a/drivers/iio/inkern.c
+++ b/drivers/iio/inkern.c
@@ -124,7 +124,7 @@ static int __of_iio_channel_get(struct iio_channel *channel,
         channel->indio_dev = indio_dev;
         index = iiospec.args_count ? iiospec.args[0] : 0;
         if (index >= indio_dev->num_channels) {
-                return -EINVAL;
+                err = -EINVAL;
                 goto err_put;
         }
         channel->channel = &indio_dev->channels[index];
@@ -450,7 +450,7 @@ static int iio_convert_raw_to_processed_unlocked(struct iio_channel *chan,
         s64 raw64 = raw;
         int ret;
 
-        ret = iio_channel_read(chan, &offset, NULL, IIO_CHAN_INFO_SCALE);
+        ret = iio_channel_read(chan, &offset, NULL, IIO_CHAN_INFO_OFFSET);
         if (ret == 0)
                 raw64 += offset;
 
diff --git a/drivers/infiniband/hw/qib/qib_keys.c b/drivers/infiniband/hw/qib/qib_keys.c
index 81c7b73695d2..3b9afccaaade 100644
--- a/drivers/infiniband/hw/qib/qib_keys.c
+++ b/drivers/infiniband/hw/qib/qib_keys.c
@@ -61,7 +61,7 @@ int qib_alloc_lkey(struct qib_mregion *mr, int dma_region)
         if (dma_region) {
                 struct qib_mregion *tmr;
 
-                tmr = rcu_dereference(dev->dma_mr);
+                tmr = rcu_access_pointer(dev->dma_mr);
                 if (!tmr) {
                         qib_get_mr(mr);
                         rcu_assign_pointer(dev->dma_mr, mr);
diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.c b/drivers/infiniband/ulp/iser/iscsi_iser.c
index f19b0998a53c..2e84ef859c5b 100644
--- a/drivers/infiniband/ulp/iser/iscsi_iser.c
+++ b/drivers/infiniband/ulp/iser/iscsi_iser.c
@@ -5,6 +5,7 @@
  * Copyright (C) 2004 Alex Aizman
  * Copyright (C) 2005 Mike Christie
  * Copyright (c) 2005, 2006 Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  * maintained by openib-general@openib.org
  *
  * This software is available to you under a choice of one of two
diff --git a/drivers/infiniband/ulp/iser/iscsi_iser.h b/drivers/infiniband/ulp/iser/iscsi_iser.h
index 06f578cde75b..4f069c0d4c04 100644
--- a/drivers/infiniband/ulp/iser/iscsi_iser.h
+++ b/drivers/infiniband/ulp/iser/iscsi_iser.h
@@ -8,6 +8,7 @@
  *
  * Copyright (c) 2004, 2005, 2006 Voltaire, Inc. All rights reserved.
  * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
diff --git a/drivers/infiniband/ulp/iser/iser_initiator.c b/drivers/infiniband/ulp/iser/iser_initiator.c
index a00ccd1ca333..b6d81a86c976 100644
--- a/drivers/infiniband/ulp/iser/iser_initiator.c
+++ b/drivers/infiniband/ulp/iser/iser_initiator.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004, 2005, 2006 Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
diff --git a/drivers/infiniband/ulp/iser/iser_memory.c b/drivers/infiniband/ulp/iser/iser_memory.c
index 68ebb7fe072a..7827baf455a1 100644
--- a/drivers/infiniband/ulp/iser/iser_memory.c
+++ b/drivers/infiniband/ulp/iser/iser_memory.c
@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2004, 2005, 2006 Voltaire, Inc. All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
diff --git a/drivers/infiniband/ulp/iser/iser_verbs.c b/drivers/infiniband/ulp/iser/iser_verbs.c
index 5278916c3103..2c4941d0656b 100644
--- a/drivers/infiniband/ulp/iser/iser_verbs.c
+++ b/drivers/infiniband/ulp/iser/iser_verbs.c
@@ -1,6 +1,7 @@
 /*
  * Copyright (c) 2004, 2005, 2006 Voltaire, Inc. All rights reserved.
  * Copyright (c) 2005, 2006 Cisco Systems.  All rights reserved.
+ * Copyright (c) 2013 Mellanox Technologies. All rights reserved.
  *
  * This software is available to you under a choice of one of two
  * licenses.  You may choose to be licensed under the terms of the GNU
@@ -292,10 +293,10 @@ out_err:
 }
 
 /**
- * releases the FMR pool, QP and CMA ID objects, returns 0 on success,
+ * releases the FMR pool and QP objects, returns 0 on success,
  * -1 on failure
  */
-static int iser_free_ib_conn_res(struct iser_conn *ib_conn, int can_destroy_id)
+static int iser_free_ib_conn_res(struct iser_conn *ib_conn)
 {
         int cq_index;
         BUG_ON(ib_conn == NULL);
@@ -314,13 +315,9 @@ static int iser_free_ib_conn_res(struct iser_conn *ib_conn, int can_destroy_id)
 
                 rdma_destroy_qp(ib_conn->cma_id);
         }
-        /* if cma handler context, the caller acts s.t the cma destroy the id */
-        if (ib_conn->cma_id != NULL && can_destroy_id)
-                rdma_destroy_id(ib_conn->cma_id);
 
         ib_conn->fmr_pool = NULL;
         ib_conn->qp       = NULL;
-        ib_conn->cma_id   = NULL;
         kfree(ib_conn->page_vec);
 
         if (ib_conn->login_buf) {
@@ -415,11 +412,16 @@ static void iser_conn_release(struct iser_conn *ib_conn, int can_destroy_id)
         list_del(&ib_conn->conn_list);
         mutex_unlock(&ig.connlist_mutex);
         iser_free_rx_descriptors(ib_conn);
-        iser_free_ib_conn_res(ib_conn, can_destroy_id);
+        iser_free_ib_conn_res(ib_conn);
         ib_conn->device = NULL;
         /* on EVENT_ADDR_ERROR there's no device yet for this conn */
         if (device != NULL)
                 iser_device_try_release(device);
+        /* if cma handler context, the caller actually destroy the id */
+        if (ib_conn->cma_id != NULL && can_destroy_id) {
+                rdma_destroy_id(ib_conn->cma_id);
+                ib_conn->cma_id = NULL;
+        }
         iscsi_destroy_endpoint(ib_conn->ep);
 }
 
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.c b/drivers/infiniband/ulp/srpt/ib_srpt.c
index b08ca7a9f76b..3f3f0416fbdd 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.c
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.c
@@ -2227,6 +2227,27 @@ static void srpt_close_ch(struct srpt_rdma_ch *ch)
 }
 
 /**
+ * srpt_shutdown_session() - Whether or not a session may be shut down.
+ */
+static int srpt_shutdown_session(struct se_session *se_sess)
+{
+        struct srpt_rdma_ch *ch = se_sess->fabric_sess_ptr;
+        unsigned long flags;
+
+        spin_lock_irqsave(&ch->spinlock, flags);
+        if (ch->in_shutdown) {
+                spin_unlock_irqrestore(&ch->spinlock, flags);
+                return true;
+        }
+
+        ch->in_shutdown = true;
+        target_sess_cmd_list_set_waiting(se_sess);
+        spin_unlock_irqrestore(&ch->spinlock, flags);
+
+        return true;
+}
+
+/**
  * srpt_drain_channel() - Drain a channel by resetting the IB queue pair.
  * @cm_id: Pointer to the CM ID of the channel to be drained.
  *
@@ -2264,6 +2285,9 @@ static void srpt_drain_channel(struct ib_cm_id *cm_id)
         spin_unlock_irq(&sdev->spinlock);
 
         if (do_reset) {
+                if (ch->sess)
+                        srpt_shutdown_session(ch->sess);
+
                 ret = srpt_ch_qp_err(ch);
                 if (ret < 0)
                         printk(KERN_ERR "Setting queue pair in error state"
@@ -2328,7 +2352,7 @@ static void srpt_release_channel_work(struct work_struct *w)
         se_sess = ch->sess;
         BUG_ON(!se_sess);
 
-        target_wait_for_sess_cmds(se_sess, 0);
+        target_wait_for_sess_cmds(se_sess);
 
         transport_deregister_session_configfs(se_sess);
         transport_deregister_session(se_sess);
@@ -3467,14 +3491,6 @@ static void srpt_release_cmd(struct se_cmd *se_cmd)
 }
 
 /**
- * srpt_shutdown_session() - Whether or not a session may be shut down.
- */
-static int srpt_shutdown_session(struct se_session *se_sess)
-{
-        return true;
-}
-
-/**
  * srpt_close_session() - Forcibly close a session.
  *
  * Callback function invoked by the TCM core to clean up sessions associated
diff --git a/drivers/infiniband/ulp/srpt/ib_srpt.h b/drivers/infiniband/ulp/srpt/ib_srpt.h
index 4caf55cda7b1..3dae156905de 100644
--- a/drivers/infiniband/ulp/srpt/ib_srpt.h
+++ b/drivers/infiniband/ulp/srpt/ib_srpt.h
@@ -325,6 +325,7 @@ struct srpt_rdma_ch {
         u8                      sess_name[36];
         struct work_struct      release_work;
         struct completion       *release_done;
+        bool                    in_shutdown;
 };
 
 /**
diff --git a/drivers/input/mouse/synaptics.c b/drivers/input/mouse/synaptics.c
index 2f78538e09d0..b2420ae19e14 100644
--- a/drivers/input/mouse/synaptics.c
+++ b/drivers/input/mouse/synaptics.c
@@ -1379,6 +1379,7 @@ static int synaptics_reconnect(struct psmouse *psmouse)
 {
         struct synaptics_data *priv = psmouse->private;
         struct synaptics_data old_priv = *priv;
+        unsigned char param[2];
         int retry = 0;
         int error;
 
@@ -1394,6 +1395,7 @@ static int synaptics_reconnect(struct psmouse *psmouse)
                          */
                         ssleep(1);
                 }
+                ps2_command(&psmouse->ps2dev, param, PSMOUSE_CMD_GETID);
                 error = synaptics_detect(psmouse, 0);
         } while (error && ++retry < 3);
 
diff --git a/drivers/input/tablet/wacom_wac.c b/drivers/input/tablet/wacom_wac.c
index 5c68e4486845..518282da6d85 100644
--- a/drivers/input/tablet/wacom_wac.c
+++ b/drivers/input/tablet/wacom_wac.c
@@ -1966,7 +1966,8 @@ static const struct wacom_features wacom_features_0xF4 =
           63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES };
 static const struct wacom_features wacom_features_0xF8 =
         { "Wacom Cintiq 24HD touch", WACOM_PKGLEN_INTUOS,   104480, 65600, 2047, /* Pen */
-          63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, .oVid = USB_VENDOR_ID_WACOM, .oPid = 0xf6 };
+          63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES,
+          .oVid = USB_VENDOR_ID_WACOM, .oPid = 0xf6 };
 static const struct wacom_features wacom_features_0xF6 =
         { "Wacom Cintiq 24HD touch", .type = WACOM_24HDT, /* Touch */
           .oVid = USB_VENDOR_ID_WACOM, .oPid = 0xf8, .touch_max = 10 };
@@ -2009,7 +2010,8 @@ static const struct wacom_features wacom_features_0xFA =
           63, WACOM_22HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES };
 static const struct wacom_features wacom_features_0x5B =
         { "Wacom Cintiq 22HDT", WACOM_PKGLEN_INTUOS,      95840, 54260, 2047,
-          63, WACOM_24HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES, .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x5e };
+          63, WACOM_22HD, WACOM_INTUOS3_RES, WACOM_INTUOS3_RES,
+          .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x5e };
 static const struct wacom_features wacom_features_0x5E =
         { "Wacom Cintiq 22HDT", .type = WACOM_24HDT,
           .oVid = USB_VENDOR_ID_WACOM, .oPid = 0x5b, .touch_max = 10 };
@@ -2042,7 +2044,7 @@ static const struct wacom_features wacom_features_0xE5 =
 static const struct wacom_features wacom_features_0xE6 =
         { "Wacom ISDv4 E6",       WACOM_PKGLEN_TPC2FG,    27760, 15694,  255,
           0, TABLETPC2FG, WACOM_INTUOS_RES, WACOM_INTUOS_RES,
-        .touch_max = 2 };
+          .touch_max = 2 };
 static const struct wacom_features wacom_features_0xEC =
         { "Wacom ISDv4 EC",       WACOM_PKGLEN_GRAPHIRE,  25710, 14500,  255,
           0, TABLETPC,    WACOM_INTUOS_RES, WACOM_INTUOS_RES };
diff --git a/drivers/irqchip/irq-mxs.c b/drivers/irqchip/irq-mxs.c
index 29889bbdcc6d..63b3d4eb0ef7 100644
--- a/drivers/irqchip/irq-mxs.c
+++ b/drivers/irqchip/irq-mxs.c
@@ -76,16 +76,10 @@ asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs)
 {
         u32 irqnr;
 
-        do {
-                irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
-                if (irqnr != 0x7f) {
-                        __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
-                        irqnr = irq_find_mapping(icoll_domain, irqnr);
-                        handle_IRQ(irqnr, regs);
-                        continue;
-                }
-                break;
-        } while (1);
+        irqnr = __raw_readl(icoll_base + HW_ICOLL_STAT_OFFSET);
+        __raw_writel(irqnr, icoll_base + HW_ICOLL_VECTOR);
+        irqnr = irq_find_mapping(icoll_domain, irqnr);
+        handle_IRQ(irqnr, regs);
 }
 
 static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
diff --git a/drivers/irqchip/irq-versatile-fpga.c b/drivers/irqchip/irq-versatile-fpga.c
index 065b7a31a478..47a52ab580d8 100644
--- a/drivers/irqchip/irq-versatile-fpga.c
+++ b/drivers/irqchip/irq-versatile-fpga.c
@@ -119,7 +119,7 @@ static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
 
         /* Skip invalid IRQs, only register handlers for the real ones */
         if (!(f->valid & BIT(hwirq)))
-                return -ENOTSUPP;
+                return -EPERM;
         irq_set_chip_data(irq, f);
         irq_set_chip_and_handler(irq, &f->chip,
                                 handle_level_irq);
diff --git a/drivers/irqchip/irq-vic.c b/drivers/irqchip/irq-vic.c
index 884d11c7355f..2bbb00404cf5 100644
--- a/drivers/irqchip/irq-vic.c
+++ b/drivers/irqchip/irq-vic.c
@@ -197,7 +197,7 @@ static int vic_irqdomain_map(struct irq_domain *d, unsigned int irq,
 
         /* Skip invalid IRQs, only register handlers for the real ones */
         if (!(v->valid_sources & (1 << hwirq)))
-                return -ENOTSUPP;
+                return -EPERM;
         irq_set_chip_and_handler(irq, &vic_chip, handle_level_irq);
         irq_set_chip_data(irq, v->base);
         set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
diff --git a/drivers/md/bcache/Kconfig b/drivers/md/bcache/Kconfig
index 05c220d05e23..f950c9d29f3e 100644
--- a/drivers/md/bcache/Kconfig
+++ b/drivers/md/bcache/Kconfig
@@ -1,7 +1,6 @@
 
 config BCACHE
         tristate "Block device as cache"
-        select CLOSURES
         ---help---
         Allows a block device to be used as cache for other devices; uses
         a btree for indexing and the layout is optimized for SSDs.
diff --git a/drivers/md/bcache/bcache.h b/drivers/md/bcache/bcache.h
index 340146d7c17f..d3e15b42a4ab 100644
--- a/drivers/md/bcache/bcache.h
+++ b/drivers/md/bcache/bcache.h
@@ -1241,7 +1241,7 @@ void bch_cache_set_stop(struct cache_set *);
 struct cache_set *bch_cache_set_alloc(struct cache_sb *);
 void bch_btree_cache_free(struct cache_set *);
 int bch_btree_cache_alloc(struct cache_set *);
-void bch_writeback_init_cached_dev(struct cached_dev *);
+void bch_cached_dev_writeback_init(struct cached_dev *);
 void bch_moving_init_cache_set(struct cache_set *);
 
 void bch_cache_allocator_exit(struct cache *ca);
diff --git a/drivers/md/bcache/stats.c b/drivers/md/bcache/stats.c
index 64e679449c2a..b8730e714d69 100644
--- a/drivers/md/bcache/stats.c
+++ b/drivers/md/bcache/stats.c
@@ -93,24 +93,6 @@ static struct attribute *bch_stats_files[] = {
 };
 static KTYPE(bch_stats);
 
-static void scale_accounting(unsigned long data);
-
-void bch_cache_accounting_init(struct cache_accounting *acc,
-                               struct closure *parent)
-{
-        kobject_init(&acc->total.kobj,          &bch_stats_ktype);
-        kobject_init(&acc->five_minute.kobj,    &bch_stats_ktype);
-        kobject_init(&acc->hour.kobj,           &bch_stats_ktype);
-        kobject_init(&acc->day.kobj,            &bch_stats_ktype);
-
-        closure_init(&acc->cl, parent);
-        init_timer(&acc->timer);
-        acc->timer.expires      = jiffies + accounting_delay;
-        acc->timer.data         = (unsigned long) acc;
-        acc->timer.function     = scale_accounting;
-        add_timer(&acc->timer);
-}
-
 int bch_cache_accounting_add_kobjs(struct cache_accounting *acc,
                                    struct kobject *parent)
 {
@@ -244,3 +226,19 @@ void bch_mark_sectors_bypassed(struct search *s, int sectors)
         atomic_add(sectors, &dc->accounting.collector.sectors_bypassed);
         atomic_add(sectors, &s->op.c->accounting.collector.sectors_bypassed);
 }
+
+void bch_cache_accounting_init(struct cache_accounting *acc,
+                               struct closure *parent)
+{
+        kobject_init(&acc->total.kobj,          &bch_stats_ktype);
+        kobject_init(&acc->five_minute.kobj,    &bch_stats_ktype);
+        kobject_init(&acc->hour.kobj,           &bch_stats_ktype);
+        kobject_init(&acc->day.kobj,            &bch_stats_ktype);
+
+        closure_init(&acc->cl, parent);
+        init_timer(&acc->timer);
+        acc->timer.expires      = jiffies + accounting_delay;
+        acc->timer.data         = (unsigned long) acc;
+        acc->timer.function     = scale_accounting;
+        add_timer(&acc->timer);
+}
diff --git a/drivers/md/bcache/super.c b/drivers/md/bcache/super.c
index c8046bc4aa57..f88e2b653a3f 100644
--- a/drivers/md/bcache/super.c
+++ b/drivers/md/bcache/super.c
@@ -634,11 +634,10 @@ static int open_dev(struct block_device *b, fmode_t mode)
         return 0;
 }
 
-static int release_dev(struct gendisk *b, fmode_t mode)
+static void release_dev(struct gendisk *b, fmode_t mode)
 {
         struct bcache_device *d = b->private_data;
         closure_put(&d->cl);
-        return 0;
 }
 
 static int ioctl_dev(struct block_device *b, fmode_t mode,
@@ -732,8 +731,7 @@ static void bcache_device_free(struct bcache_device *d)
 
         if (d->c)
                 bcache_device_detach(d);
-
-        if (d->disk)
+        if (d->disk && d->disk->flags & GENHD_FL_UP)
                 del_gendisk(d->disk);
         if (d->disk && d->disk->queue)
                 blk_cleanup_queue(d->disk->queue);
@@ -756,12 +754,9 @@ static int bcache_device_init(struct bcache_device *d, unsigned block_size)
         if (!(d->bio_split = bioset_create(4, offsetof(struct bbio, bio))) ||
             !(d->unaligned_bvec = mempool_create_kmalloc_pool(1,
                                 sizeof(struct bio_vec) * BIO_MAX_PAGES)) ||
-            bio_split_pool_init(&d->bio_split_hook))
-
-                return -ENOMEM;
-
-        d->disk = alloc_disk(1);
-        if (!d->disk)
+            bio_split_pool_init(&d->bio_split_hook) ||
+            !(d->disk = alloc_disk(1)) ||
+            !(q = blk_alloc_queue(GFP_KERNEL)))
                 return -ENOMEM;
 
         snprintf(d->disk->disk_name, DISK_NAME_LEN, "bcache%i", bcache_minor);
@@ -771,10 +766,6 @@ static int bcache_device_init(struct bcache_device *d, unsigned block_size)
         d->disk->fops           = &bcache_ops;
         d->disk->private_data   = d;
 
-        q = blk_alloc_queue(GFP_KERNEL);
-        if (!q)
-                return -ENOMEM;
-
         blk_queue_make_request(q, NULL);
         d->disk->queue                  = q;
         q->queuedata                    = d;
@@ -999,14 +990,17 @@ static void cached_dev_free(struct closure *cl)
 
         mutex_lock(&bch_register_lock);
 
-        bd_unlink_disk_holder(dc->bdev, dc->disk.disk);
+        if (atomic_read(&dc->running))
+                bd_unlink_disk_holder(dc->bdev, dc->disk.disk);
         bcache_device_free(&dc->disk);
         list_del(&dc->list);
 
         mutex_unlock(&bch_register_lock);
 
         if (!IS_ERR_OR_NULL(dc->bdev)) {
-                blk_sync_queue(bdev_get_queue(dc->bdev));
+                if (dc->bdev->bd_disk)
+                        blk_sync_queue(bdev_get_queue(dc->bdev));
+
                 blkdev_put(dc->bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
         }
 
@@ -1028,73 +1022,67 @@ static void cached_dev_flush(struct closure *cl)
 
 static int cached_dev_init(struct cached_dev *dc, unsigned block_size)
 {
-        int err;
+        int ret;
         struct io *io;
-
-        closure_init(&dc->disk.cl, NULL);
-        set_closure_fn(&dc->disk.cl, cached_dev_flush, system_wq);
+        struct request_queue *q = bdev_get_queue(dc->bdev);
 
         __module_get(THIS_MODULE);
         INIT_LIST_HEAD(&dc->list);
+        closure_init(&dc->disk.cl, NULL);
+        set_closure_fn(&dc->disk.cl, cached_dev_flush, system_wq);
         kobject_init(&dc->disk.kobj, &bch_cached_dev_ktype);
-
-        bch_cache_accounting_init(&dc->accounting, &dc->disk.cl);
-
-        err = bcache_device_init(&dc->disk, block_size);
-        if (err)
-                goto err;
-
-        spin_lock_init(&dc->io_lock);
-        closure_init_unlocked(&dc->sb_write);
         INIT_WORK(&dc->detach, cached_dev_detach_finish);
+        closure_init_unlocked(&dc->sb_write);
+        INIT_LIST_HEAD(&dc->io_lru);
+        spin_lock_init(&dc->io_lock);
+        bch_cache_accounting_init(&dc->accounting, &dc->disk.cl);
 
         dc->sequential_merge            = true;
         dc->sequential_cutoff           = 4 << 20;
 
-        INIT_LIST_HEAD(&dc->io_lru);
-        dc->sb_bio.bi_max_vecs  = 1;
-        dc->sb_bio.bi_io_vec    = dc->sb_bio.bi_inline_vecs;
-
         for (io = dc->io; io < dc->io + RECENT_IO; io++) {
                 list_add(&io->lru, &dc->io_lru);
                 hlist_add_head(&io->hash, dc->io_hash + RECENT_IO);
         }
 
-        bch_writeback_init_cached_dev(dc);
+        ret = bcache_device_init(&dc->disk, block_size);
+        if (ret)
+                return ret;
+
+        set_capacity(dc->disk.disk,
+                     dc->bdev->bd_part->nr_sects - dc->sb.data_offset);
+
+        dc->disk.disk->queue->backing_dev_info.ra_pages =
+                max(dc->disk.disk->queue->backing_dev_info.ra_pages,
+                    q->backing_dev_info.ra_pages);
+
+        bch_cached_dev_request_init(dc);
+        bch_cached_dev_writeback_init(dc);
         return 0;
-err:
-        bcache_device_stop(&dc->disk);
-        return err;
 }
 
 /* Cached device - bcache superblock */
 
-static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
+static void register_bdev(struct cache_sb *sb, struct page *sb_page,
                                  struct block_device *bdev,
                                  struct cached_dev *dc)
 {
         char name[BDEVNAME_SIZE];
         const char *err = "cannot allocate memory";
-        struct gendisk *g;
         struct cache_set *c;
 
-        if (!dc || cached_dev_init(dc, sb->block_size << 9) != 0)
-                return err;
-
         memcpy(&dc->sb, sb, sizeof(struct cache_sb));
-        dc->sb_bio.bi_io_vec[0].bv_page = sb_page;
         dc->bdev = bdev;
         dc->bdev->bd_holder = dc;
 
-        g = dc->disk.disk;
-
-        set_capacity(g, dc->bdev->bd_part->nr_sects - dc->sb.data_offset);
-
-        g->queue->backing_dev_info.ra_pages =
-                max(g->queue->backing_dev_info.ra_pages,
-                    bdev->bd_queue->backing_dev_info.ra_pages);
+        bio_init(&dc->sb_bio);
+        dc->sb_bio.bi_max_vecs  = 1;
+        dc->sb_bio.bi_io_vec    = dc->sb_bio.bi_inline_vecs;
+        dc->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        get_page(sb_page);
 
-        bch_cached_dev_request_init(dc);
+        if (cached_dev_init(dc, sb->block_size << 9))
+                goto err;
 
         err = "error creating kobject";
         if (kobject_add(&dc->disk.kobj, &part_to_dev(bdev->bd_part)->kobj,
@@ -1103,6 +1091,8 @@ static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
         if (bch_cache_accounting_add_kobjs(&dc->accounting, &dc->disk.kobj))
                 goto err;
 
+        pr_info("registered backing device %s", bdevname(bdev, name));
+
         list_add(&dc->list, &uncached_devices);
         list_for_each_entry(c, &bch_cache_sets, list)
                 bch_cached_dev_attach(dc, c);
@@ -1111,15 +1101,10 @@ static const char *register_bdev(struct cache_sb *sb, struct page *sb_page,
             BDEV_STATE(&dc->sb) == BDEV_STATE_STALE)
                 bch_cached_dev_run(dc);
 
-        return NULL;
+        return;
 err:
-        kobject_put(&dc->disk.kobj);
         pr_notice("error opening %s: %s", bdevname(bdev, name), err);
-        /*
-         * Return NULL instead of an error because kobject_put() cleans
-         * everything up
-         */
-        return NULL;
+        bcache_device_stop(&dc->disk);
 }
 
 /* Flash only volumes */
@@ -1717,20 +1702,11 @@ static int cache_alloc(struct cache_sb *sb, struct cache *ca)
         size_t free;
         struct bucket *b;
 
-        if (!ca)
-                return -ENOMEM;
-
         __module_get(THIS_MODULE);
         kobject_init(&ca->kobj, &bch_cache_ktype);
 
-        memcpy(&ca->sb, sb, sizeof(struct cache_sb));
-
         INIT_LIST_HEAD(&ca->discards);
 
-        bio_init(&ca->sb_bio);
-        ca->sb_bio.bi_max_vecs  = 1;
-        ca->sb_bio.bi_io_vec    = ca->sb_bio.bi_inline_vecs;
-
         bio_init(&ca->journal.bio);
         ca->journal.bio.bi_max_vecs = 8;
         ca->journal.bio.bi_io_vec = ca->journal.bio.bi_inline_vecs;
@@ -1742,18 +1718,17 @@ static int cache_alloc(struct cache_sb *sb, struct cache *ca)
             !init_fifo(&ca->free_inc,   free << 2, GFP_KERNEL) ||
             !init_fifo(&ca->unused,     free << 2, GFP_KERNEL) ||
             !init_heap(&ca->heap,       free << 3, GFP_KERNEL) ||
-            !(ca->buckets       = vmalloc(sizeof(struct bucket) *
+            !(ca->buckets       = vzalloc(sizeof(struct bucket) *
                                           ca->sb.nbuckets)) ||
             !(ca->prio_buckets  = kzalloc(sizeof(uint64_t) * prio_buckets(ca) *
                                           2, GFP_KERNEL)) ||
             !(ca->disk_buckets  = alloc_bucket_pages(GFP_KERNEL, ca)) ||
             !(ca->alloc_workqueue = alloc_workqueue("bch_allocator", 0, 1)) ||
             bio_split_pool_init(&ca->bio_split_hook))
-                goto err;
+                return -ENOMEM;
 
         ca->prio_last_buckets = ca->prio_buckets + prio_buckets(ca);
 
-        memset(ca->buckets, 0, ca->sb.nbuckets * sizeof(struct bucket));
         for_each_bucket(b, ca)
                 atomic_set(&b->pin, 0);
 
@@ -1766,22 +1741,28 @@ err:
         return -ENOMEM;
 }
 
-static const char *register_cache(struct cache_sb *sb, struct page *sb_page,
+static void register_cache(struct cache_sb *sb, struct page *sb_page,
                                   struct block_device *bdev, struct cache *ca)
 {
         char name[BDEVNAME_SIZE];
         const char *err = "cannot allocate memory";
 
-        if (cache_alloc(sb, ca) != 0)
-                return err;
-
-        ca->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        memcpy(&ca->sb, sb, sizeof(struct cache_sb));
         ca->bdev = bdev;
         ca->bdev->bd_holder = ca;
 
+        bio_init(&ca->sb_bio);
+        ca->sb_bio.bi_max_vecs  = 1;
+        ca->sb_bio.bi_io_vec    = ca->sb_bio.bi_inline_vecs;
+        ca->sb_bio.bi_io_vec[0].bv_page = sb_page;
+        get_page(sb_page);
+
         if (blk_queue_discard(bdev_get_queue(ca->bdev)))
                 ca->discard = CACHE_DISCARD(&ca->sb);
 
+        if (cache_alloc(sb, ca) != 0)
+                goto err;
+
         err = "error creating kobject";
         if (kobject_add(&ca->kobj, &part_to_dev(bdev->bd_part)->kobj, "bcache"))
                 goto err;
@@ -1791,15 +1772,10 @@ static const char *register_cache(struct cache_sb *sb, struct page *sb_page,
                 goto err;
 
         pr_info("registered cache device %s", bdevname(bdev, name));
-
-        return NULL;
+        return;
 err:
+        pr_notice("error opening %s: %s", bdevname(bdev, name), err);
         kobject_put(&ca->kobj);
-        pr_info("error opening %s: %s", bdevname(bdev, name), err);
-        /* Return NULL instead of an error because kobject_put() cleans
-         * everything up
-         */
-        return NULL;
 }
 
 /* Global interfaces/init */
@@ -1833,12 +1809,15 @@ static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr,
         bdev = blkdev_get_by_path(strim(path),
                                   FMODE_READ|FMODE_WRITE|FMODE_EXCL,
                                   sb);
-        if (bdev == ERR_PTR(-EBUSY))
-                err = "device busy";
-
-        if (IS_ERR(bdev) ||
-            set_blocksize(bdev, 4096))
+        if (IS_ERR(bdev)) {
+                if (bdev == ERR_PTR(-EBUSY))
+                        err = "device busy";
                 goto err;
+        }
+
+        err = "failed to set blocksize";
+        if (set_blocksize(bdev, 4096))
+                goto err_close;
 
         err = read_super(sb, bdev, &sb_page);
         if (err)
@@ -1846,33 +1825,33 @@ static ssize_t register_bcache(struct kobject *k, struct kobj_attribute *attr,
 
         if (SB_IS_BDEV(sb)) {
                 struct cached_dev *dc = kzalloc(sizeof(*dc), GFP_KERNEL);
+                if (!dc)
+                        goto err_close;
 
-                err = register_bdev(sb, sb_page, bdev, dc);
+                register_bdev(sb, sb_page, bdev, dc);
         } else {
                 struct cache *ca = kzalloc(sizeof(*ca), GFP_KERNEL);
+                if (!ca)
+                        goto err_close;
 
-                err = register_cache(sb, sb_page, bdev, ca);
+                register_cache(sb, sb_page, bdev, ca);
         }
-
-        if (err) {
-                /* register_(bdev|cache) will only return an error if they
-                 * didn't get far enough to create the kobject - if they did,
-                 * the kobject destructor will do this cleanup.
-                 */
+out:
+        if (sb_page)
                 put_page(sb_page);
-err_close:
-                blkdev_put(bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
-err:
-                if (attr != &ksysfs_register_quiet)
-                        pr_info("error opening %s: %s", path, err);
-                ret = -EINVAL;
-        }
-
         kfree(sb);
         kfree(path);
         mutex_unlock(&bch_register_lock);
         module_put(THIS_MODULE);
         return ret;
+
+err_close:
+        blkdev_put(bdev, FMODE_READ|FMODE_WRITE|FMODE_EXCL);
+err:
+        if (attr != &ksysfs_register_quiet)
+                pr_info("error opening %s: %s", path, err);
+        ret = -EINVAL;
+        goto out;
 }
 
 static int bcache_reboot(struct notifier_block *n, unsigned long code, void *x)
diff --git a/drivers/md/bcache/writeback.c b/drivers/md/bcache/writeback.c
index 93e7e31a4bd3..2714ed3991d1 100644
--- a/drivers/md/bcache/writeback.c
+++ b/drivers/md/bcache/writeback.c
@@ -375,7 +375,7 @@ err:
         refill_dirty(cl);
 }
 
-void bch_writeback_init_cached_dev(struct cached_dev *dc)
+void bch_cached_dev_writeback_init(struct cached_dev *dc)
 {
         closure_init_unlocked(&dc->writeback);
         init_rwsem(&dc->writeback_lock);
diff --git a/drivers/md/md.c b/drivers/md/md.c
index 681d1099a2d5..9b82377a833b 100644
--- a/drivers/md/md.c
+++ b/drivers/md/md.c
@@ -5268,8 +5268,8 @@ static void md_clean(struct mddev *mddev)
 
 static void __md_stop_writes(struct mddev *mddev)
 {
+        set_bit(MD_RECOVERY_FROZEN, &mddev->recovery);
         if (mddev->sync_thread) {
-                set_bit(MD_RECOVERY_FROZEN, &mddev->recovery);
                 set_bit(MD_RECOVERY_INTR, &mddev->recovery);
                 md_reap_sync_thread(mddev);
         }
diff --git a/drivers/md/raid1.c b/drivers/md/raid1.c
index 55951182af73..6e17f8181c4b 100644
--- a/drivers/md/raid1.c
+++ b/drivers/md/raid1.c
@@ -417,7 +417,17 @@ static void raid1_end_write_request(struct bio *bio, int error)
 
                 r1_bio->bios[mirror] = NULL;
                 to_put = bio;
-                set_bit(R1BIO_Uptodate, &r1_bio->state);
+                /*
+                 * Do not set R1BIO_Uptodate if the current device is
+                 * rebuilding or Faulty. This is because we cannot use
+                 * such device for properly reading the data back (we could
+                 * potentially use it, if the current write would have felt
+                 * before rdev->recovery_offset, but for simplicity we don't
+                 * check this here.
+                 */
+                if (test_bit(In_sync, &conf->mirrors[mirror].rdev->flags) &&
+                    !test_bit(Faulty, &conf->mirrors[mirror].rdev->flags))
+                        set_bit(R1BIO_Uptodate, &r1_bio->state);
 
                 /* Maybe we can clear some bad blocks. */
                 if (is_badblock(conf->mirrors[mirror].rdev,
@@ -870,17 +880,17 @@ static void allow_barrier(struct r1conf *conf)
         wake_up(&conf->wait_barrier);
 }
 
-static void freeze_array(struct r1conf *conf)
+static void freeze_array(struct r1conf *conf, int extra)
 {
         /* stop syncio and normal IO and wait for everything to
          * go quite.
          * We increment barrier and nr_waiting, and then
-         * wait until nr_pending match nr_queued+1
+         * wait until nr_pending match nr_queued+extra
          * This is called in the context of one normal IO request
          * that has failed. Thus any sync request that might be pending
          * will be blocked by nr_pending, and we need to wait for
          * pending IO requests to complete or be queued for re-try.
-         * Thus the number queued (nr_queued) plus this request (1)
+         * Thus the number queued (nr_queued) plus this request (extra)
          * must match the number of pending IOs (nr_pending) before
          * we continue.
          */
@@ -888,7 +898,7 @@ static void freeze_array(struct r1conf *conf)
         conf->barrier++;
         conf->nr_waiting++;
         wait_event_lock_irq_cmd(conf->wait_barrier,
-                                conf->nr_pending == conf->nr_queued+1,
+                                conf->nr_pending == conf->nr_queued+extra,
                                 conf->resync_lock,
                                 flush_pending_writes(conf));
         spin_unlock_irq(&conf->resync_lock);
@@ -1544,8 +1554,8 @@ static int raid1_add_disk(struct mddev *mddev, struct md_rdev *rdev)
                  * we wait for all outstanding requests to complete.
                  */
                 synchronize_sched();
-                raise_barrier(conf);
-                lower_barrier(conf);
+                freeze_array(conf, 0);
+                unfreeze_array(conf);
                 clear_bit(Unmerged, &rdev->flags);
         }
         md_integrity_add_rdev(rdev, mddev);
@@ -1595,11 +1605,11 @@ static int raid1_remove_disk(struct mddev *mddev, struct md_rdev *rdev)
                          */
                         struct md_rdev *repl =
                                 conf->mirrors[conf->raid_disks + number].rdev;
-                        raise_barrier(conf);
+                        freeze_array(conf, 0);
                         clear_bit(Replacement, &repl->flags);
                         p->rdev = repl;
                         conf->mirrors[conf->raid_disks + number].rdev = NULL;
-                        lower_barrier(conf);
+                        unfreeze_array(conf);
                         clear_bit(WantReplacement, &rdev->flags);
                 } else
                         clear_bit(WantReplacement, &rdev->flags);
@@ -2195,7 +2205,7 @@ static void handle_read_error(struct r1conf *conf, struct r1bio *r1_bio)
          * frozen
          */
         if (mddev->ro == 0) {
-                freeze_array(conf);
+                freeze_array(conf, 1);
                 fix_read_error(conf, r1_bio->read_disk,
                                r1_bio->sector, r1_bio->sectors);
                 unfreeze_array(conf);
@@ -2780,8 +2790,8 @@ static int run(struct mddev *mddev)
                 return PTR_ERR(conf);
 
         if (mddev->queue)
-                blk_queue_max_write_same_sectors(mddev->queue,
-                                                 mddev->chunk_sectors);
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
+
         rdev_for_each(rdev, mddev) {
                 if (!mddev->gendisk)
                         continue;
@@ -2963,7 +2973,7 @@ static int raid1_reshape(struct mddev *mddev)
                 return -ENOMEM;
         }
 
-        raise_barrier(conf);
+        freeze_array(conf, 0);
 
         /* ok, everything is stopped */
         oldpool = conf->r1bio_pool;
@@ -2994,7 +3004,7 @@ static int raid1_reshape(struct mddev *mddev)
         conf->raid_disks = mddev->raid_disks = raid_disks;
         mddev->delta_disks = 0;
 
-        lower_barrier(conf);
+        unfreeze_array(conf);
 
         set_bit(MD_RECOVERY_NEEDED, &mddev->recovery);
         md_wakeup_thread(mddev->thread);
diff --git a/drivers/md/raid10.c b/drivers/md/raid10.c
index 59d4daa5f4c7..6ddae2501b9a 100644
--- a/drivers/md/raid10.c
+++ b/drivers/md/raid10.c
@@ -490,7 +490,17 @@ static void raid10_end_write_request(struct bio *bio, int error)
                 sector_t first_bad;
                 int bad_sectors;
 
-                set_bit(R10BIO_Uptodate, &r10_bio->state);
+                /*
+                 * Do not set R10BIO_Uptodate if the current device is
+                 * rebuilding or Faulty. This is because we cannot use
+                 * such device for properly reading the data back (we could
+                 * potentially use it, if the current write would have felt
+                 * before rdev->recovery_offset, but for simplicity we don't
+                 * check this here.
+                 */
+                if (test_bit(In_sync, &rdev->flags) &&
+                    !test_bit(Faulty, &rdev->flags))
+                        set_bit(R10BIO_Uptodate, &r10_bio->state);
 
                 /* Maybe we can clear some bad blocks. */
                 if (is_badblock(rdev,
@@ -1055,17 +1065,17 @@ static void allow_barrier(struct r10conf *conf)
         wake_up(&conf->wait_barrier);
 }
 
-static void freeze_array(struct r10conf *conf)
+static void freeze_array(struct r10conf *conf, int extra)
 {
         /* stop syncio and normal IO and wait for everything to
          * go quiet.
          * We increment barrier and nr_waiting, and then
-         * wait until nr_pending match nr_queued+1
+         * wait until nr_pending match nr_queued+extra
          * This is called in the context of one normal IO request
          * that has failed. Thus any sync request that might be pending
          * will be blocked by nr_pending, and we need to wait for
          * pending IO requests to complete or be queued for re-try.
-         * Thus the number queued (nr_queued) plus this request (1)
+         * Thus the number queued (nr_queued) plus this request (extra)
          * must match the number of pending IOs (nr_pending) before
          * we continue.
          */
@@ -1073,7 +1083,7 @@ static void freeze_array(struct r10conf *conf)
         conf->barrier++;
         conf->nr_waiting++;
         wait_event_lock_irq_cmd(conf->wait_barrier,
-                                conf->nr_pending == conf->nr_queued+1,
+                                conf->nr_pending == conf->nr_queued+extra,
                                 conf->resync_lock,
                                 flush_pending_writes(conf));
 
@@ -1837,8 +1847,8 @@ static int raid10_add_disk(struct mddev *mddev, struct md_rdev *rdev)
                  * we wait for all outstanding requests to complete.
                  */
                 synchronize_sched();
-                raise_barrier(conf, 0);
-                lower_barrier(conf);
+                freeze_array(conf, 0);
+                unfreeze_array(conf);
                 clear_bit(Unmerged, &rdev->flags);
         }
         md_integrity_add_rdev(rdev, mddev);
@@ -2612,7 +2622,7 @@ static void handle_read_error(struct mddev *mddev, struct r10bio *r10_bio)
         r10_bio->devs[slot].bio = NULL;
 
         if (mddev->ro == 0) {
-                freeze_array(conf);
+                freeze_array(conf, 1);
                 fix_read_error(conf, mddev, r10_bio);
                 unfreeze_array(conf);
         } else
@@ -3609,8 +3619,7 @@ static int run(struct mddev *mddev)
         if (mddev->queue) {
                 blk_queue_max_discard_sectors(mddev->queue,
                                               mddev->chunk_sectors);
-                blk_queue_max_write_same_sectors(mddev->queue,
-                                                 mddev->chunk_sectors);
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
                 blk_queue_io_min(mddev->queue, chunk_size);
                 if (conf->geo.raid_disks % conf->geo.near_copies)
                         blk_queue_io_opt(mddev->queue, chunk_size * conf->geo.raid_disks);
diff --git a/drivers/md/raid5.c b/drivers/md/raid5.c
index 9359828ffe26..05e4a105b9c7 100644
--- a/drivers/md/raid5.c
+++ b/drivers/md/raid5.c
@@ -664,6 +664,7 @@ static void ops_run_io(struct stripe_head *sh, struct stripe_head_state *s)
                         if (test_bit(R5_ReadNoMerge, &sh->dev[i].flags))
                                 bi->bi_rw |= REQ_FLUSH;
 
+                        bi->bi_vcnt = 1;
                         bi->bi_io_vec[0].bv_len = STRIPE_SIZE;
                         bi->bi_io_vec[0].bv_offset = 0;
                         bi->bi_size = STRIPE_SIZE;
@@ -701,6 +702,7 @@ static void ops_run_io(struct stripe_head *sh, struct stripe_head_state *s)
                         else
                                 rbi->bi_sector = (sh->sector
                                                   + rrdev->data_offset);
+                        rbi->bi_vcnt = 1;
                         rbi->bi_io_vec[0].bv_len = STRIPE_SIZE;
                         rbi->bi_io_vec[0].bv_offset = 0;
                         rbi->bi_size = STRIPE_SIZE;
@@ -5464,7 +5466,7 @@ static int run(struct mddev *mddev)
                 if (mddev->major_version == 0 &&
                     mddev->minor_version > 90)
                         rdev->recovery_offset = reshape_offset;
-                        
+
                 if (rdev->recovery_offset < reshape_offset) {
                         /* We need to check old and new layout */
                         if (!only_parity(rdev->raid_disk,
@@ -5587,6 +5589,8 @@ static int run(struct mddev *mddev)
                  */
                 mddev->queue->limits.discard_zeroes_data = 0;
 
+                blk_queue_max_write_same_sectors(mddev->queue, 0);
+
                 rdev_for_each(rdev, mddev) {
                         disk_stack_limits(mddev->gendisk, rdev->bdev,
                                           rdev->data_offset << 9);
diff --git a/drivers/media/pci/zoran/zoran.h b/drivers/media/pci/zoran/zoran.h
index ca2754a3cd63..5e040085c2ff 100644
--- a/drivers/media/pci/zoran/zoran.h
+++ b/drivers/media/pci/zoran/zoran.h
@@ -176,7 +176,7 @@ struct zoran_fh;
 
 struct zoran_mapping {
         struct zoran_fh *fh;
-        int count;
+        atomic_t count;
 };
 
 struct zoran_buffer {
diff --git a/drivers/media/pci/zoran/zoran_driver.c b/drivers/media/pci/zoran/zoran_driver.c
index 1168a84a737d..d133c30c3fdc 100644
--- a/drivers/media/pci/zoran/zoran_driver.c
+++ b/drivers/media/pci/zoran/zoran_driver.c
@@ -2803,8 +2803,7 @@ static void
 zoran_vm_open (struct vm_area_struct *vma)
 {
         struct zoran_mapping *map = vma->vm_private_data;
-
-        map->count++;
+        atomic_inc(&map->count);
 }
 
 static void
@@ -2815,7 +2814,7 @@ zoran_vm_close (struct vm_area_struct *vma)
         struct zoran *zr = fh->zr;
         int i;
 
-        if (--map->count > 0)
+        if (!atomic_dec_and_mutex_lock(&map->count, &zr->resource_lock))
                 return;
 
         dprintk(3, KERN_INFO "%s: %s - munmap(%s)\n", ZR_DEVNAME(zr),
@@ -2828,14 +2827,16 @@ zoran_vm_close (struct vm_area_struct *vma)
         kfree(map);
 
         /* Any buffers still mapped? */
-        for (i = 0; i < fh->buffers.num_buffers; i++)
-                if (fh->buffers.buffer[i].map)
+        for (i = 0; i < fh->buffers.num_buffers; i++) {
+                if (fh->buffers.buffer[i].map) {
+                        mutex_unlock(&zr->resource_lock);
                         return;
+                }
+        }
 
         dprintk(3, KERN_INFO "%s: %s - free %s buffers\n", ZR_DEVNAME(zr),
                 __func__, mode_name(fh->map_mode));
 
-        mutex_lock(&zr->resource_lock);
 
         if (fh->map_mode == ZORAN_MAP_MODE_RAW) {
                 if (fh->buffers.active != ZORAN_FREE) {
@@ -2939,7 +2940,7 @@ zoran_mmap (struct file           *file,
                 goto mmap_unlock_and_return;
         }
         map->fh = fh;
-        map->count = 1;
+        atomic_set(&map->count, 1);
 
         vma->vm_ops = &zoran_vm_ops;
         vma->vm_flags |= VM_DONTEXPAND;
diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 0494d2769fd7..bce695d42f10 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -159,7 +159,7 @@ config VIDEO_MEM2MEM_DEINTERLACE
 
 config VIDEO_SAMSUNG_S5P_G2D
         tristate "Samsung S5P and EXYNOS4 G2D 2d graphics accelerator driver"
-        depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
+        depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
         select VIDEOBUF2_DMA_CONTIG
         select V4L2_MEM2MEM_DEV
         default n
@@ -169,7 +169,7 @@ config VIDEO_SAMSUNG_S5P_G2D
 
 config VIDEO_SAMSUNG_S5P_JPEG
         tristate "Samsung S5P/Exynos4 JPEG codec driver"
-        depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
+        depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
         select VIDEOBUF2_DMA_CONTIG
         select V4L2_MEM2MEM_DEV
         ---help---
@@ -177,7 +177,7 @@ config VIDEO_SAMSUNG_S5P_JPEG
 
 config VIDEO_SAMSUNG_S5P_MFC
         tristate "Samsung S5P MFC Video Codec"
-        depends on VIDEO_DEV && VIDEO_V4L2 && PLAT_S5P
+        depends on VIDEO_DEV && VIDEO_V4L2 && (PLAT_S5P || ARCH_EXYNOS)
         select VIDEOBUF2_DMA_CONTIG
         default n
         help
diff --git a/drivers/media/platform/exynos4-is/Kconfig b/drivers/media/platform/exynos4-is/Kconfig
index 6ff99b5849f9..004fd0b4e9df 100644
--- a/drivers/media/platform/exynos4-is/Kconfig
+++ b/drivers/media/platform/exynos4-is/Kconfig
@@ -1,7 +1,8 @@
 
 config VIDEO_SAMSUNG_EXYNOS4_IS
         bool "Samsung S5P/EXYNOS4 SoC series Camera Subsystem driver"
-        depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PLAT_S5P && PM_RUNTIME
+        depends on VIDEO_V4L2 && VIDEO_V4L2_SUBDEV_API && PM_RUNTIME
+        depends on (PLAT_S5P || ARCH_EXYNOS)
         help
           Say Y here to enable camera host interface devices for
           Samsung S5P and EXYNOS SoC series.
diff --git a/drivers/media/platform/omap/omap_vout.c b/drivers/media/platform/omap/omap_vout.c
index 477268a2415f..d338b19da544 100644
--- a/drivers/media/platform/omap/omap_vout.c
+++ b/drivers/media/platform/omap/omap_vout.c
@@ -2150,6 +2150,9 @@ static int __init omap_vout_probe(struct platform_device *pdev)
         struct omap_dss_device *def_display;
         struct omap2video_device *vid_dev = NULL;
 
+        if (omapdss_is_initialized() == false)
+                return -EPROBE_DEFER;
+
         ret = omapdss_compat_init();
         if (ret) {
                 dev_err(&pdev->dev, "failed to init dss\n");
diff --git a/drivers/media/platform/s5p-tv/Kconfig b/drivers/media/platform/s5p-tv/Kconfig
index 7b659bd09bfd..369a4c191e18 100644
--- a/drivers/media/platform/s5p-tv/Kconfig
+++ b/drivers/media/platform/s5p-tv/Kconfig
@@ -8,7 +8,7 @@
 
 config VIDEO_SAMSUNG_S5P_TV
         bool "Samsung TV driver for S5P platform"
-        depends on PLAT_S5P && PM_RUNTIME
+        depends on (PLAT_S5P || ARCH_EXYNOS) && PM_RUNTIME
         default n
         ---help---
           Say Y here to enable selecting the TV output devices for
diff --git a/drivers/mfd/syscon.c b/drivers/mfd/syscon.c
index 962a6e17a01a..1a31512369f9 100644
--- a/drivers/mfd/syscon.c
+++ b/drivers/mfd/syscon.c
@@ -159,6 +159,9 @@ static int syscon_probe(struct platform_device *pdev)
 
 static const struct platform_device_id syscon_ids[] = {
         { "syscon", },
+#ifdef CONFIG_ARCH_CLPS711X
+        { "clps711x-syscon", },
+#endif
         { }
 };
 
diff --git a/drivers/misc/mei/init.c b/drivers/misc/mei/init.c
index 713d89fedc46..f580d30bb784 100644
--- a/drivers/misc/mei/init.c
+++ b/drivers/misc/mei/init.c
@@ -197,6 +197,8 @@ void mei_stop(struct mei_device *dev)
 {
         dev_dbg(&dev->pdev->dev, "stopping the device.\n");
 
+        flush_scheduled_work();
+
         mutex_lock(&dev->device_lock);
 
         cancel_delayed_work(&dev->timer_work);
@@ -210,8 +212,6 @@ void mei_stop(struct mei_device *dev)
 
         mutex_unlock(&dev->device_lock);
 
-        flush_scheduled_work();
-
         mei_watchdog_unregister(dev);
 }
 EXPORT_SYMBOL_GPL(mei_stop);
diff --git a/drivers/misc/mei/nfc.c b/drivers/misc/mei/nfc.c
index 3adf8a70f26e..d0c6907dfd92 100644
--- a/drivers/misc/mei/nfc.c
+++ b/drivers/misc/mei/nfc.c
@@ -142,6 +142,8 @@ static void mei_nfc_free(struct mei_nfc_dev *ndev)
                 mei_cl_unlink(ndev->cl_info);
                 kfree(ndev->cl_info);
         }
+
+        memset(ndev, 0, sizeof(struct mei_nfc_dev));
 }
 
 static int mei_nfc_build_bus_name(struct mei_nfc_dev *ndev)
diff --git a/drivers/misc/mei/pci-me.c b/drivers/misc/mei/pci-me.c
index a727464e9c3f..0f268329bd3a 100644
--- a/drivers/misc/mei/pci-me.c
+++ b/drivers/misc/mei/pci-me.c
@@ -325,6 +325,7 @@ static int mei_me_pci_resume(struct device *device)
 
         mutex_lock(&dev->device_lock);
         dev->dev_state = MEI_DEV_POWER_UP;
+        mei_clear_interrupts(dev);
         mei_reset(dev, 1);
         mutex_unlock(&dev->device_lock);
 
diff --git a/drivers/misc/sgi-gru/grufile.c b/drivers/misc/sgi-gru/grufile.c
index 44d273c5e19d..0535d1e0bc78 100644
--- a/drivers/misc/sgi-gru/grufile.c
+++ b/drivers/misc/sgi-gru/grufile.c
@@ -172,6 +172,7 @@ static long gru_get_config_info(unsigned long arg)
                 nodesperblade = 2;
         else
                 nodesperblade = 1;
+        memset(&info, 0, sizeof(info));
         info.cpus = num_online_cpus();
         info.nodes = num_online_nodes();
         info.blades = info.nodes / nodesperblade;
diff --git a/drivers/mmc/host/atmel-mci.c b/drivers/mmc/host/atmel-mci.c
index e75774f72606..aca59d93d5a9 100644
--- a/drivers/mmc/host/atmel-mci.c
+++ b/drivers/mmc/host/atmel-mci.c
@@ -2230,10 +2230,15 @@ static void __exit atmci_cleanup_slot(struct atmel_mci_slot *slot,
         mmc_free_host(slot->mmc);
 }
 
-static bool atmci_filter(struct dma_chan *chan, void *slave)
+static bool atmci_filter(struct dma_chan *chan, void *pdata)
 {
-        struct mci_dma_data     *sl = slave;
+        struct mci_platform_data *sl_pdata = pdata;
+        struct mci_dma_data *sl;
 
+        if (!sl_pdata)
+                return false;
+
+        sl = sl_pdata->dma_slave;
         if (sl && find_slave_dev(sl) == chan->device->dev) {
                 chan->private = slave_data_ptr(sl);
                 return true;
@@ -2245,24 +2250,18 @@ static bool atmci_filter(struct dma_chan *chan, void *slave)
 static bool atmci_configure_dma(struct atmel_mci *host)
 {
         struct mci_platform_data        *pdata;
+        dma_cap_mask_t mask;
 
         if (host == NULL)
                 return false;
 
         pdata = host->pdev->dev.platform_data;
 
-        if (!pdata)
-                return false;
+        dma_cap_zero(mask);
+        dma_cap_set(DMA_SLAVE, mask);
 
-        if (pdata->dma_slave && find_slave_dev(pdata->dma_slave)) {
-                dma_cap_mask_t mask;
-
-                /* Try to grab a DMA channel */
-                dma_cap_zero(mask);
-                dma_cap_set(DMA_SLAVE, mask);
-                host->dma.chan =
-                        dma_request_channel(mask, atmci_filter, pdata->dma_slave);
-        }
+        host->dma.chan = dma_request_slave_channel_compat(mask, atmci_filter, pdata,
+                                                          &host->pdev->dev, "rxtx");
         if (!host->dma.chan) {
                 dev_warn(&host->pdev->dev, "no DMA channel available\n");
                 return false;
diff --git a/drivers/mmc/host/davinci_mmc.c b/drivers/mmc/host/davinci_mmc.c
index 3946a0eb3a03..5dfb70c669dc 100644
--- a/drivers/mmc/host/davinci_mmc.c
+++ b/drivers/mmc/host/davinci_mmc.c
@@ -37,6 +37,7 @@
 #include <linux/of.h>
 #include <linux/of_device.h>
 
+#include <linux/platform_data/edma.h>
 #include <linux/platform_data/mmc-davinci.h>
 
 /*
diff --git a/drivers/mmc/host/omap_hsmmc.c b/drivers/mmc/host/omap_hsmmc.c
index 6e44025acf01..eccedc7d06a4 100644
--- a/drivers/mmc/host/omap_hsmmc.c
+++ b/drivers/mmc/host/omap_hsmmc.c
@@ -161,6 +161,7 @@ struct omap_hsmmc_host {
          */
         struct  regulator       *vcc;
         struct  regulator       *vcc_aux;
+        int                     pbias_disable;
         void    __iomem         *base;
         resource_size_t         mapbase;
         spinlock_t              irq_lock; /* Prevent races with irq handler */
@@ -255,11 +256,11 @@ static int omap_hsmmc_set_power(struct device *dev, int slot, int power_on,
         if (!host->vcc)
                 return 0;
         /*
-         * With DT, never turn OFF the regulator. This is because
+         * With DT, never turn OFF the regulator for MMC1. This is because
          * the pbias cell programming support is still missing when
          * booting with Device tree
          */
-        if (dev->of_node && !vdd)
+        if (host->pbias_disable && !vdd)
                 return 0;
 
         if (mmc_slot(host).before_set_reg)
@@ -1520,10 +1521,10 @@ static void omap_hsmmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
                         (ios->vdd == DUAL_VOLT_OCR_BIT) &&
                         /*
                          * With pbias cell programming missing, this
-                         * can't be allowed when booting with device
+                         * can't be allowed on MMC1 when booting with device
                          * tree.
                          */
-                        !host->dev->of_node) {
+                        !host->pbias_disable) {
                                 /*
                                  * The mmc_select_voltage fn of the core does
                                  * not seem to set the power_mode to
@@ -1871,6 +1872,10 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 
         omap_hsmmc_context_save(host);
 
+        /* This can be removed once we support PBIAS with DT */
+        if (host->dev->of_node && host->mapbase == 0x4809c000)
+                host->pbias_disable = 1;
+
         host->dbclk = clk_get(&pdev->dev, "mmchsdb_fck");
         /*
          * MMC can still work without debounce clock.
@@ -1906,33 +1911,41 @@ static int omap_hsmmc_probe(struct platform_device *pdev)
 
         omap_hsmmc_conf_bus_power(host);
 
-        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
-        if (!res) {
-                dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
-                ret = -ENXIO;
-                goto err_irq;
-        }
-        tx_req = res->start;
+        if (!pdev->dev.of_node) {
+                res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "tx");
+                if (!res) {
+                        dev_err(mmc_dev(host->mmc), "cannot get DMA TX channel\n");
+                        ret = -ENXIO;
+                        goto err_irq;
+                }
+                tx_req = res->start;
 
-        res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
-        if (!res) {
-                dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
-                ret = -ENXIO;
-                goto err_irq;
+                res = platform_get_resource_byname(pdev, IORESOURCE_DMA, "rx");
+                if (!res) {
+                        dev_err(mmc_dev(host->mmc), "cannot get DMA RX channel\n");
+                        ret = -ENXIO;
+                        goto err_irq;
+                }
+                rx_req = res->start;
         }
-        rx_req = res->start;
 
         dma_cap_zero(mask);
         dma_cap_set(DMA_SLAVE, mask);
 
-        host->rx_chan = dma_request_channel(mask, omap_dma_filter_fn, &rx_req);
+        host->rx_chan =
+                dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+                                                 &rx_req, &pdev->dev, "rx");
+
         if (!host->rx_chan) {
                 dev_err(mmc_dev(host->mmc), "unable to obtain RX DMA engine channel %u\n", rx_req);
                 ret = -ENXIO;
                 goto err_irq;
         }
 
-        host->tx_chan = dma_request_channel(mask, omap_dma_filter_fn, &tx_req);
+        host->tx_chan =
+                dma_request_slave_channel_compat(mask, omap_dma_filter_fn,
+                                                 &tx_req, &pdev->dev, "tx");
+
         if (!host->tx_chan) {
                 dev_err(mmc_dev(host->mmc), "unable to obtain TX DMA engine channel %u\n", tx_req);
                 ret = -ENXIO;
diff --git a/drivers/mmc/host/sdhci-acpi.c b/drivers/mmc/host/sdhci-acpi.c
index 7bcf74b1a5cd..706d9cb1a49e 100644
--- a/drivers/mmc/host/sdhci-acpi.c
+++ b/drivers/mmc/host/sdhci-acpi.c
@@ -87,6 +87,12 @@ static const struct sdhci_ops sdhci_acpi_ops_dflt = {
         .enable_dma = sdhci_acpi_enable_dma,
 };
 
+static const struct sdhci_acpi_slot sdhci_acpi_slot_int_emmc = {
+        .caps    = MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE,
+        .caps2   = MMC_CAP2_HC_ERASE_SZ,
+        .flags   = SDHCI_ACPI_RUNTIME_PM,
+};
+
 static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
         .quirks2 = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
         .caps    = MMC_CAP_NONREMOVABLE | MMC_CAP_POWER_OFF_CARD,
@@ -94,23 +100,67 @@ static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sdio = {
         .pm_caps = MMC_PM_KEEP_POWER,
 };
 
+static const struct sdhci_acpi_slot sdhci_acpi_slot_int_sd = {
+};
+
+struct sdhci_acpi_uid_slot {
+        const char *hid;
+        const char *uid;
+        const struct sdhci_acpi_slot *slot;
+};
+
+static const struct sdhci_acpi_uid_slot sdhci_acpi_uids[] = {
+        { "80860F14" , "1" , &sdhci_acpi_slot_int_emmc },
+        { "80860F14" , "3" , &sdhci_acpi_slot_int_sd   },
+        { "INT33BB"  , "2" , &sdhci_acpi_slot_int_sdio },
+        { "INT33C6"  , NULL, &sdhci_acpi_slot_int_sdio },
+        { "PNP0D40"  },
+        { },
+};
+
 static const struct acpi_device_id sdhci_acpi_ids[] = {
-        { "INT33C6", (kernel_ulong_t)&sdhci_acpi_slot_int_sdio },
-        { "PNP0D40" },
+        { "80860F14" },
+        { "INT33BB"  },
+        { "INT33C6"  },
+        { "PNP0D40"  },
         { },
 };
 MODULE_DEVICE_TABLE(acpi, sdhci_acpi_ids);
 
-static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(const char *hid)
+static const struct sdhci_acpi_slot *sdhci_acpi_get_slot_by_ids(const char *hid,
+                                                                const char *uid)
 {
-        const struct acpi_device_id *id;
-
-        for (id = sdhci_acpi_ids; id->id[0]; id++)
-                if (!strcmp(id->id, hid))
-                        return (const struct sdhci_acpi_slot *)id->driver_data;
+        const struct sdhci_acpi_uid_slot *u;
+
+        for (u = sdhci_acpi_uids; u->hid; u++) {
+                if (strcmp(u->hid, hid))
+                        continue;
+                if (!u->uid)
+                        return u->slot;
+                if (uid && !strcmp(u->uid, uid))
+                        return u->slot;
+        }
         return NULL;
 }
 
+static const struct sdhci_acpi_slot *sdhci_acpi_get_slot(acpi_handle handle,
+                                                         const char *hid)
+{
+        const struct sdhci_acpi_slot *slot;
+        struct acpi_device_info *info;
+        const char *uid = NULL;
+        acpi_status status;
+
+        status = acpi_get_object_info(handle, &info);
+        if (!ACPI_FAILURE(status) && (info->valid & ACPI_VALID_UID))
+                uid = info->unique_id.string;
+
+        slot = sdhci_acpi_get_slot_by_ids(hid, uid);
+
+        kfree(info);
+        return slot;
+}
+
 static int sdhci_acpi_probe(struct platform_device *pdev)
 {
         struct device *dev = &pdev->dev;
@@ -148,7 +198,7 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
 
         c = sdhci_priv(host);
         c->host = host;
-        c->slot = sdhci_acpi_get_slot(hid);
+        c->slot = sdhci_acpi_get_slot(handle, hid);
         c->pdev = pdev;
         c->use_runtime_pm = sdhci_acpi_flag(c, SDHCI_ACPI_RUNTIME_PM);
 
@@ -202,6 +252,7 @@ static int sdhci_acpi_probe(struct platform_device *pdev)
                 goto err_free;
 
         if (c->use_runtime_pm) {
+                pm_runtime_set_active(dev);
                 pm_suspend_ignore_children(dev, 1);
                 pm_runtime_set_autosuspend_delay(dev, 50);
                 pm_runtime_use_autosuspend(dev);
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c
index 67d6dde2ff19..d5f0d59e1310 100644
--- a/drivers/mmc/host/sdhci-esdhc-imx.c
+++ b/drivers/mmc/host/sdhci-esdhc-imx.c
@@ -85,6 +85,12 @@ struct pltfm_imx_data {
         struct clk *clk_ipg;
         struct clk *clk_ahb;
         struct clk *clk_per;
+        enum {
+                NO_CMD_PENDING,      /* no multiblock command pending*/
+                MULTIBLK_IN_PROCESS, /* exact multiblock cmd in process */
+                WAIT_FOR_INT,        /* sent CMD12, waiting for response INT */
+        } multiblock_status;
+
 };
 
 static struct platform_device_id imx_esdhc_devtype[] = {
@@ -154,6 +160,8 @@ static inline void esdhc_clrset_le(struct sdhci_host *host, u32 mask, u32 val, i
 
 static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
 {
+        struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+        struct pltfm_imx_data *imx_data = pltfm_host->priv;
         u32 val = readl(host->ioaddr + reg);
 
         if (unlikely(reg == SDHCI_CAPABILITIES)) {
@@ -175,6 +183,18 @@ static u32 esdhc_readl_le(struct sdhci_host *host, int reg)
                         val &= ~ESDHC_INT_VENDOR_SPEC_DMA_ERR;
                         val |= SDHCI_INT_ADMA_ERROR;
                 }
+
+                /*
+                 * mask off the interrupt we get in response to the manually
+                 * sent CMD12
+                 */
+                if ((imx_data->multiblock_status == WAIT_FOR_INT) &&
+                    ((val & SDHCI_INT_RESPONSE) == SDHCI_INT_RESPONSE)) {
+                        val &= ~SDHCI_INT_RESPONSE;
+                        writel(SDHCI_INT_RESPONSE, host->ioaddr +
+                                                   SDHCI_INT_STATUS);
+                        imx_data->multiblock_status = NO_CMD_PENDING;
+                }
         }
 
         return val;
@@ -211,6 +231,15 @@ static void esdhc_writel_le(struct sdhci_host *host, u32 val, int reg)
                         v = readl(host->ioaddr + ESDHC_VENDOR_SPEC);
                         v &= ~ESDHC_VENDOR_SPEC_SDIO_QUIRK;
                         writel(v, host->ioaddr + ESDHC_VENDOR_SPEC);
+
+                        if (imx_data->multiblock_status == MULTIBLK_IN_PROCESS)
+                        {
+                                /* send a manual CMD12 with RESPTYP=none */
+                                data = MMC_STOP_TRANSMISSION << 24 |
+                                       SDHCI_CMD_ABORTCMD << 16;
+                                writel(data, host->ioaddr + SDHCI_TRANSFER_MODE);
+                                imx_data->multiblock_status = WAIT_FOR_INT;
+                        }
         }
 
         if (unlikely(reg == SDHCI_INT_ENABLE || reg == SDHCI_SIGNAL_ENABLE)) {
@@ -277,11 +306,13 @@ static void esdhc_writew_le(struct sdhci_host *host, u16 val, int reg)
                 }
                 return;
         case SDHCI_COMMAND:
-                if ((host->cmd->opcode == MMC_STOP_TRANSMISSION ||
-                     host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
-                    (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
+                if (host->cmd->opcode == MMC_STOP_TRANSMISSION)
                         val |= SDHCI_CMD_ABORTCMD;
 
+                if ((host->cmd->opcode == MMC_SET_BLOCK_COUNT) &&
+                    (imx_data->flags & ESDHC_FLAG_MULTIBLK_NO_INT))
+                        imx_data->multiblock_status = MULTIBLK_IN_PROCESS;
+
                 if (is_imx6q_usdhc(imx_data))
                         writel(val << 16,
                                host->ioaddr + SDHCI_TRANSFER_MODE);
@@ -324,8 +355,10 @@ static void esdhc_writeb_le(struct sdhci_host *host, u8 val, int reg)
                 /*
                  * Do not touch buswidth bits here. This is done in
                  * esdhc_pltfm_bus_width.
+                 * Do not touch the D3CD bit either which is used for the
+                 * SDIO interrupt errata workaround.
                  */
-                mask = 0xffff & ~ESDHC_CTRL_BUSWIDTH_MASK;
+                mask = 0xffff & ~(ESDHC_CTRL_BUSWIDTH_MASK | ESDHC_CTRL_D3CD);
 
                 esdhc_clrset_le(host, mask, new_val, reg);
                 return;
diff --git a/drivers/mmc/host/sdhci-pci.c b/drivers/mmc/host/sdhci-pci.c
index 0012d3fdc999..701d06d0e1fb 100644
--- a/drivers/mmc/host/sdhci-pci.c
+++ b/drivers/mmc/host/sdhci-pci.c
@@ -33,6 +33,9 @@
  */
 #define PCI_DEVICE_ID_INTEL_PCH_SDIO0   0x8809
 #define PCI_DEVICE_ID_INTEL_PCH_SDIO1   0x880a
+#define PCI_DEVICE_ID_INTEL_BYT_EMMC    0x0f14
+#define PCI_DEVICE_ID_INTEL_BYT_SDIO    0x0f15
+#define PCI_DEVICE_ID_INTEL_BYT_SD      0x0f16
 
 /*
  * PCI registers
@@ -304,6 +307,33 @@ static const struct sdhci_pci_fixes sdhci_intel_pch_sdio = {
         .probe_slot     = pch_hc_probe_slot,
 };
 
+static int byt_emmc_probe_slot(struct sdhci_pci_slot *slot)
+{
+        slot->host->mmc->caps |= MMC_CAP_8_BIT_DATA | MMC_CAP_NONREMOVABLE;
+        slot->host->mmc->caps2 |= MMC_CAP2_HC_ERASE_SZ;
+        return 0;
+}
+
+static int byt_sdio_probe_slot(struct sdhci_pci_slot *slot)
+{
+        slot->host->mmc->caps |= MMC_CAP_POWER_OFF_CARD | MMC_CAP_NONREMOVABLE;
+        return 0;
+}
+
+static const struct sdhci_pci_fixes sdhci_intel_byt_emmc = {
+        .allow_runtime_pm = true,
+        .probe_slot     = byt_emmc_probe_slot,
+};
+
+static const struct sdhci_pci_fixes sdhci_intel_byt_sdio = {
+        .quirks2        = SDHCI_QUIRK2_HOST_OFF_CARD_ON,
+        .allow_runtime_pm = true,
+        .probe_slot     = byt_sdio_probe_slot,
+};
+
+static const struct sdhci_pci_fixes sdhci_intel_byt_sd = {
+};
+
 /* O2Micro extra registers */
 #define O2_SD_LOCK_WP           0xD3
 #define O2_SD_MULTI_VCC3V       0xEE
@@ -856,6 +886,30 @@ static const struct pci_device_id pci_ids[] = {
         },
 
         {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_BYT_EMMC,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_emmc,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_BYT_SDIO,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sdio,
+        },
+
+        {
+                .vendor         = PCI_VENDOR_ID_INTEL,
+                .device         = PCI_DEVICE_ID_INTEL_BYT_SD,
+                .subvendor      = PCI_ANY_ID,
+                .subdevice      = PCI_ANY_ID,
+                .driver_data    = (kernel_ulong_t)&sdhci_intel_byt_sd,
+        },
+
+        {
                 .vendor         = PCI_VENDOR_ID_O2,
                 .device         = PCI_DEVICE_ID_O2_8120,
                 .subvendor      = PCI_ANY_ID,
diff --git a/drivers/mtd/maps/Kconfig b/drivers/mtd/maps/Kconfig
index bed9d58d5741..8b27ca054c59 100644
--- a/drivers/mtd/maps/Kconfig
+++ b/drivers/mtd/maps/Kconfig
@@ -297,13 +297,6 @@ config MTD_IXP4XX
           IXDP425 and Coyote. If you have an IXP4xx based board and
           would like to use the flash chips on it, say 'Y'.
 
-config MTD_AUTCPU12
-        bool "NV-RAM mapping AUTCPU12 board"
-        depends on ARCH_AUTCPU12
-        help
-          This enables access to the NV-RAM on autronix autcpu12 board.
-          If you have such a board, say 'Y'.
-
 config MTD_IMPA7
         tristate "JEDEC Flash device mapped on impA7"
         depends on ARM && MTD_JEDECPROBE
diff --git a/drivers/mtd/maps/Makefile b/drivers/mtd/maps/Makefile
index 395a12444048..9fdbd4ba6441 100644
--- a/drivers/mtd/maps/Makefile
+++ b/drivers/mtd/maps/Makefile
@@ -32,7 +32,6 @@ obj-$(CONFIG_MTD_VMAX)		+= vmax301.o
 obj-$(CONFIG_MTD_SCx200_DOCFLASH)+= scx200_docflash.o
 obj-$(CONFIG_MTD_SOLUTIONENGINE)+= solutionengine.o
 obj-$(CONFIG_MTD_PCI)           += pci.o
-obj-$(CONFIG_MTD_AUTCPU12)      += autcpu12-nvram.o
 obj-$(CONFIG_MTD_IMPA7)         += impa7.o
 obj-$(CONFIG_MTD_UCLINUX)       += uclinux.o
 obj-$(CONFIG_MTD_NETtel)        += nettel.o
diff --git a/drivers/mtd/maps/autcpu12-nvram.c b/drivers/mtd/maps/autcpu12-nvram.c
deleted file mode 100644
index c3525d2a2fa8..000000000000
--- a/drivers/mtd/maps/autcpu12-nvram.c
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * NV-RAM memory access on autcpu12
- * (C) 2002 Thomas Gleixner (gleixner@autronix.de)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#include <linux/err.h>
-#include <linux/sizes.h>
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-#include <linux/device.h>
-#include <linux/module.h>
-#include <linux/platform_device.h>
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/map.h>
-
-struct autcpu12_nvram_priv {
-        struct mtd_info *mtd;
-        struct map_info map;
-};
-
-static int autcpu12_nvram_probe(struct platform_device *pdev)
-{
-        map_word tmp, save0, save1;
-        struct resource *res;
-        struct autcpu12_nvram_priv *priv;
-
-        priv = devm_kzalloc(&pdev->dev,
-                            sizeof(struct autcpu12_nvram_priv), GFP_KERNEL);
-        if (!priv)
-                return -ENOMEM;
-
-        platform_set_drvdata(pdev, priv);
-
-        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res) {
-                dev_err(&pdev->dev, "failed to get memory resource\n");
-                return -ENOENT;
-        }
-
-        priv->map.bankwidth     = 4;
-        priv->map.phys          = res->start;
-        priv->map.size          = resource_size(res);
-        priv->map.virt = devm_ioremap_resource(&pdev->dev, res);
-        strcpy((char *)priv->map.name, res->name);
-        if (IS_ERR(priv->map.virt))
-                return PTR_ERR(priv->map.virt);
-
-        simple_map_init(&priv->map);
-
-        /*
-         * Check for 32K/128K
-         * read ofs 0
-         * read ofs 0x10000
-         * Write complement to ofs 0x100000
-         * Read and check result on ofs 0x0
-         * Restore contents
-         */
-        save0 = map_read(&priv->map, 0);
-        save1 = map_read(&priv->map, 0x10000);
-        tmp.x[0] = ~save0.x[0];
-        map_write(&priv->map, tmp, 0x10000);
-        tmp = map_read(&priv->map, 0);
-        /* if we find this pattern on 0x0, we have 32K size */
-        if (!map_word_equal(&priv->map, tmp, save0)) {
-                map_write(&priv->map, save0, 0x0);
-                priv->map.size = SZ_32K;
-        } else
-                map_write(&priv->map, save1, 0x10000);
-
-        priv->mtd = do_map_probe("map_ram", &priv->map);
-        if (!priv->mtd) {
-                dev_err(&pdev->dev, "probing failed\n");
-                return -ENXIO;
-        }
-
-        priv->mtd->owner        = THIS_MODULE;
-        priv->mtd->erasesize    = 16;
-        priv->mtd->dev.parent   = &pdev->dev;
-        if (!mtd_device_register(priv->mtd, NULL, 0)) {
-                dev_info(&pdev->dev,
-                         "NV-RAM device size %ldKiB registered on AUTCPU12\n",
-                         priv->map.size / SZ_1K);
-                return 0;
-        }
-
-        map_destroy(priv->mtd);
-        dev_err(&pdev->dev, "NV-RAM device addition failed\n");
-        return -ENOMEM;
-}
-
-static int autcpu12_nvram_remove(struct platform_device *pdev)
-{
-        struct autcpu12_nvram_priv *priv = platform_get_drvdata(pdev);
-
-        mtd_device_unregister(priv->mtd);
-        map_destroy(priv->mtd);
-
-        return 0;
-}
-
-static struct platform_driver autcpu12_nvram_driver = {
-        .driver         = {
-                .name   = "autcpu12_nvram",
-                .owner  = THIS_MODULE,
-        },
-        .probe          = autcpu12_nvram_probe,
-        .remove         = autcpu12_nvram_remove,
-};
-module_platform_driver(autcpu12_nvram_driver);
-
-MODULE_AUTHOR("Thomas Gleixner");
-MODULE_DESCRIPTION("autcpu12 NVRAM map driver");
-MODULE_LICENSE("GPL");
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index 29b846cbfb48..02d9ae7d527e 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -764,8 +764,8 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
         struct net_device *bond_dev, *vlan_dev, *upper_dev;
         struct vlan_entry *vlan;
 
-        rcu_read_lock();
         read_lock(&bond->lock);
+        rcu_read_lock();
 
         bond_dev = bond->dev;
 
@@ -787,12 +787,19 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
                 if (vlan_dev)
                         __bond_resend_igmp_join_requests(vlan_dev);
         }
+        rcu_read_unlock();
 
-        if (--bond->igmp_retrans > 0)
+        /* We use curr_slave_lock to protect against concurrent access to
+         * igmp_retrans from multiple running instances of this function and
+         * bond_change_active_slave
+         */
+        write_lock_bh(&bond->curr_slave_lock);
+        if (bond->igmp_retrans > 1) {
+                bond->igmp_retrans--;
                 queue_delayed_work(bond->wq, &bond->mcast_work, HZ/5);
-
+        }
+        write_unlock_bh(&bond->curr_slave_lock);
         read_unlock(&bond->lock);
-        rcu_read_unlock();
 }
 
 static void bond_resend_igmp_join_requests_delayed(struct work_struct *work)
@@ -1957,6 +1964,10 @@ err_free:
 
 err_undo_flags:
         bond_compute_features(bond);
+        /* Enslave of first slave has failed and we need to fix master's mac */
+        if (bond->slave_cnt == 0 &&
+            ether_addr_equal(bond_dev->dev_addr, slave_dev->dev_addr))
+                eth_hw_addr_random(bond_dev);
 
         return res;
 }
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index 2baec24388b1..f989e1529a29 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -225,7 +225,7 @@ struct bonding {
         rwlock_t curr_slave_lock;
         u8       send_peer_notif;
         s8       setup_by_slave;
-        s8       igmp_retrans;
+        u8       igmp_retrans;
 #ifdef CONFIG_PROC_FS
         struct   proc_dir_entry *proc_entry;
         char     proc_file_name[IFNAMSIZ];
diff --git a/drivers/net/can/usb/esd_usb2.c b/drivers/net/can/usb/esd_usb2.c
index 9b74d1e3ad44..6aa7b3266c80 100644
--- a/drivers/net/can/usb/esd_usb2.c
+++ b/drivers/net/can/usb/esd_usb2.c
@@ -612,9 +612,15 @@ static int esd_usb2_start(struct esd_usb2_net_priv *priv)
 {
         struct esd_usb2 *dev = priv->usb2;
         struct net_device *netdev = priv->netdev;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int err, i;
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg) {
+                err = -ENOMEM;
+                goto out;
+        }
+
         /*
          * Enable all IDs
          * The IDADD message takes up to 64 32 bit bitmasks (2048 bits).
@@ -628,33 +634,32 @@ static int esd_usb2_start(struct esd_usb2_net_priv *priv)
          * the number of the starting bitmask (0..64) to the filter.option
          * field followed by only some bitmasks.
          */
-        msg.msg.hdr.cmd = CMD_IDADD;
-        msg.msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
-        msg.msg.filter.net = priv->index;
-        msg.msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
+        msg->msg.hdr.cmd = CMD_IDADD;
+        msg->msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
+        msg->msg.filter.net = priv->index;
+        msg->msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
         for (i = 0; i < ESD_MAX_ID_SEGMENT; i++)
-                msg.msg.filter.mask[i] = cpu_to_le32(0xffffffff);
+                msg->msg.filter.mask[i] = cpu_to_le32(0xffffffff);
         /* enable 29bit extended IDs */
-        msg.msg.filter.mask[ESD_MAX_ID_SEGMENT] = cpu_to_le32(0x00000001);
+        msg->msg.filter.mask[ESD_MAX_ID_SEGMENT] = cpu_to_le32(0x00000001);
 
-        err = esd_usb2_send_msg(dev, &msg);
+        err = esd_usb2_send_msg(dev, msg);
         if (err)
-                goto failed;
+                goto out;
 
         err = esd_usb2_setup_rx_urbs(dev);
         if (err)
-                goto failed;
+                goto out;
 
         priv->can.state = CAN_STATE_ERROR_ACTIVE;
 
-        return 0;
-
-failed:
+out:
         if (err == -ENODEV)
                 netif_device_detach(netdev);
+        if (err)
+                netdev_err(netdev, "couldn't start device: %d\n", err);
 
-        netdev_err(netdev, "couldn't start device: %d\n", err);
-
+        kfree(msg);
         return err;
 }
 
@@ -833,26 +838,30 @@ nourbmem:
 static int esd_usb2_close(struct net_device *netdev)
 {
         struct esd_usb2_net_priv *priv = netdev_priv(netdev);
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int i;
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg)
+                return -ENOMEM;
+
         /* Disable all IDs (see esd_usb2_start()) */
-        msg.msg.hdr.cmd = CMD_IDADD;
-        msg.msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
-        msg.msg.filter.net = priv->index;
-        msg.msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
+        msg->msg.hdr.cmd = CMD_IDADD;
+        msg->msg.hdr.len = 2 + ESD_MAX_ID_SEGMENT;
+        msg->msg.filter.net = priv->index;
+        msg->msg.filter.option = ESD_ID_ENABLE; /* start with segment 0 */
         for (i = 0; i <= ESD_MAX_ID_SEGMENT; i++)
-                msg.msg.filter.mask[i] = 0;
-        if (esd_usb2_send_msg(priv->usb2, &msg) < 0)
+                msg->msg.filter.mask[i] = 0;
+        if (esd_usb2_send_msg(priv->usb2, msg) < 0)
                 netdev_err(netdev, "sending idadd message failed\n");
 
         /* set CAN controller to reset mode */
-        msg.msg.hdr.len = 2;
-        msg.msg.hdr.cmd = CMD_SETBAUD;
-        msg.msg.setbaud.net = priv->index;
-        msg.msg.setbaud.rsvd = 0;
-        msg.msg.setbaud.baud = cpu_to_le32(ESD_USB2_NO_BAUDRATE);
-        if (esd_usb2_send_msg(priv->usb2, &msg) < 0)
+        msg->msg.hdr.len = 2;
+        msg->msg.hdr.cmd = CMD_SETBAUD;
+        msg->msg.setbaud.net = priv->index;
+        msg->msg.setbaud.rsvd = 0;
+        msg->msg.setbaud.baud = cpu_to_le32(ESD_USB2_NO_BAUDRATE);
+        if (esd_usb2_send_msg(priv->usb2, msg) < 0)
                 netdev_err(netdev, "sending setbaud message failed\n");
 
         priv->can.state = CAN_STATE_STOPPED;
@@ -861,6 +870,8 @@ static int esd_usb2_close(struct net_device *netdev)
 
         close_candev(netdev);
 
+        kfree(msg);
+
         return 0;
 }
 
@@ -886,7 +897,8 @@ static int esd_usb2_set_bittiming(struct net_device *netdev)
 {
         struct esd_usb2_net_priv *priv = netdev_priv(netdev);
         struct can_bittiming *bt = &priv->can.bittiming;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
+        int err;
         u32 canbtr;
         int sjw_shift;
 
@@ -912,15 +924,22 @@ static int esd_usb2_set_bittiming(struct net_device *netdev)
         if (priv->can.ctrlmode & CAN_CTRLMODE_3_SAMPLES)
                 canbtr |= ESD_USB2_3_SAMPLES;
 
-        msg.msg.hdr.len = 2;
-        msg.msg.hdr.cmd = CMD_SETBAUD;
-        msg.msg.setbaud.net = priv->index;
-        msg.msg.setbaud.rsvd = 0;
-        msg.msg.setbaud.baud = cpu_to_le32(canbtr);
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg)
+                return -ENOMEM;
+
+        msg->msg.hdr.len = 2;
+        msg->msg.hdr.cmd = CMD_SETBAUD;
+        msg->msg.setbaud.net = priv->index;
+        msg->msg.setbaud.rsvd = 0;
+        msg->msg.setbaud.baud = cpu_to_le32(canbtr);
 
         netdev_info(netdev, "setting BTR=%#x\n", canbtr);
 
-        return esd_usb2_send_msg(priv->usb2, &msg);
+        err = esd_usb2_send_msg(priv->usb2, msg);
+
+        kfree(msg);
+        return err;
 }
 
 static int esd_usb2_get_berr_counter(const struct net_device *netdev,
@@ -1022,7 +1041,7 @@ static int esd_usb2_probe(struct usb_interface *intf,
                          const struct usb_device_id *id)
 {
         struct esd_usb2 *dev;
-        struct esd_usb2_msg msg;
+        struct esd_usb2_msg *msg;
         int i, err;
 
         dev = kzalloc(sizeof(*dev), GFP_KERNEL);
@@ -1037,27 +1056,33 @@ static int esd_usb2_probe(struct usb_interface *intf,
 
         usb_set_intfdata(intf, dev);
 
+        msg = kmalloc(sizeof(*msg), GFP_KERNEL);
+        if (!msg) {
+                err = -ENOMEM;
+                goto free_msg;
+        }
+
         /* query number of CAN interfaces (nets) */
-        msg.msg.hdr.cmd = CMD_VERSION;
-        msg.msg.hdr.len = 2;
-        msg.msg.version.rsvd = 0;
-        msg.msg.version.flags = 0;
-        msg.msg.version.drv_version = 0;
+        msg->msg.hdr.cmd = CMD_VERSION;
+        msg->msg.hdr.len = 2;
+        msg->msg.version.rsvd = 0;
+        msg->msg.version.flags = 0;
+        msg->msg.version.drv_version = 0;
 
-        err = esd_usb2_send_msg(dev, &msg);
+        err = esd_usb2_send_msg(dev, msg);
         if (err < 0) {
                 dev_err(&intf->dev, "sending version message failed\n");
-                goto free_dev;
+                goto free_msg;
         }
 
-        err = esd_usb2_wait_msg(dev, &msg);
+        err = esd_usb2_wait_msg(dev, msg);
         if (err < 0) {
                 dev_err(&intf->dev, "no version message answer\n");
-                goto free_dev;
+                goto free_msg;
         }
 
-        dev->net_count = (int)msg.msg.version_reply.nets;
-        dev->version = le32_to_cpu(msg.msg.version_reply.version);
+        dev->net_count = (int)msg->msg.version_reply.nets;
+        dev->version = le32_to_cpu(msg->msg.version_reply.version);
 
         if (device_create_file(&intf->dev, &dev_attr_firmware))
                 dev_err(&intf->dev,
@@ -1075,10 +1100,10 @@ static int esd_usb2_probe(struct usb_interface *intf,
         for (i = 0; i < dev->net_count; i++)
                 esd_usb2_probe_one_net(intf, i);
 
-        return 0;
-
-free_dev:
-        kfree(dev);
+free_msg:
+        kfree(msg);
+        if (err)
+                kfree(dev);
 done:
         return err;
 }
diff --git a/drivers/net/can/usb/kvaser_usb.c b/drivers/net/can/usb/kvaser_usb.c
index 45cb9f3c1324..3b9546588240 100644
--- a/drivers/net/can/usb/kvaser_usb.c
+++ b/drivers/net/can/usb/kvaser_usb.c
@@ -136,6 +136,9 @@
 #define KVASER_CTRL_MODE_SELFRECEPTION  3
 #define KVASER_CTRL_MODE_OFF            4
 
+/* log message */
+#define KVASER_EXTENDED_FRAME           BIT(31)
+
 struct kvaser_msg_simple {
         u8 tid;
         u8 channel;
@@ -817,8 +820,13 @@ static void kvaser_usb_rx_can_msg(const struct kvaser_usb *dev,
         priv = dev->nets[channel];
         stats = &priv->netdev->stats;
 
-        if (msg->u.rx_can.flag & (MSG_FLAG_ERROR_FRAME | MSG_FLAG_NERR |
-                                  MSG_FLAG_OVERRUN)) {
+        if ((msg->u.rx_can.flag & MSG_FLAG_ERROR_FRAME) &&
+            (msg->id == CMD_LOG_MESSAGE)) {
+                kvaser_usb_rx_error(dev, msg);
+                return;
+        } else if (msg->u.rx_can.flag & (MSG_FLAG_ERROR_FRAME |
+                                         MSG_FLAG_NERR |
+                                         MSG_FLAG_OVERRUN)) {
                 kvaser_usb_rx_can_err(priv, msg);
                 return;
         } else if (msg->u.rx_can.flag & ~MSG_FLAG_REMOTE_FRAME) {
@@ -834,22 +842,40 @@ static void kvaser_usb_rx_can_msg(const struct kvaser_usb *dev,
                 return;
         }
 
-        cf->can_id = ((msg->u.rx_can.msg[0] & 0x1f) << 6) |
-                     (msg->u.rx_can.msg[1] & 0x3f);
-        cf->can_dlc = get_can_dlc(msg->u.rx_can.msg[5]);
+        if (msg->id == CMD_LOG_MESSAGE) {
+                cf->can_id = le32_to_cpu(msg->u.log_message.id);
+                if (cf->can_id & KVASER_EXTENDED_FRAME)
+                        cf->can_id &= CAN_EFF_MASK | CAN_EFF_FLAG;
+                else
+                        cf->can_id &= CAN_SFF_MASK;
 
-        if (msg->id == CMD_RX_EXT_MESSAGE) {
-                cf->can_id <<= 18;
-                cf->can_id |= ((msg->u.rx_can.msg[2] & 0x0f) << 14) |
-                              ((msg->u.rx_can.msg[3] & 0xff) << 6) |
-                              (msg->u.rx_can.msg[4] & 0x3f);
-                cf->can_id |= CAN_EFF_FLAG;
-        }
+                cf->can_dlc = get_can_dlc(msg->u.log_message.dlc);
 
-        if (msg->u.rx_can.flag & MSG_FLAG_REMOTE_FRAME)
-                cf->can_id |= CAN_RTR_FLAG;
-        else
-                memcpy(cf->data, &msg->u.rx_can.msg[6], cf->can_dlc);
+                if (msg->u.log_message.flags & MSG_FLAG_REMOTE_FRAME)
+                        cf->can_id |= CAN_RTR_FLAG;
+                else
+                        memcpy(cf->data, &msg->u.log_message.data,
+                               cf->can_dlc);
+        } else {
+                cf->can_id = ((msg->u.rx_can.msg[0] & 0x1f) << 6) |
+                             (msg->u.rx_can.msg[1] & 0x3f);
+
+                if (msg->id == CMD_RX_EXT_MESSAGE) {
+                        cf->can_id <<= 18;
+                        cf->can_id |= ((msg->u.rx_can.msg[2] & 0x0f) << 14) |
+                                      ((msg->u.rx_can.msg[3] & 0xff) << 6) |
+                                      (msg->u.rx_can.msg[4] & 0x3f);
+                        cf->can_id |= CAN_EFF_FLAG;
+                }
+
+                cf->can_dlc = get_can_dlc(msg->u.rx_can.msg[5]);
+
+                if (msg->u.rx_can.flag & MSG_FLAG_REMOTE_FRAME)
+                        cf->can_id |= CAN_RTR_FLAG;
+                else
+                        memcpy(cf->data, &msg->u.rx_can.msg[6],
+                               cf->can_dlc);
+        }
 
         netif_rx(skb);
 
@@ -911,6 +937,7 @@ static void kvaser_usb_handle_message(const struct kvaser_usb *dev,
 
         case CMD_RX_STD_MESSAGE:
         case CMD_RX_EXT_MESSAGE:
+        case CMD_LOG_MESSAGE:
                 kvaser_usb_rx_can_msg(dev, msg);
                 break;
 
@@ -919,11 +946,6 @@ static void kvaser_usb_handle_message(const struct kvaser_usb *dev,
                 kvaser_usb_rx_error(dev, msg);
                 break;
 
-        case CMD_LOG_MESSAGE:
-                if (msg->u.log_message.flags & MSG_FLAG_ERROR_FRAME)
-                        kvaser_usb_rx_error(dev, msg);
-                break;
-
         case CMD_TX_ACKNOWLEDGE:
                 kvaser_usb_tx_acknowledge(dev, msg);
                 break;
diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_pro.c b/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
index 30d79bfa5b10..8ee9d1556e6e 100644
--- a/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_pro.c
@@ -504,15 +504,24 @@ static int pcan_usb_pro_restart_async(struct peak_usb_device *dev,
         return usb_submit_urb(urb, GFP_ATOMIC);
 }
 
-static void pcan_usb_pro_drv_loaded(struct peak_usb_device *dev, int loaded)
+static int pcan_usb_pro_drv_loaded(struct peak_usb_device *dev, int loaded)
 {
-        u8 buffer[16];
+        u8 *buffer;
+        int err;
+
+        buffer = kmalloc(PCAN_USBPRO_FCT_DRVLD_REQ_LEN, GFP_KERNEL);
+        if (!buffer)
+                return -ENOMEM;
 
         buffer[0] = 0;
         buffer[1] = !!loaded;
 
-        pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_FCT,
-                              PCAN_USBPRO_FCT_DRVLD, buffer, sizeof(buffer));
+        err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_FCT,
+                                    PCAN_USBPRO_FCT_DRVLD, buffer,
+                                    PCAN_USBPRO_FCT_DRVLD_REQ_LEN);
+        kfree(buffer);
+
+        return err;
 }
 
 static inline
@@ -851,21 +860,24 @@ static int pcan_usb_pro_stop(struct peak_usb_device *dev)
  */
 static int pcan_usb_pro_init(struct peak_usb_device *dev)
 {
-        struct pcan_usb_pro_interface *usb_if;
         struct pcan_usb_pro_device *pdev =
                         container_of(dev, struct pcan_usb_pro_device, dev);
+        struct pcan_usb_pro_interface *usb_if = NULL;
+        struct pcan_usb_pro_fwinfo *fi = NULL;
+        struct pcan_usb_pro_blinfo *bi = NULL;
+        int err;
 
         /* do this for 1st channel only */
         if (!dev->prev_siblings) {
-                struct pcan_usb_pro_fwinfo fi;
-                struct pcan_usb_pro_blinfo bi;
-                int err;
-
                 /* allocate netdevices common structure attached to first one */
                 usb_if = kzalloc(sizeof(struct pcan_usb_pro_interface),
                                  GFP_KERNEL);
-                if (!usb_if)
-                        return -ENOMEM;
+                fi = kmalloc(sizeof(struct pcan_usb_pro_fwinfo), GFP_KERNEL);
+                bi = kmalloc(sizeof(struct pcan_usb_pro_blinfo), GFP_KERNEL);
+                if (!usb_if || !fi || !bi) {
+                        err = -ENOMEM;
+                        goto err_out;
+                }
 
                 /* number of ts msgs to ignore before taking one into account */
                 usb_if->cm_ignore_count = 5;
@@ -877,34 +889,34 @@ static int pcan_usb_pro_init(struct peak_usb_device *dev)
                  */
                 err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_INFO,
                                             PCAN_USBPRO_INFO_FW,
-                                            &fi, sizeof(fi));
+                                            fi, sizeof(*fi));
                 if (err) {
-                        kfree(usb_if);
                         dev_err(dev->netdev->dev.parent,
                                 "unable to read %s firmware info (err %d)\n",
                                 pcan_usb_pro.name, err);
-                        return err;
+                        goto err_out;
                 }
 
                 err = pcan_usb_pro_send_req(dev, PCAN_USBPRO_REQ_INFO,
                                             PCAN_USBPRO_INFO_BL,
-                                            &bi, sizeof(bi));
+                                            bi, sizeof(*bi));
                 if (err) {
-                        kfree(usb_if);
                         dev_err(dev->netdev->dev.parent,
                                 "unable to read %s bootloader info (err %d)\n",
                                 pcan_usb_pro.name, err);
-                        return err;
+                        goto err_out;
                 }
 
+                /* tell the device the can driver is running */
+                err = pcan_usb_pro_drv_loaded(dev, 1);
+                if (err)
+                        goto err_out;
+
                 dev_info(dev->netdev->dev.parent,
                      "PEAK-System %s hwrev %u serial %08X.%08X (%u channels)\n",
                      pcan_usb_pro.name,
-                     bi.hw_rev, bi.serial_num_hi, bi.serial_num_lo,
+                     bi->hw_rev, bi->serial_num_hi, bi->serial_num_lo,
                      pcan_usb_pro.ctrl_count);
-
-                /* tell the device the can driver is running */
-                pcan_usb_pro_drv_loaded(dev, 1);
         } else {
                 usb_if = pcan_usb_pro_dev_if(dev->prev_siblings);
         }
@@ -916,6 +928,13 @@ static int pcan_usb_pro_init(struct peak_usb_device *dev)
         pcan_usb_pro_set_led(dev, 0, 1);
 
         return 0;
+
+ err_out:
+        kfree(bi);
+        kfree(fi);
+        kfree(usb_if);
+
+        return err;
 }
 
 static void pcan_usb_pro_exit(struct peak_usb_device *dev)
diff --git a/drivers/net/can/usb/peak_usb/pcan_usb_pro.h b/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
index a869918c5620..32275af547e0 100644
--- a/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
+++ b/drivers/net/can/usb/peak_usb/pcan_usb_pro.h
@@ -29,6 +29,7 @@
 
 /* Vendor Request value for XXX_FCT */
 #define PCAN_USBPRO_FCT_DRVLD           5 /* tell device driver is loaded */
+#define PCAN_USBPRO_FCT_DRVLD_REQ_LEN   16
 
 /* PCAN_USBPRO_INFO_BL vendor request record type */
 struct __packed pcan_usb_pro_blinfo {
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
index be59ec4b2c30..638e55435b04 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_cmn.c
@@ -3192,11 +3192,11 @@ static u32 bnx2x_xmit_type(struct bnx2x *bp, struct sk_buff *skb)
                 rc |= XMIT_CSUM_TCP;
 
         if (skb_is_gso_v6(skb)) {
-                rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP | XMIT_CSUM_V6);
+                rc |= (XMIT_GSO_V6 | XMIT_CSUM_TCP);
                 if (rc & XMIT_CSUM_ENC)
                         rc |= XMIT_GSO_ENC_V6;
         } else if (skb_is_gso(skb)) {
-                rc |= (XMIT_GSO_V4 | XMIT_CSUM_V4 | XMIT_CSUM_TCP);
+                rc |= (XMIT_GSO_V4 | XMIT_CSUM_TCP);
                 if (rc & XMIT_CSUM_ENC)
                         rc |= XMIT_GSO_ENC_V4;
         }
@@ -3483,19 +3483,18 @@ static void bnx2x_update_pbds_gso_enc(struct sk_buff *skb,
 {
         u16 hlen_w = 0;
         u8 outerip_off, outerip_len = 0;
+
         /* from outer IP to transport */
         hlen_w = (skb_inner_transport_header(skb) -
                   skb_network_header(skb)) >> 1;
 
         /* transport len */
-        if (xmit_type & XMIT_CSUM_TCP)
-                hlen_w += inner_tcp_hdrlen(skb) >> 1;
-        else
-                hlen_w += sizeof(struct udphdr) >> 1;
+        hlen_w += inner_tcp_hdrlen(skb) >> 1;
 
         pbd2->fw_ip_hdr_to_payload_w = hlen_w;
 
-        if (xmit_type & XMIT_CSUM_ENC_V4) {
+        /* outer IP header info */
+        if (xmit_type & XMIT_CSUM_V4) {
                 struct iphdr *iph = ip_hdr(skb);
                 pbd2->fw_ip_csum_wo_len_flags_frag =
                         bswab16(csum_fold((~iph->check) -
@@ -3818,8 +3817,7 @@ netdev_tx_t bnx2x_start_xmit(struct sk_buff *skb, struct net_device *dev)
                         bnx2x_set_pbd_gso_e2(skb, &pbd_e2_parsing_data,
                                              xmit_type);
                 else
-                        bnx2x_set_pbd_gso(skb, pbd_e1x, tx_start_bd,
-                                          xmit_type);
+                        bnx2x_set_pbd_gso(skb, pbd_e1x, first_bd, xmit_type);
         }
 
         /* Set the PBD's parsing_data field if not zero
diff --git a/drivers/net/ethernet/broadcom/tg3.c b/drivers/net/ethernet/broadcom/tg3.c
index 1f2dd928888a..c777b9013164 100644
--- a/drivers/net/ethernet/broadcom/tg3.c
+++ b/drivers/net/ethernet/broadcom/tg3.c
@@ -1800,6 +1800,9 @@ static int tg3_poll_fw(struct tg3 *tp)
         int i;
         u32 val;
 
+        if (tg3_flag(tp, NO_FWARE_REPORTED))
+                return 0;
+
         if (tg3_flag(tp, IS_SSB_CORE)) {
                 /* We don't use firmware. */
                 return 0;
@@ -9468,6 +9471,14 @@ static void tg3_rss_write_indir_tbl(struct tg3 *tp)
         }
 }
 
+static inline u32 tg3_lso_rd_dma_workaround_bit(struct tg3 *tp)
+{
+        if (tg3_asic_rev(tp) == ASIC_REV_5719)
+                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5719;
+        else
+                return TG3_LSO_RD_DMA_TX_LENGTH_WA_5720;
+}
+
 /* tp->lock is held. */
 static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
 {
@@ -10153,16 +10164,17 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
         tw32_f(RDMAC_MODE, rdmac_mode);
         udelay(40);
 
-        if (tg3_asic_rev(tp) == ASIC_REV_5719) {
+        if (tg3_asic_rev(tp) == ASIC_REV_5719 ||
+            tg3_asic_rev(tp) == ASIC_REV_5720) {
                 for (i = 0; i < TG3_NUM_RDMA_CHANNELS; i++) {
                         if (tr32(TG3_RDMA_LENGTH + (i << 2)) > TG3_MAX_MTU(tp))
                                 break;
                 }
                 if (i < TG3_NUM_RDMA_CHANNELS) {
                         val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
-                        val |= TG3_LSO_RD_DMA_TX_LENGTH_WA;
+                        val |= tg3_lso_rd_dma_workaround_bit(tp);
                         tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
-                        tg3_flag_set(tp, 5719_RDMA_BUG);
+                        tg3_flag_set(tp, 5719_5720_RDMA_BUG);
                 }
         }
 
@@ -10395,6 +10407,13 @@ static int tg3_reset_hw(struct tg3 *tp, bool reset_phy)
  */
 static int tg3_init_hw(struct tg3 *tp, bool reset_phy)
 {
+        /* Chip may have been just powered on. If so, the boot code may still
+         * be running initialization. Wait for it to finish to avoid races in
+         * accessing the hardware.
+         */
+        tg3_enable_register_access(tp);
+        tg3_poll_fw(tp);
+
         tg3_switch_clocks(tp);
 
         tw32(TG3PCI_MEM_WIN_BASE_ADDR, 0);
@@ -10526,15 +10545,15 @@ static void tg3_periodic_fetch_stats(struct tg3 *tp)
         TG3_STAT_ADD32(&sp->tx_ucast_packets, MAC_TX_STATS_UCAST);
         TG3_STAT_ADD32(&sp->tx_mcast_packets, MAC_TX_STATS_MCAST);
         TG3_STAT_ADD32(&sp->tx_bcast_packets, MAC_TX_STATS_BCAST);
-        if (unlikely(tg3_flag(tp, 5719_RDMA_BUG) &&
+        if (unlikely(tg3_flag(tp, 5719_5720_RDMA_BUG) &&
                      (sp->tx_ucast_packets.low + sp->tx_mcast_packets.low +
                       sp->tx_bcast_packets.low) > TG3_NUM_RDMA_CHANNELS)) {
                 u32 val;
 
                 val = tr32(TG3_LSO_RD_DMA_CRPTEN_CTRL);
-                val &= ~TG3_LSO_RD_DMA_TX_LENGTH_WA;
+                val &= ~tg3_lso_rd_dma_workaround_bit(tp);
                 tw32(TG3_LSO_RD_DMA_CRPTEN_CTRL, val);
-                tg3_flag_clear(tp, 5719_RDMA_BUG);
+                tg3_flag_clear(tp, 5719_5720_RDMA_BUG);
         }
 
         TG3_STAT_ADD32(&sp->rx_octets, MAC_RX_STATS_OCTETS);
diff --git a/drivers/net/ethernet/broadcom/tg3.h b/drivers/net/ethernet/broadcom/tg3.h
index 9b2d3ac2474a..ff6e30eeae35 100644
--- a/drivers/net/ethernet/broadcom/tg3.h
+++ b/drivers/net/ethernet/broadcom/tg3.h
@@ -1422,7 +1422,8 @@
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL      0x00004910
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K    0x00030000
 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K   0x000c0000
-#define TG3_LSO_RD_DMA_TX_LENGTH_WA      0x02000000
+#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5719         0x02000000
+#define TG3_LSO_RD_DMA_TX_LENGTH_WA_5720         0x00200000
 /* 0x4914 --> 0x4be0 unused */
 
 #define TG3_NUM_RDMA_CHANNELS           4
@@ -3059,7 +3060,7 @@ enum TG3_FLAGS {
         TG3_FLAG_APE_HAS_NCSI,
         TG3_FLAG_TX_TSTAMP_EN,
         TG3_FLAG_4K_FIFO_LIMIT,
-        TG3_FLAG_5719_RDMA_BUG,
+        TG3_FLAG_5719_5720_RDMA_BUG,
         TG3_FLAG_RESET_TASK_PENDING,
         TG3_FLAG_PTP_CAPABLE,
         TG3_FLAG_5705_PLUS,
diff --git a/drivers/net/ethernet/dec/tulip/interrupt.c b/drivers/net/ethernet/dec/tulip/interrupt.c
index 28a5e425fecf..92306b320840 100644
--- a/drivers/net/ethernet/dec/tulip/interrupt.c
+++ b/drivers/net/ethernet/dec/tulip/interrupt.c
@@ -76,6 +76,12 @@ int tulip_refill_rx(struct net_device *dev)
 
                         mapping = pci_map_single(tp->pdev, skb->data, PKT_BUF_SZ,
                                                  PCI_DMA_FROMDEVICE);
+                        if (dma_mapping_error(&tp->pdev->dev, mapping)) {
+                                dev_kfree_skb(skb);
+                                tp->rx_buffers[entry].skb = NULL;
+                                break;
+                        }
+
                         tp->rx_buffers[entry].mapping = mapping;
 
                         tp->rx_ring[entry].buffer1 = cpu_to_le32(mapping);
diff --git a/drivers/net/ethernet/emulex/benet/be.h b/drivers/net/ethernet/emulex/benet/be.h
index f544b297c9ab..0a510684e468 100644
--- a/drivers/net/ethernet/emulex/benet/be.h
+++ b/drivers/net/ethernet/emulex/benet/be.h
@@ -262,6 +262,7 @@ struct be_rx_compl_info {
         u8 ipv6;
         u8 vtm;
         u8 pkt_type;
+        u8 ip_frag;
 };
 
 struct be_rx_obj {
diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c
index a236ecd27cf3..1db2df61b8af 100644
--- a/drivers/net/ethernet/emulex/benet/be_cmds.c
+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c
@@ -562,7 +562,7 @@ int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
 
         resource_error = lancer_provisioning_error(adapter);
         if (resource_error)
-                return -1;
+                return -EAGAIN;
 
         status = lancer_wait_ready(adapter);
         if (!status) {
@@ -590,8 +590,8 @@ int lancer_test_and_set_rdy_state(struct be_adapter *adapter)
          * when PF provisions resources.
          */
         resource_error = lancer_provisioning_error(adapter);
-        if (status == -1 && !resource_error)
-                adapter->eeh_error = true;
+        if (resource_error)
+                status = -EAGAIN;
 
         return status;
 }
diff --git a/drivers/net/ethernet/emulex/benet/be_hw.h b/drivers/net/ethernet/emulex/benet/be_hw.h
index 3c1099b47f2a..8780183c6d1c 100644
--- a/drivers/net/ethernet/emulex/benet/be_hw.h
+++ b/drivers/net/ethernet/emulex/benet/be_hw.h
@@ -356,7 +356,7 @@ struct amap_eth_rx_compl_v0 {
         u8 ip_version;          /* dword 1 */
         u8 macdst[6];           /* dword 1 */
         u8 vtp;                 /* dword 1 */
-        u8 rsvd0;               /* dword 1 */
+        u8 ip_frag;             /* dword 1 */
         u8 fragndx[10];         /* dword 1 */
         u8 ct[2];               /* dword 1 */
         u8 sw;                  /* dword 1 */
diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c
index ca2967b0f18b..a0b4be51f0d1 100644
--- a/drivers/net/ethernet/emulex/benet/be_main.c
+++ b/drivers/net/ethernet/emulex/benet/be_main.c
@@ -1599,6 +1599,8 @@ static void be_parse_rx_compl_v0(struct be_eth_rx_compl *compl,
                                                compl);
         }
         rxcp->port = AMAP_GET_BITS(struct amap_eth_rx_compl_v0, port, compl);
+        rxcp->ip_frag = AMAP_GET_BITS(struct amap_eth_rx_compl_v0,
+                                      ip_frag, compl);
 }
 
 static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
@@ -1620,6 +1622,9 @@ static struct be_rx_compl_info *be_rx_compl_get(struct be_rx_obj *rxo)
         else
                 be_parse_rx_compl_v0(compl, rxcp);
 
+        if (rxcp->ip_frag)
+                rxcp->l4_csum = 0;
+
         if (rxcp->vlanf) {
                 /* vlanf could be wrongly set in some cards.
                  * ignore if vtm is not set */
@@ -2168,7 +2173,7 @@ static irqreturn_t be_msix(int irq, void *dev)
 
 static inline bool do_gro(struct be_rx_compl_info *rxcp)
 {
-        return (rxcp->tcpf && !rxcp->err) ? true : false;
+        return (rxcp->tcpf && !rxcp->err && rxcp->l4_csum) ? true : false;
 }
 
 static int be_process_rx(struct be_rx_obj *rxo, struct napi_struct *napi,
@@ -4093,6 +4098,7 @@ static int be_get_initial_config(struct be_adapter *adapter)
 
 static int lancer_recover_func(struct be_adapter *adapter)
 {
+        struct device *dev = &adapter->pdev->dev;
         int status;
 
         status = lancer_test_and_set_rdy_state(adapter);
@@ -4104,8 +4110,7 @@ static int lancer_recover_func(struct be_adapter *adapter)
 
         be_clear(adapter);
 
-        adapter->hw_error = false;
-        adapter->fw_timeout = false;
+        be_clear_all_error(adapter);
 
         status = be_setup(adapter);
         if (status)
@@ -4117,13 +4122,13 @@ static int lancer_recover_func(struct be_adapter *adapter)
                         goto err;
         }
 
-        dev_err(&adapter->pdev->dev,
-                "Adapter SLIPORT recovery succeeded\n");
+        dev_err(dev, "Error recovery successful\n");
         return 0;
 err:
-        if (adapter->eeh_error)
-                dev_err(&adapter->pdev->dev,
-                        "Adapter SLIPORT recovery failed\n");
+        if (status == -EAGAIN)
+                dev_err(dev, "Waiting for resource provisioning\n");
+        else
+                dev_err(dev, "Error recovery failed\n");
 
         return status;
 }
@@ -4132,28 +4137,27 @@ static void be_func_recovery_task(struct work_struct *work)
 {
         struct be_adapter *adapter =
                 container_of(work, struct be_adapter,  func_recovery_work.work);
-        int status;
+        int status = 0;
 
         be_detect_error(adapter);
 
         if (adapter->hw_error && lancer_chip(adapter)) {
 
-                if (adapter->eeh_error)
-                        goto out;
-
                 rtnl_lock();
                 netif_device_detach(adapter->netdev);
                 rtnl_unlock();
 
                 status = lancer_recover_func(adapter);
-
                 if (!status)
                         netif_device_attach(adapter->netdev);
         }
 
-out:
-        schedule_delayed_work(&adapter->func_recovery_work,
-                              msecs_to_jiffies(1000));
+        /* In Lancer, for all errors other than provisioning error (-EAGAIN),
+         * no need to attempt further recovery.
+         */
+        if (!status || status == -EAGAIN)
+                schedule_delayed_work(&adapter->func_recovery_work,
+                                      msecs_to_jiffies(1000));
 }
 
 static void be_worker(struct work_struct *work)
@@ -4258,6 +4262,9 @@ static int be_probe(struct pci_dev *pdev, const struct pci_device_id *pdev_id)
                 netdev->features |= NETIF_F_HIGHDMA;
         } else {
                 status = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
+                if (!status)
+                        status = dma_set_coherent_mask(&pdev->dev,
+                                                       DMA_BIT_MASK(32));
                 if (status) {
                         dev_err(&pdev->dev, "Could not set PCI DMA Mask\n");
                         goto free_netdev;
@@ -4436,20 +4443,19 @@ static pci_ers_result_t be_eeh_err_detected(struct pci_dev *pdev,
 
         dev_err(&adapter->pdev->dev, "EEH error detected\n");
 
-        adapter->eeh_error = true;
+        if (!adapter->eeh_error) {
+                adapter->eeh_error = true;
 
-        cancel_delayed_work_sync(&adapter->func_recovery_work);
-
-        rtnl_lock();
-        netif_device_detach(netdev);
-        rtnl_unlock();
+                cancel_delayed_work_sync(&adapter->func_recovery_work);
 
-        if (netif_running(netdev)) {
                 rtnl_lock();
-                be_close(netdev);
+                netif_device_detach(netdev);
+                if (netif_running(netdev))
+                        be_close(netdev);
                 rtnl_unlock();
+
+                be_clear(adapter);
         }
-        be_clear(adapter);
 
         if (state == pci_channel_io_perm_failure)
                 return PCI_ERS_RESULT_DISCONNECT;
@@ -4474,7 +4480,6 @@ static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
         int status;
 
         dev_info(&adapter->pdev->dev, "EEH reset\n");
-        be_clear_all_error(adapter);
 
         status = pci_enable_device(pdev);
         if (status)
@@ -4492,6 +4497,7 @@ static pci_ers_result_t be_eeh_reset(struct pci_dev *pdev)
                 return PCI_ERS_RESULT_DISCONNECT;
 
         pci_cleanup_aer_uncorrect_error_status(pdev);
+        be_clear_all_error(adapter);
         return PCI_ERS_RESULT_RECOVERED;
 }
 
diff --git a/drivers/net/ethernet/freescale/fec_main.c b/drivers/net/ethernet/freescale/fec_main.c
index 85a06037b242..a667015be22a 100644
--- a/drivers/net/ethernet/freescale/fec_main.c
+++ b/drivers/net/ethernet/freescale/fec_main.c
@@ -1038,6 +1038,18 @@ static void fec_get_mac(struct net_device *ndev)
                 iap = &tmpaddr[0];
         }
 
+        /*
+         * 5) random mac address
+         */
+        if (!is_valid_ether_addr(iap)) {
+                /* Report it and use a random ethernet address instead */
+                netdev_err(ndev, "Invalid MAC address: %pM\n", iap);
+                eth_hw_addr_random(ndev);
+                netdev_info(ndev, "Using random MAC address: %pM\n",
+                            ndev->dev_addr);
+                return;
+        }
+
         memcpy(ndev->dev_addr, iap, ETH_ALEN);
 
         /* Adjust MAC if using macaddr */
diff --git a/drivers/net/ethernet/mellanox/mlx4/cmd.c b/drivers/net/ethernet/mellanox/mlx4/cmd.c
index 1df56cc50ee9..0e572a527154 100644
--- a/drivers/net/ethernet/mellanox/mlx4/cmd.c
+++ b/drivers/net/ethernet/mellanox/mlx4/cmd.c
@@ -222,8 +222,6 @@ static int mlx4_comm_cmd_poll(struct mlx4_dev *dev, u8 cmd, u16 param,
                  * FLR process. The only non-zero result in the RESET command
                  * is MLX4_DELAY_RESET_SLAVE*/
                 if ((MLX4_COMM_CMD_RESET == cmd)) {
-                        mlx4_warn(dev, "Got slave FLRed from Communication"
-                                  " channel (ret:0x%x)\n", ret_from_pending);
                         err = MLX4_DELAY_RESET_SLAVE;
                 } else {
                         mlx4_warn(dev, "Communication channel timed out\n");
diff --git a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
index b35f94700093..89c47ea84b50 100644
--- a/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
+++ b/drivers/net/ethernet/mellanox/mlx4/en_netdev.c
@@ -1323,6 +1323,7 @@ static void mlx4_en_auto_moderation(struct mlx4_en_priv *priv)
                         priv->last_moder_time[ring] = moder_time;
                         cq = &priv->rx_cq[ring];
                         cq->moder_time = moder_time;
+                        cq->moder_cnt = priv->rx_frames;
                         err = mlx4_en_set_cq_moder(priv, cq);
                         if (err)
                                 en_err(priv, "Failed modifying moderation for cq:%d\n",
@@ -2118,6 +2119,7 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
         struct mlx4_en_priv *priv;
         int i;
         int err;
+        u64 mac_u64;
 
         dev = alloc_etherdev_mqs(sizeof(struct mlx4_en_priv),
                                  MAX_TX_RINGS, MAX_RX_RINGS);
@@ -2191,10 +2193,17 @@ int mlx4_en_init_netdev(struct mlx4_en_dev *mdev, int port,
         dev->addr_len = ETH_ALEN;
         mlx4_en_u64_to_mac(dev->dev_addr, mdev->dev->caps.def_mac[priv->port]);
         if (!is_valid_ether_addr(dev->dev_addr)) {
-                en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
-                       priv->port, dev->dev_addr);
-                err = -EINVAL;
-                goto out;
+                if (mlx4_is_slave(priv->mdev->dev)) {
+                        eth_hw_addr_random(dev);
+                        en_warn(priv, "Assigned random MAC address %pM\n", dev->dev_addr);
+                        mac_u64 = mlx4_en_mac_to_u64(dev->dev_addr);
+                        mdev->dev->caps.def_mac[priv->port] = mac_u64;
+                } else {
+                        en_err(priv, "Port: %d, invalid mac burned: %pM, quiting\n",
+                               priv->port, dev->dev_addr);
+                        err = -EINVAL;
+                        goto out;
+                }
         }
 
         memcpy(priv->prev_mac, dev->dev_addr, sizeof(priv->prev_mac));
diff --git a/drivers/net/ethernet/mellanox/mlx4/fw.c b/drivers/net/ethernet/mellanox/mlx4/fw.c
index 58a8e535d698..2c97901c6a6d 100644
--- a/drivers/net/ethernet/mellanox/mlx4/fw.c
+++ b/drivers/net/ethernet/mellanox/mlx4/fw.c
@@ -840,12 +840,16 @@ int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave,
                            MLX4_CMD_NATIVE);
 
         if (!err && dev->caps.function != slave) {
-                /* set slave default_mac address */
-                MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
-                def_mac += slave << 8;
                 /* if config MAC in DB use it */
                 if (priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac)
                         def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac;
+                else {
+                        /* set slave default_mac address */
+                        MLX4_GET(def_mac, outbox->buf, QUERY_PORT_MAC_OFFSET);
+                        def_mac += slave << 8;
+                        priv->mfunc.master.vf_admin[slave].vport[vhcr->in_modifier].mac = def_mac;
+                }
+
                 MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET);
 
                 /* get port type - currently only eth is enabled */
diff --git a/drivers/net/ethernet/mellanox/mlx4/main.c b/drivers/net/ethernet/mellanox/mlx4/main.c
index 0d32a82458bf..2f4a26039e80 100644
--- a/drivers/net/ethernet/mellanox/mlx4/main.c
+++ b/drivers/net/ethernet/mellanox/mlx4/main.c
@@ -1290,7 +1290,6 @@ static int mlx4_init_slave(struct mlx4_dev *dev)
 {
         struct mlx4_priv *priv = mlx4_priv(dev);
         u64 dma = (u64) priv->mfunc.vhcr_dma;
-        int num_of_reset_retries = NUM_OF_RESET_RETRIES;
         int ret_from_reset = 0;
         u32 slave_read;
         u32 cmd_channel_ver;
@@ -1304,18 +1303,10 @@ static int mlx4_init_slave(struct mlx4_dev *dev)
          * NUM_OF_RESET_RETRIES times before leaving.*/
         if (ret_from_reset) {
                 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
-                        msleep(SLEEP_TIME_IN_RESET);
-                        while (ret_from_reset && num_of_reset_retries) {
-                                mlx4_warn(dev, "slave is currently in the"
-                                          "middle of FLR. retrying..."
-                                          "(try num:%d)\n",
-                                          (NUM_OF_RESET_RETRIES -
-                                           num_of_reset_retries  + 1));
-                                ret_from_reset =
-                                        mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET,
-                                                      0, MLX4_COMM_TIME);
-                                num_of_reset_retries = num_of_reset_retries - 1;
-                        }
+                        mlx4_warn(dev, "slave is currently in the "
+                                  "middle of FLR. Deferring probe.\n");
+                        mutex_unlock(&priv->cmd.slave_cmd_mutex);
+                        return -EPROBE_DEFER;
                 } else
                         goto err;
         }
@@ -1526,7 +1517,8 @@ static int mlx4_init_hca(struct mlx4_dev *dev)
         } else {
                 err = mlx4_init_slave(dev);
                 if (err) {
-                        mlx4_err(dev, "Failed to initialize slave\n");
+                        if (err != -EPROBE_DEFER)
+                                mlx4_err(dev, "Failed to initialize slave\n");
                         return err;
                 }
 
diff --git a/drivers/net/ethernet/qlogic/qlge/qlge_main.c b/drivers/net/ethernet/qlogic/qlge/qlge_main.c
index 50235d201592..f87cc216045b 100644
--- a/drivers/net/ethernet/qlogic/qlge/qlge_main.c
+++ b/drivers/net/ethernet/qlogic/qlge/qlge_main.c
@@ -4717,6 +4717,7 @@ static int qlge_probe(struct pci_dev *pdev,
                 dev_err(&pdev->dev, "net device registration failed.\n");
                 ql_release_all(pdev);
                 pci_disable_device(pdev);
+                free_netdev(ndev);
                 return err;
         }
         /* Start up the timer to trigger EEH if
diff --git a/drivers/net/ethernet/renesas/sh_eth.c b/drivers/net/ethernet/renesas/sh_eth.c
index 42e9dd05c936..5e3982fc5398 100644
--- a/drivers/net/ethernet/renesas/sh_eth.c
+++ b/drivers/net/ethernet/renesas/sh_eth.c
@@ -897,8 +897,8 @@ static int sh_eth_check_reset(struct net_device *ndev)
                 mdelay(1);
                 cnt--;
         }
-        if (cnt < 0) {
-                pr_err("Device reset fail\n");
+        if (cnt <= 0) {
+                pr_err("Device reset failed\n");
                 ret = -ETIMEDOUT;
         }
         return ret;
@@ -1401,16 +1401,23 @@ static int sh_eth_rx(struct net_device *ndev, u32 intr_status)
                 desc_status = edmac_to_cpu(mdp, rxdesc->status);
                 pkt_len = rxdesc->frame_length;
 
-#if defined(CONFIG_ARCH_R8A7740)
-                desc_status >>= 16;
-#endif
-
                 if (--boguscnt < 0)
                         break;
 
                 if (!(desc_status & RDFEND))
                         ndev->stats.rx_length_errors++;
 
+#if defined(CONFIG_ARCH_R8A7740)
+                /*
+                 * In case of almost all GETHER/ETHERs, the Receive Frame State
+                 * (RFS) bits in the Receive Descriptor 0 are from bit 9 to
+                 * bit 0. However, in case of the R8A7740's GETHER, the RFS
+                 * bits are from bit 25 to bit 16. So, the driver needs right
+                 * shifting by 16.
+                 */
+                desc_status >>= 16;
+#endif
+
                 if (desc_status & (RD_RFS1 | RD_RFS2 | RD_RFS3 | RD_RFS4 |
                                    RD_RFS5 | RD_RFS6 | RD_RFS10)) {
                         ndev->stats.rx_errors++;
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 618446ae1ec1..ee919ca8b8a0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -1899,7 +1899,7 @@ static netdev_tx_t stmmac_xmit(struct sk_buff *skb, struct net_device *dev)
 
 #ifdef STMMAC_XMIT_DEBUG
         if (netif_msg_pktdata(priv)) {
-                pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d"
+                pr_info("%s: curr %d dirty=%d entry=%d, first=%p, nfrags=%d",
                         __func__, (priv->cur_tx % txsize),
                         (priv->dirty_tx % txsize), entry, first, nfrags);
                 if (priv->extend_desc)
diff --git a/drivers/net/ethernet/ti/davinci_mdio.c b/drivers/net/ethernet/ti/davinci_mdio.c
index 12aec173564c..c47f0dbcebb5 100644
--- a/drivers/net/ethernet/ti/davinci_mdio.c
+++ b/drivers/net/ethernet/ti/davinci_mdio.c
@@ -449,10 +449,9 @@ static int davinci_mdio_suspend(struct device *dev)
         __raw_writel(ctrl, &data->regs->control);
         wait_for_idle(data);
 
-        pm_runtime_put_sync(data->dev);
-
         data->suspended = true;
         spin_unlock(&data->lock);
+        pm_runtime_put_sync(data->dev);
 
         return 0;
 }
@@ -460,15 +459,12 @@ static int davinci_mdio_suspend(struct device *dev)
 static int davinci_mdio_resume(struct device *dev)
 {
         struct davinci_mdio_data *data = dev_get_drvdata(dev);
-        u32 ctrl;
 
-        spin_lock(&data->lock);
         pm_runtime_get_sync(data->dev);
 
+        spin_lock(&data->lock);
         /* restart the scan state machine */
-        ctrl = __raw_readl(&data->regs->control);
-        ctrl |= CONTROL_ENABLE;
-        __raw_writel(ctrl, &data->regs->control);
+        __davinci_mdio_reset(data);
 
         data->suspended = false;
         spin_unlock(&data->lock);
@@ -477,8 +473,8 @@ static int davinci_mdio_resume(struct device *dev)
 }
 
 static const struct dev_pm_ops davinci_mdio_pm_ops = {
-        .suspend        = davinci_mdio_suspend,
-        .resume         = davinci_mdio_resume,
+        .suspend_late   = davinci_mdio_suspend,
+        .resume_early   = davinci_mdio_resume,
 };
 
 static const struct of_device_id davinci_mdio_of_mtable[] = {
diff --git a/drivers/net/ethernet/xilinx/xilinx_emaclite.c b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
index 919b983114e9..b7268b3dae77 100644
--- a/drivers/net/ethernet/xilinx/xilinx_emaclite.c
+++ b/drivers/net/ethernet/xilinx/xilinx_emaclite.c
@@ -946,7 +946,8 @@ static int xemaclite_open(struct net_device *dev)
                 phy_write(lp->phy_dev, MII_CTRL1000, 0);
 
                 /* Advertise only 10 and 100mbps full/half duplex speeds */
-                phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL);
+                phy_write(lp->phy_dev, MII_ADVERTISE, ADVERTISE_ALL |
+                          ADVERTISE_CSMA);
 
                 /* Restart auto negotiation */
                 bmcr = phy_read(lp->phy_dev, MII_BMCR);
diff --git a/drivers/net/hyperv/netvsc_drv.c b/drivers/net/hyperv/netvsc_drv.c
index 088c55496191..ab2307b5d9a7 100644
--- a/drivers/net/hyperv/netvsc_drv.c
+++ b/drivers/net/hyperv/netvsc_drv.c
@@ -31,6 +31,7 @@
 #include <linux/inetdevice.h>
 #include <linux/etherdevice.h>
 #include <linux/skbuff.h>
+#include <linux/if_vlan.h>
 #include <linux/in.h>
 #include <linux/slab.h>
 #include <net/arp.h>
@@ -284,7 +285,7 @@ int netvsc_recv_callback(struct hv_device *device_obj,
 
         skb->protocol = eth_type_trans(skb, net);
         skb->ip_summed = CHECKSUM_NONE;
-        skb->vlan_tci = packet->vlan_tci;
+        __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), packet->vlan_tci);
 
         net->stats.rx_packets++;
         net->stats.rx_bytes += packet->total_data_buflen;
diff --git a/drivers/net/macvlan.c b/drivers/net/macvlan.c
index 1c502bb0c916..6e91931a1c2c 100644
--- a/drivers/net/macvlan.c
+++ b/drivers/net/macvlan.c
@@ -853,18 +853,24 @@ static int macvlan_changelink(struct net_device *dev,
                 struct nlattr *tb[], struct nlattr *data[])
 {
         struct macvlan_dev *vlan = netdev_priv(dev);
-        if (data && data[IFLA_MACVLAN_MODE])
-                vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
+
         if (data && data[IFLA_MACVLAN_FLAGS]) {
                 __u16 flags = nla_get_u16(data[IFLA_MACVLAN_FLAGS]);
                 bool promisc = (flags ^ vlan->flags) & MACVLAN_FLAG_NOPROMISC;
-
-                if (promisc && (flags & MACVLAN_FLAG_NOPROMISC))
-                        dev_set_promiscuity(vlan->lowerdev, -1);
-                else if (promisc && !(flags & MACVLAN_FLAG_NOPROMISC))
-                        dev_set_promiscuity(vlan->lowerdev, 1);
+                if (vlan->port->passthru && promisc) {
+                        int err;
+
+                        if (flags & MACVLAN_FLAG_NOPROMISC)
+                                err = dev_set_promiscuity(vlan->lowerdev, -1);
+                        else
+                                err = dev_set_promiscuity(vlan->lowerdev, 1);
+                        if (err < 0)
+                                return err;
+                }
                 vlan->flags = flags;
         }
+        if (data && data[IFLA_MACVLAN_MODE])
+                vlan->mode = nla_get_u32(data[IFLA_MACVLAN_MODE]);
         return 0;
 }
 
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index c14f14741b3f..38f0b312ff85 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -1044,7 +1044,7 @@ int phy_init_eee(struct phy_device *phydev, bool clk_stop_enable)
                 adv = mmd_eee_adv_to_ethtool_adv_t(eee_adv);
                 lp = mmd_eee_adv_to_ethtool_adv_t(eee_lp);
                 idx = phy_find_setting(phydev->speed, phydev->duplex);
-                if ((lp & adv & settings[idx].setting))
+                if (!(lp & adv & settings[idx].setting))
                         goto eee_exit;
 
                 if (clk_stop_enable) {
diff --git a/drivers/net/team/team.c b/drivers/net/team/team.c
index 7c43261975bd..b3051052f3ad 100644
--- a/drivers/net/team/team.c
+++ b/drivers/net/team/team.c
@@ -1092,8 +1092,8 @@ static int team_port_add(struct team *team, struct net_device *port_dev)
         }
 
         port->index = -1;
-        team_port_enable(team, port);
         list_add_tail_rcu(&port->list, &team->port_list);
+        team_port_enable(team, port);
         __team_compute_features(team);
         __team_port_change_port_added(port, !!netif_carrier_ok(port_dev));
         __team_options_change_check(team);
@@ -2374,7 +2374,8 @@ static int team_nl_send_port_list_get(struct team *team, u32 portid, u32 seq,
         bool incomplete;
         int i;
 
-        port = list_first_entry(&team->port_list, struct team_port, list);
+        port = list_first_entry_or_null(&team->port_list,
+                                        struct team_port, list);
 
 start_again:
         err = __send_and_alloc_skb(&skb, team, portid, send_func);
@@ -2402,8 +2403,8 @@ start_again:
                 err = team_nl_fill_one_port_get(skb, one_port);
                 if (err)
                         goto errout;
-        } else {
-                list_for_each_entry(port, &team->port_list, list) {
+        } else if (port) {
+                list_for_each_entry_from(port, &team->port_list, list) {
                         err = team_nl_fill_one_port_get(skb, port);
                         if (err) {
                                 if (err == -EMSGSIZE) {
diff --git a/drivers/net/team/team_mode_random.c b/drivers/net/team/team_mode_random.c
index 5ca14d463ba7..7f032e211343 100644
--- a/drivers/net/team/team_mode_random.c
+++ b/drivers/net/team/team_mode_random.c
@@ -28,6 +28,8 @@ static bool rnd_transmit(struct team *team, struct sk_buff *skb)
 
         port_index = random_N(team->en_port_count);
         port = team_get_port_by_index_rcu(team, port_index);
+        if (unlikely(!port))
+                goto drop;
         port = team_get_first_port_txable_rcu(team, port);
         if (unlikely(!port))
                 goto drop;
diff --git a/drivers/net/team/team_mode_roundrobin.c b/drivers/net/team/team_mode_roundrobin.c
index d268e4de781b..472623f8ce3d 100644
--- a/drivers/net/team/team_mode_roundrobin.c
+++ b/drivers/net/team/team_mode_roundrobin.c
@@ -32,6 +32,8 @@ static bool rr_transmit(struct team *team, struct sk_buff *skb)
 
         port_index = rr_priv(team)->sent_packets++ % team->en_port_count;
         port = team_get_port_by_index_rcu(team, port_index);
+        if (unlikely(!port))
+                goto drop;
         port = team_get_first_port_txable_rcu(team, port);
         if (unlikely(!port))
                 goto drop;
diff --git a/drivers/net/tun.c b/drivers/net/tun.c
index f042b0373e5d..bfa9bb48e42d 100644
--- a/drivers/net/tun.c
+++ b/drivers/net/tun.c
@@ -352,7 +352,7 @@ static u16 tun_select_queue(struct net_device *dev, struct sk_buff *skb)
         u32 numqueues = 0;
 
         rcu_read_lock();
-        numqueues = tun->numqueues;
+        numqueues = ACCESS_ONCE(tun->numqueues);
 
         txq = skb_get_rxhash(skb);
         if (txq) {
@@ -1585,6 +1585,10 @@ static int tun_set_iff(struct net *net, struct file *file, struct ifreq *ifr)
                 else
                         return -EINVAL;
 
+                if (!!(ifr->ifr_flags & IFF_MULTI_QUEUE) !=
+                    !!(tun->flags & TUN_TAP_MQ))
+                        return -EINVAL;
+
                 if (tun_not_capable(tun))
                         return -EPERM;
                 err = security_tun_dev_open(tun->security);
@@ -2155,6 +2159,8 @@ static int tun_chr_open(struct inode *inode, struct file * file)
         set_bit(SOCK_EXTERNALLY_ALLOCATED, &tfile->socket.flags);
         INIT_LIST_HEAD(&tfile->next);
 
+        sock_set_flag(&tfile->sk, SOCK_ZEROCOPY);
+
         return 0;
 }
 
diff --git a/drivers/net/usb/cdc_ether.c b/drivers/net/usb/cdc_ether.c
index 078795fe6e31..04ee044dde51 100644
--- a/drivers/net/usb/cdc_ether.c
+++ b/drivers/net/usb/cdc_ether.c
@@ -627,6 +627,12 @@ static const struct usb_device_id	products [] = {
         .driver_info = 0,
 },
 
+/* Huawei E1820 - handled by qmi_wwan */
+{
+        USB_DEVICE_INTERFACE_NUMBER(HUAWEI_VENDOR_ID, 0x14ac, 1),
+        .driver_info = 0,
+},
+
 /* Realtek RTL8152 Based USB 2.0 Ethernet Adapters */
 #if defined(CONFIG_USB_RTL8152) || defined(CONFIG_USB_RTL8152_MODULE)
 {
diff --git a/drivers/net/usb/qmi_wwan.c b/drivers/net/usb/qmi_wwan.c
index 86adfa0a912e..d095d0d3056b 100644
--- a/drivers/net/usb/qmi_wwan.c
+++ b/drivers/net/usb/qmi_wwan.c
@@ -519,6 +519,7 @@ static const struct usb_device_id products[] = {
         /* 3. Combined interface devices matching on interface number */
         {QMI_FIXED_INTF(0x0408, 0xea42, 4)},    /* Yota / Megafon M100-1 */
         {QMI_FIXED_INTF(0x12d1, 0x140c, 1)},    /* Huawei E173 */
+        {QMI_FIXED_INTF(0x12d1, 0x14ac, 1)},    /* Huawei E1820 */
         {QMI_FIXED_INTF(0x19d2, 0x0002, 1)},
         {QMI_FIXED_INTF(0x19d2, 0x0012, 1)},
         {QMI_FIXED_INTF(0x19d2, 0x0017, 3)},
diff --git a/drivers/net/wireless/ath/ath9k/Kconfig b/drivers/net/wireless/ath/ath9k/Kconfig
index f3dc124c60c7..3c2cbc9d6295 100644
--- a/drivers/net/wireless/ath/ath9k/Kconfig
+++ b/drivers/net/wireless/ath/ath9k/Kconfig
@@ -92,13 +92,17 @@ config ATH9K_MAC_DEBUG
           This option enables collection of statistics for Rx/Tx status
           data and some other MAC related statistics
 
-config ATH9K_RATE_CONTROL
+config ATH9K_LEGACY_RATE_CONTROL
         bool "Atheros ath9k rate control"
         depends on ATH9K
-        default y
+        default n
         ---help---
           Say Y, if you want to use the ath9k specific rate control
-          module instead of minstrel_ht.
+          module instead of minstrel_ht. Be warned that there are various
+          issues with the ath9k RC and minstrel is a more robust algorithm.
+          Note that even if this option is selected, "ath9k_rate_control"
+          has to be passed to mac80211 using the module parameter,
+          ieee80211_default_rc_algo.
 
 config ATH9K_HTC
        tristate "Atheros HTC based wireless cards support"
diff --git a/drivers/net/wireless/ath/ath9k/Makefile b/drivers/net/wireless/ath/ath9k/Makefile
index 2ad8f9474ba1..75ee9e7704ce 100644
--- a/drivers/net/wireless/ath/ath9k/Makefile
+++ b/drivers/net/wireless/ath/ath9k/Makefile
@@ -8,7 +8,7 @@ ath9k-y +=	beacon.o \
                 antenna.o
 
 ath9k-$(CONFIG_ATH9K_BTCOEX_SUPPORT) += mci.o
-ath9k-$(CONFIG_ATH9K_RATE_CONTROL) += rc.o
+ath9k-$(CONFIG_ATH9K_LEGACY_RATE_CONTROL) += rc.o
 ath9k-$(CONFIG_ATH9K_PCI) += pci.o
 ath9k-$(CONFIG_ATH9K_AHB) += ahb.o
 ath9k-$(CONFIG_ATH9K_DEBUGFS) += debug.o
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
index db5ffada2217..7546b9a7dcbf 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_2p2_initvals.h
@@ -958,11 +958,11 @@ static const u32 ar9300Common_rx_gain_table_2p2[][2] = {
         {0x0000a074, 0x00000000},
         {0x0000a078, 0x00000000},
         {0x0000a07c, 0x00000000},
-        {0x0000a080, 0x1a1a1a1a},
-        {0x0000a084, 0x1a1a1a1a},
-        {0x0000a088, 0x1a1a1a1a},
-        {0x0000a08c, 0x1a1a1a1a},
-        {0x0000a090, 0x171a1a1a},
+        {0x0000a080, 0x22222229},
+        {0x0000a084, 0x1d1d1d1d},
+        {0x0000a088, 0x1d1d1d1d},
+        {0x0000a08c, 0x1d1d1d1d},
+        {0x0000a090, 0x171d1d1d},
         {0x0000a094, 0x11111717},
         {0x0000a098, 0x00030311},
         {0x0000a09c, 0x00000000},
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
index 54ba42f4108a..874f6570bd1c 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
+++ b/drivers/net/wireless/ath/ath9k/ar9003_eeprom.h
@@ -68,13 +68,16 @@
 #define AR9300_BASE_ADDR 0x3ff
 #define AR9300_BASE_ADDR_512 0x1ff
 
-#define AR9300_OTP_BASE                 (AR_SREV_9340(ah) ? 0x30000 : 0x14000)
-#define AR9300_OTP_STATUS               (AR_SREV_9340(ah) ? 0x30018 : 0x15f18)
+#define AR9300_OTP_BASE \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30000 : 0x14000)
+#define AR9300_OTP_STATUS \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x30018 : 0x15f18)
 #define AR9300_OTP_STATUS_TYPE          0x7
 #define AR9300_OTP_STATUS_VALID         0x4
 #define AR9300_OTP_STATUS_ACCESS_BUSY   0x2
 #define AR9300_OTP_STATUS_SM_BUSY       0x1
-#define AR9300_OTP_READ_DATA            (AR_SREV_9340(ah) ? 0x3001c : 0x15f1c)
+#define AR9300_OTP_READ_DATA \
+                ((AR_SREV_9340(ah) || AR_SREV_9550(ah)) ? 0x3001c : 0x15f1c)
 
 enum targetPowerHTRates {
         HT_TARGET_RATE_0_8_16,
diff --git a/drivers/net/wireless/ath/ath9k/ar9003_phy.c b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
index 2bf6548dd143..e1714d7c9eeb 100644
--- a/drivers/net/wireless/ath/ath9k/ar9003_phy.c
+++ b/drivers/net/wireless/ath/ath9k/ar9003_phy.c
@@ -334,7 +334,8 @@ static void ar9003_hw_spur_ofdm(struct ath_hw *ah,
         REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                       AR_PHY_SPUR_REG_EN_VIT_SPUR_RSSI, 1);
 
-        if (REG_READ_FIELD(ah, AR_PHY_MODE,
+        if (!AR_SREV_9340(ah) &&
+            REG_READ_FIELD(ah, AR_PHY_MODE,
                            AR_PHY_MODE_DYNAMIC) == 0x1)
                 REG_RMW_FIELD(ah, AR_PHY_SPUR_REG,
                               AR_PHY_SPUR_REG_ENABLE_NF_RSSI_SPUR_MIT, 1);
diff --git a/drivers/net/wireless/ath/ath9k/ath9k.h b/drivers/net/wireless/ath/ath9k/ath9k.h
index 366002f266f8..42b03dc39d14 100644
--- a/drivers/net/wireless/ath/ath9k/ath9k.h
+++ b/drivers/net/wireless/ath/ath9k/ath9k.h
@@ -251,10 +251,9 @@ struct ath_atx_tid {
         int tidno;
         int baw_head;   /* first un-acked tx buffer */
         int baw_tail;   /* next unused tx buffer slot */
-        int sched;
-        int paused;
-        u8 state;
-        bool stop_cb;
+        bool sched;
+        bool paused;
+        bool active;
 };
 
 struct ath_node {
@@ -275,10 +274,6 @@ struct ath_node {
 #endif
 };
 
-#define AGGR_CLEANUP         BIT(1)
-#define AGGR_ADDBA_COMPLETE  BIT(2)
-#define AGGR_ADDBA_PROGRESS  BIT(3)
-
 struct ath_tx_control {
         struct ath_txq *txq;
         struct ath_node *an;
@@ -352,8 +347,7 @@ void ath_tx_tasklet(struct ath_softc *sc);
 void ath_tx_edma_tasklet(struct ath_softc *sc);
 int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
                       u16 tid, u16 *ssn);
-bool ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid,
-                      bool flush);
+void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid);
 
 void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an);
diff --git a/drivers/net/wireless/ath/ath9k/hw.c b/drivers/net/wireless/ath/ath9k/hw.c
index 7f25da8444fe..15dfefcf2d0f 100644
--- a/drivers/net/wireless/ath/ath9k/hw.c
+++ b/drivers/net/wireless/ath/ath9k/hw.c
@@ -1172,6 +1172,7 @@ u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
 static inline void ath9k_hw_set_dma(struct ath_hw *ah)
 {
         struct ath_common *common = ath9k_hw_common(ah);
+        int txbuf_size;
 
         ENABLE_REGWRITE_BUFFER(ah);
 
@@ -1225,13 +1226,17 @@ static inline void ath9k_hw_set_dma(struct ath_hw *ah)
                  * So set the usable tx buf size also to half to
                  * avoid data/delimiter underruns
                  */
-                REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
-                          AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE);
-        } else if (!AR_SREV_9271(ah)) {
-                REG_WRITE(ah, AR_PCU_TXBUF_CTRL,
-                          AR_PCU_TXBUF_CTRL_USABLE_SIZE);
+                txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
+        } else if (AR_SREV_9340_13_OR_LATER(ah)) {
+                /* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
+                txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
+        } else {
+                txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
         }
 
+        if (!AR_SREV_9271(ah))
+                REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
+
         REGWRITE_BUFFER_FLUSH(ah);
 
         if (AR_SREV_9300_20_OR_LATER(ah))
@@ -1306,9 +1311,13 @@ static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
                         AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
         } else {
                 tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE);
-                if (tmpReg &
-                    (AR_INTR_SYNC_LOCAL_TIMEOUT |
-                     AR_INTR_SYNC_RADM_CPL_TIMEOUT)) {
+                if (AR_SREV_9340(ah))
+                        tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
+                else
+                        tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
+                                  AR_INTR_SYNC_RADM_CPL_TIMEOUT;
+
+                if (tmpReg) {
                         u32 val;
                         REG_WRITE(ah, AR_INTR_SYNC_ENABLE, 0);
 
diff --git a/drivers/net/wireless/ath/ath9k/init.c b/drivers/net/wireless/ath/ath9k/init.c
index aba415103f94..2ba494567777 100644
--- a/drivers/net/wireless/ath/ath9k/init.c
+++ b/drivers/net/wireless/ath/ath9k/init.c
@@ -787,8 +787,7 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         hw->wiphy->iface_combinations = if_comb;
         hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
 
-        if (AR_SREV_5416(sc->sc_ah))
-                hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
+        hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 
         hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
         hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
@@ -830,10 +829,6 @@ void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
         sc->ant_rx = hw->wiphy->available_antennas_rx;
         sc->ant_tx = hw->wiphy->available_antennas_tx;
 
-#ifdef CONFIG_ATH9K_RATE_CONTROL
-        hw->rate_control_algorithm = "ath9k_rate_control";
-#endif
-
         if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
                 hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
                         &sc->sbands[IEEE80211_BAND_2GHZ];
diff --git a/drivers/net/wireless/ath/ath9k/mac.c b/drivers/net/wireless/ath/ath9k/mac.c
index 498fee04afa0..566109a40fb3 100644
--- a/drivers/net/wireless/ath/ath9k/mac.c
+++ b/drivers/net/wireless/ath/ath9k/mac.c
@@ -410,7 +410,7 @@ bool ath9k_hw_resettxqueue(struct ath_hw *ah, u32 q)
 
         REG_WRITE(ah, AR_QMISC(q), AR_Q_MISC_DCU_EARLY_TERM_REQ);
 
-        if (AR_SREV_9340(ah))
+        if (AR_SREV_9340(ah) && !AR_SREV_9340_13_OR_LATER(ah))
                 REG_WRITE(ah, AR_DMISC(q),
                           AR_D_MISC_CW_BKOFF_EN | AR_D_MISC_FRAG_WAIT_EN | 0x1);
         else
diff --git a/drivers/net/wireless/ath/ath9k/main.c b/drivers/net/wireless/ath/ath9k/main.c
index 2382d1262e7f..5092ecae7706 100644
--- a/drivers/net/wireless/ath/ath9k/main.c
+++ b/drivers/net/wireless/ath/ath9k/main.c
@@ -1709,7 +1709,8 @@ static int ath9k_ampdu_action(struct ieee80211_hw *hw,
                 flush = true;
         case IEEE80211_AMPDU_TX_STOP_CONT:
                 ath9k_ps_wakeup(sc);
-                if (ath_tx_aggr_stop(sc, sta, tid, flush))
+                ath_tx_aggr_stop(sc, sta, tid);
+                if (!flush)
                         ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
                 ath9k_ps_restore(sc);
                 break;
diff --git a/drivers/net/wireless/ath/ath9k/rc.c b/drivers/net/wireless/ath/ath9k/rc.c
index aa4d368d8d3d..7eb1f4b458e4 100644
--- a/drivers/net/wireless/ath/ath9k/rc.c
+++ b/drivers/net/wireless/ath/ath9k/rc.c
@@ -1227,10 +1227,7 @@ static bool ath_tx_aggr_check(struct ath_softc *sc, struct ieee80211_sta *sta,
                 return false;
 
         txtid = ATH_AN_2_TID(an, tidno);
-
-        if (!(txtid->state & (AGGR_ADDBA_COMPLETE | AGGR_ADDBA_PROGRESS)))
-                        return true;
-        return false;
+        return !txtid->active;
 }
 
 
diff --git a/drivers/net/wireless/ath/ath9k/rc.h b/drivers/net/wireless/ath/ath9k/rc.h
index 267dbfcfaa96..b9a87383cb43 100644
--- a/drivers/net/wireless/ath/ath9k/rc.h
+++ b/drivers/net/wireless/ath/ath9k/rc.h
@@ -231,7 +231,7 @@ static inline void ath_debug_stat_retries(struct ath_rate_priv *rc, int rix,
 }
 #endif
 
-#ifdef CONFIG_ATH9K_RATE_CONTROL
+#ifdef CONFIG_ATH9K_LEGACY_RATE_CONTROL
 int ath_rate_control_register(void);
 void ath_rate_control_unregister(void);
 #else
diff --git a/drivers/net/wireless/ath/ath9k/reg.h b/drivers/net/wireless/ath/ath9k/reg.h
index 5c4ab5026dca..f7c90cc58d56 100644
--- a/drivers/net/wireless/ath/ath9k/reg.h
+++ b/drivers/net/wireless/ath/ath9k/reg.h
@@ -798,6 +798,10 @@
 #define AR_SREV_REVISION_9485_10        0
 #define AR_SREV_REVISION_9485_11        1
 #define AR_SREV_VERSION_9340            0x300
+#define AR_SREV_REVISION_9340_10        0
+#define AR_SREV_REVISION_9340_11        1
+#define AR_SREV_REVISION_9340_12        2
+#define AR_SREV_REVISION_9340_13        3
 #define AR_SREV_VERSION_9580            0x1C0
 #define AR_SREV_REVISION_9580_10        4 /* AR9580 1.0 */
 #define AR_SREV_VERSION_9462            0x280
@@ -897,6 +901,10 @@
 #define AR_SREV_9340(_ah) \
         (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9340))
 
+#define AR_SREV_9340_13_OR_LATER(_ah) \
+        (AR_SREV_9340((_ah)) && \
+         ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9340_13))
+
 #define AR_SREV_9285E_20(_ah) \
     (AR_SREV_9285_12_OR_LATER(_ah) && \
      ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1))
@@ -1007,6 +1015,8 @@ enum {
                                 AR_INTR_SYNC_LOCAL_TIMEOUT |
                                 AR_INTR_SYNC_MAC_SLEEP_ACCESS),
 
+        AR9340_INTR_SYNC_LOCAL_TIMEOUT = 0x00000010,
+
         AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF,
 
 };
@@ -1881,6 +1891,7 @@ enum {
 #define AR_PCU_TXBUF_CTRL_SIZE_MASK     0x7FF
 #define AR_PCU_TXBUF_CTRL_USABLE_SIZE   0x700
 #define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE   0x380
+#define AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE   0x500
 
 #define AR_PCU_MISC_MODE2               0x8344
 #define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE           0x00000002
diff --git a/drivers/net/wireless/ath/ath9k/xmit.c b/drivers/net/wireless/ath/ath9k/xmit.c
index 14bb3354ea64..1c9b1bac8b0d 100644
--- a/drivers/net/wireless/ath/ath9k/xmit.c
+++ b/drivers/net/wireless/ath/ath9k/xmit.c
@@ -125,24 +125,6 @@ static void ath_tx_queue_tid(struct ath_txq *txq, struct ath_atx_tid *tid)
         list_add_tail(&ac->list, &txq->axq_acq);
 }
 
-static void ath_tx_resume_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
-{
-        struct ath_txq *txq = tid->ac->txq;
-
-        WARN_ON(!tid->paused);
-
-        ath_txq_lock(sc, txq);
-        tid->paused = false;
-
-        if (skb_queue_empty(&tid->buf_q))
-                goto unlock;
-
-        ath_tx_queue_tid(txq, tid);
-        ath_txq_schedule(sc, txq);
-unlock:
-        ath_txq_unlock_complete(sc, txq);
-}
-
 static struct ath_frame_info *get_frame_info(struct sk_buff *skb)
 {
         struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
@@ -164,20 +146,7 @@ static void ath_set_rates(struct ieee80211_vif *vif, struct ieee80211_sta *sta,
                                ARRAY_SIZE(bf->rates));
 }
 
-static void ath_tx_clear_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
-{
-        tid->state &= ~AGGR_ADDBA_COMPLETE;
-        tid->state &= ~AGGR_CLEANUP;
-        if (!tid->stop_cb)
-                return;
-
-        ieee80211_start_tx_ba_cb_irqsafe(tid->an->vif, tid->an->sta->addr,
-                                         tid->tidno);
-        tid->stop_cb = false;
-}
-
-static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
-                             bool flush_packets)
+static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid)
 {
         struct ath_txq *txq = tid->ac->txq;
         struct sk_buff *skb;
@@ -194,15 +163,16 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
         while ((skb = __skb_dequeue(&tid->buf_q))) {
                 fi = get_frame_info(skb);
                 bf = fi->bf;
-                if (!bf && !flush_packets)
-                        bf = ath_tx_setup_buffer(sc, txq, tid, skb);
 
                 if (!bf) {
-                        ieee80211_free_txskb(sc->hw, skb);
-                        continue;
+                        bf = ath_tx_setup_buffer(sc, txq, tid, skb);
+                        if (!bf) {
+                                ieee80211_free_txskb(sc->hw, skb);
+                                continue;
+                        }
                 }
 
-                if (fi->retries || flush_packets) {
+                if (fi->retries) {
                         list_add_tail(&bf->list, &bf_head);
                         ath_tx_update_baw(sc, tid, bf->bf_state.seqno);
                         ath_tx_complete_buf(sc, bf, txq, &bf_head, &ts, 0);
@@ -213,10 +183,7 @@ static void ath_tx_flush_tid(struct ath_softc *sc, struct ath_atx_tid *tid,
                 }
         }
 
-        if (tid->baw_head == tid->baw_tail)
-                ath_tx_clear_tid(sc, tid);
-
-        if (sendbar && !flush_packets) {
+        if (sendbar) {
                 ath_txq_unlock(sc, txq);
                 ath_send_bar(tid, tid->seq_start);
                 ath_txq_lock(sc, txq);
@@ -499,19 +466,19 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 tx_info = IEEE80211_SKB_CB(skb);
                 fi = get_frame_info(skb);
 
-                if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
+                if (!BAW_WITHIN(tid->seq_start, tid->baw_size, seqno)) {
+                        /*
+                         * Outside of the current BlockAck window,
+                         * maybe part of a previous session
+                         */
+                        txfail = 1;
+                } else if (ATH_BA_ISSET(ba, ATH_BA_INDEX(seq_st, seqno))) {
                         /* transmit completion, subframe is
                          * acked by block ack */
                         acked_cnt++;
                 } else if (!isaggr && txok) {
                         /* transmit completion */
                         acked_cnt++;
-                } else if (tid->state & AGGR_CLEANUP) {
-                        /*
-                         * cleanup in progress, just fail
-                         * the un-acked sub-frames
-                         */
-                        txfail = 1;
                 } else if (flush) {
                         txpending = 1;
                 } else if (fi->retries < ATH_MAX_SW_RETRIES) {
@@ -535,7 +502,7 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 if (bf_next != NULL || !bf_last->bf_stale)
                         list_move_tail(&bf->list, &bf_head);
 
-                if (!txpending || (tid->state & AGGR_CLEANUP)) {
+                if (!txpending) {
                         /*
                          * complete the acked-ones/xretried ones; update
                          * block-ack window
@@ -609,9 +576,6 @@ static void ath_tx_complete_aggr(struct ath_softc *sc, struct ath_txq *txq,
                 ath_txq_lock(sc, txq);
         }
 
-        if (tid->state & AGGR_CLEANUP)
-                ath_tx_flush_tid(sc, tid, false);
-
         rcu_read_unlock();
 
         if (needreset)
@@ -1244,9 +1208,6 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
         an = (struct ath_node *)sta->drv_priv;
         txtid = ATH_AN_2_TID(an, tid);
 
-        if (txtid->state & (AGGR_CLEANUP | AGGR_ADDBA_COMPLETE))
-                return -EAGAIN;
-
         /* update ampdu factor/density, they may have changed. This may happen
          * in HT IBSS when a beacon with HT-info is received after the station
          * has already been added.
@@ -1258,7 +1219,7 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
                 an->mpdudensity = density;
         }
 
-        txtid->state |= AGGR_ADDBA_PROGRESS;
+        txtid->active = true;
         txtid->paused = true;
         *ssn = txtid->seq_start = txtid->seq_next;
         txtid->bar_index = -1;
@@ -1269,45 +1230,17 @@ int ath_tx_aggr_start(struct ath_softc *sc, struct ieee80211_sta *sta,
         return 0;
 }
 
-bool ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid,
-                      bool flush)
+void ath_tx_aggr_stop(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
 {
         struct ath_node *an = (struct ath_node *)sta->drv_priv;
         struct ath_atx_tid *txtid = ATH_AN_2_TID(an, tid);
         struct ath_txq *txq = txtid->ac->txq;
-        bool ret = !flush;
-
-        if (flush)
-                txtid->stop_cb = false;
-
-        if (txtid->state & AGGR_CLEANUP)
-                return false;
-
-        if (!(txtid->state & AGGR_ADDBA_COMPLETE)) {
-                txtid->state &= ~AGGR_ADDBA_PROGRESS;
-                return ret;
-        }
 
         ath_txq_lock(sc, txq);
+        txtid->active = false;
         txtid->paused = true;
-
-        /*
-         * If frames are still being transmitted for this TID, they will be
-         * cleaned up during tx completion. To prevent race conditions, this
-         * TID can only be reused after all in-progress subframes have been
-         * completed.
-         */
-        if (txtid->baw_head != txtid->baw_tail) {
-                txtid->state |= AGGR_CLEANUP;
-                ret = false;
-                txtid->stop_cb = !flush;
-        } else {
-                txtid->state &= ~AGGR_ADDBA_COMPLETE;
-        }
-
-        ath_tx_flush_tid(sc, txtid, flush);
+        ath_tx_flush_tid(sc, txtid);
         ath_txq_unlock_complete(sc, txq);
-        return ret;
 }
 
 void ath_tx_aggr_sleep(struct ieee80211_sta *sta, struct ath_softc *sc,
@@ -1371,18 +1304,28 @@ void ath_tx_aggr_wakeup(struct ath_softc *sc, struct ath_node *an)
         }
 }
 
-void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta, u16 tid)
+void ath_tx_aggr_resume(struct ath_softc *sc, struct ieee80211_sta *sta,
+                        u16 tidno)
 {
-        struct ath_atx_tid *txtid;
+        struct ath_atx_tid *tid;
         struct ath_node *an;
+        struct ath_txq *txq;
 
         an = (struct ath_node *)sta->drv_priv;
+        tid = ATH_AN_2_TID(an, tidno);
+        txq = tid->ac->txq;
 
-        txtid = ATH_AN_2_TID(an, tid);
-        txtid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
-        txtid->state |= AGGR_ADDBA_COMPLETE;
-        txtid->state &= ~AGGR_ADDBA_PROGRESS;
-        ath_tx_resume_tid(sc, txtid);
+        ath_txq_lock(sc, txq);
+
+        tid->baw_size = IEEE80211_MIN_AMPDU_BUF << sta->ht_cap.ampdu_factor;
+        tid->paused = false;
+
+        if (!skb_queue_empty(&tid->buf_q)) {
+                ath_tx_queue_tid(txq, tid);
+                ath_txq_schedule(sc, txq);
+        }
+
+        ath_txq_unlock_complete(sc, txq);
 }
 
 /********************/
@@ -2431,13 +2374,10 @@ void ath_tx_node_init(struct ath_softc *sc, struct ath_node *an)
                 tid->baw_head  = tid->baw_tail = 0;
                 tid->sched     = false;
                 tid->paused    = false;
-                tid->state &= ~AGGR_CLEANUP;
+                tid->active        = false;
                 __skb_queue_head_init(&tid->buf_q);
                 acno = TID_TO_WME_AC(tidno);
                 tid->ac = &an->ac[acno];
-                tid->state &= ~AGGR_ADDBA_COMPLETE;
-                tid->state &= ~AGGR_ADDBA_PROGRESS;
-                tid->stop_cb = false;
         }
 
         for (acno = 0, ac = &an->ac[acno];
@@ -2474,7 +2414,7 @@ void ath_tx_node_cleanup(struct ath_softc *sc, struct ath_node *an)
                 }
 
                 ath_tid_drain(sc, txq, tid);
-                ath_tx_clear_tid(sc, tid);
+                tid->active = false;
 
                 ath_txq_unlock(sc, txq);
         }
diff --git a/drivers/net/wireless/atmel.c b/drivers/net/wireless/atmel.c
index 830bb1d1f957..b827d51c30a3 100644
--- a/drivers/net/wireless/atmel.c
+++ b/drivers/net/wireless/atmel.c
@@ -1624,7 +1624,7 @@ struct net_device *init_atmel_card(unsigned short irq, unsigned long port,
 
         netif_carrier_off(dev);
 
-        if (!proc_create_data("driver/atmel", 0, NULL, &atmel_proc_fops, priv));
+        if (!proc_create_data("driver/atmel", 0, NULL, &atmel_proc_fops, priv))
                 printk(KERN_WARNING "atmel: unable to create /proc entry.\n");
 
         printk(KERN_INFO "%s: Atmel at76c50x. Version %d.%d. MAC %pM\n",
diff --git a/drivers/net/wireless/b43/main.c b/drivers/net/wireless/b43/main.c
index 6dd07e2ec595..a95b77ab360e 100644
--- a/drivers/net/wireless/b43/main.c
+++ b/drivers/net/wireless/b43/main.c
@@ -2458,7 +2458,7 @@ static void b43_request_firmware(struct work_struct *work)
         for (i = 0; i < B43_NR_FWTYPES; i++) {
                 errmsg = ctx->errors[i];
                 if (strlen(errmsg))
-                        b43err(dev->wl, errmsg);
+                        b43err(dev->wl, "%s", errmsg);
         }
         b43_print_fw_helptext(dev->wl, 1);
         goto out;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
index be0787cab24f..9431af2465f3 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_common.c
@@ -27,7 +27,6 @@
 #include "tracepoint.h"
 
 #define PKTFILTER_BUF_SIZE              128
-#define BRCMF_ARPOL_MODE                0xb     /* agent|snoop|peer_autoreply */
 #define BRCMF_DEFAULT_BCN_TIMEOUT       3
 #define BRCMF_DEFAULT_SCAN_CHANNEL_TIME 40
 #define BRCMF_DEFAULT_SCAN_UNASSOC_TIME 40
@@ -338,23 +337,6 @@ int brcmf_c_preinit_dcmds(struct brcmf_if *ifp)
                 goto done;
         }
 
-        /* Try to set and enable ARP offload feature, this may fail */
-        err = brcmf_fil_iovar_int_set(ifp, "arp_ol", BRCMF_ARPOL_MODE);
-        if (err) {
-                brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, err = %d\n",
-                          BRCMF_ARPOL_MODE, err);
-                err = 0;
-        } else {
-                err = brcmf_fil_iovar_int_set(ifp, "arpoe", 1);
-                if (err) {
-                        brcmf_dbg(TRACE, "failed to enable ARP offload err = %d\n",
-                                  err);
-                        err = 0;
-                } else
-                        brcmf_dbg(TRACE, "successfully enabled ARP offload to 0x%x\n",
-                                  BRCMF_ARPOL_MODE);
-        }
-
         /* Setup packet filter */
         brcmf_c_pktfilter_offload_set(ifp, BRCMF_DEFAULT_PACKET_FILTER);
         brcmf_c_pktfilter_offload_enable(ifp, BRCMF_DEFAULT_PACKET_FILTER,
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
index 59c25463e428..b98f2235978e 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/dhd_linux.c
@@ -653,10 +653,13 @@ int brcmf_net_attach(struct brcmf_if *ifp, bool rtnl_locked)
 
         brcmf_dbg(INFO, "%s: Broadcom Dongle Host Driver\n", ndev->name);
 
+        ndev->destructor = free_netdev;
         return 0;
 
 fail:
+        drvr->iflist[ifp->bssidx] = NULL;
         ndev->netdev_ops = NULL;
+        free_netdev(ndev);
         return -EBADE;
 }
 
@@ -720,6 +723,9 @@ static int brcmf_net_p2p_attach(struct brcmf_if *ifp)
         return 0;
 
 fail:
+        ifp->drvr->iflist[ifp->bssidx] = NULL;
+        ndev->netdev_ops = NULL;
+        free_netdev(ndev);
         return -EBADE;
 }
 
@@ -788,6 +794,7 @@ void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
         struct brcmf_if *ifp;
 
         ifp = drvr->iflist[bssidx];
+        drvr->iflist[bssidx] = NULL;
         if (!ifp) {
                 brcmf_err("Null interface, idx=%d\n", bssidx);
                 return;
@@ -808,15 +815,13 @@ void brcmf_del_if(struct brcmf_pub *drvr, s32 bssidx)
                         cancel_work_sync(&ifp->setmacaddr_work);
                         cancel_work_sync(&ifp->multicast_work);
                 }
-
+                /* unregister will take care of freeing it */
                 unregister_netdev(ifp->ndev);
                 if (bssidx == 0)
                         brcmf_cfg80211_detach(drvr->config);
-                free_netdev(ifp->ndev);
         } else {
                 kfree(ifp);
         }
-        drvr->iflist[bssidx] = NULL;
 }
 
 int brcmf_attach(uint bus_hdrlen, struct device *dev)
@@ -925,8 +930,6 @@ fail:
                         brcmf_fws_del_interface(ifp);
                         brcmf_fws_deinit(drvr);
                 }
-                free_netdev(ifp->ndev);
-                drvr->iflist[0] = NULL;
                 if (p2p_ifp) {
                         free_netdev(p2p_ifp->ndev);
                         drvr->iflist[1] = NULL;
@@ -934,7 +937,8 @@ fail:
                 return ret;
         }
         if ((brcmf_p2p_enable) && (p2p_ifp))
-                brcmf_net_p2p_attach(p2p_ifp);
+                if (brcmf_net_p2p_attach(p2p_ifp) < 0)
+                        brcmf_p2p_enable = 0;
 
         return 0;
 }
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/fweh.c b/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
index 5a64280e6485..83ee53a7c76e 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/fweh.c
@@ -202,7 +202,8 @@ static void brcmf_fweh_handle_if_event(struct brcmf_pub *drvr,
                         return;
                 brcmf_fws_add_interface(ifp);
                 if (!drvr->fweh.evt_handler[BRCMF_E_IF])
-                        err = brcmf_net_attach(ifp, false);
+                        if (brcmf_net_attach(ifp, false) < 0)
+                                return;
         }
 
         if (ifevent->action == BRCMF_E_IF_CHANGE)
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h b/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
index 0f2c83bc95dc..665ef69e974b 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/fwil_types.h
@@ -23,6 +23,12 @@
 
 #define BRCMF_FIL_ACTION_FRAME_SIZE     1800
 
+/* ARP Offload feature flags for arp_ol iovar */
+#define BRCMF_ARP_OL_AGENT              0x00000001
+#define BRCMF_ARP_OL_SNOOP              0x00000002
+#define BRCMF_ARP_OL_HOST_AUTO_REPLY    0x00000004
+#define BRCMF_ARP_OL_PEER_AUTO_REPLY    0x00000008
+
 
 enum brcmf_fil_p2p_if_types {
         BRCMF_FIL_P2P_IF_CLIENT,
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
index e7a1a4770996..79555f006d53 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/p2p.c
@@ -47,6 +47,7 @@
 #define IS_P2P_SOCIAL_CHANNEL(channel) ((channel == SOCIAL_CHAN_1) || \
                                          (channel == SOCIAL_CHAN_2) || \
                                          (channel == SOCIAL_CHAN_3))
+#define BRCMF_P2P_TEMP_CHAN     SOCIAL_CHAN_3
 #define SOCIAL_CHAN_CNT         3
 #define AF_PEER_SEARCH_CNT      2
 
@@ -1954,21 +1955,21 @@ s32 brcmf_p2p_attach(struct brcmf_cfg80211_info *cfg)
                 err = brcmf_fil_iovar_int_set(pri_ifp, "p2p_disc", 1);
                 if (err < 0) {
                         brcmf_err("set p2p_disc error\n");
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
                 /* obtain bsscfg index for P2P discovery */
                 err = brcmf_fil_iovar_int_get(pri_ifp, "p2p_dev", &bssidx);
                 if (err < 0) {
                         brcmf_err("retrieving discover bsscfg index failed\n");
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
                 /* Verify that firmware uses same bssidx as driver !! */
                 if (p2p_ifp->bssidx != bssidx) {
                         brcmf_err("Incorrect bssidx=%d, compared to p2p_ifp->bssidx=%d\n",
                                   bssidx, p2p_ifp->bssidx);
-                        brcmf_free_vif(p2p_vif);
+                        brcmf_free_vif(cfg, p2p_vif);
                         goto exit;
                 }
 
@@ -1996,7 +1997,7 @@ void brcmf_p2p_detach(struct brcmf_p2p_info *p2p)
                 brcmf_p2p_cancel_remain_on_channel(vif->ifp);
                 brcmf_p2p_deinit_discovery(p2p);
                 /* remove discovery interface */
-                brcmf_free_vif(vif);
+                brcmf_free_vif(p2p->cfg, vif);
                 p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
         }
         /* just set it all to zero */
@@ -2013,17 +2014,30 @@ static void brcmf_p2p_get_current_chanspec(struct brcmf_p2p_info *p2p,
                                            u16 *chanspec)
 {
         struct brcmf_if *ifp;
-        struct brcmf_fil_chan_info_le ci;
+        u8 mac_addr[ETH_ALEN];
         struct brcmu_chan ch;
-        s32 err;
+        struct brcmf_bss_info_le *bi;
+        u8 *buf;
 
         ifp = p2p->bss_idx[P2PAPI_BSSCFG_PRIMARY].vif->ifp;
 
-        ch.chnum = 11;
-
-        err = brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_CHANNEL, &ci, sizeof(ci));
-        if (!err)
-                ch.chnum = le32_to_cpu(ci.hw_channel);
+        if (brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSSID, mac_addr,
+                                   ETH_ALEN) == 0) {
+                buf = kzalloc(WL_BSS_INFO_MAX, GFP_KERNEL);
+                if (buf != NULL) {
+                        *(__le32 *)buf = cpu_to_le32(WL_BSS_INFO_MAX);
+                        if (brcmf_fil_cmd_data_get(ifp, BRCMF_C_GET_BSS_INFO,
+                                                   buf, WL_BSS_INFO_MAX) == 0) {
+                                bi = (struct brcmf_bss_info_le *)(buf + 4);
+                                *chanspec = le16_to_cpu(bi->chanspec);
+                                kfree(buf);
+                                return;
+                        }
+                        kfree(buf);
+                }
+        }
+        /* Use default channel for P2P */
+        ch.chnum = BRCMF_P2P_TEMP_CHAN;
         ch.bw = BRCMU_CHAN_BW_20;
         p2p->cfg->d11inf.encchspec(&ch);
         *chanspec = ch.chspec;
@@ -2208,7 +2222,7 @@ static struct wireless_dev *brcmf_p2p_create_p2pdev(struct brcmf_p2p_info *p2p,
         return &p2p_vif->wdev;
 
 fail:
-        brcmf_free_vif(p2p_vif);
+        brcmf_free_vif(p2p->cfg, p2p_vif);
         return ERR_PTR(err);
 }
 
@@ -2217,13 +2231,31 @@ fail:
  *
  * @vif: virtual interface object to delete.
  */
-static void brcmf_p2p_delete_p2pdev(struct brcmf_cfg80211_vif *vif)
+static void brcmf_p2p_delete_p2pdev(struct brcmf_cfg80211_info *cfg,
+                                    struct brcmf_cfg80211_vif *vif)
 {
-        struct brcmf_p2p_info *p2p = &vif->ifp->drvr->config->p2p;
-
         cfg80211_unregister_wdev(&vif->wdev);
-        p2p->bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
-        brcmf_free_vif(vif);
+        cfg->p2p.bss_idx[P2PAPI_BSSCFG_DEVICE].vif = NULL;
+        brcmf_free_vif(cfg, vif);
+}
+
+/**
+ * brcmf_p2p_free_p2p_if() - free up net device related data.
+ *
+ * @ndev: net device that needs to be freed.
+ */
+static void brcmf_p2p_free_p2p_if(struct net_device *ndev)
+{
+        struct brcmf_cfg80211_info *cfg;
+        struct brcmf_cfg80211_vif *vif;
+        struct brcmf_if *ifp;
+
+        ifp = netdev_priv(ndev);
+        cfg = ifp->drvr->config;
+        vif = ifp->vif;
+
+        brcmf_free_vif(cfg, vif);
+        free_netdev(ifp->ndev);
 }
 
 /**
@@ -2303,6 +2335,9 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,
                 brcmf_err("Registering netdevice failed\n");
                 goto fail;
         }
+        /* override destructor */
+        ifp->ndev->destructor = brcmf_p2p_free_p2p_if;
+
         cfg->p2p.bss_idx[P2PAPI_BSSCFG_CONNECTION].vif = vif;
         /* Disable firmware roaming for P2P interface  */
         brcmf_fil_iovar_int_set(ifp, "roam_off", 1);
@@ -2314,7 +2349,7 @@ struct wireless_dev *brcmf_p2p_add_vif(struct wiphy *wiphy, const char *name,
         return &ifp->vif->wdev;
 
 fail:
-        brcmf_free_vif(vif);
+        brcmf_free_vif(cfg, vif);
         return ERR_PTR(err);
 }
 
@@ -2350,7 +2385,7 @@ int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
                 break;
 
         case NL80211_IFTYPE_P2P_DEVICE:
-                brcmf_p2p_delete_p2pdev(vif);
+                brcmf_p2p_delete_p2pdev(cfg, vif);
                 return 0;
         default:
                 return -ENOTSUPP;
@@ -2378,7 +2413,6 @@ int brcmf_p2p_del_vif(struct wiphy *wiphy, struct wireless_dev *wdev)
                         err = 0;
         }
         brcmf_cfg80211_arm_vif_event(cfg, NULL);
-        brcmf_free_vif(vif);
         p2p->bss_idx[P2PAPI_BSSCFG_CONNECTION].vif = NULL;
 
         return err;
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
index 761f501959a9..301e572e8923 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.c
@@ -459,6 +459,38 @@ send_key_to_dongle(struct net_device *ndev, struct brcmf_wsec_key *key)
         return err;
 }
 
+static s32
+brcmf_configure_arp_offload(struct brcmf_if *ifp, bool enable)
+{
+        s32 err;
+        u32 mode;
+
+        if (enable)
+                mode = BRCMF_ARP_OL_AGENT | BRCMF_ARP_OL_PEER_AUTO_REPLY;
+        else
+                mode = 0;
+
+        /* Try to set and enable ARP offload feature, this may fail, then it  */
+        /* is simply not supported and err 0 will be returned                 */
+        err = brcmf_fil_iovar_int_set(ifp, "arp_ol", mode);
+        if (err) {
+                brcmf_dbg(TRACE, "failed to set ARP offload mode to 0x%x, err = %d\n",
+                          mode, err);
+                err = 0;
+        } else {
+                err = brcmf_fil_iovar_int_set(ifp, "arpoe", enable);
+                if (err) {
+                        brcmf_dbg(TRACE, "failed to configure (%d) ARP offload err = %d\n",
+                                  enable, err);
+                        err = 0;
+                } else
+                        brcmf_dbg(TRACE, "successfully configured (%d) ARP offload to 0x%x\n",
+                                  enable, mode);
+        }
+
+        return err;
+}
+
 static struct wireless_dev *brcmf_cfg80211_add_iface(struct wiphy *wiphy,
                                                      const char *name,
                                                      enum nl80211_iftype type,
@@ -2216,6 +2248,11 @@ brcmf_cfg80211_set_power_mgmt(struct wiphy *wiphy, struct net_device *ndev,
         }
 
         pm = enabled ? PM_FAST : PM_OFF;
+        /* Do not enable the power save after assoc if it is a p2p interface */
+        if (ifp->vif->wdev.iftype == NL80211_IFTYPE_P2P_CLIENT) {
+                brcmf_dbg(INFO, "Do not enable power save for P2P clients\n");
+                pm = PM_OFF;
+        }
         brcmf_dbg(INFO, "power save %s\n", (pm ? "enabled" : "disabled"));
 
         err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_PM, pm);
@@ -3640,10 +3677,28 @@ brcmf_config_ap_mgmt_ie(struct brcmf_cfg80211_vif *vif,
 }
 
 static s32
+brcmf_cfg80211_set_channel(struct brcmf_cfg80211_info *cfg,
+                           struct brcmf_if *ifp,
+                           struct ieee80211_channel *channel)
+{
+        u16 chanspec;
+        s32 err;
+
+        brcmf_dbg(TRACE, "band=%d, center_freq=%d\n", channel->band,
+                  channel->center_freq);
+
+        chanspec = channel_to_chanspec(&cfg->d11inf, channel);
+        err = brcmf_fil_iovar_int_set(ifp, "chanspec", chanspec);
+
+        return err;
+}
+
+static s32
 brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
                         struct cfg80211_ap_settings *settings)
 {
         s32 ie_offset;
+        struct brcmf_cfg80211_info *cfg = wiphy_to_cfg(wiphy);
         struct brcmf_if *ifp = netdev_priv(ndev);
         struct brcmf_tlv *ssid_ie;
         struct brcmf_ssid_le ssid_le;
@@ -3683,6 +3738,7 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
         }
 
         brcmf_set_mpc(ifp, 0);
+        brcmf_configure_arp_offload(ifp, false);
 
         /* find the RSN_IE */
         rsn_ie = brcmf_parse_tlvs((u8 *)settings->beacon.tail,
@@ -3713,6 +3769,12 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
 
         brcmf_config_ap_mgmt_ie(ifp->vif, &settings->beacon);
 
+        err = brcmf_cfg80211_set_channel(cfg, ifp, settings->chandef.chan);
+        if (err < 0) {
+                brcmf_err("Set Channel failed, %d\n", err);
+                goto exit;
+        }
+
         if (settings->beacon_interval) {
                 err = brcmf_fil_cmd_int_set(ifp, BRCMF_C_SET_BCNPRD,
                                             settings->beacon_interval);
@@ -3789,8 +3851,10 @@ brcmf_cfg80211_start_ap(struct wiphy *wiphy, struct net_device *ndev,
         set_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
 
 exit:
-        if (err)
+        if (err) {
                 brcmf_set_mpc(ifp, 1);
+                brcmf_configure_arp_offload(ifp, true);
+        }
         return err;
 }
 
@@ -3831,6 +3895,7 @@ static int brcmf_cfg80211_stop_ap(struct wiphy *wiphy, struct net_device *ndev)
                         brcmf_err("bss_enable config failed %d\n", err);
         }
         brcmf_set_mpc(ifp, 1);
+        brcmf_configure_arp_offload(ifp, true);
         set_bit(BRCMF_VIF_STATUS_AP_CREATING, &ifp->vif->sme_state);
         clear_bit(BRCMF_VIF_STATUS_AP_CREATED, &ifp->vif->sme_state);
 
@@ -4148,7 +4213,7 @@ static const struct ieee80211_iface_limit brcmf_iface_limits[] = {
 static const struct ieee80211_iface_combination brcmf_iface_combos[] = {
         {
                  .max_interfaces = BRCMF_IFACE_MAX_CNT,
-                 .num_different_channels = 1, /* no multi-channel for now */
+                 .num_different_channels = 2,
                  .n_limits = ARRAY_SIZE(brcmf_iface_limits),
                  .limits = brcmf_iface_limits
         }
@@ -4256,20 +4321,16 @@ struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
         return vif;
 }
 
-void brcmf_free_vif(struct brcmf_cfg80211_vif *vif)
+void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
+                    struct brcmf_cfg80211_vif *vif)
 {
-        struct brcmf_cfg80211_info *cfg;
-        struct wiphy *wiphy;
-
-        wiphy = vif->wdev.wiphy;
-        cfg = wiphy_priv(wiphy);
         list_del(&vif->list);
         cfg->vif_cnt--;
 
         kfree(vif);
         if (!cfg->vif_cnt) {
-                wiphy_unregister(wiphy);
-                wiphy_free(wiphy);
+                wiphy_unregister(cfg->wiphy);
+                wiphy_free(cfg->wiphy);
         }
 }
 
@@ -4646,7 +4707,6 @@ static s32 brcmf_notify_vif_event(struct brcmf_if *ifp,
                 return 0;
 
         case BRCMF_E_IF_DEL:
-                ifp->vif = NULL;
                 mutex_unlock(&event->vif_event_lock);
                 /* event may not be upon user request */
                 if (brcmf_cfg80211_vif_event_armed(cfg))
@@ -4852,8 +4912,7 @@ cfg80211_p2p_attach_out:
         wl_deinit_priv(cfg);
 
 cfg80211_attach_out:
-        brcmf_free_vif(vif);
-        wiphy_free(wiphy);
+        brcmf_free_vif(cfg, vif);
         return NULL;
 }
 
@@ -4865,7 +4924,7 @@ void brcmf_cfg80211_detach(struct brcmf_cfg80211_info *cfg)
         wl_deinit_priv(cfg);
         brcmf_btcoex_detach(cfg);
         list_for_each_entry_safe(vif, tmp, &cfg->vif_list, list) {
-                brcmf_free_vif(vif);
+                brcmf_free_vif(cfg, vif);
         }
 }
 
@@ -5229,6 +5288,8 @@ static s32 brcmf_config_dongle(struct brcmf_cfg80211_info *cfg)
         if (err)
                 goto default_conf_out;
 
+        brcmf_configure_arp_offload(ifp, true);
+
         cfg->dongle_up = true;
 default_conf_out:
 
diff --git a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
index a71cff84cdcf..d9bdaf9a72d0 100644
--- a/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
+++ b/drivers/net/wireless/brcm80211/brcmfmac/wl_cfg80211.h
@@ -487,7 +487,8 @@ enum nl80211_iftype brcmf_cfg80211_get_iftype(struct brcmf_if *ifp);
 struct brcmf_cfg80211_vif *brcmf_alloc_vif(struct brcmf_cfg80211_info *cfg,
                                            enum nl80211_iftype type,
                                            bool pm_block);
-void brcmf_free_vif(struct brcmf_cfg80211_vif *vif);
+void brcmf_free_vif(struct brcmf_cfg80211_info *cfg,
+                    struct brcmf_cfg80211_vif *vif);
 
 s32 brcmf_vif_set_mgmt_ie(struct brcmf_cfg80211_vif *vif, s32 pktflag,
                           const u8 *vndr_ie_buf, u32 vndr_ie_len);
diff --git a/drivers/net/wireless/iwlegacy/common.h b/drivers/net/wireless/iwlegacy/common.h
index f8246f2d88f9..4caaf52986a4 100644
--- a/drivers/net/wireless/iwlegacy/common.h
+++ b/drivers/net/wireless/iwlegacy/common.h
@@ -1832,16 +1832,16 @@ u32 il_usecs_to_beacons(struct il_priv *il, u32 usec, u32 beacon_interval);
 __le32 il_add_beacon_time(struct il_priv *il, u32 base, u32 addon,
                           u32 beacon_interval);
 
-#ifdef CONFIG_PM
+#ifdef CONFIG_PM_SLEEP
 extern const struct dev_pm_ops il_pm_ops;
 
 #define IL_LEGACY_PM_OPS        (&il_pm_ops)
 
-#else /* !CONFIG_PM */
+#else /* !CONFIG_PM_SLEEP */
 
 #define IL_LEGACY_PM_OPS        NULL
 
-#endif /* !CONFIG_PM */
+#endif /* !CONFIG_PM_SLEEP */
 
 /*****************************************************
 *  Error Handling Debugging
diff --git a/drivers/net/wireless/iwlwifi/dvm/sta.c b/drivers/net/wireless/iwlwifi/dvm/sta.c
index db183b44e038..c3c13ce96eb0 100644
--- a/drivers/net/wireless/iwlwifi/dvm/sta.c
+++ b/drivers/net/wireless/iwlwifi/dvm/sta.c
@@ -735,7 +735,7 @@ void iwl_restore_stations(struct iwl_priv *priv, struct iwl_rxon_context *ctx)
                                         memcpy(&lq, priv->stations[i].lq,
                                                sizeof(struct iwl_link_quality_cmd));
 
-                                if (!memcmp(&lq, &zero_lq, sizeof(lq)))
+                                if (memcmp(&lq, &zero_lq, sizeof(lq)))
                                         send_lq = true;
                         }
                         spin_unlock_bh(&priv->sta_lock);
diff --git a/drivers/net/wireless/mwifiex/debugfs.c b/drivers/net/wireless/mwifiex/debugfs.c
index 753b5682d53f..a5f9875cfd6e 100644
--- a/drivers/net/wireless/mwifiex/debugfs.c
+++ b/drivers/net/wireless/mwifiex/debugfs.c
@@ -26,10 +26,17 @@
 static struct dentry *mwifiex_dfs_dir;
 
 static char *bss_modes[] = {
-        "Unknown",
-        "Ad-hoc",
-        "Managed",
-        "Auto"
+        "UNSPECIFIED",
+        "ADHOC",
+        "STATION",
+        "AP",
+        "AP_VLAN",
+        "WDS",
+        "MONITOR",
+        "MESH_POINT",
+        "P2P_CLIENT",
+        "P2P_GO",
+        "P2P_DEVICE",
 };
 
 /* size/addr for mwifiex_debug_info */
@@ -200,7 +207,12 @@ mwifiex_info_read(struct file *file, char __user *ubuf,
         p += sprintf(p, "driver_version = %s", fmt);
         p += sprintf(p, "\nverext = %s", priv->version_str);
         p += sprintf(p, "\ninterface_name=\"%s\"\n", netdev->name);
-        p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
+
+        if (info.bss_mode >= ARRAY_SIZE(bss_modes))
+                p += sprintf(p, "bss_mode=\"%d\"\n", info.bss_mode);
+        else
+                p += sprintf(p, "bss_mode=\"%s\"\n", bss_modes[info.bss_mode]);
+
         p += sprintf(p, "media_state=\"%s\"\n",
                      (!priv->media_connected ? "Disconnected" : "Connected"));
         p += sprintf(p, "mac_address=\"%pM\"\n", netdev->dev_addr);
diff --git a/drivers/net/wireless/rtlwifi/pci.c b/drivers/net/wireless/rtlwifi/pci.c
index 999ffc12578b..c97e9d327331 100644
--- a/drivers/net/wireless/rtlwifi/pci.c
+++ b/drivers/net/wireless/rtlwifi/pci.c
@@ -764,6 +764,7 @@ static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
                                  "can't alloc skb for rx\n");
                         goto done;
                 }
+                kmemleak_not_leak(new_skb);
 
                 pci_unmap_single(rtlpci->pdev,
                                  *((dma_addr_t *) skb->cb),
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
index 3d0498e69c8c..189ba124a8c6 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.c
@@ -1973,26 +1973,35 @@ void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val)
         }
 }
 
-void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
-                                   struct ieee80211_sta *sta,
-                                   u8 rssi_level)
+static void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
+                                          struct ieee80211_sta *sta)
 {
         struct rtl_priv *rtlpriv = rtl_priv(hw);
         struct rtl_phy *rtlphy = &(rtlpriv->phy);
         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-        u32 ratr_value = (u32) mac->basic_rates;
-        u8 *mcsrate = mac->mcs;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        u32 ratr_value;
         u8 ratr_index = 0;
         u8 nmode = mac->ht_enable;
-        u8 mimo_ps = 1;
-        u16 shortgi_rate = 0;
-        u32 tmp_ratr_value = 0;
+        u8 mimo_ps = IEEE80211_SMPS_OFF;
+        u16 shortgi_rate;
+        u32 tmp_ratr_value;
         u8 curtxbw_40mhz = mac->bw_40;
-        u8 curshortgi_40mhz = mac->sgi_40;
-        u8 curshortgi_20mhz = mac->sgi_20;
+        u8 curshortgi_40mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
+                               1 : 0;
+        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
+                               1 : 0;
         enum wireless_mode wirelessmode = mac->mode;
 
-        ratr_value |= ((*(u16 *) (mcsrate))) << 12;
+        if (rtlhal->current_bandtype == BAND_ON_5G)
+                ratr_value = sta->supp_rates[1] << 4;
+        else
+                ratr_value = sta->supp_rates[0];
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                ratr_value = 0xfff;
+
+        ratr_value |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
+                        sta->ht_cap.mcs.rx_mask[0] << 12);
         switch (wirelessmode) {
         case WIRELESS_MODE_B:
                 if (ratr_value & 0x0000000c)
@@ -2006,7 +2015,7 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
         case WIRELESS_MODE_N_24G:
         case WIRELESS_MODE_N_5G:
                 nmode = 1;
-                if (mimo_ps == 0) {
+                if (mimo_ps == IEEE80211_SMPS_STATIC) {
                         ratr_value &= 0x0007F005;
                 } else {
                         u32 ratr_mask;
@@ -2016,8 +2025,7 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
                                 ratr_mask = 0x000ff005;
                         else
                                 ratr_mask = 0x0f0ff005;
-                        if (curtxbw_40mhz)
-                                ratr_mask |= 0x00000010;
+
                         ratr_value &= ratr_mask;
                 }
                 break;
@@ -2026,41 +2034,74 @@ void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
                         ratr_value &= 0x000ff0ff;
                 else
                         ratr_value &= 0x0f0ff0ff;
+
                 break;
         }
+
         ratr_value &= 0x0FFFFFFF;
-        if (nmode && ((curtxbw_40mhz && curshortgi_40mhz) ||
-            (!curtxbw_40mhz && curshortgi_20mhz))) {
+
+        if (nmode && ((curtxbw_40mhz &&
+                         curshortgi_40mhz) || (!curtxbw_40mhz &&
+                                               curshortgi_20mhz))) {
+
                 ratr_value |= 0x10000000;
                 tmp_ratr_value = (ratr_value >> 12);
+
                 for (shortgi_rate = 15; shortgi_rate > 0; shortgi_rate--) {
                         if ((1 << shortgi_rate) & tmp_ratr_value)
                                 break;
                 }
+
                 shortgi_rate = (shortgi_rate << 12) | (shortgi_rate << 8) |
-                               (shortgi_rate << 4) | (shortgi_rate);
+                    (shortgi_rate << 4) | (shortgi_rate);
         }
+
         rtl_write_dword(rtlpriv, REG_ARFR0 + ratr_index * 4, ratr_value);
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "%x\n",
+                 rtl_read_dword(rtlpriv, REG_ARFR0));
 }
 
-void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
+static void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw,
+                                         struct ieee80211_sta *sta,
+                                         u8 rssi_level)
 {
         struct rtl_priv *rtlpriv = rtl_priv(hw);
         struct rtl_phy *rtlphy = &(rtlpriv->phy);
         struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
-        u32 ratr_bitmap = (u32) mac->basic_rates;
-        u8 *p_mcsrate = mac->mcs;
-        u8 ratr_index = 0;
-        u8 curtxbw_40mhz = mac->bw_40;
-        u8 curshortgi_40mhz = mac->sgi_40;
-        u8 curshortgi_20mhz = mac->sgi_20;
-        enum wireless_mode wirelessmode = mac->mode;
+        struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
+        struct rtl_sta_info *sta_entry = NULL;
+        u32 ratr_bitmap;
+        u8 ratr_index;
+        u8 curtxbw_40mhz = (sta->bandwidth >= IEEE80211_STA_RX_BW_40) ? 1 : 0;
+        u8 curshortgi_40mhz = curtxbw_40mhz &&
+                              (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_40) ?
+                                1 : 0;
+        u8 curshortgi_20mhz = (sta->ht_cap.cap & IEEE80211_HT_CAP_SGI_20) ?
+                                1 : 0;
+        enum wireless_mode wirelessmode = 0;
         bool shortgi = false;
         u8 rate_mask[5];
         u8 macid = 0;
-        u8 mimops = 1;
-
-        ratr_bitmap |= (p_mcsrate[1] << 20) | (p_mcsrate[0] << 12);
+        u8 mimo_ps = IEEE80211_SMPS_OFF;
+
+        sta_entry = (struct rtl_sta_info *) sta->drv_priv;
+        wirelessmode = sta_entry->wireless_mode;
+        if (mac->opmode == NL80211_IFTYPE_STATION ||
+            mac->opmode == NL80211_IFTYPE_MESH_POINT)
+                curtxbw_40mhz = mac->bw_40;
+        else if (mac->opmode == NL80211_IFTYPE_AP ||
+                mac->opmode == NL80211_IFTYPE_ADHOC)
+                macid = sta->aid + 1;
+
+        if (rtlhal->current_bandtype == BAND_ON_5G)
+                ratr_bitmap = sta->supp_rates[1] << 4;
+        else
+                ratr_bitmap = sta->supp_rates[0];
+        if (mac->opmode == NL80211_IFTYPE_ADHOC)
+                ratr_bitmap = 0xfff;
+        ratr_bitmap |= (sta->ht_cap.mcs.rx_mask[1] << 20 |
+                        sta->ht_cap.mcs.rx_mask[0] << 12);
         switch (wirelessmode) {
         case WIRELESS_MODE_B:
                 ratr_index = RATR_INX_WIRELESS_B;
@@ -2071,6 +2112,7 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                 break;
         case WIRELESS_MODE_G:
                 ratr_index = RATR_INX_WIRELESS_GB;
+
                 if (rssi_level == 1)
                         ratr_bitmap &= 0x00000f00;
                 else if (rssi_level == 2)
@@ -2085,7 +2127,8 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
         case WIRELESS_MODE_N_24G:
         case WIRELESS_MODE_N_5G:
                 ratr_index = RATR_INX_WIRELESS_NGB;
-                if (mimops == 0) {
+
+                if (mimo_ps == IEEE80211_SMPS_STATIC) {
                         if (rssi_level == 1)
                                 ratr_bitmap &= 0x00070000;
                         else if (rssi_level == 2)
@@ -2128,8 +2171,10 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                                 }
                         }
                 }
+
                 if ((curtxbw_40mhz && curshortgi_40mhz) ||
                     (!curtxbw_40mhz && curshortgi_20mhz)) {
+
                         if (macid == 0)
                                 shortgi = true;
                         else if (macid == 1)
@@ -2138,21 +2183,42 @@ void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level)
                 break;
         default:
                 ratr_index = RATR_INX_WIRELESS_NGB;
+
                 if (rtlphy->rf_type == RF_1T2R)
                         ratr_bitmap &= 0x000ff0ff;
                 else
                         ratr_bitmap &= 0x0f0ff0ff;
                 break;
         }
-        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG, "ratr_bitmap :%x\n",
-                 ratr_bitmap);
-        *(u32 *)&rate_mask = ((ratr_bitmap & 0x0fffffff) |
-                                      ratr_index << 28);
+        sta_entry->ratr_index = ratr_index;
+
+        RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
+                 "ratr_bitmap :%x\n", ratr_bitmap);
+        *(u32 *)&rate_mask = (ratr_bitmap & 0x0fffffff) |
+                                     (ratr_index << 28);
         rate_mask[4] = macid | (shortgi ? 0x20 : 0x00) | 0x80;
         RT_TRACE(rtlpriv, COMP_RATR, DBG_DMESG,
                  "Rate_index:%x, ratr_val:%x, %5phC\n",
                  ratr_index, ratr_bitmap, rate_mask);
-        rtl92c_fill_h2c_cmd(hw, H2C_RA_MASK, 5, rate_mask);
+        memcpy(rtlpriv->rate_mask, rate_mask, 5);
+        /* rtl92c_fill_h2c_cmd() does USB I/O and will result in a
+         * "scheduled while atomic" if called directly */
+        schedule_work(&rtlpriv->works.fill_h2c_cmd);
+
+        if (macid != 0)
+                sta_entry->ratr_index = ratr_index;
+}
+
+void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
+                                 struct ieee80211_sta *sta,
+                                 u8 rssi_level)
+{
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        if (rtlpriv->dm.useramask)
+                rtl92cu_update_hal_rate_mask(hw, sta, rssi_level);
+        else
+                rtl92cu_update_hal_rate_table(hw, sta);
 }
 
 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw)
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
index f41a3aa4a26f..8e3ec1e25644 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/hw.h
@@ -98,10 +98,6 @@ void rtl92cu_update_interrupt_mask(struct ieee80211_hw *hw,
                                    u32 add_msr, u32 rm_msr);
 void rtl92cu_get_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
 void rtl92cu_set_hw_reg(struct ieee80211_hw *hw, u8 variable, u8 *val);
-void rtl92cu_update_hal_rate_table(struct ieee80211_hw *hw,
-                                   struct ieee80211_sta *sta,
-                                   u8 rssi_level);
-void rtl92cu_update_hal_rate_mask(struct ieee80211_hw *hw, u8 rssi_level);
 
 void rtl92cu_update_channel_access_setting(struct ieee80211_hw *hw);
 bool rtl92cu_gpio_radio_on_off_checking(struct ieee80211_hw *hw, u8 * valid);
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
index 85b6bdb163c0..da4f587199ee 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/mac.c
@@ -289,14 +289,30 @@ void rtl92c_set_key(struct ieee80211_hw *hw, u32 key_index,
                                 macaddr = cam_const_broad;
                                 entry_id = key_index;
                         } else {
+                                if (mac->opmode == NL80211_IFTYPE_AP ||
+                                    mac->opmode == NL80211_IFTYPE_MESH_POINT) {
+                                        entry_id = rtl_cam_get_free_entry(hw,
+                                                                 p_macaddr);
+                                        if (entry_id >=  TOTAL_CAM_ENTRY) {
+                                                RT_TRACE(rtlpriv, COMP_SEC,
+                                                         DBG_EMERG,
+                                                         "Can not find free hw security cam entry\n");
+                                                return;
+                                        }
+                                } else {
+                                        entry_id = CAM_PAIRWISE_KEY_POSITION;
+                                }
+
                                 key_index = PAIRWISE_KEYIDX;
-                                entry_id = CAM_PAIRWISE_KEY_POSITION;
                                 is_pairwise = true;
                         }
                 }
                 if (rtlpriv->sec.key_len[key_index] == 0) {
                         RT_TRACE(rtlpriv, COMP_SEC, DBG_DMESG,
                                  "delete one entry\n");
+                        if (mac->opmode == NL80211_IFTYPE_AP ||
+                            mac->opmode == NL80211_IFTYPE_MESH_POINT)
+                                rtl_cam_del_entry(hw, p_macaddr);
                         rtl_cam_delete_one_entry(hw, p_macaddr, entry_id);
                 } else {
                         RT_TRACE(rtlpriv, COMP_SEC, DBG_LOUD,
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
index 938b1e670b93..826f085c29dd 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.c
@@ -106,8 +106,7 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
         .update_interrupt_mask = rtl92cu_update_interrupt_mask,
         .get_hw_reg = rtl92cu_get_hw_reg,
         .set_hw_reg = rtl92cu_set_hw_reg,
-        .update_rate_tbl = rtl92cu_update_hal_rate_table,
-        .update_rate_mask = rtl92cu_update_hal_rate_mask,
+        .update_rate_tbl = rtl92cu_update_hal_rate_tbl,
         .fill_tx_desc = rtl92cu_tx_fill_desc,
         .fill_fake_txdesc = rtl92cu_fill_fake_txdesc,
         .fill_tx_cmddesc = rtl92cu_tx_fill_cmddesc,
@@ -137,6 +136,7 @@ static struct rtl_hal_ops rtl8192cu_hal_ops = {
         .phy_lc_calibrate = _rtl92cu_phy_lc_calibrate,
         .phy_set_bw_mode_callback = rtl92cu_phy_set_bw_mode_callback,
         .dm_dynamic_txpower = rtl92cu_dm_dynamic_txpower,
+        .fill_h2c_cmd = rtl92c_fill_h2c_cmd,
 };
 
 static struct rtl_mod_params rtl92cu_mod_params = {
diff --git a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
index a1310abd0d54..262e1e4c6e5b 100644
--- a/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
+++ b/drivers/net/wireless/rtlwifi/rtl8192cu/sw.h
@@ -49,5 +49,8 @@ bool rtl92cu_phy_set_rf_power_state(struct ieee80211_hw *hw,
 u32 rtl92cu_phy_query_rf_reg(struct ieee80211_hw *hw,
                             enum radio_path rfpath, u32 regaddr, u32 bitmask);
 void rtl92cu_phy_set_bw_mode_callback(struct ieee80211_hw *hw);
+void rtl92cu_update_hal_rate_tbl(struct ieee80211_hw *hw,
+                                 struct ieee80211_sta *sta,
+                                 u8 rssi_level);
 
 #endif
diff --git a/drivers/net/wireless/rtlwifi/usb.c b/drivers/net/wireless/rtlwifi/usb.c
index 76732b0cd221..a3532e077871 100644
--- a/drivers/net/wireless/rtlwifi/usb.c
+++ b/drivers/net/wireless/rtlwifi/usb.c
@@ -824,6 +824,7 @@ static void rtl_usb_stop(struct ieee80211_hw *hw)
 
         /* should after adapter start and interrupt enable. */
         set_hal_stop(rtlhal);
+        cancel_work_sync(&rtlpriv->works.fill_h2c_cmd);
         /* Enable software */
         SET_USB_STOP(rtlusb);
         rtl_usb_deinit(hw);
@@ -1026,6 +1027,16 @@ static bool rtl_usb_tx_chk_waitq_insert(struct ieee80211_hw *hw,
         return false;
 }
 
+static void rtl_fill_h2c_cmd_work_callback(struct work_struct *work)
+{
+        struct rtl_works *rtlworks =
+            container_of(work, struct rtl_works, fill_h2c_cmd);
+        struct ieee80211_hw *hw = rtlworks->hw;
+        struct rtl_priv *rtlpriv = rtl_priv(hw);
+
+        rtlpriv->cfg->ops->fill_h2c_cmd(hw, H2C_RA_MASK, 5, rtlpriv->rate_mask);
+}
+
 static struct rtl_intf_ops rtl_usb_ops = {
         .adapter_start = rtl_usb_start,
         .adapter_stop = rtl_usb_stop,
@@ -1057,6 +1068,8 @@ int rtl_usb_probe(struct usb_interface *intf,
 
         /* this spin lock must be initialized early */
         spin_lock_init(&rtlpriv->locks.usb_lock);
+        INIT_WORK(&rtlpriv->works.fill_h2c_cmd,
+                  rtl_fill_h2c_cmd_work_callback);
 
         rtlpriv->usb_data_index = 0;
         init_completion(&rtlpriv->firmware_loading_complete);
diff --git a/drivers/net/wireless/rtlwifi/wifi.h b/drivers/net/wireless/rtlwifi/wifi.h
index 44328baa6389..cc03e7c87cbe 100644
--- a/drivers/net/wireless/rtlwifi/wifi.h
+++ b/drivers/net/wireless/rtlwifi/wifi.h
@@ -1736,6 +1736,8 @@ struct rtl_hal_ops {
         void (*bt_wifi_media_status_notify) (struct ieee80211_hw *hw,
                                              bool mstate);
         void (*bt_coex_off_before_lps) (struct ieee80211_hw *hw);
+        void (*fill_h2c_cmd) (struct ieee80211_hw *hw, u8 element_id,
+                              u32 cmd_len, u8 *p_cmdbuffer);
 };
 
 struct rtl_intf_ops {
@@ -1869,6 +1871,7 @@ struct rtl_works {
         struct delayed_work fwevt_wq;
 
         struct work_struct lps_change_work;
+        struct work_struct fill_h2c_cmd;
 };
 
 struct rtl_debug {
@@ -2048,6 +2051,7 @@ struct rtl_priv {
                 };
         };
         bool enter_ps;  /* true when entering PS */
+        u8 rate_mask[5];
 
         /*This must be the last item so
            that it points to the data allocated
diff --git a/drivers/net/wireless/ti/wl12xx/scan.c b/drivers/net/wireless/ti/wl12xx/scan.c
index affdb3ec6225..4a0bbb13806b 100644
--- a/drivers/net/wireless/ti/wl12xx/scan.c
+++ b/drivers/net/wireless/ti/wl12xx/scan.c
@@ -310,7 +310,7 @@ static void wl12xx_adjust_channels(struct wl1271_cmd_sched_scan_config *cmd,
         memcpy(cmd->channels_2, cmd_channels->channels_2,
                sizeof(cmd->channels_2));
         memcpy(cmd->channels_5, cmd_channels->channels_5,
-               sizeof(cmd->channels_2));
+               sizeof(cmd->channels_5));
         /* channels_4 are not supported, so no need to copy them */
 }
 
diff --git a/drivers/net/wireless/ti/wl12xx/wl12xx.h b/drivers/net/wireless/ti/wl12xx/wl12xx.h
index 222d03540200..9e5484a73667 100644
--- a/drivers/net/wireless/ti/wl12xx/wl12xx.h
+++ b/drivers/net/wireless/ti/wl12xx/wl12xx.h
@@ -36,12 +36,12 @@
 #define WL127X_IFTYPE_SR_VER    3
 #define WL127X_MAJOR_SR_VER     10
 #define WL127X_SUBTYPE_SR_VER   WLCORE_FW_VER_IGNORE
-#define WL127X_MINOR_SR_VER     115
+#define WL127X_MINOR_SR_VER     133
 /* minimum multi-role FW version for wl127x */
 #define WL127X_IFTYPE_MR_VER    5
 #define WL127X_MAJOR_MR_VER     7
 #define WL127X_SUBTYPE_MR_VER   WLCORE_FW_VER_IGNORE
-#define WL127X_MINOR_MR_VER     115
+#define WL127X_MINOR_MR_VER     42
 
 /* FW chip version for wl128x */
 #define WL128X_CHIP_VER         7
@@ -49,7 +49,7 @@
 #define WL128X_IFTYPE_SR_VER    3
 #define WL128X_MAJOR_SR_VER     10
 #define WL128X_SUBTYPE_SR_VER   WLCORE_FW_VER_IGNORE
-#define WL128X_MINOR_SR_VER     115
+#define WL128X_MINOR_SR_VER     133
 /* minimum multi-role FW version for wl128x */
 #define WL128X_IFTYPE_MR_VER    5
 #define WL128X_MAJOR_MR_VER     7
diff --git a/drivers/net/wireless/ti/wl18xx/scan.c b/drivers/net/wireless/ti/wl18xx/scan.c
index 09d944505ac0..2b642f8c9266 100644
--- a/drivers/net/wireless/ti/wl18xx/scan.c
+++ b/drivers/net/wireless/ti/wl18xx/scan.c
@@ -34,7 +34,7 @@ static void wl18xx_adjust_channels(struct wl18xx_cmd_scan_params *cmd,
         memcpy(cmd->channels_2, cmd_channels->channels_2,
                sizeof(cmd->channels_2));
         memcpy(cmd->channels_5, cmd_channels->channels_5,
-               sizeof(cmd->channels_2));
+               sizeof(cmd->channels_5));
         /* channels_4 are not supported, so no need to copy them */
 }
 
diff --git a/drivers/net/xen-netback/netback.c b/drivers/net/xen-netback/netback.c
index 37984e6d4e99..8c20935d72c9 100644
--- a/drivers/net/xen-netback/netback.c
+++ b/drivers/net/xen-netback/netback.c
@@ -662,7 +662,7 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
 {
         struct xenvif *vif = NULL, *tmp;
         s8 status;
-        u16 irq, flags;
+        u16 flags;
         struct xen_netif_rx_response *resp;
         struct sk_buff_head rxq;
         struct sk_buff *skb;
@@ -771,13 +771,13 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
                                          sco->meta_slots_used);
 
                 RING_PUSH_RESPONSES_AND_CHECK_NOTIFY(&vif->rx, ret);
-                irq = vif->irq;
-                if (ret && list_empty(&vif->notify_list))
-                        list_add_tail(&vif->notify_list, &notify);
 
                 xenvif_notify_tx_completion(vif);
 
-                xenvif_put(vif);
+                if (ret && list_empty(&vif->notify_list))
+                        list_add_tail(&vif->notify_list, &notify);
+                else
+                        xenvif_put(vif);
                 npo.meta_cons += sco->meta_slots_used;
                 dev_kfree_skb(skb);
         }
@@ -785,6 +785,7 @@ static void xen_netbk_rx_action(struct xen_netbk *netbk)
         list_for_each_entry_safe(vif, tmp, &notify, notify_list) {
                 notify_remote_via_irq(vif->irq);
                 list_del_init(&vif->notify_list);
+                xenvif_put(vif);
         }
 
         /* More work to do? */
diff --git a/drivers/nfc/Kconfig b/drivers/nfc/Kconfig
index 4775d4e61b88..74a852e4e41f 100644
--- a/drivers/nfc/Kconfig
+++ b/drivers/nfc/Kconfig
@@ -28,7 +28,7 @@ config NFC_WILINK
 
 config NFC_MEI_PHY
         tristate "MEI bus NFC device support"
-        depends on INTEL_MEI_BUS_NFC && NFC_HCI
+        depends on INTEL_MEI && NFC_HCI
         help
           This adds support to use an mei bus nfc device. Select this if you
           will use an HCI NFC driver for an NFC chip connected behind an
diff --git a/drivers/nfc/mei_phy.c b/drivers/nfc/mei_phy.c
index b8f8abc422f0..1201bdbfb791 100644
--- a/drivers/nfc/mei_phy.c
+++ b/drivers/nfc/mei_phy.c
@@ -64,6 +64,15 @@ int nfc_mei_phy_enable(void *phy_id)
                 return r;
         }
 
+        r = mei_cl_register_event_cb(phy->device, nfc_mei_event_cb, phy);
+        if (r) {
+                pr_err("MEY_PHY: Event cb registration failed\n");
+                mei_cl_disable_device(phy->device);
+                phy->powered = 0;
+
+                return r;
+        }
+
         phy->powered = 1;
 
         return 0;
diff --git a/drivers/nfc/microread/mei.c b/drivers/nfc/microread/mei.c
index 1ad044dce7b6..cdf1bc53b257 100644
--- a/drivers/nfc/microread/mei.c
+++ b/drivers/nfc/microread/mei.c
@@ -43,24 +43,16 @@ static int microread_mei_probe(struct mei_cl_device *device,
                 return -ENOMEM;
         }
 
-        r = mei_cl_register_event_cb(device, nfc_mei_event_cb, phy);
-        if (r) {
-                pr_err(MICROREAD_DRIVER_NAME ": event cb registration failed\n");
-                goto err_out;
-        }
-
         r = microread_probe(phy, &mei_phy_ops, LLC_NOP_NAME,
                             MEI_NFC_HEADER_SIZE, 0, MEI_NFC_MAX_HCI_PAYLOAD,
                             &phy->hdev);
-        if (r < 0)
-                goto err_out;
-
-        return 0;
+        if (r < 0) {
+                nfc_mei_phy_free(phy);
 
-err_out:
-        nfc_mei_phy_free(phy);
+                return r;
+        }
 
-        return r;
+        return 0;
 }
 
 static int microread_mei_remove(struct mei_cl_device *device)
@@ -71,8 +63,6 @@ static int microread_mei_remove(struct mei_cl_device *device)
 
         microread_remove(phy->hdev);
 
-        nfc_mei_phy_disable(phy);
-
         nfc_mei_phy_free(phy);
 
         return 0;
diff --git a/drivers/nfc/pn544/mei.c b/drivers/nfc/pn544/mei.c
index 1eb48848a35a..b5d3d18179eb 100644
--- a/drivers/nfc/pn544/mei.c
+++ b/drivers/nfc/pn544/mei.c
@@ -43,24 +43,16 @@ static int pn544_mei_probe(struct mei_cl_device *device,
                 return -ENOMEM;
         }
 
-        r = mei_cl_register_event_cb(device, nfc_mei_event_cb, phy);
-        if (r) {
-                pr_err(PN544_DRIVER_NAME ": event cb registration failed\n");
-                goto err_out;
-        }
-
         r = pn544_hci_probe(phy, &mei_phy_ops, LLC_NOP_NAME,
                             MEI_NFC_HEADER_SIZE, 0, MEI_NFC_MAX_HCI_PAYLOAD,
                             &phy->hdev);
-        if (r < 0)
-                goto err_out;
-
-        return 0;
+        if (r < 0) {
+                nfc_mei_phy_free(phy);
 
-err_out:
-        nfc_mei_phy_free(phy);
+                return r;
+        }
 
-        return r;
+        return 0;
 }
 
 static int pn544_mei_remove(struct mei_cl_device *device)
@@ -71,8 +63,6 @@ static int pn544_mei_remove(struct mei_cl_device *device)
 
         pn544_hci_remove(phy->hdev);
 
-        nfc_mei_phy_disable(phy);
-
         nfc_mei_phy_free(phy);
 
         return 0;
diff --git a/drivers/of/address.c b/drivers/of/address.c
index 04da786c84d2..fdd0636a987d 100644
--- a/drivers/of/address.c
+++ b/drivers/of/address.c
@@ -227,6 +227,73 @@ int of_pci_address_to_resource(struct device_node *dev, int bar,
         return __of_address_to_resource(dev, addrp, size, flags, NULL, r);
 }
 EXPORT_SYMBOL_GPL(of_pci_address_to_resource);
+
+int of_pci_range_parser_init(struct of_pci_range_parser *parser,
+                                struct device_node *node)
+{
+        const int na = 3, ns = 2;
+        int rlen;
+
+        parser->node = node;
+        parser->pna = of_n_addr_cells(node);
+        parser->np = parser->pna + na + ns;
+
+        parser->range = of_get_property(node, "ranges", &rlen);
+        if (parser->range == NULL)
+                return -ENOENT;
+
+        parser->end = parser->range + rlen / sizeof(__be32);
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_init);
+
+struct of_pci_range *of_pci_range_parser_one(struct of_pci_range_parser *parser,
+                                                struct of_pci_range *range)
+{
+        const int na = 3, ns = 2;
+
+        if (!range)
+                return NULL;
+
+        if (!parser->range || parser->range + parser->np > parser->end)
+                return NULL;
+
+        range->pci_space = parser->range[0];
+        range->flags = of_bus_pci_get_flags(parser->range);
+        range->pci_addr = of_read_number(parser->range + 1, ns);
+        range->cpu_addr = of_translate_address(parser->node,
+                                parser->range + na);
+        range->size = of_read_number(parser->range + parser->pna + na, ns);
+
+        parser->range += parser->np;
+
+        /* Now consume following elements while they are contiguous */
+        while (parser->range + parser->np <= parser->end) {
+                u32 flags, pci_space;
+                u64 pci_addr, cpu_addr, size;
+
+                pci_space = be32_to_cpup(parser->range);
+                flags = of_bus_pci_get_flags(parser->range);
+                pci_addr = of_read_number(parser->range + 1, ns);
+                cpu_addr = of_translate_address(parser->node,
+                                parser->range + na);
+                size = of_read_number(parser->range + parser->pna + na, ns);
+
+                if (flags != range->flags)
+                        break;
+                if (pci_addr != range->pci_addr + range->size ||
+                    cpu_addr != range->cpu_addr + range->size)
+                        break;
+
+                range->size += size;
+                parser->range += parser->np;
+        }
+
+        return range;
+}
+EXPORT_SYMBOL_GPL(of_pci_range_parser_one);
+
 #endif /* CONFIG_PCI */
 
 /*
diff --git a/drivers/of/base.c b/drivers/of/base.c
index f53b992f060a..a6f584a7f4a1 100644
--- a/drivers/of/base.c
+++ b/drivers/of/base.c
@@ -192,14 +192,15 @@ EXPORT_SYMBOL(of_find_property);
 struct device_node *of_find_all_nodes(struct device_node *prev)
 {
         struct device_node *np;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         np = prev ? prev->allnext : of_allnodes;
         for (; np != NULL; np = np->allnext)
                 if (of_node_get(np))
                         break;
         of_node_put(prev);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return np;
 }
 EXPORT_SYMBOL(of_find_all_nodes);
@@ -421,8 +422,9 @@ struct device_node *of_get_next_available_child(const struct device_node *node,
         struct device_node *prev)
 {
         struct device_node *next;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         next = prev ? prev->sibling : node->child;
         for (; next; next = next->sibling) {
                 if (!__of_device_is_available(next))
@@ -431,7 +433,7 @@ struct device_node *of_get_next_available_child(const struct device_node *node,
                         break;
         }
         of_node_put(prev);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return next;
 }
 EXPORT_SYMBOL(of_get_next_available_child);
@@ -735,13 +737,14 @@ EXPORT_SYMBOL_GPL(of_modalias_node);
 struct device_node *of_find_node_by_phandle(phandle handle)
 {
         struct device_node *np;
+        unsigned long flags;
 
-        raw_spin_lock(&devtree_lock);
+        raw_spin_lock_irqsave(&devtree_lock, flags);
         for (np = of_allnodes; np; np = np->allnext)
                 if (np->phandle == handle)
                         break;
         of_node_get(np);
-        raw_spin_unlock(&devtree_lock);
+        raw_spin_unlock_irqrestore(&devtree_lock, flags);
         return np;
 }
 EXPORT_SYMBOL(of_find_node_by_phandle);
diff --git a/drivers/of/of_pci.c b/drivers/of/of_pci.c
index 13e37e2d8ec1..42c687a820ac 100644
--- a/drivers/of/of_pci.c
+++ b/drivers/of/of_pci.c
@@ -5,14 +5,15 @@
 #include <asm/prom.h>
 
 static inline int __of_pci_pci_compare(struct device_node *node,
-                                       unsigned int devfn)
+                                       unsigned int data)
 {
-        unsigned int size;
-        const __be32 *reg = of_get_property(node, "reg", &size);
+        int devfn;
 
-        if (!reg || size < 5 * sizeof(__be32))
+        devfn = of_pci_get_devfn(node);
+        if (devfn < 0)
                 return 0;
-        return ((be32_to_cpup(&reg[0]) >> 8) & 0xff) == devfn;
+
+        return devfn == data;
 }
 
 struct device_node *of_pci_find_child_device(struct device_node *parent,
@@ -40,3 +41,51 @@ struct device_node *of_pci_find_child_device(struct device_node *parent,
         return NULL;
 }
 EXPORT_SYMBOL_GPL(of_pci_find_child_device);
+
+/**
+ * of_pci_get_devfn() - Get device and function numbers for a device node
+ * @np: device node
+ *
+ * Parses a standard 5-cell PCI resource and returns an 8-bit value that can
+ * be passed to the PCI_SLOT() and PCI_FUNC() macros to extract the device
+ * and function numbers respectively. On error a negative error code is
+ * returned.
+ */
+int of_pci_get_devfn(struct device_node *np)
+{
+        unsigned int size;
+        const __be32 *reg;
+
+        reg = of_get_property(np, "reg", &size);
+
+        if (!reg || size < 5 * sizeof(__be32))
+                return -EINVAL;
+
+        return (be32_to_cpup(reg) >> 8) & 0xff;
+}
+EXPORT_SYMBOL_GPL(of_pci_get_devfn);
+
+/**
+ * of_pci_parse_bus_range() - parse the bus-range property of a PCI device
+ * @node: device node
+ * @res: address to a struct resource to return the bus-range
+ *
+ * Returns 0 on success or a negative error-code on failure.
+ */
+int of_pci_parse_bus_range(struct device_node *node, struct resource *res)
+{
+        const __be32 *values;
+        int len;
+
+        values = of_get_property(node, "bus-range", &len);
+        if (!values || len < sizeof(*values) * 2)
+                return -EINVAL;
+
+        res->name = node->name;
+        res->start = be32_to_cpup(values++);
+        res->end = be32_to_cpup(values);
+        res->flags = IORESOURCE_BUS;
+
+        return 0;
+}
+EXPORT_SYMBOL_GPL(of_pci_parse_bus_range);
diff --git a/drivers/parisc/lba_pci.c b/drivers/parisc/lba_pci.c
index 2ef7103270bb..1f05913ae677 100644
--- a/drivers/parisc/lba_pci.c
+++ b/drivers/parisc/lba_pci.c
@@ -668,7 +668,7 @@ lba_fixup_bus(struct pci_bus *bus)
                         BUG();
                 }
 
-                if (ldev->hba.elmmio_space.start) {
+                if (ldev->hba.elmmio_space.flags) {
                         err = request_resource(&iomem_resource,
                                         &(ldev->hba.elmmio_space));
                         if (err < 0) {
@@ -993,7 +993,7 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
 
                 case PAT_LMMIO:
                         /* used to fix up pre-initialized MEM BARs */
-                        if (!lba_dev->hba.lmmio_space.start) {
+                        if (!lba_dev->hba.lmmio_space.flags) {
                                 sprintf(lba_dev->hba.lmmio_name,
                                                 "PCI%02x LMMIO",
                                                 (int)lba_dev->hba.bus_num.start);
@@ -1001,7 +1001,7 @@ lba_pat_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
                                         io->start;
                                 r = &lba_dev->hba.lmmio_space;
                                 r->name = lba_dev->hba.lmmio_name;
-                        } else if (!lba_dev->hba.elmmio_space.start) {
+                        } else if (!lba_dev->hba.elmmio_space.flags) {
                                 sprintf(lba_dev->hba.elmmio_name,
                                                 "PCI%02x ELMMIO",
                                                 (int)lba_dev->hba.bus_num.start);
@@ -1096,6 +1096,7 @@ lba_legacy_resources(struct parisc_device *pa_dev, struct lba_device *lba_dev)
         r->name = "LBA PCI Busses";
         r->start = lba_num & 0xff;
         r->end = (lba_num>>8) & 0xff;
+        r->flags = IORESOURCE_BUS;
 
         /* Set up local PCI Bus resources - we don't need them for
         ** Legacy boxes but it's nice to see in /proc/iomem.
@@ -1494,7 +1495,7 @@ lba_driver_probe(struct parisc_device *dev)
 
         pci_add_resource_offset(&resources, &lba_dev->hba.io_space,
                                 HBA_PORT_BASE(lba_dev->hba.hba_num));
-        if (lba_dev->hba.elmmio_space.start)
+        if (lba_dev->hba.elmmio_space.flags)
                 pci_add_resource_offset(&resources, &lba_dev->hba.elmmio_space,
                                         lba_dev->hba.lmmio_space_offset);
         if (lba_dev->hba.lmmio_space.flags)
diff --git a/drivers/parport/Kconfig b/drivers/parport/Kconfig
index 24e12d4d1769..a50576081b34 100644
--- a/drivers/parport/Kconfig
+++ b/drivers/parport/Kconfig
@@ -71,7 +71,7 @@ config PARPORT_PC_FIFO
 
 config PARPORT_PC_SUPERIO
         bool "SuperIO chipset support"
-        depends on PARPORT_PC
+        depends on PARPORT_PC && !PARISC
         help
           Saying Y here enables some probes for Super-IO chipsets in order to
           find out things like base addresses, IRQ lines and DMA channels.  It
diff --git a/drivers/parport/parport_gsc.c b/drivers/parport/parport_gsc.c
index a5251cb5fb0c..6e3a60c78873 100644
--- a/drivers/parport/parport_gsc.c
+++ b/drivers/parport/parport_gsc.c
@@ -234,7 +234,7 @@ static int parport_PS2_supported(struct parport *pb)
 
 struct parport *parport_gsc_probe_port(unsigned long base,
                                        unsigned long base_hi, int irq,
-                                       int dma, struct pci_dev *dev)
+                                       int dma, struct parisc_device *padev)
 {
         struct parport_gsc_private *priv;
         struct parport_operations *ops;
@@ -258,7 +258,6 @@ struct parport *parport_gsc_probe_port(unsigned long base,
         priv->ctr_writable = 0xff;
         priv->dma_buf = 0;
         priv->dma_handle = 0;
-        priv->dev = dev;
         p->base = base;
         p->base_hi = base_hi;
         p->irq = irq;
@@ -282,6 +281,7 @@ struct parport *parport_gsc_probe_port(unsigned long base,
                 return NULL;
         }
 
+        p->dev = &padev->dev;
         p->base_hi = base_hi;
         p->modes = tmp.modes;
         p->size = (p->modes & PARPORT_MODE_EPP)?8:3;
@@ -373,7 +373,7 @@ static int parport_init_chip(struct parisc_device *dev)
         }
         
         p = parport_gsc_probe_port(port, 0, dev->irq,
-                        /* PARPORT_IRQ_NONE */ PARPORT_DMA_NONE, NULL);
+                        /* PARPORT_IRQ_NONE */ PARPORT_DMA_NONE, dev);
         if (p)
                 parport_count++;
         dev_set_drvdata(&dev->dev, p);
diff --git a/drivers/parport/parport_gsc.h b/drivers/parport/parport_gsc.h
index fc9c37c54022..812214768d27 100644
--- a/drivers/parport/parport_gsc.h
+++ b/drivers/parport/parport_gsc.h
@@ -217,6 +217,6 @@ extern void parport_gsc_dec_use_count(void);
 extern struct parport *parport_gsc_probe_port(unsigned long base,
                                                 unsigned long base_hi,
                                                 int irq, int dma,
-                                                struct pci_dev *dev);
+                                                struct parisc_device *padev);
 
 #endif  /* __DRIVERS_PARPORT_PARPORT_GSC_H */
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index 6d51aa68ec7a..ac45398ebb8e 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -119,3 +119,5 @@ config PCI_IOAPIC
 config PCI_LABEL
         def_bool y if (DMI || ACPI)
         select NLS
+
+source "drivers/pci/host/Kconfig"
diff --git a/drivers/pci/Makefile b/drivers/pci/Makefile
index 0c3efcffa83b..6ebf5bf8e7a7 100644
--- a/drivers/pci/Makefile
+++ b/drivers/pci/Makefile
@@ -67,3 +67,6 @@ obj-$(CONFIG_XEN_PCIDEV_FRONTEND) += xen-pcifront.o
 obj-$(CONFIG_OF) += of.o
 
 ccflags-$(CONFIG_PCI_DEBUG) := -DDEBUG
+
+# PCI host controller drivers
+obj-y += host/
diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
new file mode 100644
index 000000000000..1f1d67fec8b2
--- /dev/null
+++ b/drivers/pci/host/Kconfig
@@ -0,0 +1,8 @@
+menu "PCI host controller drivers"
+        depends on PCI
+
+config PCI_MVEBU
+        bool "Marvell EBU PCIe controller"
+        depends on ARCH_MVEBU || ARCH_KIRKWOOD
+
+endmenu
diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
new file mode 100644
index 000000000000..5ea2d8bf013a
--- /dev/null
+++ b/drivers/pci/host/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
diff --git a/drivers/pci/host/pci-mvebu.c b/drivers/pci/host/pci-mvebu.c
new file mode 100644
index 000000000000..13a633b1612e
--- /dev/null
+++ b/drivers/pci/host/pci-mvebu.c
@@ -0,0 +1,914 @@
+/*
+ * PCIe driver for Marvell Armada 370 and Armada XP SoCs
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mbus.h>
+#include <linux/slab.h>
+#include <linux/platform_device.h>
+#include <linux/of_address.h>
+#include <linux/of_pci.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+
+/*
+ * PCIe unit register offsets.
+ */
+#define PCIE_DEV_ID_OFF         0x0000
+#define PCIE_CMD_OFF            0x0004
+#define PCIE_DEV_REV_OFF        0x0008
+#define PCIE_BAR_LO_OFF(n)      (0x0010 + ((n) << 3))
+#define PCIE_BAR_HI_OFF(n)      (0x0014 + ((n) << 3))
+#define PCIE_HEADER_LOG_4_OFF   0x0128
+#define PCIE_BAR_CTRL_OFF(n)    (0x1804 + (((n) - 1) * 4))
+#define PCIE_WIN04_CTRL_OFF(n)  (0x1820 + ((n) << 4))
+#define PCIE_WIN04_BASE_OFF(n)  (0x1824 + ((n) << 4))
+#define PCIE_WIN04_REMAP_OFF(n) (0x182c + ((n) << 4))
+#define PCIE_WIN5_CTRL_OFF      0x1880
+#define PCIE_WIN5_BASE_OFF      0x1884
+#define PCIE_WIN5_REMAP_OFF     0x188c
+#define PCIE_CONF_ADDR_OFF      0x18f8
+#define  PCIE_CONF_ADDR_EN              0x80000000
+#define  PCIE_CONF_REG(r)               ((((r) & 0xf00) << 16) | ((r) & 0xfc))
+#define  PCIE_CONF_BUS(b)               (((b) & 0xff) << 16)
+#define  PCIE_CONF_DEV(d)               (((d) & 0x1f) << 11)
+#define  PCIE_CONF_FUNC(f)              (((f) & 0x7) << 8)
+#define  PCIE_CONF_ADDR(bus, devfn, where) \
+        (PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn))    | \
+         PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where) | \
+         PCIE_CONF_ADDR_EN)
+#define PCIE_CONF_DATA_OFF      0x18fc
+#define PCIE_MASK_OFF           0x1910
+#define  PCIE_MASK_ENABLE_INTS          0x0f000000
+#define PCIE_CTRL_OFF           0x1a00
+#define  PCIE_CTRL_X1_MODE              0x0001
+#define PCIE_STAT_OFF           0x1a04
+#define  PCIE_STAT_BUS                  0xff00
+#define  PCIE_STAT_DEV                  0x1f0000
+#define  PCIE_STAT_LINK_DOWN            BIT(0)
+#define PCIE_DEBUG_CTRL         0x1a60
+#define  PCIE_DEBUG_SOFT_RESET          BIT(20)
+
+/*
+ * This product ID is registered by Marvell, and used when the Marvell
+ * SoC is not the root complex, but an endpoint on the PCIe bus. It is
+ * therefore safe to re-use this PCI ID for our emulated PCI-to-PCI
+ * bridge.
+ */
+#define MARVELL_EMULATED_PCI_PCI_BRIDGE_ID 0x7846
+
+/* PCI configuration space of a PCI-to-PCI bridge */
+struct mvebu_sw_pci_bridge {
+        u16 vendor;
+        u16 device;
+        u16 command;
+        u16 class;
+        u8 interface;
+        u8 revision;
+        u8 bist;
+        u8 header_type;
+        u8 latency_timer;
+        u8 cache_line_size;
+        u32 bar[2];
+        u8 primary_bus;
+        u8 secondary_bus;
+        u8 subordinate_bus;
+        u8 secondary_latency_timer;
+        u8 iobase;
+        u8 iolimit;
+        u16 secondary_status;
+        u16 membase;
+        u16 memlimit;
+        u16 prefmembase;
+        u16 prefmemlimit;
+        u32 prefbaseupper;
+        u32 preflimitupper;
+        u16 iobaseupper;
+        u16 iolimitupper;
+        u8 cappointer;
+        u8 reserved1;
+        u16 reserved2;
+        u32 romaddr;
+        u8 intline;
+        u8 intpin;
+        u16 bridgectrl;
+};
+
+struct mvebu_pcie_port;
+
+/* Structure representing all PCIe interfaces */
+struct mvebu_pcie {
+        struct platform_device *pdev;
+        struct mvebu_pcie_port *ports;
+        struct resource io;
+        struct resource realio;
+        struct resource mem;
+        struct resource busn;
+        int nports;
+};
+
+/* Structure representing one PCIe interface */
+struct mvebu_pcie_port {
+        char *name;
+        void __iomem *base;
+        spinlock_t conf_lock;
+        int haslink;
+        u32 port;
+        u32 lane;
+        int devfn;
+        struct clk *clk;
+        struct mvebu_sw_pci_bridge bridge;
+        struct device_node *dn;
+        struct mvebu_pcie *pcie;
+        phys_addr_t memwin_base;
+        size_t memwin_size;
+        phys_addr_t iowin_base;
+        size_t iowin_size;
+};
+
+static bool mvebu_pcie_link_up(struct mvebu_pcie_port *port)
+{
+        return !(readl(port->base + PCIE_STAT_OFF) & PCIE_STAT_LINK_DOWN);
+}
+
+static void mvebu_pcie_set_local_bus_nr(struct mvebu_pcie_port *port, int nr)
+{
+        u32 stat;
+
+        stat = readl(port->base + PCIE_STAT_OFF);
+        stat &= ~PCIE_STAT_BUS;
+        stat |= nr << 8;
+        writel(stat, port->base + PCIE_STAT_OFF);
+}
+
+static void mvebu_pcie_set_local_dev_nr(struct mvebu_pcie_port *port, int nr)
+{
+        u32 stat;
+
+        stat = readl(port->base + PCIE_STAT_OFF);
+        stat &= ~PCIE_STAT_DEV;
+        stat |= nr << 16;
+        writel(stat, port->base + PCIE_STAT_OFF);
+}
+
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void __init mvebu_pcie_setup_wins(struct mvebu_pcie_port *port)
+{
+        const struct mbus_dram_target_info *dram;
+        u32 size;
+        int i;
+
+        dram = mv_mbus_dram_info();
+
+        /* First, disable and clear BARs and windows. */
+        for (i = 1; i < 3; i++) {
+                writel(0, port->base + PCIE_BAR_CTRL_OFF(i));
+                writel(0, port->base + PCIE_BAR_LO_OFF(i));
+                writel(0, port->base + PCIE_BAR_HI_OFF(i));
+        }
+
+        for (i = 0; i < 5; i++) {
+                writel(0, port->base + PCIE_WIN04_CTRL_OFF(i));
+                writel(0, port->base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+        }
+
+        writel(0, port->base + PCIE_WIN5_CTRL_OFF);
+        writel(0, port->base + PCIE_WIN5_BASE_OFF);
+        writel(0, port->base + PCIE_WIN5_REMAP_OFF);
+
+        /* Setup windows for DDR banks.  Count total DDR size on the fly. */
+        size = 0;
+        for (i = 0; i < dram->num_cs; i++) {
+                const struct mbus_dram_window *cs = dram->cs + i;
+
+                writel(cs->base & 0xffff0000,
+                       port->base + PCIE_WIN04_BASE_OFF(i));
+                writel(0, port->base + PCIE_WIN04_REMAP_OFF(i));
+                writel(((cs->size - 1) & 0xffff0000) |
+                        (cs->mbus_attr << 8) |
+                        (dram->mbus_dram_target_id << 4) | 1,
+                       port->base + PCIE_WIN04_CTRL_OFF(i));
+
+                size += cs->size;
+        }
+
+        /* Round up 'size' to the nearest power of two. */
+        if ((size & (size - 1)) != 0)
+                size = 1 << fls(size);
+
+        /* Setup BAR[1] to all DRAM banks. */
+        writel(dram->cs[0].base, port->base + PCIE_BAR_LO_OFF(1));
+        writel(0, port->base + PCIE_BAR_HI_OFF(1));
+        writel(((size - 1) & 0xffff0000) | 1,
+               port->base + PCIE_BAR_CTRL_OFF(1));
+}
+
+static void __init mvebu_pcie_setup_hw(struct mvebu_pcie_port *port)
+{
+        u16 cmd;
+        u32 mask;
+
+        /* Point PCIe unit MBUS decode windows to DRAM space. */
+        mvebu_pcie_setup_wins(port);
+
+        /* Master + slave enable. */
+        cmd = readw(port->base + PCIE_CMD_OFF);
+        cmd |= PCI_COMMAND_IO;
+        cmd |= PCI_COMMAND_MEMORY;
+        cmd |= PCI_COMMAND_MASTER;
+        writew(cmd, port->base + PCIE_CMD_OFF);
+
+        /* Enable interrupt lines A-D. */
+        mask = readl(port->base + PCIE_MASK_OFF);
+        mask |= PCIE_MASK_ENABLE_INTS;
+        writel(mask, port->base + PCIE_MASK_OFF);
+}
+
+static int mvebu_pcie_hw_rd_conf(struct mvebu_pcie_port *port,
+                                 struct pci_bus *bus,
+                                 u32 devfn, int where, int size, u32 *val)
+{
+        writel(PCIE_CONF_ADDR(bus->number, devfn, where),
+               port->base + PCIE_CONF_ADDR_OFF);
+
+        *val = readl(port->base + PCIE_CONF_DATA_OFF);
+
+        if (size == 1)
+                *val = (*val >> (8 * (where & 3))) & 0xff;
+        else if (size == 2)
+                *val = (*val >> (8 * (where & 3))) & 0xffff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static int mvebu_pcie_hw_wr_conf(struct mvebu_pcie_port *port,
+                                 struct pci_bus *bus,
+                                 u32 devfn, int where, int size, u32 val)
+{
+        int ret = PCIBIOS_SUCCESSFUL;
+
+        writel(PCIE_CONF_ADDR(bus->number, devfn, where),
+               port->base + PCIE_CONF_ADDR_OFF);
+
+        if (size == 4)
+                writel(val, port->base + PCIE_CONF_DATA_OFF);
+        else if (size == 2)
+                writew(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+        else if (size == 1)
+                writeb(val, port->base + PCIE_CONF_DATA_OFF + (where & 3));
+        else
+                ret = PCIBIOS_BAD_REGISTER_NUMBER;
+
+        return ret;
+}
+
+static void mvebu_pcie_handle_iobase_change(struct mvebu_pcie_port *port)
+{
+        phys_addr_t iobase;
+
+        /* Are the new iobase/iolimit values invalid? */
+        if (port->bridge.iolimit < port->bridge.iobase ||
+            port->bridge.iolimitupper < port->bridge.iobaseupper) {
+
+                /* If a window was configured, remove it */
+                if (port->iowin_base) {
+                        mvebu_mbus_del_window(port->iowin_base,
+                                              port->iowin_size);
+                        port->iowin_base = 0;
+                        port->iowin_size = 0;
+                }
+
+                return;
+        }
+
+        /*
+         * We read the PCI-to-PCI bridge emulated registers, and
+         * calculate the base address and size of the address decoding
+         * window to setup, according to the PCI-to-PCI bridge
+         * specifications. iobase is the bus address, port->iowin_base
+         * is the CPU address.
+         */
+        iobase = ((port->bridge.iobase & 0xF0) << 8) |
+                (port->bridge.iobaseupper << 16);
+        port->iowin_base = port->pcie->io.start + iobase;
+        port->iowin_size = ((0xFFF | ((port->bridge.iolimit & 0xF0) << 8) |
+                            (port->bridge.iolimitupper << 16)) -
+                            iobase);
+
+        mvebu_mbus_add_window_remap_flags(port->name, port->iowin_base,
+                                          port->iowin_size,
+                                          iobase,
+                                          MVEBU_MBUS_PCI_IO);
+
+        pci_ioremap_io(iobase, port->iowin_base);
+}
+
+static void mvebu_pcie_handle_membase_change(struct mvebu_pcie_port *port)
+{
+        /* Are the new membase/memlimit values invalid? */
+        if (port->bridge.memlimit < port->bridge.membase) {
+
+                /* If a window was configured, remove it */
+                if (port->memwin_base) {
+                        mvebu_mbus_del_window(port->memwin_base,
+                                              port->memwin_size);
+                        port->memwin_base = 0;
+                        port->memwin_size = 0;
+                }
+
+                return;
+        }
+
+        /*
+         * We read the PCI-to-PCI bridge emulated registers, and
+         * calculate the base address and size of the address decoding
+         * window to setup, according to the PCI-to-PCI bridge
+         * specifications.
+         */
+        port->memwin_base  = ((port->bridge.membase & 0xFFF0) << 16);
+        port->memwin_size  =
+                (((port->bridge.memlimit & 0xFFF0) << 16) | 0xFFFFF) -
+                port->memwin_base;
+
+        mvebu_mbus_add_window_remap_flags(port->name, port->memwin_base,
+                                          port->memwin_size,
+                                          MVEBU_MBUS_NO_REMAP,
+                                          MVEBU_MBUS_PCI_MEM);
+}
+
+/*
+ * Initialize the configuration space of the PCI-to-PCI bridge
+ * associated with the given PCIe interface.
+ */
+static void mvebu_sw_pci_bridge_init(struct mvebu_pcie_port *port)
+{
+        struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+
+        memset(bridge, 0, sizeof(struct mvebu_sw_pci_bridge));
+
+        bridge->class = PCI_CLASS_BRIDGE_PCI;
+        bridge->vendor = PCI_VENDOR_ID_MARVELL;
+        bridge->device = MARVELL_EMULATED_PCI_PCI_BRIDGE_ID;
+        bridge->header_type = PCI_HEADER_TYPE_BRIDGE;
+        bridge->cache_line_size = 0x10;
+
+        /* We support 32 bits I/O addressing */
+        bridge->iobase = PCI_IO_RANGE_TYPE_32;
+        bridge->iolimit = PCI_IO_RANGE_TYPE_32;
+}
+
+/*
+ * Read the configuration space of the PCI-to-PCI bridge associated to
+ * the given PCIe interface.
+ */
+static int mvebu_sw_pci_bridge_read(struct mvebu_pcie_port *port,
+                                  unsigned int where, int size, u32 *value)
+{
+        struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+
+        switch (where & ~3) {
+        case PCI_VENDOR_ID:
+                *value = bridge->device << 16 | bridge->vendor;
+                break;
+
+        case PCI_COMMAND:
+                *value = bridge->command;
+                break;
+
+        case PCI_CLASS_REVISION:
+                *value = bridge->class << 16 | bridge->interface << 8 |
+                         bridge->revision;
+                break;
+
+        case PCI_CACHE_LINE_SIZE:
+                *value = bridge->bist << 24 | bridge->header_type << 16 |
+                         bridge->latency_timer << 8 | bridge->cache_line_size;
+                break;
+
+        case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+                *value = bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4];
+                break;
+
+        case PCI_PRIMARY_BUS:
+                *value = (bridge->secondary_latency_timer << 24 |
+                          bridge->subordinate_bus         << 16 |
+                          bridge->secondary_bus           <<  8 |
+                          bridge->primary_bus);
+                break;
+
+        case PCI_IO_BASE:
+                *value = (bridge->secondary_status << 16 |
+                          bridge->iolimit          <<  8 |
+                          bridge->iobase);
+                break;
+
+        case PCI_MEMORY_BASE:
+                *value = (bridge->memlimit << 16 | bridge->membase);
+                break;
+
+        case PCI_PREF_MEMORY_BASE:
+                *value = (bridge->prefmemlimit << 16 | bridge->prefmembase);
+                break;
+
+        case PCI_PREF_BASE_UPPER32:
+                *value = bridge->prefbaseupper;
+                break;
+
+        case PCI_PREF_LIMIT_UPPER32:
+                *value = bridge->preflimitupper;
+                break;
+
+        case PCI_IO_BASE_UPPER16:
+                *value = (bridge->iolimitupper << 16 | bridge->iobaseupper);
+                break;
+
+        case PCI_ROM_ADDRESS1:
+                *value = 0;
+                break;
+
+        default:
+                *value = 0xffffffff;
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+        }
+
+        if (size == 2)
+                *value = (*value >> (8 * (where & 3))) & 0xffff;
+        else if (size == 1)
+                *value = (*value >> (8 * (where & 3))) & 0xff;
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+/* Write to the PCI-to-PCI bridge configuration space */
+static int mvebu_sw_pci_bridge_write(struct mvebu_pcie_port *port,
+                                     unsigned int where, int size, u32 value)
+{
+        struct mvebu_sw_pci_bridge *bridge = &port->bridge;
+        u32 mask, reg;
+        int err;
+
+        if (size == 4)
+                mask = 0x0;
+        else if (size == 2)
+                mask = ~(0xffff << ((where & 3) * 8));
+        else if (size == 1)
+                mask = ~(0xff << ((where & 3) * 8));
+        else
+                return PCIBIOS_BAD_REGISTER_NUMBER;
+
+        err = mvebu_sw_pci_bridge_read(port, where & ~3, 4, &reg);
+        if (err)
+                return err;
+
+        value = (reg & mask) | value << ((where & 3) * 8);
+
+        switch (where & ~3) {
+        case PCI_COMMAND:
+                bridge->command = value & 0xffff;
+                break;
+
+        case PCI_BASE_ADDRESS_0 ... PCI_BASE_ADDRESS_1:
+                bridge->bar[((where & ~3) - PCI_BASE_ADDRESS_0) / 4] = value;
+                break;
+
+        case PCI_IO_BASE:
+                /*
+                 * We also keep bit 1 set, it is a read-only bit that
+                 * indicates we support 32 bits addressing for the
+                 * I/O
+                 */
+                bridge->iobase = (value & 0xff) | PCI_IO_RANGE_TYPE_32;
+                bridge->iolimit = ((value >> 8) & 0xff) | PCI_IO_RANGE_TYPE_32;
+                bridge->secondary_status = value >> 16;
+                mvebu_pcie_handle_iobase_change(port);
+                break;
+
+        case PCI_MEMORY_BASE:
+                bridge->membase = value & 0xffff;
+                bridge->memlimit = value >> 16;
+                mvebu_pcie_handle_membase_change(port);
+                break;
+
+        case PCI_PREF_MEMORY_BASE:
+                bridge->prefmembase = value & 0xffff;
+                bridge->prefmemlimit = value >> 16;
+                break;
+
+        case PCI_PREF_BASE_UPPER32:
+                bridge->prefbaseupper = value;
+                break;
+
+        case PCI_PREF_LIMIT_UPPER32:
+                bridge->preflimitupper = value;
+                break;
+
+        case PCI_IO_BASE_UPPER16:
+                bridge->iobaseupper = value & 0xffff;
+                bridge->iolimitupper = value >> 16;
+                mvebu_pcie_handle_iobase_change(port);
+                break;
+
+        case PCI_PRIMARY_BUS:
+                bridge->primary_bus             = value & 0xff;
+                bridge->secondary_bus           = (value >> 8) & 0xff;
+                bridge->subordinate_bus         = (value >> 16) & 0xff;
+                bridge->secondary_latency_timer = (value >> 24) & 0xff;
+                mvebu_pcie_set_local_bus_nr(port, bridge->secondary_bus);
+                break;
+
+        default:
+                break;
+        }
+
+        return PCIBIOS_SUCCESSFUL;
+}
+
+static inline struct mvebu_pcie *sys_to_pcie(struct pci_sys_data *sys)
+{
+        return sys->private_data;
+}
+
+static struct mvebu_pcie_port *
+mvebu_pcie_find_port(struct mvebu_pcie *pcie, struct pci_bus *bus,
+                     int devfn)
+{
+        int i;
+
+        for (i = 0; i < pcie->nports; i++) {
+                struct mvebu_pcie_port *port = &pcie->ports[i];
+                if (bus->number == 0 && port->devfn == devfn)
+                        return port;
+                if (bus->number != 0 &&
+                    bus->number >= port->bridge.secondary_bus &&
+                    bus->number <= port->bridge.subordinate_bus)
+                        return port;
+        }
+
+        return NULL;
+}
+
+/* PCI configuration space write function */
+static int mvebu_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
+                              int where, int size, u32 val)
+{
+        struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
+        struct mvebu_pcie_port *port;
+        unsigned long flags;
+        int ret;
+
+        port = mvebu_pcie_find_port(pcie, bus, devfn);
+        if (!port)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /* Access the emulated PCI-to-PCI bridge */
+        if (bus->number == 0)
+                return mvebu_sw_pci_bridge_write(port, where, size, val);
+
+        if (!port->haslink)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /*
+         * On the secondary bus, we don't want to expose any other
+         * device than the device physically connected in the PCIe
+         * slot, visible in slot 0. In slot 1, there's a special
+         * Marvell device that only makes sense when the Armada is
+         * used as a PCIe endpoint.
+         */
+        if (bus->number == port->bridge.secondary_bus &&
+            PCI_SLOT(devfn) != 0)
+                return PCIBIOS_DEVICE_NOT_FOUND;
+
+        /* Access the real PCIe interface */
+        spin_lock_irqsave(&port->conf_lock, flags);
+        ret = mvebu_pcie_hw_wr_conf(port, bus, devfn,
+                                    where, size, val);
+        spin_unlock_irqrestore(&port->conf_lock, flags);
+
+        return ret;
+}
+
+/* PCI configuration space read function */
+static int mvebu_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
+                              int size, u32 *val)
+{
+        struct mvebu_pcie *pcie = sys_to_pcie(bus->sysdata);
+        struct mvebu_pcie_port *port;
+        unsigned long flags;
+        int ret;
+
+        port = mvebu_pcie_find_port(pcie, bus, devfn);
+        if (!port) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /* Access the emulated PCI-to-PCI bridge */
+        if (bus->number == 0)
+                return mvebu_sw_pci_bridge_read(port, where, size, val);
+
+        if (!port->haslink) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /*
+         * On the secondary bus, we don't want to expose any other
+         * device than the device physically connected in the PCIe
+         * slot, visible in slot 0. In slot 1, there's a special
+         * Marvell device that only makes sense when the Armada is
+         * used as a PCIe endpoint.
+         */
+        if (bus->number == port->bridge.secondary_bus &&
+            PCI_SLOT(devfn) != 0) {
+                *val = 0xffffffff;
+                return PCIBIOS_DEVICE_NOT_FOUND;
+        }
+
+        /* Access the real PCIe interface */
+        spin_lock_irqsave(&port->conf_lock, flags);
+        ret = mvebu_pcie_hw_rd_conf(port, bus, devfn,
+                                    where, size, val);
+        spin_unlock_irqrestore(&port->conf_lock, flags);
+
+        return ret;
+}
+
+static struct pci_ops mvebu_pcie_ops = {
+        .read = mvebu_pcie_rd_conf,
+        .write = mvebu_pcie_wr_conf,
+};
+
+static int __init mvebu_pcie_setup(int nr, struct pci_sys_data *sys)
+{
+        struct mvebu_pcie *pcie = sys_to_pcie(sys);
+        int i;
+
+        pci_add_resource_offset(&sys->resources, &pcie->realio, sys->io_offset);
+        pci_add_resource_offset(&sys->resources, &pcie->mem, sys->mem_offset);
+        pci_add_resource(&sys->resources, &pcie->busn);
+
+        for (i = 0; i < pcie->nports; i++) {
+                struct mvebu_pcie_port *port = &pcie->ports[i];
+                mvebu_pcie_setup_hw(port);
+        }
+
+        return 1;
+}
+
+static int __init mvebu_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+        struct of_irq oirq;
+        int ret;
+
+        ret = of_irq_map_pci(dev, &oirq);
+        if (ret)
+                return ret;
+
+        return irq_create_of_mapping(oirq.controller, oirq.specifier,
+                                     oirq.size);
+}
+
+static struct pci_bus *mvebu_pcie_scan_bus(int nr, struct pci_sys_data *sys)
+{
+        struct mvebu_pcie *pcie = sys_to_pcie(sys);
+        struct pci_bus *bus;
+
+        bus = pci_create_root_bus(&pcie->pdev->dev, sys->busnr,
+                                  &mvebu_pcie_ops, sys, &sys->resources);
+        if (!bus)
+                return NULL;
+
+        pci_scan_child_bus(bus);
+
+        return bus;
+}
+
+resource_size_t mvebu_pcie_align_resource(struct pci_dev *dev,
+                                          const struct resource *res,
+                                          resource_size_t start,
+                                          resource_size_t size,
+                                          resource_size_t align)
+{
+        if (dev->bus->number != 0)
+                return start;
+
+        /*
+         * On the PCI-to-PCI bridge side, the I/O windows must have at
+         * least a 64 KB size and be aligned on their size, and the
+         * memory windows must have at least a 1 MB size and be
+         * aligned on their size
+         */
+        if (res->flags & IORESOURCE_IO)
+                return round_up(start, max((resource_size_t)SZ_64K, size));
+        else if (res->flags & IORESOURCE_MEM)
+                return round_up(start, max((resource_size_t)SZ_1M, size));
+        else
+                return start;
+}
+
+static void __init mvebu_pcie_enable(struct mvebu_pcie *pcie)
+{
+        struct hw_pci hw;
+
+        memset(&hw, 0, sizeof(hw));
+
+        hw.nr_controllers = 1;
+        hw.private_data   = (void **)&pcie;
+        hw.setup          = mvebu_pcie_setup;
+        hw.scan           = mvebu_pcie_scan_bus;
+        hw.map_irq        = mvebu_pcie_map_irq;
+        hw.ops            = &mvebu_pcie_ops;
+        hw.align_resource = mvebu_pcie_align_resource;
+
+        pci_common_init(&hw);
+}
+
+/*
+ * Looks up the list of register addresses encoded into the reg =
+ * <...> property for one that matches the given port/lane. Once
+ * found, maps it.
+ */
+static void __iomem * __init
+mvebu_pcie_map_registers(struct platform_device *pdev,
+                         struct device_node *np,
+                         struct mvebu_pcie_port *port)
+{
+        struct resource regs;
+        int ret = 0;
+
+        ret = of_address_to_resource(np, 0, &regs);
+        if (ret)
+                return NULL;
+
+        return devm_request_and_ioremap(&pdev->dev, &regs);
+}
+
+static int __init mvebu_pcie_probe(struct platform_device *pdev)
+{
+        struct mvebu_pcie *pcie;
+        struct device_node *np = pdev->dev.of_node;
+        struct of_pci_range range;
+        struct of_pci_range_parser parser;
+        struct device_node *child;
+        int i, ret;
+
+        pcie = devm_kzalloc(&pdev->dev, sizeof(struct mvebu_pcie),
+                            GFP_KERNEL);
+        if (!pcie)
+                return -ENOMEM;
+
+        pcie->pdev = pdev;
+
+        if (of_pci_range_parser_init(&parser, np))
+                return -EINVAL;
+
+        /* Get the I/O and memory ranges from DT */
+        for_each_of_pci_range(&parser, &range) {
+                unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
+                if (restype == IORESOURCE_IO) {
+                        of_pci_range_to_resource(&range, np, &pcie->io);
+                        of_pci_range_to_resource(&range, np, &pcie->realio);
+                        pcie->io.name = "I/O";
+                        pcie->realio.start = max_t(resource_size_t,
+                                                   PCIBIOS_MIN_IO,
+                                                   range.pci_addr);
+                        pcie->realio.end = min_t(resource_size_t,
+                                                 IO_SPACE_LIMIT,
+                                                 range.pci_addr + range.size);
+                }
+                if (restype == IORESOURCE_MEM) {
+                        of_pci_range_to_resource(&range, np, &pcie->mem);
+                        pcie->mem.name = "MEM";
+                }
+        }
+
+        /* Get the bus range */
+        ret = of_pci_parse_bus_range(np, &pcie->busn);
+        if (ret) {
+                dev_err(&pdev->dev, "failed to parse bus-range property: %d\n",
+                        ret);
+                return ret;
+        }
+
+        for_each_child_of_node(pdev->dev.of_node, child) {
+                if (!of_device_is_available(child))
+                        continue;
+                pcie->nports++;
+        }
+
+        pcie->ports = devm_kzalloc(&pdev->dev, pcie->nports *
+                                   sizeof(struct mvebu_pcie_port),
+                                   GFP_KERNEL);
+        if (!pcie->ports)
+                return -ENOMEM;
+
+        i = 0;
+        for_each_child_of_node(pdev->dev.of_node, child) {
+                struct mvebu_pcie_port *port = &pcie->ports[i];
+
+                if (!of_device_is_available(child))
+                        continue;
+
+                port->pcie = pcie;
+
+                if (of_property_read_u32(child, "marvell,pcie-port",
+                                         &port->port)) {
+                        dev_warn(&pdev->dev,
+                                 "ignoring PCIe DT node, missing pcie-port property\n");
+                        continue;
+                }
+
+                if (of_property_read_u32(child, "marvell,pcie-lane",
+                                         &port->lane))
+                        port->lane = 0;
+
+                port->name = kasprintf(GFP_KERNEL, "pcie%d.%d",
+                                       port->port, port->lane);
+
+                port->devfn = of_pci_get_devfn(child);
+                if (port->devfn < 0)
+                        continue;
+
+                port->base = mvebu_pcie_map_registers(pdev, child, port);
+                if (!port->base) {
+                        dev_err(&pdev->dev, "PCIe%d.%d: cannot map registers\n",
+                                port->port, port->lane);
+                        continue;
+                }
+
+                mvebu_pcie_set_local_dev_nr(port, 1);
+
+                if (mvebu_pcie_link_up(port)) {
+                        port->haslink = 1;
+                        dev_info(&pdev->dev, "PCIe%d.%d: link up\n",
+                                 port->port, port->lane);
+                } else {
+                        port->haslink = 0;
+                        dev_info(&pdev->dev, "PCIe%d.%d: link down\n",
+                                 port->port, port->lane);
+                }
+
+                port->clk = of_clk_get_by_name(child, NULL);
+                if (IS_ERR(port->clk)) {
+                        dev_err(&pdev->dev, "PCIe%d.%d: cannot get clock\n",
+                               port->port, port->lane);
+                        iounmap(port->base);
+                        port->haslink = 0;
+                        continue;
+                }
+
+                port->dn = child;
+
+                clk_prepare_enable(port->clk);
+                spin_lock_init(&port->conf_lock);
+
+                mvebu_sw_pci_bridge_init(port);
+
+                i++;
+        }
+
+        mvebu_pcie_enable(pcie);
+
+        return 0;
+}
+
+static const struct of_device_id mvebu_pcie_of_match_table[] = {
+        { .compatible = "marvell,armada-xp-pcie", },
+        { .compatible = "marvell,armada-370-pcie", },
+        { .compatible = "marvell,kirkwood-pcie", },
+        {},
+};
+MODULE_DEVICE_TABLE(of, mvebu_pcie_of_match_table);
+
+static struct platform_driver mvebu_pcie_driver = {
+        .driver = {
+                .owner = THIS_MODULE,
+                .name = "mvebu-pcie",
+                .of_match_table =
+                   of_match_ptr(mvebu_pcie_of_match_table),
+        },
+};
+
+static int __init mvebu_pcie_init(void)
+{
+        return platform_driver_probe(&mvebu_pcie_driver,
+                                     mvebu_pcie_probe);
+}
+
+subsys_initcall(mvebu_pcie_init);
+
+MODULE_AUTHOR("Thomas Petazzoni <thomas.petazzoni@free-electrons.com>");
+MODULE_DESCRIPTION("Marvell EBU PCIe driver");
+MODULE_LICENSE("GPLv2");
diff --git a/drivers/pci/pcie/aer/aerdrv_core.c b/drivers/pci/pcie/aer/aerdrv_core.c
index 8ec8b4f48560..0f4554e48cc5 100644
--- a/drivers/pci/pcie/aer/aerdrv_core.c
+++ b/drivers/pci/pcie/aer/aerdrv_core.c
@@ -580,6 +580,7 @@ struct aer_recover_entry
         u8      devfn;
         u16     domain;
         int     severity;
+        struct aer_capability_regs *regs;
 };
 
 static DEFINE_KFIFO(aer_recover_ring, struct aer_recover_entry,
@@ -593,7 +594,7 @@ static DEFINE_SPINLOCK(aer_recover_ring_lock);
 static DECLARE_WORK(aer_recover_work, aer_recover_work_func);
 
 void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
-                       int severity)
+                       int severity, struct aer_capability_regs *aer_regs)
 {
         unsigned long flags;
         struct aer_recover_entry entry = {
@@ -601,6 +602,7 @@ void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn,
                 .devfn          = devfn,
                 .domain         = domain,
                 .severity       = severity,
+                .regs           = aer_regs,
         };
 
         spin_lock_irqsave(&aer_recover_ring_lock, flags);
@@ -627,6 +629,7 @@ static void aer_recover_work_func(struct work_struct *work)
                                PCI_SLOT(entry.devfn), PCI_FUNC(entry.devfn));
                         continue;
                 }
+                cper_print_aer(pdev, entry.severity, entry.regs);
                 do_recovery(pdev, entry.severity);
                 pci_dev_put(pdev);
         }
diff --git a/drivers/pci/pcie/aer/aerdrv_errprint.c b/drivers/pci/pcie/aer/aerdrv_errprint.c
index 5ab14251839d..2c7c9f5f592c 100644
--- a/drivers/pci/pcie/aer/aerdrv_errprint.c
+++ b/drivers/pci/pcie/aer/aerdrv_errprint.c
@@ -220,7 +220,7 @@ int cper_severity_to_aer(int cper_severity)
 }
 EXPORT_SYMBOL_GPL(cper_severity_to_aer);
 
-void cper_print_aer(const char *prefix, struct pci_dev *dev, int cper_severity,
+void cper_print_aer(struct pci_dev *dev, int cper_severity,
                     struct aer_capability_regs *aer)
 {
         int aer_severity, layer, agent, status_strs_size, tlp_header_valid = 0;
@@ -244,7 +244,7 @@ void cper_print_aer(const char *prefix, struct pci_dev *dev, int cper_severity,
         agent = AER_GET_AGENT(aer_severity, status);
         dev_err(&dev->dev, "aer_status: 0x%08x, aer_mask: 0x%08x\n",
                status, mask);
-        cper_print_bits(prefix, status, status_strs, status_strs_size);
+        cper_print_bits("", status, status_strs, status_strs_size);
         dev_err(&dev->dev, "aer_layer=%s, aer_agent=%s\n",
                aer_error_layer[layer], aer_agent_string[agent]);
         if (aer_severity != AER_CORRECTABLE)
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 8f6692438149..a1c6dd32e14b 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -207,12 +207,13 @@ config PINCTRL_SAMSUNG
         select PINCONF
 
 config PINCTRL_EXYNOS
-        bool "Pinctrl driver data for Samsung EXYNOS SoCs"
-        depends on OF && GPIOLIB
+        bool "Pinctrl driver data for Samsung EXYNOS SoCs other than 5440"
+        depends on OF && GPIOLIB && ARCH_EXYNOS
         select PINCTRL_SAMSUNG
 
 config PINCTRL_EXYNOS5440
         bool "Samsung EXYNOS5440 SoC pinctrl driver"
+        depends on SOC_EXYNOS5440
         select PINMUX
         select PINCONF
 
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index c67c37e23dd7..694c3ace4520 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -610,7 +610,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
         bool found = false;
         unsigned long config;
 
-        mutex_lock(&pctldev->mutex);
+        mutex_lock(&pinctrl_maps_mutex);
 
         /* Parse the pinctrl map and look for the elected pin/state */
         for_each_maps(maps_node, i, map) {
@@ -659,7 +659,7 @@ static int pinconf_dbg_config_print(struct seq_file *s, void *d)
                 confops->pin_config_config_dbg_show(pctldev, s, config);
 
 exit:
-        mutex_unlock(&pctldev->mutex);
+        mutex_unlock(&pinctrl_maps_mutex);
 
         return 0;
 }
diff --git a/drivers/pinctrl/pinctrl-coh901.c b/drivers/pinctrl/pinctrl-coh901.c
index a67af419f531..eeff7f7fc920 100644
--- a/drivers/pinctrl/pinctrl-coh901.c
+++ b/drivers/pinctrl/pinctrl-coh901.c
@@ -22,7 +22,6 @@
 #include <linux/slab.h>
 #include <linux/pinctrl/consumer.h>
 #include <linux/pinctrl/pinconf-generic.h>
-#include <linux/platform_data/pinctrl-coh901.h>
 #include "pinctrl-coh901.h"
 
 #define U300_GPIO_PORT_STRIDE                           (0x30)
@@ -58,8 +57,9 @@
 #define U300_GPIO_PXICR_IRQ_CONFIG_RISING_EDGE          (0x00000001UL)
 
 /* 8 bits per port, no version has more than 7 ports */
+#define U300_GPIO_NUM_PORTS 7
 #define U300_GPIO_PINS_PER_PORT 8
-#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * 7)
+#define U300_GPIO_MAX (U300_GPIO_PINS_PER_PORT * U300_GPIO_NUM_PORTS)
 
 struct u300_gpio {
         struct gpio_chip chip;
@@ -111,9 +111,6 @@ struct u300_gpio_confdata {
         int outval;
 };
 
-/* BS335 has seven ports of 8 bits each = GPIO pins 0..55 */
-#define BS335_GPIO_NUM_PORTS 7
-
 #define U300_FLOATING_INPUT { \
         .bias_mode = PIN_CONFIG_BIAS_HIGH_IMPEDANCE, \
         .output = false, \
@@ -136,7 +133,7 @@ struct u300_gpio_confdata {
 
 /* Initial configuration */
 static const struct __initconst u300_gpio_confdata
-bs335_gpio_config[BS335_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
+bs335_gpio_config[U300_GPIO_NUM_PORTS][U300_GPIO_PINS_PER_PORT] = {
         /* Port 0, pins 0-7 */
         {
                 U300_FLOATING_INPUT,
@@ -630,13 +627,12 @@ static void __init u300_gpio_init_pin(struct u300_gpio *gpio,
         }
 }
 
-static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio,
-                                     struct u300_gpio_platform *plat)
+static void __init u300_gpio_init_coh901571(struct u300_gpio *gpio)
 {
         int i, j;
 
         /* Write default config and values to all pins */
-        for (i = 0; i < plat->ports; i++) {
+        for (i = 0; i < U300_GPIO_NUM_PORTS; i++) {
                 for (j = 0; j < 8; j++) {
                         const struct u300_gpio_confdata *conf;
                         int offset = (i*8) + j;
@@ -693,7 +689,6 @@ static struct coh901_pinpair coh901_pintable[] = {
 
 static int __init u300_gpio_probe(struct platform_device *pdev)
 {
-        struct u300_gpio_platform *plat = dev_get_platdata(&pdev->dev);
         struct u300_gpio *gpio;
         struct resource *memres;
         int err = 0;
@@ -707,9 +702,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                 return -ENOMEM;
 
         gpio->chip = u300_gpio_chip;
-        gpio->chip.ngpio = plat->ports * U300_GPIO_PINS_PER_PORT;
+        gpio->chip.ngpio = U300_GPIO_NUM_PORTS * U300_GPIO_PINS_PER_PORT;
         gpio->chip.dev = &pdev->dev;
-        gpio->chip.base = plat->gpio_base;
+        gpio->chip.base = 0;
         gpio->dev = &pdev->dev;
 
         memres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
@@ -750,11 +745,11 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                  ((val & 0x0000FE00) >> 9) * 8);
         writel(U300_GPIO_CR_BLOCK_CLKRQ_ENABLE,
                gpio->base + U300_GPIO_CR);
-        u300_gpio_init_coh901571(gpio, plat);
+        u300_gpio_init_coh901571(gpio);
 
         /* Add each port with its IRQ separately */
         INIT_LIST_HEAD(&gpio->port_list);
-        for (portno = 0 ; portno < plat->ports; portno++) {
+        for (portno = 0 ; portno < U300_GPIO_NUM_PORTS; portno++) {
                 struct u300_gpio_port *port =
                         kmalloc(sizeof(struct u300_gpio_port), GFP_KERNEL);
 
@@ -768,8 +763,7 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
                 port->number = portno;
                 port->gpio = gpio;
 
-                port->irq = platform_get_irq_byname(pdev,
-                                                    port->name);
+                port->irq = platform_get_irq(pdev, portno);
 
                 dev_dbg(gpio->dev, "register IRQ %d for port %s\n", port->irq,
                         port->name);
@@ -806,6 +800,9 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
         }
         dev_dbg(gpio->dev, "initialized %d GPIO ports\n", portno);
 
+#ifdef CONFIG_OF_GPIO
+        gpio->chip.of_node = pdev->dev.of_node;
+#endif
         err = gpiochip_add(&gpio->chip);
         if (err) {
                 dev_err(gpio->dev, "unable to add gpiochip: %d\n", err);
@@ -830,7 +827,8 @@ static int __init u300_gpio_probe(struct platform_device *pdev)
         return 0;
 
 err_no_range:
-        err = gpiochip_remove(&gpio->chip);
+        if (gpiochip_remove(&gpio->chip))
+                dev_err(&pdev->dev, "failed to remove gpio chip\n");
 err_no_chip:
 err_no_domain:
 err_no_port:
@@ -859,9 +857,15 @@ static int __exit u300_gpio_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id u300_gpio_match[] = {
+        { .compatible = "stericsson,gpio-coh901" },
+        {},
+};
+
 static struct platform_driver u300_gpio_driver = {
         .driver         = {
                 .name   = "u300-gpio",
+                .of_match_table = u300_gpio_match,
         },
         .remove         = __exit_p(u300_gpio_remove),
 };
diff --git a/drivers/pinctrl/pinctrl-exynos.c b/drivers/pinctrl/pinctrl-exynos.c
index ac742817ebce..2d76f66a2e0b 100644
--- a/drivers/pinctrl/pinctrl-exynos.c
+++ b/drivers/pinctrl/pinctrl-exynos.c
@@ -196,6 +196,12 @@ static irqreturn_t exynos_eint_gpio_irq(int irq, void *data)
         return IRQ_HANDLED;
 }
 
+struct exynos_eint_gpio_save {
+        u32 eint_con;
+        u32 eint_fltcon0;
+        u32 eint_fltcon1;
+};
+
 /*
  * exynos_eint_gpio_init() - setup handling of external gpio interrupts.
  * @d: driver data of samsung pinctrl driver.
@@ -204,8 +210,8 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
 {
         struct samsung_pin_bank *bank;
         struct device *dev = d->dev;
-        unsigned int ret;
-        unsigned int i;
+        int ret;
+        int i;
 
         if (!d->irq) {
                 dev_err(dev, "irq number not available\n");
@@ -227,11 +233,29 @@ static int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d)
                                 bank->nr_pins, &exynos_gpio_irqd_ops, bank);
                 if (!bank->irq_domain) {
                         dev_err(dev, "gpio irq domain add failed\n");
-                        return -ENXIO;
+                        ret = -ENXIO;
+                        goto err_domains;
+                }
+
+                bank->soc_priv = devm_kzalloc(d->dev,
+                        sizeof(struct exynos_eint_gpio_save), GFP_KERNEL);
+                if (!bank->soc_priv) {
+                        irq_domain_remove(bank->irq_domain);
+                        ret = -ENOMEM;
+                        goto err_domains;
                 }
         }
 
         return 0;
+
+err_domains:
+        for (--i, --bank; i >= 0; --i, --bank) {
+                if (bank->eint_type != EINT_TYPE_GPIO)
+                        continue;
+                irq_domain_remove(bank->irq_domain);
+        }
+
+        return ret;
 }
 
 static void exynos_wkup_irq_unmask(struct irq_data *irqd)
@@ -326,6 +350,28 @@ static int exynos_wkup_irq_set_type(struct irq_data *irqd, unsigned int type)
         return 0;
 }
 
+static u32 exynos_eint_wake_mask = 0xffffffff;
+
+u32 exynos_get_eint_wake_mask(void)
+{
+        return exynos_eint_wake_mask;
+}
+
+static int exynos_wkup_irq_set_wake(struct irq_data *irqd, unsigned int on)
+{
+        struct samsung_pin_bank *bank = irq_data_get_irq_chip_data(irqd);
+        unsigned long bit = 1UL << (2 * bank->eint_offset + irqd->hwirq);
+
+        pr_info("wake %s for irq %d\n", on ? "enabled" : "disabled", irqd->irq);
+
+        if (!on)
+                exynos_eint_wake_mask |= bit;
+        else
+                exynos_eint_wake_mask &= ~bit;
+
+        return 0;
+}
+
 /*
  * irq_chip for wakeup interrupts
  */
@@ -335,6 +381,7 @@ static struct irq_chip exynos_wkup_irq_chip = {
         .irq_mask       = exynos_wkup_irq_mask,
         .irq_ack        = exynos_wkup_irq_ack,
         .irq_set_type   = exynos_wkup_irq_set_type,
+        .irq_set_wake   = exynos_wkup_irq_set_wake,
 };
 
 /* interrupt handler for wakeup interrupts 0..15 */
@@ -505,6 +552,72 @@ static int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d)
         return 0;
 }
 
+static void exynos_pinctrl_suspend_bank(
+                                struct samsung_pinctrl_drv_data *drvdata,
+                                struct samsung_pin_bank *bank)
+{
+        struct exynos_eint_gpio_save *save = bank->soc_priv;
+        void __iomem *regs = drvdata->virt_base;
+
+        save->eint_con = readl(regs + EXYNOS_GPIO_ECON_OFFSET
+                                                + bank->eint_offset);
+        save->eint_fltcon0 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                                + 2 * bank->eint_offset);
+        save->eint_fltcon1 = readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                                + 2 * bank->eint_offset + 4);
+
+        pr_debug("%s: save     con %#010x\n", bank->name, save->eint_con);
+        pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0);
+        pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1);
+}
+
+static void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata)
+{
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        struct samsung_pin_bank *bank = ctrl->pin_banks;
+        int i;
+
+        for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+                if (bank->eint_type == EINT_TYPE_GPIO)
+                        exynos_pinctrl_suspend_bank(drvdata, bank);
+}
+
+static void exynos_pinctrl_resume_bank(
+                                struct samsung_pinctrl_drv_data *drvdata,
+                                struct samsung_pin_bank *bank)
+{
+        struct exynos_eint_gpio_save *save = bank->soc_priv;
+        void __iomem *regs = drvdata->virt_base;
+
+        pr_debug("%s:     con %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_ECON_OFFSET
+                        + bank->eint_offset), save->eint_con);
+        pr_debug("%s: fltcon0 %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                        + 2 * bank->eint_offset), save->eint_fltcon0);
+        pr_debug("%s: fltcon1 %#010x => %#010x\n", bank->name,
+                        readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                        + 2 * bank->eint_offset + 4), save->eint_fltcon1);
+
+        writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET
+                                                + bank->eint_offset);
+        writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                                + 2 * bank->eint_offset);
+        writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET
+                                                + 2 * bank->eint_offset + 4);
+}
+
+static void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata)
+{
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        struct samsung_pin_bank *bank = ctrl->pin_banks;
+        int i;
+
+        for (i = 0; i < ctrl->nr_banks; ++i, ++bank)
+                if (bank->eint_type == EINT_TYPE_GPIO)
+                        exynos_pinctrl_resume_bank(drvdata, bank);
+}
+
 /* pin banks of exynos4210 pin-controller 0 */
 static struct samsung_pin_bank exynos4210_pin_banks0[] = {
         EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
@@ -568,6 +681,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4210-gpio-ctrl0",
         }, {
                 /* pin-controller instance 1 data */
@@ -582,6 +697,8 @@ struct samsung_pin_ctrl exynos4210_pin_ctrl[] = {
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
                 .eint_wkup_init = exynos_eint_wkup_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4210-gpio-ctrl1",
         }, {
                 /* pin-controller instance 2 data */
@@ -663,6 +780,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4x12-gpio-ctrl0",
         }, {
                 /* pin-controller instance 1 data */
@@ -677,6 +796,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
                 .eint_wkup_init = exynos_eint_wkup_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4x12-gpio-ctrl1",
         }, {
                 /* pin-controller instance 2 data */
@@ -687,6 +808,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4x12-gpio-ctrl2",
         }, {
                 /* pin-controller instance 3 data */
@@ -697,6 +820,8 @@ struct samsung_pin_ctrl exynos4x12_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos4x12-gpio-ctrl3",
         },
 };
@@ -775,6 +900,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
                 .eint_wkup_init = exynos_eint_wkup_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos5250-gpio-ctrl0",
         }, {
                 /* pin-controller instance 1 data */
@@ -785,6 +912,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos5250-gpio-ctrl1",
         }, {
                 /* pin-controller instance 2 data */
@@ -795,6 +924,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos5250-gpio-ctrl2",
         }, {
                 /* pin-controller instance 3 data */
@@ -805,6 +936,8 @@ struct samsung_pin_ctrl exynos5250_pin_ctrl[] = {
                 .geint_pend     = EXYNOS_GPIO_EPEND_OFFSET,
                 .svc            = EXYNOS_SVC_OFFSET,
                 .eint_gpio_init = exynos_eint_gpio_init,
+                .suspend        = exynos_pinctrl_suspend,
+                .resume         = exynos_pinctrl_resume,
                 .label          = "exynos5250-gpio-ctrl3",
         },
 };
diff --git a/drivers/pinctrl/pinctrl-exynos.h b/drivers/pinctrl/pinctrl-exynos.h
index 9b1f77a5bf0f..3c91c357792f 100644
--- a/drivers/pinctrl/pinctrl-exynos.h
+++ b/drivers/pinctrl/pinctrl-exynos.h
@@ -19,6 +19,7 @@
 
 /* External GPIO and wakeup interrupt related definitions */
 #define EXYNOS_GPIO_ECON_OFFSET         0x700
+#define EXYNOS_GPIO_EFLTCON_OFFSET      0x800
 #define EXYNOS_GPIO_EMASK_OFFSET        0x900
 #define EXYNOS_GPIO_EPEND_OFFSET        0xA00
 #define EXYNOS_WKUP_ECON_OFFSET         0xE00
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 055d0162098b..63ac22e89678 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -28,6 +28,7 @@
 #include <linux/gpio.h>
 #include <linux/irqdomain.h>
 #include <linux/spinlock.h>
+#include <linux/syscore_ops.h>
 
 #include "core.h"
 #include "pinctrl-samsung.h"
@@ -48,6 +49,9 @@ static struct pin_config {
         { "samsung,pin-pud-pdn", PINCFG_TYPE_PUD_PDN },
 };
 
+/* Global list of devices (struct samsung_pinctrl_drv_data) */
+LIST_HEAD(drvdata_list);
+
 static unsigned int pin_base;
 
 static inline struct samsung_pin_bank *gc_to_pin_bank(struct gpio_chip *gc)
@@ -956,9 +960,151 @@ static int samsung_pinctrl_probe(struct platform_device *pdev)
                 ctrl->eint_wkup_init(drvdata);
 
         platform_set_drvdata(pdev, drvdata);
+
+        /* Add to the global list */
+        list_add_tail(&drvdata->node, &drvdata_list);
+
         return 0;
 }
 
+#ifdef CONFIG_PM
+
+/**
+ * samsung_pinctrl_suspend_dev - save pinctrl state for suspend for a device
+ *
+ * Save data for all banks handled by this device.
+ */
+static void samsung_pinctrl_suspend_dev(
+        struct samsung_pinctrl_drv_data *drvdata)
+{
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        void __iomem *virt_base = drvdata->virt_base;
+        int i;
+
+        for (i = 0; i < ctrl->nr_banks; i++) {
+                struct samsung_pin_bank *bank = &ctrl->pin_banks[i];
+                void __iomem *reg = virt_base + bank->pctl_offset;
+
+                u8 *offs = bank->type->reg_offset;
+                u8 *widths = bank->type->fld_width;
+                enum pincfg_type type;
+
+                /* Registers without a powerdown config aren't lost */
+                if (!widths[PINCFG_TYPE_CON_PDN])
+                        continue;
+
+                for (type = 0; type < PINCFG_TYPE_NUM; type++)
+                        if (widths[type])
+                                bank->pm_save[type] = readl(reg + offs[type]);
+
+                if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) {
+                        /* Some banks have two config registers */
+                        bank->pm_save[PINCFG_TYPE_NUM] =
+                                readl(reg + offs[PINCFG_TYPE_FUNC] + 4);
+                        pr_debug("Save %s @ %p (con %#010x %08x)\n",
+                                 bank->name, reg,
+                                 bank->pm_save[PINCFG_TYPE_FUNC],
+                                 bank->pm_save[PINCFG_TYPE_NUM]);
+                } else {
+                        pr_debug("Save %s @ %p (con %#010x)\n", bank->name,
+                                 reg, bank->pm_save[PINCFG_TYPE_FUNC]);
+                }
+        }
+
+        if (ctrl->suspend)
+                ctrl->suspend(drvdata);
+}
+
+/**
+ * samsung_pinctrl_resume_dev - restore pinctrl state from suspend for a device
+ *
+ * Restore one of the banks that was saved during suspend.
+ *
+ * We don't bother doing anything complicated to avoid glitching lines since
+ * we're called before pad retention is turned off.
+ */
+static void samsung_pinctrl_resume_dev(struct samsung_pinctrl_drv_data *drvdata)
+{
+        struct samsung_pin_ctrl *ctrl = drvdata->ctrl;
+        void __iomem *virt_base = drvdata->virt_base;
+        int i;
+
+        if (ctrl->resume)
+                ctrl->resume(drvdata);
+
+        for (i = 0; i < ctrl->nr_banks; i++) {
+                struct samsung_pin_bank *bank = &ctrl->pin_banks[i];
+                void __iomem *reg = virt_base + bank->pctl_offset;
+
+                u8 *offs = bank->type->reg_offset;
+                u8 *widths = bank->type->fld_width;
+                enum pincfg_type type;
+
+                /* Registers without a powerdown config aren't lost */
+                if (!widths[PINCFG_TYPE_CON_PDN])
+                        continue;
+
+                if (widths[PINCFG_TYPE_FUNC] * bank->nr_pins > 32) {
+                        /* Some banks have two config registers */
+                        pr_debug("%s @ %p (con %#010x %08x => %#010x %08x)\n",
+                                 bank->name, reg,
+                                 readl(reg + offs[PINCFG_TYPE_FUNC]),
+                                 readl(reg + offs[PINCFG_TYPE_FUNC] + 4),
+                                 bank->pm_save[PINCFG_TYPE_FUNC],
+                                 bank->pm_save[PINCFG_TYPE_NUM]);
+                        writel(bank->pm_save[PINCFG_TYPE_NUM],
+                               reg + offs[PINCFG_TYPE_FUNC] + 4);
+                } else {
+                        pr_debug("%s @ %p (con %#010x => %#010x)\n", bank->name,
+                                 reg, readl(reg + offs[PINCFG_TYPE_FUNC]),
+                                 bank->pm_save[PINCFG_TYPE_FUNC]);
+                }
+                for (type = 0; type < PINCFG_TYPE_NUM; type++)
+                        if (widths[type])
+                                writel(bank->pm_save[type], reg + offs[type]);
+        }
+}
+
+/**
+ * samsung_pinctrl_suspend - save pinctrl state for suspend
+ *
+ * Save data for all banks across all devices.
+ */
+static int samsung_pinctrl_suspend(void)
+{
+        struct samsung_pinctrl_drv_data *drvdata;
+
+        list_for_each_entry(drvdata, &drvdata_list, node) {
+                samsung_pinctrl_suspend_dev(drvdata);
+        }
+
+        return 0;
+}
+
+/**
+ * samsung_pinctrl_resume - restore pinctrl state for suspend
+ *
+ * Restore data for all banks across all devices.
+ */
+static void samsung_pinctrl_resume(void)
+{
+        struct samsung_pinctrl_drv_data *drvdata;
+
+        list_for_each_entry_reverse(drvdata, &drvdata_list, node) {
+                samsung_pinctrl_resume_dev(drvdata);
+        }
+}
+
+#else
+#define samsung_pinctrl_suspend         NULL
+#define samsung_pinctrl_resume          NULL
+#endif
+
+static struct syscore_ops samsung_pinctrl_syscore_ops = {
+        .suspend        = samsung_pinctrl_suspend,
+        .resume         = samsung_pinctrl_resume,
+};
+
 static const struct of_device_id samsung_pinctrl_dt_match[] = {
 #ifdef CONFIG_PINCTRL_EXYNOS
         { .compatible = "samsung,exynos4210-pinctrl",
@@ -987,6 +1133,14 @@ static struct platform_driver samsung_pinctrl_driver = {
 
 static int __init samsung_pinctrl_drv_register(void)
 {
+        /*
+         * Register syscore ops for save/restore of registers across suspend.
+         * It's important to ensure that this driver is running at an earlier
+         * initcall level than any arch-specific init calls that install syscore
+         * ops that turn off pad retention (like exynos_pm_resume).
+         */
+        register_syscore_ops(&samsung_pinctrl_syscore_ops);
+
         return platform_driver_register(&samsung_pinctrl_driver);
 }
 postcore_initcall(samsung_pinctrl_drv_register);
diff --git a/drivers/pinctrl/pinctrl-samsung.h b/drivers/pinctrl/pinctrl-samsung.h
index 7c7f9ebcd05b..26d3519240c9 100644
--- a/drivers/pinctrl/pinctrl-samsung.h
+++ b/drivers/pinctrl/pinctrl-samsung.h
@@ -127,6 +127,7 @@ struct samsung_pin_bank_type {
  * @gpio_chip: GPIO chip of the bank.
  * @grange: linux gpio pin range supported by this bank.
  * @slock: spinlock protecting bank registers
+ * @pm_save: saved register values during suspend
  */
 struct samsung_pin_bank {
         struct samsung_pin_bank_type *type;
@@ -138,12 +139,15 @@ struct samsung_pin_bank {
         u32             eint_mask;
         u32             eint_offset;
         char            *name;
+        void            *soc_priv;
         struct device_node *of_node;
         struct samsung_pinctrl_drv_data *drvdata;
         struct irq_domain *irq_domain;
         struct gpio_chip gpio_chip;
         struct pinctrl_gpio_range grange;
         spinlock_t slock;
+
+        u32 pm_save[PINCFG_TYPE_NUM + 1]; /* +1 to handle double CON registers*/
 };
 
 /**
@@ -184,11 +188,15 @@ struct samsung_pin_ctrl {
 
         int             (*eint_gpio_init)(struct samsung_pinctrl_drv_data *);
         int             (*eint_wkup_init)(struct samsung_pinctrl_drv_data *);
+        void            (*suspend)(struct samsung_pinctrl_drv_data *);
+        void            (*resume)(struct samsung_pinctrl_drv_data *);
+
         char            *label;
 };
 
 /**
  * struct samsung_pinctrl_drv_data: wrapper for holding driver data together.
+ * @node: global list node
  * @virt_base: register base address of the controller.
  * @dev: device instance representing the controller.
  * @irq: interrpt number used by the controller to notify gpio interrupts.
@@ -201,6 +209,7 @@ struct samsung_pin_ctrl {
  * @nr_function: number of such pin functions.
  */
 struct samsung_pinctrl_drv_data {
+        struct list_head                node;
         void __iomem                    *virt_base;
         struct device                   *dev;
         int                             irq;
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index c52fc2c08732..b7d8c890514c 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -1990,8 +1990,10 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
         }
 
         clk = devm_clk_get(&pdev->dev, NULL);
-        if (IS_ERR(clk))
+        if (IS_ERR(clk)) {
+                ret = PTR_ERR(clk);
                 goto gpiochip_error;
+        }
 
         clk_prepare_enable(clk);
 
@@ -2000,7 +2002,8 @@ static int sunxi_pinctrl_probe(struct platform_device *pdev)
         return 0;
 
 gpiochip_error:
-        ret = gpiochip_remove(pctl->chip);
+        if (gpiochip_remove(pctl->chip))
+                dev_err(&pdev->dev, "failed to remove gpio chip\n");
 pinctrl_error:
         pinctrl_unregister(pctl->pctl_dev);
         return ret;
diff --git a/drivers/pinctrl/pinctrl-u300.c b/drivers/pinctrl/pinctrl-u300.c
index 6a3a7503e6a0..06bfa09bb15c 100644
--- a/drivers/pinctrl/pinctrl-u300.c
+++ b/drivers/pinctrl/pinctrl-u300.c
@@ -1105,10 +1105,17 @@ static int u300_pmx_remove(struct platform_device *pdev)
         return 0;
 }
 
+static const struct of_device_id u300_pinctrl_match[] = {
+        { .compatible = "stericsson,pinctrl-u300" },
+        {},
+};
+
+
 static struct platform_driver u300_pmx_driver = {
         .driver = {
                 .name = DRIVER_NAME,
                 .owner = THIS_MODULE,
+                .of_match_table = u300_pinctrl_match,
         },
         .probe = u300_pmx_probe,
         .remove = u300_pmx_remove,
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index f8a2ae413c7f..636a882b406e 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -5,8 +5,6 @@
 if ARCH_SHMOBILE || SUPERH
 
 config PINCTRL_SH_PFC
-        # XXX move off the gpio dependency
-        depends on GPIOLIB
         select GPIO_SH_PFC if ARCH_REQUIRE_GPIOLIB
         select PINMUX
         select PINCONF
@@ -32,11 +30,21 @@ config PINCTRL_PFC_R8A7740
         depends on ARCH_R8A7740
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7778
+        def_bool y
+        depends on ARCH_R8A7778
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_R8A7779
         def_bool y
         depends on ARCH_R8A7779
         select PINCTRL_SH_PFC
 
+config PINCTRL_PFC_R8A7790
+        def_bool y
+        depends on ARCH_R8A7790
+        select PINCTRL_SH_PFC
+
 config PINCTRL_PFC_SH7203
         def_bool y
         depends on CPU_SUBTYPE_SH7203
@@ -64,6 +72,7 @@ config PINCTRL_PFC_SH73A0
         def_bool y
         depends on ARCH_SH73A0
         select PINCTRL_SH_PFC
+        select REGULATOR
 
 config PINCTRL_PFC_SH7720
         def_bool y
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 211cd8e98a8a..5e0c222c12d7 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -5,7 +5,9 @@ endif
 obj-$(CONFIG_PINCTRL_SH_PFC)    += sh-pfc.o
 obj-$(CONFIG_PINCTRL_PFC_R8A73A4)       += pfc-r8a73a4.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7740)       += pfc-r8a7740.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7778)       += pfc-r8a7778.o
 obj-$(CONFIG_PINCTRL_PFC_R8A7779)       += pfc-r8a7779.o
+obj-$(CONFIG_PINCTRL_PFC_R8A7790)       += pfc-r8a7790.o
 obj-$(CONFIG_PINCTRL_PFC_SH7203)        += pfc-sh7203.o
 obj-$(CONFIG_PINCTRL_PFC_SH7264)        += pfc-sh7264.o
 obj-$(CONFIG_PINCTRL_PFC_SH7269)        += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index b551336924a5..3b2fd43ff294 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -372,6 +372,12 @@ static int sh_pfc_probe(struct platform_device *pdev)
 
         spin_lock_init(&pfc->lock);
 
+        if (info->ops && info->ops->init) {
+                ret = info->ops->init(pfc);
+                if (ret < 0)
+                        return ret;
+        }
+
         pinctrl_provide_dummies();
 
         /*
@@ -379,7 +385,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
          */
         ret = sh_pfc_register_pinctrl(pfc);
         if (unlikely(ret != 0))
-                return ret;
+                goto error;
 
 #ifdef CONFIG_GPIO_SH_PFC
         /*
@@ -401,6 +407,11 @@ static int sh_pfc_probe(struct platform_device *pdev)
         dev_info(pfc->dev, "%s support registered\n", info->name);
 
         return 0;
+
+error:
+        if (info->ops && info->ops->exit)
+                info->ops->exit(pfc);
+        return ret;
 }
 
 static int sh_pfc_remove(struct platform_device *pdev)
@@ -412,6 +423,9 @@ static int sh_pfc_remove(struct platform_device *pdev)
 #endif
         sh_pfc_unregister_pinctrl(pfc);
 
+        if (pfc->info->ops && pfc->info->ops->exit)
+                pfc->info->ops->exit(pfc);
+
         platform_set_drvdata(pdev, NULL);
 
         return 0;
@@ -424,9 +438,15 @@ static const struct platform_device_id sh_pfc_id_table[] = {
 #ifdef CONFIG_PINCTRL_PFC_R8A7740
         { "pfc-r8a7740", (kernel_ulong_t)&r8a7740_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7778
+        { "pfc-r8a7778", (kernel_ulong_t)&r8a7778_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_R8A7779
         { "pfc-r8a7779", (kernel_ulong_t)&r8a7779_pinmux_info },
 #endif
+#ifdef CONFIG_PINCTRL_PFC_R8A7790
+        { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
+#endif
 #ifdef CONFIG_PINCTRL_PFC_SH7203
         { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
 #endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 89cb4289d761..f02ba1dde3a0 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -11,6 +11,7 @@
 #define __SH_PFC_CORE_H__
 
 #include <linux/compiler.h>
+#include <linux/spinlock.h>
 #include <linux/types.h>
 
 #include "sh_pfc.h"
@@ -27,6 +28,7 @@ struct sh_pfc_pinctrl;
 struct sh_pfc {
         struct device *dev;
         const struct sh_pfc_soc_info *info;
+        void *soc_data;
         spinlock_t lock;
 
         unsigned int num_windows;
@@ -56,7 +58,9 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type);
 
 extern const struct sh_pfc_soc_info r8a73a4_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
 extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
+extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
 extern const struct sh_pfc_soc_info sh7203_pinmux_info;
 extern const struct sh_pfc_soc_info sh7264_pinmux_info;
 extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bbd87d29bfd0..f6ea47c433b3 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -18,10 +18,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/r8a7740.h>
 #include <mach/irqs.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx)                                      \
@@ -30,6 +34,29 @@
         PORT_10(fn, pfx##20, sfx),                                      \
         PORT_1(fn, pfx##210, sfx),      PORT_1(fn, pfx##211, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)                                           \
+        [gpio] = {                                                      \
+                .name = __stringify(PORT##gpio),                        \
+                .enum_id = PORT##gpio##_DATA,                           \
+        }
+
+#define IRQC_PIN_MUX(irq, pin)                                          \
+static const unsigned int intc_irq##irq##_pins[] = {                    \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_mux[] = {                     \
+        IRQ##irq##_MARK,                                                \
+}
+
+#define IRQC_PINS_MUX(irq, idx, pin)                                    \
+static const unsigned int intc_irq##irq##_##idx##_pins[] = {            \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_##idx##_mux[] = {             \
+        IRQ##irq##_PORT##pin##_MARK,                                    \
+}
+
 enum {
         PINMUX_RESERVED = 0,
 
@@ -43,16 +70,6 @@ enum {
         PORT_ALL(IN),
         PINMUX_INPUT_END,
 
-        /* PORT0_IN_PU -> PORT211_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-
-        /* PORT0_IN_PD -> PORT211_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-
         /* PORT0_OUT -> PORT211_OUT */
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),
@@ -261,8 +278,6 @@ enum {
         SCIFB_CTS_PORT173_MARK,
 
         /* LCD0 */
-        LCDC0_SELECT_MARK,
-
         LCD0_D0_MARK,   LCD0_D1_MARK,   LCD0_D2_MARK,   LCD0_D3_MARK,
         LCD0_D4_MARK,   LCD0_D5_MARK,   LCD0_D6_MARK,   LCD0_D7_MARK,
         LCD0_D8_MARK,   LCD0_D9_MARK,   LCD0_D10_MARK,  LCD0_D11_MARK,
@@ -285,8 +300,6 @@ enum {
         LCD0_LCLK_PORT102_MARK,
 
         /* LCD1 */
-        LCDC1_SELECT_MARK,
-
         LCD1_D0_MARK,   LCD1_D1_MARK,   LCD1_D2_MARK,   LCD1_D3_MARK,
         LCD1_D4_MARK,   LCD1_D5_MARK,   LCD1_D6_MARK,   LCD1_D7_MARK,
         LCD1_D8_MARK,   LCD1_D9_MARK,   LCD1_D10_MARK,  LCD1_D11_MARK,
@@ -577,137 +590,11 @@ enum {
         PINMUX_MARK_END,
 };
 
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
+
 static const pinmux_enum_t pinmux_data[] = {
-        /* specify valid pin states for each pin in GPIO mode */
-
-        /* I/O and Pull U/D */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_IO_PD(2),             PORT_DATA_IO_PD(3),
-        PORT_DATA_IO_PD(4),             PORT_DATA_IO_PD(5),
-        PORT_DATA_IO_PD(6),             PORT_DATA_IO(7),
-        PORT_DATA_IO(8),                PORT_DATA_IO(9),
-
-        PORT_DATA_IO_PD(10),            PORT_DATA_IO_PD(11),
-        PORT_DATA_IO_PD(12),            PORT_DATA_IO_PU_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_IO_PD(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_IO(18),               PORT_DATA_IO_PU(19),
-
-        PORT_DATA_IO_PU_PD(20),         PORT_DATA_IO_PD(21),
-        PORT_DATA_IO_PU_PD(22),         PORT_DATA_IO(23),
-        PORT_DATA_IO_PU(24),            PORT_DATA_IO_PU(25),
-        PORT_DATA_IO_PU(26),            PORT_DATA_IO_PU(27),
-        PORT_DATA_IO_PU(28),            PORT_DATA_IO_PU(29),
-
-        PORT_DATA_IO_PU(30),            PORT_DATA_IO_PD(31),
-        PORT_DATA_IO_PD(32),            PORT_DATA_IO_PD(33),
-        PORT_DATA_IO_PD(34),            PORT_DATA_IO_PU(35),
-        PORT_DATA_IO_PU(36),            PORT_DATA_IO_PD(37),
-        PORT_DATA_IO_PU(38),            PORT_DATA_IO_PD(39),
-
-        PORT_DATA_IO_PU_PD(40),         PORT_DATA_IO_PD(41),
-        PORT_DATA_IO_PD(42),            PORT_DATA_IO_PU_PD(43),
-        PORT_DATA_IO_PU_PD(44),         PORT_DATA_IO_PU_PD(45),
-        PORT_DATA_IO_PU_PD(46),         PORT_DATA_IO_PU_PD(47),
-        PORT_DATA_IO_PU_PD(48),         PORT_DATA_IO_PU_PD(49),
-
-        PORT_DATA_IO_PU_PD(50),         PORT_DATA_IO_PD(51),
-        PORT_DATA_IO_PD(52),            PORT_DATA_IO_PD(53),
-        PORT_DATA_IO_PD(54),            PORT_DATA_IO_PU_PD(55),
-        PORT_DATA_IO_PU_PD(56),         PORT_DATA_IO_PU_PD(57),
-        PORT_DATA_IO_PU_PD(58),         PORT_DATA_IO_PU_PD(59),
-
-        PORT_DATA_IO_PU_PD(60),         PORT_DATA_IO_PD(61),
-        PORT_DATA_IO_PD(62),            PORT_DATA_IO_PD(63),
-        PORT_DATA_IO_PD(64),            PORT_DATA_IO_PD(65),
-        PORT_DATA_IO_PU_PD(66),         PORT_DATA_IO_PU_PD(67),
-        PORT_DATA_IO_PU_PD(68),         PORT_DATA_IO_PU_PD(69),
-
-        PORT_DATA_IO_PU_PD(70),         PORT_DATA_IO_PU_PD(71),
-        PORT_DATA_IO_PU_PD(72),         PORT_DATA_IO_PU_PD(73),
-        PORT_DATA_IO_PU_PD(74),         PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO(82),               PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO(84),               PORT_DATA_IO_PD(85),
-        PORT_DATA_IO_PD(86),            PORT_DATA_IO_PD(87),
-        PORT_DATA_IO_PD(88),            PORT_DATA_IO_PD(89),
-
-        PORT_DATA_IO_PD(90),            PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU_PD(96),         PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_IO_PU_PD(99),
-
-        PORT_DATA_IO_PU_PD(100),        PORT_DATA_IO(101),
-        PORT_DATA_IO_PU(102),           PORT_DATA_IO_PU_PD(103),
-        PORT_DATA_IO_PU(104),           PORT_DATA_IO_PU(105),
-        PORT_DATA_IO_PU_PD(106),        PORT_DATA_IO(107),
-        PORT_DATA_IO(108),              PORT_DATA_IO(109),
-
-        PORT_DATA_IO(110),              PORT_DATA_IO(111),
-        PORT_DATA_IO(112),              PORT_DATA_IO(113),
-        PORT_DATA_IO_PU_PD(114),        PORT_DATA_IO(115),
-        PORT_DATA_IO_PD(116),           PORT_DATA_IO_PD(117),
-        PORT_DATA_IO_PD(118),           PORT_DATA_IO_PD(119),
-
-        PORT_DATA_IO_PD(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO(125),
-        PORT_DATA_IO(126),              PORT_DATA_IO(127),
-        PORT_DATA_IO(128),              PORT_DATA_IO(129),
-
-        PORT_DATA_IO(130),              PORT_DATA_IO(131),
-        PORT_DATA_IO(132),              PORT_DATA_IO(133),
-        PORT_DATA_IO(134),              PORT_DATA_IO(135),
-        PORT_DATA_IO(136),              PORT_DATA_IO(137),
-        PORT_DATA_IO(138),              PORT_DATA_IO(139),
-
-        PORT_DATA_IO(140),              PORT_DATA_IO(141),
-        PORT_DATA_IO_PU(142),           PORT_DATA_IO_PU(143),
-        PORT_DATA_IO_PU(144),           PORT_DATA_IO_PU(145),
-        PORT_DATA_IO_PU(146),           PORT_DATA_IO_PU(147),
-        PORT_DATA_IO_PU(148),           PORT_DATA_IO_PU(149),
-
-        PORT_DATA_IO_PU(150),           PORT_DATA_IO_PU(151),
-        PORT_DATA_IO_PU(152),           PORT_DATA_IO_PU(153),
-        PORT_DATA_IO_PU(154),           PORT_DATA_IO_PU(155),
-        PORT_DATA_IO_PU(156),           PORT_DATA_IO_PU(157),
-        PORT_DATA_IO_PD(158),           PORT_DATA_IO_PD(159),
-
-        PORT_DATA_IO_PU_PD(160),        PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_IO_PD(164),           PORT_DATA_IO_PD(165),
-        PORT_DATA_IO_PU(166),           PORT_DATA_IO_PU(167),
-        PORT_DATA_IO_PU(168),           PORT_DATA_IO_PU(169),
-
-        PORT_DATA_IO_PU(170),           PORT_DATA_IO_PU(171),
-        PORT_DATA_IO_PD(172),           PORT_DATA_IO_PD(173),
-        PORT_DATA_IO_PD(174),           PORT_DATA_IO_PD(175),
-        PORT_DATA_IO_PU(176),           PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU(178),           PORT_DATA_IO_PD(179),
-
-        PORT_DATA_IO_PD(180),           PORT_DATA_IO_PU(181),
-        PORT_DATA_IO_PU(182),           PORT_DATA_IO(183),
-        PORT_DATA_IO_PD(184),           PORT_DATA_IO_PD(185),
-        PORT_DATA_IO_PD(186),           PORT_DATA_IO_PD(187),
-        PORT_DATA_IO_PD(188),           PORT_DATA_IO_PD(189),
-
-        PORT_DATA_IO_PD(190),           PORT_DATA_IO_PD(191),
-        PORT_DATA_IO_PD(192),           PORT_DATA_IO_PU_PD(193),
-        PORT_DATA_IO_PU_PD(194),        PORT_DATA_IO_PD(195),
-        PORT_DATA_IO_PU_PD(196),        PORT_DATA_IO_PD(197),
-        PORT_DATA_IO_PU_PD(198),        PORT_DATA_IO_PU_PD(199),
-
-        PORT_DATA_IO_PU_PD(200),        PORT_DATA_IO_PU(201),
-        PORT_DATA_IO_PU_PD(202),        PORT_DATA_IO(203),
-        PORT_DATA_IO_PU_PD(204),        PORT_DATA_IO_PU_PD(205),
-        PORT_DATA_IO_PU_PD(206),        PORT_DATA_IO_PU_PD(207),
-        PORT_DATA_IO_PU_PD(208),        PORT_DATA_IO_PD(209),
-
-        PORT_DATA_IO_PD(210),           PORT_DATA_IO_PD(211),
+        PINMUX_DATA_GP_ALL(),
 
         /* Port0 */
         PINMUX_DATA(DBGMDT2_MARK,               PORT0_FN1),
@@ -986,7 +873,7 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQ27_PORT57_MARK,          PORT57_FN0,     MSEL1CR_27_1),
 
         /* Port58 */
-        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1),
+        PINMUX_DATA(LCD0_D0_MARK,               PORT58_FN1,     MSEL3CR_6_0),
         PINMUX_DATA(KEYOUT7_MARK,               PORT58_FN3),
         PINMUX_DATA(KEYIN0_PORT58_MARK,         PORT58_FN4,     MSEL4CR_18_1),
         PINMUX_DATA(DV_D0_MARK,                 PORT58_FN6),
@@ -1633,10 +1520,6 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(IRQ16_PORT211_MARK,         PORT211_FN0,    MSEL1CR_16_1),
         PINMUX_DATA(HDMI_CEC_MARK,              PORT211_FN1),
 
-        /* LCDC select */
-        PINMUX_DATA(LCDC0_SELECT_MARK,                          MSEL3CR_6_0),
-        PINMUX_DATA(LCDC1_SELECT_MARK,                          MSEL3CR_6_1),
-
         /* SDENC */
         PINMUX_DATA(SDENC_CPG_MARK,                             MSEL4CR_19_0),
         PINMUX_DATA(SDENC_DV_CLKI_MARK,                         MSEL4CR_19_1),
@@ -1654,9 +1537,565 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK,                    MSEL5CR_30_1,   MSEL5CR_29_0),
 };
 
+#define R8A7740_PIN(pin, cfgs)                                          \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define R8A7740_PIN_I_PD(pin)           R8A7740_PIN(pin, __I | __PD)
+#define R8A7740_PIN_I_PU(pin)           R8A7740_PIN(pin, __I | __PU)
+#define R8A7740_PIN_I_PU_PD(pin)                R8A7740_PIN(pin, __I | __PUD)
+#define R8A7740_PIN_IO(pin)             R8A7740_PIN(pin, __IO)
+#define R8A7740_PIN_IO_PD(pin)          R8A7740_PIN(pin, __IO | __PD)
+#define R8A7740_PIN_IO_PU(pin)          R8A7740_PIN(pin, __IO | __PU)
+#define R8A7740_PIN_IO_PU_PD(pin)       R8A7740_PIN(pin, __IO | __PUD)
+#define R8A7740_PIN_O(pin)              R8A7740_PIN(pin, __O)
+#define R8A7740_PIN_O_PU_PD(pin)                R8A7740_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-        GPIO_PORT_ALL(),
+        /* Table 56-1 (I/O and Pull U/D) */
+        R8A7740_PIN_IO_PD(0),           R8A7740_PIN_IO_PD(1),
+        R8A7740_PIN_IO_PD(2),           R8A7740_PIN_IO_PD(3),
+        R8A7740_PIN_IO_PD(4),           R8A7740_PIN_IO_PD(5),
+        R8A7740_PIN_IO_PD(6),           R8A7740_PIN_IO(7),
+        R8A7740_PIN_IO(8),              R8A7740_PIN_IO(9),
+        R8A7740_PIN_IO_PD(10),          R8A7740_PIN_IO_PD(11),
+        R8A7740_PIN_IO_PD(12),          R8A7740_PIN_IO_PU_PD(13),
+        R8A7740_PIN_IO_PD(14),          R8A7740_PIN_IO_PD(15),
+        R8A7740_PIN_IO_PD(16),          R8A7740_PIN_IO_PD(17),
+        R8A7740_PIN_IO(18),             R8A7740_PIN_IO_PU(19),
+        R8A7740_PIN_IO_PU_PD(20),       R8A7740_PIN_IO_PD(21),
+        R8A7740_PIN_IO_PU_PD(22),       R8A7740_PIN_IO(23),
+        R8A7740_PIN_IO_PU(24),          R8A7740_PIN_IO_PU(25),
+        R8A7740_PIN_IO_PU(26),          R8A7740_PIN_IO_PU(27),
+        R8A7740_PIN_IO_PU(28),          R8A7740_PIN_IO_PU(29),
+        R8A7740_PIN_IO_PU(30),          R8A7740_PIN_IO_PD(31),
+        R8A7740_PIN_IO_PD(32),          R8A7740_PIN_IO_PD(33),
+        R8A7740_PIN_IO_PD(34),          R8A7740_PIN_IO_PU(35),
+        R8A7740_PIN_IO_PU(36),          R8A7740_PIN_IO_PD(37),
+        R8A7740_PIN_IO_PU(38),          R8A7740_PIN_IO_PD(39),
+        R8A7740_PIN_IO_PU_PD(40),       R8A7740_PIN_IO_PD(41),
+        R8A7740_PIN_IO_PD(42),          R8A7740_PIN_IO_PU_PD(43),
+        R8A7740_PIN_IO_PU_PD(44),       R8A7740_PIN_IO_PU_PD(45),
+        R8A7740_PIN_IO_PU_PD(46),       R8A7740_PIN_IO_PU_PD(47),
+        R8A7740_PIN_IO_PU_PD(48),       R8A7740_PIN_IO_PU_PD(49),
+        R8A7740_PIN_IO_PU_PD(50),       R8A7740_PIN_IO_PD(51),
+        R8A7740_PIN_IO_PD(52),          R8A7740_PIN_IO_PD(53),
+        R8A7740_PIN_IO_PD(54),          R8A7740_PIN_IO_PU_PD(55),
+        R8A7740_PIN_IO_PU_PD(56),       R8A7740_PIN_IO_PU_PD(57),
+        R8A7740_PIN_IO_PU_PD(58),       R8A7740_PIN_IO_PU_PD(59),
+        R8A7740_PIN_IO_PU_PD(60),       R8A7740_PIN_IO_PD(61),
+        R8A7740_PIN_IO_PD(62),          R8A7740_PIN_IO_PD(63),
+        R8A7740_PIN_IO_PD(64),          R8A7740_PIN_IO_PD(65),
+        R8A7740_PIN_IO_PU_PD(66),       R8A7740_PIN_IO_PU_PD(67),
+        R8A7740_PIN_IO_PU_PD(68),       R8A7740_PIN_IO_PU_PD(69),
+        R8A7740_PIN_IO_PU_PD(70),       R8A7740_PIN_IO_PU_PD(71),
+        R8A7740_PIN_IO_PU_PD(72),       R8A7740_PIN_IO_PU_PD(73),
+        R8A7740_PIN_IO_PU_PD(74),       R8A7740_PIN_IO_PU_PD(75),
+        R8A7740_PIN_IO_PU_PD(76),       R8A7740_PIN_IO_PU_PD(77),
+        R8A7740_PIN_IO_PU_PD(78),       R8A7740_PIN_IO_PU_PD(79),
+        R8A7740_PIN_IO_PU_PD(80),       R8A7740_PIN_IO_PU_PD(81),
+        R8A7740_PIN_IO(82),             R8A7740_PIN_IO_PU_PD(83),
+        R8A7740_PIN_IO(84),             R8A7740_PIN_IO_PD(85),
+        R8A7740_PIN_IO_PD(86),          R8A7740_PIN_IO_PD(87),
+        R8A7740_PIN_IO_PD(88),          R8A7740_PIN_IO_PD(89),
+        R8A7740_PIN_IO_PD(90),          R8A7740_PIN_IO_PU_PD(91),
+        R8A7740_PIN_IO_PU_PD(92),       R8A7740_PIN_IO_PU_PD(93),
+        R8A7740_PIN_IO_PU_PD(94),       R8A7740_PIN_IO_PU_PD(95),
+        R8A7740_PIN_IO_PU_PD(96),       R8A7740_PIN_IO_PU_PD(97),
+        R8A7740_PIN_IO_PU_PD(98),       R8A7740_PIN_IO_PU_PD(99),
+        R8A7740_PIN_IO_PU_PD(100),      R8A7740_PIN_IO(101),
+        R8A7740_PIN_IO_PU(102),         R8A7740_PIN_IO_PU_PD(103),
+        R8A7740_PIN_IO_PU(104),         R8A7740_PIN_IO_PU(105),
+        R8A7740_PIN_IO_PU_PD(106),      R8A7740_PIN_IO(107),
+        R8A7740_PIN_IO(108),            R8A7740_PIN_IO(109),
+        R8A7740_PIN_IO(110),            R8A7740_PIN_IO(111),
+        R8A7740_PIN_IO(112),            R8A7740_PIN_IO(113),
+        R8A7740_PIN_IO_PU_PD(114),      R8A7740_PIN_IO(115),
+        R8A7740_PIN_IO_PD(116),         R8A7740_PIN_IO_PD(117),
+        R8A7740_PIN_IO_PD(118),         R8A7740_PIN_IO_PD(119),
+        R8A7740_PIN_IO_PD(120),         R8A7740_PIN_IO_PD(121),
+        R8A7740_PIN_IO_PD(122),         R8A7740_PIN_IO_PD(123),
+        R8A7740_PIN_IO_PD(124),         R8A7740_PIN_IO(125),
+        R8A7740_PIN_IO(126),            R8A7740_PIN_IO(127),
+        R8A7740_PIN_IO(128),            R8A7740_PIN_IO(129),
+        R8A7740_PIN_IO(130),            R8A7740_PIN_IO(131),
+        R8A7740_PIN_IO(132),            R8A7740_PIN_IO(133),
+        R8A7740_PIN_IO(134),            R8A7740_PIN_IO(135),
+        R8A7740_PIN_IO(136),            R8A7740_PIN_IO(137),
+        R8A7740_PIN_IO(138),            R8A7740_PIN_IO(139),
+        R8A7740_PIN_IO(140),            R8A7740_PIN_IO(141),
+        R8A7740_PIN_IO_PU(142),         R8A7740_PIN_IO_PU(143),
+        R8A7740_PIN_IO_PU(144),         R8A7740_PIN_IO_PU(145),
+        R8A7740_PIN_IO_PU(146),         R8A7740_PIN_IO_PU(147),
+        R8A7740_PIN_IO_PU(148),         R8A7740_PIN_IO_PU(149),
+        R8A7740_PIN_IO_PU(150),         R8A7740_PIN_IO_PU(151),
+        R8A7740_PIN_IO_PU(152),         R8A7740_PIN_IO_PU(153),
+        R8A7740_PIN_IO_PU(154),         R8A7740_PIN_IO_PU(155),
+        R8A7740_PIN_IO_PU(156),         R8A7740_PIN_IO_PU(157),
+        R8A7740_PIN_IO_PD(158),         R8A7740_PIN_IO_PD(159),
+        R8A7740_PIN_IO_PU_PD(160),      R8A7740_PIN_IO_PD(161),
+        R8A7740_PIN_IO_PD(162),         R8A7740_PIN_IO_PD(163),
+        R8A7740_PIN_IO_PD(164),         R8A7740_PIN_IO_PD(165),
+        R8A7740_PIN_IO_PU(166),         R8A7740_PIN_IO_PU(167),
+        R8A7740_PIN_IO_PU(168),         R8A7740_PIN_IO_PU(169),
+        R8A7740_PIN_IO_PU(170),         R8A7740_PIN_IO_PU(171),
+        R8A7740_PIN_IO_PD(172),         R8A7740_PIN_IO_PD(173),
+        R8A7740_PIN_IO_PD(174),         R8A7740_PIN_IO_PD(175),
+        R8A7740_PIN_IO_PU(176),         R8A7740_PIN_IO_PU_PD(177),
+        R8A7740_PIN_IO_PU(178),         R8A7740_PIN_IO_PD(179),
+        R8A7740_PIN_IO_PD(180),         R8A7740_PIN_IO_PU(181),
+        R8A7740_PIN_IO_PU(182),         R8A7740_PIN_IO(183),
+        R8A7740_PIN_IO_PD(184),         R8A7740_PIN_IO_PD(185),
+        R8A7740_PIN_IO_PD(186),         R8A7740_PIN_IO_PD(187),
+        R8A7740_PIN_IO_PD(188),         R8A7740_PIN_IO_PD(189),
+        R8A7740_PIN_IO_PD(190),         R8A7740_PIN_IO_PD(191),
+        R8A7740_PIN_IO_PD(192),         R8A7740_PIN_IO_PU_PD(193),
+        R8A7740_PIN_IO_PU_PD(194),      R8A7740_PIN_IO_PD(195),
+        R8A7740_PIN_IO_PU_PD(196),      R8A7740_PIN_IO_PD(197),
+        R8A7740_PIN_IO_PU_PD(198),      R8A7740_PIN_IO_PU_PD(199),
+        R8A7740_PIN_IO_PU_PD(200),      R8A7740_PIN_IO_PU(201),
+        R8A7740_PIN_IO_PU_PD(202),      R8A7740_PIN_IO(203),
+        R8A7740_PIN_IO_PU_PD(204),      R8A7740_PIN_IO_PU_PD(205),
+        R8A7740_PIN_IO_PU_PD(206),      R8A7740_PIN_IO_PU_PD(207),
+        R8A7740_PIN_IO_PU_PD(208),      R8A7740_PIN_IO_PD(209),
+        R8A7740_PIN_IO_PD(210),         R8A7740_PIN_IO_PD(211),
+};
+
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+        /* D[0:7] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+};
+static const unsigned int bsc_data8_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+        /* D[0:15] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+        149, 148, 147, 146, 145, 144, 143, 142,
+};
+static const unsigned int bsc_data16_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_data32_pins[] = {
+        /* D[0:31] */
+        157, 156, 155, 154, 153, 152, 151, 150,
+        149, 148, 147, 146, 145, 144, 143, 142,
+        171, 170, 169, 168, 167, 166, 173, 172,
+        165, 164, 163, 162, 161, 160, 159, 158,
+};
+static const unsigned int bsc_data32_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+        D16_MARK, D17_MARK, D18_MARK, D19_MARK,
+        D20_MARK, D21_MARK, D22_MARK, D23_MARK,
+        D24_MARK, D25_MARK, D26_MARK, D27_MARK,
+        D28_MARK, D29_MARK, D30_MARK, D31_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+        /* CS */
+        109,
+};
+static const unsigned int bsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+        /* CS */
+        110,
+};
+static const unsigned int bsc_cs2_mux[] = {
+        CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        111,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4_MARK,
+};
+static const unsigned int bsc_cs5a_0_pins[] = {
+        /* CS */
+        105,
+};
+static const unsigned int bsc_cs5a_0_mux[] = {
+        CS5A_PORT105_MARK,
+};
+static const unsigned int bsc_cs5a_1_pins[] = {
+        /* CS */
+        19,
+};
+static const unsigned int bsc_cs5a_1_mux[] = {
+        CS5A_PORT19_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+        /* CS */
+        103,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+        CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+        /* CS */
+        104,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+        CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+        /* RD, WE[0] */
+        115, 113,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+        /* RD, WE[0:1] */
+        115, 113, 112,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_rd_we32_pins[] = {
+        /* RD, WE[0:3] */
+        115, 113, 112, 108, 107,
+};
+static const unsigned int bsc_rd_we32_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+        /* BS */
+        175,
+};
+static const unsigned int bsc_bs_mux[] = {
+        BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+        /* RDWR */
+        114,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+        RDWR_MARK,
+};
+/* - CEU0 ------------------------------------------------------------------- */
+static const unsigned int ceu0_data_0_7_pins[] = {
+        /* D[0:7] */
+        34, 33, 32, 31, 30, 29, 28, 27,
+};
+static const unsigned int ceu0_data_0_7_mux[] = {
+        VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
+        VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
+};
+static const unsigned int ceu0_data_8_15_0_pins[] = {
+        /* D[8:15] */
+        182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu0_data_8_15_0_mux[] = {
+        VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+        VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
+        VIO0_D15_PORT24_MARK,
+};
+static const unsigned int ceu0_data_8_15_1_pins[] = {
+        /* D[8:15] */
+        182, 181, 180, 179, 178, 22, 95, 96,
+};
+static const unsigned int ceu0_data_8_15_1_mux[] = {
+        VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
+        VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
+        VIO0_D15_PORT96_MARK,
+};
+static const unsigned int ceu0_clk_0_pins[] = {
+        /* CKO */
+        36,
+};
+static const unsigned int ceu0_clk_0_mux[] = {
+        VIO_CKO_MARK,
+};
+static const unsigned int ceu0_clk_1_pins[] = {
+        /* CKO */
+        14,
+};
+static const unsigned int ceu0_clk_1_mux[] = {
+        VIO_CKO1_MARK,
+};
+static const unsigned int ceu0_clk_2_pins[] = {
+        /* CKO */
+        15,
+};
+static const unsigned int ceu0_clk_2_mux[] = {
+        VIO_CKO2_MARK,
+};
+static const unsigned int ceu0_sync_pins[] = {
+        /* CLK, VD, HD */
+        35, 39, 37,
+};
+static const unsigned int ceu0_sync_mux[] = {
+        VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
+};
+static const unsigned int ceu0_field_pins[] = {
+        /* FIELD */
+        38,
+};
+static const unsigned int ceu0_field_mux[] = {
+        VIO0_FIELD_MARK,
+};
+/* - CEU1 ------------------------------------------------------------------- */
+static const unsigned int ceu1_data_pins[] = {
+        /* D[0:7] */
+        182, 181, 180, 179, 178, 26, 25, 24,
+};
+static const unsigned int ceu1_data_mux[] = {
+        VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
+        VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
+};
+static const unsigned int ceu1_clk_pins[] = {
+        /* CKO */
+        23,
+};
+static const unsigned int ceu1_clk_mux[] = {
+        VIO_CKO_1_MARK,
+};
+static const unsigned int ceu1_sync_pins[] = {
+        /* CLK, VD, HD */
+        197, 198, 160,
+};
+static const unsigned int ceu1_sync_mux[] = {
+        VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
+};
+static const unsigned int ceu1_field_pins[] = {
+        /* FIELD */
+        21,
+};
+static const unsigned int ceu1_field_mux[] = {
+        VIO1_FIELD_MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        11,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        10,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        12, 13,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        7, 8,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_0_pins[] = {
+        /* ISLD */
+        0,
 };
+static const unsigned int fsia_data_in_0_mux[] = {
+        FSIAISLD_PORT0_MARK,
+};
+static const unsigned int fsia_data_in_1_pins[] = {
+        /* ISLD */
+        5,
+};
+static const unsigned int fsia_data_in_1_mux[] = {
+        FSIAISLD_PORT5_MARK,
+};
+static const unsigned int fsia_data_out_0_pins[] = {
+        /* OSLD */
+        9,
+};
+static const unsigned int fsia_data_out_0_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_data_out_1_pins[] = {
+        /* OSLD */
+        0,
+};
+static const unsigned int fsia_data_out_1_mux[] = {
+        FSIAOSLD1_MARK,
+};
+static const unsigned int fsia_data_out_2_pins[] = {
+        /* OSLD */
+        1,
+};
+static const unsigned int fsia_data_out_2_mux[] = {
+        FSIAOSLD2_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+        /* SPDIF */
+        9,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+        FSIASPDIF_PORT9_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+        /* SPDIF */
+        18,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+        FSIASPDIF_PORT18_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        11,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+/* - GETHER ----------------------------------------------------------------- */
+static const unsigned int gether_rmii_pins[] = {
+        /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
+        195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
+};
+static const unsigned int gether_rmii_mux[] = {
+        RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
+        RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
+        RMII_MDC_MARK, RMII_MDIO_MARK,
+};
+static const unsigned int gether_mii_pins[] = {
+        /* RXD[0:3], RX_CLK, RX_DV, RX_ER
+         * TXD[0:3], TX_CLK, TX_EN, TX_ER
+         * CRS, COL, MDC, MDIO,
+         */
+        185, 186, 187, 188, 174, 161, 204,
+        171, 170, 169, 168, 184, 183, 203,
+        205, 163, 206, 207,
+};
+static const unsigned int gether_mii_mux[] = {
+        ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+        ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+        ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+        ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+        ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+};
+static const unsigned int gether_gmii_pins[] = {
+        /* RXD[0:7], RX_CLK, RX_DV, RX_ER
+         * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
+         * CRS, COL, MDC, MDIO, REF125CK_MARK,
+         */
+        185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
+        171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
+        205, 163, 206, 207,
+};
+static const unsigned int gether_gmii_mux[] = {
+        ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
+        ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
+        ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
+        ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
+        ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
+        ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
+        ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
+        RMII_REF125CK_MARK,
+};
+static const unsigned int gether_int_pins[] = {
+        /* PHY_INT */
+        164,
+};
+static const unsigned int gether_int_mux[] = {
+        ET_PHY_INT_MARK,
+};
+static const unsigned int gether_link_pins[] = {
+        /* LINK */
+        177,
+};
+static const unsigned int gether_link_mux[] = {
+        ET_LINK_MARK,
+};
+static const unsigned int gether_wol_pins[] = {
+        /* WOL */
+        175,
+};
+static const unsigned int gether_wol_mux[] = {
+        ET_WOL_MARK,
+};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+        /* HPD, CEC */
+        210, 211,
+};
+static const unsigned int hdmi_mux[] = {
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 0, 2);
+IRQC_PINS_MUX(0, 1, 13);
+IRQC_PIN_MUX(1, 20);
+IRQC_PINS_MUX(2, 0, 11);
+IRQC_PINS_MUX(2, 1, 12);
+IRQC_PINS_MUX(3, 0, 10);
+IRQC_PINS_MUX(3, 1, 14);
+IRQC_PINS_MUX(4, 0, 15);
+IRQC_PINS_MUX(4, 1, 172);
+IRQC_PINS_MUX(5, 0, 0);
+IRQC_PINS_MUX(5, 1, 1);
+IRQC_PINS_MUX(6, 0, 121);
+IRQC_PINS_MUX(6, 1, 173);
+IRQC_PINS_MUX(7, 0, 120);
+IRQC_PINS_MUX(7, 1, 209);
+IRQC_PIN_MUX(8, 119);
+IRQC_PINS_MUX(9, 0, 118);
+IRQC_PINS_MUX(9, 1, 210);
+IRQC_PIN_MUX(10, 19);
+IRQC_PIN_MUX(11, 104);
+IRQC_PINS_MUX(12, 0, 42);
+IRQC_PINS_MUX(12, 1, 97);
+IRQC_PINS_MUX(13, 0, 64);
+IRQC_PINS_MUX(13, 1, 98);
+IRQC_PINS_MUX(14, 0, 63);
+IRQC_PINS_MUX(14, 1, 99);
+IRQC_PINS_MUX(15, 0, 62);
+IRQC_PINS_MUX(15, 1, 100);
+IRQC_PINS_MUX(16, 0, 68);
+IRQC_PINS_MUX(16, 1, 211);
+IRQC_PIN_MUX(17, 69);
+IRQC_PIN_MUX(18, 70);
+IRQC_PIN_MUX(19, 71);
+IRQC_PIN_MUX(20, 67);
+IRQC_PIN_MUX(21, 202);
+IRQC_PIN_MUX(22, 95);
+IRQC_PIN_MUX(23, 96);
+IRQC_PIN_MUX(24, 180);
+IRQC_PIN_MUX(25, 38);
+IRQC_PINS_MUX(26, 0, 58);
+IRQC_PINS_MUX(26, 1, 81);
+IRQC_PINS_MUX(27, 0, 57);
+IRQC_PINS_MUX(27, 1, 168);
+IRQC_PINS_MUX(28, 0, 56);
+IRQC_PINS_MUX(28, 1, 169);
+IRQC_PINS_MUX(29, 0, 50);
+IRQC_PINS_MUX(29, 1, 170);
+IRQC_PINS_MUX(30, 0, 49);
+IRQC_PINS_MUX(30, 1, 171);
+IRQC_PINS_MUX(31, 0, 41);
+IRQC_PINS_MUX(31, 1, 167);
 
 /* - LCD0 ------------------------------------------------------------------- */
 static const unsigned int lcd0_data8_pins[] = {
@@ -1930,6 +2369,260 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
         MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        197, 198,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        188,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        194, 193,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        195, 196,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        185,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        23, 21,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        200, 201,
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_0_pins[] = {
+        /* SCK */
+        22,
+};
+static const unsigned int scifa2_clk_0_mux[] = {
+        SCIFA2_SCK_PORT22_MARK,
+};
+static const unsigned int scifa2_clk_1_pins[] = {
+        /* SCK */
+        199,
+};
+static const unsigned int scifa2_clk_1_mux[] = {
+        SCIFA2_SCK_PORT199_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        96, 95,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_0_pins[] = {
+        /* RXD, TXD */
+        174, 175,
+};
+static const unsigned int scifa3_data_0_mux[] = {
+        SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
+};
+static const unsigned int scifa3_clk_0_pins[] = {
+        /* SCK */
+        116,
+};
+static const unsigned int scifa3_clk_0_mux[] = {
+        SCIFA3_SCK_PORT116_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        105, 117,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+        SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
+};
+static const unsigned int scifa3_data_1_pins[] = {
+        /* RXD, TXD */
+        159, 160,
+};
+static const unsigned int scifa3_data_1_mux[] = {
+        SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
+};
+static const unsigned int scifa3_clk_1_pins[] = {
+        /* SCK */
+        158,
+};
+static const unsigned int scifa3_clk_1_mux[] = {
+        SCIFA3_SCK_PORT158_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        161, 162,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+        SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_0_pins[] = {
+        /* RXD, TXD */
+        12, 13,
+};
+static const unsigned int scifa4_data_0_mux[] = {
+        SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
+};
+static const unsigned int scifa4_data_1_pins[] = {
+        /* RXD, TXD */
+        204, 203,
+};
+static const unsigned int scifa4_data_1_mux[] = {
+        SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
+};
+static const unsigned int scifa4_data_2_pins[] = {
+        /* RXD, TXD */
+        94, 93,
+};
+static const unsigned int scifa4_data_2_mux[] = {
+        SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
+};
+static const unsigned int scifa4_clk_0_pins[] = {
+        /* SCK */
+        21,
+};
+static const unsigned int scifa4_clk_0_mux[] = {
+        SCIFA4_SCK_PORT21_MARK,
+};
+static const unsigned int scifa4_clk_1_pins[] = {
+        /* SCK */
+        205,
+};
+static const unsigned int scifa4_clk_1_mux[] = {
+        SCIFA4_SCK_PORT205_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_0_pins[] = {
+        /* RXD, TXD */
+        10, 20,
+};
+static const unsigned int scifa5_data_0_mux[] = {
+        SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
+};
+static const unsigned int scifa5_data_1_pins[] = {
+        /* RXD, TXD */
+        207, 208,
+};
+static const unsigned int scifa5_data_1_mux[] = {
+        SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
+};
+static const unsigned int scifa5_data_2_pins[] = {
+        /* RXD, TXD */
+        92, 91,
+};
+static const unsigned int scifa5_data_2_mux[] = {
+        SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
+};
+static const unsigned int scifa5_clk_0_pins[] = {
+        /* SCK */
+        23,
+};
+static const unsigned int scifa5_clk_0_mux[] = {
+        SCIFA5_SCK_PORT23_MARK,
+};
+static const unsigned int scifa5_clk_1_pins[] = {
+        /* SCK */
+        206,
+};
+static const unsigned int scifa5_clk_1_mux[] = {
+        SCIFA5_SCK_PORT206_MARK,
+};
+/* - SCIFA6 ----------------------------------------------------------------- */
+static const unsigned int scifa6_data_pins[] = {
+        /* RXD, TXD */
+        25, 26,
+};
+static const unsigned int scifa6_data_mux[] = {
+        SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
+};
+static const unsigned int scifa6_clk_pins[] = {
+        /* SCK */
+        24,
+};
+static const unsigned int scifa6_clk_mux[] = {
+        SCIFA6_SCK_MARK,
+};
+/* - SCIFA7 ----------------------------------------------------------------- */
+static const unsigned int scifa7_data_pins[] = {
+        /* RXD, TXD */
+        0, 1,
+};
+static const unsigned int scifa7_data_mux[] = {
+        SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_0_pins[] = {
+        /* RXD, TXD */
+        191, 192,
+};
+static const unsigned int scifb_data_0_mux[] = {
+        SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
+};
+static const unsigned int scifb_clk_0_pins[] = {
+        /* SCK */
+        190,
+};
+static const unsigned int scifb_clk_0_mux[] = {
+        SCIFB_SCK_PORT190_MARK,
+};
+static const unsigned int scifb_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        186, 187,
+};
+static const unsigned int scifb_ctrl_0_mux[] = {
+        SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
+};
+static const unsigned int scifb_data_1_pins[] = {
+        /* RXD, TXD */
+        3, 4,
+};
+static const unsigned int scifb_data_1_mux[] = {
+        SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
+};
+static const unsigned int scifb_clk_1_pins[] = {
+        /* SCK */
+        2,
+};
+static const unsigned int scifb_clk_1_mux[] = {
+        SCIFB_SCK_PORT2_MARK,
+};
+static const unsigned int scifb_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        172, 173,
+};
+static const unsigned int scifb_ctrl_1_mux[] = {
+        SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
@@ -2052,8 +2745,141 @@ static const unsigned int sdhi2_wp_1_pins[] = {
 static const unsigned int sdhi2_wp_1_mux[] = {
         SDHI2_WP_PORT25_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        23,
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        21,
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_0_pins[] = {
+        /* TO */
+        66,
+};
+static const unsigned int tpu0_to2_0_mux[] = {
+        TPU0TO2_PORT66_MARK,
+};
+static const unsigned int tpu0_to2_1_pins[] = {
+        /* TO */
+        202,
+};
+static const unsigned int tpu0_to2_1_mux[] = {
+        TPU0TO2_PORT202_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        180,
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data8),
+        SH_PFC_PIN_GROUP(bsc_data16),
+        SH_PFC_PIN_GROUP(bsc_data32),
+        SH_PFC_PIN_GROUP(bsc_cs0),
+        SH_PFC_PIN_GROUP(bsc_cs2),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5a_0),
+        SH_PFC_PIN_GROUP(bsc_cs5a_1),
+        SH_PFC_PIN_GROUP(bsc_cs5b),
+        SH_PFC_PIN_GROUP(bsc_cs6a),
+        SH_PFC_PIN_GROUP(bsc_rd_we8),
+        SH_PFC_PIN_GROUP(bsc_rd_we16),
+        SH_PFC_PIN_GROUP(bsc_rd_we32),
+        SH_PFC_PIN_GROUP(bsc_bs),
+        SH_PFC_PIN_GROUP(bsc_rdwr),
+        SH_PFC_PIN_GROUP(ceu0_data_0_7),
+        SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
+        SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
+        SH_PFC_PIN_GROUP(ceu0_clk_0),
+        SH_PFC_PIN_GROUP(ceu0_clk_1),
+        SH_PFC_PIN_GROUP(ceu0_clk_2),
+        SH_PFC_PIN_GROUP(ceu0_sync),
+        SH_PFC_PIN_GROUP(ceu0_field),
+        SH_PFC_PIN_GROUP(ceu1_data),
+        SH_PFC_PIN_GROUP(ceu1_clk),
+        SH_PFC_PIN_GROUP(ceu1_sync),
+        SH_PFC_PIN_GROUP(ceu1_field),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in_0),
+        SH_PFC_PIN_GROUP(fsia_data_in_1),
+        SH_PFC_PIN_GROUP(fsia_data_out_0),
+        SH_PFC_PIN_GROUP(fsia_data_out_1),
+        SH_PFC_PIN_GROUP(fsia_data_out_2),
+        SH_PFC_PIN_GROUP(fsia_spdif_0),
+        SH_PFC_PIN_GROUP(fsia_spdif_1),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(gether_rmii),
+        SH_PFC_PIN_GROUP(gether_mii),
+        SH_PFC_PIN_GROUP(gether_gmii),
+        SH_PFC_PIN_GROUP(gether_int),
+        SH_PFC_PIN_GROUP(gether_link),
+        SH_PFC_PIN_GROUP(gether_wol),
+        SH_PFC_PIN_GROUP(hdmi),
+        SH_PFC_PIN_GROUP(intc_irq0_0),
+        SH_PFC_PIN_GROUP(intc_irq0_1),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2_0),
+        SH_PFC_PIN_GROUP(intc_irq2_1),
+        SH_PFC_PIN_GROUP(intc_irq3_0),
+        SH_PFC_PIN_GROUP(intc_irq3_1),
+        SH_PFC_PIN_GROUP(intc_irq4_0),
+        SH_PFC_PIN_GROUP(intc_irq4_1),
+        SH_PFC_PIN_GROUP(intc_irq5_0),
+        SH_PFC_PIN_GROUP(intc_irq5_1),
+        SH_PFC_PIN_GROUP(intc_irq6_0),
+        SH_PFC_PIN_GROUP(intc_irq6_1),
+        SH_PFC_PIN_GROUP(intc_irq7_0),
+        SH_PFC_PIN_GROUP(intc_irq7_1),
+        SH_PFC_PIN_GROUP(intc_irq8),
+        SH_PFC_PIN_GROUP(intc_irq9_0),
+        SH_PFC_PIN_GROUP(intc_irq9_1),
+        SH_PFC_PIN_GROUP(intc_irq10),
+        SH_PFC_PIN_GROUP(intc_irq11),
+        SH_PFC_PIN_GROUP(intc_irq12_0),
+        SH_PFC_PIN_GROUP(intc_irq12_1),
+        SH_PFC_PIN_GROUP(intc_irq13_0),
+        SH_PFC_PIN_GROUP(intc_irq13_1),
+        SH_PFC_PIN_GROUP(intc_irq14_0),
+        SH_PFC_PIN_GROUP(intc_irq14_1),
+        SH_PFC_PIN_GROUP(intc_irq15_0),
+        SH_PFC_PIN_GROUP(intc_irq15_1),
+        SH_PFC_PIN_GROUP(intc_irq16_0),
+        SH_PFC_PIN_GROUP(intc_irq16_1),
+        SH_PFC_PIN_GROUP(intc_irq17),
+        SH_PFC_PIN_GROUP(intc_irq18),
+        SH_PFC_PIN_GROUP(intc_irq19),
+        SH_PFC_PIN_GROUP(intc_irq20),
+        SH_PFC_PIN_GROUP(intc_irq21),
+        SH_PFC_PIN_GROUP(intc_irq22),
+        SH_PFC_PIN_GROUP(intc_irq23),
+        SH_PFC_PIN_GROUP(intc_irq24),
+        SH_PFC_PIN_GROUP(intc_irq25),
+        SH_PFC_PIN_GROUP(intc_irq26_0),
+        SH_PFC_PIN_GROUP(intc_irq26_1),
+        SH_PFC_PIN_GROUP(intc_irq27_0),
+        SH_PFC_PIN_GROUP(intc_irq27_1),
+        SH_PFC_PIN_GROUP(intc_irq28_0),
+        SH_PFC_PIN_GROUP(intc_irq28_1),
+        SH_PFC_PIN_GROUP(intc_irq29_0),
+        SH_PFC_PIN_GROUP(intc_irq29_1),
+        SH_PFC_PIN_GROUP(intc_irq30_0),
+        SH_PFC_PIN_GROUP(intc_irq30_1),
+        SH_PFC_PIN_GROUP(intc_irq31_0),
+        SH_PFC_PIN_GROUP(intc_irq31_1),
         SH_PFC_PIN_GROUP(lcd0_data8),
         SH_PFC_PIN_GROUP(lcd0_data9),
         SH_PFC_PIN_GROUP(lcd0_data12),
@@ -2084,6 +2910,41 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(mmc0_data4_1),
         SH_PFC_PIN_GROUP(mmc0_data8_1),
         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk_0),
+        SH_PFC_PIN_GROUP(scifa2_clk_1),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa3_data_0),
+        SH_PFC_PIN_GROUP(scifa3_clk_0),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa3_data_1),
+        SH_PFC_PIN_GROUP(scifa3_clk_1),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa4_data_0),
+        SH_PFC_PIN_GROUP(scifa4_data_1),
+        SH_PFC_PIN_GROUP(scifa4_data_2),
+        SH_PFC_PIN_GROUP(scifa4_clk_0),
+        SH_PFC_PIN_GROUP(scifa4_clk_1),
+        SH_PFC_PIN_GROUP(scifa5_data_0),
+        SH_PFC_PIN_GROUP(scifa5_data_1),
+        SH_PFC_PIN_GROUP(scifa5_data_2),
+        SH_PFC_PIN_GROUP(scifa5_clk_0),
+        SH_PFC_PIN_GROUP(scifa5_clk_1),
+        SH_PFC_PIN_GROUP(scifa6_data),
+        SH_PFC_PIN_GROUP(scifa6_clk),
+        SH_PFC_PIN_GROUP(scifa7_data),
+        SH_PFC_PIN_GROUP(scifb_data_0),
+        SH_PFC_PIN_GROUP(scifb_clk_0),
+        SH_PFC_PIN_GROUP(scifb_ctrl_0),
+        SH_PFC_PIN_GROUP(scifb_data_1),
+        SH_PFC_PIN_GROUP(scifb_clk_1),
+        SH_PFC_PIN_GROUP(scifb_ctrl_1),
         SH_PFC_PIN_GROUP(sdhi0_data1),
         SH_PFC_PIN_GROUP(sdhi0_data4),
         SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -2101,6 +2962,132 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_wp_0),
         SH_PFC_PIN_GROUP(sdhi2_cd_1),
         SH_PFC_PIN_GROUP(sdhi2_wp_1),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2_0),
+        SH_PFC_PIN_GROUP(tpu0_to2_1),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data8",
+        "bsc_data16",
+        "bsc_data32",
+        "bsc_cs0",
+        "bsc_cs2",
+        "bsc_cs4",
+        "bsc_cs5a_0",
+        "bsc_cs5a_1",
+        "bsc_cs5b",
+        "bsc_cs6a",
+        "bsc_rd_we8",
+        "bsc_rd_we16",
+        "bsc_rd_we32",
+        "bsc_bs",
+        "bsc_rdwr",
+};
+
+static const char * const ceu0_groups[] = {
+        "ceu0_data_0_7",
+        "ceu0_data_8_15_0",
+        "ceu0_data_8_15_1",
+        "ceu0_clk_0",
+        "ceu0_clk_1",
+        "ceu0_clk_2",
+        "ceu0_sync",
+        "ceu0_field",
+};
+
+static const char * const ceu1_groups[] = {
+        "ceu1_data",
+        "ceu1_clk",
+        "ceu1_sync",
+        "ceu1_field",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in_0",
+        "fsia_data_in_1",
+        "fsia_data_out_0",
+        "fsia_data_out_1",
+        "fsia_data_out_2",
+        "fsia_spdif_0",
+        "fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+};
+
+static const char * const gether_groups[] = {
+        "gether_rmii",
+        "gether_mii",
+        "gether_gmii",
+        "gether_int",
+        "gether_link",
+        "gether_wol",
+};
+
+static const char * const hdmi_groups[] = {
+        "hdmi",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0_0",
+        "intc_irq0_1",
+        "intc_irq1",
+        "intc_irq2_0",
+        "intc_irq2_1",
+        "intc_irq3_0",
+        "intc_irq3_1",
+        "intc_irq4_0",
+        "intc_irq4_1",
+        "intc_irq5_0",
+        "intc_irq5_1",
+        "intc_irq6_0",
+        "intc_irq6_1",
+        "intc_irq7_0",
+        "intc_irq7_1",
+        "intc_irq8",
+        "intc_irq9_0",
+        "intc_irq9_1",
+        "intc_irq10",
+        "intc_irq11",
+        "intc_irq12_0",
+        "intc_irq12_1",
+        "intc_irq13_0",
+        "intc_irq13_1",
+        "intc_irq14_0",
+        "intc_irq14_1",
+        "intc_irq15_0",
+        "intc_irq15_1",
+        "intc_irq16_0",
+        "intc_irq16_1",
+        "intc_irq17",
+        "intc_irq18",
+        "intc_irq19",
+        "intc_irq20",
+        "intc_irq21",
+        "intc_irq22",
+        "intc_irq23",
+        "intc_irq24",
+        "intc_irq25",
+        "intc_irq26_0",
+        "intc_irq26_1",
+        "intc_irq27_0",
+        "intc_irq27_1",
+        "intc_irq28_0",
+        "intc_irq28_1",
+        "intc_irq29_0",
+        "intc_irq29_1",
+        "intc_irq30_0",
+        "intc_irq30_1",
+        "intc_irq31_0",
+        "intc_irq31_1",
 };
 
 static const char * const lcd0_groups[] = {
@@ -2142,6 +3129,68 @@ static const char * const mmc0_groups[] = {
         "mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk_0",
+        "scifa2_clk_1",
+        "scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data_0",
+        "scifa3_clk_0",
+        "scifa3_ctrl_0",
+        "scifa3_data_1",
+        "scifa3_clk_1",
+        "scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data_0",
+        "scifa4_data_1",
+        "scifa4_data_2",
+        "scifa4_clk_0",
+        "scifa4_clk_1",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data_0",
+        "scifa5_data_1",
+        "scifa5_data_2",
+        "scifa5_clk_0",
+        "scifa5_clk_1",
+};
+
+static const char * const scifa6_groups[] = {
+        "scifa6_data",
+        "scifa6_clk",
+};
+
+static const char * const scifa7_groups[] = {
+        "scifa7_data",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data_0",
+        "scifb_clk_0",
+        "scifb_ctrl_0",
+        "scifb_data_1",
+        "scifb_clk_1",
+        "scifb_ctrl_1",
+};
+
 static const char * const sdhi0_groups[] = {
         "sdhi0_data1",
         "sdhi0_data4",
@@ -2168,412 +3217,51 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_wp_1",
 };
 
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2_0",
+        "tpu0_to2_1",
+        "tpu0_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(ceu0),
+        SH_PFC_FUNCTION(ceu1),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(gether),
+        SH_PFC_FUNCTION(hdmi),
+        SH_PFC_FUNCTION(intc),
         SH_PFC_FUNCTION(lcd0),
         SH_PFC_FUNCTION(lcd1),
         SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifa6),
+        SH_PFC_FUNCTION(scifa7),
+        SH_PFC_FUNCTION(scifb),
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(tpu0),
 };
 
-#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* IRQ */
-        GPIO_FN(IRQ0_PORT2),    GPIO_FN(IRQ0_PORT13),
-        GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_PORT11),   GPIO_FN(IRQ2_PORT12),
-        GPIO_FN(IRQ3_PORT10),   GPIO_FN(IRQ3_PORT14),
-        GPIO_FN(IRQ4_PORT15),   GPIO_FN(IRQ4_PORT172),
-        GPIO_FN(IRQ5_PORT0),    GPIO_FN(IRQ5_PORT1),
-        GPIO_FN(IRQ6_PORT121),  GPIO_FN(IRQ6_PORT173),
-        GPIO_FN(IRQ7_PORT120),  GPIO_FN(IRQ7_PORT209),
-        GPIO_FN(IRQ8),
-        GPIO_FN(IRQ9_PORT118),  GPIO_FN(IRQ9_PORT210),
-        GPIO_FN(IRQ10),
-        GPIO_FN(IRQ11),
-        GPIO_FN(IRQ12_PORT42),  GPIO_FN(IRQ12_PORT97),
-        GPIO_FN(IRQ13_PORT64),  GPIO_FN(IRQ13_PORT98),
-        GPIO_FN(IRQ14_PORT63),  GPIO_FN(IRQ14_PORT99),
-        GPIO_FN(IRQ15_PORT62),  GPIO_FN(IRQ15_PORT100),
-        GPIO_FN(IRQ16_PORT68),  GPIO_FN(IRQ16_PORT211),
-        GPIO_FN(IRQ17),
-        GPIO_FN(IRQ18),
-        GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),
-        GPIO_FN(IRQ21),
-        GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),
-        GPIO_FN(IRQ24),
-        GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_PORT58),  GPIO_FN(IRQ26_PORT81),
-        GPIO_FN(IRQ27_PORT57),  GPIO_FN(IRQ27_PORT168),
-        GPIO_FN(IRQ28_PORT56),  GPIO_FN(IRQ28_PORT169),
-        GPIO_FN(IRQ29_PORT50),  GPIO_FN(IRQ29_PORT170),
-        GPIO_FN(IRQ30_PORT49),  GPIO_FN(IRQ30_PORT171),
-        GPIO_FN(IRQ31_PORT41),  GPIO_FN(IRQ31_PORT167),
-
-        /* Function */
-
-        /* DBGT */
-        GPIO_FN(DBGMDT2),       GPIO_FN(DBGMDT1),       GPIO_FN(DBGMDT0),
-        GPIO_FN(DBGMD10),       GPIO_FN(DBGMD11),       GPIO_FN(DBGMD20),
-        GPIO_FN(DBGMD21),
-
-        /* FSI-A */
-        GPIO_FN(FSIAISLD_PORT0),        /* FSIAISLD Port 0/5 */
-        GPIO_FN(FSIAISLD_PORT5),
-        GPIO_FN(FSIASPDIF_PORT9),       /* FSIASPDIF Port 9/18 */
-        GPIO_FN(FSIASPDIF_PORT18),
-        GPIO_FN(FSIAOSLD1),     GPIO_FN(FSIAOSLD2),     GPIO_FN(FSIAOLR),
-        GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIACK),        GPIO_FN(FSIAILR),       GPIO_FN(FSIAIBT),
-
-        /* FSI-B */
-        GPIO_FN(FSIBCK),
-
-        /* FMSI */
-        GPIO_FN(FMSISLD_PORT1), /* FMSISLD Port 1/6 */
-        GPIO_FN(FMSISLD_PORT6),
-        GPIO_FN(FMSIILR),       GPIO_FN(FMSIIBT),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSIOBT),       GPIO_FN(FMSICK),        GPIO_FN(FMSOILR),
-        GPIO_FN(FMSOIBT),       GPIO_FN(FMSOOLR),       GPIO_FN(FMSOOBT),
-        GPIO_FN(FMSOSLD),       GPIO_FN(FMSOCK),
-
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_SCK),    GPIO_FN(SCIFA0_CTS),    GPIO_FN(SCIFA0_RTS),
-        GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_TXD),
-
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_CTS),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RTS),
-
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_SCK_PORT22), /* SCIFA2_SCK Port 22/199 */
-        GPIO_FN(SCIFA2_SCK_PORT199),
-        GPIO_FN(SCIFA2_RXD),    GPIO_FN(SCIFA2_TXD),
-        GPIO_FN(SCIFA2_CTS),    GPIO_FN(SCIFA2_RTS),
-
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_RTS_PORT105), /* MSEL5CR_8_0 */
-        GPIO_FN(SCIFA3_SCK_PORT116),
-        GPIO_FN(SCIFA3_CTS_PORT117),
-        GPIO_FN(SCIFA3_RXD_PORT174),
-        GPIO_FN(SCIFA3_TXD_PORT175),
-
-        GPIO_FN(SCIFA3_RTS_PORT161), /* MSEL5CR_8_1 */
-        GPIO_FN(SCIFA3_SCK_PORT158),
-        GPIO_FN(SCIFA3_CTS_PORT162),
-        GPIO_FN(SCIFA3_RXD_PORT159),
-        GPIO_FN(SCIFA3_TXD_PORT160),
-
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD_PORT12), /* MSEL5CR[12:11] = 00 */
-        GPIO_FN(SCIFA4_TXD_PORT13),
-
-        GPIO_FN(SCIFA4_RXD_PORT204), /* MSEL5CR[12:11] = 01 */
-        GPIO_FN(SCIFA4_TXD_PORT203),
-
-        GPIO_FN(SCIFA4_RXD_PORT94), /* MSEL5CR[12:11] = 10 */
-        GPIO_FN(SCIFA4_TXD_PORT93),
-
-        GPIO_FN(SCIFA4_SCK_PORT21), /* SCIFA4_SCK Port 21/205 */
-        GPIO_FN(SCIFA4_SCK_PORT205),
-
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_TXD_PORT20), /* MSEL5CR[15:14] = 00 */
-        GPIO_FN(SCIFA5_RXD_PORT10),
-
-        GPIO_FN(SCIFA5_RXD_PORT207), /* MSEL5CR[15:14] = 01 */
-        GPIO_FN(SCIFA5_TXD_PORT208),
-
-        GPIO_FN(SCIFA5_TXD_PORT91), /* MSEL5CR[15:14] = 10 */
-        GPIO_FN(SCIFA5_RXD_PORT92),
-
-        GPIO_FN(SCIFA5_SCK_PORT23), /* SCIFA5_SCK Port 23/206 */
-        GPIO_FN(SCIFA5_SCK_PORT206),
-
-        /* SCIFA6 */
-        GPIO_FN(SCIFA6_SCK),    GPIO_FN(SCIFA6_RXD),    GPIO_FN(SCIFA6_TXD),
-
-        /* SCIFA7 */
-        GPIO_FN(SCIFA7_TXD),    GPIO_FN(SCIFA7_RXD),
-
-        /* SCIFAB */
-        GPIO_FN(SCIFB_SCK_PORT190), /* MSEL5CR_17_0 */
-        GPIO_FN(SCIFB_RXD_PORT191),
-        GPIO_FN(SCIFB_TXD_PORT192),
-        GPIO_FN(SCIFB_RTS_PORT186),
-        GPIO_FN(SCIFB_CTS_PORT187),
-
-        GPIO_FN(SCIFB_SCK_PORT2), /* MSEL5CR_17_1 */
-        GPIO_FN(SCIFB_RXD_PORT3),
-        GPIO_FN(SCIFB_TXD_PORT4),
-        GPIO_FN(SCIFB_RTS_PORT172),
-        GPIO_FN(SCIFB_CTS_PORT173),
-
-        /* RSPI */
-        GPIO_FN(RSPI_SSL0_A),   GPIO_FN(RSPI_SSL1_A),   GPIO_FN(RSPI_SSL2_A),
-        GPIO_FN(RSPI_SSL3_A),   GPIO_FN(RSPI_CK_A),     GPIO_FN(RSPI_MOSI_A),
-        GPIO_FN(RSPI_MISO_A),
-
-        /* VIO CKO */
-        GPIO_FN(VIO_CKO1),
-        GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_CKO_1),
-        GPIO_FN(VIO_CKO),
-
-        /* VIO0 */
-        GPIO_FN(VIO0_D0),       GPIO_FN(VIO0_D1),       GPIO_FN(VIO0_D2),
-        GPIO_FN(VIO0_D3),       GPIO_FN(VIO0_D4),       GPIO_FN(VIO0_D5),
-        GPIO_FN(VIO0_D6),       GPIO_FN(VIO0_D7),       GPIO_FN(VIO0_D8),
-        GPIO_FN(VIO0_D9),       GPIO_FN(VIO0_D10),      GPIO_FN(VIO0_D11),
-        GPIO_FN(VIO0_D12),      GPIO_FN(VIO0_VD),       GPIO_FN(VIO0_HD),
-        GPIO_FN(VIO0_CLK),      GPIO_FN(VIO0_FIELD),
-
-        GPIO_FN(VIO0_D13_PORT26), /* MSEL5CR_27_0 */
-        GPIO_FN(VIO0_D14_PORT25),
-        GPIO_FN(VIO0_D15_PORT24),
-
-        GPIO_FN(VIO0_D13_PORT22), /* MSEL5CR_27_1 */
-        GPIO_FN(VIO0_D14_PORT95),
-        GPIO_FN(VIO0_D15_PORT96),
-
-        /* VIO1 */
-        GPIO_FN(VIO1_D0),       GPIO_FN(VIO1_D1),       GPIO_FN(VIO1_D2),
-        GPIO_FN(VIO1_D3),       GPIO_FN(VIO1_D4),       GPIO_FN(VIO1_D5),
-        GPIO_FN(VIO1_D6),       GPIO_FN(VIO1_D7),       GPIO_FN(VIO1_VD),
-        GPIO_FN(VIO1_HD),       GPIO_FN(VIO1_CLK),      GPIO_FN(VIO1_FIELD),
-
-        /* TPU0 */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO3),
-        GPIO_FN(TPU0TO2_PORT66), /* TPU0TO2 Port 66/202 */
-        GPIO_FN(TPU0TO2_PORT202),
-
-        /* SSP1 0 */
-        GPIO_FN(STP0_IPD0),     GPIO_FN(STP0_IPD1),     GPIO_FN(STP0_IPD2),
-        GPIO_FN(STP0_IPD3),     GPIO_FN(STP0_IPD4),     GPIO_FN(STP0_IPD5),
-        GPIO_FN(STP0_IPD6),     GPIO_FN(STP0_IPD7),     GPIO_FN(STP0_IPEN),
-        GPIO_FN(STP0_IPCLK),    GPIO_FN(STP0_IPSYNC),
-
-        /* SSP1 1 */
-        GPIO_FN(STP1_IPD1),     GPIO_FN(STP1_IPD2),     GPIO_FN(STP1_IPD3),
-        GPIO_FN(STP1_IPD4),     GPIO_FN(STP1_IPD5),     GPIO_FN(STP1_IPD6),
-        GPIO_FN(STP1_IPD7),     GPIO_FN(STP1_IPCLK),    GPIO_FN(STP1_IPSYNC),
-
-        GPIO_FN(STP1_IPD0_PORT186), /* MSEL5CR_23_0 */
-        GPIO_FN(STP1_IPEN_PORT187),
-
-        GPIO_FN(STP1_IPD0_PORT194), /* MSEL5CR_23_1 */
-        GPIO_FN(STP1_IPEN_PORT193),
-
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),
-        GPIO_FN(SIM_D_PORT22), /* SIM_D  Port 22/199 */
-        GPIO_FN(SIM_D_PORT199),
-
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_TXD),    GPIO_FN(MSIOF2_RXD),    GPIO_FN(MSIOF2_TSCK),
-        GPIO_FN(MSIOF2_SS2),    GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_MCK0),   GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(MSIOF2_RSCK),
-
-        /* KEYSC */
-        GPIO_FN(KEYIN4),        GPIO_FN(KEYIN5),
-        GPIO_FN(KEYIN6),        GPIO_FN(KEYIN7),
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYOUT1),       GPIO_FN(KEYOUT2),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYOUT4),       GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYOUT6),       GPIO_FN(KEYOUT7),
-
-        GPIO_FN(KEYIN0_PORT43), /* MSEL4CR_18_0 */
-        GPIO_FN(KEYIN1_PORT44),
-        GPIO_FN(KEYIN2_PORT45),
-        GPIO_FN(KEYIN3_PORT46),
-
-        GPIO_FN(KEYIN0_PORT58), /* MSEL4CR_18_1 */
-        GPIO_FN(KEYIN1_PORT57),
-        GPIO_FN(KEYIN2_PORT56),
-        GPIO_FN(KEYIN3_PORT55),
-
-        /* VOU */
-        GPIO_FN(DV_D0),         GPIO_FN(DV_D1),         GPIO_FN(DV_D2),
-        GPIO_FN(DV_D3),         GPIO_FN(DV_D4),         GPIO_FN(DV_D5),
-        GPIO_FN(DV_D6),         GPIO_FN(DV_D7),         GPIO_FN(DV_D8),
-        GPIO_FN(DV_D9),         GPIO_FN(DV_D10),        GPIO_FN(DV_D11),
-        GPIO_FN(DV_D12),        GPIO_FN(DV_D13),        GPIO_FN(DV_D14),
-        GPIO_FN(DV_D15),        GPIO_FN(DV_CLK),
-        GPIO_FN(DV_VSYNC),      GPIO_FN(DV_HSYNC),
-
-        /* MEMC */
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),     GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_INT),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_NOE),      GPIO_FN(MEMC_CS1),
-        GPIO_FN(MEMC_A1),       GPIO_FN(MEMC_ADV),      GPIO_FN(MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT),     GPIO_FN(MEMC_DREQ1),    GPIO_FN(MEMC_BUSCLK),
-        GPIO_FN(MEMC_A0),
-
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),    GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_TXD),    GPIO_FN(MSIOF0_MCK0),   GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(MSIOF0_TSYNC),
-
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_RSCK),   GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),   GPIO_FN(MSIOF1_MCK1),
-
-        GPIO_FN(MSIOF1_SS2_PORT116),    GPIO_FN(MSIOF1_SS1_PORT117),
-        GPIO_FN(MSIOF1_RXD_PORT118),    GPIO_FN(MSIOF1_TXD_PORT119),
-        GPIO_FN(MSIOF1_TSYNC_PORT120),
-        GPIO_FN(MSIOF1_TSCK_PORT121),   /* MSEL4CR_10_0 */
-
-        GPIO_FN(MSIOF1_SS1_PORT67),     GPIO_FN(MSIOF1_TSCK_PORT72),
-        GPIO_FN(MSIOF1_TSYNC_PORT73),   GPIO_FN(MSIOF1_TXD_PORT74),
-        GPIO_FN(MSIOF1_RXD_PORT75),
-        GPIO_FN(MSIOF1_SS2_PORT202),    /* MSEL4CR_10_1 */
-
-        /* GPIO */
-        GPIO_FN(GPO0),  GPIO_FN(GPI0),
-        GPIO_FN(GPO1),  GPIO_FN(GPI1),
-
-        /* USB0 */
-        GPIO_FN(USB0_OCI),      GPIO_FN(USB0_PPON),     GPIO_FN(VBUS),
-
-        /* USB1 */
-        GPIO_FN(USB1_OCI),      GPIO_FN(USB1_PPON),
-
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(BBIF1_TSCK),    GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BBIF1_RX_FLOW_N),
-
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TXD2_PORT5), /* MSEL5CR_0_0 */
-        GPIO_FN(BBIF2_RXD2_PORT60),
-        GPIO_FN(BBIF2_TSYNC2_PORT6),
-        GPIO_FN(BBIF2_TSCK2_PORT59),
-
-        GPIO_FN(BBIF2_RXD2_PORT90), /* MSEL5CR_0_1 */
-        GPIO_FN(BBIF2_TXD2_PORT183),
-        GPIO_FN(BBIF2_TSCK2_PORT89),
-        GPIO_FN(BBIF2_TSYNC2_PORT184),
-
-        /* BSC / FLCTL / PCMCIA */
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5B),  GPIO_FN(CS6A),
-        GPIO_FN(CS5A_PORT105), /* CS5A PORT 19/105 */
-        GPIO_FN(CS5A_PORT19),
-        GPIO_FN(IOIS16), /* ? */
-
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),    GPIO_FN(A3),
-        GPIO_FN(A4_FOE),        GPIO_FN(A5_FCDE),       /* share with FLCTL */
-        GPIO_FN(A6),    GPIO_FN(A7),    GPIO_FN(A8),    GPIO_FN(A9),
-        GPIO_FN(A10),   GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),   GPIO_FN(A17),
-        GPIO_FN(A18),   GPIO_FN(A19),   GPIO_FN(A20),   GPIO_FN(A21),
-        GPIO_FN(A22),   GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-
-        GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),       /* share with FLCTL */
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       /* share with FLCTL */
-        GPIO_FN(D4_NAF4),       GPIO_FN(D5_NAF5),       /* share with FLCTL */
-        GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),       /* share with FLCTL */
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       /* share with FLCTL */
-        GPIO_FN(D10_NAF10),     GPIO_FN(D11_NAF11),     /* share with FLCTL */
-        GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),     /* share with FLCTL */
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),     /* share with FLCTL */
-        GPIO_FN(D16),   GPIO_FN(D17),   GPIO_FN(D18),   GPIO_FN(D19),
-        GPIO_FN(D20),   GPIO_FN(D21),   GPIO_FN(D22),   GPIO_FN(D23),
-        GPIO_FN(D24),   GPIO_FN(D25),   GPIO_FN(D26),   GPIO_FN(D27),
-        GPIO_FN(D28),   GPIO_FN(D29),   GPIO_FN(D30),   GPIO_FN(D31),
-
-        GPIO_FN(WE0_FWE),       /* share with FLCTL */
-        GPIO_FN(WE1),
-        GPIO_FN(WE2_ICIORD),    /* share with PCMCIA */
-        GPIO_FN(WE3_ICIOWR),    /* share with PCMCIA */
-        GPIO_FN(CKO),   GPIO_FN(BS),    GPIO_FN(RDWR),
-        GPIO_FN(RD_FSC),        /* share with FLCTL */
-        GPIO_FN(WAIT_PORT177), /* WAIT Port 90/177 */
-        GPIO_FN(WAIT_PORT90),
-
-        GPIO_FN(FCE0),  GPIO_FN(FCE1),  GPIO_FN(FRB), /* FLCTL */
-
-        /* IRDA */
-        GPIO_FN(IRDA_FIRSEL),   GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_OUT),
-
-        /* ATAPI */
-        GPIO_FN(IDE_D0),        GPIO_FN(IDE_D1),        GPIO_FN(IDE_D2),
-        GPIO_FN(IDE_D3),        GPIO_FN(IDE_D4),        GPIO_FN(IDE_D5),
-        GPIO_FN(IDE_D6),        GPIO_FN(IDE_D7),        GPIO_FN(IDE_D8),
-        GPIO_FN(IDE_D9),        GPIO_FN(IDE_D10),       GPIO_FN(IDE_D11),
-        GPIO_FN(IDE_D12),       GPIO_FN(IDE_D13),       GPIO_FN(IDE_D14),
-        GPIO_FN(IDE_D15),       GPIO_FN(IDE_A0),        GPIO_FN(IDE_A1),
-        GPIO_FN(IDE_A2),        GPIO_FN(IDE_CS0),       GPIO_FN(IDE_CS1),
-        GPIO_FN(IDE_IOWR),      GPIO_FN(IDE_IORD),      GPIO_FN(IDE_IORDY),
-        GPIO_FN(IDE_INT),       GPIO_FN(IDE_RST),       GPIO_FN(IDE_DIRECTION),
-        GPIO_FN(IDE_EXBUF_ENB), GPIO_FN(IDE_IODACK),    GPIO_FN(IDE_IODREQ),
-
-        /* RMII */
-        GPIO_FN(RMII_CRS_DV),   GPIO_FN(RMII_RX_ER),    GPIO_FN(RMII_RXD0),
-        GPIO_FN(RMII_RXD1),     GPIO_FN(RMII_TX_EN),    GPIO_FN(RMII_TXD0),
-        GPIO_FN(RMII_MDC),      GPIO_FN(RMII_TXD1),     GPIO_FN(RMII_MDIO),
-        GPIO_FN(RMII_REF50CK),  GPIO_FN(RMII_REF125CK), /* for GMII */
-
-        /* GEther */
-        GPIO_FN(ET_TX_CLK),     GPIO_FN(ET_TX_EN),      GPIO_FN(ET_ETXD0),
-        GPIO_FN(ET_ETXD1),      GPIO_FN(ET_ETXD2),      GPIO_FN(ET_ETXD3),
-        GPIO_FN(ET_ETXD4),      GPIO_FN(ET_ETXD5), /* for GEther */
-        GPIO_FN(ET_ETXD6),      GPIO_FN(ET_ETXD7), /* for GEther */
-        GPIO_FN(ET_COL),        GPIO_FN(ET_TX_ER),      GPIO_FN(ET_RX_CLK),
-        GPIO_FN(ET_RX_DV),      GPIO_FN(ET_ERXD0),      GPIO_FN(ET_ERXD1),
-        GPIO_FN(ET_ERXD2),      GPIO_FN(ET_ERXD3),
-        GPIO_FN(ET_ERXD4),      GPIO_FN(ET_ERXD5), /* for GEther */
-        GPIO_FN(ET_ERXD6),      GPIO_FN(ET_ERXD7), /* for GEther */
-        GPIO_FN(ET_RX_ER),      GPIO_FN(ET_CRS),        GPIO_FN(ET_MDC),
-        GPIO_FN(ET_MDIO),       GPIO_FN(ET_LINK),       GPIO_FN(ET_PHY_INT),
-        GPIO_FN(ET_WOL),        GPIO_FN(ET_GTX_CLK),
-
-        /* DMA0 */
-        GPIO_FN(DREQ0), GPIO_FN(DACK0),
-
-        /* DMA1 */
-        GPIO_FN(DREQ1), GPIO_FN(DACK1),
-
-        /* SYSC */
-        GPIO_FN(RESETOUTS),
-
-        /* IRREM */
-        GPIO_FN(IROUT),
-
-        /* LCDC */
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),
-        GPIO_FN(HDMI_CEC),
-
-        /* SYSC */
-        GPIO_FN(RESETP_PULLUP),
-        GPIO_FN(RESETP_PLAIN),
-
-        /* DEBUG */
-        GPIO_FN(EDEBGREQ_PULLDOWN),
-        GPIO_FN(EDEBGREQ_PULLUP),
-
-        GPIO_FN(TRACEAUD_FROM_VIO),
-        GPIO_FN(TRACEAUD_FROM_LCDC0),
-        GPIO_FN(TRACEAUD_FROM_MEMC),
-};
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xe6050000), /* PORT0CR */
@@ -2994,48 +3682,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 };
 
 static const struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(irq_pin(0), GPIO_PORT2,   GPIO_PORT13),      /* IRQ0A */
-        PINMUX_IRQ(irq_pin(1), GPIO_PORT20),            /* IRQ1A */
-        PINMUX_IRQ(irq_pin(2), GPIO_PORT11,  GPIO_PORT12),      /* IRQ2A */
-        PINMUX_IRQ(irq_pin(3), GPIO_PORT10,  GPIO_PORT14),      /* IRQ3A */
-        PINMUX_IRQ(irq_pin(4), GPIO_PORT15,  GPIO_PORT172),/* IRQ4A */
-        PINMUX_IRQ(irq_pin(5), GPIO_PORT0,   GPIO_PORT1),       /* IRQ5A */
-        PINMUX_IRQ(irq_pin(6), GPIO_PORT121, GPIO_PORT173),/* IRQ6A */
-        PINMUX_IRQ(irq_pin(7), GPIO_PORT120, GPIO_PORT209),/* IRQ7A */
-        PINMUX_IRQ(irq_pin(8), GPIO_PORT119),           /* IRQ8A */
-        PINMUX_IRQ(irq_pin(9), GPIO_PORT118, GPIO_PORT210),/* IRQ9A */
-        PINMUX_IRQ(irq_pin(10), GPIO_PORT19),           /* IRQ10A */
-        PINMUX_IRQ(irq_pin(11), GPIO_PORT104),          /* IRQ11A */
-        PINMUX_IRQ(irq_pin(12), GPIO_PORT42,  GPIO_PORT97),     /* IRQ12A */
-        PINMUX_IRQ(irq_pin(13), GPIO_PORT64,  GPIO_PORT98),     /* IRQ13A */
-        PINMUX_IRQ(irq_pin(14), GPIO_PORT63,  GPIO_PORT99),     /* IRQ14A */
-        PINMUX_IRQ(irq_pin(15), GPIO_PORT62,  GPIO_PORT100),/* IRQ15A */
-        PINMUX_IRQ(irq_pin(16), GPIO_PORT68,  GPIO_PORT211),/* IRQ16A */
-        PINMUX_IRQ(irq_pin(17), GPIO_PORT69),           /* IRQ17A */
-        PINMUX_IRQ(irq_pin(18), GPIO_PORT70),           /* IRQ18A */
-        PINMUX_IRQ(irq_pin(19), GPIO_PORT71),           /* IRQ19A */
-        PINMUX_IRQ(irq_pin(20), GPIO_PORT67),           /* IRQ20A */
-        PINMUX_IRQ(irq_pin(21), GPIO_PORT202),          /* IRQ21A */
-        PINMUX_IRQ(irq_pin(22), GPIO_PORT95),           /* IRQ22A */
-        PINMUX_IRQ(irq_pin(23), GPIO_PORT96),           /* IRQ23A */
-        PINMUX_IRQ(irq_pin(24), GPIO_PORT180),          /* IRQ24A */
-        PINMUX_IRQ(irq_pin(25), GPIO_PORT38),           /* IRQ25A */
-        PINMUX_IRQ(irq_pin(26), GPIO_PORT58,  GPIO_PORT81),     /* IRQ26A */
-        PINMUX_IRQ(irq_pin(27), GPIO_PORT57,  GPIO_PORT168),/* IRQ27A */
-        PINMUX_IRQ(irq_pin(28), GPIO_PORT56,  GPIO_PORT169),/* IRQ28A */
-        PINMUX_IRQ(irq_pin(29), GPIO_PORT50,  GPIO_PORT170),/* IRQ29A */
-        PINMUX_IRQ(irq_pin(30), GPIO_PORT49,  GPIO_PORT171),/* IRQ30A */
-        PINMUX_IRQ(irq_pin(31), GPIO_PORT41,  GPIO_PORT167),/* IRQ31A */
+        PINMUX_IRQ(irq_pin(0), 2,   13),        /* IRQ0A */
+        PINMUX_IRQ(irq_pin(1), 20),             /* IRQ1A */
+        PINMUX_IRQ(irq_pin(2), 11,  12),        /* IRQ2A */
+        PINMUX_IRQ(irq_pin(3), 10,  14),        /* IRQ3A */
+        PINMUX_IRQ(irq_pin(4), 15,  172),       /* IRQ4A */
+        PINMUX_IRQ(irq_pin(5), 0,   1),         /* IRQ5A */
+        PINMUX_IRQ(irq_pin(6), 121, 173),       /* IRQ6A */
+        PINMUX_IRQ(irq_pin(7), 120, 209),       /* IRQ7A */
+        PINMUX_IRQ(irq_pin(8), 119),            /* IRQ8A */
+        PINMUX_IRQ(irq_pin(9), 118, 210),       /* IRQ9A */
+        PINMUX_IRQ(irq_pin(10), 19),            /* IRQ10A */
+        PINMUX_IRQ(irq_pin(11), 104),           /* IRQ11A */
+        PINMUX_IRQ(irq_pin(12), 42,  97),       /* IRQ12A */
+        PINMUX_IRQ(irq_pin(13), 64,  98),       /* IRQ13A */
+        PINMUX_IRQ(irq_pin(14), 63,  99),       /* IRQ14A */
+        PINMUX_IRQ(irq_pin(15), 62,  100),      /* IRQ15A */
+        PINMUX_IRQ(irq_pin(16), 68,  211),      /* IRQ16A */
+        PINMUX_IRQ(irq_pin(17), 69),            /* IRQ17A */
+        PINMUX_IRQ(irq_pin(18), 70),            /* IRQ18A */
+        PINMUX_IRQ(irq_pin(19), 71),            /* IRQ19A */
+        PINMUX_IRQ(irq_pin(20), 67),            /* IRQ20A */
+        PINMUX_IRQ(irq_pin(21), 202),           /* IRQ21A */
+        PINMUX_IRQ(irq_pin(22), 95),            /* IRQ22A */
+        PINMUX_IRQ(irq_pin(23), 96),            /* IRQ23A */
+        PINMUX_IRQ(irq_pin(24), 180),           /* IRQ24A */
+        PINMUX_IRQ(irq_pin(25), 38),            /* IRQ25A */
+        PINMUX_IRQ(irq_pin(26), 58,  81),       /* IRQ26A */
+        PINMUX_IRQ(irq_pin(27), 57,  168),      /* IRQ27A */
+        PINMUX_IRQ(irq_pin(28), 56,  169),      /* IRQ28A */
+        PINMUX_IRQ(irq_pin(29), 50,  170),      /* IRQ29A */
+        PINMUX_IRQ(irq_pin(30), 49,  171),      /* IRQ30A */
+        PINMUX_IRQ(irq_pin(31), 41,  167),      /* IRQ31A */
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+struct r8a7740_portcr_group {
+        unsigned int end_pin;
+        unsigned int offset;
+};
+
+static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
+        { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
+};
+
+static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
+                const struct r8a7740_portcr_group *group =
+                        &r8a7740_portcr_offsets[i];
+
+                if (i <= group->end_pin)
+                        return pfc->window->virt + group->offset + pin;
+        }
+
+        return NULL;
+}
+
+static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations r8a7740_pinmux_ops = {
+        .get_bias = r8a7740_pinmux_get_bias,
+        .set_bias = r8a7740_pinmux_set_bias,
 };
 
 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .name           = "r8a7740_pfc",
+        .ops            = &r8a7740_pinmux_ops,
+
         .input          = { PINMUX_INPUT_BEGIN,
                             PINMUX_INPUT_END },
-        .input_pu       = { PINMUX_INPUT_PULLUP_BEGIN,
-                            PINMUX_INPUT_PULLUP_END },
-        .input_pd       = { PINMUX_INPUT_PULLDOWN_BEGIN,
-                            PINMUX_INPUT_PULLDOWN_END },
         .output         = { PINMUX_OUTPUT_BEGIN,
                             PINMUX_OUTPUT_END },
         .function       = { PINMUX_FUNCTION_BEGIN,
@@ -3048,9 +3802,6 @@ const struct sh_pfc_soc_info r8a7740_pinmux_info = {
         .functions      = pinmux_functions,
         .nr_functions   = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios     = pinmux_func_gpios,
-        .nr_func_gpios  = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs       = pinmux_config_regs,
         .data_regs      = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
new file mode 100644
index 000000000000..1dcbabcd7b3c
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -0,0 +1,2783 @@
+/*
+ * r8a7778 processor support - PFC hardware block
+ *
+ * Copyright (C) 2013  Renesas Solutions Corp.
+ * Copyright (C) 2013  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Copyright (C) 2013  Cogent Embedded, Inc.
+ *
+ * based on
+ * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011  Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/platform_data/gpio-rcar.h>
+#include <linux/kernel.h>
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
+        PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
+        PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_27(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)           \
+        PORT_GP_32(0, fn, sfx),         \
+        PORT_GP_32(1, fn, sfx),         \
+        PORT_GP_32(2, fn, sfx),         \
+        PORT_GP_32(3, fn, sfx),         \
+        PORT_GP_27(4, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)         \
+        [RCAR_GP_PIN(bank, pin)] = {            \
+                .name = __stringify(_name),     \
+                .enum_id = _name##_DATA,        \
+        }
+
+#define _GP_DATA(bank, pin, name, sfx)          \
+        PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_NOGP(ispr, fn)      PINMUX_DATA(fn##_MARK, FN_##fn)
+#define PINMUX_IPSR_DATA(ipsr, fn)      PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
+#define PINMUX_IPSR_MSEL(ipsr, fn, ms)  PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr, FN_##ms)
+#define PINMUX_IPSR_NOGM(ispr, fn, ms)  PINMUX_DATA(fn##_MARK, FN_##fn,            FN_##ms)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA), /* GP_0_0_DATA -> GP_4_26_DATA */
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN), /* GP_0_0_FN -> GP_4_26_FN */
+
+        /* GPSR0 */
+        FN_IP0_1_0,     FN_PENC0,       FN_PENC1,       FN_IP0_4_2,
+        FN_IP0_7_5,     FN_IP0_11_8,    FN_IP0_14_12,   FN_A1,
+        FN_A2,          FN_A3,          FN_IP0_15,      FN_IP0_16,
+        FN_IP0_17,      FN_IP0_18,      FN_IP0_19,      FN_IP0_20,
+        FN_IP0_21,      FN_IP0_22,      FN_IP0_23,      FN_IP0_24,
+        FN_IP0_25,      FN_IP0_26,      FN_IP0_27,      FN_IP0_28,
+        FN_IP0_29,      FN_IP0_30,      FN_IP1_0,       FN_IP1_1,
+        FN_IP1_4_2,     FN_IP1_7_5,     FN_IP1_10_8,    FN_IP1_14_11,
+
+        /* GPSR1 */
+        FN_IP1_23_21,   FN_WE0,         FN_IP1_24,      FN_IP1_27_25,
+        FN_IP1_29_28,   FN_IP2_2_0,     FN_IP2_5_3,     FN_IP2_8_6,
+        FN_IP2_11_9,    FN_IP2_13_12,   FN_IP2_16_14,   FN_IP2_17,
+        FN_IP2_30,      FN_IP2_31,      FN_IP3_1_0,     FN_IP3_4_2,
+        FN_IP3_7_5,     FN_IP3_9_8,     FN_IP3_12_10,   FN_IP3_15_13,
+        FN_IP3_18_16,   FN_IP3_20_19,   FN_IP3_23_21,   FN_IP3_26_24,
+        FN_IP3_27,      FN_IP3_28,      FN_IP3_29,      FN_IP3_30,
+        FN_IP3_31,      FN_IP4_0,       FN_IP4_3_1,     FN_IP4_6_4,
+
+        /* GPSR2 */
+        FN_IP4_7,       FN_IP4_8,       FN_IP4_10_9,    FN_IP4_12_11,
+        FN_IP4_14_13,   FN_IP4_16_15,   FN_IP4_20_17,   FN_IP4_24_21,
+        FN_IP4_26_25,   FN_IP4_28_27,   FN_IP4_30_29,   FN_IP5_1_0,
+        FN_IP5_3_2,     FN_IP5_5_4,     FN_IP5_6,       FN_IP5_7,
+        FN_IP5_9_8,     FN_IP5_11_10,   FN_IP5_12,      FN_IP5_14_13,
+        FN_IP5_17_15,   FN_IP5_20_18,   FN_AUDIO_CLKA,  FN_AUDIO_CLKB,
+        FN_IP5_22_21,   FN_IP5_25_23,   FN_IP5_28_26,   FN_IP5_30_29,
+        FN_IP6_1_0,     FN_IP6_4_2,     FN_IP6_6_5,     FN_IP6_7,
+
+        /* GPSR3 */
+        FN_IP6_8,       FN_IP6_9,       FN_SSI_SCK34,   FN_IP6_10,
+        FN_IP6_12_11,   FN_IP6_13,      FN_IP6_15_14,   FN_IP6_16,
+        FN_IP6_18_17,   FN_IP6_20_19,   FN_IP6_21,      FN_IP6_23_22,
+        FN_IP6_25_24,   FN_IP6_27_26,   FN_IP6_29_28,   FN_IP6_31_30,
+        FN_IP7_1_0,     FN_IP7_3_2,     FN_IP7_5_4,     FN_IP7_8_6,
+        FN_IP7_11_9,    FN_IP7_14_12,   FN_IP7_17_15,   FN_IP7_20_18,
+        FN_IP7_21,      FN_IP7_24_22,   FN_IP7_28_25,   FN_IP7_31_29,
+        FN_IP8_2_0,     FN_IP8_5_3,     FN_IP8_8_6,     FN_IP8_10_9,
+
+        /* GPSR4 */
+        FN_IP8_13_11,   FN_IP8_15_14,   FN_IP8_18_16,   FN_IP8_21_19,
+        FN_IP8_23_22,   FN_IP8_26_24,   FN_IP8_29_27,   FN_IP9_2_0,
+        FN_IP9_5_3,     FN_IP9_8_6,     FN_IP9_11_9,    FN_IP9_14_12,
+        FN_IP9_17_15,   FN_IP9_20_18,   FN_IP9_23_21,   FN_IP9_26_24,
+        FN_IP9_29_27,   FN_IP10_2_0,    FN_IP10_5_3,    FN_IP10_8_6,
+        FN_IP10_12_9,   FN_IP10_15_13,  FN_IP10_18_16,  FN_IP10_21_19,
+        FN_IP10_24_22,  FN_AVS1,        FN_AVS2,
+
+        /* IPSR0 */
+        FN_PRESETOUT,   FN_PWM1,        FN_AUDATA0,     FN_ARM_TRACEDATA_0,
+        FN_GPSCLK_C,    FN_USB_OVC0,    FN_TX2_E,       FN_SDA2_B,
+        FN_AUDATA1,     FN_ARM_TRACEDATA_1,             FN_GPSIN_C,
+        FN_USB_OVC1,    FN_RX2_E,       FN_SCL2_B,      FN_SD1_DAT2_A,
+        FN_MMC_D2,      FN_BS,          FN_ATADIR0_A,   FN_SDSELF_A,
+        FN_PWM4_B,      FN_SD1_DAT3_A,  FN_MMC_D3,      FN_A0,
+        FN_ATAG0_A,     FN_REMOCON_B,   FN_A4,          FN_A5,
+        FN_A6,          FN_A7,          FN_A8,          FN_A9,
+        FN_A10,         FN_A11,         FN_A12,         FN_A13,
+        FN_A14,         FN_A15,         FN_A16,         FN_A17,
+        FN_A18,         FN_A19,
+
+        /* IPSR1 */
+        FN_A20,         FN_HSPI_CS1_B,  FN_A21,         FN_HSPI_CLK1_B,
+        FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
+        FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
+        FN_TS_SDEN0_A,  FN_SD1_CD_A,    FN_MMC_D6,      FN_A24,
+        FN_DREQ1_A,     FN_HRX0_B,      FN_TS_SPSYNC0_A,
+        FN_SD1_WP_A,    FN_MMC_D7,      FN_A25, FN_DACK1_A,
+        FN_HCTS0_B,     FN_RX3_C,       FN_TS_SDAT0_A,  FN_CLKOUT,
+        FN_HSPI_TX1_B,  FN_PWM0_B,      FN_CS0,         FN_HSPI_RX1_B,
+        FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
+        FN_SCK2_B,      FN_MMC_D5,      FN_ATADIR0_B,   FN_RD_WR,
+        FN_WE1,         FN_ATAWR0_B,    FN_SSI_WS1_B,   FN_EX_CS0,
+        FN_SCL2_A,      FN_TX3_C,       FN_TS_SCK0_A,   FN_EX_CS1,
+        FN_MMC_D4,
+
+        /* IPSR2 */
+        FN_SD1_CLK_A,   FN_MMC_CLK,     FN_ATACS00,     FN_EX_CS2,
+        FN_SD1_CMD_A,   FN_MMC_CMD,     FN_ATACS10,     FN_EX_CS3,
+        FN_SD1_DAT0_A,  FN_MMC_D0,      FN_ATARD0,      FN_EX_CS4,
+        FN_EX_WAIT1_A,  FN_SD1_DAT1_A,  FN_MMC_D1,      FN_ATAWR0_A,
+        FN_EX_CS5,      FN_EX_WAIT2_A,  FN_DREQ0_A,     FN_RX3_A,
+        FN_DACK0,       FN_TX3_A,       FN_DRACK0,      FN_EX_WAIT0,
+        FN_PWM0_C,      FN_D0,          FN_D1,          FN_D2,
+        FN_D3,          FN_D4,          FN_D5,          FN_D6,
+        FN_D7,          FN_D8,          FN_D9,          FN_D10,
+        FN_D11,         FN_RD_WR_B,     FN_IRQ0,        FN_MLB_CLK,
+        FN_IRQ1_A,
+
+        /* IPSR3 */
+        FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
+        FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
+        FN_SDSELF_B,    FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,
+        FN_CAN_CLK_B,   FN_SDA3_B,      FN_SD1_CLK_B,   FN_HTX0_A,
+        FN_TX0_A,       FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,
+        FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
+        FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        FN_SD1_DAT3_B,
+        FN_HRTS0_A,     FN_RTS0,        FN_SSI_SCK4,    FN_DU0_DR0,
+        FN_LCDOUT0,     FN_AUDATA2,     FN_ARM_TRACEDATA_2,
+        FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,  FN_SSI_WS4,
+        FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,     FN_ARM_TRACEDATA_3,
+        FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
+        FN_DU0_DR2,     FN_LCDOUT2,     FN_DU0_DR3,     FN_LCDOUT3,
+        FN_DU0_DR4,     FN_LCDOUT4,     FN_DU0_DR5,     FN_LCDOUT5,
+        FN_DU0_DR6,     FN_LCDOUT6,
+
+        /* IPSR4 */
+        FN_DU0_DR7,     FN_LCDOUT7,     FN_DU0_DG0,     FN_LCDOUT8,
+        FN_AUDATA4,     FN_ARM_TRACEDATA_4,             FN_TX1_D,
+        FN_CAN0_TX_A,   FN_ADICHS0,     FN_DU0_DG1,     FN_LCDOUT9,
+        FN_AUDATA5,     FN_ARM_TRACEDATA_5,             FN_RX1_D,
+        FN_CAN0_RX_A,   FN_ADIDATA,     FN_DU0_DG2,     FN_LCDOUT10,
+        FN_DU0_DG3,     FN_LCDOUT11,    FN_DU0_DG4,     FN_LCDOUT12,
+        FN_RX0_B,       FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,
+        FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       FN_DU0_DG7,
+        FN_LCDOUT15,    FN_TX4_A,       FN_SSI_SCK2_B,  FN_VI0_R0_B,
+        FN_DU0_DB0,     FN_LCDOUT16,    FN_AUDATA6,     FN_ARM_TRACEDATA_6,
+        FN_GPSCLK_A,    FN_PWM0_A,      FN_ADICLK,      FN_TS_SDAT0_B,
+        FN_AUDIO_CLKC,  FN_VI0_R1_B,    FN_DU0_DB1,     FN_LCDOUT17,
+        FN_AUDATA7,     FN_ARM_TRACEDATA_7,             FN_GPSIN_A,
+        FN_ADICS_SAMP,  FN_TS_SCK0_B,   FN_VI0_R2_B,    FN_DU0_DB2,
+        FN_LCDOUT18,    FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,
+        FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,
+
+        /* IPSR5 */
+        FN_VI0_R5_B,    FN_DU0_DB5,     FN_LCDOUT21,    FN_VI1_DATA10_B,
+        FN_DU0_DB6,     FN_LCDOUT22,    FN_VI1_DATA11_B,
+        FN_DU0_DB7,     FN_LCDOUT23,    FN_DU0_DOTCLKIN,
+        FN_QSTVA_QVS,   FN_DU0_DOTCLKO_UT0,             FN_QCLK,
+        FN_DU0_DOTCLKO_UT1,             FN_QSTVB_QVE,   FN_AUDIO_CLKOUT_A,
+        FN_REMOCON_C,   FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
+        FN_QSTH_QHS,    FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
+        FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,
+        FN_QCPV_QDE,    FN_FMCLK_D,     FN_SSI_SCK1_A,  FN_DU0_DISP,
+        FN_QPOLA,       FN_AUDCK,       FN_ARM_TRACECLK,
+        FN_BPFCLK_D,    FN_SSI_WS1_A,   FN_DU0_CDE,     FN_QPOLB,
+        FN_AUDSYNC,     FN_ARM_TRACECTL,                FN_FMIN_D,
+        FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
+        FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
+        FN_CAN_CLK_D,   FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,
+        FN_TX2_A,       FN_CAN0_TX_B,   FN_SSI_SDATA7,  FN_HSPI_TX0_B,
+        FN_RX2_A,       FN_CAN0_RX_B,
+
+        /* IPSR6 */
+        FN_SSI_SCK6,    FN_HSPI_RX2_A,  FN_FMCLK_B,     FN_CAN1_TX_B,
+        FN_SSI_WS6,     FN_HSPI_CLK2_A, FN_BPFCLK_B,    FN_CAN1_RX_B,
+        FN_SSI_SDATA6,  FN_HSPI_TX2_A,  FN_FMIN_B,      FN_SSI_SCK5,
+        FN_RX4_C,       FN_SSI_WS5,     FN_TX4_C,       FN_SSI_SDATA5,
+        FN_RX0_D,       FN_SSI_WS34,    FN_ARM_TRACEDATA_8,
+        FN_SSI_SDATA4,  FN_SSI_WS2_A,   FN_ARM_TRACEDATA_9,
+        FN_SSI_SDATA3,  FN_ARM_TRACEDATA_10,
+        FN_SSI_SCK012,  FN_ARM_TRACEDATA_11,
+        FN_TX0_D,       FN_SSI_WS012,   FN_ARM_TRACEDATA_12,
+        FN_SSI_SDATA2,  FN_HSPI_CS2_A,  FN_ARM_TRACEDATA_13,
+        FN_SDA1_A,      FN_SSI_SDATA1,  FN_ARM_TRACEDATA_14,
+        FN_SCL1_A,      FN_SCK2_A,      FN_SSI_SDATA0,
+        FN_ARM_TRACEDATA_15,
+        FN_SD0_CLK,     FN_SUB_TDO,     FN_SD0_CMD,     FN_SUB_TRST,
+        FN_SD0_DAT0,    FN_SUB_TMS,     FN_SD0_DAT1,    FN_SUB_TCK,
+        FN_SD0_DAT2,    FN_SUB_TDI,
+
+        /* IPSR7 */
+        FN_SD0_DAT3,    FN_IRQ1_B,      FN_SD0_CD,      FN_TX5_A,
+        FN_SD0_WP,      FN_RX5_A,       FN_VI1_CLKENB,  FN_HSPI_CLK0_A,
+        FN_HTX1_A,      FN_RTS1_C,      FN_VI1_FIELD,   FN_HSPI_CS0_A,
+        FN_HRX1_A,      FN_SCK1_C,      FN_VI1_HSYNC,   FN_HSPI_RX0_A,
+        FN_HRTS1_A,     FN_FMCLK_A,     FN_RX1_C,       FN_VI1_VSYNC,
+        FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,    FN_TX1_C,
+        FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      FN_IRQ2_C,
+        FN_CTS1_C,      FN_SPEEDIN,     FN_VI0_CLK,     FN_CAN_CLK_A,
+        FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
+        FN_HSPI_RX1_A,  FN_RX4_B,       FN_VI0_FIELD,   FN_SD2_DAT3_B,
+        FN_VI0_R3_C,    FN_VI1_DATA1,   FN_DU1_DG7,     FN_HSPI_CLK1_A,
+        FN_TX4_B,       FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,
+        FN_DU1_DR2,     FN_HSPI_CS1_A,  FN_RX3_B,
+
+        /* IPSR8 */
+        FN_VI0_VSYNC,   FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
+        FN_HSPI_TX1_A,  FN_TX3_B,       FN_VI0_DATA0_VI0_B0,
+        FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,       FN_VI0_DATA1_VI0_B1,
+        FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,       FN_VI0_DATA2_VI0_B2,
+        FN_DU1_DG4,     FN_RX0_C,       FN_VI0_DATA3_VI0_B3,
+        FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,       FN_VI0_DATA4_VI0_B4,
+        FN_DU1_DB2,     FN_RX1_A,       FN_VI0_DATA5_VI0_B5,
+        FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,        FN_HSCK1_B,
+        FN_VI0_DATA6_VI0_G0,            FN_DU1_DB4,     FN_CTS1_A,
+        FN_PWM5,        FN_VI0_DATA7_VI0_G1,            FN_DU1_DB5,
+        FN_RTS1_A,      FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,
+        FN_DU1_DR4,     FN_HTX1_B,      FN_VI0_G3,      FN_SD2_CMD_B,
+        FN_VI1_DATA5,   FN_DU1_DR5,     FN_HRX1_B,
+
+        /* IPSR9 */
+        FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
+        FN_HRTS1_B,     FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,
+        FN_DU1_DR7,     FN_HCTS1_B,     FN_VI0_R0_A,    FN_VI1_CLK,
+        FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,                FN_VI0_R1_A,
+        FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,    FN_PWM2,
+        FN_TCLK1,       FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,
+        FN_ETH_TXD1,    FN_PWM3,        FN_VI0_R3_A,    FN_ETH_CRS_DV,
+        FN_IECLK,       FN_SCK2_C,      FN_VI0_R4_A,    FN_ETH_TX_EN,
+        FN_IETX,        FN_TX2_C,       FN_VI0_R5_A,    FN_ETH_RX_ER,
+        FN_FMCLK_C,     FN_IERX,        FN_RX2_C,       FN_VI1_DATA10_A,
+        FN_DU1_DOTCLKOUT,               FN_ETH_RXD0,    FN_BPFCLK_C,
+        FN_TX2_D,       FN_SDA2_C,      FN_VI1_DATA11_A,
+        FN_DU1_EXHSYNC_DU1_HSYNC,       FN_ETH_RXD1,    FN_FMIN_C,
+        FN_RX2_D,       FN_SCL2_C,
+
+        /* IPSR10 */
+        FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,       FN_ATARD1,
+        FN_ETH_MDC,     FN_SDA1_B,      FN_SD2_CMD_A,
+        FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,                FN_ATAWR1,
+        FN_ETH_MDIO,    FN_SCL1_B,      FN_SD2_DAT0_A,  FN_DU1_DISP,
+        FN_ATACS01,     FN_DREQ1_B,     FN_ETH_LINK,    FN_CAN1_RX_A,
+        FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
+        FN_ETH_MAGIC,   FN_CAN1_TX_A,   FN_PWM6,        FN_SD2_DAT2_A,
+        FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,     FN_HSPI_CLK2_B,
+        FN_GPSCLK_B,    FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,
+        FN_ATAG1,       FN_HSPI_CS2_B,  FN_GPSIN_B,     FN_SD2_CD_A,
+        FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,     FN_HSPI_RX2_B,
+        FN_REMOCON_A,   FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,
+        FN_DACK0_B,     FN_HSPI_TX2_B,  FN_CAN_CLK_C,
+
+        /* SEL */
+        FN_SEL_SCIF5_A, FN_SEL_SCIF5_B,
+        FN_SEL_SCIF4_A, FN_SEL_SCIF4_B, FN_SEL_SCIF4_C,
+        FN_SEL_SCIF3_A, FN_SEL_SCIF3_B, FN_SEL_SCIF3_C, FN_SEL_SCIF3_D,
+        FN_SEL_SCIF2_A, FN_SEL_SCIF2_B, FN_SEL_SCIF2_C, FN_SEL_SCIF2_D, FN_SEL_SCIF2_E,
+        FN_SEL_SCIF1_A, FN_SEL_SCIF1_B, FN_SEL_SCIF1_C, FN_SEL_SCIF1_D,
+        FN_SEL_SCIF0_A, FN_SEL_SCIF0_B, FN_SEL_SCIF0_C, FN_SEL_SCIF0_D,
+        FN_SEL_SSI2_A,  FN_SEL_SSI2_B,
+        FN_SEL_SSI1_A,  FN_SEL_SSI1_B,
+        FN_SEL_VI1_A,   FN_SEL_VI1_B,
+        FN_SEL_VI0_A,   FN_SEL_VI0_B,   FN_SEL_VI0_C,   FN_SEL_VI0_D,
+        FN_SEL_SD2_A,   FN_SEL_SD2_B,
+        FN_SEL_SD1_A,   FN_SEL_SD1_B,
+        FN_SEL_IRQ3_A,  FN_SEL_IRQ3_B,
+        FN_SEL_IRQ2_A,  FN_SEL_IRQ2_B,  FN_SEL_IRQ2_C,
+        FN_SEL_IRQ1_A,  FN_SEL_IRQ1_B,
+        FN_SEL_DREQ2_A, FN_SEL_DREQ2_B,
+        FN_SEL_DREQ1_A, FN_SEL_DREQ1_B,
+        FN_SEL_DREQ0_A, FN_SEL_DREQ0_B,
+        FN_SEL_WAIT2_A, FN_SEL_WAIT2_B,
+        FN_SEL_WAIT1_A, FN_SEL_WAIT1_B,
+        FN_SEL_CAN1_A,  FN_SEL_CAN1_B,
+        FN_SEL_CAN0_A,  FN_SEL_CAN0_B,
+        FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
+        FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
+        FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
+        FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
+        FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,       FN_SEL_REMOCON_C,
+        FN_SEL_FM_A,    FN_SEL_FM_B,    FN_SEL_FM_C,    FN_SEL_FM_D,
+        FN_SEL_GPS_A,   FN_SEL_GPS_B,   FN_SEL_GPS_C,
+        FN_SEL_TSIF0_A, FN_SEL_TSIF0_B,
+        FN_SEL_HSPI2_A, FN_SEL_HSPI2_B,
+        FN_SEL_HSPI1_A, FN_SEL_HSPI1_B,
+        FN_SEL_HSPI0_A, FN_SEL_HSPI0_B,
+        FN_SEL_I2C3_A,  FN_SEL_I2C3_B,  FN_SEL_I2C3_C,
+        FN_SEL_I2C2_A,  FN_SEL_I2C2_B,  FN_SEL_I2C2_C,
+        FN_SEL_I2C1_A,  FN_SEL_I2C1_B,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        /* GPSR0 */
+        PENC0_MARK,     PENC1_MARK,     A1_MARK,        A2_MARK,        A3_MARK,
+
+        /* GPSR1 */
+        WE0_MARK,
+
+        /* GPSR2 */
+        AUDIO_CLKA_MARK,
+        AUDIO_CLKB_MARK,
+
+        /* GPSR3 */
+        SSI_SCK34_MARK,
+
+        /* GPSR4 */
+        AVS1_MARK,
+        AVS2_MARK,
+
+        VI0_R0_C_MARK,          /* see sel_vi0 */
+        VI0_R1_C_MARK,          /* see sel_vi0 */
+        VI0_R2_C_MARK,          /* see sel_vi0 */
+        /* VI0_R3_C_MARK, */
+        VI0_R4_C_MARK,          /* see sel_vi0 */
+        VI0_R5_C_MARK,          /* see sel_vi0 */
+
+        VI0_R0_D_MARK,          /* see sel_vi0 */
+        VI0_R1_D_MARK,          /* see sel_vi0 */
+        VI0_R2_D_MARK,          /* see sel_vi0 */
+        VI0_R3_D_MARK,          /* see sel_vi0 */
+        VI0_R4_D_MARK,          /* see sel_vi0 */
+        VI0_R5_D_MARK,          /* see sel_vi0 */
+
+        /* IPSR0 */
+        PRESETOUT_MARK, PWM1_MARK,      AUDATA0_MARK,
+        ARM_TRACEDATA_0_MARK,           GPSCLK_C_MARK,  USB_OVC0_MARK,
+        TX2_E_MARK,     SDA2_B_MARK,    AUDATA1_MARK,   ARM_TRACEDATA_1_MARK,
+        GPSIN_C_MARK,   USB_OVC1_MARK,  RX2_E_MARK,     SCL2_B_MARK,
+        SD1_DAT2_A_MARK,                MMC_D2_MARK,    BS_MARK,
+        ATADIR0_A_MARK, SDSELF_A_MARK,  PWM4_B_MARK,    SD1_DAT3_A_MARK,
+        MMC_D3_MARK,    A0_MARK,        ATAG0_A_MARK,   REMOCON_B_MARK,
+        A4_MARK,        A5_MARK,        A6_MARK,        A7_MARK,
+        A8_MARK,        A9_MARK,        A10_MARK,       A11_MARK,
+        A12_MARK,       A13_MARK,       A14_MARK,       A15_MARK,
+        A16_MARK,       A17_MARK,       A18_MARK,       A19_MARK,
+
+        /* IPSR1 */
+        A20_MARK,       HSPI_CS1_B_MARK,                A21_MARK,
+        HSPI_CLK1_B_MARK,               A22_MARK,       HRTS0_B_MARK,
+        RX2_B_MARK,     DREQ2_A_MARK,   A23_MARK,       HTX0_B_MARK,
+        TX2_B_MARK,     DACK2_A_MARK,   TS_SDEN0_A_MARK,
+        SD1_CD_A_MARK,  MMC_D6_MARK,    A24_MARK,       DREQ1_A_MARK,
+        HRX0_B_MARK,    TS_SPSYNC0_A_MARK,              SD1_WP_A_MARK,
+        MMC_D7_MARK,    A25_MARK,       DACK1_A_MARK,   HCTS0_B_MARK,
+        RX3_C_MARK,     TS_SDAT0_A_MARK,                CLKOUT_MARK,
+        HSPI_TX1_B_MARK,                PWM0_B_MARK,    CS0_MARK,
+        HSPI_RX1_B_MARK,                SSI_SCK1_B_MARK,
+        ATAG0_B_MARK,   CS1_A26_MARK,   SDA2_A_MARK,    SCK2_B_MARK,
+        MMC_D5_MARK,    ATADIR0_B_MARK, RD_WR_MARK,     WE1_MARK,
+        ATAWR0_B_MARK,  SSI_WS1_B_MARK, EX_CS0_MARK,    SCL2_A_MARK,
+        TX3_C_MARK,     TS_SCK0_A_MARK, EX_CS1_MARK,    MMC_D4_MARK,
+
+        /* IPSR2 */
+        SD1_CLK_A_MARK, MMC_CLK_MARK,   ATACS00_MARK,   EX_CS2_MARK,
+        SD1_CMD_A_MARK, MMC_CMD_MARK,   ATACS10_MARK,   EX_CS3_MARK,
+        SD1_DAT0_A_MARK,                MMC_D0_MARK,    ATARD0_MARK,
+        EX_CS4_MARK,    EX_WAIT1_A_MARK,                SD1_DAT1_A_MARK,
+        MMC_D1_MARK,    ATAWR0_A_MARK,  EX_CS5_MARK,    EX_WAIT2_A_MARK,
+        DREQ0_A_MARK,   RX3_A_MARK,     DACK0_MARK,     TX3_A_MARK,
+        DRACK0_MARK,    EX_WAIT0_MARK,  PWM0_C_MARK,    D0_MARK,
+        D1_MARK,        D2_MARK,        D3_MARK,        D4_MARK,
+        D5_MARK,        D6_MARK,        D7_MARK,        D8_MARK,
+        D9_MARK,        D10_MARK,       D11_MARK,       RD_WR_B_MARK,
+        IRQ0_MARK,      MLB_CLK_MARK,   IRQ1_A_MARK,
+
+        /* IPSR3 */
+        MLB_SIG_MARK,   RX5_B_MARK,     SDA3_A_MARK,    IRQ2_A_MARK,
+        MLB_DAT_MARK,   TX5_B_MARK,     SCL3_A_MARK,    IRQ3_A_MARK,
+        SDSELF_B_MARK,  SD1_CMD_B_MARK, SCIF_CLK_MARK,  AUDIO_CLKOUT_B_MARK,
+        CAN_CLK_B_MARK, SDA3_B_MARK,    SD1_CLK_B_MARK, HTX0_A_MARK,
+        TX0_A_MARK,     SD1_DAT0_B_MARK,                HRX0_A_MARK,
+        RX0_A_MARK,     SD1_DAT1_B_MARK,                HSCK0_MARK,
+        SCK0_MARK,      SCL3_B_MARK,    SD1_DAT2_B_MARK,
+        HCTS0_A_MARK,   CTS0_MARK,      SD1_DAT3_B_MARK,
+        HRTS0_A_MARK,   RTS0_MARK,      SSI_SCK4_MARK,
+        DU0_DR0_MARK,   LCDOUT0_MARK,   AUDATA2_MARK,   ARM_TRACEDATA_2_MARK,
+        SDA3_C_MARK,    ADICHS1_MARK,   TS_SDEN0_B_MARK,
+        SSI_WS4_MARK,   DU0_DR1_MARK,   LCDOUT1_MARK,   AUDATA3_MARK,
+        ARM_TRACEDATA_3_MARK,           SCL3_C_MARK,    ADICHS2_MARK,
+        TS_SPSYNC0_B_MARK,              DU0_DR2_MARK,   LCDOUT2_MARK,
+        DU0_DR3_MARK,   LCDOUT3_MARK,   DU0_DR4_MARK,   LCDOUT4_MARK,
+        DU0_DR5_MARK,   LCDOUT5_MARK,   DU0_DR6_MARK,   LCDOUT6_MARK,
+
+        /* IPSR4 */
+        DU0_DR7_MARK,   LCDOUT7_MARK,   DU0_DG0_MARK,   LCDOUT8_MARK,
+        AUDATA4_MARK,   ARM_TRACEDATA_4_MARK,
+        TX1_D_MARK,     CAN0_TX_A_MARK, ADICHS0_MARK,   DU0_DG1_MARK,
+        LCDOUT9_MARK,   AUDATA5_MARK,   ARM_TRACEDATA_5_MARK,
+        RX1_D_MARK,     CAN0_RX_A_MARK, ADIDATA_MARK,   DU0_DG2_MARK,
+        LCDOUT10_MARK,  DU0_DG3_MARK,   LCDOUT11_MARK,  DU0_DG4_MARK,
+        LCDOUT12_MARK,  RX0_B_MARK,     DU0_DG5_MARK,   LCDOUT13_MARK,
+        TX0_B_MARK,     DU0_DG6_MARK,   LCDOUT14_MARK,  RX4_A_MARK,
+        DU0_DG7_MARK,   LCDOUT15_MARK,  TX4_A_MARK,     SSI_SCK2_B_MARK,
+        VI0_R0_B_MARK,  DU0_DB0_MARK,   LCDOUT16_MARK,  AUDATA6_MARK,
+        ARM_TRACEDATA_6_MARK,           GPSCLK_A_MARK,  PWM0_A_MARK,
+        ADICLK_MARK,    TS_SDAT0_B_MARK,                AUDIO_CLKC_MARK,
+        VI0_R1_B_MARK,  DU0_DB1_MARK,   LCDOUT17_MARK,  AUDATA7_MARK,
+        ARM_TRACEDATA_7_MARK,           GPSIN_A_MARK,   ADICS_SAMP_MARK,
+        TS_SCK0_B_MARK, VI0_R2_B_MARK,  DU0_DB2_MARK,   LCDOUT18_MARK,
+        VI0_R3_B_MARK,  DU0_DB3_MARK,   LCDOUT19_MARK,  VI0_R4_B_MARK,
+        DU0_DB4_MARK,   LCDOUT20_MARK,
+
+        /* IPSR5 */
+        VI0_R5_B_MARK,  DU0_DB5_MARK,   LCDOUT21_MARK,  VI1_DATA10_B_MARK,
+        DU0_DB6_MARK,   LCDOUT22_MARK,  VI1_DATA11_B_MARK,
+        DU0_DB7_MARK,   LCDOUT23_MARK,  DU0_DOTCLKIN_MARK,
+        QSTVA_QVS_MARK, DU0_DOTCLKO_UT0_MARK,
+        QCLK_MARK,      DU0_DOTCLKO_UT1_MARK,           QSTVB_QVE_MARK,
+        AUDIO_CLKOUT_A_MARK,            REMOCON_C_MARK, SSI_WS2_B_MARK,
+        DU0_EXHSYNC_DU0_HSYNC_MARK,     QSTH_QHS_MARK,
+        DU0_EXVSYNC_DU0_VSYNC_MARK,     QSTB_QHE_MARK,
+        DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK,
+        QCPV_QDE_MARK,  FMCLK_D_MARK,   SSI_SCK1_A_MARK,
+        DU0_DISP_MARK,  QPOLA_MARK,     AUDCK_MARK,     ARM_TRACECLK_MARK,
+        BPFCLK_D_MARK,  SSI_WS1_A_MARK, DU0_CDE_MARK,   QPOLB_MARK,
+        AUDSYNC_MARK,   ARM_TRACECTL_MARK,              FMIN_D_MARK,
+        SD1_CD_B_MARK,  SSI_SCK78_MARK, HSPI_RX0_B_MARK,
+        TX1_B_MARK,     SD1_WP_B_MARK,  SSI_WS78_MARK,  HSPI_CLK0_B_MARK,
+        RX1_B_MARK,     CAN_CLK_D_MARK, SSI_SDATA8_MARK,
+        SSI_SCK2_A_MARK,                HSPI_CS0_B_MARK,
+        TX2_A_MARK,     CAN0_TX_B_MARK, SSI_SDATA7_MARK,
+        HSPI_TX0_B_MARK,                RX2_A_MARK,     CAN0_RX_B_MARK,
+
+        /* IPSR6 */
+        SSI_SCK6_MARK,  HSPI_RX2_A_MARK,                FMCLK_B_MARK,
+        CAN1_TX_B_MARK, SSI_WS6_MARK,   HSPI_CLK2_A_MARK,
+        BPFCLK_B_MARK,  CAN1_RX_B_MARK, SSI_SDATA6_MARK,
+        HSPI_TX2_A_MARK,                FMIN_B_MARK,    SSI_SCK5_MARK,
+        RX4_C_MARK,     SSI_WS5_MARK,   TX4_C_MARK,     SSI_SDATA5_MARK,
+        RX0_D_MARK,     SSI_WS34_MARK,  ARM_TRACEDATA_8_MARK,
+        SSI_SDATA4_MARK,                SSI_WS2_A_MARK, ARM_TRACEDATA_9_MARK,
+        SSI_SDATA3_MARK,                ARM_TRACEDATA_10_MARK,
+        SSI_SCK012_MARK,                ARM_TRACEDATA_11_MARK,
+        TX0_D_MARK,     SSI_WS012_MARK, ARM_TRACEDATA_12_MARK,
+        SSI_SDATA2_MARK,                HSPI_CS2_A_MARK,
+        ARM_TRACEDATA_13_MARK,          SDA1_A_MARK,    SSI_SDATA1_MARK,
+        ARM_TRACEDATA_14_MARK,          SCL1_A_MARK,    SCK2_A_MARK,
+        SSI_SDATA0_MARK,                ARM_TRACEDATA_15_MARK,
+        SD0_CLK_MARK,   SUB_TDO_MARK,   SD0_CMD_MARK,   SUB_TRST_MARK,
+        SD0_DAT0_MARK,  SUB_TMS_MARK,   SD0_DAT1_MARK,  SUB_TCK_MARK,
+        SD0_DAT2_MARK,  SUB_TDI_MARK,
+
+        /* IPSR7 */
+        SD0_DAT3_MARK,  IRQ1_B_MARK,    SD0_CD_MARK,    TX5_A_MARK,
+        SD0_WP_MARK,    RX5_A_MARK,     VI1_CLKENB_MARK,
+        HSPI_CLK0_A_MARK,       HTX1_A_MARK,    RTS1_C_MARK,    VI1_FIELD_MARK,
+        HSPI_CS0_A_MARK,        HRX1_A_MARK,    SCK1_C_MARK,    VI1_HSYNC_MARK,
+        HSPI_RX0_A_MARK,        HRTS1_A_MARK,   FMCLK_A_MARK,   RX1_C_MARK,
+        VI1_VSYNC_MARK, HSPI_TX0_MARK,  HCTS1_A_MARK,   BPFCLK_A_MARK,
+        TX1_C_MARK,     TCLK0_MARK,     HSCK1_A_MARK,   FMIN_A_MARK,
+        IRQ2_C_MARK,    CTS1_C_MARK,    SPEEDIN_MARK,   VI0_CLK_MARK,
+        CAN_CLK_A_MARK, VI0_CLKENB_MARK,                SD2_DAT2_B_MARK,
+        VI1_DATA0_MARK, DU1_DG6_MARK,   HSPI_RX1_A_MARK,
+        RX4_B_MARK,     VI0_FIELD_MARK, SD2_DAT3_B_MARK,
+        VI0_R3_C_MARK,  VI1_DATA1_MARK, DU1_DG7_MARK,   HSPI_CLK1_A_MARK,
+        TX4_B_MARK,     VI0_HSYNC_MARK, SD2_CD_B_MARK,  VI1_DATA2_MARK,
+        DU1_DR2_MARK,   HSPI_CS1_A_MARK,                RX3_B_MARK,
+
+        /* IPSR8 */
+        VI0_VSYNC_MARK, SD2_WP_B_MARK,  VI1_DATA3_MARK, DU1_DR3_MARK,
+        HSPI_TX1_A_MARK,                TX3_B_MARK,     VI0_DATA0_VI0_B0_MARK,
+        DU1_DG2_MARK,   IRQ2_B_MARK,    RX3_D_MARK,     VI0_DATA1_VI0_B1_MARK,
+        DU1_DG3_MARK,   IRQ3_B_MARK,    TX3_D_MARK,     VI0_DATA2_VI0_B2_MARK,
+        DU1_DG4_MARK,   RX0_C_MARK,     VI0_DATA3_VI0_B3_MARK,
+        DU1_DG5_MARK,   TX1_A_MARK,     TX0_C_MARK,     VI0_DATA4_VI0_B4_MARK,
+        DU1_DB2_MARK,   RX1_A_MARK,     VI0_DATA5_VI0_B5_MARK,
+        DU1_DB3_MARK,   SCK1_A_MARK,    PWM4_MARK,      HSCK1_B_MARK,
+        VI0_DATA6_VI0_G0_MARK,          DU1_DB4_MARK,   CTS1_A_MARK,
+        PWM5_MARK,      VI0_DATA7_VI0_G1_MARK,          DU1_DB5_MARK,
+        RTS1_A_MARK,    VI0_G2_MARK,    SD2_CLK_B_MARK, VI1_DATA4_MARK,
+        DU1_DR4_MARK,   HTX1_B_MARK,    VI0_G3_MARK,    SD2_CMD_B_MARK,
+        VI1_DATA5_MARK, DU1_DR5_MARK,   HRX1_B_MARK,
+
+        /* IPSR9 */
+        VI0_G4_MARK,    SD2_DAT0_B_MARK,                VI1_DATA6_MARK,
+        DU1_DR6_MARK,   HRTS1_B_MARK,   VI0_G5_MARK,    SD2_DAT1_B_MARK,
+        VI1_DATA7_MARK, DU1_DR7_MARK,   HCTS1_B_MARK,   VI0_R0_A_MARK,
+        VI1_CLK_MARK,   ETH_REF_CLK_MARK,               DU1_DOTCLKIN_MARK,
+        VI0_R1_A_MARK,  VI1_DATA8_MARK, DU1_DB6_MARK,   ETH_TXD0_MARK,
+        PWM2_MARK,      TCLK1_MARK,     VI0_R2_A_MARK,  VI1_DATA9_MARK,
+        DU1_DB7_MARK,   ETH_TXD1_MARK,  PWM3_MARK,      VI0_R3_A_MARK,
+        ETH_CRS_DV_MARK,                IECLK_MARK,     SCK2_C_MARK,
+        VI0_R4_A_MARK,                  ETH_TX_EN_MARK, IETX_MARK,
+        TX2_C_MARK,     VI0_R5_A_MARK,  ETH_RX_ER_MARK, FMCLK_C_MARK,
+        IERX_MARK,      RX2_C_MARK,     VI1_DATA10_A_MARK,
+        DU1_DOTCLKOUT_MARK,             ETH_RXD0_MARK,
+        BPFCLK_C_MARK,  TX2_D_MARK,     SDA2_C_MARK,    VI1_DATA11_A_MARK,
+        DU1_EXHSYNC_DU1_HSYNC_MARK,     ETH_RXD1_MARK,  FMIN_C_MARK,
+        RX2_D_MARK,     SCL2_C_MARK,
+
+        /* IPSR10 */
+        SD2_CLK_A_MARK, DU1_EXVSYNC_DU1_VSYNC_MARK,     ATARD1_MARK,
+        ETH_MDC_MARK,   SDA1_B_MARK,    SD2_CMD_A_MARK,
+        DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,              ATAWR1_MARK,
+        ETH_MDIO_MARK,  SCL1_B_MARK,    SD2_DAT0_A_MARK,
+        DU1_DISP_MARK,  ATACS01_MARK,   DREQ1_B_MARK,   ETH_LINK_MARK,
+        CAN1_RX_A_MARK, SD2_DAT1_A_MARK,                DU1_CDE_MARK,
+        ATACS11_MARK,   DACK1_B_MARK,   ETH_MAGIC_MARK, CAN1_TX_A_MARK,
+        PWM6_MARK,      SD2_DAT2_A_MARK,                VI1_DATA12_MARK,
+        DREQ2_B_MARK,   ATADIR1_MARK,   HSPI_CLK2_B_MARK,
+        GPSCLK_B_MARK,  SD2_DAT3_A_MARK,                VI1_DATA13_MARK,
+        DACK2_B_MARK,   ATAG1_MARK,     HSPI_CS2_B_MARK,
+        GPSIN_B_MARK,   SD2_CD_A_MARK,  VI1_DATA14_MARK,
+        EX_WAIT1_B_MARK,                DREQ0_B_MARK,   HSPI_RX2_B_MARK,
+        REMOCON_A_MARK, SD2_WP_A_MARK,  VI1_DATA15_MARK,
+        EX_WAIT2_B_MARK,                DACK0_B_MARK,
+        HSPI_TX2_B_MARK,                CAN_CLK_C_MARK,
+
+        PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_DATA(PENC0_MARK,         FN_PENC0),
+        PINMUX_DATA(PENC1_MARK,         FN_PENC1),
+        PINMUX_DATA(A1_MARK,            FN_A1),
+        PINMUX_DATA(A2_MARK,            FN_A2),
+        PINMUX_DATA(A3_MARK,            FN_A3),
+        PINMUX_DATA(WE0_MARK,           FN_WE0),
+        PINMUX_DATA(AUDIO_CLKA_MARK,    FN_AUDIO_CLKA),
+        PINMUX_DATA(AUDIO_CLKB_MARK,    FN_AUDIO_CLKB),
+        PINMUX_DATA(SSI_SCK34_MARK,     FN_SSI_SCK34),
+        PINMUX_DATA(AVS1_MARK,          FN_AVS1),
+        PINMUX_DATA(AVS2_MARK,          FN_AVS2),
+
+        /* IPSR0 */
+        PINMUX_IPSR_DATA(IP0_1_0,       PRESETOUT),
+        PINMUX_IPSR_DATA(IP0_1_0,       PWM1),
+
+        PINMUX_IPSR_DATA(IP0_4_2,       AUDATA0),
+        PINMUX_IPSR_DATA(IP0_4_2,       ARM_TRACEDATA_0),
+        PINMUX_IPSR_MSEL(IP0_4_2,       GPSCLK_C,       SEL_GPS_C),
+        PINMUX_IPSR_DATA(IP0_4_2,       USB_OVC0),
+        PINMUX_IPSR_DATA(IP0_4_2,       TX2_E),
+        PINMUX_IPSR_MSEL(IP0_4_2,       SDA2_B,         SEL_I2C2_B),
+
+        PINMUX_IPSR_DATA(IP0_7_5,       AUDATA1),
+        PINMUX_IPSR_DATA(IP0_7_5,       ARM_TRACEDATA_1),
+        PINMUX_IPSR_MSEL(IP0_7_5,       GPSIN_C,        SEL_GPS_C),
+        PINMUX_IPSR_DATA(IP0_7_5,       USB_OVC1),
+        PINMUX_IPSR_MSEL(IP0_7_5,       RX2_E,          SEL_SCIF2_E),
+        PINMUX_IPSR_MSEL(IP0_7_5,       SCL2_B,         SEL_I2C2_B),
+
+        PINMUX_IPSR_MSEL(IP0_11_8,      SD1_DAT2_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      MMC_D2),
+        PINMUX_IPSR_DATA(IP0_11_8,      BS),
+        PINMUX_IPSR_DATA(IP0_11_8,      ATADIR0_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      SDSELF_A),
+        PINMUX_IPSR_DATA(IP0_11_8,      PWM4_B),
+
+        PINMUX_IPSR_MSEL(IP0_14_12,     SD1_DAT3_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP0_14_12,     MMC_D3),
+        PINMUX_IPSR_DATA(IP0_14_12,     A0),
+        PINMUX_IPSR_DATA(IP0_14_12,     ATAG0_A),
+        PINMUX_IPSR_MSEL(IP0_14_12,     REMOCON_B,      SEL_REMOCON_B),
+
+        PINMUX_IPSR_DATA(IP0_15,        A4),
+        PINMUX_IPSR_DATA(IP0_16,        A5),
+        PINMUX_IPSR_DATA(IP0_17,        A6),
+        PINMUX_IPSR_DATA(IP0_18,        A7),
+        PINMUX_IPSR_DATA(IP0_19,        A8),
+        PINMUX_IPSR_DATA(IP0_20,        A9),
+        PINMUX_IPSR_DATA(IP0_21,        A10),
+        PINMUX_IPSR_DATA(IP0_22,        A11),
+        PINMUX_IPSR_DATA(IP0_23,        A12),
+        PINMUX_IPSR_DATA(IP0_24,        A13),
+        PINMUX_IPSR_DATA(IP0_25,        A14),
+        PINMUX_IPSR_DATA(IP0_26,        A15),
+        PINMUX_IPSR_DATA(IP0_27,        A16),
+        PINMUX_IPSR_DATA(IP0_28,        A17),
+        PINMUX_IPSR_DATA(IP0_29,        A18),
+        PINMUX_IPSR_DATA(IP0_30,        A19),
+
+        /* IPSR1 */
+        PINMUX_IPSR_DATA(IP1_0,         A20),
+        PINMUX_IPSR_MSEL(IP1_0,         HSPI_CS1_B,     SEL_HSPI1_B),
+
+        PINMUX_IPSR_DATA(IP1_1,         A21),
+        PINMUX_IPSR_MSEL(IP1_1,         HSPI_CLK1_B,    SEL_HSPI1_B),
+
+        PINMUX_IPSR_DATA(IP1_4_2,       A22),
+        PINMUX_IPSR_MSEL(IP1_4_2,       HRTS0_B,        SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_4_2,       RX2_B,          SEL_SCIF2_B),
+        PINMUX_IPSR_MSEL(IP1_4_2,       DREQ2_A,        SEL_DREQ2_A),
+
+        PINMUX_IPSR_DATA(IP1_7_5,       A23),
+        PINMUX_IPSR_DATA(IP1_7_5,       HTX0_B),
+        PINMUX_IPSR_DATA(IP1_7_5,       TX2_B),
+        PINMUX_IPSR_DATA(IP1_7_5,       DACK2_A),
+        PINMUX_IPSR_MSEL(IP1_7_5,       TS_SDEN0_A,     SEL_TSIF0_A),
+
+        PINMUX_IPSR_MSEL(IP1_10_8,      SD1_CD_A,       SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP1_10_8,      MMC_D6),
+        PINMUX_IPSR_DATA(IP1_10_8,      A24),
+        PINMUX_IPSR_MSEL(IP1_10_8,      DREQ1_A,        SEL_DREQ1_A),
+        PINMUX_IPSR_MSEL(IP1_10_8,      HRX0_B,         SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_10_8,      TS_SPSYNC0_A,   SEL_TSIF0_A),
+
+        PINMUX_IPSR_MSEL(IP1_14_11,     SD1_WP_A,       SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP1_14_11,     MMC_D7),
+        PINMUX_IPSR_DATA(IP1_14_11,     A25),
+        PINMUX_IPSR_DATA(IP1_14_11,     DACK1_A),
+        PINMUX_IPSR_MSEL(IP1_14_11,     HCTS0_B,        SEL_HSCIF0_B),
+        PINMUX_IPSR_MSEL(IP1_14_11,     RX3_C,          SEL_SCIF3_C),
+        PINMUX_IPSR_MSEL(IP1_14_11,     TS_SDAT0_A,     SEL_TSIF0_A),
+
+        PINMUX_IPSR_NOGP(IP1_16_15,     CLKOUT),
+        PINMUX_IPSR_NOGP(IP1_16_15,     HSPI_TX1_B),
+        PINMUX_IPSR_NOGP(IP1_16_15,     PWM0_B),
+
+        PINMUX_IPSR_NOGP(IP1_17,        CS0),
+        PINMUX_IPSR_NOGM(IP1_17,        HSPI_RX1_B,     SEL_HSPI1_B),
+
+        PINMUX_IPSR_NOGM(IP1_20_18,     SSI_SCK1_B,     SEL_SSI1_B),
+        PINMUX_IPSR_NOGP(IP1_20_18,     ATAG0_B),
+        PINMUX_IPSR_NOGP(IP1_20_18,     CS1_A26),
+        PINMUX_IPSR_NOGM(IP1_20_18,     SDA2_A,         SEL_I2C2_A),
+        PINMUX_IPSR_NOGM(IP1_20_18,     SCK2_B,         SEL_SCIF2_B),
+
+        PINMUX_IPSR_DATA(IP1_23_21,     MMC_D5),
+        PINMUX_IPSR_DATA(IP1_23_21,     ATADIR0_B),
+        PINMUX_IPSR_DATA(IP1_23_21,     RD_WR),
+
+        PINMUX_IPSR_DATA(IP1_24,        WE1),
+        PINMUX_IPSR_DATA(IP1_24,        ATAWR0_B),
+
+        PINMUX_IPSR_MSEL(IP1_27_25,     SSI_WS1_B,      SEL_SSI1_B),
+        PINMUX_IPSR_DATA(IP1_27_25,     EX_CS0),
+        PINMUX_IPSR_MSEL(IP1_27_25,     SCL2_A,         SEL_I2C2_A),
+        PINMUX_IPSR_DATA(IP1_27_25,     TX3_C),
+        PINMUX_IPSR_MSEL(IP1_27_25,     TS_SCK0_A,      SEL_TSIF0_A),
+
+        PINMUX_IPSR_DATA(IP1_29_28,     EX_CS1),
+        PINMUX_IPSR_DATA(IP1_29_28,     MMC_D4),
+
+        /* IPSR2 */
+        PINMUX_IPSR_DATA(IP2_2_0,       SD1_CLK_A),
+        PINMUX_IPSR_DATA(IP2_2_0,       MMC_CLK),
+        PINMUX_IPSR_DATA(IP2_2_0,       ATACS00),
+        PINMUX_IPSR_DATA(IP2_2_0,       EX_CS2),
+
+        PINMUX_IPSR_MSEL(IP2_5_3,       SD1_CMD_A,      SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_5_3,       MMC_CMD),
+        PINMUX_IPSR_DATA(IP2_5_3,       ATACS10),
+        PINMUX_IPSR_DATA(IP2_5_3,       EX_CS3),
+
+        PINMUX_IPSR_MSEL(IP2_8_6,       SD1_DAT0_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_8_6,       MMC_D0),
+        PINMUX_IPSR_DATA(IP2_8_6,       ATARD0),
+        PINMUX_IPSR_DATA(IP2_8_6,       EX_CS4),
+        PINMUX_IPSR_MSEL(IP2_8_6,       EX_WAIT1_A,     SEL_WAIT1_A),
+
+        PINMUX_IPSR_MSEL(IP2_11_9,      SD1_DAT1_A,     SEL_SD1_A),
+        PINMUX_IPSR_DATA(IP2_11_9,      MMC_D1),
+        PINMUX_IPSR_DATA(IP2_11_9,      ATAWR0_A),
+        PINMUX_IPSR_DATA(IP2_11_9,      EX_CS5),
+        PINMUX_IPSR_MSEL(IP2_11_9,      EX_WAIT2_A,     SEL_WAIT2_A),
+
+        PINMUX_IPSR_MSEL(IP2_13_12,     DREQ0_A,        SEL_DREQ0_A),
+        PINMUX_IPSR_MSEL(IP2_13_12,     RX3_A,          SEL_SCIF3_A),
+
+        PINMUX_IPSR_DATA(IP2_16_14,     DACK0),
+        PINMUX_IPSR_DATA(IP2_16_14,     TX3_A),
+        PINMUX_IPSR_DATA(IP2_16_14,     DRACK0),
+
+        PINMUX_IPSR_DATA(IP2_17,        EX_WAIT0),
+        PINMUX_IPSR_DATA(IP2_17,        PWM0_C),
+
+        PINMUX_IPSR_NOGP(IP2_18,        D0),
+        PINMUX_IPSR_NOGP(IP2_19,        D1),
+        PINMUX_IPSR_NOGP(IP2_20,        D2),
+        PINMUX_IPSR_NOGP(IP2_21,        D3),
+        PINMUX_IPSR_NOGP(IP2_22,        D4),
+        PINMUX_IPSR_NOGP(IP2_23,        D5),
+        PINMUX_IPSR_NOGP(IP2_24,        D6),
+        PINMUX_IPSR_NOGP(IP2_25,        D7),
+        PINMUX_IPSR_NOGP(IP2_26,        D8),
+        PINMUX_IPSR_NOGP(IP2_27,        D9),
+        PINMUX_IPSR_NOGP(IP2_28,        D10),
+        PINMUX_IPSR_NOGP(IP2_29,        D11),
+
+        PINMUX_IPSR_DATA(IP2_30,        RD_WR_B),
+        PINMUX_IPSR_DATA(IP2_30,        IRQ0),
+
+        PINMUX_IPSR_DATA(IP2_31,        MLB_CLK),
+        PINMUX_IPSR_MSEL(IP2_31,        IRQ1_A,         SEL_IRQ1_A),
+
+        /* IPSR3 */
+        PINMUX_IPSR_DATA(IP3_1_0,       MLB_SIG),
+        PINMUX_IPSR_MSEL(IP3_1_0,       RX5_B,          SEL_SCIF5_B),
+        PINMUX_IPSR_MSEL(IP3_1_0,       SDA3_A,         SEL_I2C3_A),
+        PINMUX_IPSR_MSEL(IP3_1_0,       IRQ2_A,         SEL_IRQ2_A),
+
+        PINMUX_IPSR_DATA(IP3_4_2,       MLB_DAT),
+        PINMUX_IPSR_DATA(IP3_4_2,       TX5_B),
+        PINMUX_IPSR_MSEL(IP3_4_2,       SCL3_A,         SEL_I2C3_A),
+        PINMUX_IPSR_MSEL(IP3_4_2,       IRQ3_A,         SEL_IRQ3_A),
+        PINMUX_IPSR_DATA(IP3_4_2,       SDSELF_B),
+
+        PINMUX_IPSR_MSEL(IP3_7_5,       SD1_CMD_B,      SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP3_7_5,       SCIF_CLK),
+        PINMUX_IPSR_DATA(IP3_7_5,       AUDIO_CLKOUT_B),
+        PINMUX_IPSR_MSEL(IP3_7_5,       CAN_CLK_B,      SEL_CANCLK_B),
+        PINMUX_IPSR_MSEL(IP3_7_5,       SDA3_B,         SEL_I2C3_B),
+
+        PINMUX_IPSR_DATA(IP3_9_8,       SD1_CLK_B),
+        PINMUX_IPSR_DATA(IP3_9_8,       HTX0_A),
+        PINMUX_IPSR_DATA(IP3_9_8,       TX0_A),
+
+        PINMUX_IPSR_MSEL(IP3_12_10,     SD1_DAT0_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_12_10,     HRX0_A,         SEL_HSCIF0_A),
+        PINMUX_IPSR_MSEL(IP3_12_10,     RX0_A,          SEL_SCIF0_A),
+
+        PINMUX_IPSR_MSEL(IP3_15_13,     SD1_DAT1_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_15_13,     HSCK0,          SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_15_13,     SCK0),
+        PINMUX_IPSR_MSEL(IP3_15_13,     SCL3_B,         SEL_I2C3_B),
+
+        PINMUX_IPSR_MSEL(IP3_18_16,     SD1_DAT2_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_18_16,     HCTS0_A,        SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_18_16,     CTS0),
+
+        PINMUX_IPSR_MSEL(IP3_20_19,     SD1_DAT3_B,     SEL_SD1_B),
+        PINMUX_IPSR_MSEL(IP3_20_19,     HRTS0_A,        SEL_HSCIF0_A),
+        PINMUX_IPSR_DATA(IP3_20_19,     RTS0),
+
+        PINMUX_IPSR_DATA(IP3_23_21,     SSI_SCK4),
+        PINMUX_IPSR_DATA(IP3_23_21,     DU0_DR0),
+        PINMUX_IPSR_DATA(IP3_23_21,     LCDOUT0),
+        PINMUX_IPSR_DATA(IP3_23_21,     AUDATA2),
+        PINMUX_IPSR_DATA(IP3_23_21,     ARM_TRACEDATA_2),
+        PINMUX_IPSR_MSEL(IP3_23_21,     SDA3_C,         SEL_I2C3_C),
+        PINMUX_IPSR_DATA(IP3_23_21,     ADICHS1),
+        PINMUX_IPSR_MSEL(IP3_23_21,     TS_SDEN0_B,     SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP3_26_24,     SSI_WS4),
+        PINMUX_IPSR_DATA(IP3_26_24,     DU0_DR1),
+        PINMUX_IPSR_DATA(IP3_26_24,     LCDOUT1),
+        PINMUX_IPSR_DATA(IP3_26_24,     AUDATA3),
+        PINMUX_IPSR_DATA(IP3_26_24,     ARM_TRACEDATA_3),
+        PINMUX_IPSR_MSEL(IP3_26_24,     SCL3_C,         SEL_I2C3_C),
+        PINMUX_IPSR_DATA(IP3_26_24,     ADICHS2),
+        PINMUX_IPSR_MSEL(IP3_26_24,     TS_SPSYNC0_B,   SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP3_27,        DU0_DR2),
+        PINMUX_IPSR_DATA(IP3_27,        LCDOUT2),
+
+        PINMUX_IPSR_DATA(IP3_28,        DU0_DR3),
+        PINMUX_IPSR_DATA(IP3_28,        LCDOUT3),
+
+        PINMUX_IPSR_DATA(IP3_29,        DU0_DR4),
+        PINMUX_IPSR_DATA(IP3_29,        LCDOUT4),
+
+        PINMUX_IPSR_DATA(IP3_30,        DU0_DR5),
+        PINMUX_IPSR_DATA(IP3_30,        LCDOUT5),
+
+        PINMUX_IPSR_DATA(IP3_31,        DU0_DR6),
+        PINMUX_IPSR_DATA(IP3_31,        LCDOUT6),
+
+        /* IPSR4 */
+        PINMUX_IPSR_DATA(IP4_0,         DU0_DR7),
+        PINMUX_IPSR_DATA(IP4_0,         LCDOUT7),
+
+        PINMUX_IPSR_DATA(IP4_3_1,       DU0_DG0),
+        PINMUX_IPSR_DATA(IP4_3_1,       LCDOUT8),
+        PINMUX_IPSR_DATA(IP4_3_1,       AUDATA4),
+        PINMUX_IPSR_DATA(IP4_3_1,       ARM_TRACEDATA_4),
+        PINMUX_IPSR_DATA(IP4_3_1,       TX1_D),
+        PINMUX_IPSR_DATA(IP4_3_1,       CAN0_TX_A),
+        PINMUX_IPSR_DATA(IP4_3_1,       ADICHS0),
+
+        PINMUX_IPSR_DATA(IP4_6_4,       DU0_DG1),
+        PINMUX_IPSR_DATA(IP4_6_4,       LCDOUT9),
+        PINMUX_IPSR_DATA(IP4_6_4,       AUDATA5),
+        PINMUX_IPSR_DATA(IP4_6_4,       ARM_TRACEDATA_5),
+        PINMUX_IPSR_MSEL(IP4_6_4,       RX1_D,          SEL_SCIF1_D),
+        PINMUX_IPSR_MSEL(IP4_6_4,       CAN0_RX_A,      SEL_CAN0_A),
+        PINMUX_IPSR_DATA(IP4_6_4,       ADIDATA),
+
+        PINMUX_IPSR_DATA(IP4_7,         DU0_DG2),
+        PINMUX_IPSR_DATA(IP4_7,         LCDOUT10),
+
+        PINMUX_IPSR_DATA(IP4_8,         DU0_DG3),
+        PINMUX_IPSR_DATA(IP4_8,         LCDOUT11),
+
+        PINMUX_IPSR_DATA(IP4_10_9,      DU0_DG4),
+        PINMUX_IPSR_DATA(IP4_10_9,      LCDOUT12),
+        PINMUX_IPSR_MSEL(IP4_10_9,      RX0_B,          SEL_SCIF0_B),
+
+        PINMUX_IPSR_DATA(IP4_12_11,     DU0_DG5),
+        PINMUX_IPSR_DATA(IP4_12_11,     LCDOUT13),
+        PINMUX_IPSR_DATA(IP4_12_11,     TX0_B),
+
+        PINMUX_IPSR_DATA(IP4_14_13,     DU0_DG6),
+        PINMUX_IPSR_DATA(IP4_14_13,     LCDOUT14),
+        PINMUX_IPSR_MSEL(IP4_14_13,     RX4_A,          SEL_SCIF4_A),
+
+        PINMUX_IPSR_DATA(IP4_16_15,     DU0_DG7),
+        PINMUX_IPSR_DATA(IP4_16_15,     LCDOUT15),
+        PINMUX_IPSR_DATA(IP4_16_15,     TX4_A),
+
+        PINMUX_IPSR_MSEL(IP4_20_17,     SSI_SCK2_B,     SEL_SSI2_B),
+        PINMUX_DATA(VI0_R0_B_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R0_D_MARK,      FN_IP4_20_17,   FN_VI0_R0_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_20_17,     DU0_DB0),
+        PINMUX_IPSR_DATA(IP4_20_17,     LCDOUT16),
+        PINMUX_IPSR_DATA(IP4_20_17,     AUDATA6),
+        PINMUX_IPSR_DATA(IP4_20_17,     ARM_TRACEDATA_6),
+        PINMUX_IPSR_MSEL(IP4_20_17,     GPSCLK_A,       SEL_GPS_A),
+        PINMUX_IPSR_DATA(IP4_20_17,     PWM0_A),
+        PINMUX_IPSR_DATA(IP4_20_17,     ADICLK),
+        PINMUX_IPSR_MSEL(IP4_20_17,     TS_SDAT0_B,     SEL_TSIF0_B),
+
+        PINMUX_IPSR_DATA(IP4_24_21,     AUDIO_CLKC),
+        PINMUX_DATA(VI0_R1_B_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R1_D_MARK,      FN_IP4_24_21,   FN_VI0_R1_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_24_21,     DU0_DB1),
+        PINMUX_IPSR_DATA(IP4_24_21,     LCDOUT17),
+        PINMUX_IPSR_DATA(IP4_24_21,     AUDATA7),
+        PINMUX_IPSR_DATA(IP4_24_21,     ARM_TRACEDATA_7),
+        PINMUX_IPSR_MSEL(IP4_24_21,     GPSIN_A,        SEL_GPS_A),
+        PINMUX_IPSR_DATA(IP4_24_21,     ADICS_SAMP),
+        PINMUX_IPSR_MSEL(IP4_24_21,     TS_SCK0_B,      SEL_TSIF0_B),
+
+        PINMUX_DATA(VI0_R2_B_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R2_D_MARK,      FN_IP4_26_25,   FN_VI0_R2_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_26_25,     DU0_DB2),
+        PINMUX_IPSR_DATA(IP4_26_25,     LCDOUT18),
+
+        PINMUX_IPSR_MSEL(IP4_28_27,     VI0_R3_B,       SEL_VI0_B),
+        PINMUX_IPSR_DATA(IP4_28_27,     DU0_DB3),
+        PINMUX_IPSR_DATA(IP4_28_27,     LCDOUT19),
+
+        PINMUX_DATA(VI0_R4_B_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R4_D_MARK,      FN_IP4_30_29,   FN_VI0_R4_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP4_30_29,     DU0_DB4),
+        PINMUX_IPSR_DATA(IP4_30_29,     LCDOUT20),
+
+        /* IPSR5 */
+        PINMUX_DATA(VI0_R5_B_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_B), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R5_D_MARK,      FN_IP5_1_0,     FN_VI0_R5_B,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP5_1_0,       DU0_DB5),
+        PINMUX_IPSR_DATA(IP5_1_0,       LCDOUT21),
+
+        PINMUX_IPSR_MSEL(IP5_3_2,       VI1_DATA10_B,   SEL_VI1_B),
+        PINMUX_IPSR_DATA(IP5_3_2,       DU0_DB6),
+        PINMUX_IPSR_DATA(IP5_3_2,       LCDOUT22),
+
+        PINMUX_IPSR_MSEL(IP5_5_4,       VI1_DATA11_B,   SEL_VI1_B),
+        PINMUX_IPSR_DATA(IP5_5_4,       DU0_DB7),
+        PINMUX_IPSR_DATA(IP5_5_4,       LCDOUT23),
+
+        PINMUX_IPSR_DATA(IP5_6,         DU0_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP5_6,         QSTVA_QVS),
+
+        PINMUX_IPSR_DATA(IP5_7,         DU0_DOTCLKO_UT0),
+        PINMUX_IPSR_DATA(IP5_7,         QCLK),
+
+        PINMUX_IPSR_DATA(IP5_9_8,       DU0_DOTCLKO_UT1),
+        PINMUX_IPSR_DATA(IP5_9_8,       QSTVB_QVE),
+        PINMUX_IPSR_DATA(IP5_9_8,       AUDIO_CLKOUT_A),
+        PINMUX_IPSR_MSEL(IP5_9_8,       REMOCON_C,      SEL_REMOCON_C),
+
+        PINMUX_IPSR_MSEL(IP5_11_10,     SSI_WS2_B,      SEL_SSI2_B),
+        PINMUX_IPSR_DATA(IP5_11_10,     DU0_EXHSYNC_DU0_HSYNC),
+        PINMUX_IPSR_DATA(IP5_11_10,     QSTH_QHS),
+
+        PINMUX_IPSR_DATA(IP5_12,        DU0_EXVSYNC_DU0_VSYNC),
+        PINMUX_IPSR_DATA(IP5_12,        QSTB_QHE),
+
+        PINMUX_IPSR_DATA(IP5_14_13,     DU0_EXODDF_DU0_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP5_14_13,     QCPV_QDE),
+        PINMUX_IPSR_MSEL(IP5_14_13,     FMCLK_D,        SEL_FM_D),
+
+        PINMUX_IPSR_MSEL(IP5_17_15,     SSI_SCK1_A,     SEL_SSI1_A),
+        PINMUX_IPSR_DATA(IP5_17_15,     DU0_DISP),
+        PINMUX_IPSR_DATA(IP5_17_15,     QPOLA),
+        PINMUX_IPSR_DATA(IP5_17_15,     AUDCK),
+        PINMUX_IPSR_DATA(IP5_17_15,     ARM_TRACECLK),
+        PINMUX_IPSR_DATA(IP5_17_15,     BPFCLK_D),
+
+        PINMUX_IPSR_MSEL(IP5_20_18,     SSI_WS1_A,      SEL_SSI1_A),
+        PINMUX_IPSR_DATA(IP5_20_18,     DU0_CDE),
+        PINMUX_IPSR_DATA(IP5_20_18,     QPOLB),
+        PINMUX_IPSR_DATA(IP5_20_18,     AUDSYNC),
+        PINMUX_IPSR_DATA(IP5_20_18,     ARM_TRACECTL),
+        PINMUX_IPSR_MSEL(IP5_20_18,     FMIN_D,         SEL_FM_D),
+
+        PINMUX_IPSR_MSEL(IP5_22_21,     SD1_CD_B,       SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP5_22_21,     SSI_SCK78),
+        PINMUX_IPSR_MSEL(IP5_22_21,     HSPI_RX0_B,     SEL_HSPI0_B),
+        PINMUX_IPSR_DATA(IP5_22_21,     TX1_B),
+
+        PINMUX_IPSR_MSEL(IP5_25_23,     SD1_WP_B,       SEL_SD1_B),
+        PINMUX_IPSR_DATA(IP5_25_23,     SSI_WS78),
+        PINMUX_IPSR_MSEL(IP5_25_23,     HSPI_CLK0_B,    SEL_HSPI0_B),
+        PINMUX_IPSR_MSEL(IP5_25_23,     RX1_B,          SEL_SCIF1_B),
+        PINMUX_IPSR_MSEL(IP5_25_23,     CAN_CLK_D,      SEL_CANCLK_D),
+
+        PINMUX_IPSR_DATA(IP5_28_26,     SSI_SDATA8),
+        PINMUX_IPSR_MSEL(IP5_28_26,     SSI_SCK2_A,     SEL_SSI2_A),
+        PINMUX_IPSR_MSEL(IP5_28_26,     HSPI_CS0_B,     SEL_HSPI0_B),
+        PINMUX_IPSR_DATA(IP5_28_26,     TX2_A),
+        PINMUX_IPSR_DATA(IP5_28_26,     CAN0_TX_B),
+
+        PINMUX_IPSR_DATA(IP5_30_29,     SSI_SDATA7),
+        PINMUX_IPSR_DATA(IP5_30_29,     HSPI_TX0_B),
+        PINMUX_IPSR_MSEL(IP5_30_29,     RX2_A,          SEL_SCIF2_A),
+        PINMUX_IPSR_MSEL(IP5_30_29,     CAN0_RX_B,      SEL_CAN0_B),
+
+        /* IPSR6 */
+        PINMUX_IPSR_DATA(IP6_1_0,       SSI_SCK6),
+        PINMUX_IPSR_MSEL(IP6_1_0,       HSPI_RX2_A,     SEL_HSPI2_A),
+        PINMUX_IPSR_MSEL(IP6_1_0,       FMCLK_B,        SEL_FM_B),
+        PINMUX_IPSR_DATA(IP6_1_0,       CAN1_TX_B),
+
+        PINMUX_IPSR_DATA(IP6_4_2,       SSI_WS6),
+        PINMUX_IPSR_MSEL(IP6_4_2,       HSPI_CLK2_A,    SEL_HSPI2_A),
+        PINMUX_IPSR_DATA(IP6_4_2,       BPFCLK_B),
+        PINMUX_IPSR_MSEL(IP6_4_2,       CAN1_RX_B,      SEL_CAN1_B),
+
+        PINMUX_IPSR_DATA(IP6_6_5,       SSI_SDATA6),
+        PINMUX_IPSR_DATA(IP6_6_5,       HSPI_TX2_A),
+        PINMUX_IPSR_MSEL(IP6_6_5,       FMIN_B,         SEL_FM_B),
+
+        PINMUX_IPSR_DATA(IP6_7,         SSI_SCK5),
+        PINMUX_IPSR_MSEL(IP6_7,         RX4_C,          SEL_SCIF4_C),
+
+        PINMUX_IPSR_DATA(IP6_8,         SSI_WS5),
+        PINMUX_IPSR_DATA(IP6_8,         TX4_C),
+
+        PINMUX_IPSR_DATA(IP6_9,         SSI_SDATA5),
+        PINMUX_IPSR_MSEL(IP6_9,         RX0_D,          SEL_SCIF0_D),
+
+        PINMUX_IPSR_DATA(IP6_10,        SSI_WS34),
+        PINMUX_IPSR_DATA(IP6_10,        ARM_TRACEDATA_8),
+
+        PINMUX_IPSR_DATA(IP6_12_11,     SSI_SDATA4),
+        PINMUX_IPSR_MSEL(IP6_12_11,     SSI_WS2_A,      SEL_SSI2_A),
+        PINMUX_IPSR_DATA(IP6_12_11,     ARM_TRACEDATA_9),
+
+        PINMUX_IPSR_DATA(IP6_13,        SSI_SDATA3),
+        PINMUX_IPSR_DATA(IP6_13,        ARM_TRACEDATA_10),
+
+        PINMUX_IPSR_DATA(IP6_15_14,     SSI_SCK012),
+        PINMUX_IPSR_DATA(IP6_15_14,     ARM_TRACEDATA_11),
+        PINMUX_IPSR_DATA(IP6_15_14,     TX0_D),
+
+        PINMUX_IPSR_DATA(IP6_16,        SSI_WS012),
+        PINMUX_IPSR_DATA(IP6_16,        ARM_TRACEDATA_12),
+
+        PINMUX_IPSR_DATA(IP6_18_17,     SSI_SDATA2),
+        PINMUX_IPSR_MSEL(IP6_18_17,     HSPI_CS2_A,     SEL_HSPI2_A),
+        PINMUX_IPSR_DATA(IP6_18_17,     ARM_TRACEDATA_13),
+        PINMUX_IPSR_MSEL(IP6_18_17,     SDA1_A,         SEL_I2C1_A),
+
+        PINMUX_IPSR_DATA(IP6_20_19,     SSI_SDATA1),
+        PINMUX_IPSR_DATA(IP6_20_19,     ARM_TRACEDATA_14),
+        PINMUX_IPSR_MSEL(IP6_20_19,     SCL1_A,         SEL_I2C1_A),
+        PINMUX_IPSR_MSEL(IP6_20_19,     SCK2_A,         SEL_SCIF2_A),
+
+        PINMUX_IPSR_DATA(IP6_21,        SSI_SDATA0),
+        PINMUX_IPSR_DATA(IP6_21,        ARM_TRACEDATA_15),
+
+        PINMUX_IPSR_DATA(IP6_23_22,     SD0_CLK),
+        PINMUX_IPSR_DATA(IP6_23_22,     SUB_TDO),
+
+        PINMUX_IPSR_DATA(IP6_25_24,     SD0_CMD),
+        PINMUX_IPSR_DATA(IP6_25_24,     SUB_TRST),
+
+        PINMUX_IPSR_DATA(IP6_27_26,     SD0_DAT0),
+        PINMUX_IPSR_DATA(IP6_27_26,     SUB_TMS),
+
+        PINMUX_IPSR_DATA(IP6_29_28,     SD0_DAT1),
+        PINMUX_IPSR_DATA(IP6_29_28,     SUB_TCK),
+
+        PINMUX_IPSR_DATA(IP6_31_30,     SD0_DAT2),
+        PINMUX_IPSR_DATA(IP6_31_30,     SUB_TDI),
+
+        /* IPSR7 */
+        PINMUX_IPSR_DATA(IP7_1_0,       SD0_DAT3),
+        PINMUX_IPSR_MSEL(IP7_1_0,       IRQ1_B,         SEL_IRQ1_B),
+
+        PINMUX_IPSR_DATA(IP7_3_2,       SD0_CD),
+        PINMUX_IPSR_DATA(IP7_3_2,       TX5_A),
+
+        PINMUX_IPSR_DATA(IP7_5_4,       SD0_WP),
+        PINMUX_IPSR_MSEL(IP7_5_4,       RX5_A,          SEL_SCIF5_A),
+
+        PINMUX_IPSR_DATA(IP7_8_6,       VI1_CLKENB),
+        PINMUX_IPSR_MSEL(IP7_8_6,       HSPI_CLK0_A,    SEL_HSPI0_A),
+        PINMUX_IPSR_DATA(IP7_8_6,       HTX1_A),
+        PINMUX_IPSR_MSEL(IP7_8_6,       RTS1_C,         SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_11_9,      VI1_FIELD),
+        PINMUX_IPSR_MSEL(IP7_11_9,      HSPI_CS0_A,     SEL_HSPI0_A),
+        PINMUX_IPSR_MSEL(IP7_11_9,      HRX1_A,         SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_11_9,      SCK1_C,         SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_14_12,     VI1_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_14_12,     HSPI_RX0_A,     SEL_HSPI0_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     HRTS1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     FMCLK_A,        SEL_FM_A),
+        PINMUX_IPSR_MSEL(IP7_14_12,     RX1_C,          SEL_SCIF1_C),
+
+        PINMUX_IPSR_DATA(IP7_17_15,     VI1_VSYNC),
+        PINMUX_IPSR_DATA(IP7_17_15,     HSPI_TX0),
+        PINMUX_IPSR_MSEL(IP7_17_15,     HCTS1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_DATA(IP7_17_15,     BPFCLK_A),
+        PINMUX_IPSR_DATA(IP7_17_15,     TX1_C),
+
+        PINMUX_IPSR_DATA(IP7_20_18,     TCLK0),
+        PINMUX_IPSR_MSEL(IP7_20_18,     HSCK1_A,        SEL_HSCIF1_A),
+        PINMUX_IPSR_MSEL(IP7_20_18,     FMIN_A,         SEL_FM_A),
+        PINMUX_IPSR_MSEL(IP7_20_18,     IRQ2_C,         SEL_IRQ2_C),
+        PINMUX_IPSR_MSEL(IP7_20_18,     CTS1_C,         SEL_SCIF1_C),
+        PINMUX_IPSR_DATA(IP7_20_18,     SPEEDIN),
+
+        PINMUX_IPSR_DATA(IP7_21,        VI0_CLK),
+        PINMUX_IPSR_MSEL(IP7_21,        CAN_CLK_A,      SEL_CANCLK_A),
+
+        PINMUX_IPSR_DATA(IP7_24_22,     VI0_CLKENB),
+        PINMUX_IPSR_MSEL(IP7_24_22,     SD2_DAT2_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP7_24_22,     VI1_DATA0),
+        PINMUX_IPSR_DATA(IP7_24_22,     DU1_DG6),
+        PINMUX_IPSR_MSEL(IP7_24_22,     HSPI_RX1_A,     SEL_HSPI1_A),
+        PINMUX_IPSR_MSEL(IP7_24_22,     RX4_B,          SEL_SCIF4_B),
+
+        PINMUX_IPSR_DATA(IP7_28_25,     VI0_FIELD),
+        PINMUX_IPSR_MSEL(IP7_28_25,     SD2_DAT3_B,     SEL_SD2_B),
+        PINMUX_DATA(VI0_R3_C_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R3_D_MARK,      FN_IP7_28_25,   FN_VI0_R3_C,    FN_SEL_VI0_D), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP7_28_25,     VI1_DATA1),
+        PINMUX_IPSR_DATA(IP7_28_25,     DU1_DG7),
+        PINMUX_IPSR_MSEL(IP7_28_25,     HSPI_CLK1_A,    SEL_HSPI1_A),
+        PINMUX_IPSR_DATA(IP7_28_25,     TX4_B),
+
+        PINMUX_IPSR_DATA(IP7_31_29,     VI0_HSYNC),
+        PINMUX_IPSR_MSEL(IP7_31_29,     SD2_CD_B,       SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP7_31_29,     VI1_DATA2),
+        PINMUX_IPSR_DATA(IP7_31_29,     DU1_DR2),
+        PINMUX_IPSR_MSEL(IP7_31_29,     HSPI_CS1_A,     SEL_HSPI1_A),
+        PINMUX_IPSR_MSEL(IP7_31_29,     RX3_B,          SEL_SCIF3_B),
+
+        /* IPSR8 */
+        PINMUX_IPSR_DATA(IP8_2_0,       VI0_VSYNC),
+        PINMUX_IPSR_MSEL(IP8_2_0,       SD2_WP_B,       SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP8_2_0,       VI1_DATA3),
+        PINMUX_IPSR_DATA(IP8_2_0,       DU1_DR3),
+        PINMUX_IPSR_DATA(IP8_2_0,       HSPI_TX1_A),
+        PINMUX_IPSR_DATA(IP8_2_0,       TX3_B),
+
+        PINMUX_IPSR_DATA(IP8_5_3,       VI0_DATA0_VI0_B0),
+        PINMUX_IPSR_DATA(IP8_5_3,       DU1_DG2),
+        PINMUX_IPSR_MSEL(IP8_5_3,       IRQ2_B,         SEL_IRQ2_B),
+        PINMUX_IPSR_MSEL(IP8_5_3,       RX3_D,          SEL_SCIF3_D),
+
+        PINMUX_IPSR_DATA(IP8_8_6,       VI0_DATA1_VI0_B1),
+        PINMUX_IPSR_DATA(IP8_8_6,       DU1_DG3),
+        PINMUX_IPSR_MSEL(IP8_8_6,       IRQ3_B,         SEL_IRQ3_B),
+        PINMUX_IPSR_DATA(IP8_8_6,       TX3_D),
+
+        PINMUX_IPSR_DATA(IP8_10_9,      VI0_DATA2_VI0_B2),
+        PINMUX_IPSR_DATA(IP8_10_9,      DU1_DG4),
+        PINMUX_IPSR_MSEL(IP8_10_9,      RX0_C,          SEL_SCIF0_C),
+
+        PINMUX_IPSR_DATA(IP8_13_11,     VI0_DATA3_VI0_B3),
+        PINMUX_IPSR_DATA(IP8_13_11,     DU1_DG5),
+        PINMUX_IPSR_DATA(IP8_13_11,     TX1_A),
+        PINMUX_IPSR_DATA(IP8_13_11,     TX0_C),
+
+        PINMUX_IPSR_DATA(IP8_15_14,     VI0_DATA4_VI0_B4),
+        PINMUX_IPSR_DATA(IP8_15_14,     DU1_DB2),
+        PINMUX_IPSR_MSEL(IP8_15_14,     RX1_A,          SEL_SCIF1_A),
+
+        PINMUX_IPSR_DATA(IP8_18_16,     VI0_DATA5_VI0_B5),
+        PINMUX_IPSR_DATA(IP8_18_16,     DU1_DB3),
+        PINMUX_IPSR_MSEL(IP8_18_16,     SCK1_A,         SEL_SCIF1_A),
+        PINMUX_IPSR_DATA(IP8_18_16,     PWM4),
+        PINMUX_IPSR_MSEL(IP8_18_16,     HSCK1_B,        SEL_HSCIF1_B),
+
+        PINMUX_IPSR_DATA(IP8_21_19,     VI0_DATA6_VI0_G0),
+        PINMUX_IPSR_DATA(IP8_21_19,     DU1_DB4),
+        PINMUX_IPSR_MSEL(IP8_21_19,     CTS1_A,         SEL_SCIF1_A),
+        PINMUX_IPSR_DATA(IP8_21_19,     PWM5),
+
+        PINMUX_IPSR_DATA(IP8_23_22,     VI0_DATA7_VI0_G1),
+        PINMUX_IPSR_DATA(IP8_23_22,     DU1_DB5),
+        PINMUX_IPSR_MSEL(IP8_23_22,     RTS1_A,         SEL_SCIF1_A),
+
+        PINMUX_IPSR_DATA(IP8_26_24,     VI0_G2),
+        PINMUX_IPSR_DATA(IP8_26_24,     SD2_CLK_B),
+        PINMUX_IPSR_DATA(IP8_26_24,     VI1_DATA4),
+        PINMUX_IPSR_DATA(IP8_26_24,     DU1_DR4),
+        PINMUX_IPSR_DATA(IP8_26_24,     HTX1_B),
+
+        PINMUX_IPSR_DATA(IP8_29_27,     VI0_G3),
+        PINMUX_IPSR_MSEL(IP8_29_27,     SD2_CMD_B,      SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP8_29_27,     VI1_DATA5),
+        PINMUX_IPSR_DATA(IP8_29_27,     DU1_DR5),
+        PINMUX_IPSR_MSEL(IP8_29_27,     HRX1_B,         SEL_HSCIF1_B),
+
+        /* IPSR9 */
+        PINMUX_IPSR_DATA(IP9_2_0,       VI0_G4),
+        PINMUX_IPSR_MSEL(IP9_2_0,       SD2_DAT0_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP9_2_0,       VI1_DATA6),
+        PINMUX_IPSR_DATA(IP9_2_0,       DU1_DR6),
+        PINMUX_IPSR_MSEL(IP9_2_0,       HRTS1_B,        SEL_HSCIF1_B),
+
+        PINMUX_IPSR_DATA(IP9_5_3,       VI0_G5),
+        PINMUX_IPSR_MSEL(IP9_5_3,       SD2_DAT1_B,     SEL_SD2_B),
+        PINMUX_IPSR_DATA(IP9_5_3,       VI1_DATA7),
+        PINMUX_IPSR_DATA(IP9_5_3,       DU1_DR7),
+        PINMUX_IPSR_MSEL(IP9_5_3,       HCTS1_B,        SEL_HSCIF1_B),
+
+        PINMUX_DATA(VI0_R0_A_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R0_C_MARK,      FN_IP9_8_6,     FN_VI0_R0_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_8_6,       VI1_CLK),
+        PINMUX_IPSR_DATA(IP9_8_6,       ETH_REF_CLK),
+        PINMUX_IPSR_DATA(IP9_8_6,       DU1_DOTCLKIN),
+
+        PINMUX_DATA(VI0_R1_A_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R1_C_MARK,      FN_IP9_11_9,    FN_VI0_R1_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_11_9,      VI1_DATA8),
+        PINMUX_IPSR_DATA(IP9_11_9,      DU1_DB6),
+        PINMUX_IPSR_DATA(IP9_11_9,      ETH_TXD0),
+        PINMUX_IPSR_DATA(IP9_11_9,      PWM2),
+        PINMUX_IPSR_DATA(IP9_11_9,      TCLK1),
+
+        PINMUX_DATA(VI0_R2_A_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R2_C_MARK,      FN_IP9_14_12,   FN_VI0_R2_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_14_12,     VI1_DATA9),
+        PINMUX_IPSR_DATA(IP9_14_12,     DU1_DB7),
+        PINMUX_IPSR_DATA(IP9_14_12,     ETH_TXD1),
+        PINMUX_IPSR_DATA(IP9_14_12,     PWM3),
+
+        PINMUX_IPSR_MSEL(IP9_17_15,     VI0_R3_A,       SEL_VI0_A),
+        PINMUX_IPSR_DATA(IP9_17_15,     ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP9_17_15,     IECLK),
+        PINMUX_IPSR_MSEL(IP9_17_15,     SCK2_C,         SEL_SCIF2_C),
+
+        PINMUX_DATA(VI0_R4_A_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R3_C_MARK,      FN_IP9_20_18,   FN_VI0_R4_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_20_18,     ETH_TX_EN),
+        PINMUX_IPSR_DATA(IP9_20_18,     IETX),
+        PINMUX_IPSR_DATA(IP9_20_18,     TX2_C),
+
+        PINMUX_DATA(VI0_R5_A_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_A), /* see sel_vi0 */
+        PINMUX_DATA(VI0_R5_C_MARK,      FN_IP9_23_21,   FN_VI0_R5_A,    FN_SEL_VI0_C), /* see sel_vi0 */
+        PINMUX_IPSR_DATA(IP9_23_21,     ETH_RX_ER),
+        PINMUX_IPSR_MSEL(IP9_23_21,     FMCLK_C,        SEL_FM_C),
+        PINMUX_IPSR_DATA(IP9_23_21,     IERX),
+        PINMUX_IPSR_MSEL(IP9_23_21,     RX2_C,          SEL_SCIF2_C),
+
+        PINMUX_IPSR_MSEL(IP9_26_24,     VI1_DATA10_A,   SEL_VI1_A),
+        PINMUX_IPSR_DATA(IP9_26_24,     DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP9_26_24,     ETH_RXD0),
+        PINMUX_IPSR_DATA(IP9_26_24,     BPFCLK_C),
+        PINMUX_IPSR_DATA(IP9_26_24,     TX2_D),
+        PINMUX_IPSR_MSEL(IP9_26_24,     SDA2_C,         SEL_I2C2_C),
+
+        PINMUX_IPSR_MSEL(IP9_29_27,     VI1_DATA11_A,   SEL_VI1_A),
+        PINMUX_IPSR_DATA(IP9_29_27,     DU1_EXHSYNC_DU1_HSYNC),
+        PINMUX_IPSR_DATA(IP9_29_27,     ETH_RXD1),
+        PINMUX_IPSR_MSEL(IP9_29_27,     FMIN_C,         SEL_FM_C),
+        PINMUX_IPSR_MSEL(IP9_29_27,     RX2_D,          SEL_SCIF2_D),
+        PINMUX_IPSR_MSEL(IP9_29_27,     SCL2_C,         SEL_I2C2_C),
+
+        /* IPSR10 */
+        PINMUX_IPSR_DATA(IP10_2_0,      SD2_CLK_A),
+        PINMUX_IPSR_DATA(IP10_2_0,      DU1_EXVSYNC_DU1_VSYNC),
+        PINMUX_IPSR_DATA(IP10_2_0,      ATARD1),
+        PINMUX_IPSR_DATA(IP10_2_0,      ETH_MDC),
+        PINMUX_IPSR_MSEL(IP10_2_0,      SDA1_B,         SEL_I2C1_B),
+
+        PINMUX_IPSR_MSEL(IP10_5_3,      SD2_CMD_A,      SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_5_3,      DU1_EXODDF_DU1_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP10_5_3,      ATAWR1),
+        PINMUX_IPSR_DATA(IP10_5_3,      ETH_MDIO),
+        PINMUX_IPSR_MSEL(IP10_5_3,      SCL1_B,         SEL_I2C1_B),
+
+        PINMUX_IPSR_MSEL(IP10_8_6,      SD2_DAT0_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_8_6,      DU1_DISP),
+        PINMUX_IPSR_DATA(IP10_8_6,      ATACS01),
+        PINMUX_IPSR_MSEL(IP10_8_6,      DREQ1_B,        SEL_DREQ1_B),
+        PINMUX_IPSR_DATA(IP10_8_6,      ETH_LINK),
+        PINMUX_IPSR_MSEL(IP10_8_6,      CAN1_RX_A,      SEL_CAN1_A),
+
+        PINMUX_IPSR_MSEL(IP10_12_9,     SD2_DAT1_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_12_9,     DU1_CDE),
+        PINMUX_IPSR_DATA(IP10_12_9,     ATACS11),
+        PINMUX_IPSR_DATA(IP10_12_9,     DACK1_B),
+        PINMUX_IPSR_DATA(IP10_12_9,     ETH_MAGIC),
+        PINMUX_IPSR_DATA(IP10_12_9,     CAN1_TX_A),
+        PINMUX_IPSR_DATA(IP10_12_9,     PWM6),
+
+        PINMUX_IPSR_MSEL(IP10_15_13,    SD2_DAT2_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_15_13,    VI1_DATA12),
+        PINMUX_IPSR_MSEL(IP10_15_13,    DREQ2_B,        SEL_DREQ2_B),
+        PINMUX_IPSR_DATA(IP10_15_13,    ATADIR1),
+        PINMUX_IPSR_MSEL(IP10_15_13,    HSPI_CLK2_B,    SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_15_13,    GPSCLK_B,       SEL_GPS_B),
+
+        PINMUX_IPSR_MSEL(IP10_18_16,    SD2_DAT3_A,     SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_18_16,    VI1_DATA13),
+        PINMUX_IPSR_DATA(IP10_18_16,    DACK2_B),
+        PINMUX_IPSR_DATA(IP10_18_16,    ATAG1),
+        PINMUX_IPSR_MSEL(IP10_18_16,    HSPI_CS2_B,     SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_18_16,    GPSIN_B,        SEL_GPS_B),
+
+        PINMUX_IPSR_MSEL(IP10_21_19,    SD2_CD_A,       SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_21_19,    VI1_DATA14),
+        PINMUX_IPSR_MSEL(IP10_21_19,    EX_WAIT1_B,     SEL_WAIT1_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    DREQ0_B,        SEL_DREQ0_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    HSPI_RX2_B,     SEL_HSPI2_B),
+        PINMUX_IPSR_MSEL(IP10_21_19,    REMOCON_A,      SEL_REMOCON_A),
+
+        PINMUX_IPSR_MSEL(IP10_24_22,    SD2_WP_A,       SEL_SD2_A),
+        PINMUX_IPSR_DATA(IP10_24_22,    VI1_DATA15),
+        PINMUX_IPSR_MSEL(IP10_24_22,    EX_WAIT2_B,     SEL_WAIT2_B),
+        PINMUX_IPSR_DATA(IP10_24_22,    DACK0_B),
+        PINMUX_IPSR_DATA(IP10_24_22,    HSPI_TX2_B),
+        PINMUX_IPSR_MSEL(IP10_24_22,    CAN_CLK_C,      SEL_CANCLK_C),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* Pin numbers for pins without a corresponding GPIO port number are computed
+ * from the row and column numbers with a 1000 offset to avoid collisions with
+ * GPIO port numbers.
+ */
+#define PIN_NUMBER(row, col)            (1000+((row)-1)*25+(col)-1)
+
+/* - macro */
+#define SH_PFC_PINS(name, args...) \
+        static const unsigned int name ##_pins[] = { args }
+#define SH_PFC_MUX1(name, arg1)                                 \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK }
+#define SH_PFC_MUX2(name, arg1, arg2)                                   \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, }
+#define SH_PFC_MUX3(name, arg1, arg2, arg3)                                     \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK,  \
+                                                     arg3##_MARK }
+#define SH_PFC_MUX4(name, arg1, arg2, arg3, arg4)                       \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+                                                     arg3##_MARK, arg4##_MARK }
+#define SH_PFC_MUX8(name, arg1, arg2, arg3, arg4, arg5, arg6, arg7, arg8) \
+        static const unsigned int name ##_mux[]  = { arg1##_MARK, arg2##_MARK, \
+                                                     arg3##_MARK, arg4##_MARK, \
+                                                     arg5##_MARK, arg6##_MARK, \
+                                                     arg7##_MARK, arg8##_MARK, }
+
+/* - Ether ------------------------------------------------------------------ */
+SH_PFC_PINS(ether_rmii,         RCAR_GP_PIN(4, 10),     RCAR_GP_PIN(4, 11),
+                                RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 9),
+                                RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16),
+                                RCAR_GP_PIN(4, 12),     RCAR_GP_PIN(4, 14),
+                                RCAR_GP_PIN(4, 18),     RCAR_GP_PIN(4, 17));
+static const unsigned int ether_rmii_mux[] = {
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REF_CLK_MARK,
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+        ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+SH_PFC_PINS(ether_link,         RCAR_GP_PIN(4, 19));
+SH_PFC_MUX1(ether_link,         ETH_LINK);
+SH_PFC_PINS(ether_magic,        RCAR_GP_PIN(4, 20));
+SH_PFC_MUX1(ether_magic,        ETH_MAGIC);
+
+/* - SCIF macro ------------------------------------------------------------- */
+#define SCIF_PFC_PIN(name, args...)     SH_PFC_PINS(name, args)
+#define SCIF_PFC_DAT(name, tx, rx)      SH_PFC_MUX2(name, tx, rx)
+#define SCIF_PFC_CTR(name, cts, rts)    SH_PFC_MUX2(name, cts, rts)
+#define SCIF_PFC_CLK(name, sck)         SH_PFC_MUX1(name, sck)
+
+/* - HSCIF0 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif0_data_a,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(hscif0_data_a,     HTX0_A,                 HRX0_A);
+SCIF_PFC_PIN(hscif0_data_b,     RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 30));
+SCIF_PFC_DAT(hscif0_data_b,     HTX0_B,                 HRX0_B);
+SCIF_PFC_PIN(hscif0_ctrl_a,     RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(hscif0_ctrl_a,     HCTS0_A,                HRTS0_A);
+SCIF_PFC_PIN(hscif0_ctrl_b,     RCAR_GP_PIN(0, 31),     RCAR_GP_PIN(0, 28));
+SCIF_PFC_CTR(hscif0_ctrl_b,     HCTS0_B,                HRTS0_B);
+SCIF_PFC_PIN(hscif0_clk,        RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(hscif0_clk,        HSCK0);
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+SCIF_PFC_PIN(hscif1_data_a,     RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20));
+SCIF_PFC_DAT(hscif1_data_a,     HTX1_A,                 HRX1_A);
+SCIF_PFC_PIN(hscif1_data_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
+SCIF_PFC_DAT(hscif1_data_b,     HTX1_B,                 HRX1_B);
+SCIF_PFC_PIN(hscif1_ctrl_a,     RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
+SCIF_PFC_CTR(hscif1_ctrl_a,     HCTS1_A,                HRTS1_A);
+SCIF_PFC_PIN(hscif1_ctrl_b,     RCAR_GP_PIN(4, 8),      RCAR_GP_PIN(4, 7));
+SCIF_PFC_CTR(hscif1_ctrl_b,     HCTS1_B,                HRTS1_B);
+SCIF_PFC_PIN(hscif1_clk_a,      RCAR_GP_PIN(3, 23));
+SCIF_PFC_CLK(hscif1_clk_a,      HSCK1_A);
+SCIF_PFC_PIN(hscif1_clk_b,      RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(hscif1_clk_b,      HSCK1_B);
+
+/* - HSPI macro --------------------------------------------------------------*/
+#define HSPI_PFC_PIN(name, args...)             SH_PFC_PINS(name, args)
+#define HSPI_PFC_DAT(name, clk, cs, rx, tx)     SH_PFC_MUX4(name, clk, cs, rx, tx)
+
+/* - HSPI0 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi0_a,   RCAR_GP_PIN(3, 19),     RCAR_GP_PIN(3, 20),
+                        RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
+HSPI_PFC_DAT(hspi0_a,   HSPI_CLK0_A,            HSPI_CS0_A,
+                        HSPI_RX0_A,             HSPI_TX0);
+
+HSPI_PFC_PIN(hspi0_b,   RCAR_GP_PIN(2, 25),     RCAR_GP_PIN(2, 26),
+                        RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 27));
+HSPI_PFC_DAT(hspi0_b,   HSPI_CLK0_B,            HSPI_CS0_B,
+                        HSPI_RX0_B,             HSPI_TX0_B);
+
+/* - HSPI1 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi1_a,   RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 27),
+                        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 28));
+HSPI_PFC_DAT(hspi1_a,   HSPI_CLK1_A,            HSPI_CS1_A,
+                        HSPI_RX1_A,             HSPI_TX1_A);
+
+HSPI_PFC_PIN(hspi1_b,   RCAR_GP_PIN(0, 27),     RCAR_GP_PIN(0, 26),
+                        PIN_NUMBER(20, 1),      PIN_NUMBER(25, 2));
+HSPI_PFC_DAT(hspi1_b,   HSPI_CLK1_B,            HSPI_CS1_B,
+                        HSPI_RX1_B,             HSPI_TX1_B);
+
+/* - HSPI2 -------------------------------------------------------------------*/
+HSPI_PFC_PIN(hspi2_a,   RCAR_GP_PIN(2, 29),     RCAR_GP_PIN(3, 8),
+                        RCAR_GP_PIN(2, 28),     RCAR_GP_PIN(2, 30));
+HSPI_PFC_DAT(hspi2_a,   HSPI_CLK2_A,            HSPI_CS2_A,
+                        HSPI_RX2_A,             HSPI_TX2_A);
+
+HSPI_PFC_PIN(hspi2_b,   RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22),
+                        RCAR_GP_PIN(4, 23),     RCAR_GP_PIN(4, 24));
+HSPI_PFC_DAT(hspi2_b,   HSPI_CLK2_B,            HSPI_CS2_B,
+                        HSPI_RX2_B,             HSPI_TX2_B);
+
+/* - I2C macro ------------------------------------------------------------- */
+#define I2C_PFC_PIN(name, args...)      SH_PFC_PINS(name, args)
+#define I2C_PFC_MUX(name, sda, scl)     SH_PFC_MUX2(name, sda, scl)
+
+/* - I2C1 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c1_a,     RCAR_GP_PIN(3, 8),      RCAR_GP_PIN(3, 9));
+I2C_PFC_MUX(i2c1_a,     SDA1_A,                 SCL1_A);
+I2C_PFC_PIN(i2c1_b,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
+I2C_PFC_MUX(i2c1_b,     SDA1_B,                 SCL1_B);
+
+/* - I2C2 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c2_a,     PIN_NUMBER(3, 20),      RCAR_GP_PIN(1, 3));
+I2C_PFC_MUX(i2c2_a,     SDA2_A,                 SCL2_A);
+I2C_PFC_PIN(i2c2_b,     RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
+I2C_PFC_MUX(i2c2_b,     SDA2_B,                 SCL2_B);
+I2C_PFC_PIN(i2c2_c,     RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
+I2C_PFC_MUX(i2c2_c,     SDA2_C,                 SCL2_C);
+
+/* - I2C3 ------------------------------------------------------------------ */
+I2C_PFC_PIN(i2c3_a,     RCAR_GP_PIN(1, 14),     RCAR_GP_PIN(1, 15));
+I2C_PFC_MUX(i2c3_a,     SDA3_A,                 SCL3_A);
+I2C_PFC_PIN(i2c3_b,     RCAR_GP_PIN(1, 16),     RCAR_GP_PIN(1, 19));
+I2C_PFC_MUX(i2c3_b,     SDA3_B,                 SCL3_B);
+I2C_PFC_PIN(i2c3_c,     RCAR_GP_PIN(1, 22),     RCAR_GP_PIN(1, 23));
+I2C_PFC_MUX(i2c3_c,     SDA3_C,                 SCL3_C);
+
+/* - MMC macro -------------------------------------------------------------- */
+#define MMC_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
+#define MMC_PFC_CTRL(name, clk, cmd)            SH_PFC_MUX2(name, clk, cmd)
+#define MMC_PFC_DAT1(name, d0)                  SH_PFC_MUX1(name, d0)
+#define MMC_PFC_DAT4(name, d0, d1, d2, d3)      SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define MMC_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
+                        SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+
+/* - MMC -------------------------------------------------------------------- */
+MMC_PFC_PINS(mmc_ctrl,          RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
+MMC_PFC_CTRL(mmc_ctrl,          MMC_CLK,                MMC_CMD);
+MMC_PFC_PINS(mmc_data1,         RCAR_GP_PIN(1, 7));
+MMC_PFC_DAT1(mmc_data1,         MMC_D0);
+MMC_PFC_PINS(mmc_data4,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(2, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
+MMC_PFC_DAT4(mmc_data4,         MMC_D0,                 MMC_D1,
+                                MMC_D2,                 MMC_D3);
+MMC_PFC_PINS(mmc_data8,         RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(2, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6),
+                                RCAR_GP_PIN(1, 4),      RCAR_GP_PIN(1, 0),
+                                RCAR_GP_PIN(0, 30),     RCAR_GP_PIN(0, 31));
+MMC_PFC_DAT8(mmc_data8,         MMC_D0,                 MMC_D1,
+                                MMC_D2,                 MMC_D3,
+                                MMC_D4,                 MMC_D5,
+                                MMC_D6,                 MMC_D7);
+
+/* - SCIF CLOCK ------------------------------------------------------------- */
+SCIF_PFC_PIN(scif_clk,          RCAR_GP_PIN(1, 16));
+SCIF_PFC_CLK(scif_clk,          SCIF_CLK);
+
+/* - SCIF0 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif0_data_a,      RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 18));
+SCIF_PFC_DAT(scif0_data_a,      TX0_A,                  RX0_A);
+SCIF_PFC_PIN(scif0_data_b,      RCAR_GP_PIN(2, 3),      RCAR_GP_PIN(2, 2));
+SCIF_PFC_DAT(scif0_data_b,      TX0_B,                  RX0_B);
+SCIF_PFC_PIN(scif0_data_c,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(3, 31));
+SCIF_PFC_DAT(scif0_data_c,      TX0_C,                  RX0_C);
+SCIF_PFC_PIN(scif0_data_d,      RCAR_GP_PIN(3, 6),      RCAR_GP_PIN(3, 1));
+SCIF_PFC_DAT(scif0_data_d,      TX0_D,                  RX0_D);
+SCIF_PFC_PIN(scif0_ctrl,        RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SCIF_PFC_CTR(scif0_ctrl,        CTS0,                   RTS0);
+SCIF_PFC_PIN(scif0_clk,         RCAR_GP_PIN(1, 19));
+SCIF_PFC_CLK(scif0_clk,         SCK0);
+
+/* - SCIF1 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif1_data_a,      RCAR_GP_PIN(4, 0),      RCAR_GP_PIN(4, 1));
+SCIF_PFC_DAT(scif1_data_a,      TX1_A,                  RX1_A);
+SCIF_PFC_PIN(scif1_data_b,      RCAR_GP_PIN(2, 24),     RCAR_GP_PIN(2, 25));
+SCIF_PFC_DAT(scif1_data_b,      TX1_B,                  RX1_B);
+SCIF_PFC_PIN(scif1_data_c,      RCAR_GP_PIN(3, 22),     RCAR_GP_PIN(3, 21));
+SCIF_PFC_DAT(scif1_data_c,      TX1_C,                  RX1_C);
+SCIF_PFC_PIN(scif1_data_d,      RCAR_GP_PIN(1, 30),     RCAR_GP_PIN(1, 31));
+SCIF_PFC_DAT(scif1_data_d,      TX1_D,                  RX1_D);
+SCIF_PFC_PIN(scif1_ctrl_a,      RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
+SCIF_PFC_CTR(scif1_ctrl_a,      CTS1_A,                 RTS1_A);
+SCIF_PFC_PIN(scif1_ctrl_c,      RCAR_GP_PIN(3, 23),     RCAR_GP_PIN(3, 19));
+SCIF_PFC_CTR(scif1_ctrl_c,      CTS1_C,                 RTS1_C);
+SCIF_PFC_PIN(scif1_clk_a,       RCAR_GP_PIN(4, 2));
+SCIF_PFC_CLK(scif1_clk_a,       SCK1_A);
+SCIF_PFC_PIN(scif1_clk_c,       RCAR_GP_PIN(3, 20));
+SCIF_PFC_CLK(scif1_clk_c,       SCK1_C);
+
+/* - SCIF2 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif2_data_a,      RCAR_GP_PIN(2, 26),     RCAR_GP_PIN(2, 27));
+SCIF_PFC_DAT(scif2_data_a,      TX2_A,                  RX2_A);
+SCIF_PFC_PIN(scif2_data_b,      RCAR_GP_PIN(0, 29),     RCAR_GP_PIN(0, 28));
+SCIF_PFC_DAT(scif2_data_b,      TX2_B,                  RX2_B);
+SCIF_PFC_PIN(scif2_data_c,      RCAR_GP_PIN(4, 13),     RCAR_GP_PIN(4, 14));
+SCIF_PFC_DAT(scif2_data_c,      TX2_C,                  RX2_C);
+SCIF_PFC_PIN(scif2_data_d,      RCAR_GP_PIN(4, 15),     RCAR_GP_PIN(4, 16));
+SCIF_PFC_DAT(scif2_data_d,      TX2_D,                  RX2_D);
+SCIF_PFC_PIN(scif2_data_e,      RCAR_GP_PIN(0, 3),      RCAR_GP_PIN(0, 4));
+SCIF_PFC_DAT(scif2_data_e,      TX2_E,                  RX2_E);
+SCIF_PFC_PIN(scif2_clk_a,       RCAR_GP_PIN(3, 9));
+SCIF_PFC_CLK(scif2_clk_a,       SCK2_A);
+SCIF_PFC_PIN(scif2_clk_b,       PIN_NUMBER(3, 20));
+SCIF_PFC_CLK(scif2_clk_b,       SCK2_B);
+SCIF_PFC_PIN(scif2_clk_c,       RCAR_GP_PIN(4, 12));
+SCIF_PFC_CLK(scif2_clk_c,       SCK2_C);
+
+/* - SCIF3 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif3_data_a,      RCAR_GP_PIN(1, 10),     RCAR_GP_PIN(1, 9));
+SCIF_PFC_DAT(scif3_data_a,      TX3_A,                  RX3_A);
+SCIF_PFC_PIN(scif3_data_b,      RCAR_GP_PIN(3, 28),     RCAR_GP_PIN(3, 27));
+SCIF_PFC_DAT(scif3_data_b,      TX3_B,                  RX3_B);
+SCIF_PFC_PIN(scif3_data_c,      RCAR_GP_PIN(1, 3),      RCAR_GP_PIN(0, 31));
+SCIF_PFC_DAT(scif3_data_c,      TX3_C,                  RX3_C);
+SCIF_PFC_PIN(scif3_data_d,      RCAR_GP_PIN(3, 30),     RCAR_GP_PIN(3, 29));
+SCIF_PFC_DAT(scif3_data_d,      TX3_D,                  RX3_D);
+
+/* - SCIF4 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif4_data_a,      RCAR_GP_PIN(2, 5),      RCAR_GP_PIN(2, 4));
+SCIF_PFC_DAT(scif4_data_a,      TX4_A,                  RX4_A);
+SCIF_PFC_PIN(scif4_data_b,      RCAR_GP_PIN(3, 26),     RCAR_GP_PIN(3, 25));
+SCIF_PFC_DAT(scif4_data_b,      TX4_B,                  RX4_B);
+SCIF_PFC_PIN(scif4_data_c,      RCAR_GP_PIN(3, 0),      RCAR_GP_PIN(2, 31));
+SCIF_PFC_DAT(scif4_data_c,      TX4_C,                  RX4_C);
+
+/* - SCIF5 ------------------------------------------------------------------ */
+SCIF_PFC_PIN(scif5_data_a,      RCAR_GP_PIN(3, 17),     RCAR_GP_PIN(3, 18));
+SCIF_PFC_DAT(scif5_data_a,      TX5_A,                  RX5_A);
+SCIF_PFC_PIN(scif5_data_b,      RCAR_GP_PIN(1, 15),     RCAR_GP_PIN(1, 14));
+SCIF_PFC_DAT(scif5_data_b,      TX5_B,                  RX5_B);
+
+/* - SDHI macro ------------------------------------------------------------- */
+#define SDHI_PFC_PINS(name, args...)            SH_PFC_PINS(name, args)
+#define SDHI_PFC_DAT1(name, d0)                 SH_PFC_MUX1(name, d0)
+#define SDHI_PFC_DAT4(name, d0, d1, d2, d3)     SH_PFC_MUX4(name, d0, d1, d2, d3)
+#define SDHI_PFC_CTRL(name, clk, cmd)           SH_PFC_MUX2(name, clk, cmd)
+#define SDHI_PFC_CDPN(name, cd)                 SH_PFC_MUX1(name, cd)
+#define SDHI_PFC_WPPN(name, wp)                 SH_PFC_MUX1(name, wp)
+
+/* - SDHI0 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi0_cd,         RCAR_GP_PIN(3, 17));
+SDHI_PFC_CDPN(sdhi0_cd,         SD0_CD);
+SDHI_PFC_PINS(sdhi0_ctrl,       RCAR_GP_PIN(3, 11),     RCAR_GP_PIN(3, 12));
+SDHI_PFC_CTRL(sdhi0_ctrl,       SD0_CLK,                SD0_CMD);
+SDHI_PFC_PINS(sdhi0_data1,      RCAR_GP_PIN(3, 13));
+SDHI_PFC_DAT1(sdhi0_data1,      SD0_DAT0);
+SDHI_PFC_PINS(sdhi0_data4,      RCAR_GP_PIN(3, 13),     RCAR_GP_PIN(3, 14),
+                                RCAR_GP_PIN(3, 15),     RCAR_GP_PIN(3, 16));
+SDHI_PFC_DAT4(sdhi0_data4,      SD0_DAT0,               SD0_DAT1,
+                                SD0_DAT2,               SD0_DAT3);
+SDHI_PFC_PINS(sdhi0_wp,         RCAR_GP_PIN(3, 18));
+SDHI_PFC_WPPN(sdhi0_wp,         SD0_WP);
+
+/* - SDHI1 ------------------------------------------------------------------ */
+SDHI_PFC_PINS(sdhi1_cd_a,       RCAR_GP_PIN(0, 30));
+SDHI_PFC_CDPN(sdhi1_cd_a,       SD1_CD_A);
+SDHI_PFC_PINS(sdhi1_cd_b,       RCAR_GP_PIN(2, 24));
+SDHI_PFC_CDPN(sdhi1_cd_b,       SD1_CD_B);
+SDHI_PFC_PINS(sdhi1_ctrl_a,     RCAR_GP_PIN(1, 5),      RCAR_GP_PIN(1, 6));
+SDHI_PFC_CTRL(sdhi1_ctrl_a,     SD1_CLK_A,              SD1_CMD_A);
+SDHI_PFC_PINS(sdhi1_ctrl_b,     RCAR_GP_PIN(1, 17),     RCAR_GP_PIN(1, 16));
+SDHI_PFC_CTRL(sdhi1_ctrl_b,     SD1_CLK_B,              SD1_CMD_B);
+SDHI_PFC_PINS(sdhi1_data1_a,    RCAR_GP_PIN(1, 7));
+SDHI_PFC_DAT1(sdhi1_data1_a,    SD1_DAT0_A);
+SDHI_PFC_PINS(sdhi1_data1_b,    RCAR_GP_PIN(1, 18));
+SDHI_PFC_DAT1(sdhi1_data1_b,    SD1_DAT0_B);
+SDHI_PFC_PINS(sdhi1_data4_a,    RCAR_GP_PIN(1, 7),      RCAR_GP_PIN(1, 8),
+                                RCAR_GP_PIN(0, 5),      RCAR_GP_PIN(0, 6));
+SDHI_PFC_DAT4(sdhi1_data4_a,    SD1_DAT0_A,             SD1_DAT1_A,
+                                SD1_DAT2_A,             SD1_DAT3_A);
+SDHI_PFC_PINS(sdhi1_data4_b,    RCAR_GP_PIN(1, 18),     RCAR_GP_PIN(1, 19),
+                                RCAR_GP_PIN(1, 20),     RCAR_GP_PIN(1, 21));
+SDHI_PFC_DAT4(sdhi1_data4_b,    SD1_DAT0_B,             SD1_DAT1_B,
+                                SD1_DAT2_B,             SD1_DAT3_B);
+SDHI_PFC_PINS(sdhi1_wp_a,       RCAR_GP_PIN(0, 31));
+SDHI_PFC_WPPN(sdhi1_wp_a,       SD1_WP_A);
+SDHI_PFC_PINS(sdhi1_wp_b,       RCAR_GP_PIN(2, 25));
+SDHI_PFC_WPPN(sdhi1_wp_b,       SD1_WP_B);
+
+/* - SDH2 ------------------------------------------------------------------- */
+SDHI_PFC_PINS(sdhi2_cd_a,       RCAR_GP_PIN(4, 23));
+SDHI_PFC_CDPN(sdhi2_cd_a,       SD2_CD_A);
+SDHI_PFC_PINS(sdhi2_cd_b,       RCAR_GP_PIN(3, 27));
+SDHI_PFC_CDPN(sdhi2_cd_b,       SD2_CD_B);
+SDHI_PFC_PINS(sdhi2_ctrl_a,     RCAR_GP_PIN(4, 17),     RCAR_GP_PIN(4, 18));
+SDHI_PFC_CTRL(sdhi2_ctrl_a,     SD2_CLK_A,              SD2_CMD_A);
+SDHI_PFC_PINS(sdhi2_ctrl_b,     RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6));
+SDHI_PFC_CTRL(sdhi2_ctrl_b,     SD2_CLK_B,              SD2_CMD_B);
+SDHI_PFC_PINS(sdhi2_data1_a,    RCAR_GP_PIN(4, 19));
+SDHI_PFC_DAT1(sdhi2_data1_a,    SD2_DAT0_A);
+SDHI_PFC_PINS(sdhi2_data1_b,    RCAR_GP_PIN(4, 7));
+SDHI_PFC_DAT1(sdhi2_data1_b,    SD2_DAT0_B);
+SDHI_PFC_PINS(sdhi2_data4_a,    RCAR_GP_PIN(4, 19),     RCAR_GP_PIN(4, 20),
+                                RCAR_GP_PIN(4, 21),     RCAR_GP_PIN(4, 22));
+SDHI_PFC_DAT4(sdhi2_data4_a,    SD2_DAT0_A,             SD2_DAT1_A,
+                                SD2_DAT2_A,             SD2_DAT3_A);
+SDHI_PFC_PINS(sdhi2_data4_b,    RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8),
+                                RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26));
+SDHI_PFC_DAT4(sdhi2_data4_b,    SD2_DAT0_B,             SD2_DAT1_B,
+                                SD2_DAT2_B,             SD2_DAT3_B);
+SDHI_PFC_PINS(sdhi2_wp_a,       RCAR_GP_PIN(4, 24));
+SDHI_PFC_WPPN(sdhi2_wp_a,       SD2_WP_A);
+SDHI_PFC_PINS(sdhi2_wp_b,       RCAR_GP_PIN(3, 28));
+SDHI_PFC_WPPN(sdhi2_wp_b,       SD2_WP_B);
+
+/* - USB0 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb0,               RCAR_GP_PIN(0, 1));
+SH_PFC_MUX1(usb0,               PENC0);
+SH_PFC_PINS(usb0_ovc,           RCAR_GP_PIN(0, 3));
+SH_PFC_MUX1(usb0_ovc,           USB_OVC0);
+
+/* - USB1 ------------------------------------------------------------------- */
+SH_PFC_PINS(usb1,               RCAR_GP_PIN(0, 2));
+SH_PFC_MUX1(usb1,               PENC1);
+SH_PFC_PINS(usb1_ovc,           RCAR_GP_PIN(0, 4));
+SH_PFC_MUX1(usb1_ovc,           USB_OVC1);
+
+/* - VIN macros ------------------------------------------------------------- */
+#define VIN_PFC_PINS(name, args...)             SH_PFC_PINS(name, args)
+#define VIN_PFC_DAT8(name, d0, d1, d2, d3, d4, d5, d6, d7)      \
+        SH_PFC_MUX8(name, d0, d1, d2, d3, d4, d5, d6, d7)
+#define VIN_PFC_CLK(name, clk)                  SH_PFC_MUX1(name, clk)
+#define VIN_PFC_SYNC(name, hsync, vsync)        SH_PFC_MUX2(name, hsync, vsync)
+
+/* - VIN0 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin0_data8,        RCAR_GP_PIN(3, 29),     RCAR_GP_PIN(3, 30),
+                                RCAR_GP_PIN(3, 31),     RCAR_GP_PIN(4, 0),
+                                RCAR_GP_PIN(4, 1),      RCAR_GP_PIN(4, 2),
+                                RCAR_GP_PIN(4, 3),      RCAR_GP_PIN(4, 4));
+VIN_PFC_DAT8(vin0_data8,        VI0_DATA0_VI0_B0,       VI0_DATA1_VI0_B1,
+                                VI0_DATA2_VI0_B2,       VI0_DATA3_VI0_B3,
+                                VI0_DATA4_VI0_B4,       VI0_DATA5_VI0_B5,
+                                VI0_DATA6_VI0_G0,       VI0_DATA7_VI0_G1);
+VIN_PFC_PINS(vin0_clk,          RCAR_GP_PIN(3, 24));
+VIN_PFC_CLK(vin0_clk,           VI0_CLK);
+VIN_PFC_PINS(vin0_sync,         RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28));
+VIN_PFC_SYNC(vin0_sync,         VI0_HSYNC,              VI0_VSYNC);
+/* - VIN1 ------------------------------------------------------------------- */
+VIN_PFC_PINS(vin1_data8,        RCAR_GP_PIN(3, 25),     RCAR_GP_PIN(3, 26),
+                                RCAR_GP_PIN(3, 27),     RCAR_GP_PIN(3, 28),
+                                RCAR_GP_PIN(4, 5),      RCAR_GP_PIN(4, 6),
+                                RCAR_GP_PIN(4, 7),      RCAR_GP_PIN(4, 8));
+VIN_PFC_DAT8(vin1_data8,        VI1_DATA0,              VI1_DATA1,
+                                VI1_DATA2,              VI1_DATA3,
+                                VI1_DATA4,              VI1_DATA5,
+                                VI1_DATA6,              VI1_DATA7);
+VIN_PFC_PINS(vin1_clk,          RCAR_GP_PIN(4, 9));
+VIN_PFC_CLK(vin1_clk,           VI1_CLK);
+VIN_PFC_PINS(vin1_sync,         RCAR_GP_PIN(3, 21),     RCAR_GP_PIN(3, 22));
+VIN_PFC_SYNC(vin1_sync,         VI1_HSYNC,              VI1_VSYNC);
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(ether_rmii),
+        SH_PFC_PIN_GROUP(ether_link),
+        SH_PFC_PIN_GROUP(ether_magic),
+        SH_PFC_PIN_GROUP(hscif0_data_a),
+        SH_PFC_PIN_GROUP(hscif0_data_b),
+        SH_PFC_PIN_GROUP(hscif0_ctrl_a),
+        SH_PFC_PIN_GROUP(hscif0_ctrl_b),
+        SH_PFC_PIN_GROUP(hscif0_clk),
+        SH_PFC_PIN_GROUP(hscif1_data_a),
+        SH_PFC_PIN_GROUP(hscif1_data_b),
+        SH_PFC_PIN_GROUP(hscif1_ctrl_a),
+        SH_PFC_PIN_GROUP(hscif1_ctrl_b),
+        SH_PFC_PIN_GROUP(hscif1_clk_a),
+        SH_PFC_PIN_GROUP(hscif1_clk_b),
+        SH_PFC_PIN_GROUP(hspi0_a),
+        SH_PFC_PIN_GROUP(hspi0_b),
+        SH_PFC_PIN_GROUP(hspi1_a),
+        SH_PFC_PIN_GROUP(hspi1_b),
+        SH_PFC_PIN_GROUP(hspi2_a),
+        SH_PFC_PIN_GROUP(hspi2_b),
+        SH_PFC_PIN_GROUP(i2c1_a),
+        SH_PFC_PIN_GROUP(i2c1_b),
+        SH_PFC_PIN_GROUP(i2c2_a),
+        SH_PFC_PIN_GROUP(i2c2_b),
+        SH_PFC_PIN_GROUP(i2c2_c),
+        SH_PFC_PIN_GROUP(i2c3_a),
+        SH_PFC_PIN_GROUP(i2c3_b),
+        SH_PFC_PIN_GROUP(i2c3_c),
+        SH_PFC_PIN_GROUP(mmc_ctrl),
+        SH_PFC_PIN_GROUP(mmc_data1),
+        SH_PFC_PIN_GROUP(mmc_data4),
+        SH_PFC_PIN_GROUP(mmc_data8),
+        SH_PFC_PIN_GROUP(scif_clk),
+        SH_PFC_PIN_GROUP(scif0_data_a),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif0_data_c),
+        SH_PFC_PIN_GROUP(scif0_data_d),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif1_data_a),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif1_ctrl_a),
+        SH_PFC_PIN_GROUP(scif1_ctrl_c),
+        SH_PFC_PIN_GROUP(scif1_clk_a),
+        SH_PFC_PIN_GROUP(scif1_clk_c),
+        SH_PFC_PIN_GROUP(scif2_data_a),
+        SH_PFC_PIN_GROUP(scif2_data_b),
+        SH_PFC_PIN_GROUP(scif2_data_c),
+        SH_PFC_PIN_GROUP(scif2_data_d),
+        SH_PFC_PIN_GROUP(scif2_data_e),
+        SH_PFC_PIN_GROUP(scif2_clk_a),
+        SH_PFC_PIN_GROUP(scif2_clk_b),
+        SH_PFC_PIN_GROUP(scif2_clk_c),
+        SH_PFC_PIN_GROUP(scif3_data_a),
+        SH_PFC_PIN_GROUP(scif3_data_b),
+        SH_PFC_PIN_GROUP(scif3_data_c),
+        SH_PFC_PIN_GROUP(scif3_data_d),
+        SH_PFC_PIN_GROUP(scif4_data_a),
+        SH_PFC_PIN_GROUP(scif4_data_b),
+        SH_PFC_PIN_GROUP(scif4_data_c),
+        SH_PFC_PIN_GROUP(scif5_data_a),
+        SH_PFC_PIN_GROUP(scif5_data_b),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_cd_a),
+        SH_PFC_PIN_GROUP(sdhi1_cd_b),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl_a),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl_b),
+        SH_PFC_PIN_GROUP(sdhi1_data1_a),
+        SH_PFC_PIN_GROUP(sdhi1_data1_b),
+        SH_PFC_PIN_GROUP(sdhi1_data4_a),
+        SH_PFC_PIN_GROUP(sdhi1_data4_b),
+        SH_PFC_PIN_GROUP(sdhi1_wp_a),
+        SH_PFC_PIN_GROUP(sdhi1_wp_b),
+        SH_PFC_PIN_GROUP(sdhi2_cd_a),
+        SH_PFC_PIN_GROUP(sdhi2_cd_b),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl_a),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl_b),
+        SH_PFC_PIN_GROUP(sdhi2_data1_a),
+        SH_PFC_PIN_GROUP(sdhi2_data1_b),
+        SH_PFC_PIN_GROUP(sdhi2_data4_a),
+        SH_PFC_PIN_GROUP(sdhi2_data4_b),
+        SH_PFC_PIN_GROUP(sdhi2_wp_a),
+        SH_PFC_PIN_GROUP(sdhi2_wp_b),
+        SH_PFC_PIN_GROUP(usb0),
+        SH_PFC_PIN_GROUP(usb0_ovc),
+        SH_PFC_PIN_GROUP(usb1),
+        SH_PFC_PIN_GROUP(usb1_ovc),
+        SH_PFC_PIN_GROUP(vin0_data8),
+        SH_PFC_PIN_GROUP(vin0_clk),
+        SH_PFC_PIN_GROUP(vin0_sync),
+        SH_PFC_PIN_GROUP(vin1_data8),
+        SH_PFC_PIN_GROUP(vin1_clk),
+        SH_PFC_PIN_GROUP(vin1_sync),
+};
+
+static const char * const ether_groups[] = {
+        "ether_rmii",
+        "ether_link",
+        "ether_magic",
+};
+
+static const char * const hscif0_groups[] = {
+        "hscif0_data_a",
+        "hscif0_data_b",
+        "hscif0_ctrl_a",
+        "hscif0_ctrl_b",
+        "hscif0_clk",
+};
+
+static const char * const hscif1_groups[] = {
+        "hscif1_data_a",
+        "hscif1_data_b",
+        "hscif1_ctrl_a",
+        "hscif1_ctrl_b",
+        "hscif1_clk_a",
+        "hscif1_clk_b",
+};
+
+static const char * const hspi0_groups[] = {
+        "hspi0_a",
+        "hspi0_b",
+};
+
+static const char * const hspi1_groups[] = {
+        "hspi1_a",
+        "hspi1_b",
+};
+
+static const char * const hspi2_groups[] = {
+        "hspi2_a",
+        "hspi2_b",
+};
+
+static const char * const i2c1_groups[] = {
+        "i2c1_a",
+        "i2c1_b",
+};
+
+static const char * const i2c2_groups[] = {
+        "i2c2_a",
+        "i2c2_b",
+        "i2c2_c",
+};
+
+static const char * const i2c3_groups[] = {
+        "i2c3_a",
+        "i2c3_b",
+        "i2c3_c",
+};
+
+static const char * const mmc_groups[] = {
+        "mmc_ctrl",
+        "mmc_data1",
+        "mmc_data4",
+        "mmc_data8",
+};
+
+static const char * const scif_clk_groups[] = {
+        "scif_clk",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data_a",
+        "scif0_data_b",
+        "scif0_data_c",
+        "scif0_data_d",
+        "scif0_ctrl",
+        "scif0_clk",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data_a",
+        "scif1_data_b",
+        "scif1_data_c",
+        "scif1_data_d",
+        "scif1_ctrl_a",
+        "scif1_ctrl_c",
+        "scif1_clk_a",
+        "scif1_clk_c",
+};
+
+static const char * const scif2_groups[] = {
+        "scif2_data_a",
+        "scif2_data_b",
+        "scif2_data_c",
+        "scif2_data_d",
+        "scif2_data_e",
+        "scif2_clk_a",
+        "scif2_clk_b",
+        "scif2_clk_c",
+};
+
+static const char * const scif3_groups[] = {
+        "scif3_data_a",
+        "scif3_data_b",
+        "scif3_data_c",
+        "scif3_data_d",
+};
+
+static const char * const scif4_groups[] = {
+        "scif4_data_a",
+        "scif4_data_b",
+        "scif4_data_c",
+};
+
+static const char * const scif5_groups[] = {
+        "scif5_data_a",
+        "scif5_data_b",
+};
+
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_cd",
+        "sdhi0_ctrl",
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_cd_a",
+        "sdhi1_cd_b",
+        "sdhi1_ctrl_a",
+        "sdhi1_ctrl_b",
+        "sdhi1_data1_a",
+        "sdhi1_data1_b",
+        "sdhi1_data4_a",
+        "sdhi1_data4_b",
+        "sdhi1_wp_a",
+        "sdhi1_wp_b",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_cd_a",
+        "sdhi2_cd_b",
+        "sdhi2_ctrl_a",
+        "sdhi2_ctrl_b",
+        "sdhi2_data1_a",
+        "sdhi2_data1_b",
+        "sdhi2_data4_a",
+        "sdhi2_data4_b",
+        "sdhi2_wp_a",
+        "sdhi2_wp_b",
+};
+
+static const char * const usb0_groups[] = {
+        "usb0",
+        "usb0_ovc",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1",
+        "usb1_ovc",
+};
+
+static const char * const vin0_groups[] = {
+        "vin0_data8",
+        "vin0_clk",
+        "vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+        "vin1_data8",
+        "vin1_clk",
+        "vin1_sync",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(ether),
+        SH_PFC_FUNCTION(hscif0),
+        SH_PFC_FUNCTION(hscif1),
+        SH_PFC_FUNCTION(hspi0),
+        SH_PFC_FUNCTION(hspi1),
+        SH_PFC_FUNCTION(hspi2),
+        SH_PFC_FUNCTION(i2c1),
+        SH_PFC_FUNCTION(i2c2),
+        SH_PFC_FUNCTION(i2c3),
+        SH_PFC_FUNCTION(mmc),
+        SH_PFC_FUNCTION(scif_clk),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scif2),
+        SH_PFC_FUNCTION(scif3),
+        SH_PFC_FUNCTION(scif4),
+        SH_PFC_FUNCTION(scif5),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
+        SH_PFC_FUNCTION(vin0),
+        SH_PFC_FUNCTION(vin1),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
+                GP_0_31_FN,     FN_IP1_14_11,
+                GP_0_30_FN,     FN_IP1_10_8,
+                GP_0_29_FN,     FN_IP1_7_5,
+                GP_0_28_FN,     FN_IP1_4_2,
+                GP_0_27_FN,     FN_IP1_1,
+                GP_0_26_FN,     FN_IP1_0,
+                GP_0_25_FN,     FN_IP0_30,
+                GP_0_24_FN,     FN_IP0_29,
+                GP_0_23_FN,     FN_IP0_28,
+                GP_0_22_FN,     FN_IP0_27,
+                GP_0_21_FN,     FN_IP0_26,
+                GP_0_20_FN,     FN_IP0_25,
+                GP_0_19_FN,     FN_IP0_24,
+                GP_0_18_FN,     FN_IP0_23,
+                GP_0_17_FN,     FN_IP0_22,
+                GP_0_16_FN,     FN_IP0_21,
+                GP_0_15_FN,     FN_IP0_20,
+                GP_0_14_FN,     FN_IP0_19,
+                GP_0_13_FN,     FN_IP0_18,
+                GP_0_12_FN,     FN_IP0_17,
+                GP_0_11_FN,     FN_IP0_16,
+                GP_0_10_FN,     FN_IP0_15,
+                GP_0_9_FN,      FN_A3,
+                GP_0_8_FN,      FN_A2,
+                GP_0_7_FN,      FN_A1,
+                GP_0_6_FN,      FN_IP0_14_12,
+                GP_0_5_FN,      FN_IP0_11_8,
+                GP_0_4_FN,      FN_IP0_7_5,
+                GP_0_3_FN,      FN_IP0_4_2,
+                GP_0_2_FN,      FN_PENC1,
+                GP_0_1_FN,      FN_PENC0,
+                GP_0_0_FN,      FN_IP0_1_0 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xfffc0008, 32, 1) {
+                GP_1_31_FN,     FN_IP4_6_4,
+                GP_1_30_FN,     FN_IP4_3_1,
+                GP_1_29_FN,     FN_IP4_0,
+                GP_1_28_FN,     FN_IP3_31,
+                GP_1_27_FN,     FN_IP3_30,
+                GP_1_26_FN,     FN_IP3_29,
+                GP_1_25_FN,     FN_IP3_28,
+                GP_1_24_FN,     FN_IP3_27,
+                GP_1_23_FN,     FN_IP3_26_24,
+                GP_1_22_FN,     FN_IP3_23_21,
+                GP_1_21_FN,     FN_IP3_20_19,
+                GP_1_20_FN,     FN_IP3_18_16,
+                GP_1_19_FN,     FN_IP3_15_13,
+                GP_1_18_FN,     FN_IP3_12_10,
+                GP_1_17_FN,     FN_IP3_9_8,
+                GP_1_16_FN,     FN_IP3_7_5,
+                GP_1_15_FN,     FN_IP3_4_2,
+                GP_1_14_FN,     FN_IP3_1_0,
+                GP_1_13_FN,     FN_IP2_31,
+                GP_1_12_FN,     FN_IP2_30,
+                GP_1_11_FN,     FN_IP2_17,
+                GP_1_10_FN,     FN_IP2_16_14,
+                GP_1_9_FN,      FN_IP2_13_12,
+                GP_1_8_FN,      FN_IP2_11_9,
+                GP_1_7_FN,      FN_IP2_8_6,
+                GP_1_6_FN,      FN_IP2_5_3,
+                GP_1_5_FN,      FN_IP2_2_0,
+                GP_1_4_FN,      FN_IP1_29_28,
+                GP_1_3_FN,      FN_IP1_27_25,
+                GP_1_2_FN,      FN_IP1_24,
+                GP_1_1_FN,      FN_WE0,
+                GP_1_0_FN,      FN_IP1_23_21 }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xfffc000c, 32, 1) {
+                GP_2_31_FN,     FN_IP6_7,
+                GP_2_30_FN,     FN_IP6_6_5,
+                GP_2_29_FN,     FN_IP6_4_2,
+                GP_2_28_FN,     FN_IP6_1_0,
+                GP_2_27_FN,     FN_IP5_30_29,
+                GP_2_26_FN,     FN_IP5_28_26,
+                GP_2_25_FN,     FN_IP5_25_23,
+                GP_2_24_FN,     FN_IP5_22_21,
+                GP_2_23_FN,     FN_AUDIO_CLKB,
+                GP_2_22_FN,     FN_AUDIO_CLKA,
+                GP_2_21_FN,     FN_IP5_20_18,
+                GP_2_20_FN,     FN_IP5_17_15,
+                GP_2_19_FN,     FN_IP5_14_13,
+                GP_2_18_FN,     FN_IP5_12,
+                GP_2_17_FN,     FN_IP5_11_10,
+                GP_2_16_FN,     FN_IP5_9_8,
+                GP_2_15_FN,     FN_IP5_7,
+                GP_2_14_FN,     FN_IP5_6,
+                GP_2_13_FN,     FN_IP5_5_4,
+                GP_2_12_FN,     FN_IP5_3_2,
+                GP_2_11_FN,     FN_IP5_1_0,
+                GP_2_10_FN,     FN_IP4_30_29,
+                GP_2_9_FN,      FN_IP4_28_27,
+                GP_2_8_FN,      FN_IP4_26_25,
+                GP_2_7_FN,      FN_IP4_24_21,
+                GP_2_6_FN,      FN_IP4_20_17,
+                GP_2_5_FN,      FN_IP4_16_15,
+                GP_2_4_FN,      FN_IP4_14_13,
+                GP_2_3_FN,      FN_IP4_12_11,
+                GP_2_2_FN,      FN_IP4_10_9,
+                GP_2_1_FN,      FN_IP4_8,
+                GP_2_0_FN,      FN_IP4_7 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xfffc0010, 32, 1) {
+                GP_3_31_FN,     FN_IP8_10_9,
+                GP_3_30_FN,     FN_IP8_8_6,
+                GP_3_29_FN,     FN_IP8_5_3,
+                GP_3_28_FN,     FN_IP8_2_0,
+                GP_3_27_FN,     FN_IP7_31_29,
+                GP_3_26_FN,     FN_IP7_28_25,
+                GP_3_25_FN,     FN_IP7_24_22,
+                GP_3_24_FN,     FN_IP7_21,
+                GP_3_23_FN,     FN_IP7_20_18,
+                GP_3_22_FN,     FN_IP7_17_15,
+                GP_3_21_FN,     FN_IP7_14_12,
+                GP_3_20_FN,     FN_IP7_11_9,
+                GP_3_19_FN,     FN_IP7_8_6,
+                GP_3_18_FN,     FN_IP7_5_4,
+                GP_3_17_FN,     FN_IP7_3_2,
+                GP_3_16_FN,     FN_IP7_1_0,
+                GP_3_15_FN,     FN_IP6_31_30,
+                GP_3_14_FN,     FN_IP6_29_28,
+                GP_3_13_FN,     FN_IP6_27_26,
+                GP_3_12_FN,     FN_IP6_25_24,
+                GP_3_11_FN,     FN_IP6_23_22,
+                GP_3_10_FN,     FN_IP6_21,
+                GP_3_9_FN,      FN_IP6_20_19,
+                GP_3_8_FN,      FN_IP6_18_17,
+                GP_3_7_FN,      FN_IP6_16,
+                GP_3_6_FN,      FN_IP6_15_14,
+                GP_3_5_FN,      FN_IP6_13,
+                GP_3_4_FN,      FN_IP6_12_11,
+                GP_3_3_FN,      FN_IP6_10,
+                GP_3_2_FN,      FN_SSI_SCK34,
+                GP_3_1_FN,      FN_IP6_9,
+                GP_3_0_FN,      FN_IP6_8 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xfffc0014, 32, 1) {
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                0, 0,
+                GP_4_26_FN,     FN_AVS2,
+                GP_4_25_FN,     FN_AVS1,
+                GP_4_24_FN,     FN_IP10_24_22,
+                GP_4_23_FN,     FN_IP10_21_19,
+                GP_4_22_FN,     FN_IP10_18_16,
+                GP_4_21_FN,     FN_IP10_15_13,
+                GP_4_20_FN,     FN_IP10_12_9,
+                GP_4_19_FN,     FN_IP10_8_6,
+                GP_4_18_FN,     FN_IP10_5_3,
+                GP_4_17_FN,     FN_IP10_2_0,
+                GP_4_16_FN,     FN_IP9_29_27,
+                GP_4_15_FN,     FN_IP9_26_24,
+                GP_4_14_FN,     FN_IP9_23_21,
+                GP_4_13_FN,     FN_IP9_20_18,
+                GP_4_12_FN,     FN_IP9_17_15,
+                GP_4_11_FN,     FN_IP9_14_12,
+                GP_4_10_FN,     FN_IP9_11_9,
+                GP_4_9_FN,      FN_IP9_8_6,
+                GP_4_8_FN,      FN_IP9_5_3,
+                GP_4_7_FN,      FN_IP9_2_0,
+                GP_4_6_FN,      FN_IP8_29_27,
+                GP_4_5_FN,      FN_IP8_26_24,
+                GP_4_4_FN,      FN_IP8_23_22,
+                GP_4_3_FN,      FN_IP8_21_19,
+                GP_4_2_FN,      FN_IP8_18_16,
+                GP_4_1_FN,      FN_IP8_15_14,
+                GP_4_0_FN,      FN_IP8_13_11 }
+        },
+
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xfffc0020, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 1, 1, 1, 3, 4, 3, 3, 2) {
+                /* IP0_31 [1] */
+                0,      0,
+                /* IP0_30 [1] */
+                FN_A19, 0,
+                /* IP0_29 [1] */
+                FN_A18, 0,
+                /* IP0_28 [1] */
+                FN_A17, 0,
+                /* IP0_27 [1] */
+                FN_A16, 0,
+                /* IP0_26 [1] */
+                FN_A15, 0,
+                /* IP0_25 [1] */
+                FN_A14, 0,
+                /* IP0_24 [1] */
+                FN_A13, 0,
+                /* IP0_23 [1] */
+                FN_A12, 0,
+                /* IP0_22 [1] */
+                FN_A11, 0,
+                /* IP0_21 [1] */
+                FN_A10, 0,
+                /* IP0_20 [1] */
+                FN_A9,  0,
+                /* IP0_19 [1] */
+                FN_A8,  0,
+                /* IP0_18 [1] */
+                FN_A7,  0,
+                /* IP0_17 [1] */
+                FN_A6,  0,
+                /* IP0_16 [1] */
+                FN_A5,  0,
+                /* IP0_15 [1] */
+                FN_A4,  0,
+                /* IP0_14_12 [3] */
+                FN_SD1_DAT3_A,  FN_MMC_D3,      0,              FN_A0,
+                FN_ATAG0_A,     0,              FN_REMOCON_B,   0,
+                /* IP0_11_8 [4] */
+                FN_SD1_DAT2_A,  FN_MMC_D2,      0,              FN_BS,
+                FN_ATADIR0_A,   0,              FN_SDSELF_B,    0,
+                FN_PWM4_B,      0,              0,              0,
+                0,              0,              0,              0,
+                /* IP0_7_5 [3] */
+                FN_AUDATA1,     FN_ARM_TRACEDATA_1,     FN_GPSIN_C,     FN_USB_OVC1,
+                FN_RX2_E,       FN_SCL2_B,              0,              0,
+                /* IP0_4_2 [3] */
+                FN_AUDATA0,     FN_ARM_TRACEDATA_0,     FN_GPSCLK_C,    FN_USB_OVC0,
+                FN_TX2_E,       FN_SDA2_B,              0,              0,
+                /* IP0_1_0 [2] */
+                FN_PRESETOUT,   0,      FN_PWM1,        0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xfffc0024, 32,
+                             1, 1, 2, 3, 1, 3, 3, 1, 2, 4, 3, 3, 3, 1, 1) {
+                /* IP1_31 [1] */
+                0,      0,
+                /* IP1_30 [1] */
+                0,      0,
+                /* IP1_29_28 [2] */
+                FN_EX_CS1,      FN_MMC_D4,      0,      0,
+                /* IP1_27_25 [3] */
+                FN_SSI_WS1_B,   FN_EX_CS0,      FN_SCL2_A,      FN_TX3_C,
+                FN_TS_SCK0_A,   0,              0,              0,
+                /* IP1_24 [1] */
+                FN_WE1,         FN_ATAWR0_B,
+                /* IP1_23_21 [3] */
+                FN_MMC_D5,      FN_ATADIR0_B,   0,              FN_RD_WR,
+                0,              0,              0,              0,
+                /* IP1_20_18 [3] */
+                FN_SSI_SCK1_B,  FN_ATAG0_B,     FN_CS1_A26,     FN_SDA2_A,
+                FN_SCK2_B,      0,              0,              0,
+                /* IP1_17 [1] */
+                FN_CS0,         FN_HSPI_RX1_B,
+                /* IP1_16_15 [2] */
+                FN_CLKOUT,      FN_HSPI_TX1_B,  FN_PWM0_B,      0,
+                /* IP1_14_11 [4] */
+                FN_SD1_WP_A,    FN_MMC_D7,      0,              FN_A25,
+                FN_DACK1_A,     0,              FN_HCTS0_B,     FN_RX3_C,
+                FN_TS_SDAT0_A,  0,              0,              0,
+                0,              0,              0,              0,
+                /* IP1_10_8 [3] */
+                FN_SD1_CLK_B,   FN_MMC_D6,      0,              FN_A24,
+                FN_DREQ1_A,     0,              FN_HRX0_B,      FN_TS_SPSYNC0_A,
+                /* IP1_7_5 [3] */
+                FN_A23,         FN_HTX0_B,      FN_TX2_B,       FN_DACK2_A,
+                FN_TS_SDEN0_A,  0,              0,              0,
+                /* IP1_4_2 [3] */
+                FN_A22,         FN_HRTS0_B,     FN_RX2_B,       FN_DREQ2_A,
+                0,              0,              0,              0,
+                /* IP1_1 [1] */
+                FN_A21,         FN_HSPI_CLK1_B,
+                /* IP1_0 [1] */
+                FN_A20,         FN_HSPI_CS1_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xfffc0028, 32,
+                             1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 1, 3, 2, 3, 3, 3, 3) {
+                /* IP2_31 [1] */
+                FN_MLB_CLK,     FN_IRQ1_A,
+                /* IP2_30 [1] */
+                FN_RD_WR_B,     FN_IRQ0,
+                /* IP2_29 [1] */
+                FN_D11,         0,
+                /* IP2_28 [1] */
+                FN_D10,         0,
+                /* IP2_27 [1] */
+                FN_D9,          0,
+                /* IP2_26 [1] */
+                FN_D8,          0,
+                /* IP2_25 [1] */
+                FN_D7,          0,
+                /* IP2_24 [1] */
+                FN_D6,          0,
+                /* IP2_23 [1] */
+                FN_D5,          0,
+                /* IP2_22 [1] */
+                FN_D4,          0,
+                /* IP2_21 [1] */
+                FN_D3,          0,
+                /* IP2_20 [1] */
+                FN_D2,          0,
+                /* IP2_19 [1] */
+                FN_D1,          0,
+                /* IP2_18 [1] */
+                FN_D0,          0,
+                /* IP2_17 [1] */
+                FN_EX_WAIT0,    FN_PWM0_C,
+                /* IP2_16_14 [3] */
+                FN_DACK0,       0,      0,      FN_TX3_A,
+                FN_DRACK0,      0,      0,      0,
+                /* IP2_13_12 [2] */
+                FN_DREQ0_A,     0,      0,      FN_RX3_A,
+                /* IP2_11_9 [3] */
+                FN_SD1_DAT1_A,  FN_MMC_D1,      0,      FN_ATAWR0_A,
+                FN_EX_CS5,      FN_EX_WAIT2_A,  0,      0,
+                /* IP2_8_6 [3] */
+                FN_SD1_DAT0_A,  FN_MMC_D0,      0,      FN_ATARD0,
+                FN_EX_CS4,      FN_EX_WAIT1_A,  0,      0,
+                /* IP2_5_3 [3] */
+                FN_SD1_CMD_A,   FN_MMC_CMD,     0,      FN_ATACS10,
+                FN_EX_CS3,      0,              0,      0,
+                /* IP2_2_0 [3] */
+                FN_SD1_CLK_A,   FN_MMC_CLK,     0,      FN_ATACS00,
+                FN_EX_CS2,      0,              0,      0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xfffc002c, 32,
+                             1, 1, 1, 1, 1, 3, 3, 2,
+                             3, 3, 3, 2, 3, 3, 2) {
+                /* IP3_31 [1] */
+                FN_DU0_DR6,     FN_LCDOUT6,
+                /* IP3_30 [1] */
+                FN_DU0_DR5,     FN_LCDOUT5,
+                /* IP3_29 [1] */
+                FN_DU0_DR4,     FN_LCDOUT4,
+                /* IP3_28 [1] */
+                FN_DU0_DR3,     FN_LCDOUT3,
+                /* IP3_27 [1] */
+                FN_DU0_DR2,     FN_LCDOUT2,
+                /* IP3_26_24 [3] */
+                FN_SSI_WS4,             FN_DU0_DR1,     FN_LCDOUT1,     FN_AUDATA3,
+                FN_ARM_TRACEDATA_3,     FN_SCL3_C,      FN_ADICHS2,     FN_TS_SPSYNC0_B,
+                /* IP3_23_21 [3] */
+                FN_SSI_SCK4,            FN_DU0_DR0,     FN_LCDOUT0,     FN_AUDATA2,
+                FN_ARM_TRACEDATA_2,     FN_SDA3_C,      FN_ADICHS1,     FN_TS_SDEN0_B,
+                /* IP3_20_19 [2] */
+                FN_SD1_DAT3_B,  FN_HRTS0_A,     FN_RTS0,        0,
+                /* IP3_18_16 [3] */
+                FN_SD1_DAT2_B,  FN_HCTS0_A,     FN_CTS0,        0,
+                0,              0,              0,              0,
+                /* IP3_15_13 [3] */
+                FN_SD1_DAT1_B,  FN_HSCK0,       FN_SCK0,        FN_SCL3_B,
+                0,              0,              0,              0,
+                /* IP3_12_10 [3] */
+                FN_SD1_DAT0_B,  FN_HRX0_A,      FN_RX0_A,       0,
+                0,              0,              0,              0,
+                /* IP3_9_8 [2] */
+                FN_SD1_CLK_B,   FN_HTX0_A,      FN_TX0_A,       0,
+                /* IP3_7_5 [3] */
+                FN_SD1_CMD_B,   FN_SCIF_CLK,    FN_AUDIO_CLKOUT_B,      FN_CAN_CLK_B,
+                FN_SDA3_B,      0,              0,                      0,
+                /* IP3_4_2 [3] */
+                FN_MLB_DAT,     FN_TX5_B,       FN_SCL3_A,      FN_IRQ3_A,
+                FN_SDSELF_B,    0,              0,              0,
+                /* IP3_1_0 [2] */
+                FN_MLB_SIG,     FN_RX5_B,       FN_SDA3_A,      FN_IRQ2_A,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xfffc0030, 32,
+                             1, 2, 2, 2, 4, 4, 2, 2, 2, 2, 1, 1, 3, 3, 1) {
+                /* IP4_31 [1] */
+                0,      0,
+                /* IP4_30_29 [2] */
+                FN_VI0_R4_B,    FN_DU0_DB4,     FN_LCDOUT20,    0,
+                /* IP4_28_27 [2] */
+                FN_VI0_R3_B,    FN_DU0_DB3,     FN_LCDOUT19,    0,
+                /* IP4_26_25 [2] */
+                FN_VI0_R2_B,    FN_DU0_DB2,     FN_LCDOUT18,    0,
+                /* IP4_24_21 [4] */
+                FN_AUDIO_CLKC,  FN_VI0_R1_B,            FN_DU0_DB1,     FN_LCDOUT17,
+                FN_AUDATA7,     FN_ARM_TRACEDATA_7,     FN_GPSIN_A,     0,
+                FN_ADICS_SAMP,  FN_TS_SCK0_B,           0,              0,
+                0,              0,                      0,              0,
+                /* IP4_20_17 [4] */
+                FN_SSI_SCK2_B,  FN_VI0_R0_B,            FN_DU0_DB0,     FN_LCDOUT16,
+                FN_AUDATA6,     FN_ARM_TRACEDATA_6,     FN_GPSCLK_A,    FN_PWM0_A,
+                FN_ADICLK,      FN_TS_SDAT0_B,          0,              0,
+                0,              0,                      0,              0,
+                /* IP4_16_15 [2] */
+                FN_DU0_DG7,     FN_LCDOUT15,    FN_TX4_A,       0,
+                /* IP4_14_13 [2] */
+                FN_DU0_DG6,     FN_LCDOUT14,    FN_RX4_A,       0,
+                /* IP4_12_11 [2] */
+                FN_DU0_DG5,     FN_LCDOUT13,    FN_TX0_B,       0,
+                /* IP4_10_9 [2] */
+                FN_DU0_DG4,     FN_LCDOUT12,    FN_RX0_B,       0,
+                /* IP4_8 [1] */
+                FN_DU0_DG3,     FN_LCDOUT11,
+                /* IP4_7 [1] */
+                FN_DU0_DG2,     FN_LCDOUT10,
+                /* IP4_6_4 [3] */
+                FN_DU0_DG1,     FN_LCDOUT9,     FN_AUDATA5,     FN_ARM_TRACEDATA_5,
+                FN_RX1_D,       FN_CAN0_RX_A,   FN_ADIDATA,     0,
+                /* IP4_3_1 [3] */
+                FN_DU0_DG0,     FN_LCDOUT8,     FN_AUDATA4,     FN_ARM_TRACEDATA_4,
+                FN_TX1_D,       FN_CAN0_TX_A,   FN_ADICHS0,     0,
+                /* IP4_0 [1] */
+                FN_DU0_DR7,     FN_LCDOUT7,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xfffc0034, 32,
+                             1, 2, 3, 3, 2, 3, 3, 2, 1, 2, 2, 1, 1, 2, 2, 2) {
+
+                /* IP5_31 [1] */
+                0, 0,
+                /* IP5_30_29 [2] */
+                FN_SSI_SDATA7,  FN_HSPI_TX0_B,  FN_RX2_A,       FN_CAN0_RX_B,
+                /* IP5_28_26 [3] */
+                FN_SSI_SDATA8,  FN_SSI_SCK2_A,  FN_HSPI_CS0_B,  FN_TX2_A,
+                FN_CAN0_TX_B,   0,              0,              0,
+                /* IP5_25_23 [3] */
+                FN_SD1_WP_B,    FN_SSI_WS78,    FN_HSPI_CLK0_B, FN_RX1_B,
+                FN_CAN_CLK_D,   0,              0,              0,
+                /* IP5_22_21 [2] */
+                FN_SD1_CD_B,    FN_SSI_SCK78,   FN_HSPI_RX0_B,  FN_TX1_B,
+                /* IP5_20_18 [3] */
+                FN_SSI_WS1_A,           FN_DU0_CDE,     FN_QPOLB,       FN_AUDSYNC,
+                FN_ARM_TRACECTL,        FN_FMIN_D,      0,              0,
+                /* IP5_17_15 [3] */
+                FN_SSI_SCK1_A,          FN_DU0_DISP,    FN_QPOLA,       FN_AUDCK,
+                FN_ARM_TRACECLK,        FN_BPFCLK_D,    0,              0,
+                /* IP5_14_13 [2] */
+                FN_DU0_EXODDF_DU0_ODDF_DISP_CDE,        FN_QCPV_QDE,
+                FN_FMCLK_D,                             0,
+                /* IP5_12 [1] */
+                FN_DU0_EXVSYNC_DU0_VSYNC,       FN_QSTB_QHE,
+                /* IP5_11_10 [2] */
+                FN_SSI_WS2_B,   FN_DU0_EXHSYNC_DU0_HSYNC,
+                FN_QSTH_QHS,    0,
+                /* IP5_9_8 [2] */
+                FN_DU0_DOTCLKO_UT1,     FN_QSTVB_QVE,
+                FN_AUDIO_CLKOUT_A,      FN_REMOCON_C,
+                /* IP5_7 [1] */
+                FN_DU0_DOTCLKO_UT0,     FN_QCLK,
+                /* IP5_6 [1] */
+                FN_DU0_DOTCLKIN,        FN_QSTVA_QVS,
+                /* IP5_5_4 [2] */
+                FN_VI1_DATA11_B,        FN_DU0_DB7,     FN_LCDOUT23,    0,
+                /* IP5_3_2 [2] */
+                FN_VI1_DATA10_B,        FN_DU0_DB6,     FN_LCDOUT22,    0,
+                /* IP5_1_0 [2] */
+                FN_VI0_R5_B,            FN_DU0_DB5,     FN_LCDOUT21,    0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xfffc0038, 32,
+                             2, 2, 2, 2, 2, 1, 2, 2, 1, 2,
+                             1, 2, 1, 1, 1, 1, 2, 3, 2) {
+                /* IP6_31_30 [2] */
+                FN_SD0_DAT2,    0,      FN_SUB_TDI,     0,
+                /* IP6_29_28 [2] */
+                FN_SD0_DAT1,    0,      FN_SUB_TCK,     0,
+                /* IP6_27_26 [2] */
+                FN_SD0_DAT0,    0,      FN_SUB_TMS,     0,
+                /* IP6_25_24 [2] */
+                FN_SD0_CMD,     0,      FN_SUB_TRST,    0,
+                /* IP6_23_22 [2] */
+                FN_SD0_CLK,     0,      FN_SUB_TDO,     0,
+                /* IP6_21 [1] */
+                FN_SSI_SDATA0,          FN_ARM_TRACEDATA_15,
+                /* IP6_20_19 [2] */
+                FN_SSI_SDATA1,          FN_ARM_TRACEDATA_14,
+                FN_SCL1_A,              FN_SCK2_A,
+                /* IP6_18_17 [2] */
+                FN_SSI_SDATA2,          FN_HSPI_CS2_A,
+                FN_ARM_TRACEDATA_13,    FN_SDA1_A,
+                /* IP6_16 [1] */
+                FN_SSI_WS012,           FN_ARM_TRACEDATA_12,
+                /* IP6_15_14 [2] */
+                FN_SSI_SCK012,          FN_ARM_TRACEDATA_11,
+                FN_TX0_D,               0,
+                /* IP6_13 [1] */
+                FN_SSI_SDATA3,          FN_ARM_TRACEDATA_10,
+                /* IP6_12_11 [2] */
+                FN_SSI_SDATA4,          FN_SSI_WS2_A,
+                FN_ARM_TRACEDATA_9,     0,
+                /* IP6_10 [1] */
+                FN_SSI_WS34,            FN_ARM_TRACEDATA_8,
+                /* IP6_9 [1] */
+                FN_SSI_SDATA5,          FN_RX0_D,
+                /* IP6_8 [1] */
+                FN_SSI_WS5,             FN_TX4_C,
+                /* IP6_7 [1] */
+                FN_SSI_SCK5,            FN_RX4_C,
+                /* IP6_6_5 [2] */
+                FN_SSI_SDATA6,          FN_HSPI_TX2_A,
+                FN_FMIN_B,              0,
+                /* IP6_4_2 [3] */
+                FN_SSI_WS6,             FN_HSPI_CLK2_A,
+                FN_BPFCLK_B,            FN_CAN1_RX_B,
+                0,      0,      0,      0,
+                /* IP6_1_0 [2] */
+                FN_SSI_SCK6,            FN_HSPI_RX2_A,
+                FN_FMCLK_B,             FN_CAN1_TX_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xfffc003c, 32,
+                             3, 4, 3, 1, 3, 3, 3, 3, 3, 2, 2, 2) {
+
+                /* IP7_31_29 [3] */
+                FN_VI0_HSYNC,   FN_SD2_CD_B,    FN_VI1_DATA2,   FN_DU1_DR2,
+                0,              FN_HSPI_CS1_A,  FN_RX3_B,       0,
+                /* IP7_28_25 [4] */
+                FN_VI0_FIELD,   FN_SD2_DAT3_B,  FN_VI0_R3_C,    FN_VI1_DATA1,
+                FN_DU1_DG7,     0,              FN_HSPI_CLK1_A, FN_TX4_B,
+                0,      0,      0,      0,
+                0,      0,      0,      0,
+                /* IP7_24_22 [3] */
+                FN_VI0_CLKENB,  FN_SD2_DAT2_B,  FN_VI1_DATA0,   FN_DU1_DG6,
+                0,              FN_HSPI_RX1_A,  FN_RX4_B,       0,
+                /* IP7_21 [1] */
+                FN_VI0_CLK,     FN_CAN_CLK_A,
+                /* IP7_20_18 [3] */
+                FN_TCLK0,       FN_HSCK1_A,     FN_FMIN_A,      0,
+                FN_IRQ2_C,      FN_CTS1_C,      FN_SPEEDIN,     0,
+                /* IP7_17_15 [3] */
+                FN_VI1_VSYNC,   FN_HSPI_TX0,    FN_HCTS1_A,     FN_BPFCLK_A,
+                0,              FN_TX1_C,       0,              0,
+                /* IP7_14_12 [3] */
+                FN_VI1_HSYNC,   FN_HSPI_RX0_A,  FN_HRTS1_A,     FN_FMCLK_A,
+                0,              FN_RX1_C,       0,              0,
+                /* IP7_11_9 [3] */
+                FN_VI1_FIELD,   FN_HSPI_CS0_A,  FN_HRX1_A,      0,
+                FN_SCK1_C,      0,              0,              0,
+                /* IP7_8_6 [3] */
+                FN_VI1_CLKENB,  FN_HSPI_CLK0_A, FN_HTX1_A,      0,
+                FN_RTS1_C,      0,              0,              0,
+                /* IP7_5_4 [2] */
+                FN_SD0_WP,      0,              FN_RX5_A,       0,
+                /* IP7_3_2 [2] */
+                FN_SD0_CD,      0,              FN_TX5_A,       0,
+                /* IP7_1_0 [2] */
+                FN_SD0_DAT3,    0,              FN_IRQ1_B,      0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xfffc0040, 32,
+                             1, 1, 3, 3, 2, 3, 3, 2, 3, 2, 3, 3, 3) {
+                /* IP8_31 [1] */
+                0, 0,
+                /* IP8_30 [1] */
+                0, 0,
+                /* IP8_29_27 [3] */
+                FN_VI0_G3,      FN_SD2_CMD_B,   FN_VI1_DATA5,   FN_DU1_DR5,
+                0,              FN_HRX1_B,      0,              0,
+                /* IP8_26_24 [3] */
+                FN_VI0_G2,      FN_SD2_CLK_B,   FN_VI1_DATA4,   FN_DU1_DR4,
+                0,              FN_HTX1_B,      0,              0,
+                /* IP8_23_22 [2] */
+                FN_VI0_DATA7_VI0_G1,    FN_DU1_DB5,
+                FN_RTS1_A,              0,
+                /* IP8_21_19 [3] */
+                FN_VI0_DATA6_VI0_G0,    FN_DU1_DB4,
+                FN_CTS1_A,              FN_PWM5,
+                0,      0,      0,      0,
+                /* IP8_18_16 [3] */
+                FN_VI0_DATA5_VI0_B5,    FN_DU1_DB3,     FN_SCK1_A,      FN_PWM4,
+                0,                      FN_HSCK1_B,     0,              0,
+                /* IP8_15_14 [2] */
+                FN_VI0_DATA4_VI0_B4,    FN_DU1_DB2,     FN_RX1_A,       0,
+                /* IP8_13_11 [3] */
+                FN_VI0_DATA3_VI0_B3,    FN_DU1_DG5,     FN_TX1_A,       FN_TX0_C,
+                0,                       0,             0,              0,
+                /* IP8_10_9 [2] */
+                FN_VI0_DATA2_VI0_B2,    FN_DU1_DG4,     FN_RX0_C,       0,
+                /* IP8_8_6 [3] */
+                FN_VI0_DATA1_VI0_B1,    FN_DU1_DG3,     FN_IRQ3_B,      FN_TX3_D,
+                0,                       0,             0,              0,
+                /* IP8_5_3 [3] */
+                FN_VI0_DATA0_VI0_B0,    FN_DU1_DG2,     FN_IRQ2_B,      FN_RX3_D,
+                0,                       0,             0,              0,
+                /* IP8_2_0 [3] */
+                FN_VI0_VSYNC,           FN_SD2_WP_B,    FN_VI1_DATA3,   FN_DU1_DR3,
+                0,                      FN_HSPI_TX1_A,  FN_TX3_B,       0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xfffc0044, 32,
+                             1, 1, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+                /* IP9_31 [1] */
+                0, 0,
+                /* IP9_30 [1] */
+                0, 0,
+                /* IP9_29_27 [3] */
+                FN_VI1_DATA11_A,        FN_DU1_EXHSYNC_DU1_HSYNC,
+                FN_ETH_RXD1,            FN_FMIN_C,
+                0,                      FN_RX2_D,
+                FN_SCL2_C,              0,
+                /* IP9_26_24 [3] */
+                FN_VI1_DATA10_A,        FN_DU1_DOTCLKOUT,
+                FN_ETH_RXD0,            FN_BPFCLK_C,
+                0,                      FN_TX2_D,
+                FN_SDA2_C,              0,
+                /* IP9_23_21 [3] */
+                FN_VI0_R5_A,    0,              FN_ETH_RX_ER,   FN_FMCLK_C,
+                FN_IERX,        FN_RX2_C,       0,              0,
+                /* IP9_20_18 [3] */
+                FN_VI0_R4_A,    FN_ETH_TX_EN,   0,              0,
+                FN_IETX,        FN_TX2_C,       0,              0,
+                /* IP9_17_15 [3] */
+                FN_VI0_R3_A,    FN_ETH_CRS_DV,  0,              FN_IECLK,
+                FN_SCK2_C,      0,              0,              0,
+                /* IP9_14_12 [3] */
+                FN_VI0_R2_A,    FN_VI1_DATA9,   FN_DU1_DB7,     FN_ETH_TXD1,
+                0,              FN_PWM3,        0,              0,
+                /* IP9_11_9 [3] */
+                FN_VI0_R1_A,    FN_VI1_DATA8,   FN_DU1_DB6,     FN_ETH_TXD0,
+                0,              FN_PWM2,        FN_TCLK1,       0,
+                /* IP9_8_6 [3] */
+                FN_VI0_R0_A,    FN_VI1_CLK,     FN_ETH_REF_CLK, FN_DU1_DOTCLKIN,
+                0,              0,              0,              0,
+                /* IP9_5_3 [3] */
+                FN_VI0_G5,      FN_SD2_DAT1_B,  FN_VI1_DATA7,   FN_DU1_DR7,
+                0,              FN_HCTS1_B,     0,              0,
+                /* IP9_2_0 [3] */
+                FN_VI0_G4,      FN_SD2_DAT0_B,  FN_VI1_DATA6,   FN_DU1_DR6,
+                0,              FN_HRTS1_B,     0,              0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xfffc0048, 32,
+                             1, 1, 1, 1, 1, 1, 1, 3, 3, 3, 3, 4, 3, 3, 3) {
+
+                /* IP10_31 [1] */
+                0, 0,
+                /* IP10_30 [1] */
+                0, 0,
+                /* IP10_29 [1] */
+                0, 0,
+                /* IP10_28 [1] */
+                0, 0,
+                /* IP10_27 [1] */
+                0, 0,
+                /* IP10_26 [1] */
+                0, 0,
+                /* IP10_25 [1] */
+                0, 0,
+                /* IP10_24_22 [3] */
+                FN_SD2_WP_A,    FN_VI1_DATA15,  FN_EX_WAIT2_B,  FN_DACK0_B,
+                FN_HSPI_TX2_B,  FN_CAN_CLK_C,   0,              0,
+                /* IP10_21_19 [3] */
+                FN_SD2_CD_A,    FN_VI1_DATA14,  FN_EX_WAIT1_B,  FN_DREQ0_B,
+                FN_HSPI_RX2_B,  FN_REMOCON_A,   0,              0,
+                /* IP10_18_16 [3] */
+                FN_SD2_DAT3_A,  FN_VI1_DATA13,  FN_DACK2_B,     FN_ATAG1,
+                FN_HSPI_CS2_B,  FN_GPSIN_B,     0,              0,
+                /* IP10_15_13 [3] */
+                FN_SD2_DAT2_A,  FN_VI1_DATA12,  FN_DREQ2_B,     FN_ATADIR1,
+                FN_HSPI_CLK2_B, FN_GPSCLK_B,    0,              0,
+                /* IP10_12_9 [4] */
+                FN_SD2_DAT1_A,  FN_DU1_CDE,     FN_ATACS11,     FN_DACK1_B,
+                FN_ETH_MAGIC,   FN_CAN1_TX_A,   0,              FN_PWM6,
+                0, 0, 0, 0,
+                0, 0, 0, 0,
+                /* IP10_8_6 [3] */
+                FN_SD2_DAT0_A,  FN_DU1_DISP,    FN_ATACS01,     FN_DREQ1_B,
+                FN_ETH_LINK,    FN_CAN1_RX_A,   0,              0,
+                /* IP10_5_3 [3] */
+                FN_SD2_CMD_A,   FN_DU1_EXODDF_DU1_ODDF_DISP_CDE,
+                FN_ATAWR1,      FN_ETH_MDIO,
+                FN_SCL1_B,      0,
+                0,              0,
+                /* IP10_2_0 [3] */
+                FN_SD2_CLK_A,   FN_DU1_EXVSYNC_DU1_VSYNC,
+                FN_ATARD1,      FN_ETH_MDC,
+                FN_SDA1_B,      0,
+                0,              0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL0", 0xfffc0050, 32,
+                             1, 1, 2, 2, 3, 2, 2, 1, 1, 1, 1, 2,
+                             1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1) {
+
+                /* SEL 31  [1] */
+                0, 0,
+                /* SEL_30 (SCIF5) [1] */
+                FN_SEL_SCIF5_A,         FN_SEL_SCIF5_B,
+                /* SEL_29_28 (SCIF4) [2] */
+                FN_SEL_SCIF4_A,         FN_SEL_SCIF4_B,
+                FN_SEL_SCIF4_C,         0,
+                /* SEL_27_26 (SCIF3) [2] */
+                FN_SEL_SCIF3_A,         FN_SEL_SCIF3_B,
+                FN_SEL_SCIF3_C,         FN_SEL_SCIF3_D,
+                /* SEL_25_23 (SCIF2) [3] */
+                FN_SEL_SCIF2_A,         FN_SEL_SCIF2_B,
+                FN_SEL_SCIF2_C,         FN_SEL_SCIF2_D,
+                FN_SEL_SCIF2_E,         0,
+                0,                      0,
+                /* SEL_22_21 (SCIF1) [2] */
+                FN_SEL_SCIF1_A,         FN_SEL_SCIF1_B,
+                FN_SEL_SCIF1_C,         FN_SEL_SCIF1_D,
+                /* SEL_20_19 (SCIF0) [2] */
+                FN_SEL_SCIF0_A,         FN_SEL_SCIF0_B,
+                FN_SEL_SCIF0_C,         FN_SEL_SCIF0_D,
+                /* SEL_18 [1] */
+                0, 0,
+                /* SEL_17 (SSI2) [1] */
+                FN_SEL_SSI2_A,          FN_SEL_SSI2_B,
+                /* SEL_16 (SSI1) [1] */
+                FN_SEL_SSI1_A,          FN_SEL_SSI1_B,
+                /* SEL_15 (VI1) [1] */
+                FN_SEL_VI1_A,           FN_SEL_VI1_B,
+                /* SEL_14_13 (VI0) [2] */
+                FN_SEL_VI0_A,           FN_SEL_VI0_B,
+                FN_SEL_VI0_C,           FN_SEL_VI0_D,
+                /* SEL_12 [1] */
+                0, 0,
+                /* SEL_11 (SD2) [1] */
+                FN_SEL_SD2_A,           FN_SEL_SD2_B,
+                /* SEL_10 (SD1) [1] */
+                FN_SEL_SD1_A,           FN_SEL_SD1_B,
+                /* SEL_9 (IRQ3) [1] */
+                FN_SEL_IRQ3_A,          FN_SEL_IRQ3_B,
+                /* SEL_8_7 (IRQ2) [2] */
+                FN_SEL_IRQ2_A,          FN_SEL_IRQ2_B,
+                FN_SEL_IRQ2_C,          0,
+                /* SEL_6 (IRQ1) [1] */
+                FN_SEL_IRQ1_A,          FN_SEL_IRQ1_B,
+                /* SEL_5 [1] */
+                0, 0,
+                /* SEL_4 (DREQ2) [1] */
+                FN_SEL_DREQ2_A,         FN_SEL_DREQ2_B,
+                /* SEL_3 (DREQ1) [1] */
+                FN_SEL_DREQ1_A,         FN_SEL_DREQ1_B,
+                /* SEL_2 (DREQ0) [1] */
+                FN_SEL_DREQ0_A,         FN_SEL_DREQ0_B,
+                /* SEL_1 (WAIT2) [1] */
+                FN_SEL_WAIT2_A,         FN_SEL_WAIT2_B,
+                /* SEL_0 (WAIT1) [1] */
+                FN_SEL_WAIT1_A,         FN_SEL_WAIT1_B,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL1", 0xfffc0054, 32,
+                             1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1,
+                             1, 1, 1, 2, 2, 2, 1, 1, 1, 1, 2, 2, 1) {
+
+                /* SEL_31 [1] */
+                0, 0,
+                /* SEL_30 [1] */
+                0, 0,
+                /* SEL_29 [1] */
+                0, 0,
+                /* SEL_28 [1] */
+                0, 0,
+                /* SEL_27 (CAN1) [1] */
+                FN_SEL_CAN1_A,          FN_SEL_CAN1_B,
+                /* SEL_26 (CAN0) [1] */
+                FN_SEL_CAN0_A,          FN_SEL_CAN0_B,
+                /* SEL_25_24 (CANCLK) [2] */
+                FN_SEL_CANCLK_A,        FN_SEL_CANCLK_B,
+                FN_SEL_CANCLK_C,        FN_SEL_CANCLK_D,
+                /* SEL_23 (HSCIF1) [1] */
+                FN_SEL_HSCIF1_A,        FN_SEL_HSCIF1_B,
+                /* SEL_22 (HSCIF0) [1] */
+                FN_SEL_HSCIF0_A,        FN_SEL_HSCIF0_B,
+                /* SEL_21 [1] */
+                0, 0,
+                /* SEL_20 [1] */
+                0, 0,
+                /* SEL_19 [1] */
+                0, 0,
+                /* SEL_18 [1] */
+                0, 0,
+                /* SEL_17 [1] */
+                0, 0,
+                /* SEL_16 [1] */
+                0, 0,
+                /* SEL_15 [1] */
+                0, 0,
+                /* SEL_14_13 (REMOCON) [2] */
+                FN_SEL_REMOCON_A,       FN_SEL_REMOCON_B,
+                FN_SEL_REMOCON_C,       0,
+                /* SEL_12_11 (FM) [2] */
+                FN_SEL_FM_A,            FN_SEL_FM_B,
+                FN_SEL_FM_C,            FN_SEL_FM_D,
+                /* SEL_10_9 (GPS) [2] */
+                FN_SEL_GPS_A,           FN_SEL_GPS_B,
+                FN_SEL_GPS_C,           0,
+                /* SEL_8 (TSIF0) [1] */
+                FN_SEL_TSIF0_A,         FN_SEL_TSIF0_B,
+                /* SEL_7 (HSPI2) [1] */
+                FN_SEL_HSPI2_A,         FN_SEL_HSPI2_B,
+                /* SEL_6 (HSPI1) [1] */
+                FN_SEL_HSPI1_A,         FN_SEL_HSPI1_B,
+                /* SEL_5 (HSPI0) [1] */
+                FN_SEL_HSPI0_A,         FN_SEL_HSPI0_B,
+                /* SEL_4_3 (I2C3) [2] */
+                FN_SEL_I2C3_A,          FN_SEL_I2C3_B,
+                FN_SEL_I2C3_C,          0,
+                /* SEL_2_1 (I2C2) [2] */
+                FN_SEL_I2C2_A,          FN_SEL_I2C2_B,
+                FN_SEL_I2C2_C,          0,
+                /* SEL_0 (I2C1) [1] */
+                FN_SEL_I2C1_A,          FN_SEL_I2C1_B,
+                }
+        },
+        { },
+};
+
+const struct sh_pfc_soc_info r8a7778_pinmux_info = {
+        .name = "r8a7778_pfc",
+
+        .unlock_reg = 0xfffc0000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index 791a6719d8a9..8e22ca6c1044 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1,8 +1,9 @@
 /*
  * r8a7779 processor support - PFC hardware block
  *
- * Copyright (C) 2011  Renesas Solutions Corp.
+ * Copyright (C) 2011, 2013  Renesas Solutions Corp.
  * Copyright (C) 2011  Magnus Damm
+ * Copyright (C) 2013  Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -19,6 +20,7 @@
  */
 
 #include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
 
 #include "sh_pfc.h"
 
@@ -79,7 +81,7 @@
 #define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
 
 #define _GP_GPIO(bank, pin, _name, sfx)                                 \
-        [(bank * 32) + pin] = {                                         \
+        [RCAR_GP_PIN(bank, pin)] = {                                    \
                 .name = __stringify(_name),                             \
                 .enum_id = _name##_DATA,                                \
         }
@@ -1472,9 +1474,12 @@ static struct sh_pfc_pin pinmux_pins[] = {
 /* - DU0 -------------------------------------------------------------------- */
 static const unsigned int du0_rgb666_pins[] = {
         /* R[7:2], G[7:2], B[7:2] */
-        188, 187, 186, 185, 184, 183,
-        194, 193, 192, 191, 190, 189,
-        200, 199, 198, 197, 196, 195,
+        RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+        RCAR_GP_PIN(6, 2),  RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),
+        RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29),
+        RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),  RCAR_GP_PIN(6, 6),
+        RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),  RCAR_GP_PIN(6, 3),
 };
 static const unsigned int du0_rgb666_mux[] = {
         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1486,9 +1491,14 @@ static const unsigned int du0_rgb666_mux[] = {
 };
 static const unsigned int du0_rgb888_pins[] = {
         /* R[7:0], G[7:0], B[7:0] */
-        188, 187, 186, 185, 184, 183, 24, 23,
-        194, 193, 192, 191, 190, 189, 26, 25,
-        200, 199, 198, 197, 196, 195, 28, 27,
+        RCAR_GP_PIN(5, 28), RCAR_GP_PIN(5, 27), RCAR_GP_PIN(5, 26),
+        RCAR_GP_PIN(5, 25), RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 23),
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23), RCAR_GP_PIN(6, 2),
+        RCAR_GP_PIN(6, 1),  RCAR_GP_PIN(6, 0),  RCAR_GP_PIN(5, 31),
+        RCAR_GP_PIN(5, 30), RCAR_GP_PIN(5, 29), RCAR_GP_PIN(0, 26),
+        RCAR_GP_PIN(0, 25), RCAR_GP_PIN(6, 8),  RCAR_GP_PIN(6, 7),
+        RCAR_GP_PIN(6, 6),  RCAR_GP_PIN(6, 5),  RCAR_GP_PIN(6, 4),
+        RCAR_GP_PIN(6, 3),  RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 27),
 };
 static const unsigned int du0_rgb888_mux[] = {
         DU0_DR7_MARK, DU0_DR6_MARK, DU0_DR5_MARK, DU0_DR4_MARK,
@@ -1500,28 +1510,28 @@ static const unsigned int du0_rgb888_mux[] = {
 };
 static const unsigned int du0_clk_in_pins[] = {
         /* CLKIN */
-        29,
+        RCAR_GP_PIN(0, 29),
 };
 static const unsigned int du0_clk_in_mux[] = {
         DU0_DOTCLKIN_MARK,
 };
 static const unsigned int du0_clk_out_0_pins[] = {
         /* CLKOUT */
-        180,
+        RCAR_GP_PIN(5, 20),
 };
 static const unsigned int du0_clk_out_0_mux[] = {
         DU0_DOTCLKOUT0_MARK,
 };
 static const unsigned int du0_clk_out_1_pins[] = {
         /* CLKOUT */
-        30,
+        RCAR_GP_PIN(0, 30),
 };
 static const unsigned int du0_clk_out_1_mux[] = {
         DU0_DOTCLKOUT1_MARK,
 };
 static const unsigned int du0_sync_0_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        182, 181, 31,
+        RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_sync_0_mux[] = {
         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1529,7 +1539,7 @@ static const unsigned int du0_sync_0_mux[] = {
 };
 static const unsigned int du0_sync_1_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        182, 181, 32,
+        RCAR_GP_PIN(5, 22), RCAR_GP_PIN(5, 21), RCAR_GP_PIN(1, 0),
 };
 static const unsigned int du0_sync_1_mux[] = {
         DU0_EXHSYNC_DU0_HSYNC_MARK, DU0_EXVSYNC_DU0_VSYNC_MARK,
@@ -1537,14 +1547,14 @@ static const unsigned int du0_sync_1_mux[] = {
 };
 static const unsigned int du0_oddf_pins[] = {
         /* ODDF */
-        31,
+        RCAR_GP_PIN(0, 31),
 };
 static const unsigned int du0_oddf_mux[] = {
         DU0_EXODDF_DU0_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du0_cde_pins[] = {
         /* CDE */
-        33,
+        RCAR_GP_PIN(1, 1),
 };
 static const unsigned int du0_cde_mux[] = {
         DU0_CDE_MARK
@@ -1552,9 +1562,12 @@ static const unsigned int du0_cde_mux[] = {
 /* - DU1 -------------------------------------------------------------------- */
 static const unsigned int du1_rgb666_pins[] = {
         /* R[7:2], G[7:2], B[7:2] */
-        41, 40, 39, 38, 37, 36,
-        49, 48, 47, 46, 45, 44,
-        57, 56, 55, 54, 53, 52,
+        RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+        RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+        RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15),
+        RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12),
+        RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 23),
+        RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 20),
 };
 static const unsigned int du1_rgb666_mux[] = {
         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1566,9 +1579,14 @@ static const unsigned int du1_rgb666_mux[] = {
 };
 static const unsigned int du1_rgb888_pins[] = {
         /* R[7:0], G[7:0], B[7:0] */
-        41, 40, 39, 38, 37, 36, 35, 34,
-        49, 48, 47, 46, 45, 44, 43, 32,
-        57, 56, 55, 54, 53, 52, 51, 50,
+        RCAR_GP_PIN(1, 9),  RCAR_GP_PIN(1, 8),  RCAR_GP_PIN(1, 7),
+        RCAR_GP_PIN(1, 6),  RCAR_GP_PIN(1, 5),  RCAR_GP_PIN(1, 4),
+        RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 17),
+        RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 14),
+        RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 11),
+        RCAR_GP_PIN(1, 0),  RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 24),
+        RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 21),
+        RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int du1_rgb888_mux[] = {
         DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
@@ -1580,21 +1598,21 @@ static const unsigned int du1_rgb888_mux[] = {
 };
 static const unsigned int du1_clk_in_pins[] = {
         /* CLKIN */
-        58,
+        RCAR_GP_PIN(1, 26),
 };
 static const unsigned int du1_clk_in_mux[] = {
         DU1_DOTCLKIN_MARK,
 };
 static const unsigned int du1_clk_out_pins[] = {
         /* CLKOUT */
-        59,
+        RCAR_GP_PIN(1, 27),
 };
 static const unsigned int du1_clk_out_mux[] = {
         DU1_DOTCLKOUT_MARK,
 };
 static const unsigned int du1_sync_0_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        61, 60, 62,
+        RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_sync_0_mux[] = {
         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1602,7 +1620,7 @@ static const unsigned int du1_sync_0_mux[] = {
 };
 static const unsigned int du1_sync_1_pins[] = {
         /* VSYNC, HSYNC, DISP */
-        61, 60, 63,
+        RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 31),
 };
 static const unsigned int du1_sync_1_mux[] = {
         DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK,
@@ -1610,22 +1628,55 @@ static const unsigned int du1_sync_1_mux[] = {
 };
 static const unsigned int du1_oddf_pins[] = {
         /* ODDF */
-        62,
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int du1_oddf_mux[] = {
         DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK
 };
 static const unsigned int du1_cde_pins[] = {
         /* CDE */
-        64,
+        RCAR_GP_PIN(2, 0),
 };
 static const unsigned int du1_cde_mux[] = {
         DU1_CDE_MARK
 };
+/* - Ether ------------------------------------------------------------------ */
+static const unsigned int ether_rmii_pins[] = {
+        /*
+         * ETH_TXD0, ETH_TXD1, ETH_TX_EN,  ETH_REFCLK,
+         * ETH_RXD0, ETH_RXD1, ETH_CRS_DV, ETH_RX_ER,
+         * ETH_MDIO, ETH_MDC
+         */
+        RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 18),
+        RCAR_GP_PIN(2, 26),
+        RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 17),
+        RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 28),
+};
+static const unsigned int ether_rmii_mux[] = {
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK,  ETH_REFCLK_MARK,
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_CRS_DV_MARK, ETH_RX_ER_MARK,
+        ETH_MDIO_MARK, ETH_MDC_MARK,
+};
+static const unsigned int ether_link_pins[] = {
+        /* ETH_LINK */
+        RCAR_GP_PIN(2, 24),
+};
+static const unsigned int ether_link_mux[] = {
+        ETH_LINK_MARK,
+};
+static const unsigned int ether_magic_pins[] = {
+        /* ETH_MAGIC */
+        RCAR_GP_PIN(2, 25),
+};
+static const unsigned int ether_magic_mux[] = {
+        ETH_MAGIC_MARK,
+};
 /* - HSPI0 ------------------------------------------------------------------ */
 static const unsigned int hspi0_pins[] = {
         /* CLK, CS, RX, TX */
-        150, 151, 153, 152,
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 25),
+        RCAR_GP_PIN(4, 24),
 };
 static const unsigned int hspi0_mux[] = {
         HSPI_CLK0_MARK, HSPI_CS0_MARK, HSPI_RX0_MARK, HSPI_TX0_MARK,
@@ -1633,28 +1684,32 @@ static const unsigned int hspi0_mux[] = {
 /* - HSPI1 ------------------------------------------------------------------ */
 static const unsigned int hspi1_pins[] = {
         /* CLK, CS, RX, TX */
-        63, 58, 64, 62,
+        RCAR_GP_PIN(1, 31), RCAR_GP_PIN(1, 26), RCAR_GP_PIN(2, 0),
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int hspi1_mux[] = {
         HSPI_CLK1_MARK, HSPI_CS1_MARK, HSPI_RX1_MARK, HSPI_TX1_MARK,
 };
 static const unsigned int hspi1_b_pins[] = {
         /* CLK, CS, RX, TX */
-        90, 91, 93, 92,
+        RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 29),
+        RCAR_GP_PIN(2, 28),
 };
 static const unsigned int hspi1_b_mux[] = {
         HSPI_CLK1_B_MARK, HSPI_CS1_B_MARK, HSPI_RX1_B_MARK, HSPI_TX1_B_MARK,
 };
 static const unsigned int hspi1_c_pins[] = {
         /* CLK, CS, RX, TX */
-        141, 142, 144, 143,
+        RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 16),
+        RCAR_GP_PIN(4, 15),
 };
 static const unsigned int hspi1_c_mux[] = {
         HSPI_CLK1_C_MARK, HSPI_CS1_C_MARK, HSPI_RX1_C_MARK, HSPI_TX1_C_MARK,
 };
 static const unsigned int hspi1_d_pins[] = {
         /* CLK, CS, RX, TX */
-        101, 102, 104, 103,
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 8),
+        RCAR_GP_PIN(3, 7),
 };
 static const unsigned int hspi1_d_mux[] = {
         HSPI_CLK1_D_MARK, HSPI_CS1_D_MARK, HSPI_RX1_D_MARK, HSPI_TX1_D_MARK,
@@ -1662,14 +1717,16 @@ static const unsigned int hspi1_d_mux[] = {
 /* - HSPI2 ------------------------------------------------------------------ */
 static const unsigned int hspi2_pins[] = {
         /* CLK, CS, RX, TX */
-        9, 10, 11, 14,
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+        RCAR_GP_PIN(0, 14),
 };
 static const unsigned int hspi2_mux[] = {
         HSPI_CLK2_MARK, HSPI_CS2_MARK, HSPI_RX2_MARK, HSPI_TX2_MARK,
 };
 static const unsigned int hspi2_b_pins[] = {
         /* CLK, CS, RX, TX */
-        7, 13, 8, 6,
+        RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 13), RCAR_GP_PIN(0, 8),
+        RCAR_GP_PIN(0, 6),
 };
 static const unsigned int hspi2_b_mux[] = {
         HSPI_CLK2_B_MARK, HSPI_CS2_B_MARK, HSPI_RX2_B_MARK, HSPI_TX2_B_MARK,
@@ -1677,56 +1734,56 @@ static const unsigned int hspi2_b_mux[] = {
 /* - INTC ------------------------------------------------------------------- */
 static const unsigned int intc_irq0_pins[] = {
         /* IRQ */
-        78,
+        RCAR_GP_PIN(2, 14),
 };
 static const unsigned int intc_irq0_mux[] = {
         IRQ0_MARK,
 };
 static const unsigned int intc_irq0_b_pins[] = {
         /* IRQ */
-        141,
+        RCAR_GP_PIN(4, 13),
 };
 static const unsigned int intc_irq0_b_mux[] = {
         IRQ0_B_MARK,
 };
 static const unsigned int intc_irq1_pins[] = {
         /* IRQ */
-        79,
+        RCAR_GP_PIN(2, 15),
 };
 static const unsigned int intc_irq1_mux[] = {
         IRQ1_MARK,
 };
 static const unsigned int intc_irq1_b_pins[] = {
         /* IRQ */
-        142,
+        RCAR_GP_PIN(4, 14),
 };
 static const unsigned int intc_irq1_b_mux[] = {
         IRQ1_B_MARK,
 };
 static const unsigned int intc_irq2_pins[] = {
         /* IRQ */
-        88,
+        RCAR_GP_PIN(2, 24),
 };
 static const unsigned int intc_irq2_mux[] = {
         IRQ2_MARK,
 };
 static const unsigned int intc_irq2_b_pins[] = {
         /* IRQ */
-        143,
+        RCAR_GP_PIN(4, 15),
 };
 static const unsigned int intc_irq2_b_mux[] = {
         IRQ2_B_MARK,
 };
 static const unsigned int intc_irq3_pins[] = {
         /* IRQ */
-        89,
+        RCAR_GP_PIN(2, 25),
 };
 static const unsigned int intc_irq3_mux[] = {
         IRQ3_MARK,
 };
 static const unsigned int intc_irq3_b_pins[] = {
         /* IRQ */
-        144,
+        RCAR_GP_PIN(4, 16),
 };
 static const unsigned int intc_irq3_b_mux[] = {
         IRQ3_B_MARK,
@@ -1734,56 +1791,56 @@ static const unsigned int intc_irq3_b_mux[] = {
 /* - LSBC ------------------------------------------------------------------- */
 static const unsigned int lbsc_cs0_pins[] = {
         /* CS */
-        13,
+        RCAR_GP_PIN(0, 13),
 };
 static const unsigned int lbsc_cs0_mux[] = {
         CS0_MARK,
 };
 static const unsigned int lbsc_cs1_pins[] = {
         /* CS */
-        14,
+        RCAR_GP_PIN(0, 14),
 };
 static const unsigned int lbsc_cs1_mux[] = {
         CS1_A26_MARK,
 };
 static const unsigned int lbsc_ex_cs0_pins[] = {
         /* CS */
-        15,
+        RCAR_GP_PIN(0, 15),
 };
 static const unsigned int lbsc_ex_cs0_mux[] = {
         EX_CS0_MARK,
 };
 static const unsigned int lbsc_ex_cs1_pins[] = {
         /* CS */
-        16,
+        RCAR_GP_PIN(0, 16),
 };
 static const unsigned int lbsc_ex_cs1_mux[] = {
         EX_CS1_MARK,
 };
 static const unsigned int lbsc_ex_cs2_pins[] = {
         /* CS */
-        17,
+        RCAR_GP_PIN(0, 17),
 };
 static const unsigned int lbsc_ex_cs2_mux[] = {
         EX_CS2_MARK,
 };
 static const unsigned int lbsc_ex_cs3_pins[] = {
         /* CS */
-        18,
+        RCAR_GP_PIN(0, 18),
 };
 static const unsigned int lbsc_ex_cs3_mux[] = {
         EX_CS3_MARK,
 };
 static const unsigned int lbsc_ex_cs4_pins[] = {
         /* CS */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int lbsc_ex_cs4_mux[] = {
         EX_CS4_MARK,
 };
 static const unsigned int lbsc_ex_cs5_pins[] = {
         /* CS */
-        20,
+        RCAR_GP_PIN(0, 20),
 };
 static const unsigned int lbsc_ex_cs5_mux[] = {
         EX_CS5_MARK,
@@ -1791,21 +1848,24 @@ static const unsigned int lbsc_ex_cs5_mux[] = {
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_pins[] = {
         /* D[0] */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int mmc0_data1_mux[] = {
         MMC0_D0_MARK,
 };
 static const unsigned int mmc0_data4_pins[] = {
         /* D[0:3] */
-        19, 20, 21, 2,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),
 };
 static const unsigned int mmc0_data4_mux[] = {
         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
 };
 static const unsigned int mmc0_data8_pins[] = {
         /* D[0:7] */
-        19, 20, 21, 2, 10, 11, 15, 16,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),  RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 16),
 };
 static const unsigned int mmc0_data8_mux[] = {
         MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
@@ -1813,28 +1873,31 @@ static const unsigned int mmc0_data8_mux[] = {
 };
 static const unsigned int mmc0_ctrl_pins[] = {
         /* CMD, CLK */
-        18, 17,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int mmc0_ctrl_mux[] = {
         MMC0_CMD_MARK, MMC0_CLK_MARK,
 };
 static const unsigned int mmc1_data1_pins[] = {
         /* D[0] */
-        72,
+        RCAR_GP_PIN(2, 8),
 };
 static const unsigned int mmc1_data1_mux[] = {
         MMC1_D0_MARK,
 };
 static const unsigned int mmc1_data4_pins[] = {
         /* D[0:3] */
-        72, 73, 74, 75,
+        RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9), RCAR_GP_PIN(2, 10),
+        RCAR_GP_PIN(2, 11),
 };
 static const unsigned int mmc1_data4_mux[] = {
         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
 };
 static const unsigned int mmc1_data8_pins[] = {
         /* D[0:7] */
-        72, 73, 74, 75, 76, 77, 80, 81,
+        RCAR_GP_PIN(2, 8),  RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10),
+        RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+        RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
 };
 static const unsigned int mmc1_data8_mux[] = {
         MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
@@ -1842,7 +1905,7 @@ static const unsigned int mmc1_data8_mux[] = {
 };
 static const unsigned int mmc1_ctrl_pins[] = {
         /* CMD, CLK */
-        68, 65,
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 1),
 };
 static const unsigned int mmc1_ctrl_mux[] = {
         MMC1_CMD_MARK, MMC1_CLK_MARK,
@@ -1850,84 +1913,84 @@ static const unsigned int mmc1_ctrl_mux[] = {
 /* - SCIF0 ------------------------------------------------------------------ */
 static const unsigned int scif0_data_pins[] = {
         /* RXD, TXD */
-        153, 152,
+        RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
 };
 static const unsigned int scif0_data_mux[] = {
         RX0_MARK, TX0_MARK,
 };
 static const unsigned int scif0_clk_pins[] = {
         /* SCK */
-        156,
+        RCAR_GP_PIN(4, 28),
 };
 static const unsigned int scif0_clk_mux[] = {
         SCK0_MARK,
 };
 static const unsigned int scif0_ctrl_pins[] = {
         /* RTS, CTS */
-        151, 150,
+        RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 22),
 };
 static const unsigned int scif0_ctrl_mux[] = {
         RTS0_TANS_MARK, CTS0_MARK,
 };
 static const unsigned int scif0_data_b_pins[] = {
         /* RXD, TXD */
-        20, 19,
+        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif0_data_b_mux[] = {
         RX0_B_MARK, TX0_B_MARK,
 };
 static const unsigned int scif0_clk_b_pins[] = {
         /* SCK */
-        33,
+        RCAR_GP_PIN(1, 1),
 };
 static const unsigned int scif0_clk_b_mux[] = {
         SCK0_B_MARK,
 };
 static const unsigned int scif0_ctrl_b_pins[] = {
         /* RTS, CTS */
-        18, 11,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif0_ctrl_b_mux[] = {
         RTS0_B_TANS_B_MARK, CTS0_B_MARK,
 };
 static const unsigned int scif0_data_c_pins[] = {
         /* RXD, TXD */
-        146, 147,
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 19),
 };
 static const unsigned int scif0_data_c_mux[] = {
         RX0_C_MARK, TX0_C_MARK,
 };
 static const unsigned int scif0_clk_c_pins[] = {
         /* SCK */
-        145,
+        RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif0_clk_c_mux[] = {
         SCK0_C_MARK,
 };
 static const unsigned int scif0_ctrl_c_pins[] = {
         /* RTS, CTS */
-        149, 148,
+        RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif0_ctrl_c_mux[] = {
         RTS0_C_TANS_C_MARK, CTS0_C_MARK,
 };
 static const unsigned int scif0_data_d_pins[] = {
         /* RXD, TXD */
-        43, 42,
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif0_data_d_mux[] = {
         RX0_D_MARK, TX0_D_MARK,
 };
 static const unsigned int scif0_clk_d_pins[] = {
         /* SCK */
-        50,
+        RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif0_clk_d_mux[] = {
         SCK0_D_MARK,
 };
 static const unsigned int scif0_ctrl_d_pins[] = {
         /* RTS, CTS */
-        51, 35,
+        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 3),
 };
 static const unsigned int scif0_ctrl_d_mux[] = {
         RTS0_D_TANS_D_MARK, CTS0_D_MARK,
@@ -1935,63 +1998,63 @@ static const unsigned int scif0_ctrl_d_mux[] = {
 /* - SCIF1 ------------------------------------------------------------------ */
 static const unsigned int scif1_data_pins[] = {
         /* RXD, TXD */
-        149, 148,
+        RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 20),
 };
 static const unsigned int scif1_data_mux[] = {
         RX1_MARK, TX1_MARK,
 };
 static const unsigned int scif1_clk_pins[] = {
         /* SCK */
-        145,
+        RCAR_GP_PIN(4, 17),
 };
 static const unsigned int scif1_clk_mux[] = {
         SCK1_MARK,
 };
 static const unsigned int scif1_ctrl_pins[] = {
         /* RTS, CTS */
-        147, 146,
+        RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 18),
 };
 static const unsigned int scif1_ctrl_mux[] = {
         RTS1_TANS_MARK, CTS1_MARK,
 };
 static const unsigned int scif1_data_b_pins[] = {
         /* RXD, TXD */
-        117, 114,
+        RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 18),
 };
 static const unsigned int scif1_data_b_mux[] = {
         RX1_B_MARK, TX1_B_MARK,
 };
 static const unsigned int scif1_clk_b_pins[] = {
         /* SCK */
-        113,
+        RCAR_GP_PIN(3, 17),
 };
 static const unsigned int scif1_clk_b_mux[] = {
         SCK1_B_MARK,
 };
 static const unsigned int scif1_ctrl_b_pins[] = {
         /* RTS, CTS */
-        115, 116,
+        RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20),
 };
 static const unsigned int scif1_ctrl_b_mux[] = {
         RTS1_B_TANS_B_MARK, CTS1_B_MARK,
 };
 static const unsigned int scif1_data_c_pins[] = {
         /* RXD, TXD */
-        67, 66,
+        RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 2),
 };
 static const unsigned int scif1_data_c_mux[] = {
         RX1_C_MARK, TX1_C_MARK,
 };
 static const unsigned int scif1_clk_c_pins[] = {
         /* SCK */
-        86,
+        RCAR_GP_PIN(2, 22),
 };
 static const unsigned int scif1_clk_c_mux[] = {
         SCK1_C_MARK,
 };
 static const unsigned int scif1_ctrl_c_pins[] = {
         /* RTS, CTS */
-        69, 68,
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif1_ctrl_c_mux[] = {
         RTS1_C_TANS_C_MARK, CTS1_C_MARK,
@@ -1999,63 +2062,63 @@ static const unsigned int scif1_ctrl_c_mux[] = {
 /* - SCIF2 ------------------------------------------------------------------ */
 static const unsigned int scif2_data_pins[] = {
         /* RXD, TXD */
-        106, 105,
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 9),
 };
 static const unsigned int scif2_data_mux[] = {
         RX2_MARK, TX2_MARK,
 };
 static const unsigned int scif2_clk_pins[] = {
         /* SCK */
-        107,
+        RCAR_GP_PIN(3, 11),
 };
 static const unsigned int scif2_clk_mux[] = {
         SCK2_MARK,
 };
 static const unsigned int scif2_data_b_pins[] = {
         /* RXD, TXD */
-        120, 119,
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 23),
 };
 static const unsigned int scif2_data_b_mux[] = {
         RX2_B_MARK, TX2_B_MARK,
 };
 static const unsigned int scif2_clk_b_pins[] = {
         /* SCK */
-        118,
+        RCAR_GP_PIN(3, 22),
 };
 static const unsigned int scif2_clk_b_mux[] = {
         SCK2_B_MARK,
 };
 static const unsigned int scif2_data_c_pins[] = {
         /* RXD, TXD */
-        33, 31,
+        RCAR_GP_PIN(1, 1), RCAR_GP_PIN(0, 31),
 };
 static const unsigned int scif2_data_c_mux[] = {
         RX2_C_MARK, TX2_C_MARK,
 };
 static const unsigned int scif2_clk_c_pins[] = {
         /* SCK */
-        32,
+        RCAR_GP_PIN(1, 0),
 };
 static const unsigned int scif2_clk_c_mux[] = {
         SCK2_C_MARK,
 };
 static const unsigned int scif2_data_d_pins[] = {
         /* RXD, TXD */
-        64, 62,
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif2_data_d_mux[] = {
         RX2_D_MARK, TX2_D_MARK,
 };
 static const unsigned int scif2_clk_d_pins[] = {
         /* SCK */
-        63,
+        RCAR_GP_PIN(1, 31),
 };
 static const unsigned int scif2_clk_d_mux[] = {
         SCK2_D_MARK,
 };
 static const unsigned int scif2_data_e_pins[] = {
         /* RXD, TXD */
-        20, 19,
+        RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif2_data_e_mux[] = {
         RX2_E_MARK, TX2_E_MARK,
@@ -2063,14 +2126,14 @@ static const unsigned int scif2_data_e_mux[] = {
 /* - SCIF3 ------------------------------------------------------------------ */
 static const unsigned int scif3_data_pins[] = {
         /* RXD, TXD */
-        137, 136,
+        RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 8),
 };
 static const unsigned int scif3_data_mux[] = {
         RX3_IRDA_RX_MARK, TX3_IRDA_TX_MARK,
 };
 static const unsigned int scif3_clk_pins[] = {
         /* SCK */
-        135,
+        RCAR_GP_PIN(4, 7),
 };
 static const unsigned int scif3_clk_mux[] = {
         SCK3_MARK,
@@ -2078,35 +2141,35 @@ static const unsigned int scif3_clk_mux[] = {
 
 static const unsigned int scif3_data_b_pins[] = {
         /* RXD, TXD */
-        64, 62,
+        RCAR_GP_PIN(2, 0), RCAR_GP_PIN(1, 30),
 };
 static const unsigned int scif3_data_b_mux[] = {
         RX3_B_IRDA_RX_B_MARK, TX3_B_IRDA_TX_B_MARK,
 };
 static const unsigned int scif3_data_c_pins[] = {
         /* RXD, TXD */
-        15, 12,
+        RCAR_GP_PIN(0, 15), RCAR_GP_PIN(0, 12),
 };
 static const unsigned int scif3_data_c_mux[] = {
         RX3_C_IRDA_RX_C_MARK, TX3C_IRDA_TX_C_MARK,
 };
 static const unsigned int scif3_data_d_pins[] = {
         /* RXD, TXD */
-        30, 29,
+        RCAR_GP_PIN(0, 30), RCAR_GP_PIN(0, 29),
 };
 static const unsigned int scif3_data_d_mux[] = {
         RX3_D_IRDA_RX_D_MARK, TX3_D_IRDA_TX_D_MARK,
 };
 static const unsigned int scif3_data_e_pins[] = {
         /* RXD, TXD */
-        35, 34,
+        RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int scif3_data_e_mux[] = {
         RX3_E_IRDA_RX_E_MARK, TX3_E_IRDA_TX_E_MARK,
 };
 static const unsigned int scif3_clk_e_pins[] = {
         /* SCK */
-        42,
+        RCAR_GP_PIN(1, 10),
 };
 static const unsigned int scif3_clk_e_mux[] = {
         SCK3_E_MARK,
@@ -2114,42 +2177,42 @@ static const unsigned int scif3_clk_e_mux[] = {
 /* - SCIF4 ------------------------------------------------------------------ */
 static const unsigned int scif4_data_pins[] = {
         /* RXD, TXD */
-        123, 122,
+        RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 26),
 };
 static const unsigned int scif4_data_mux[] = {
         RX4_MARK, TX4_MARK,
 };
 static const unsigned int scif4_clk_pins[] = {
         /* SCK */
-        121,
+        RCAR_GP_PIN(3, 25),
 };
 static const unsigned int scif4_clk_mux[] = {
         SCK4_MARK,
 };
 static const unsigned int scif4_data_b_pins[] = {
         /* RXD, TXD */
-        111, 110,
+        RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
 };
 static const unsigned int scif4_data_b_mux[] = {
         RX4_B_MARK, TX4_B_MARK,
 };
 static const unsigned int scif4_clk_b_pins[] = {
         /* SCK */
-        112,
+        RCAR_GP_PIN(3, 16),
 };
 static const unsigned int scif4_clk_b_mux[] = {
         SCK4_B_MARK,
 };
 static const unsigned int scif4_data_c_pins[] = {
         /* RXD, TXD */
-        22, 21,
+        RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 21),
 };
 static const unsigned int scif4_data_c_mux[] = {
         RX4_C_MARK, TX4_C_MARK,
 };
 static const unsigned int scif4_data_d_pins[] = {
         /* RXD, TXD */
-        69, 68,
+        RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 4),
 };
 static const unsigned int scif4_data_d_mux[] = {
         RX4_D_MARK, TX4_D_MARK,
@@ -2157,56 +2220,56 @@ static const unsigned int scif4_data_d_mux[] = {
 /* - SCIF5 ------------------------------------------------------------------ */
 static const unsigned int scif5_data_pins[] = {
         /* RXD, TXD */
-        51, 50,
+        RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 18),
 };
 static const unsigned int scif5_data_mux[] = {
         RX5_MARK, TX5_MARK,
 };
 static const unsigned int scif5_clk_pins[] = {
         /* SCK */
-        43,
+        RCAR_GP_PIN(1, 11),
 };
 static const unsigned int scif5_clk_mux[] = {
         SCK5_MARK,
 };
 static const unsigned int scif5_data_b_pins[] = {
         /* RXD, TXD */
-        18, 11,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 11),
 };
 static const unsigned int scif5_data_b_mux[] = {
         RX5_B_MARK, TX5_B_MARK,
 };
 static const unsigned int scif5_clk_b_pins[] = {
         /* SCK */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int scif5_clk_b_mux[] = {
         SCK5_B_MARK,
 };
 static const unsigned int scif5_data_c_pins[] = {
         /* RXD, TXD */
-        24, 23,
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 23),
 };
 static const unsigned int scif5_data_c_mux[] = {
         RX5_C_MARK, TX5_C_MARK,
 };
 static const unsigned int scif5_clk_c_pins[] = {
         /* SCK */
-        28,
+        RCAR_GP_PIN(0, 28),
 };
 static const unsigned int scif5_clk_c_mux[] = {
         SCK5_C_MARK,
 };
 static const unsigned int scif5_data_d_pins[] = {
         /* RXD, TXD */
-        8, 6,
+        RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 6),
 };
 static const unsigned int scif5_data_d_mux[] = {
         RX5_D_MARK, TX5_D_MARK,
 };
 static const unsigned int scif5_clk_d_pins[] = {
         /* SCK */
-        7,
+        RCAR_GP_PIN(0, 7),
 };
 static const unsigned int scif5_clk_d_mux[] = {
         SCK5_D_MARK,
@@ -2214,35 +2277,36 @@ static const unsigned int scif5_clk_d_mux[] = {
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
-        117,
+        RCAR_GP_PIN(3, 21),
 };
 static const unsigned int sdhi0_data1_mux[] = {
         SD0_DAT0_MARK,
 };
 static const unsigned int sdhi0_data4_pins[] = {
         /* D[0:3] */
-        117, 118, 119, 120,
+        RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+        RCAR_GP_PIN(3, 24),
 };
 static const unsigned int sdhi0_data4_mux[] = {
         SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
 };
 static const unsigned int sdhi0_ctrl_pins[] = {
         /* CMD, CLK */
-        114, 113,
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 17),
 };
 static const unsigned int sdhi0_ctrl_mux[] = {
         SD0_CMD_MARK, SD0_CLK_MARK,
 };
 static const unsigned int sdhi0_cd_pins[] = {
         /* CD */
-        115,
+        RCAR_GP_PIN(3, 19),
 };
 static const unsigned int sdhi0_cd_mux[] = {
         SD0_CD_MARK,
 };
 static const unsigned int sdhi0_wp_pins[] = {
         /* WP */
-        116,
+        RCAR_GP_PIN(3, 20),
 };
 static const unsigned int sdhi0_wp_mux[] = {
         SD0_WP_MARK,
@@ -2250,35 +2314,36 @@ static const unsigned int sdhi0_wp_mux[] = {
 /* - SDHI1 ------------------------------------------------------------------ */
 static const unsigned int sdhi1_data1_pins[] = {
         /* D0 */
-        19,
+        RCAR_GP_PIN(0, 19),
 };
 static const unsigned int sdhi1_data1_mux[] = {
         SD1_DAT0_MARK,
 };
 static const unsigned int sdhi1_data4_pins[] = {
         /* D[0:3] */
-        19, 20, 21, 2,
+        RCAR_GP_PIN(0, 19), RCAR_GP_PIN(0, 20), RCAR_GP_PIN(0, 21),
+        RCAR_GP_PIN(0, 2),
 };
 static const unsigned int sdhi1_data4_mux[] = {
         SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
 };
 static const unsigned int sdhi1_ctrl_pins[] = {
         /* CMD, CLK */
-        18, 17,
+        RCAR_GP_PIN(0, 18), RCAR_GP_PIN(0, 17),
 };
 static const unsigned int sdhi1_ctrl_mux[] = {
         SD1_CMD_MARK, SD1_CLK_MARK,
 };
 static const unsigned int sdhi1_cd_pins[] = {
         /* CD */
-        10,
+        RCAR_GP_PIN(0, 10),
 };
 static const unsigned int sdhi1_cd_mux[] = {
         SD1_CD_MARK,
 };
 static const unsigned int sdhi1_wp_pins[] = {
         /* WP */
-        11,
+        RCAR_GP_PIN(0, 11),
 };
 static const unsigned int sdhi1_wp_mux[] = {
         SD1_WP_MARK,
@@ -2286,35 +2351,36 @@ static const unsigned int sdhi1_wp_mux[] = {
 /* - SDHI2 ------------------------------------------------------------------ */
 static const unsigned int sdhi2_data1_pins[] = {
         /* D0 */
-        97,
+        RCAR_GP_PIN(3, 1),
 };
 static const unsigned int sdhi2_data1_mux[] = {
         SD2_DAT0_MARK,
 };
 static const unsigned int sdhi2_data4_pins[] = {
         /* D[0:3] */
-        97, 98, 99, 100,
+        RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4),
 };
 static const unsigned int sdhi2_data4_mux[] = {
         SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
 };
 static const unsigned int sdhi2_ctrl_pins[] = {
         /* CMD, CLK */
-        102, 101,
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
 };
 static const unsigned int sdhi2_ctrl_mux[] = {
         SD2_CMD_MARK, SD2_CLK_MARK,
 };
 static const unsigned int sdhi2_cd_pins[] = {
         /* CD */
-        103,
+        RCAR_GP_PIN(3, 7),
 };
 static const unsigned int sdhi2_cd_mux[] = {
         SD2_CD_MARK,
 };
 static const unsigned int sdhi2_wp_pins[] = {
         /* WP */
-        104,
+        RCAR_GP_PIN(3, 8),
 };
 static const unsigned int sdhi2_wp_mux[] = {
         SD2_WP_MARK,
@@ -2322,62 +2388,188 @@ static const unsigned int sdhi2_wp_mux[] = {
 /* - SDHI3 ------------------------------------------------------------------ */
 static const unsigned int sdhi3_data1_pins[] = {
         /* D0 */
-        50,
+        RCAR_GP_PIN(1, 18),
 };
 static const unsigned int sdhi3_data1_mux[] = {
         SD3_DAT0_MARK,
 };
 static const unsigned int sdhi3_data4_pins[] = {
         /* D[0:3] */
-        50, 51, 52, 53,
+        RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19), RCAR_GP_PIN(1, 20),
+        RCAR_GP_PIN(1, 21),
 };
 static const unsigned int sdhi3_data4_mux[] = {
         SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
 };
 static const unsigned int sdhi3_ctrl_pins[] = {
         /* CMD, CLK */
-        35, 34,
+        RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 2),
 };
 static const unsigned int sdhi3_ctrl_mux[] = {
         SD3_CMD_MARK, SD3_CLK_MARK,
 };
 static const unsigned int sdhi3_cd_pins[] = {
         /* CD */
-        62,
+        RCAR_GP_PIN(1, 30),
 };
 static const unsigned int sdhi3_cd_mux[] = {
         SD3_CD_MARK,
 };
 static const unsigned int sdhi3_wp_pins[] = {
         /* WP */
-        64,
+        RCAR_GP_PIN(2, 0),
 };
 static const unsigned int sdhi3_wp_mux[] = {
         SD3_WP_MARK,
 };
 /* - USB0 ------------------------------------------------------------------- */
 static const unsigned int usb0_pins[] = {
-        /* OVC */
-        150, 154,
+        /* PENC */
+        RCAR_GP_PIN(4, 26),
 };
 static const unsigned int usb0_mux[] = {
-        USB_OVC0_MARK, USB_PENC0_MARK,
+        USB_PENC0_MARK,
+};
+static const unsigned int usb0_ovc_pins[] = {
+        /* USB_OVC */
+        RCAR_GP_PIN(4, 22),
+};
+static const unsigned int usb0_ovc_mux[] = {
+        USB_OVC0_MARK,
 };
 /* - USB1 ------------------------------------------------------------------- */
 static const unsigned int usb1_pins[] = {
-        /* OVC */
-        152, 155,
+        /* PENC */
+        RCAR_GP_PIN(4, 27),
 };
 static const unsigned int usb1_mux[] = {
-        USB_OVC1_MARK, USB_PENC1_MARK,
+        USB_PENC1_MARK,
+};
+static const unsigned int usb1_ovc_pins[] = {
+        /* USB_OVC */
+        RCAR_GP_PIN(4, 24),
+};
+static const unsigned int usb1_ovc_mux[] = {
+        USB_OVC1_MARK,
 };
 /* - USB2 ------------------------------------------------------------------- */
 static const unsigned int usb2_pins[] = {
-        /* OVC, PENC */
-        125, 156,
+        /* PENC */
+        RCAR_GP_PIN(4, 28),
 };
 static const unsigned int usb2_mux[] = {
-        USB_OVC2_MARK, USB_PENC2_MARK,
+        USB_PENC2_MARK,
+};
+static const unsigned int usb2_ovc_pins[] = {
+        /* USB_OVC */
+        RCAR_GP_PIN(3, 29),
+};
+static const unsigned int usb2_ovc_mux[] = {
+        USB_OVC2_MARK,
+};
+/* - VIN0 ------------------------------------------------------------------- */
+static const unsigned int vin0_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(2, 6),  RCAR_GP_PIN(2, 7),  RCAR_GP_PIN(2, 8),
+        RCAR_GP_PIN(2, 9),  RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
+        RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int vin0_data8_mux[] = {
+        VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK,
+        VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
+        VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
+};
+static const unsigned int vin0_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 1),
+};
+static const unsigned int vin0_clk_mux[] = {
+        VI0_CLK_MARK,
+};
+static const unsigned int vin0_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
+};
+static const unsigned int vin0_sync_mux[] = {
+        VI0_HSYNC_MARK, VI0_VSYNC_MARK,
+};
+/* - VIN1 ------------------------------------------------------------------- */
+static const unsigned int vin1_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+        RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 6),
+        RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 8),
+};
+static const unsigned int vin1_data8_mux[] = {
+        VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK,
+        VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
+        VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
+};
+static const unsigned int vin1_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 30),
+};
+static const unsigned int vin1_clk_mux[] = {
+        VI1_CLK_MARK,
+};
+static const unsigned int vin1_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0),
+};
+static const unsigned int vin1_sync_mux[] = {
+        VI1_HSYNC_MARK, VI1_VSYNC_MARK,
+};
+/* - VIN2 ------------------------------------------------------------------- */
+static const unsigned int vin2_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(1, 2),  RCAR_GP_PIN(1, 3),  RCAR_GP_PIN(1, 10),
+        RCAR_GP_PIN(1, 11), RCAR_GP_PIN(1, 18), RCAR_GP_PIN(1, 19),
+        RCAR_GP_PIN(1, 31), RCAR_GP_PIN(2, 0),
+};
+static const unsigned int vin2_data8_mux[] = {
+        VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK, VI2_DATA2_VI2_B2_MARK,
+        VI2_DATA3_VI2_B3_MARK, VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
+        VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
+};
+static const unsigned int vin2_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(1, 30),
+};
+static const unsigned int vin2_clk_mux[] = {
+        VI2_CLK_MARK,
+};
+static const unsigned int vin2_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin2_sync_mux[] = {
+        VI2_HSYNC_MARK, VI2_VSYNC_MARK,
+};
+/* - VIN3 ------------------------------------------------------------------- */
+static const unsigned int vin3_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 9),  RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+        RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+        RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 16),
+};
+static const unsigned int vin3_data8_mux[] = {
+        VI3_DATA0_MARK, VI3_DATA1_MARK, VI3_DATA2_MARK,
+        VI3_DATA3_MARK, VI3_DATA4_MARK, VI3_DATA5_MARK,
+        VI3_DATA6_MARK, VI3_DATA7_MARK,
+};
+static const unsigned int vin3_clk_pins[] = {
+        /* CLK */
+        RCAR_GP_PIN(2, 31),
+};
+static const unsigned int vin3_clk_mux[] = {
+        VI3_CLK_MARK,
+};
+static const unsigned int vin3_sync_pins[] = {
+        /* HSYNC, VSYNC */
+        RCAR_GP_PIN(1, 28), RCAR_GP_PIN(1, 29),
+};
+static const unsigned int vin3_sync_mux[] = {
+        VI3_HSYNC_MARK, VI3_VSYNC_MARK,
 };
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
@@ -2398,6 +2590,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(du1_sync_1),
         SH_PFC_PIN_GROUP(du1_oddf),
         SH_PFC_PIN_GROUP(du1_cde),
+        SH_PFC_PIN_GROUP(ether_rmii),
+        SH_PFC_PIN_GROUP(ether_link),
+        SH_PFC_PIN_GROUP(ether_magic),
         SH_PFC_PIN_GROUP(hspi0),
         SH_PFC_PIN_GROUP(hspi1),
         SH_PFC_PIN_GROUP(hspi1_b),
@@ -2501,8 +2696,23 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi3_cd),
         SH_PFC_PIN_GROUP(sdhi3_wp),
         SH_PFC_PIN_GROUP(usb0),
+        SH_PFC_PIN_GROUP(usb0_ovc),
         SH_PFC_PIN_GROUP(usb1),
+        SH_PFC_PIN_GROUP(usb1_ovc),
         SH_PFC_PIN_GROUP(usb2),
+        SH_PFC_PIN_GROUP(usb2_ovc),
+        SH_PFC_PIN_GROUP(vin0_data8),
+        SH_PFC_PIN_GROUP(vin0_clk),
+        SH_PFC_PIN_GROUP(vin0_sync),
+        SH_PFC_PIN_GROUP(vin1_data8),
+        SH_PFC_PIN_GROUP(vin1_clk),
+        SH_PFC_PIN_GROUP(vin1_sync),
+        SH_PFC_PIN_GROUP(vin2_data8),
+        SH_PFC_PIN_GROUP(vin2_clk),
+        SH_PFC_PIN_GROUP(vin2_sync),
+        SH_PFC_PIN_GROUP(vin3_data8),
+        SH_PFC_PIN_GROUP(vin3_clk),
+        SH_PFC_PIN_GROUP(vin3_sync),
 };
 
 static const char * const du0_groups[] = {
@@ -2528,6 +2738,12 @@ static const char * const du1_groups[] = {
         "du1_cde",
 };
 
+static const char * const ether_groups[] = {
+        "ether_rmii",
+        "ether_link",
+        "ether_magic",
+};
+
 static const char * const hspi0_groups[] = {
         "hspi0",
 };
@@ -2683,19 +2899,47 @@ static const char * const sdhi3_groups[] = {
 
 static const char * const usb0_groups[] = {
         "usb0",
+        "usb0_ovc",
 };
 
 static const char * const usb1_groups[] = {
         "usb1",
+        "usb1_ovc",
 };
 
 static const char * const usb2_groups[] = {
         "usb2",
+        "usb2_ovc",
+};
+
+static const char * const vin0_groups[] = {
+        "vin0_data8",
+        "vin0_clk",
+        "vin0_sync",
+};
+
+static const char * const vin1_groups[] = {
+        "vin1_data8",
+        "vin1_clk",
+        "vin1_sync",
+};
+
+static const char * const vin2_groups[] = {
+        "vin2_data8",
+        "vin2_clk",
+        "vin2_sync",
+};
+
+static const char * const vin3_groups[] = {
+        "vin3_data8",
+        "vin3_clk",
+        "vin3_sync",
 };
 
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(du0),
         SH_PFC_FUNCTION(du1),
+        SH_PFC_FUNCTION(ether),
         SH_PFC_FUNCTION(hspi0),
         SH_PFC_FUNCTION(hspi1),
         SH_PFC_FUNCTION(hspi2),
@@ -2716,6 +2960,10 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(usb0),
         SH_PFC_FUNCTION(usb1),
         SH_PFC_FUNCTION(usb2),
+        SH_PFC_FUNCTION(vin0),
+        SH_PFC_FUNCTION(vin1),
+        SH_PFC_FUNCTION(vin2),
+        SH_PFC_FUNCTION(vin3),
 };
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
@@ -3520,7 +3768,7 @@ static const struct pinmux_cfg_reg pinmux_config_regs[] = {
             /* SEL_SCIF [2] */
             FN_SEL_SCIF_0, FN_SEL_SCIF_1, FN_SEL_SCIF_2, FN_SEL_SCIF_3,
             /* SEL_CANCLK [2] */
-            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2,
+            FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, 0,
             /* SEL_CAN0 [1] */
             FN_SEL_CAN0_0, FN_SEL_CAN0_1,
             /* SEL_HSCIF1 [1] */
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
new file mode 100644
index 000000000000..85d77a417c0e
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -0,0 +1,3835 @@
+/*
+ * R8A7790 processor support
+ *
+ * Copyright (C) 2013  Renesas Electronics Corporation
+ * Copyright (C) 2013  Magnus Damm
+ * Copyright (C) 2012  Renesas Solutions Corp.
+ * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of the
+ * License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <linux/kernel.h>
+#include <linux/platform_data/gpio-rcar.h>
+
+#include "core.h"
+#include "sh_pfc.h"
+
+#define PORT_GP_1(bank, pin, fn, sfx) fn(bank, pin, GP_##bank##_##pin, sfx)
+
+#define PORT_GP_32(bank, fn, sfx)                                       \
+        PORT_GP_1(bank, 0,  fn, sfx), PORT_GP_1(bank, 1,  fn, sfx),     \
+        PORT_GP_1(bank, 2,  fn, sfx), PORT_GP_1(bank, 3,  fn, sfx),     \
+        PORT_GP_1(bank, 4,  fn, sfx), PORT_GP_1(bank, 5,  fn, sfx),     \
+        PORT_GP_1(bank, 6,  fn, sfx), PORT_GP_1(bank, 7,  fn, sfx),     \
+        PORT_GP_1(bank, 8,  fn, sfx), PORT_GP_1(bank, 9,  fn, sfx),     \
+        PORT_GP_1(bank, 10, fn, sfx), PORT_GP_1(bank, 11, fn, sfx),     \
+        PORT_GP_1(bank, 12, fn, sfx), PORT_GP_1(bank, 13, fn, sfx),     \
+        PORT_GP_1(bank, 14, fn, sfx), PORT_GP_1(bank, 15, fn, sfx),     \
+        PORT_GP_1(bank, 16, fn, sfx), PORT_GP_1(bank, 17, fn, sfx),     \
+        PORT_GP_1(bank, 18, fn, sfx), PORT_GP_1(bank, 19, fn, sfx),     \
+        PORT_GP_1(bank, 20, fn, sfx), PORT_GP_1(bank, 21, fn, sfx),     \
+        PORT_GP_1(bank, 22, fn, sfx), PORT_GP_1(bank, 23, fn, sfx),     \
+        PORT_GP_1(bank, 24, fn, sfx), PORT_GP_1(bank, 25, fn, sfx),     \
+        PORT_GP_1(bank, 26, fn, sfx), PORT_GP_1(bank, 27, fn, sfx),     \
+        PORT_GP_1(bank, 28, fn, sfx), PORT_GP_1(bank, 29, fn, sfx),     \
+        PORT_GP_1(bank, 30, fn, sfx), PORT_GP_1(bank, 31, fn, sfx)
+
+#define PORT_GP_32_REV(bank, fn, sfx)                                   \
+        PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx),     \
+        PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx),     \
+        PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx),     \
+        PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx),     \
+        PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx),     \
+        PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx),     \
+        PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx),     \
+        PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx),     \
+        PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx),     \
+        PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx),     \
+        PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx),     \
+        PORT_GP_1(bank, 9,  fn, sfx), PORT_GP_1(bank, 8,  fn, sfx),     \
+        PORT_GP_1(bank, 7,  fn, sfx), PORT_GP_1(bank, 6,  fn, sfx),     \
+        PORT_GP_1(bank, 5,  fn, sfx), PORT_GP_1(bank, 4,  fn, sfx),     \
+        PORT_GP_1(bank, 3,  fn, sfx), PORT_GP_1(bank, 2,  fn, sfx),     \
+        PORT_GP_1(bank, 1,  fn, sfx), PORT_GP_1(bank, 0,  fn, sfx)
+
+#define CPU_ALL_PORT(fn, sfx)                                           \
+        PORT_GP_32(0, fn, sfx),                                         \
+        PORT_GP_32(1, fn, sfx),                                         \
+        PORT_GP_32(2, fn, sfx),                                         \
+        PORT_GP_32(3, fn, sfx),                                         \
+        PORT_GP_32(4, fn, sfx),                                         \
+        PORT_GP_32(5, fn, sfx)
+
+#define _GP_PORT_ALL(bank, pin, name, sfx)      name##_##sfx
+
+#define _GP_GPIO(bank, pin, _name, sfx)                                 \
+        [(bank * 32) + pin] = {                                         \
+                .name = __stringify(_name),                             \
+                .enum_id = _name##_DATA,                                \
+        }
+
+#define _GP_DATA(bank, pin, name, sfx)                                  \
+        PINMUX_DATA(name##_DATA, name##_FN)
+
+#define GP_ALL(str)             CPU_ALL_PORT(_GP_PORT_ALL, str)
+#define PINMUX_GPIO_GP_ALL()    CPU_ALL_PORT(_GP_GPIO, unused)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_GP_DATA, unused)
+
+#define PINMUX_IPSR_DATA(ipsr, fn) PINMUX_DATA(fn##_MARK, FN_##ipsr, FN_##fn)
+#define PINMUX_IPSR_MODSEL_DATA(ipsr, fn, ms) PINMUX_DATA(fn##_MARK, FN_##ms, \
+                                                          FN_##ipsr, FN_##fn)
+
+enum {
+        PINMUX_RESERVED = 0,
+
+        PINMUX_DATA_BEGIN,
+        GP_ALL(DATA),
+        PINMUX_DATA_END,
+
+        PINMUX_FUNCTION_BEGIN,
+        GP_ALL(FN),
+
+        /* GPSR0 */
+        FN_IP0_2_0, FN_IP0_5_3, FN_IP0_8_6, FN_IP0_11_9, FN_IP0_15_12,
+        FN_IP0_19_16, FN_IP0_22_20, FN_IP0_26_23, FN_IP0_30_27,
+        FN_IP1_3_0, FN_IP1_7_4, FN_IP1_11_8, FN_IP1_14_12,
+        FN_IP1_17_15, FN_IP1_21_18, FN_IP1_25_22, FN_IP1_27_26,
+        FN_IP1_29_28, FN_IP2_2_0, FN_IP2_5_3, FN_IP2_8_6, FN_IP2_11_9,
+        FN_IP2_14_12, FN_IP2_17_15, FN_IP2_21_18, FN_IP2_25_22,
+        FN_IP2_28_26, FN_IP3_3_0, FN_IP3_7_4, FN_IP3_11_8,
+        FN_IP3_14_12, FN_IP3_17_15,
+
+        /* GPSR1 */
+        FN_IP3_19_18, FN_IP3_22_20, FN_IP3_25_23, FN_IP3_28_26,
+        FN_IP3_31_29, FN_IP4_2_0, FN_IP4_5_3, FN_IP4_8_6, FN_IP4_11_9,
+        FN_IP4_14_12, FN_IP4_17_15, FN_IP4_20_18, FN_IP4_23_21,
+        FN_IP4_26_24, FN_IP4_29_27, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_9_6,
+        FN_IP5_12_10, FN_IP5_14_13, FN_IP5_17_15, FN_IP5_20_18,
+        FN_IP5_23_21, FN_IP5_26_24, FN_IP5_29_27, FN_IP6_2_0,
+        FN_IP6_5_3, FN_IP6_8_6, FN_IP6_10_9, FN_IP6_13_11,
+
+        /* GPSR2 */
+        FN_IP7_28_27, FN_IP7_30_29, FN_IP8_1_0, FN_IP8_3_2, FN_IP8_5_4,
+        FN_IP8_7_6, FN_IP8_9_8, FN_IP8_11_10, FN_IP8_13_12, FN_IP8_15_14,
+        FN_IP8_17_16, FN_IP8_19_18, FN_IP8_21_20, FN_IP8_23_22,
+        FN_IP8_25_24, FN_IP8_26, FN_IP8_27, FN_VI1_DATA7_VI1_B7,
+        FN_IP6_16_14, FN_IP6_19_17, FN_IP6_22_20, FN_IP6_25_23,
+        FN_IP6_28_26, FN_IP6_31_29, FN_IP7_2_0, FN_IP7_5_3, FN_IP7_7_6,
+        FN_IP7_9_8, FN_IP7_12_10, FN_IP7_15_13,
+
+        /* GPSR3 */
+        FN_IP8_28, FN_IP8_30_29, FN_IP9_1_0, FN_IP9_3_2, FN_IP9_5_4,
+        FN_IP9_7_6, FN_IP9_11_8, FN_IP9_15_12, FN_IP9_17_16, FN_IP9_19_18,
+        FN_IP9_21_20, FN_IP9_23_22, FN_IP9_25_24, FN_IP9_27_26,
+        FN_IP9_31_28, FN_IP10_3_0, FN_IP10_6_4, FN_IP10_10_7, FN_IP10_14_11,
+        FN_IP10_18_15, FN_IP10_22_19, FN_IP10_25_23, FN_IP10_29_26,
+        FN_IP11_3_0, FN_IP11_4, FN_IP11_6_5, FN_IP11_8_7, FN_IP11_10_9,
+        FN_IP11_12_11, FN_IP11_14_13, FN_IP11_17_15, FN_IP11_21_18,
+
+        /* GPSR4 */
+        FN_IP11_23_22, FN_IP11_26_24, FN_IP11_29_27, FN_IP11_31_30,
+        FN_IP12_1_0, FN_IP12_3_2, FN_IP12_5_4, FN_IP12_7_6, FN_IP12_10_8,
+        FN_IP12_13_11, FN_IP12_16_14, FN_IP12_19_17, FN_IP12_22_20,
+        FN_IP12_24_23, FN_IP12_27_25, FN_IP12_30_28, FN_IP13_2_0,
+        FN_IP13_6_3, FN_IP13_9_7, FN_IP13_12_10, FN_IP13_15_13,
+        FN_IP13_18_16, FN_IP13_22_19, FN_IP13_25_23, FN_IP13_28_26,
+        FN_IP13_30_29, FN_IP14_2_0, FN_IP14_5_3, FN_IP14_8_6, FN_IP14_11_9,
+        FN_IP14_15_12, FN_IP14_18_16,
+
+        /* GPSR5 */
+        FN_IP14_21_19, FN_IP14_24_22, FN_IP14_27_25, FN_IP14_30_28,
+        FN_IP15_2_0, FN_IP15_5_3, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_13_12,
+        FN_IP15_15_14, FN_IP15_17_16, FN_IP15_19_18, FN_IP15_22_20,
+        FN_IP15_25_23, FN_IP15_27_26, FN_IP15_29_28, FN_IP16_2_0,
+        FN_IP16_5_3, FN_USB0_PWEN, FN_USB0_OVC_VBUS, FN_IP16_6, FN_IP16_7,
+        FN_USB2_PWEN, FN_USB2_OVC, FN_AVS1, FN_AVS2, FN_DU_DOTCLKIN0,
+        FN_IP7_26_25, FN_DU_DOTCLKIN2, FN_IP7_18_16, FN_IP7_21_19, FN_IP7_24_22,
+
+        /* IPSR0 */
+        FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+        FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5,
+        FN_VI0_G5_B, FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2,
+        FN_VI0_G6, FN_VI0_G6_B, FN_D3, FN_MSIOF3_TXD_B,
+        FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B, FN_D4,
+        FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+        FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B, FN_D5,
+        FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+        FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B, FN_D6,
+        FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+        FN_SCL2_CIS_C, FN_D7, FN_AD_DI_B, FN_SDA2_C,
+        FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
+        FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
+        FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+
+        /* IPSR1 */
+        FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
+        FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1, FN_D10,
+        FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
+        FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2, FN_D11,
+        FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
+        FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+        FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+        FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+        FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+        FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5, FN_D14,
+        FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+        FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+        FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+        FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+        FN_A0, FN_PWM3, FN_A1, FN_PWM4,
+
+        /* IPSR2 */
+        FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, FN_A3,
+        FN_PWM6, FN_MSIOF1_SS2_B, FN_A4, FN_MSIOF1_TXD_B,
+        FN_TPU0TO0, FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1,
+        FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, FN_A7,
+        FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+        FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+        FN_VI0_R4_B, FN_SCIFB2_RXD_C, FN_VI2_DATA0_VI2_B0_B,
+        FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+        FN_VI0_R5_B, FN_SCIFB2_TXD_C, FN_VI2_DATA1_VI2_B1_B,
+        FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+        FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B,
+
+        /* IPSR3 */
+        FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+        FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B,
+        FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+        FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+        FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+        FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+        FN_VI2_DATA5_VI2_B5_B, FN_A14, FN_SCIFB2_TXD_B,
+        FN_ATACS11_N, FN_MSIOF2_SS1, FN_A15, FN_SCIFB2_SCK_B,
+        FN_ATARD1_N, FN_MSIOF2_SS2, FN_A16, FN_ATAWR1_N,
+        FN_A17, FN_AD_DO_B, FN_ATADIR1_N, FN_A18,
+        FN_AD_CLK_B, FN_ATAG1_N, FN_A19, FN_AD_NCS_N_B,
+        FN_ATACS01_N, FN_EX_WAIT0_B, FN_A20, FN_SPCLK,
+        FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+
+        /* IPSR4 */
+        FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5,
+        FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B,
+        FN_VI2_G6, FN_A23, FN_IO2, FN_VI1_G7,
+        FN_VI1_G7_B, FN_VI2_G7, FN_A24, FN_IO3,
+        FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+        FN_VI2_CLKENB_B, FN_A25, FN_SSL, FN_VI1_G6,
+        FN_VI1_G6_B, FN_VI2_FIELD, FN_VI2_FIELD_B, FN_CS0_N,
+        FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+        FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+        FN_VI2_CLK, FN_VI2_CLK_B, FN_EX_CS0_N, FN_HRX1_B,
+        FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0, FN_HTX0_B,
+        FN_MSIOF0_SS1_B, FN_EX_CS1_N, FN_GPS_CLK,
+        FN_HCTS1_N_B, FN_VI1_FIELD, FN_VI1_FIELD_B,
+        FN_VI2_R1, FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+        FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2,
+
+        /* IPSR5 */
+        FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+        FN_VI2_R3, FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+        FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
+        FN_INTC_EN0_N, FN_SCL1_CIS, FN_EX_CS5_N, FN_CAN0_RX,
+        FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N, FN_VI1_G2,
+        FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
+        FN_SDA1_CIS, FN_BS_N, FN_IETX, FN_HTX1_B,
+        FN_CAN1_TX, FN_DRACK0, FN_IETX_C, FN_RD_N,
+        FN_CAN0_TX, FN_SCIFA0_SCK_B, FN_RD_WR_N, FN_VI1_G3,
+        FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+        FN_INTC_IRQ4_N, FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+        FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B,
+        FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+        FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+        FN_IERX_C, FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+        FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+        FN_MSIOF0_SCK_B, FN_DREQ0_N, FN_VI1_HSYNC_N,
+        FN_VI1_HSYNC_N_B, FN_VI2_R7, FN_SSI_SCK78_C,
+        FN_SSI_WS78_B,
+
+        /* IPSR6 */
+        FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+        FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C,
+        FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+        FN_SSI_SDATA7_C, FN_SSI_SCK78_B, FN_DACK1, FN_IRQ1,
+        FN_INTC_IRQ1_N, FN_SSI_WS6_B, FN_SSI_SDATA8_C,
+        FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B,
+        FN_MSIOF0_TXD_B, FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+        FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B,
+        FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+        FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+        FN_SCL2_CIS_E, FN_ETH_RX_ER, FN_RMII_RX_ER,
+        FN_STP_ISD_0_B, FN_TS_SPSYNC0_D, FN_GLO_Q1_C,
+        FN_SDA2_E, FN_SDA2_CIS_E, FN_ETH_RXD0, FN_RMII_RXD0,
+        FN_STP_ISEN_0_B, FN_TS_SDAT0_D, FN_GLO_I0_C,
+        FN_SCIFB1_SCK_G, FN_SCK1_E, FN_ETH_RXD1,
+        FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+        FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G,
+        FN_RX1_E, FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+        FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E,
+        FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+        FN_STP_IVCXO27_1_B, FN_HRX0_F,
+
+        /* IPSR7 */
+        FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+        FN_SIM0_D_C, FN_HCTS0_N_F, FN_ETH_TXD1,
+        FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+        FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C,
+        FN_HRTS0_N_F, FN_ETH_MAGIC, FN_RMII_MAGIC,
+        FN_SIM0_RST_C, FN_ETH_TXD0, FN_RMII_TXD0,
+        FN_STP_ISCLK_1_B, FN_TS_SDEN1_C, FN_GLO_SCLK_C,
+        FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+        FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, FN_PWM0,
+        FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+        FN_GLO_SS_C, FN_PWM1, FN_SCIFA2_TXD_C,
+        FN_STP_ISSYNC_1_B, FN_TS_SCK1_C, FN_GLO_RFON_C,
+        FN_PCMOE_N, FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C,
+        FN_PCMWE_N, FN_IECLK_C, FN_DU1_DOTCLKIN,
+        FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, FN_VI0_CLK,
+        FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+        FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+        FN_MII_RXD2,
+
+        /* IPSR8 */
+        FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3,
+        FN_MII_RXD3, FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N,
+        FN_AVB_RXD4, FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N,
+        FN_AVB_RXD5, FN_VI0_DATA4_VI0_B4, FN_ATAG0_N,
+        FN_AVB_RXD6, FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1,
+        FN_AVB_RXD7, FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER,
+        FN_MII_RX_ER, FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK,
+        FN_MII_RX_CLK, FN_VI1_CLK, FN_AVB_RX_DV,
+        FN_MII_RX_DV, FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D,
+        FN_AVB_CRS, FN_MII_CRS, FN_VI1_DATA1_VI1_B1,
+        FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+        FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+        FN_MII_MDIO, FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D,
+        FN_AVB_GTX_CLK, FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+        FN_AVB_MAGIC, FN_MII_MAGIC, FN_VI1_DATA5_VI1_B5,
+        FN_AVB_PHY_INT, FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+        FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B, FN_SD0_CMD,
+        FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B,
+
+        /* IPSR9 */
+        FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B,
+        FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B,
+        FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B,
+        FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B,
+        FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+        FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+        FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, FN_SD0_WP,
+        FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+        FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+        FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, FN_SD1_CLK,
+        FN_AVB_TX_EN, FN_MII_TX_EN, FN_SD1_CMD,
+        FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+        FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK,
+        FN_SCIFB0_RXD_B, FN_SD1_DAT1, FN_AVB_LINK,
+        FN_MII_LINK, FN_SCIFB0_TXD_B, FN_SD1_DAT2,
+        FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+        FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0,
+        FN_SCIFB0_RTS_N_B, FN_SD1_CD, FN_MMC1_D6,
+        FN_TS_SDEN1, FN_USB1_EXTP, FN_GLO_SS, FN_VI0_CLK_B,
+        FN_SCL2_D, FN_SCL2_CIS_D, FN_SIM0_CLK_B,
+        FN_VI3_CLK_B,
+
+        /* IPSR10 */
+        FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+        FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+        FN_SIM0_D_B, FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+        FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+        FN_VI3_DATA0_B, FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+        FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+        FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+        FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+        FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+        FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+        FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+        FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+        FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+        FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+        FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+        FN_GLO_Q0_B, FN_VI3_DATA4_B, FN_SD2_DAT3,
+        FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+        FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B,
+        FN_VI3_DATA5_B, FN_SD2_CD, FN_MMC0_D4,
+        FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+        FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+        FN_GLO_I0_B, FN_VI3_DATA6_B,
+
+        /* IPSR11 */
+        FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+        FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+        FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B,
+        FN_SD3_CLK, FN_MMC1_CLK, FN_SD3_CMD, FN_MMC1_CMD,
+        FN_MTS_N, FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N,
+        FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, FN_SD3_DAT2,
+        FN_MMC1_D2, FN_SDATA, FN_SD3_DAT3, FN_MMC1_D3,
+        FN_SCKZ, FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+        FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, FN_SD3_WP,
+        FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+        FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+        FN_RDS_DATA_E, FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B,
+        FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B,
+        FN_SDA2_CIS_B, FN_MLB_DAT, FN_SPV_EVEN,
+        FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+        FN_RDS_CLK_B, FN_SSI_SCK0129, FN_CAN_CLK_B,
+        FN_MOUT0,
+
+        /* IPSR12 */
+        FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1,
+        FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2,
+        FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5,
+        FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+        FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+        FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, FN_SSI_WS34,
+        FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+        FN_CAN_STEP0, FN_SSI_SDATA3, FN_STP_ISCLK_0,
+        FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK,
+        FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+        FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0,
+        FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+        FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1,
+        FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+        FN_CAN_DEBUGOUT2, FN_SSI_SCK5, FN_SCIFB1_SCK,
+        FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+        FN_CAN_DEBUGOUT3, FN_SSI_WS5, FN_SCIFB1_RXD,
+        FN_IECLK_B, FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+        FN_CAN_DEBUGOUT4,
+
+        /* IPSR13 */
+        FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+        FN_LCDOUT2, FN_CAN_DEBUGOUT5, FN_SSI_SCK6,
+        FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
+        FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+        FN_BPFCLK_F, FN_RDS_CLK_E, FN_SSI_WS6,
+        FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+        FN_LCDOUT4, FN_CAN_DEBUGOUT7, FN_SSI_SDATA6,
+        FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
+        FN_CAN_DEBUGOUT8, FN_SSI_SCK78, FN_STP_IVCXO27_1,
+        FN_SCK1, FN_SCIFA1_SCK, FN_DU2_DR6, FN_LCDOUT6,
+        FN_CAN_DEBUGOUT9, FN_SSI_WS78, FN_STP_ISCLK_1,
+        FN_SCIFB2_SCK, FN_SCIFA2_CTS_N, FN_DU2_DR7,
+        FN_LCDOUT7, FN_CAN_DEBUGOUT10, FN_SSI_SDATA7,
+        FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+        FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11,
+        FN_BPFCLK_E, FN_RDS_CLK_D, FN_SSI_SDATA7_B,
+        FN_FMIN_G, FN_RDS_DATA_F, FN_SSI_SDATA8,
+        FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+        FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, FN_SSI_SDATA9,
+        FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+        FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, FN_AUDIO_CLKA,
+        FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14,
+
+        /* IPSR14 */
+        FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+        FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+        FN_REMOCON, FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0,
+        FN_MSIOF3_SS2, FN_DU2_DG2, FN_LCDOUT10, FN_SDA1_C,
+        FN_SDA1_CIS_C, FN_SCIFA0_RXD, FN_HRX1, FN_RX0,
+        FN_DU2_DR0, FN_LCDOUT0, FN_SCIFA0_TXD, FN_HTX1,
+        FN_TX0, FN_DU2_DR1, FN_LCDOUT1, FN_SCIFA0_CTS_N,
+        FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC, FN_DU2_DG3,
+        FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
+        FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
+        FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B,
+        FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+        FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE,
+        FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+        FN_LCDOUT9, FN_SCIFA1_CTS_N, FN_AD_CLK,
+        FN_CTS1_N, FN_MSIOF3_RXD, FN_DU0_DOTCLKOUT, FN_QCLK,
+        FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
+        FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+        FN_HRTS0_N_C,
+
+        /* IPSR15 */
+        FN_SCIFA2_SCK, FN_FMCLK, FN_MSIOF3_SCK, FN_DU2_DG7,
+        FN_LCDOUT15, FN_SCIF_CLK_B, FN_SCIFA2_RXD, FN_FMIN,
+        FN_DU2_DB0, FN_LCDOUT16, FN_SCL2, FN_SCL2_CIS,
+        FN_SCIFA2_TXD, FN_BPFCLK, FN_DU2_DB1, FN_LCDOUT17,
+        FN_SDA2, FN_SDA2_CIS, FN_HSCK0, FN_TS_SDEN0,
+        FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C, FN_HRX0,
+        FN_DU2_DB2, FN_LCDOUT18, FN_HTX0, FN_DU2_DB3,
+        FN_LCDOUT19, FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4,
+        FN_LCDOUT20, FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5,
+        FN_LCDOUT21, FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+        FN_DU2_DB6, FN_LCDOUT22, FN_MSIOF0_SYNC, FN_TS_SCK0,
+        FN_SSI_SCK2, FN_ADIDATA, FN_DU2_DB7, FN_LCDOUT23,
+        FN_SCIFA2_RXD_B, FN_MSIOF0_SS1, FN_ADICHS0,
+        FN_DU2_DG5, FN_LCDOUT13, FN_MSIOF0_TXD, FN_ADICHS1,
+        FN_DU2_DG6, FN_LCDOUT14,
+
+        /* IPSR16 */
+        FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+        FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B,
+        FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+        FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C,
+        FN_USB1_PWEN, FN_AUDIO_CLKOUT_D, FN_USB1_OVC,
+        FN_TCLK1_B,
+
+        FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+        FN_SEL_SCIF1_4,
+        FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2,
+        FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2,
+        FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
+        FN_SEL_SCIFB1_4,
+        FN_SEL_SCIFB1_5, FN_SEL_SCIFB1_6,
+        FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, FN_SEL_SCIFA1_3,
+        FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+        FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+        FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+        FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2,
+        FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+        FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2,
+        FN_SEL_VI3_0, FN_SEL_VI3_1,
+        FN_SEL_VI2_0, FN_SEL_VI2_1,
+        FN_SEL_VI1_0, FN_SEL_VI1_1,
+        FN_SEL_VI0_0, FN_SEL_VI0_1,
+        FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2,
+        FN_SEL_LBS_0, FN_SEL_LBS_1,
+        FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+        FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+        FN_SEL_SOF0_0, FN_SEL_SOF0_1,
+
+        FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+        FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+        FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+        FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+        FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+        FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2,
+        FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+        FN_SEL_ADI_0, FN_SEL_ADI_1,
+        FN_SEL_SSP_0, FN_SEL_SSP_1,
+        FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+        FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6,
+        FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, FN_SEL_HSCIF0_3,
+        FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5,
+        FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2,
+        FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+        FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5,
+        FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2,
+        FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2,
+
+        FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+        FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+        FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
+        FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+        FN_SEL_IIC2_4,
+        FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2,
+        FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+        FN_SEL_I2C2_4,
+        FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2,
+        PINMUX_FUNCTION_END,
+
+        PINMUX_MARK_BEGIN,
+
+        VI1_DATA7_VI1_B7_MARK,
+
+        USB0_PWEN_MARK, USB0_OVC_VBUS_MARK,
+        USB2_PWEN_MARK, USB2_OVC_MARK, AVS1_MARK, AVS2_MARK,
+        DU_DOTCLKIN0_MARK, DU_DOTCLKIN2_MARK,
+
+        D0_MARK, MSIOF3_SCK_B_MARK, VI3_DATA0_MARK, VI0_G4_MARK, VI0_G4_B_MARK,
+        D1_MARK, MSIOF3_SYNC_B_MARK, VI3_DATA1_MARK, VI0_G5_MARK,
+        VI0_G5_B_MARK, D2_MARK, MSIOF3_RXD_B_MARK, VI3_DATA2_MARK,
+        VI0_G6_MARK, VI0_G6_B_MARK, D3_MARK, MSIOF3_TXD_B_MARK,
+        VI3_DATA3_MARK, VI0_G7_MARK, VI0_G7_B_MARK, D4_MARK,
+        SCIFB1_RXD_F_MARK, SCIFB0_RXD_C_MARK, VI3_DATA4_MARK,
+        VI0_R0_MARK, VI0_R0_B_MARK, RX0_B_MARK, D5_MARK,
+        SCIFB1_TXD_F_MARK, SCIFB0_TXD_C_MARK, VI3_DATA5_MARK,
+        VI0_R1_MARK, VI0_R1_B_MARK, TX0_B_MARK, D6_MARK,
+        SCL2_C_MARK, VI3_DATA6_MARK, VI0_R2_MARK, VI0_R2_B_MARK,
+        SCL2_CIS_C_MARK, D7_MARK, AD_DI_B_MARK, SDA2_C_MARK,
+        VI3_DATA7_MARK, VI0_R3_MARK, VI0_R3_B_MARK, SDA2_CIS_C_MARK,
+        D8_MARK, SCIFA1_SCK_C_MARK, AVB_TXD0_MARK, MII_TXD0_MARK,
+        VI0_G0_MARK, VI0_G0_B_MARK, VI2_DATA0_VI2_B0_MARK,
+
+        D9_MARK, SCIFA1_RXD_C_MARK, AVB_TXD1_MARK, MII_TXD1_MARK,
+        VI0_G1_MARK, VI0_G1_B_MARK, VI2_DATA1_VI2_B1_MARK, D10_MARK,
+        SCIFA1_TXD_C_MARK, AVB_TXD2_MARK, MII_TXD2_MARK,
+        VI0_G2_MARK, VI0_G2_B_MARK, VI2_DATA2_VI2_B2_MARK, D11_MARK,
+        SCIFA1_CTS_N_C_MARK, AVB_TXD3_MARK, MII_TXD3_MARK,
+        VI0_G3_MARK, VI0_G3_B_MARK, VI2_DATA3_VI2_B3_MARK,
+        D12_MARK, SCIFA1_RTS_N_C_MARK, AVB_TXD4_MARK,
+        VI0_HSYNC_N_MARK, VI0_HSYNC_N_B_MARK, VI2_DATA4_VI2_B4_MARK,
+        D13_MARK, AVB_TXD5_MARK, VI0_VSYNC_N_MARK,
+        VI0_VSYNC_N_B_MARK, VI2_DATA5_VI2_B5_MARK, D14_MARK,
+        SCIFB1_RXD_C_MARK, AVB_TXD6_MARK, RX1_B_MARK,
+        VI0_CLKENB_MARK, VI0_CLKENB_B_MARK, VI2_DATA6_VI2_B6_MARK,
+        D15_MARK, SCIFB1_TXD_C_MARK, AVB_TXD7_MARK, TX1_B_MARK,
+        VI0_FIELD_MARK, VI0_FIELD_B_MARK, VI2_DATA7_VI2_B7_MARK,
+        A0_MARK, PWM3_MARK, A1_MARK, PWM4_MARK,
+
+        A2_MARK, PWM5_MARK, MSIOF1_SS1_B_MARK, A3_MARK,
+        PWM6_MARK, MSIOF1_SS2_B_MARK, A4_MARK, MSIOF1_TXD_B_MARK,
+        TPU0TO0_MARK, A5_MARK, SCIFA1_TXD_B_MARK, TPU0TO1_MARK,
+        A6_MARK, SCIFA1_RTS_N_B_MARK, TPU0TO2_MARK, A7_MARK,
+        SCIFA1_SCK_B_MARK, AUDIO_CLKOUT_B_MARK, TPU0TO3_MARK,
+        A8_MARK, SCIFA1_RXD_B_MARK, SSI_SCK5_B_MARK, VI0_R4_MARK,
+        VI0_R4_B_MARK, SCIFB2_RXD_C_MARK, VI2_DATA0_VI2_B0_B_MARK,
+        A9_MARK, SCIFA1_CTS_N_B_MARK, SSI_WS5_B_MARK, VI0_R5_MARK,
+        VI0_R5_B_MARK, SCIFB2_TXD_C_MARK, VI2_DATA1_VI2_B1_B_MARK,
+        A10_MARK, SSI_SDATA5_B_MARK, MSIOF2_SYNC_MARK, VI0_R6_MARK,
+        VI0_R6_B_MARK, VI2_DATA2_VI2_B2_B_MARK,
+
+        A11_MARK, SCIFB2_CTS_N_B_MARK, MSIOF2_SCK_MARK, VI1_R0_MARK,
+        VI1_R0_B_MARK, VI2_G0_MARK, VI2_DATA3_VI2_B3_B_MARK,
+        A12_MARK, SCIFB2_RXD_B_MARK, MSIOF2_TXD_MARK, VI1_R1_MARK,
+        VI1_R1_B_MARK, VI2_G1_MARK, VI2_DATA4_VI2_B4_B_MARK,
+        A13_MARK, SCIFB2_RTS_N_B_MARK, EX_WAIT2_MARK,
+        MSIOF2_RXD_MARK, VI1_R2_MARK, VI1_R2_B_MARK, VI2_G2_MARK,
+        VI2_DATA5_VI2_B5_B_MARK, A14_MARK, SCIFB2_TXD_B_MARK,
+        ATACS11_N_MARK, MSIOF2_SS1_MARK, A15_MARK, SCIFB2_SCK_B_MARK,
+        ATARD1_N_MARK, MSIOF2_SS2_MARK, A16_MARK, ATAWR1_N_MARK,
+        A17_MARK, AD_DO_B_MARK, ATADIR1_N_MARK, A18_MARK,
+        AD_CLK_B_MARK, ATAG1_N_MARK, A19_MARK, AD_NCS_N_B_MARK,
+        ATACS01_N_MARK, EX_WAIT0_B_MARK, A20_MARK, SPCLK_MARK,
+        VI1_R3_MARK, VI1_R3_B_MARK, VI2_G4_MARK,
+
+        A21_MARK, MOSI_IO0_MARK, VI1_R4_MARK, VI1_R4_B_MARK, VI2_G5_MARK,
+        A22_MARK, MISO_IO1_MARK, VI1_R5_MARK, VI1_R5_B_MARK,
+        VI2_G6_MARK, A23_MARK, IO2_MARK, VI1_G7_MARK,
+        VI1_G7_B_MARK, VI2_G7_MARK, A24_MARK, IO3_MARK,
+        VI1_R7_MARK, VI1_R7_B_MARK, VI2_CLKENB_MARK,
+        VI2_CLKENB_B_MARK, A25_MARK, SSL_MARK, VI1_G6_MARK,
+        VI1_G6_B_MARK, VI2_FIELD_MARK, VI2_FIELD_B_MARK, CS0_N_MARK,
+        VI1_R6_MARK, VI1_R6_B_MARK, VI2_G3_MARK, MSIOF0_SS2_B_MARK,
+        CS1_N_A26_MARK, SPEEDIN_MARK, VI0_R7_MARK, VI0_R7_B_MARK,
+        VI2_CLK_MARK, VI2_CLK_B_MARK, EX_CS0_N_MARK, HRX1_B_MARK,
+        VI1_G5_MARK, VI1_G5_B_MARK, VI2_R0_MARK, HTX0_B_MARK,
+        MSIOF0_SS1_B_MARK, EX_CS1_N_MARK, GPS_CLK_MARK,
+        HCTS1_N_B_MARK, VI1_FIELD_MARK, VI1_FIELD_B_MARK,
+        VI2_R1_MARK, EX_CS2_N_MARK, GPS_SIGN_MARK, HRTS1_N_B_MARK,
+        VI3_CLKENB_MARK, VI1_G0_MARK, VI1_G0_B_MARK, VI2_R2_MARK,
+
+        EX_CS3_N_MARK, GPS_MAG_MARK, VI3_FIELD_MARK,
+        VI1_G1_MARK, VI1_G1_B_MARK, VI2_R3_MARK,
+        EX_CS4_N_MARK, MSIOF1_SCK_B_MARK, VI3_HSYNC_N_MARK,
+        VI2_HSYNC_N_MARK, SCL1_MARK, VI2_HSYNC_N_B_MARK,
+        INTC_EN0_N_MARK, SCL1_CIS_MARK, EX_CS5_N_MARK, CAN0_RX_MARK,
+        MSIOF1_RXD_B_MARK, VI3_VSYNC_N_MARK, VI1_G2_MARK,
+        VI1_G2_B_MARK, VI2_R4_MARK, SDA1_MARK, INTC_EN1_N_MARK,
+        SDA1_CIS_MARK, BS_N_MARK, IETX_MARK, HTX1_B_MARK,
+        CAN1_TX_MARK, DRACK0_MARK, IETX_C_MARK, RD_N_MARK,
+        CAN0_TX_MARK, SCIFA0_SCK_B_MARK, RD_WR_N_MARK, VI1_G3_MARK,
+        VI1_G3_B_MARK, VI2_R5_MARK, SCIFA0_RXD_B_MARK,
+        INTC_IRQ4_N_MARK, WE0_N_MARK, IECLK_MARK, CAN_CLK_MARK,
+        VI2_VSYNC_N_MARK, SCIFA0_TXD_B_MARK, VI2_VSYNC_N_B_MARK,
+        WE1_N_MARK, IERX_MARK, CAN1_RX_MARK, VI1_G4_MARK,
+        VI1_G4_B_MARK, VI2_R6_MARK, SCIFA0_CTS_N_B_MARK,
+        IERX_C_MARK, EX_WAIT0_MARK, IRQ3_MARK, INTC_IRQ3_N_MARK,
+        VI3_CLK_MARK, SCIFA0_RTS_N_B_MARK, HRX0_B_MARK,
+        MSIOF0_SCK_B_MARK, DREQ0_N_MARK, VI1_HSYNC_N_MARK,
+        VI1_HSYNC_N_B_MARK, VI2_R7_MARK, SSI_SCK78_C_MARK,
+        SSI_WS78_B_MARK,
+
+        DACK0_MARK, IRQ0_MARK, INTC_IRQ0_N_MARK, SSI_SCK6_B_MARK,
+        VI1_VSYNC_N_MARK, VI1_VSYNC_N_B_MARK, SSI_WS78_C_MARK,
+        DREQ1_N_MARK, VI1_CLKENB_MARK, VI1_CLKENB_B_MARK,
+        SSI_SDATA7_C_MARK, SSI_SCK78_B_MARK, DACK1_MARK, IRQ1_MARK,
+        INTC_IRQ1_N_MARK, SSI_WS6_B_MARK, SSI_SDATA8_C_MARK,
+        DREQ2_N_MARK, HSCK1_B_MARK, HCTS0_N_B_MARK,
+        MSIOF0_TXD_B_MARK, DACK2_MARK, IRQ2_MARK, INTC_IRQ2_N_MARK,
+        SSI_SDATA6_B_MARK, HRTS0_N_B_MARK, MSIOF0_RXD_B_MARK,
+        ETH_CRS_DV_MARK, RMII_CRS_DV_MARK, STP_ISCLK_0_B_MARK,
+        TS_SDEN0_D_MARK, GLO_Q0_C_MARK, SCL2_E_MARK,
+        SCL2_CIS_E_MARK, ETH_RX_ER_MARK, RMII_RX_ER_MARK,
+        STP_ISD_0_B_MARK, TS_SPSYNC0_D_MARK, GLO_Q1_C_MARK,
+        SDA2_E_MARK, SDA2_CIS_E_MARK, ETH_RXD0_MARK, RMII_RXD0_MARK,
+        STP_ISEN_0_B_MARK, TS_SDAT0_D_MARK, GLO_I0_C_MARK,
+        SCIFB1_SCK_G_MARK, SCK1_E_MARK, ETH_RXD1_MARK,
+        RMII_RXD1_MARK, HRX0_E_MARK, STP_ISSYNC_0_B_MARK,
+        TS_SCK0_D_MARK, GLO_I1_C_MARK, SCIFB1_RXD_G_MARK,
+        RX1_E_MARK, ETH_LINK_MARK, RMII_LINK_MARK, HTX0_E_MARK,
+        STP_IVCXO27_0_B_MARK, SCIFB1_TXD_G_MARK, TX1_E_MARK,
+        ETH_REF_CLK_MARK, RMII_REF_CLK_MARK, HCTS0_N_E_MARK,
+        STP_IVCXO27_1_B_MARK, HRX0_F_MARK,
+
+        ETH_MDIO_MARK, RMII_MDIO_MARK, HRTS0_N_E_MARK,
+        SIM0_D_C_MARK, HCTS0_N_F_MARK, ETH_TXD1_MARK,
+        RMII_TXD1_MARK, HTX0_F_MARK, BPFCLK_G_MARK, RDS_CLK_F_MARK,
+        ETH_TX_EN_MARK, RMII_TX_EN_MARK, SIM0_CLK_C_MARK,
+        HRTS0_N_F_MARK, ETH_MAGIC_MARK, RMII_MAGIC_MARK,
+        SIM0_RST_C_MARK, ETH_TXD0_MARK, RMII_TXD0_MARK,
+        STP_ISCLK_1_B_MARK, TS_SDEN1_C_MARK, GLO_SCLK_C_MARK,
+        ETH_MDC_MARK, RMII_MDC_MARK, STP_ISD_1_B_MARK,
+        TS_SPSYNC1_C_MARK, GLO_SDATA_C_MARK, PWM0_MARK,
+        SCIFA2_SCK_C_MARK, STP_ISEN_1_B_MARK, TS_SDAT1_C_MARK,
+        GLO_SS_C_MARK, PWM1_MARK, SCIFA2_TXD_C_MARK,
+        STP_ISSYNC_1_B_MARK, TS_SCK1_C_MARK, GLO_RFON_C_MARK,
+        PCMOE_N_MARK, PWM2_MARK, PWMFSW0_MARK, SCIFA2_RXD_C_MARK,
+        PCMWE_N_MARK, IECLK_C_MARK, DU1_DOTCLKIN_MARK,
+        AUDIO_CLKC_MARK, AUDIO_CLKOUT_C_MARK, VI0_CLK_MARK,
+        ATACS00_N_MARK, AVB_RXD1_MARK, MII_RXD1_MARK,
+        VI0_DATA0_VI0_B0_MARK, ATACS10_N_MARK, AVB_RXD2_MARK,
+        MII_RXD2_MARK,
+
+        VI0_DATA1_VI0_B1_MARK, ATARD0_N_MARK, AVB_RXD3_MARK,
+        MII_RXD3_MARK, VI0_DATA2_VI0_B2_MARK, ATAWR0_N_MARK,
+        AVB_RXD4_MARK, VI0_DATA3_VI0_B3_MARK, ATADIR0_N_MARK,
+        AVB_RXD5_MARK, VI0_DATA4_VI0_B4_MARK, ATAG0_N_MARK,
+        AVB_RXD6_MARK, VI0_DATA5_VI0_B5_MARK, EX_WAIT1_MARK,
+        AVB_RXD7_MARK, VI0_DATA6_VI0_B6_MARK, AVB_RX_ER_MARK,
+        MII_RX_ER_MARK, VI0_DATA7_VI0_B7_MARK, AVB_RX_CLK_MARK,
+        MII_RX_CLK_MARK, VI1_CLK_MARK, AVB_RX_DV_MARK,
+        MII_RX_DV_MARK, VI1_DATA0_VI1_B0_MARK, SCIFA1_SCK_D_MARK,
+        AVB_CRS_MARK, MII_CRS_MARK, VI1_DATA1_VI1_B1_MARK,
+        SCIFA1_RXD_D_MARK, AVB_MDC_MARK, MII_MDC_MARK,
+        VI1_DATA2_VI1_B2_MARK, SCIFA1_TXD_D_MARK, AVB_MDIO_MARK,
+        MII_MDIO_MARK, VI1_DATA3_VI1_B3_MARK, SCIFA1_CTS_N_D_MARK,
+        AVB_GTX_CLK_MARK, VI1_DATA4_VI1_B4_MARK, SCIFA1_RTS_N_D_MARK,
+        AVB_MAGIC_MARK, MII_MAGIC_MARK, VI1_DATA5_VI1_B5_MARK,
+        AVB_PHY_INT_MARK, VI1_DATA6_VI1_B6_MARK, AVB_GTXREFCLK_MARK,
+        SD0_CLK_MARK, VI1_DATA0_VI1_B0_B_MARK, SD0_CMD_MARK,
+        SCIFB1_SCK_B_MARK, VI1_DATA1_VI1_B1_B_MARK,
+
+        SD0_DAT0_MARK, SCIFB1_RXD_B_MARK, VI1_DATA2_VI1_B2_B_MARK,
+        SD0_DAT1_MARK, SCIFB1_TXD_B_MARK, VI1_DATA3_VI1_B3_B_MARK,
+        SD0_DAT2_MARK, SCIFB1_CTS_N_B_MARK, VI1_DATA4_VI1_B4_B_MARK,
+        SD0_DAT3_MARK, SCIFB1_RTS_N_B_MARK, VI1_DATA5_VI1_B5_B_MARK,
+        SD0_CD_MARK, MMC0_D6_MARK, TS_SDEN0_B_MARK, USB0_EXTP_MARK,
+        GLO_SCLK_MARK, VI1_DATA6_VI1_B6_B_MARK, SCL1_B_MARK,
+        SCL1_CIS_B_MARK, VI2_DATA6_VI2_B6_B_MARK, SD0_WP_MARK,
+        MMC0_D7_MARK, TS_SPSYNC0_B_MARK, USB0_IDIN_MARK,
+        GLO_SDATA_MARK, VI1_DATA7_VI1_B7_B_MARK, SDA1_B_MARK,
+        SDA1_CIS_B_MARK, VI2_DATA7_VI2_B7_B_MARK, SD1_CLK_MARK,
+        AVB_TX_EN_MARK, MII_TX_EN_MARK, SD1_CMD_MARK,
+        AVB_TX_ER_MARK, MII_TX_ER_MARK, SCIFB0_SCK_B_MARK,
+        SD1_DAT0_MARK, AVB_TX_CLK_MARK, MII_TX_CLK_MARK,
+        SCIFB0_RXD_B_MARK, SD1_DAT1_MARK, AVB_LINK_MARK,
+        MII_LINK_MARK, SCIFB0_TXD_B_MARK, SD1_DAT2_MARK,
+        AVB_COL_MARK, MII_COL_MARK, SCIFB0_CTS_N_B_MARK,
+        SD1_DAT3_MARK, AVB_RXD0_MARK, MII_RXD0_MARK,
+        SCIFB0_RTS_N_B_MARK, SD1_CD_MARK, MMC1_D6_MARK,
+        TS_SDEN1_MARK, USB1_EXTP_MARK, GLO_SS_MARK, VI0_CLK_B_MARK,
+        SCL2_D_MARK, SCL2_CIS_D_MARK, SIM0_CLK_B_MARK,
+        VI3_CLK_B_MARK,
+
+        SD1_WP_MARK, MMC1_D7_MARK, TS_SPSYNC1_MARK, USB1_IDIN_MARK,
+        GLO_RFON_MARK, VI1_CLK_B_MARK, SDA2_D_MARK, SDA2_CIS_D_MARK,
+        SIM0_D_B_MARK, SD2_CLK_MARK, MMC0_CLK_MARK, SIM0_CLK_MARK,
+        VI0_DATA0_VI0_B0_B_MARK, TS_SDEN0_C_MARK, GLO_SCLK_B_MARK,
+        VI3_DATA0_B_MARK, SD2_CMD_MARK, MMC0_CMD_MARK, SIM0_D_MARK,
+        VI0_DATA1_VI0_B1_B_MARK, SCIFB1_SCK_E_MARK, SCK1_D_MARK,
+        TS_SPSYNC0_C_MARK, GLO_SDATA_B_MARK, VI3_DATA1_B_MARK,
+        SD2_DAT0_MARK, MMC0_D0_MARK, FMCLK_B_MARK,
+        VI0_DATA2_VI0_B2_B_MARK, SCIFB1_RXD_E_MARK, RX1_D_MARK,
+        TS_SDAT0_C_MARK, GLO_SS_B_MARK, VI3_DATA2_B_MARK,
+        SD2_DAT1_MARK, MMC0_D1_MARK, FMIN_B_MARK, RDS_DATA_MARK,
+        VI0_DATA3_VI0_B3_B_MARK, SCIFB1_TXD_E_MARK, TX1_D_MARK,
+        TS_SCK0_C_MARK, GLO_RFON_B_MARK, VI3_DATA3_B_MARK,
+        SD2_DAT2_MARK, MMC0_D2_MARK, BPFCLK_B_MARK, RDS_CLK_MARK,
+        VI0_DATA4_VI0_B4_B_MARK, HRX0_D_MARK, TS_SDEN1_B_MARK,
+        GLO_Q0_B_MARK, VI3_DATA4_B_MARK, SD2_DAT3_MARK,
+        MMC0_D3_MARK, SIM0_RST_MARK, VI0_DATA5_VI0_B5_B_MARK,
+        HTX0_D_MARK, TS_SPSYNC1_B_MARK, GLO_Q1_B_MARK,
+        VI3_DATA5_B_MARK, SD2_CD_MARK, MMC0_D4_MARK,
+        TS_SDAT0_B_MARK, USB2_EXTP_MARK, GLO_I0_MARK,
+        VI0_DATA6_VI0_B6_B_MARK, HCTS0_N_D_MARK, TS_SDAT1_B_MARK,
+        GLO_I0_B_MARK, VI3_DATA6_B_MARK,
+
+        SD2_WP_MARK, MMC0_D5_MARK, TS_SCK0_B_MARK, USB2_IDIN_MARK,
+        GLO_I1_MARK, VI0_DATA7_VI0_B7_B_MARK, HRTS0_N_D_MARK,
+        TS_SCK1_B_MARK, GLO_I1_B_MARK, VI3_DATA7_B_MARK,
+        SD3_CLK_MARK, MMC1_CLK_MARK, SD3_CMD_MARK, MMC1_CMD_MARK,
+        MTS_N_MARK, SD3_DAT0_MARK, MMC1_D0_MARK, STM_N_MARK,
+        SD3_DAT1_MARK, MMC1_D1_MARK, MDATA_MARK, SD3_DAT2_MARK,
+        MMC1_D2_MARK, SDATA_MARK, SD3_DAT3_MARK, MMC1_D3_MARK,
+        SCKZ_MARK, SD3_CD_MARK, MMC1_D4_MARK, TS_SDAT1_MARK,
+        VSP_MARK, GLO_Q0_MARK, SIM0_RST_B_MARK, SD3_WP_MARK,
+        MMC1_D5_MARK, TS_SCK1_MARK, GLO_Q1_MARK, FMIN_C_MARK,
+        RDS_DATA_B_MARK, FMIN_E_MARK, RDS_DATA_D_MARK, FMIN_F_MARK,
+        RDS_DATA_E_MARK, MLB_CLK_MARK, SCL2_B_MARK, SCL2_CIS_B_MARK,
+        MLB_SIG_MARK, SCIFB1_RXD_D_MARK, RX1_C_MARK, SDA2_B_MARK,
+        SDA2_CIS_B_MARK, MLB_DAT_MARK, SPV_EVEN_MARK,
+        SCIFB1_TXD_D_MARK, TX1_C_MARK, BPFCLK_C_MARK,
+        RDS_CLK_B_MARK, SSI_SCK0129_MARK, CAN_CLK_B_MARK,
+        MOUT0_MARK,
+
+        SSI_WS0129_MARK, CAN0_TX_B_MARK, MOUT1_MARK,
+        SSI_SDATA0_MARK, CAN0_RX_B_MARK, MOUT2_MARK,
+        SSI_SDATA1_MARK, CAN1_TX_B_MARK, MOUT5_MARK,
+        SSI_SDATA2_MARK, CAN1_RX_B_MARK, SSI_SCK1_MARK, MOUT6_MARK,
+        SSI_SCK34_MARK, STP_OPWM_0_MARK, SCIFB0_SCK_MARK,
+        MSIOF1_SCK_MARK, CAN_DEBUG_HW_TRIGGER_MARK, SSI_WS34_MARK,
+        STP_IVCXO27_0_MARK, SCIFB0_RXD_MARK, MSIOF1_SYNC_MARK,
+        CAN_STEP0_MARK, SSI_SDATA3_MARK, STP_ISCLK_0_MARK,
+        SCIFB0_TXD_MARK, MSIOF1_SS1_MARK, CAN_TXCLK_MARK,
+        SSI_SCK4_MARK, STP_ISD_0_MARK, SCIFB0_CTS_N_MARK,
+        MSIOF1_SS2_MARK, SSI_SCK5_C_MARK, CAN_DEBUGOUT0_MARK,
+        SSI_WS4_MARK, STP_ISEN_0_MARK, SCIFB0_RTS_N_MARK,
+        MSIOF1_TXD_MARK, SSI_WS5_C_MARK, CAN_DEBUGOUT1_MARK,
+        SSI_SDATA4_MARK, STP_ISSYNC_0_MARK, MSIOF1_RXD_MARK,
+        CAN_DEBUGOUT2_MARK, SSI_SCK5_MARK, SCIFB1_SCK_MARK,
+        IERX_B_MARK, DU2_EXHSYNC_DU2_HSYNC_MARK, QSTH_QHS_MARK,
+        CAN_DEBUGOUT3_MARK, SSI_WS5_MARK, SCIFB1_RXD_MARK,
+        IECLK_B_MARK, DU2_EXVSYNC_DU2_VSYNC_MARK, QSTB_QHE_MARK,
+        CAN_DEBUGOUT4_MARK,
+
+        SSI_SDATA5_MARK, SCIFB1_TXD_MARK, IETX_B_MARK, DU2_DR2_MARK,
+        LCDOUT2_MARK, CAN_DEBUGOUT5_MARK, SSI_SCK6_MARK,
+        SCIFB1_CTS_N_MARK, BPFCLK_D_MARK, RDS_CLK_C_MARK,
+        DU2_DR3_MARK, LCDOUT3_MARK, CAN_DEBUGOUT6_MARK,
+        BPFCLK_F_MARK, RDS_CLK_E_MARK, SSI_WS6_MARK,
+        SCIFB1_RTS_N_MARK, CAN0_TX_D_MARK, DU2_DR4_MARK,
+        LCDOUT4_MARK, CAN_DEBUGOUT7_MARK, SSI_SDATA6_MARK,
+        FMIN_D_MARK, RDS_DATA_C_MARK, DU2_DR5_MARK, LCDOUT5_MARK,
+        CAN_DEBUGOUT8_MARK, SSI_SCK78_MARK, STP_IVCXO27_1_MARK,
+        SCK1_MARK, SCIFA1_SCK_MARK, DU2_DR6_MARK, LCDOUT6_MARK,
+        CAN_DEBUGOUT9_MARK, SSI_WS78_MARK, STP_ISCLK_1_MARK,
+        SCIFB2_SCK_MARK, SCIFA2_CTS_N_MARK, DU2_DR7_MARK,
+        LCDOUT7_MARK, CAN_DEBUGOUT10_MARK, SSI_SDATA7_MARK,
+        STP_ISD_1_MARK, SCIFB2_RXD_MARK, SCIFA2_RTS_N_MARK,
+        TCLK2_MARK, QSTVA_QVS_MARK, CAN_DEBUGOUT11_MARK,
+        BPFCLK_E_MARK, RDS_CLK_D_MARK, SSI_SDATA7_B_MARK,
+        FMIN_G_MARK, RDS_DATA_F_MARK, SSI_SDATA8_MARK,
+        STP_ISEN_1_MARK, SCIFB2_TXD_MARK, CAN0_TX_C_MARK,
+        CAN_DEBUGOUT12_MARK, SSI_SDATA8_B_MARK, SSI_SDATA9_MARK,
+        STP_ISSYNC_1_MARK, SCIFB2_CTS_N_MARK, SSI_WS1_MARK,
+        SSI_SDATA5_C_MARK, CAN_DEBUGOUT13_MARK, AUDIO_CLKA_MARK,
+        SCIFB2_RTS_N_MARK, CAN_DEBUGOUT14_MARK,
+
+        AUDIO_CLKB_MARK, SCIF_CLK_MARK, CAN0_RX_D_MARK,
+        DVC_MUTE_MARK, CAN0_RX_C_MARK, CAN_DEBUGOUT15_MARK,
+        REMOCON_MARK, SCIFA0_SCK_MARK, HSCK1_MARK, SCK0_MARK,
+        MSIOF3_SS2_MARK, DU2_DG2_MARK, LCDOUT10_MARK, SDA1_C_MARK,
+        SDA1_CIS_C_MARK, SCIFA0_RXD_MARK, HRX1_MARK, RX0_MARK,
+        DU2_DR0_MARK, LCDOUT0_MARK, SCIFA0_TXD_MARK, HTX1_MARK,
+        TX0_MARK, DU2_DR1_MARK, LCDOUT1_MARK, SCIFA0_CTS_N_MARK,
+        HCTS1_N_MARK, CTS0_N_MARK, MSIOF3_SYNC_MARK, DU2_DG3_MARK,
+        LCDOUT11_MARK, PWM0_B_MARK, SCL1_C_MARK, SCL1_CIS_C_MARK,
+        SCIFA0_RTS_N_MARK, HRTS1_N_MARK, RTS0_N_TANS_MARK,
+        MSIOF3_SS1_MARK, DU2_DG0_MARK, LCDOUT8_MARK, PWM1_B_MARK,
+        SCIFA1_RXD_MARK, AD_DI_MARK, RX1_MARK,
+        DU2_EXODDF_DU2_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
+        SCIFA1_TXD_MARK, AD_DO_MARK, TX1_MARK, DU2_DG1_MARK,
+        LCDOUT9_MARK, SCIFA1_CTS_N_MARK, AD_CLK_MARK,
+        CTS1_N_MARK, MSIOF3_RXD_MARK, DU0_DOTCLKOUT_MARK, QCLK_MARK,
+        SCIFA1_RTS_N_MARK, AD_NCS_N_MARK, RTS1_N_TANS_MARK,
+        MSIOF3_TXD_MARK, DU1_DOTCLKOUT_MARK, QSTVB_QVE_MARK,
+        HRTS0_N_C_MARK,
+
+        SCIFA2_SCK_MARK, FMCLK_MARK, MSIOF3_SCK_MARK, DU2_DG7_MARK,
+        LCDOUT15_MARK, SCIF_CLK_B_MARK, SCIFA2_RXD_MARK, FMIN_MARK,
+        DU2_DB0_MARK, LCDOUT16_MARK, SCL2_MARK, SCL2_CIS_MARK,
+        SCIFA2_TXD_MARK, BPFCLK_MARK, DU2_DB1_MARK, LCDOUT17_MARK,
+        SDA2_MARK, SDA2_CIS_MARK, HSCK0_MARK, TS_SDEN0_MARK,
+        DU2_DG4_MARK, LCDOUT12_MARK, HCTS0_N_C_MARK, HRX0_MARK,
+        DU2_DB2_MARK, LCDOUT18_MARK, HTX0_MARK, DU2_DB3_MARK,
+        LCDOUT19_MARK, HCTS0_N_MARK, SSI_SCK9_MARK, DU2_DB4_MARK,
+        LCDOUT20_MARK, HRTS0_N_MARK, SSI_WS9_MARK, DU2_DB5_MARK,
+        LCDOUT21_MARK, MSIOF0_SCK_MARK, TS_SDAT0_MARK, ADICLK_MARK,
+        DU2_DB6_MARK, LCDOUT22_MARK, MSIOF0_SYNC_MARK, TS_SCK0_MARK,
+        SSI_SCK2_MARK, ADIDATA_MARK, DU2_DB7_MARK, LCDOUT23_MARK,
+        SCIFA2_RXD_B_MARK, MSIOF0_SS1_MARK, ADICHS0_MARK,
+        DU2_DG5_MARK, LCDOUT13_MARK, MSIOF0_TXD_MARK, ADICHS1_MARK,
+        DU2_DG6_MARK, LCDOUT14_MARK,
+
+        MSIOF0_SS2_MARK, AUDIO_CLKOUT_MARK, ADICHS2_MARK,
+        DU2_DISP_MARK, QPOLA_MARK, HTX0_C_MARK, SCIFA2_TXD_B_MARK,
+        MSIOF0_RXD_MARK, TS_SPSYNC0_MARK, SSI_WS2_MARK,
+        ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, HRX0_C_MARK,
+        USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
+        TCLK1_B_MARK,
+        PINMUX_MARK_END,
+};
+
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
+
+        PINMUX_DATA(VI1_DATA7_VI1_B7_MARK, FN_VI1_DATA7_VI1_B7),
+        PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
+        PINMUX_DATA(USB0_OVC_VBUS_MARK, FN_USB0_OVC_VBUS),
+        PINMUX_DATA(USB2_PWEN_MARK, FN_USB2_PWEN),
+        PINMUX_DATA(USB2_OVC_MARK, FN_USB2_OVC),
+        PINMUX_DATA(AVS1_MARK, FN_AVS1),
+        PINMUX_DATA(AVS2_MARK, FN_AVS2),
+        PINMUX_DATA(DU_DOTCLKIN0_MARK, FN_DU_DOTCLKIN0),
+        PINMUX_DATA(DU_DOTCLKIN2_MARK, FN_DU_DOTCLKIN2),
+
+        PINMUX_IPSR_DATA(IP0_2_0, D0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, MSIOF3_SCK_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI3_DATA0, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_2_0, VI0_G4_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_5_3, D1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, MSIOF3_SYNC_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI3_DATA1, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_5_3, VI0_G5_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_8_6, D2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, MSIOF3_RXD_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI3_DATA2, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_8_6, VI0_G6_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_11_9, D3),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, MSIOF3_TXD_B, SEL_SOF3_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI3_DATA3, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_11_9, VI0_G7_B, SEL_VI0_1),
+        PINMUX_IPSR_DATA(IP0_15_12, D4),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB1_RXD_F, SEL_SCIFB1_5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, SCIFB0_RXD_C, SEL_SCIFB_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI3_DATA4, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, VI0_R0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_15_12, RX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_19_16, D5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB1_TXD_F, SEL_SCIFB1_5),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, SCIFB0_TXD_C, SEL_SCIFB_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI3_DATA5, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, VI0_R1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_19_16, TX0_B, SEL_SCIF0_1),
+        PINMUX_IPSR_DATA(IP0_22_20, D6),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_C, SEL_IIC2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI3_DATA6, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, VI0_R2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_22_20, SCL2_CIS_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP0_26_23, D7),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, AD_DI_B, SEL_ADI_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_C, SEL_IIC2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI3_DATA7, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, VI0_R3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_26_23, SDA2_CIS_C, SEL_I2C2_2),
+        PINMUX_IPSR_DATA(IP0_30_27, D8),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, SCIFA1_SCK_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP0_30_27, AVB_TXD0),
+        PINMUX_IPSR_DATA(IP0_30_27, MII_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI0_G0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP0_30_27, VI2_DATA0_VI2_B0, SEL_VI2_0),
+
+        PINMUX_IPSR_DATA(IP1_3_0, D9),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, SCIFA1_RXD_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_3_0, AVB_TXD1),
+        PINMUX_IPSR_DATA(IP1_3_0, MII_TXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI0_G1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_3_0, VI2_DATA1_VI2_B1, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_7_4, D10),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, SCIFA1_TXD_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_7_4, AVB_TXD2),
+        PINMUX_IPSR_DATA(IP1_7_4, MII_TXD2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI0_G2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_7_4, VI2_DATA2_VI2_B2, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_11_8, D11),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, SCIFA1_CTS_N_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_11_8, AVB_TXD3),
+        PINMUX_IPSR_DATA(IP1_11_8, MII_TXD3),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI0_G3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_11_8, VI2_DATA3_VI2_B3, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_14_12, D12),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, SCIFA1_RTS_N_C, SEL_SCIFA1_2),
+        PINMUX_IPSR_DATA(IP1_14_12, AVB_TXD4),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI0_HSYNC_N_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_14_12, VI2_DATA4_VI2_B4, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_17_15, D13),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, AVB_TXD5, SEL_SCIFA1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI0_VSYNC_N_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_17_15, VI2_DATA5_VI2_B5, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_21_18, D14),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, SCIFB1_RXD_C, SEL_SCIFB1_2),
+        PINMUX_IPSR_DATA(IP1_21_18, AVB_TXD6),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, RX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI0_CLKENB_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_21_18, VI2_DATA6_VI2_B6, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_25_22, D15),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, SCIFB1_TXD_C, SEL_SCIFB1_2),
+        PINMUX_IPSR_DATA(IP1_25_22, AVB_TXD7),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, TX1_B, SEL_SCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI0_FIELD_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP1_25_22, VI2_DATA7_VI2_B7, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP1_27_26, A0),
+        PINMUX_IPSR_DATA(IP1_27_26, PWM3),
+        PINMUX_IPSR_DATA(IP1_29_28, A1),
+        PINMUX_IPSR_DATA(IP1_29_28, PWM4),
+
+        PINMUX_IPSR_DATA(IP2_2_0, A2),
+        PINMUX_IPSR_DATA(IP2_2_0, PWM5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_2_0, MSIOF1_SS1_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_5_3, A3),
+        PINMUX_IPSR_DATA(IP2_5_3, PWM6),
+        PINMUX_IPSR_MODSEL_DATA(IP2_5_3, MSIOF1_SS2_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_8_6, A4),
+        PINMUX_IPSR_MODSEL_DATA(IP2_8_6, MSIOF1_TXD_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP2_8_6, TPU0TO0),
+        PINMUX_IPSR_DATA(IP2_11_9, A5),
+        PINMUX_IPSR_MODSEL_DATA(IP2_11_9, SCIFA1_TXD_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_11_9, TPU0TO1),
+        PINMUX_IPSR_DATA(IP2_14_12, A6),
+        PINMUX_IPSR_MODSEL_DATA(IP2_14_12, SCIFA1_RTS_N_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_14_12, TPU0TO2),
+        PINMUX_IPSR_DATA(IP2_17_15, A7),
+        PINMUX_IPSR_MODSEL_DATA(IP2_17_15, SCIFA1_SCK_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_DATA(IP2_17_15, AUDIO_CLKOUT_B),
+        PINMUX_IPSR_DATA(IP2_17_15, TPU0TO3),
+        PINMUX_IPSR_DATA(IP2_21_18, A8),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFA1_RXD_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SSI_SCK5_B, SEL_SSI5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI0_R4_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, SCIFB2_RXD_C, SEL_SCIFB2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_21_18, VI2_DATA0_VI2_B0_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP2_25_22, A9),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFA1_CTS_N_B, SEL_SCIFA1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SSI_WS5_B, SEL_SSI5_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI0_R5_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, SCIFB2_TXD_C, SEL_SCIFB2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP2_25_22, VI2_DATA1_VI2_B1_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP2_28_26, A10),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, SSI_SDATA5_B, SEL_SSI5_1),
+        PINMUX_IPSR_DATA(IP2_28_26, MSIOF2_SYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI0_R6_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP2_28_26, VI2_DATA2_VI2_B2_B, SEL_VI2_1),
+
+        PINMUX_IPSR_DATA(IP3_3_0, A11),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_3_0, MSIOF2_SCK),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_3_0, VI1_R0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_3_0, VI2_G0),
+        PINMUX_IPSR_DATA(IP3_3_0, VI2_DATA3_VI2_B3_B),
+        PINMUX_IPSR_DATA(IP3_7_4, A12),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_7_4, MSIOF2_TXD),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_7_4, VI1_R1_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_7_4, VI2_G1),
+        PINMUX_IPSR_DATA(IP3_7_4, VI2_DATA4_VI2_B4_B),
+        PINMUX_IPSR_DATA(IP3_11_8, A13),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_11_8, EX_WAIT2),
+        PINMUX_IPSR_DATA(IP3_11_8, MSIOF2_RXD),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI1_R2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_11_8, VI2_G2),
+        PINMUX_IPSR_MODSEL_DATA(IP3_11_8, VI2_DATA5_VI2_B5_B, SEL_VI2_0),
+        PINMUX_IPSR_DATA(IP3_14_12, A14),
+        PINMUX_IPSR_MODSEL_DATA(IP3_14_12, SCIFB2_TXD_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_14_12, ATACS11_N),
+        PINMUX_IPSR_DATA(IP3_14_12, MSIOF2_SS1),
+        PINMUX_IPSR_DATA(IP3_17_15, A15),
+        PINMUX_IPSR_MODSEL_DATA(IP3_17_15, SCIFB2_SCK_B, SEL_SCIFB2_1),
+        PINMUX_IPSR_DATA(IP3_17_15, ATARD1_N),
+        PINMUX_IPSR_DATA(IP3_17_15, MSIOF2_SS2),
+        PINMUX_IPSR_DATA(IP3_19_18, A16),
+        PINMUX_IPSR_DATA(IP3_19_18, ATAWR1_N),
+        PINMUX_IPSR_DATA(IP3_22_20, A17),
+        PINMUX_IPSR_MODSEL_DATA(IP3_22_20, AD_DO_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_22_20, ATADIR1_N),
+        PINMUX_IPSR_DATA(IP3_25_23, A18),
+        PINMUX_IPSR_MODSEL_DATA(IP3_25_23, AD_CLK_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_25_23, ATAG1_N),
+        PINMUX_IPSR_DATA(IP3_28_26, A19),
+        PINMUX_IPSR_MODSEL_DATA(IP3_28_26, AD_NCS_N_B, SEL_ADI_1),
+        PINMUX_IPSR_DATA(IP3_28_26, ATACS01_N),
+        PINMUX_IPSR_MODSEL_DATA(IP3_28_26, EX_WAIT0_B, SEL_LBS_1),
+        PINMUX_IPSR_DATA(IP3_31_29, A20),
+        PINMUX_IPSR_DATA(IP3_31_29, SPCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP3_31_29, VI1_R3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP3_31_29, VI2_G4),
+
+        PINMUX_IPSR_DATA(IP4_2_0, A21),
+        PINMUX_IPSR_DATA(IP4_2_0, MOSI_IO0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_2_0, VI1_R4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_2_0, VI2_G5),
+        PINMUX_IPSR_DATA(IP4_5_3, A22),
+        PINMUX_IPSR_DATA(IP4_5_3, MISO_IO1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_5_3, VI1_R5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_5_3, VI2_G6),
+        PINMUX_IPSR_DATA(IP4_8_6, A23),
+        PINMUX_IPSR_DATA(IP4_8_6, IO2),
+        PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_8_6, VI1_G7_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_8_6, VI2_G7),
+        PINMUX_IPSR_DATA(IP4_11_9, A24),
+        PINMUX_IPSR_DATA(IP4_11_9, IO3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI1_R7_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_11_9, VI2_CLKENB_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_14_12, A25),
+        PINMUX_IPSR_DATA(IP4_14_12, SSL),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI1_G6_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_14_12, VI2_FIELD_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_17_15, CS0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, VI1_R6_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_17_15, VI2_G3),
+        PINMUX_IPSR_MODSEL_DATA(IP4_17_15, MSIOF0_SS2_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP4_20_18, CS1_N_A26),
+        PINMUX_IPSR_DATA(IP4_20_18, SPEEDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7, SEL_VI0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI0_R7_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_20_18, VI2_CLK_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP4_23_21, EX_CS0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HRX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, VI1_G5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_23_21, VI2_R0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, HTX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_23_21, MSIOF0_SS1_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP4_26_24, EX_CS1_N),
+        PINMUX_IPSR_DATA(IP4_26_24, GPS_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, HCTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_26_24, VI1_FIELD_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_26_24, VI2_R1),
+        PINMUX_IPSR_DATA(IP4_29_27, EX_CS2_N),
+        PINMUX_IPSR_DATA(IP4_29_27, GPS_SIGN),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, HRTS1_N_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_DATA(IP4_29_27, VI3_CLKENB),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP4_29_27, VI1_G0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP4_29_27, VI2_R2),
+
+        PINMUX_IPSR_DATA(IP5_2_0, EX_CS3_N),
+        PINMUX_IPSR_DATA(IP5_2_0, GPS_MAG),
+        PINMUX_IPSR_DATA(IP5_2_0, VI3_FIELD),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_2_0, VI1_G1_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_2_0, VI2_R3),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, EX_CS4_N, SEL_I2C1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_SCK_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP5_5_3, VI3_HSYNC_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1, SEL_IIC1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, VI2_HSYNC_N_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP5_5_3, INTC_EN0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_5_3, SCL1_CIS, SEL_I2C1_0),
+        PINMUX_IPSR_DATA(IP5_9_6, EX_CS5_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, CAN0_RX, SEL_CAN0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, MSIOF1_RXD_B, SEL_SOF1_1),
+        PINMUX_IPSR_DATA(IP5_9_6, VI3_VSYNC_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, VI1_G2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_9_6, VI2_R4),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1, SEL_IIC1_0),
+        PINMUX_IPSR_DATA(IP5_9_6, INTC_EN1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_9_6, SDA1_CIS, SEL_I2C1_0),
+        PINMUX_IPSR_DATA(IP5_12_10, BS_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, HTX1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, CAN1_TX, SEL_CAN1_0),
+        PINMUX_IPSR_DATA(IP5_12_10, DRACK0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_12_10, IETX_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP5_14_13, RD_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_14_13, CAN0_TX, SEL_CAN0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_14_13, SCIFA0_SCK_B, SEL_SCFA_1),
+        PINMUX_IPSR_DATA(IP5_17_15, RD_WR_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, VI1_G3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_17_15, VI2_R5),
+        PINMUX_IPSR_MODSEL_DATA(IP5_17_15, SCIFA0_RXD_B, SEL_SCFA_1),
+        PINMUX_IPSR_DATA(IP5_17_15, INTC_IRQ4_N),
+        PINMUX_IPSR_DATA(IP5_20_18, WE0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, IECLK, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, CAN_CLK, SEL_CANCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N, SEL_VI2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, SCIFA0_TXD_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_20_18, VI2_VSYNC_N_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP5_23_21, WE1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX, SEL_IEB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, CAN1_RX, SEL_CAN1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, VI1_G4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_23_21, VI2_R6),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, SCIFA0_CTS_N_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_23_21, IERX_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP5_26_24, EX_WAIT0),
+        PINMUX_IPSR_DATA(IP5_26_24, IRQ3),
+        PINMUX_IPSR_DATA(IP5_26_24, INTC_IRQ3_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, VI3_CLK, SEL_VI3_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, SCIFA0_RTS_N_B, SEL_SCFA_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, HRX0_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP5_26_24, MSIOF0_SCK_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP5_29_27, DREQ0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, VI1_HSYNC_N_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP5_29_27, VI2_R7),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_SCK78_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP5_29_27, SSI_WS78_B, SEL_SSI7_1),
+
+        PINMUX_IPSR_DATA(IP6_2_0, DACK0),
+        PINMUX_IPSR_DATA(IP6_2_0, IRQ0),
+        PINMUX_IPSR_DATA(IP6_2_0, INTC_IRQ0_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_SCK6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, VI1_VSYNC_N_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SSI_WS78_C, SEL_SSI7_2),
+        PINMUX_IPSR_DATA(IP6_5_3, DREQ1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, VI1_CLKENB_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SDATA7_C, SEL_SSI7_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SSI_SCK78_B, SEL_SSI7_1),
+        PINMUX_IPSR_DATA(IP6_8_6, DACK1),
+        PINMUX_IPSR_DATA(IP6_8_6, IRQ1),
+        PINMUX_IPSR_DATA(IP6_8_6, INTC_IRQ1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_WS6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_8_6, SSI_SDATA8_C, SEL_SSI8_2),
+        PINMUX_IPSR_DATA(IP6_10_9, DREQ2_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HSCK1_B, SEL_HSCIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, HCTS0_N_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_10_9, MSIOF0_TXD_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP6_13_11, DACK2),
+        PINMUX_IPSR_DATA(IP6_13_11, IRQ2),
+        PINMUX_IPSR_DATA(IP6_13_11, INTC_IRQ2_N),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, SSI_SDATA6_B, SEL_SSI6_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, HRTS0_N_B, SEL_HSCIF0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_13_11, MSIOF0_RXD_B, SEL_SOF0_1),
+        PINMUX_IPSR_DATA(IP6_16_14, ETH_CRS_DV),
+        PINMUX_IPSR_DATA(IP6_16_14, RMII_CRS_DV),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, STP_ISCLK_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, TS_SDEN0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, GLO_Q0_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_E, SEL_IIC2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_16_14, SCL2_CIS_E, SEL_I2C2_4),
+        PINMUX_IPSR_DATA(IP6_19_17, ETH_RX_ER),
+        PINMUX_IPSR_DATA(IP6_19_17, RMII_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, STP_ISD_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, TS_SPSYNC0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, GLO_Q1_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_E, SEL_IIC2_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_19_17, SDA2_CIS_E, SEL_I2C2_4),
+        PINMUX_IPSR_DATA(IP6_22_20, ETH_RXD0),
+        PINMUX_IPSR_DATA(IP6_22_20, RMII_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, STP_ISEN_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, TS_SDAT0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, GLO_I0_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCIFB1_SCK_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_22_20, SCK1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_25_23, ETH_RXD1),
+        PINMUX_IPSR_DATA(IP6_25_23, RMII_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, HRX0_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, STP_ISSYNC_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, TS_SCK0_D, SEL_TSIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, GLO_I1_C, SEL_GPS_2),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, SCIFB1_RXD_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_25_23, RX1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_28_26, ETH_LINK),
+        PINMUX_IPSR_DATA(IP6_28_26, RMII_LINK),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, HTX0_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, STP_IVCXO27_0_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, SCIFB1_TXD_G, SEL_SCIFB1_6),
+        PINMUX_IPSR_MODSEL_DATA(IP6_28_26, TX1_E, SEL_SCIF1_4),
+        PINMUX_IPSR_DATA(IP6_31_29, ETH_REF_CLK),
+        PINMUX_IPSR_DATA(IP6_31_29, RMII_REF_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HCTS0_N_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, STP_IVCXO27_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP6_31_29, HRX0_F, SEL_HSCIF0_5),
+
+        PINMUX_IPSR_DATA(IP7_2_0, ETH_MDIO),
+        PINMUX_IPSR_DATA(IP7_2_0, RMII_MDIO),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HRTS0_N_E, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SIM0_D_C, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_2_0, HCTS0_N_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_5_3, ETH_TXD1),
+        PINMUX_IPSR_DATA(IP7_5_3, RMII_TXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, HTX0_F, SEL_HSCIF0_4),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, BPFCLK_G, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_5_3, RDS_CLK_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_7_6, ETH_TX_EN),
+        PINMUX_IPSR_DATA(IP7_7_6, RMII_TX_EN),
+        PINMUX_IPSR_MODSEL_DATA(IP7_7_6, SIM0_CLK_C, SEL_SIM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_7_6, HRTS0_N_F, SEL_HSCIF0_5),
+        PINMUX_IPSR_DATA(IP7_9_8, ETH_MAGIC),
+        PINMUX_IPSR_DATA(IP7_9_8, RMII_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP7_9_8, SIM0_RST_C, SEL_SIM_2),
+        PINMUX_IPSR_DATA(IP7_12_10, ETH_TXD0),
+        PINMUX_IPSR_DATA(IP7_12_10, RMII_TXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, STP_ISCLK_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, TS_SDEN1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_12_10, GLO_SCLK_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_15_13, ETH_MDC),
+        PINMUX_IPSR_DATA(IP7_15_13, RMII_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, STP_ISD_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, TS_SPSYNC1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_15_13, GLO_SDATA_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_18_16, PWM0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, SCIFA2_SCK_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, STP_ISEN_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, TS_SDAT1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_18_16, GLO_SS_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_21_19, PWM1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, SCIFA2_TXD_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, STP_ISSYNC_1_B, SEL_SSP_1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, TS_SCK1_C, SEL_TSIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP7_21_19, GLO_RFON_C, SEL_GPS_2),
+        PINMUX_IPSR_DATA(IP7_21_19, PCMOE_N),
+        PINMUX_IPSR_DATA(IP7_24_22, PWM2),
+        PINMUX_IPSR_DATA(IP7_24_22, PWMFSW0),
+        PINMUX_IPSR_MODSEL_DATA(IP7_24_22, SCIFA2_RXD_C, SEL_SCIFA2_2),
+        PINMUX_IPSR_DATA(IP7_24_22, PCMWE_N),
+        PINMUX_IPSR_MODSEL_DATA(IP7_24_22, IECLK_C, SEL_IEB_2),
+        PINMUX_IPSR_DATA(IP7_26_25, DU1_DOTCLKIN),
+        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKC),
+        PINMUX_IPSR_DATA(IP7_26_25, AUDIO_CLKOUT_C),
+        PINMUX_IPSR_MODSEL_DATA(IP7_28_27, VI0_CLK, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP7_28_27, ATACS00_N),
+        PINMUX_IPSR_DATA(IP7_28_27, AVB_RXD1),
+        PINMUX_IPSR_DATA(IP7_28_27, MII_RXD1),
+        PINMUX_IPSR_MODSEL_DATA(IP7_30_29, VI0_DATA0_VI0_B0, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP7_30_29, ATACS10_N),
+        PINMUX_IPSR_DATA(IP7_30_29, AVB_RXD2),
+        PINMUX_IPSR_DATA(IP7_30_29, MII_RXD2),
+
+        PINMUX_IPSR_MODSEL_DATA(IP8_1_0, VI0_DATA1_VI0_B1, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_1_0, ATARD0_N),
+        PINMUX_IPSR_DATA(IP8_1_0, AVB_RXD3),
+        PINMUX_IPSR_DATA(IP8_1_0, MII_RXD3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_3_2, VI0_DATA2_VI0_B2, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_3_2, ATAWR0_N),
+        PINMUX_IPSR_DATA(IP8_3_2, AVB_RXD4),
+        PINMUX_IPSR_MODSEL_DATA(IP8_5_4, VI0_DATA3_VI0_B3, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_5_4, ATADIR0_N),
+        PINMUX_IPSR_DATA(IP8_5_4, AVB_RXD5),
+        PINMUX_IPSR_MODSEL_DATA(IP8_7_6, VI0_DATA4_VI0_B4, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_7_6, ATAG0_N),
+        PINMUX_IPSR_DATA(IP8_7_6, AVB_RXD6),
+        PINMUX_IPSR_MODSEL_DATA(IP8_9_8, VI0_DATA5_VI0_B5, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_9_8, EX_WAIT1),
+        PINMUX_IPSR_DATA(IP8_9_8, AVB_RXD7),
+        PINMUX_IPSR_MODSEL_DATA(IP8_11_10, VI0_DATA6_VI0_B6, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_11_10, AVB_RX_ER),
+        PINMUX_IPSR_DATA(IP8_11_10, MII_RX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP8_13_12, VI0_DATA7_VI0_B7, SEL_VI0_0),
+        PINMUX_IPSR_DATA(IP8_13_12, AVB_RX_CLK),
+        PINMUX_IPSR_DATA(IP8_13_12, MII_RX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_15_14, VI1_CLK, SEL_VI1_0),
+        PINMUX_IPSR_DATA(IP8_15_14, AVB_RX_DV),
+        PINMUX_IPSR_DATA(IP8_15_14, MII_RX_DV),
+        PINMUX_IPSR_MODSEL_DATA(IP8_17_16, VI1_DATA0_VI1_B0, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_17_16, SCIFA1_SCK_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_17_16, AVB_CRS),
+        PINMUX_IPSR_DATA(IP8_17_16, MII_CRS),
+        PINMUX_IPSR_MODSEL_DATA(IP8_19_18, VI1_DATA1_VI1_B1, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_19_18, SCIFA1_RXD_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_19_18, AVB_MDC),
+        PINMUX_IPSR_DATA(IP8_19_18, MII_MDC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_21_20, VI1_DATA2_VI1_B2, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_21_20, SCIFA1_TXD_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_21_20, AVB_MDIO),
+        PINMUX_IPSR_DATA(IP8_21_20, MII_MDIO),
+        PINMUX_IPSR_MODSEL_DATA(IP8_23_22, VI1_DATA3_VI1_B3, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_23_22, SCIFA1_CTS_N_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_23_22, AVB_GTX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_DATA4_VI1_B4, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_25_24, SCIFA1_RTS_N_D, SEL_SCIFA1_3),
+        PINMUX_IPSR_DATA(IP8_25_24, AVB_MAGIC),
+        PINMUX_IPSR_DATA(IP8_25_24, MII_MAGIC),
+        PINMUX_IPSR_MODSEL_DATA(IP8_26, VI1_DATA5_VI1_B5, SEL_VI1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP8_26, AVB_PHY_INT, SEL_SCIFA1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP8_27, VI1_DATA6_VI1_B6, SEL_VI1_0),
+        PINMUX_IPSR_DATA(IP8_27, AVB_GTXREFCLK),
+        PINMUX_IPSR_DATA(IP8_28, SD0_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP8_28, VI1_DATA0_VI1_B0_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP8_30_29, SD0_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_29, SCIFB1_SCK_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP8_30_29, VI1_DATA1_VI1_B1_B, SEL_VI1_1),
+
+        PINMUX_IPSR_DATA(IP9_1_0, SD0_DAT0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, SCIFB1_RXD_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_1_0, VI1_DATA2_VI1_B2_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_3_2, SD0_DAT1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, SCIFB1_TXD_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_3_2, VI1_DATA3_VI1_B3_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_5_4, SD0_DAT2),
+        PINMUX_IPSR_MODSEL_DATA(IP9_5_4, SCIFB1_CTS_N_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_5_4, VI1_DATA4_VI1_B4_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_7_6, SD0_DAT3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_7_6, SCIFB1_RTS_N_B, SEL_SCIFB1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_7_6, VI1_DATA5_VI1_B5_B, SEL_VI1_1),
+        PINMUX_IPSR_DATA(IP9_11_8, SD0_CD),
+        PINMUX_IPSR_DATA(IP9_11_8, MMC0_D6),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, TS_SDEN0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP9_11_8, USB0_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, GLO_SCLK, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI1_DATA6_VI1_B6_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_B, SEL_IIC1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, SCL1_CIS_B, SEL_I2C1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_11_8, VI2_DATA6_VI2_B6_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP9_15_12, SD0_WP),
+        PINMUX_IPSR_DATA(IP9_15_12, MMC0_D7),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, TS_SPSYNC0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP9_15_12, USB0_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, GLO_SDATA, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI1_DATA7_VI1_B7_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_B, SEL_IIC1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, SDA1_CIS_B, SEL_I2C1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_15_12, VI2_DATA7_VI2_B7_B, SEL_VI2_1),
+        PINMUX_IPSR_DATA(IP9_17_16, SD1_CLK),
+        PINMUX_IPSR_DATA(IP9_17_16, AVB_TX_EN),
+        PINMUX_IPSR_DATA(IP9_17_16, MII_TX_EN),
+        PINMUX_IPSR_DATA(IP9_19_18, SD1_CMD),
+        PINMUX_IPSR_DATA(IP9_19_18, AVB_TX_ER),
+        PINMUX_IPSR_DATA(IP9_19_18, MII_TX_ER),
+        PINMUX_IPSR_MODSEL_DATA(IP9_19_18, SCIFB0_SCK_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_21_20, SD1_DAT0),
+        PINMUX_IPSR_DATA(IP9_21_20, AVB_TX_CLK),
+        PINMUX_IPSR_DATA(IP9_21_20, MII_TX_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP9_21_20, SCIFB0_RXD_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_23_22, SD1_DAT1),
+        PINMUX_IPSR_DATA(IP9_23_22, AVB_LINK),
+        PINMUX_IPSR_DATA(IP9_23_22, MII_LINK),
+        PINMUX_IPSR_MODSEL_DATA(IP9_23_22, SCIFB0_TXD_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_25_24, SD1_DAT2),
+        PINMUX_IPSR_DATA(IP9_25_24, AVB_COL),
+        PINMUX_IPSR_DATA(IP9_25_24, MII_COL),
+        PINMUX_IPSR_MODSEL_DATA(IP9_25_24, SCIFB0_CTS_N_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_27_26, SD1_DAT3),
+        PINMUX_IPSR_DATA(IP9_27_26, AVB_RXD0),
+        PINMUX_IPSR_DATA(IP9_27_26, MII_RXD0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_27_26, SCIFB0_RTS_N_B, SEL_SCIFB_1),
+        PINMUX_IPSR_DATA(IP9_31_28, SD1_CD),
+        PINMUX_IPSR_DATA(IP9_31_28, MMC1_D6),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, TS_SDEN1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP9_31_28, USB1_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, GLO_SS, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI0_CLK_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_D, SEL_IIC2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SCL2_CIS_D, SEL_I2C2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, SIM0_CLK_B, SEL_SIM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP9_31_28, VI3_CLK_B, SEL_VI3_1),
+
+        PINMUX_IPSR_DATA(IP10_3_0, SD1_WP),
+        PINMUX_IPSR_DATA(IP10_3_0, MMC1_D7),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, TS_SPSYNC1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP10_3_0, USB1_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, GLO_RFON, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, VI1_CLK_B, SEL_VI1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_D, SEL_IIC2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SDA2_CIS_D, SEL_I2C2_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_3_0, SIM0_D_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP10_6_4, SD2_CLK),
+        PINMUX_IPSR_DATA(IP10_6_4, MMC0_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, SIM0_CLK, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI0_DATA0_VI0_B0_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, TS_SDEN0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, GLO_SCLK_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_6_4, VI3_DATA0_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_10_7, SD2_CMD),
+        PINMUX_IPSR_DATA(IP10_10_7, MMC0_CMD),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SIM0_D, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI0_DATA1_VI0_B1_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCIFB1_SCK_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, SCK1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, TS_SPSYNC0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, GLO_SDATA_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_10_7, VI3_DATA1_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_14_11, SD2_DAT0),
+        PINMUX_IPSR_DATA(IP10_14_11, MMC0_D0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, FMCLK_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI0_DATA2_VI0_B2_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, SCIFB1_RXD_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, RX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, TS_SDAT0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, GLO_SS_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_14_11, VI3_DATA2_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_18_15, SD2_DAT1),
+        PINMUX_IPSR_DATA(IP10_18_15, MMC0_D1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, FMIN_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, RDS_DATA, SEL_RDS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI0_DATA3_VI0_B3_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, SCIFB1_TXD_E, SEL_SCIFB1_4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TX1_D, SEL_SCIF1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, TS_SCK0_C, SEL_TSIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, GLO_RFON_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_18_15, VI3_DATA3_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_22_19, SD2_DAT2),
+        PINMUX_IPSR_DATA(IP10_22_19, MMC0_D2),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, BPFCLK_B, SEL_FM_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, RDS_CLK, SEL_RDS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI0_DATA4_VI0_B4_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, HRX0_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, TS_SDEN1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, GLO_Q0_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_22_19, VI3_DATA4_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_25_23, SD2_DAT3),
+        PINMUX_IPSR_DATA(IP10_25_23, MMC0_D3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, SIM0_RST, SEL_SIM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI0_DATA5_VI0_B5_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, HTX0_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, TS_SPSYNC1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, GLO_Q1_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_25_23, VI3_DATA5_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP10_29_26, SD2_CD),
+        PINMUX_IPSR_DATA(IP10_29_26, MMC0_D4),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP10_29_26, USB2_EXTP),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI0_DATA6_VI0_B6_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, HCTS0_N_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, TS_SDAT1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, GLO_I0_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP10_29_26, VI3_DATA6_B, SEL_VI3_1),
+
+        PINMUX_IPSR_DATA(IP11_3_0, SD2_WP),
+        PINMUX_IPSR_DATA(IP11_3_0, MMC0_D5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK0_B, SEL_TSIF0_1),
+        PINMUX_IPSR_DATA(IP11_3_0, USB2_IDIN),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI0_DATA7_VI0_B7_B, SEL_VI0_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, HRTS0_N_D, SEL_HSCIF0_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, TS_SCK1_B, SEL_TSIF1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, GLO_I1_B, SEL_GPS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_3_0, VI3_DATA7_B, SEL_VI3_1),
+        PINMUX_IPSR_DATA(IP11_4, SD3_CLK),
+        PINMUX_IPSR_DATA(IP11_4, MMC1_CLK),
+        PINMUX_IPSR_DATA(IP11_6_5, SD3_CMD),
+        PINMUX_IPSR_DATA(IP11_6_5, MMC1_CMD),
+        PINMUX_IPSR_DATA(IP11_6_5, MTS_N),
+        PINMUX_IPSR_DATA(IP11_8_7, SD3_DAT0),
+        PINMUX_IPSR_DATA(IP11_8_7, MMC1_D0),
+        PINMUX_IPSR_DATA(IP11_8_7, STM_N),
+        PINMUX_IPSR_DATA(IP11_10_9, SD3_DAT1),
+        PINMUX_IPSR_DATA(IP11_10_9, MMC1_D1),
+        PINMUX_IPSR_DATA(IP11_10_9, MDATA),
+        PINMUX_IPSR_DATA(IP11_12_11, SD3_DAT2),
+        PINMUX_IPSR_DATA(IP11_12_11, MMC1_D2),
+        PINMUX_IPSR_DATA(IP11_12_11, SDATA),
+        PINMUX_IPSR_DATA(IP11_14_13, SD3_DAT3),
+        PINMUX_IPSR_DATA(IP11_14_13, MMC1_D3),
+        PINMUX_IPSR_DATA(IP11_14_13, SCKZ),
+        PINMUX_IPSR_DATA(IP11_17_15, SD3_CD),
+        PINMUX_IPSR_DATA(IP11_17_15, MMC1_D4),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, TS_SDAT1, SEL_TSIF1_0),
+        PINMUX_IPSR_DATA(IP11_17_15, VSP),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, GLO_Q0, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_17_15, SIM0_RST_B, SEL_SIM_1),
+        PINMUX_IPSR_DATA(IP11_21_18, SD3_WP),
+        PINMUX_IPSR_DATA(IP11_21_18, MMC1_D5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, TS_SCK1, SEL_TSIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, GLO_Q1, SEL_GPS_0),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_C, SEL_FM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_B, SEL_RDS_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_E, SEL_FM_4),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_D, SEL_RDS_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, FMIN_F, SEL_FM_5),
+        PINMUX_IPSR_MODSEL_DATA(IP11_21_18, RDS_DATA_E, SEL_RDS_4),
+        PINMUX_IPSR_DATA(IP11_23_22, MLB_CLK),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_B, SEL_IIC2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_23_22, SCL2_CIS_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP11_26_24, MLB_SIG),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SCIFB1_RXD_D, SEL_SCIFB1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, RX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_B, SEL_IIC2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP11_26_24, SDA2_CIS_B, SEL_I2C2_1),
+        PINMUX_IPSR_DATA(IP11_29_27, MLB_DAT),
+        PINMUX_IPSR_DATA(IP11_29_27, SPV_EVEN),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, SCIFB1_TXD_D, SEL_SCIFB1_3),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, TX1_C, SEL_SCIF1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, BPFCLK_C, SEL_FM_2),
+        PINMUX_IPSR_MODSEL_DATA(IP11_29_27, RDS_CLK_B, SEL_RDS_1),
+        PINMUX_IPSR_DATA(IP11_31_30, SSI_SCK0129),
+        PINMUX_IPSR_MODSEL_DATA(IP11_31_30, CAN_CLK_B, SEL_CANCLK_1),
+        PINMUX_IPSR_DATA(IP11_31_30, MOUT0),
+
+        PINMUX_IPSR_DATA(IP12_1_0, SSI_WS0129),
+        PINMUX_IPSR_MODSEL_DATA(IP12_1_0, CAN0_TX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP12_1_0, MOUT1),
+        PINMUX_IPSR_DATA(IP12_3_2, SSI_SDATA0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_3_2, CAN0_RX_B, SEL_CAN0_1),
+        PINMUX_IPSR_DATA(IP12_3_2, MOUT2),
+        PINMUX_IPSR_DATA(IP12_5_4, SSI_SDATA1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_5_4, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_DATA(IP12_5_4, MOUT5),
+        PINMUX_IPSR_DATA(IP12_7_6, SSI_SDATA2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_RX_B, SEL_CAN1_1),
+        PINMUX_IPSR_MODSEL_DATA(IP12_7_6, CAN1_TX_B, SEL_CAN1_1),
+        PINMUX_IPSR_DATA(IP12_7_6, MOUT6),
+        PINMUX_IPSR_DATA(IP12_10_8, SSI_SCK34),
+        PINMUX_IPSR_DATA(IP12_10_8, STP_OPWM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_10_8, SCIFB0_SCK, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_10_8, MSIOF1_SCK, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_10_8, CAN_DEBUG_HW_TRIGGER),
+        PINMUX_IPSR_DATA(IP12_13_11, SSI_WS34),
+        PINMUX_IPSR_MODSEL_DATA(IP12_13_11, STP_IVCXO27_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_13_11, SCIFB0_RXD, SEL_SCIFB_0),
+        PINMUX_IPSR_DATA(IP12_13_11, MSIOF1_SYNC),
+        PINMUX_IPSR_DATA(IP12_13_11, CAN_STEP0),
+        PINMUX_IPSR_DATA(IP12_16_14, SSI_SDATA3),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, STP_ISCLK_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, SCIFB0_TXD, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_16_14, MSIOF1_SS1, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_16_14, CAN_TXCLK),
+        PINMUX_IPSR_DATA(IP12_19_17, SSI_SCK4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, STP_ISD_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SCIFB0_CTS_N, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, MSIOF1_SS2, SEL_SOF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_19_17, SSI_SCK5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP12_19_17, CAN_DEBUGOUT0),
+        PINMUX_IPSR_DATA(IP12_22_20, SSI_WS4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, STP_ISEN_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SCIFB0_RTS_N, SEL_SCIFB_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, MSIOF1_TXD, SEL_SOF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_22_20, SSI_WS5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP12_22_20, CAN_DEBUGOUT1),
+        PINMUX_IPSR_DATA(IP12_24_23, SSI_SDATA4),
+        PINMUX_IPSR_MODSEL_DATA(IP12_24_23, STP_ISSYNC_0, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_24_23, MSIOF1_RXD, SEL_SOF1_0),
+        PINMUX_IPSR_DATA(IP12_24_23, CAN_DEBUGOUT2),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SSI_SCK5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, SCIFB1_SCK, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_27_25, IERX_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP12_27_25, DU2_EXHSYNC_DU2_HSYNC),
+        PINMUX_IPSR_DATA(IP12_27_25, QSTH_QHS),
+        PINMUX_IPSR_DATA(IP12_27_25, CAN_DEBUGOUT3),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SSI_WS5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, SCIFB1_RXD, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP12_30_28, IECLK_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP12_30_28, DU2_EXVSYNC_DU2_VSYNC),
+        PINMUX_IPSR_DATA(IP12_30_28, QSTB_QHE),
+        PINMUX_IPSR_DATA(IP12_30_28, CAN_DEBUGOUT4),
+
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SSI_SDATA5, SEL_SSI5_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB1_TXD, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_2_0, IETX_B, SEL_IEB_1),
+        PINMUX_IPSR_DATA(IP13_2_0, DU2_DR2),
+        PINMUX_IPSR_DATA(IP13_2_0, LCDOUT2),
+        PINMUX_IPSR_DATA(IP13_2_0, CAN_DEBUGOUT5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SSI_SCK6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, SCIFB1_CTS_N, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_D, SEL_FM_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_C, SEL_RDS_2),
+        PINMUX_IPSR_DATA(IP13_6_3, DU2_DR3),
+        PINMUX_IPSR_DATA(IP13_6_3, LCDOUT3),
+        PINMUX_IPSR_DATA(IP13_6_3, CAN_DEBUGOUT6),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, BPFCLK_F, SEL_FM_5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_6_3, RDS_CLK_E, SEL_RDS_4),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SSI_WS6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, SCIFB1_RTS_N, SEL_SCIFB1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_9_7, CAN0_TX_D, SEL_CAN0_3),
+        PINMUX_IPSR_DATA(IP13_9_7, DU2_DR4),
+        PINMUX_IPSR_DATA(IP13_9_7, LCDOUT4),
+        PINMUX_IPSR_DATA(IP13_9_7, CAN_DEBUGOUT7),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, SSI_SDATA6, SEL_SSI6_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, FMIN_D, SEL_FM_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_12_10, RDS_DATA_C, SEL_RDS_2),
+        PINMUX_IPSR_DATA(IP13_12_10, DU2_DR5),
+        PINMUX_IPSR_DATA(IP13_12_10, LCDOUT5),
+        PINMUX_IPSR_DATA(IP13_12_10, CAN_DEBUGOUT8),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SSI_SCK78, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, STP_IVCXO27_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCK1, SEL_SCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_15_13, SCIFA1_SCK, SEL_SCIFA1_0),
+        PINMUX_IPSR_DATA(IP13_15_13, DU2_DR6),
+        PINMUX_IPSR_DATA(IP13_15_13, LCDOUT6),
+        PINMUX_IPSR_DATA(IP13_15_13, CAN_DEBUGOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SSI_WS78, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, STP_ISCLK_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFB2_SCK, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_18_16, SCIFA2_CTS_N),
+        PINMUX_IPSR_DATA(IP13_18_16, DU2_DR7),
+        PINMUX_IPSR_DATA(IP13_18_16, LCDOUT7),
+        PINMUX_IPSR_DATA(IP13_18_16, CAN_DEBUGOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7, SEL_SSI7_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, STP_ISD_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SCIFB2_RXD, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_22_19, SCIFA2_RTS_N),
+        PINMUX_IPSR_DATA(IP13_22_19, TCLK2),
+        PINMUX_IPSR_DATA(IP13_22_19, QSTVA_QVS),
+        PINMUX_IPSR_DATA(IP13_22_19, CAN_DEBUGOUT11),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, BPFCLK_E, SEL_FM_4),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_CLK_D, SEL_RDS_3),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, SSI_SDATA7_B, SEL_SSI7_1),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, FMIN_G, SEL_FM_6),
+        PINMUX_IPSR_MODSEL_DATA(IP13_22_19, RDS_DATA_F, SEL_RDS_5),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8, SEL_SSI8_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, STP_ISEN_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SCIFB2_TXD, SEL_SCIFB2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, CAN0_TX_C, SEL_CAN0_2),
+        PINMUX_IPSR_DATA(IP13_25_23, CAN_DEBUGOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP13_25_23, SSI_SDATA8_B, SEL_SSI8_1),
+        PINMUX_IPSR_DATA(IP13_28_26, SSI_SDATA9),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, STP_ISSYNC_1, SEL_SSP_0),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SCIFB2_CTS_N, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_28_26, SSI_WS1),
+        PINMUX_IPSR_MODSEL_DATA(IP13_28_26, SSI_SDATA5_C, SEL_SSI5_2),
+        PINMUX_IPSR_DATA(IP13_28_26, CAN_DEBUGOUT13),
+        PINMUX_IPSR_DATA(IP13_30_29, AUDIO_CLKA),
+        PINMUX_IPSR_MODSEL_DATA(IP13_30_29, SCIFB2_RTS_N, SEL_SCIFB2_0),
+        PINMUX_IPSR_DATA(IP13_30_29, CAN_DEBUGOUT14),
+
+        PINMUX_IPSR_DATA(IP14_2_0, AUDIO_CLKB),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, SCIF_CLK, SEL_SCIFCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_D, SEL_CAN0_3),
+        PINMUX_IPSR_DATA(IP14_2_0, DVC_MUTE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_2_0, CAN0_RX_C, SEL_CAN0_2),
+        PINMUX_IPSR_DATA(IP14_2_0, CAN_DEBUGOUT15),
+        PINMUX_IPSR_DATA(IP14_2_0, REMOCON),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SCIFA0_SCK, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, HSCK1, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP14_5_3, SCK0),
+        PINMUX_IPSR_DATA(IP14_5_3, MSIOF3_SS2),
+        PINMUX_IPSR_DATA(IP14_5_3, DU2_DG2),
+        PINMUX_IPSR_DATA(IP14_5_3, LCDOUT10),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_C, SEL_IIC1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_5_3, SDA1_CIS_C, SEL_I2C1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, SCIFA0_RXD, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, HRX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_8_6, RX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP14_8_6, DU2_DR0),
+        PINMUX_IPSR_DATA(IP14_8_6, LCDOUT0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, SCIFA0_TXD, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, HTX1, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_11_9, TX0, SEL_SCIF0_0),
+        PINMUX_IPSR_DATA(IP14_11_9, DU2_DR1),
+        PINMUX_IPSR_DATA(IP14_11_9, LCDOUT1),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCIFA0_CTS_N, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, HCTS1_N, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, CTS0_N, SEL_SCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, MSIOF3_SYNC, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_15_12, DU2_DG3),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, LCDOUT11, SEL_HSCIF1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, PWM0_B, SEL_SCIF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_C, SEL_IIC1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_15_12, SCL1_CIS_C, SEL_I2C1_2),
+        PINMUX_IPSR_MODSEL_DATA(IP14_18_16, SCIFA0_RTS_N, SEL_SCFA_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_18_16, HRTS1_N, SEL_HSCIF1_0),
+        PINMUX_IPSR_DATA(IP14_18_16, RTS0_N_TANS),
+        PINMUX_IPSR_DATA(IP14_18_16, MSIOF3_SS1),
+        PINMUX_IPSR_DATA(IP14_18_16, DU2_DG0),
+        PINMUX_IPSR_DATA(IP14_18_16, LCDOUT8),
+        PINMUX_IPSR_DATA(IP14_18_16, PWM1_B),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, SCIFA1_RXD, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, AD_DI, SEL_ADI_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_21_19, RX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP14_21_19, DU2_EXODDF_DU2_ODDF_DISP_CDE),
+        PINMUX_IPSR_DATA(IP14_21_19, QCPV_QDE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, SCIFA1_TXD, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, AD_DO, SEL_ADI_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_24_22, TX1, SEL_SCIF1_0),
+        PINMUX_IPSR_DATA(IP14_24_22, DU2_DG1),
+        PINMUX_IPSR_DATA(IP14_24_22, LCDOUT9),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, SCIFA1_CTS_N, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, AD_CLK, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP14_27_25, CTS1_N),
+        PINMUX_IPSR_MODSEL_DATA(IP14_27_25, MSIOF3_RXD, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_27_25, DU0_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP14_27_25, QCLK),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, SCIFA1_RTS_N, SEL_SCIFA1_0),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, AD_NCS_N, SEL_ADI_0),
+        PINMUX_IPSR_DATA(IP14_30_28, RTS1_N_TANS),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, MSIOF3_TXD, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP14_30_28, DU1_DOTCLKOUT),
+        PINMUX_IPSR_DATA(IP14_30_28, QSTVB_QVE),
+        PINMUX_IPSR_MODSEL_DATA(IP14_30_28, HRTS0_N_C, SEL_HSCIF0_2),
+
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIFA2_SCK, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, FMCLK, SEL_FM_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, MSIOF3_SCK, SEL_SOF3_0),
+        PINMUX_IPSR_DATA(IP15_2_0, DU2_DG7),
+        PINMUX_IPSR_DATA(IP15_2_0, LCDOUT15),
+        PINMUX_IPSR_MODSEL_DATA(IP15_2_0, SCIF_CLK_B, SEL_SCIFCLK_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, FMIN, SEL_FM_0),
+        PINMUX_IPSR_DATA(IP15_5_3, DU2_DB0),
+        PINMUX_IPSR_DATA(IP15_5_3, LCDOUT16),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_5_3, SCL2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA2_TXD, SEL_SCIFA2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, BPFCLK, SEL_FM_0),
+        PINMUX_IPSR_DATA(IP15_8_6, DU2_DB1),
+        PINMUX_IPSR_DATA(IP15_8_6, LCDOUT17),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SDA2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_DATA(IP15_11_9, HSCK0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TS_SDEN0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_11_9, DU2_DG4),
+        PINMUX_IPSR_DATA(IP15_11_9, LCDOUT12),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, HCTS0_N_C, SEL_IIC2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SDA2_CIS, SEL_I2C2_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_13_12, HRX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_13_12, DU2_DB2),
+        PINMUX_IPSR_DATA(IP15_13_12, LCDOUT18),
+        PINMUX_IPSR_MODSEL_DATA(IP15_15_14, HTX0, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_15_14, DU2_DB3),
+        PINMUX_IPSR_DATA(IP15_15_14, LCDOUT19),
+        PINMUX_IPSR_MODSEL_DATA(IP15_17_16, HCTS0_N, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_17_16, SSI_SCK9),
+        PINMUX_IPSR_DATA(IP15_17_16, DU2_DB4),
+        PINMUX_IPSR_DATA(IP15_17_16, LCDOUT20),
+        PINMUX_IPSR_MODSEL_DATA(IP15_19_18, HRTS0_N, SEL_HSCIF0_0),
+        PINMUX_IPSR_DATA(IP15_19_18, SSI_WS9),
+        PINMUX_IPSR_DATA(IP15_19_18, DU2_DB5),
+        PINMUX_IPSR_DATA(IP15_19_18, LCDOUT21),
+        PINMUX_IPSR_MODSEL_DATA(IP15_22_20, MSIOF0_SCK, SEL_SOF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP15_22_20, TS_SDAT0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_22_20, ADICLK),
+        PINMUX_IPSR_DATA(IP15_22_20, DU2_DB6),
+        PINMUX_IPSR_DATA(IP15_22_20, LCDOUT22),
+        PINMUX_IPSR_DATA(IP15_25_23, MSIOF0_SYNC),
+        PINMUX_IPSR_MODSEL_DATA(IP15_25_23, TS_SCK0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP15_25_23, SSI_SCK2),
+        PINMUX_IPSR_DATA(IP15_25_23, ADIDATA),
+        PINMUX_IPSR_DATA(IP15_25_23, DU2_DB7),
+        PINMUX_IPSR_DATA(IP15_25_23, LCDOUT23),
+        PINMUX_IPSR_MODSEL_DATA(IP15_25_23, SCIFA2_RXD_B, SEL_SCIFA2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP15_27_26, MSIOF0_SS1, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP15_27_26, ADICHS0),
+        PINMUX_IPSR_DATA(IP15_27_26, DU2_DG5),
+        PINMUX_IPSR_DATA(IP15_27_26, LCDOUT13),
+        PINMUX_IPSR_MODSEL_DATA(IP15_29_28, MSIOF0_TXD, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP15_29_28, ADICHS1),
+        PINMUX_IPSR_DATA(IP15_29_28, DU2_DG6),
+        PINMUX_IPSR_DATA(IP15_29_28, LCDOUT14),
+
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, MSIOF0_SS2, SEL_SOF0_0),
+        PINMUX_IPSR_DATA(IP16_2_0, AUDIO_CLKOUT),
+        PINMUX_IPSR_DATA(IP16_2_0, ADICHS2),
+        PINMUX_IPSR_DATA(IP16_2_0, DU2_DISP),
+        PINMUX_IPSR_DATA(IP16_2_0, QPOLA),
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HTX0_C, SEL_HSCIF0_2),
+        PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFA2_TXD_B, SEL_SCIFA2_1),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, MSIOF0_RXD, SEL_SOF0_0),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, TS_SPSYNC0, SEL_TSIF0_0),
+        PINMUX_IPSR_DATA(IP16_5_3, SSI_WS2),
+        PINMUX_IPSR_DATA(IP16_5_3, ADICS_SAMP),
+        PINMUX_IPSR_DATA(IP16_5_3, DU2_CDE),
+        PINMUX_IPSR_DATA(IP16_5_3, QPOLB),
+        PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HRX0_C, SEL_HSCIF0_2),
+        PINMUX_IPSR_DATA(IP16_6, USB1_PWEN),
+        PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
+        PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
+        PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
+};
+
+static struct sh_pfc_pin pinmux_pins[] = {
+        PINMUX_GPIO_GP_ALL(),
+};
+
+/* - ETH -------------------------------------------------------------------- */
+static const unsigned int eth_link_pins[] = {
+        /* LINK */
+        RCAR_GP_PIN(2, 22),
+};
+static const unsigned int eth_link_mux[] = {
+        ETH_LINK_MARK,
+};
+static const unsigned int eth_magic_pins[] = {
+        /* MAGIC */
+        RCAR_GP_PIN(2, 27),
+};
+static const unsigned int eth_magic_mux[] = {
+        ETH_MAGIC_MARK,
+};
+static const unsigned int eth_mdio_pins[] = {
+        /* MDC, MDIO */
+        RCAR_GP_PIN(2, 29), RCAR_GP_PIN(2, 24),
+};
+static const unsigned int eth_mdio_mux[] = {
+        ETH_MDC_MARK, ETH_MDIO_MARK,
+};
+static const unsigned int eth_rmii_pins[] = {
+        /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
+        RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 19),
+        RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 25),
+        RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 23),
+};
+static const unsigned int eth_rmii_mux[] = {
+        ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
+        ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REF_CLK_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+static const unsigned int intc_irq0_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 25),
+};
+static const unsigned int intc_irq0_mux[] = {
+        IRQ0_MARK,
+};
+static const unsigned int intc_irq1_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 27),
+};
+static const unsigned int intc_irq1_mux[] = {
+        IRQ1_MARK,
+};
+static const unsigned int intc_irq2_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 29),
+};
+static const unsigned int intc_irq2_mux[] = {
+        IRQ2_MARK,
+};
+static const unsigned int intc_irq3_pins[] = {
+        /* IRQ */
+        RCAR_GP_PIN(1, 23),
+};
+static const unsigned int intc_irq3_mux[] = {
+        IRQ3_MARK,
+};
+/* - SCIF0 ----------------------------------------------------------------- */
+static const unsigned int scif0_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scif0_data_mux[] = {
+        RX0_MARK, TX0_MARK,
+};
+static const unsigned int scif0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scif0_clk_mux[] = {
+        SCK0_MARK,
+};
+static const unsigned int scif0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scif0_ctrl_mux[] = {
+        RTS0_N_TANS_MARK, CTS0_N_MARK,
+};
+static const unsigned int scif0_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scif0_data_b_mux[] = {
+        RX0_B_MARK, TX0_B_MARK,
+};
+/* - SCIF1 ----------------------------------------------------------------- */
+static const unsigned int scif1_data_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scif1_data_mux[] = {
+        RX1_MARK, TX1_MARK,
+};
+static const unsigned int scif1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scif1_clk_mux[] = {
+        SCK1_MARK,
+};
+static const unsigned int scif1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scif1_ctrl_mux[] = {
+        RTS1_N_TANS_MARK, CTS1_N_MARK,
+};
+static const unsigned int scif1_data_b_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scif1_data_b_mux[] = {
+        RX1_B_MARK, TX1_B_MARK,
+};
+static const unsigned int scif1_data_c_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scif1_data_c_mux[] = {
+        RX1_C_MARK, TX1_C_MARK,
+};
+static const unsigned int scif1_data_d_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scif1_data_d_mux[] = {
+        RX1_D_MARK, TX1_D_MARK,
+};
+static const unsigned int scif1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scif1_clk_d_mux[] = {
+        SCK1_D_MARK,
+};
+static const unsigned int scif1_data_e_pins[] = {
+        /* RX, TX */
+        RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scif1_data_e_mux[] = {
+        RX1_E_MARK, TX1_E_MARK,
+};
+static const unsigned int scif1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scif1_clk_e_mux[] = {
+        SCK1_E_MARK,
+};
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 29),
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 27),
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 31), RCAR_GP_PIN(4, 30),
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_N_MARK, SCIFA0_CTS_N_MARK,
+};
+static const unsigned int scifa0_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
+};
+static const unsigned int scifa0_data_b_mux[] = {
+        SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
+};
+static const unsigned int scifa0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(1, 19),
+};
+static const unsigned int scifa0_clk_b_mux[] = {
+        SCIFA0_SCK_B_MARK,
+};
+static const unsigned int scifa0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(1, 23), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int scifa0_ctrl_b_mux[] = {
+        SCIFA0_RTS_N_B_MARK, SCIFA0_CTS_N_B_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 0), RCAR_GP_PIN(5, 1),
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 20),
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(5, 3), RCAR_GP_PIN(5, 2),
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_N_MARK, SCIFA1_CTS_N_MARK,
+};
+static const unsigned int scifa1_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 21),
+};
+static const unsigned int scifa1_data_b_mux[] = {
+        SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
+};
+static const unsigned int scifa1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 23),
+};
+static const unsigned int scifa1_clk_b_mux[] = {
+        SCIFA1_SCK_B_MARK,
+};
+static const unsigned int scifa1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 22), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifa1_ctrl_b_mux[] = {
+        SCIFA1_RTS_N_B_MARK, SCIFA1_CTS_N_B_MARK,
+};
+static const unsigned int scifa1_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10),
+};
+static const unsigned int scifa1_data_c_mux[] = {
+        SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
+};
+static const unsigned int scifa1_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 8),
+};
+static const unsigned int scifa1_clk_c_mux[] = {
+        SCIFA1_SCK_C_MARK,
+};
+static const unsigned int scifa1_ctrl_c_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 11),
+};
+static const unsigned int scifa1_ctrl_c_mux[] = {
+        SCIFA1_RTS_N_C_MARK, SCIFA1_CTS_N_C_MARK,
+};
+static const unsigned int scifa1_data_d_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12),
+};
+static const unsigned int scifa1_data_d_mux[] = {
+        SCIFA1_RXD_D_MARK, SCIFA1_TXD_D_MARK,
+};
+static const unsigned int scifa1_clk_d_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 10),
+};
+static const unsigned int scifa1_clk_d_mux[] = {
+        SCIFA1_SCK_D_MARK,
+};
+static const unsigned int scifa1_ctrl_d_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 13),
+};
+static const unsigned int scifa1_ctrl_d_mux[] = {
+        SCIFA1_RTS_N_D_MARK, SCIFA1_CTS_N_D_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 4),
+};
+static const unsigned int scifa2_clk_mux[] = {
+        SCIFA2_SCK_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS_N_MARK, SCIFA2_CTS_N_MARK,
+};
+static const unsigned int scifa2_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 16),
+};
+static const unsigned int scifa2_data_b_mux[] = {
+        SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
+};
+static const unsigned int scifa2_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(5, 31), RCAR_GP_PIN(5, 30),
+};
+static const unsigned int scifa2_data_c_mux[] = {
+        SCIFA2_RXD_C_MARK, SCIFA2_TXD_C_MARK,
+};
+static const unsigned int scifa2_clk_c_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(5, 29),
+};
+static const unsigned int scifa2_clk_c_mux[] = {
+        SCIFA2_SCK_C_MARK,
+};
+/* - SCIFB0 ----------------------------------------------------------------- */
+static const unsigned int scifb0_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
+};
+static const unsigned int scifb0_data_mux[] = {
+        SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
+};
+static const unsigned int scifb0_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 8),
+};
+static const unsigned int scifb0_clk_mux[] = {
+        SCIFB0_SCK_MARK,
+};
+static const unsigned int scifb0_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 12), RCAR_GP_PIN(4, 11),
+};
+static const unsigned int scifb0_ctrl_mux[] = {
+        SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
+};
+static const unsigned int scifb0_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
+};
+static const unsigned int scifb0_data_b_mux[] = {
+        SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
+};
+static const unsigned int scifb0_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 9),
+};
+static const unsigned int scifb0_clk_b_mux[] = {
+        SCIFB0_SCK_B_MARK,
+};
+static const unsigned int scifb0_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 12),
+};
+static const unsigned int scifb0_ctrl_b_mux[] = {
+        SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
+};
+static const unsigned int scifb0_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb0_data_c_mux[] = {
+        SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
+};
+/* - SCIFB1 ----------------------------------------------------------------- */
+static const unsigned int scifb1_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
+};
+static const unsigned int scifb1_data_mux[] = {
+        SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
+};
+static const unsigned int scifb1_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 14),
+};
+static const unsigned int scifb1_clk_mux[] = {
+        SCIFB1_SCK_MARK,
+};
+static const unsigned int scifb1_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 18), RCAR_GP_PIN(4, 17),
+};
+static const unsigned int scifb1_ctrl_mux[] = {
+        SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
+};
+static const unsigned int scifb1_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3),
+};
+static const unsigned int scifb1_data_b_mux[] = {
+        SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
+};
+static const unsigned int scifb1_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 1),
+};
+static const unsigned int scifb1_clk_b_mux[] = {
+        SCIFB1_SCK_B_MARK,
+};
+static const unsigned int scifb1_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(3, 5), RCAR_GP_PIN(3, 4),
+};
+static const unsigned int scifb1_ctrl_b_mux[] = {
+        SCIFB1_RTS_N_B_MARK, SCIFB1_CTS_N_B_MARK,
+};
+static const unsigned int scifb1_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
+};
+static const unsigned int scifb1_data_c_mux[] = {
+        SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
+};
+static const unsigned int scifb1_data_d_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 1), RCAR_GP_PIN(4, 2),
+};
+static const unsigned int scifb1_data_d_mux[] = {
+        SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
+};
+static const unsigned int scifb1_data_e_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+};
+static const unsigned int scifb1_data_e_mux[] = {
+        SCIFB1_RXD_E_MARK, SCIFB1_TXD_E_MARK,
+};
+static const unsigned int scifb1_clk_e_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(3, 17),
+};
+static const unsigned int scifb1_clk_e_mux[] = {
+        SCIFB1_SCK_E_MARK,
+};
+static const unsigned int scifb1_data_f_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
+};
+static const unsigned int scifb1_data_f_mux[] = {
+        SCIFB1_RXD_F_MARK, SCIFB1_TXD_F_MARK,
+};
+static const unsigned int scifb1_data_g_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(2, 21), RCAR_GP_PIN(2, 22),
+};
+static const unsigned int scifb1_data_g_mux[] = {
+        SCIFB1_RXD_G_MARK, SCIFB1_TXD_G_MARK,
+};
+static const unsigned int scifb1_clk_g_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(2, 20),
+};
+static const unsigned int scifb1_clk_g_mux[] = {
+        SCIFB1_SCK_G_MARK,
+};
+/* - SCIFB2 ----------------------------------------------------------------- */
+static const unsigned int scifb2_data_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
+};
+static const unsigned int scifb2_data_mux[] = {
+        SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
+};
+static const unsigned int scifb2_clk_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(4, 21),
+};
+static const unsigned int scifb2_clk_mux[] = {
+        SCIFB2_SCK_MARK,
+};
+static const unsigned int scifb2_ctrl_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 24),
+};
+static const unsigned int scifb2_ctrl_mux[] = {
+        SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
+};
+static const unsigned int scifb2_data_b_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 28), RCAR_GP_PIN(0, 30),
+};
+static const unsigned int scifb2_data_b_mux[] = {
+        SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
+};
+static const unsigned int scifb2_clk_b_pins[] = {
+        /* SCK */
+        RCAR_GP_PIN(0, 31),
+};
+static const unsigned int scifb2_clk_b_mux[] = {
+        SCIFB2_SCK_B_MARK,
+};
+static const unsigned int scifb2_ctrl_b_pins[] = {
+        /* RTS, CTS */
+        RCAR_GP_PIN(0, 29), RCAR_GP_PIN(0, 27),
+};
+static const unsigned int scifb2_ctrl_b_mux[] = {
+        SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
+};
+static const unsigned int scifb2_data_c_pins[] = {
+        /* RXD, TXD */
+        RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
+};
+static const unsigned int scifb2_data_c_mux[] = {
+        SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
+};
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 20),
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 21),
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 22),
+};
+static const unsigned int tpu0_to2_mux[] = {
+        TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        RCAR_GP_PIN(0, 23),
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
+
+/* - MMCIF ------------------------------------------------------------------ */
+static const unsigned int mmc0_data1_pins[] = {
+        /* D[0] */
+        RCAR_GP_PIN(3, 18),
+};
+static const unsigned int mmc0_data1_mux[] = {
+        MMC0_D0_MARK,
+};
+static const unsigned int mmc0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int mmc0_data4_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+};
+static const unsigned int mmc0_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19),
+        RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+        RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
+        RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
+};
+static const unsigned int mmc0_data8_mux[] = {
+        MMC0_D0_MARK, MMC0_D1_MARK, MMC0_D2_MARK, MMC0_D3_MARK,
+        MMC0_D4_MARK, MMC0_D5_MARK, MMC0_D6_MARK, MMC0_D7_MARK,
+};
+static const unsigned int mmc0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int mmc0_ctrl_mux[] = {
+        MMC0_CLK_MARK, MMC0_CMD_MARK,
+};
+
+static const unsigned int mmc1_data1_pins[] = {
+        /* D[0] */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int mmc1_data1_mux[] = {
+        MMC1_D0_MARK,
+};
+static const unsigned int mmc1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+        RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int mmc1_data4_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+};
+static const unsigned int mmc1_data8_pins[] = {
+        /* D[0:7] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27),
+        RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+        RCAR_GP_PIN(3, 30), RCAR_GP_PIN(3, 31),
+        RCAR_GP_PIN(3, 13), RCAR_GP_PIN(3, 14),
+};
+static const unsigned int mmc1_data8_mux[] = {
+        MMC1_D0_MARK, MMC1_D1_MARK, MMC1_D2_MARK, MMC1_D3_MARK,
+        MMC1_D4_MARK, MMC1_D5_MARK, MMC1_D6_MARK, MMC1_D7_MARK,
+};
+static const unsigned int mmc1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int mmc1_ctrl_mux[] = {
+        MMC1_CLK_MARK, MMC1_CMD_MARK,
+};
+
+/* - SDHI ------------------------------------------------------------------- */
+static const unsigned int sdhi0_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 2),
+};
+static const unsigned int sdhi0_data1_mux[] = {
+        SD0_DAT0_MARK,
+};
+static const unsigned int sdhi0_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 5),
+};
+static const unsigned int sdhi0_data4_mux[] = {
+        SD0_DAT0_MARK, SD0_DAT1_MARK, SD0_DAT2_MARK, SD0_DAT3_MARK,
+};
+static const unsigned int sdhi0_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
+};
+static const unsigned int sdhi0_ctrl_mux[] = {
+        SD0_CLK_MARK, SD0_CMD_MARK,
+};
+static const unsigned int sdhi0_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 6),
+};
+static const unsigned int sdhi0_cd_mux[] = {
+        SD0_CD_MARK,
+};
+static const unsigned int sdhi0_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 7),
+};
+static const unsigned int sdhi0_wp_mux[] = {
+        SD0_WP_MARK,
+};
+
+static const unsigned int sdhi1_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 10),
+};
+static const unsigned int sdhi1_data1_mux[] = {
+        SD1_DAT0_MARK,
+};
+static const unsigned int sdhi1_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
+};
+static const unsigned int sdhi1_data4_mux[] = {
+        SD1_DAT0_MARK, SD1_DAT1_MARK, SD1_DAT2_MARK, SD1_DAT3_MARK,
+};
+static const unsigned int sdhi1_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
+};
+static const unsigned int sdhi1_ctrl_mux[] = {
+        SD1_CLK_MARK, SD1_CMD_MARK,
+};
+static const unsigned int sdhi1_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 14),
+};
+static const unsigned int sdhi1_cd_mux[] = {
+        SD1_CD_MARK,
+};
+static const unsigned int sdhi1_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 15),
+};
+static const unsigned int sdhi1_wp_mux[] = {
+        SD1_WP_MARK,
+};
+
+static const unsigned int sdhi2_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 18),
+};
+static const unsigned int sdhi2_data1_mux[] = {
+        SD2_DAT0_MARK,
+};
+static const unsigned int sdhi2_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 18), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 21),
+};
+static const unsigned int sdhi2_data4_mux[] = {
+        SD2_DAT0_MARK, SD2_DAT1_MARK, SD2_DAT2_MARK, SD2_DAT3_MARK,
+};
+static const unsigned int sdhi2_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 16), RCAR_GP_PIN(3, 17),
+};
+static const unsigned int sdhi2_ctrl_mux[] = {
+        SD2_CLK_MARK, SD2_CMD_MARK,
+};
+static const unsigned int sdhi2_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 22),
+};
+static const unsigned int sdhi2_cd_mux[] = {
+        SD2_CD_MARK,
+};
+static const unsigned int sdhi2_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 23),
+};
+static const unsigned int sdhi2_wp_mux[] = {
+        SD2_WP_MARK,
+};
+
+static const unsigned int sdhi3_data1_pins[] = {
+        /* D0 */
+        RCAR_GP_PIN(3, 26),
+};
+static const unsigned int sdhi3_data1_mux[] = {
+        SD3_DAT0_MARK,
+};
+static const unsigned int sdhi3_data4_pins[] = {
+        /* D[0:3] */
+        RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 27), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 29),
+};
+static const unsigned int sdhi3_data4_mux[] = {
+        SD3_DAT0_MARK, SD3_DAT1_MARK, SD3_DAT2_MARK, SD3_DAT3_MARK,
+};
+static const unsigned int sdhi3_ctrl_pins[] = {
+        /* CLK, CMD */
+        RCAR_GP_PIN(3, 24), RCAR_GP_PIN(3, 25),
+};
+static const unsigned int sdhi3_ctrl_mux[] = {
+        SD3_CLK_MARK, SD3_CMD_MARK,
+};
+static const unsigned int sdhi3_cd_pins[] = {
+        /* CD */
+        RCAR_GP_PIN(3, 30),
+};
+static const unsigned int sdhi3_cd_mux[] = {
+        SD3_CD_MARK,
+};
+static const unsigned int sdhi3_wp_pins[] = {
+        /* WP */
+        RCAR_GP_PIN(3, 31),
+};
+static const unsigned int sdhi3_wp_mux[] = {
+        SD3_WP_MARK,
+};
+
+static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(eth_link),
+        SH_PFC_PIN_GROUP(eth_magic),
+        SH_PFC_PIN_GROUP(eth_mdio),
+        SH_PFC_PIN_GROUP(eth_rmii),
+        SH_PFC_PIN_GROUP(intc_irq0),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2),
+        SH_PFC_PIN_GROUP(intc_irq3),
+        SH_PFC_PIN_GROUP(scif0_data),
+        SH_PFC_PIN_GROUP(scif0_clk),
+        SH_PFC_PIN_GROUP(scif0_ctrl),
+        SH_PFC_PIN_GROUP(scif0_data_b),
+        SH_PFC_PIN_GROUP(scif1_data),
+        SH_PFC_PIN_GROUP(scif1_clk),
+        SH_PFC_PIN_GROUP(scif1_ctrl),
+        SH_PFC_PIN_GROUP(scif1_data_b),
+        SH_PFC_PIN_GROUP(scif1_data_c),
+        SH_PFC_PIN_GROUP(scif1_data_d),
+        SH_PFC_PIN_GROUP(scif1_clk_d),
+        SH_PFC_PIN_GROUP(scif1_data_e),
+        SH_PFC_PIN_GROUP(scif1_clk_e),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa0_data_b),
+        SH_PFC_PIN_GROUP(scifa0_clk_b),
+        SH_PFC_PIN_GROUP(scifa0_ctrl_b),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data_b),
+        SH_PFC_PIN_GROUP(scifa1_clk_b),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_b),
+        SH_PFC_PIN_GROUP(scifa1_data_c),
+        SH_PFC_PIN_GROUP(scifa1_clk_c),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_c),
+        SH_PFC_PIN_GROUP(scifa1_data_d),
+        SH_PFC_PIN_GROUP(scifa1_clk_d),
+        SH_PFC_PIN_GROUP(scifa1_ctrl_d),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data_b),
+        SH_PFC_PIN_GROUP(scifa2_data_c),
+        SH_PFC_PIN_GROUP(scifa2_clk_c),
+        SH_PFC_PIN_GROUP(scifb0_data),
+        SH_PFC_PIN_GROUP(scifb0_clk),
+        SH_PFC_PIN_GROUP(scifb0_ctrl),
+        SH_PFC_PIN_GROUP(scifb0_data_b),
+        SH_PFC_PIN_GROUP(scifb0_clk_b),
+        SH_PFC_PIN_GROUP(scifb0_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb0_data_c),
+        SH_PFC_PIN_GROUP(scifb1_data),
+        SH_PFC_PIN_GROUP(scifb1_clk),
+        SH_PFC_PIN_GROUP(scifb1_ctrl),
+        SH_PFC_PIN_GROUP(scifb1_data_b),
+        SH_PFC_PIN_GROUP(scifb1_clk_b),
+        SH_PFC_PIN_GROUP(scifb1_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb1_data_c),
+        SH_PFC_PIN_GROUP(scifb1_data_d),
+        SH_PFC_PIN_GROUP(scifb1_data_e),
+        SH_PFC_PIN_GROUP(scifb1_clk_e),
+        SH_PFC_PIN_GROUP(scifb1_data_f),
+        SH_PFC_PIN_GROUP(scifb1_data_g),
+        SH_PFC_PIN_GROUP(scifb1_clk_g),
+        SH_PFC_PIN_GROUP(scifb2_data),
+        SH_PFC_PIN_GROUP(scifb2_clk),
+        SH_PFC_PIN_GROUP(scifb2_ctrl),
+        SH_PFC_PIN_GROUP(scifb2_data_b),
+        SH_PFC_PIN_GROUP(scifb2_clk_b),
+        SH_PFC_PIN_GROUP(scifb2_ctrl_b),
+        SH_PFC_PIN_GROUP(scifb2_data_c),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+        SH_PFC_PIN_GROUP(mmc0_data1),
+        SH_PFC_PIN_GROUP(mmc0_data4),
+        SH_PFC_PIN_GROUP(mmc0_data8),
+        SH_PFC_PIN_GROUP(mmc0_ctrl),
+        SH_PFC_PIN_GROUP(mmc1_data1),
+        SH_PFC_PIN_GROUP(mmc1_data4),
+        SH_PFC_PIN_GROUP(mmc1_data8),
+        SH_PFC_PIN_GROUP(mmc1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_data1),
+        SH_PFC_PIN_GROUP(sdhi0_data4),
+        SH_PFC_PIN_GROUP(sdhi0_ctrl),
+        SH_PFC_PIN_GROUP(sdhi0_cd),
+        SH_PFC_PIN_GROUP(sdhi0_wp),
+        SH_PFC_PIN_GROUP(sdhi1_data1),
+        SH_PFC_PIN_GROUP(sdhi1_data4),
+        SH_PFC_PIN_GROUP(sdhi1_ctrl),
+        SH_PFC_PIN_GROUP(sdhi1_cd),
+        SH_PFC_PIN_GROUP(sdhi1_wp),
+        SH_PFC_PIN_GROUP(sdhi2_data1),
+        SH_PFC_PIN_GROUP(sdhi2_data4),
+        SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(sdhi2_cd),
+        SH_PFC_PIN_GROUP(sdhi2_wp),
+        SH_PFC_PIN_GROUP(sdhi3_data1),
+        SH_PFC_PIN_GROUP(sdhi3_data4),
+        SH_PFC_PIN_GROUP(sdhi3_ctrl),
+        SH_PFC_PIN_GROUP(sdhi3_cd),
+        SH_PFC_PIN_GROUP(sdhi3_wp),
+};
+
+static const char * const eth_groups[] = {
+        "eth_link",
+        "eth_magic",
+        "eth_mdio",
+        "eth_rmii",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0",
+        "intc_irq1",
+        "intc_irq2",
+        "intc_irq3",
+};
+
+static const char * const scif0_groups[] = {
+        "scif0_data",
+        "scif0_clk",
+        "scif0_ctrl",
+        "scif0_data_b",
+};
+
+static const char * const scif1_groups[] = {
+        "scif1_data",
+        "scif1_clk",
+        "scif1_ctrl",
+        "scif1_data_b",
+        "scif1_data_c",
+        "scif1_data_d",
+        "scif1_clk_d",
+        "scif1_data_e",
+        "scif1_clk_e",
+};
+
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+        "scifa0_data_b",
+        "scifa0_clk_b",
+        "scifa0_ctrl_b",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+        "scifa1_data_b",
+        "scifa1_clk_b",
+        "scifa1_ctrl_b",
+        "scifa1_data_c",
+        "scifa1_clk_c",
+        "scifa1_ctrl_c",
+        "scifa1_data_d",
+        "scifa1_clk_d",
+        "scifa1_ctrl_d",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk",
+        "scifa2_ctrl",
+        "scifa2_data_b",
+        "scifa2_data_c",
+        "scifa2_clk_c",
+};
+
+static const char * const scifb0_groups[] = {
+        "scifb0_data",
+        "scifb0_clk",
+        "scifb0_ctrl",
+        "scifb0_data_b",
+        "scifb0_clk_b",
+        "scifb0_ctrl_b",
+        "scifb0_data_c",
+};
+
+static const char * const scifb1_groups[] = {
+        "scifb1_data",
+        "scifb1_clk",
+        "scifb1_ctrl",
+        "scifb1_data_b",
+        "scifb1_clk_b",
+        "scifb1_ctrl_b",
+        "scifb1_data_c",
+        "scifb1_data_d",
+        "scifb1_data_e",
+        "scifb1_clk_e",
+        "scifb1_data_f",
+        "scifb1_data_g",
+        "scifb1_clk_g",
+};
+
+static const char * const scifb2_groups[] = {
+        "scifb2_data",
+        "scifb2_clk",
+        "scifb2_ctrl",
+        "scifb2_data_b",
+        "scifb2_clk_b",
+        "scifb2_ctrl_b",
+        "scifb2_data_c",
+};
+
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2",
+        "tpu0_to3",
+};
+
+static const char * const mmc0_groups[] = {
+        "mmc0_data1",
+        "mmc0_data4",
+        "mmc0_data8",
+        "mmc0_ctrl",
+};
+
+static const char * const mmc1_groups[] = {
+        "mmc1_data1",
+        "mmc1_data4",
+        "mmc1_data8",
+        "mmc1_ctrl",
+};
+
+static const char * const sdhi0_groups[] = {
+        "sdhi0_data1",
+        "sdhi0_data4",
+        "sdhi0_ctrl",
+        "sdhi0_cd",
+        "sdhi0_wp",
+};
+
+static const char * const sdhi1_groups[] = {
+        "sdhi1_data1",
+        "sdhi1_data4",
+        "sdhi1_ctrl",
+        "sdhi1_cd",
+        "sdhi1_wp",
+};
+
+static const char * const sdhi2_groups[] = {
+        "sdhi2_data1",
+        "sdhi2_data4",
+        "sdhi2_ctrl",
+        "sdhi2_cd",
+        "sdhi2_wp",
+};
+
+static const char * const sdhi3_groups[] = {
+        "sdhi3_data1",
+        "sdhi3_data4",
+        "sdhi3_ctrl",
+        "sdhi3_cd",
+        "sdhi3_wp",
+};
+
+static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(eth),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(scif0),
+        SH_PFC_FUNCTION(scif1),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifb0),
+        SH_PFC_FUNCTION(scifb1),
+        SH_PFC_FUNCTION(scifb2),
+        SH_PFC_FUNCTION(tpu0),
+        SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(mmc1),
+        SH_PFC_FUNCTION(sdhi0),
+        SH_PFC_FUNCTION(sdhi1),
+        SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(sdhi3),
+};
+
+static struct pinmux_cfg_reg pinmux_config_regs[] = {
+        { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
+                GP_0_31_FN, FN_IP3_17_15,
+                GP_0_30_FN, FN_IP3_14_12,
+                GP_0_29_FN, FN_IP3_11_8,
+                GP_0_28_FN, FN_IP3_7_4,
+                GP_0_27_FN, FN_IP3_3_0,
+                GP_0_26_FN, FN_IP2_28_26,
+                GP_0_25_FN, FN_IP2_25_22,
+                GP_0_24_FN, FN_IP2_21_18,
+                GP_0_23_FN, FN_IP2_17_15,
+                GP_0_22_FN, FN_IP2_14_12,
+                GP_0_21_FN, FN_IP2_11_9,
+                GP_0_20_FN, FN_IP2_8_6,
+                GP_0_19_FN, FN_IP2_5_3,
+                GP_0_18_FN, FN_IP2_2_0,
+                GP_0_17_FN, FN_IP1_29_28,
+                GP_0_16_FN, FN_IP1_27_26,
+                GP_0_15_FN, FN_IP1_25_22,
+                GP_0_14_FN, FN_IP1_21_18,
+                GP_0_13_FN, FN_IP1_17_15,
+                GP_0_12_FN, FN_IP1_14_12,
+                GP_0_11_FN, FN_IP1_11_8,
+                GP_0_10_FN, FN_IP1_7_4,
+                GP_0_9_FN, FN_IP1_3_0,
+                GP_0_8_FN, FN_IP0_30_27,
+                GP_0_7_FN, FN_IP0_26_23,
+                GP_0_6_FN, FN_IP0_22_20,
+                GP_0_5_FN, FN_IP0_19_16,
+                GP_0_4_FN, FN_IP0_15_12,
+                GP_0_3_FN, FN_IP0_11_9,
+                GP_0_2_FN, FN_IP0_8_6,
+                GP_0_1_FN, FN_IP0_5_3,
+                GP_0_0_FN, FN_IP0_2_0 }
+        },
+        { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_1_29_FN, FN_IP6_13_11,
+                GP_1_28_FN, FN_IP6_10_9,
+                GP_1_27_FN, FN_IP6_8_6,
+                GP_1_26_FN, FN_IP6_5_3,
+                GP_1_25_FN, FN_IP6_2_0,
+                GP_1_24_FN, FN_IP5_29_27,
+                GP_1_23_FN, FN_IP5_26_24,
+                GP_1_22_FN, FN_IP5_23_21,
+                GP_1_21_FN, FN_IP5_20_18,
+                GP_1_20_FN, FN_IP5_17_15,
+                GP_1_19_FN, FN_IP5_14_13,
+                GP_1_18_FN, FN_IP5_12_10,
+                GP_1_17_FN, FN_IP5_9_6,
+                GP_1_16_FN, FN_IP5_5_3,
+                GP_1_15_FN, FN_IP5_2_0,
+                GP_1_14_FN, FN_IP4_29_27,
+                GP_1_13_FN, FN_IP4_26_24,
+                GP_1_12_FN, FN_IP4_23_21,
+                GP_1_11_FN, FN_IP4_20_18,
+                GP_1_10_FN, FN_IP4_17_15,
+                GP_1_9_FN, FN_IP4_14_12,
+                GP_1_8_FN, FN_IP4_11_9,
+                GP_1_7_FN, FN_IP4_8_6,
+                GP_1_6_FN, FN_IP4_5_3,
+                GP_1_5_FN, FN_IP4_2_0,
+                GP_1_4_FN, FN_IP3_31_29,
+                GP_1_3_FN, FN_IP3_28_26,
+                GP_1_2_FN, FN_IP3_25_23,
+                GP_1_1_FN, FN_IP3_22_20,
+                GP_1_0_FN, FN_IP3_19_18, }
+        },
+        { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
+                0, 0,
+                0, 0,
+                GP_2_29_FN, FN_IP7_15_13,
+                GP_2_28_FN, FN_IP7_12_10,
+                GP_2_27_FN, FN_IP7_9_8,
+                GP_2_26_FN, FN_IP7_7_6,
+                GP_2_25_FN, FN_IP7_5_3,
+                GP_2_24_FN, FN_IP7_2_0,
+                GP_2_23_FN, FN_IP6_31_29,
+                GP_2_22_FN, FN_IP6_28_26,
+                GP_2_21_FN, FN_IP6_25_23,
+                GP_2_20_FN, FN_IP6_22_20,
+                GP_2_19_FN, FN_IP6_19_17,
+                GP_2_18_FN, FN_IP6_16_14,
+                GP_2_17_FN, FN_VI1_DATA7_VI1_B7,
+                GP_2_16_FN, FN_IP8_27,
+                GP_2_15_FN, FN_IP8_26,
+                GP_2_14_FN, FN_IP8_25_24,
+                GP_2_13_FN, FN_IP8_23_22,
+                GP_2_12_FN, FN_IP8_21_20,
+                GP_2_11_FN, FN_IP8_19_18,
+                GP_2_10_FN, FN_IP8_17_16,
+                GP_2_9_FN, FN_IP8_15_14,
+                GP_2_8_FN, FN_IP8_13_12,
+                GP_2_7_FN, FN_IP8_11_10,
+                GP_2_6_FN, FN_IP8_9_8,
+                GP_2_5_FN, FN_IP8_7_6,
+                GP_2_4_FN, FN_IP8_5_4,
+                GP_2_3_FN, FN_IP8_3_2,
+                GP_2_2_FN, FN_IP8_1_0,
+                GP_2_1_FN, FN_IP7_30_29,
+                GP_2_0_FN, FN_IP7_28_27 }
+        },
+        { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
+                GP_3_31_FN, FN_IP11_21_18,
+                GP_3_30_FN, FN_IP11_17_15,
+                GP_3_29_FN, FN_IP11_14_13,
+                GP_3_28_FN, FN_IP11_12_11,
+                GP_3_27_FN, FN_IP11_10_9,
+                GP_3_26_FN, FN_IP11_8_7,
+                GP_3_25_FN, FN_IP11_6_5,
+                GP_3_24_FN, FN_IP11_4,
+                GP_3_23_FN, FN_IP11_3_0,
+                GP_3_22_FN, FN_IP10_29_26,
+                GP_3_21_FN, FN_IP10_25_23,
+                GP_3_20_FN, FN_IP10_22_19,
+                GP_3_19_FN, FN_IP10_18_15,
+                GP_3_18_FN, FN_IP10_14_11,
+                GP_3_17_FN, FN_IP10_10_7,
+                GP_3_16_FN, FN_IP10_6_4,
+                GP_3_15_FN, FN_IP10_3_0,
+                GP_3_14_FN, FN_IP9_31_28,
+                GP_3_13_FN, FN_IP9_27_26,
+                GP_3_12_FN, FN_IP9_25_24,
+                GP_3_11_FN, FN_IP9_23_22,
+                GP_3_10_FN, FN_IP9_21_20,
+                GP_3_9_FN, FN_IP9_19_18,
+                GP_3_8_FN, FN_IP9_17_16,
+                GP_3_7_FN, FN_IP9_15_12,
+                GP_3_6_FN, FN_IP9_11_8,
+                GP_3_5_FN, FN_IP9_7_6,
+                GP_3_4_FN, FN_IP9_5_4,
+                GP_3_3_FN, FN_IP9_3_2,
+                GP_3_2_FN, FN_IP9_1_0,
+                GP_3_1_FN, FN_IP8_30_29,
+                GP_3_0_FN, FN_IP8_28 }
+        },
+        { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
+                GP_4_31_FN, FN_IP14_18_16,
+                GP_4_30_FN, FN_IP14_15_12,
+                GP_4_29_FN, FN_IP14_11_9,
+                GP_4_28_FN, FN_IP14_8_6,
+                GP_4_27_FN, FN_IP14_5_3,
+                GP_4_26_FN, FN_IP14_2_0,
+                GP_4_25_FN, FN_IP13_30_29,
+                GP_4_24_FN, FN_IP13_28_26,
+                GP_4_23_FN, FN_IP13_25_23,
+                GP_4_22_FN, FN_IP13_22_19,
+                GP_4_21_FN, FN_IP13_18_16,
+                GP_4_20_FN, FN_IP13_15_13,
+                GP_4_19_FN, FN_IP13_12_10,
+                GP_4_18_FN, FN_IP13_9_7,
+                GP_4_17_FN, FN_IP13_6_3,
+                GP_4_16_FN, FN_IP13_2_0,
+                GP_4_15_FN, FN_IP12_30_28,
+                GP_4_14_FN, FN_IP12_27_25,
+                GP_4_13_FN, FN_IP12_24_23,
+                GP_4_12_FN, FN_IP12_22_20,
+                GP_4_11_FN, FN_IP12_19_17,
+                GP_4_10_FN, FN_IP12_16_14,
+                GP_4_9_FN, FN_IP12_13_11,
+                GP_4_8_FN, FN_IP12_10_8,
+                GP_4_7_FN, FN_IP12_7_6,
+                GP_4_6_FN, FN_IP12_5_4,
+                GP_4_5_FN, FN_IP12_3_2,
+                GP_4_4_FN, FN_IP12_1_0,
+                GP_4_3_FN, FN_IP11_31_30,
+                GP_4_2_FN, FN_IP11_29_27,
+                GP_4_1_FN, FN_IP11_26_24,
+                GP_4_0_FN, FN_IP11_23_22 }
+        },
+        { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
+                GP_5_31_FN, FN_IP7_24_22,
+                GP_5_30_FN, FN_IP7_21_19,
+                GP_5_29_FN, FN_IP7_18_16,
+                GP_5_28_FN, FN_DU_DOTCLKIN2,
+                GP_5_27_FN, FN_IP7_26_25,
+                GP_5_26_FN, FN_DU_DOTCLKIN0,
+                GP_5_25_FN, FN_AVS2,
+                GP_5_24_FN, FN_AVS1,
+                GP_5_23_FN, FN_USB2_OVC,
+                GP_5_22_FN, FN_USB2_PWEN,
+                GP_5_21_FN, FN_IP16_7,
+                GP_5_20_FN, FN_IP16_6,
+                GP_5_19_FN, FN_USB0_OVC_VBUS,
+                GP_5_18_FN, FN_USB0_PWEN,
+                GP_5_17_FN, FN_IP16_5_3,
+                GP_5_16_FN, FN_IP16_2_0,
+                GP_5_15_FN, FN_IP15_29_28,
+                GP_5_14_FN, FN_IP15_27_26,
+                GP_5_13_FN, FN_IP15_25_23,
+                GP_5_12_FN, FN_IP15_22_20,
+                GP_5_11_FN, FN_IP15_19_18,
+                GP_5_10_FN, FN_IP15_17_16,
+                GP_5_9_FN, FN_IP15_15_14,
+                GP_5_8_FN, FN_IP15_13_12,
+                GP_5_7_FN, FN_IP15_11_9,
+                GP_5_6_FN, FN_IP15_8_6,
+                GP_5_5_FN, FN_IP15_5_3,
+                GP_5_4_FN, FN_IP15_2_0,
+                GP_5_3_FN, FN_IP14_30_28,
+                GP_5_2_FN, FN_IP14_27_25,
+                GP_5_1_FN, FN_IP14_24_22,
+                GP_5_0_FN, FN_IP14_21_19 }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
+                             1, 4, 4, 3, 4, 4, 3, 3, 3, 3) {
+                /* IP0_31 [1] */
+                0, 0,
+                /* IP0_30_27 [4] */
+                FN_D8, FN_SCIFA1_SCK_C, FN_AVB_TXD0, FN_MII_TXD0,
+                FN_VI0_G0, FN_VI0_G0_B, FN_VI2_DATA0_VI2_B0,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_26_23 [4] */
+                FN_D7, FN_AD_DI_B, FN_SDA2_C,
+                FN_VI3_DATA7, FN_VI0_R3, FN_VI0_R3_B, FN_SDA2_CIS_C,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_22_20 [3] */
+                FN_D6, FN_SCL2_C, FN_VI3_DATA6, FN_VI0_R2, FN_VI0_R2_B,
+                FN_SCL2_CIS_C, 0, 0,
+                /* IP0_19_16 [4] */
+                FN_D5, FN_SCIFB1_TXD_F, FN_SCIFB0_TXD_C, FN_VI3_DATA5,
+                FN_VI0_R1, FN_VI0_R1_B, FN_TX0_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_15_12 [4] */
+                FN_D4, FN_SCIFB1_RXD_F, FN_SCIFB0_RXD_C, FN_VI3_DATA4,
+                FN_VI0_R0, FN_VI0_R0_B, FN_RX0_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP0_11_9 [3] */
+                FN_D3, FN_MSIOF3_TXD_B, FN_VI3_DATA3, FN_VI0_G7, FN_VI0_G7_B,
+                0, 0, 0,
+                /* IP0_8_6 [3] */
+                FN_D2, FN_MSIOF3_RXD_B, FN_VI3_DATA2, FN_VI0_G6, FN_VI0_G6_B,
+                0, 0, 0,
+                /* IP0_5_3 [3] */
+                FN_D1, FN_MSIOF3_SYNC_B, FN_VI3_DATA1, FN_VI0_G5, FN_VI0_G5_B,
+                0, 0, 0,
+                /* IP0_2_0 [3] */
+                FN_D0, FN_MSIOF3_SCK_B, FN_VI3_DATA0, FN_VI0_G4, FN_VI0_G4_B,
+                0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
+                             2, 2, 2, 4, 4, 3, 3, 4, 4, 4) {
+                /* IP1_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP1_29_28 [2] */
+                FN_A1, FN_PWM4, 0, 0,
+                /* IP1_27_26 [2] */
+                FN_A0, FN_PWM3, 0, 0,
+                /* IP1_25_22 [4] */
+                FN_D15, FN_SCIFB1_TXD_C, FN_AVB_TXD7, FN_TX1_B,
+                FN_VI0_FIELD, FN_VI0_FIELD_B, FN_VI2_DATA7_VI2_B7,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_21_18 [4] */
+                FN_D14, FN_SCIFB1_RXD_C, FN_AVB_TXD6, FN_RX1_B,
+                FN_VI0_CLKENB, FN_VI0_CLKENB_B, FN_VI2_DATA6_VI2_B6,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_17_15 [3] */
+                FN_D13, FN_AVB_TXD5, FN_VI0_VSYNC_N,
+                FN_VI0_VSYNC_N_B, FN_VI2_DATA5_VI2_B5,
+                0, 0, 0,
+                /* IP1_14_12 [3] */
+                FN_D12, FN_SCIFA1_RTS_N_C, FN_AVB_TXD4,
+                FN_VI0_HSYNC_N, FN_VI0_HSYNC_N_B, FN_VI2_DATA4_VI2_B4,
+                0, 0,
+                /* IP1_11_8 [4] */
+                FN_D11, FN_SCIFA1_CTS_N_C, FN_AVB_TXD3, FN_MII_TXD3,
+                FN_VI0_G3, FN_VI0_G3_B, FN_VI2_DATA3_VI2_B3,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_7_4 [4] */
+                FN_D10, FN_SCIFA1_TXD_C, FN_AVB_TXD2, FN_MII_TXD2,
+                FN_VI0_G2, FN_VI0_G2_B, FN_VI2_DATA2_VI2_B2,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP1_3_0 [4] */
+                FN_D9, FN_SCIFA1_RXD_C, FN_AVB_TXD1, FN_MII_TXD1,
+                FN_VI0_G1, FN_VI0_G1_B, FN_VI2_DATA1_VI2_B1,
+                0, 0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
+                             3, 3, 4, 4, 3, 3, 3, 3, 3, 3) {
+                /* IP2_31_29 [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_28_26 [3] */
+                FN_A10, FN_SSI_SDATA5_B, FN_MSIOF2_SYNC, FN_VI0_R6,
+                FN_VI0_R6_B, FN_VI2_DATA2_VI2_B2_B, 0, 0,
+                /* IP2_25_22 [4] */
+                FN_A9, FN_SCIFA1_CTS_N_B, FN_SSI_WS5_B, FN_VI0_R5,
+                FN_VI0_R5_B, FN_SCIFB2_TXD_C, 0, FN_VI2_DATA1_VI2_B1_B,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_21_18 [4] */
+                FN_A8, FN_SCIFA1_RXD_B, FN_SSI_SCK5_B, FN_VI0_R4,
+                FN_VI0_R4_B, FN_SCIFB2_RXD_C, 0, FN_VI2_DATA0_VI2_B0_B,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP2_17_15 [3] */
+                FN_A7, FN_SCIFA1_SCK_B, FN_AUDIO_CLKOUT_B, FN_TPU0TO3,
+                0, 0, 0, 0,
+                /* IP2_14_12 [3] */
+                FN_A6, FN_SCIFA1_RTS_N_B, FN_TPU0TO2, 0, 0, 0, 0, 0,
+                /* IP2_11_9 [3] */
+                FN_A5, FN_SCIFA1_TXD_B, FN_TPU0TO1, 0, 0, 0, 0, 0,
+                /* IP2_8_6 [3] */
+                FN_A4, FN_MSIOF1_TXD_B, FN_TPU0TO0, 0, 0, 0, 0, 0,
+                /* IP2_5_3 [3] */
+                FN_A3, FN_PWM6, FN_MSIOF1_SS2_B, 0, 0, 0, 0, 0,
+                /* IP2_2_0 [3] */
+                FN_A2, FN_PWM5, FN_MSIOF1_SS1_B, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
+                             3, 3, 3, 3, 2, 3, 3, 4, 4, 4) {
+                /* IP3_31_29 [3] */
+                FN_A20, FN_SPCLK, FN_VI1_R3, FN_VI1_R3_B, FN_VI2_G4,
+                0, 0, 0,
+                /* IP3_28_26 [3] */
+                FN_A19, FN_AD_NCS_N_B, FN_ATACS01_N, FN_EX_WAIT0_B,
+                0, 0, 0, 0,
+                /* IP3_25_23 [3] */
+                FN_A18, FN_AD_CLK_B, FN_ATAG1_N, 0, 0, 0, 0, 0,
+                /* IP3_22_20 [3] */
+                FN_A17, FN_AD_DO_B, FN_ATADIR1_N, 0, 0, 0, 0, 0,
+                /* IP3_19_18 [2] */
+                FN_A16, FN_ATAWR1_N, 0, 0,
+                /* IP3_17_15 [3] */
+                FN_A15, FN_SCIFB2_SCK_B, FN_ATARD1_N, FN_MSIOF2_SS2,
+                0, 0, 0, 0,
+                /* IP3_14_12 [3] */
+                FN_A14, FN_SCIFB2_TXD_B, FN_ATACS11_N, FN_MSIOF2_SS1,
+                0, 0, 0, 0,
+                /* IP3_11_8 [4] */
+                FN_A13, FN_SCIFB2_RTS_N_B, FN_EX_WAIT2,
+                FN_MSIOF2_RXD, FN_VI1_R2, FN_VI1_R2_B, FN_VI2_G2,
+                FN_VI2_DATA5_VI2_B5_B, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_7_4 [4] */
+                FN_A12, FN_SCIFB2_RXD_B, FN_MSIOF2_TXD, FN_VI1_R1,
+                FN_VI1_R1_B, FN_VI2_G1, FN_VI2_DATA4_VI2_B4_B,
+                0, 0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP3_3_0 [4] */
+                FN_A11, FN_SCIFB2_CTS_N_B, FN_MSIOF2_SCK, FN_VI1_R0,
+                FN_VI1_R0_B, FN_VI2_G0, FN_VI2_DATA3_VI2_B3_B, 0,
+                0, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
+                             2, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3) {
+                /* IP4_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP4_29_27 [3] */
+                FN_EX_CS2_N, FN_GPS_SIGN, FN_HRTS1_N_B,
+                FN_VI3_CLKENB, FN_VI1_G0, FN_VI1_G0_B, FN_VI2_R2, 0,
+                /* IP4_26_24 [3] */
+                FN_EX_CS1_N, FN_GPS_CLK, FN_HCTS1_N_B, FN_VI1_FIELD,
+                FN_VI1_FIELD_B, FN_VI2_R1, 0, 0,
+                /* IP4_23_21 [3] */
+                FN_EX_CS0_N, FN_HRX1_B, FN_VI1_G5, FN_VI1_G5_B, FN_VI2_R0,
+                FN_HTX0_B, FN_MSIOF0_SS1_B, 0,
+                /* IP4_20_18 [3] */
+                FN_CS1_N_A26, FN_SPEEDIN, FN_VI0_R7, FN_VI0_R7_B,
+                FN_VI2_CLK, FN_VI2_CLK_B, 0, 0,
+                /* IP4_17_15 [3] */
+                FN_CS0_N, FN_VI1_R6, FN_VI1_R6_B, FN_VI2_G3, FN_MSIOF0_SS2_B,
+                0, 0, 0,
+                /* IP4_14_12 [3] */
+                FN_A25, FN_SSL, FN_VI1_G6, FN_VI1_G6_B, FN_VI2_FIELD,
+                FN_VI2_FIELD_B, 0, 0,
+                /* IP4_11_9 [3] */
+                FN_A24, FN_IO3, FN_VI1_R7, FN_VI1_R7_B, FN_VI2_CLKENB,
+                FN_VI2_CLKENB_B, 0, 0,
+                /* IP4_8_6 [3] */
+                FN_A23, FN_IO2, FN_VI1_G7, FN_VI1_G7_B, FN_VI2_G7, 0, 0, 0,
+                /* IP4_5_3 [3] */
+                FN_A22, FN_MISO_IO1, FN_VI1_R5, FN_VI1_R5_B, FN_VI2_G6, 0, 0, 0,
+                /* IP4_2_0 [3] */
+                FN_A21, FN_MOSI_IO0, FN_VI1_R4, FN_VI1_R4_B, FN_VI2_G5, 0, 0, 0,
+                }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
+                             2, 3, 3, 3, 3, 3, 2, 3, 4, 3, 3) {
+                /* IP5_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP5_29_27 [3] */
+                FN_DREQ0_N, FN_VI1_HSYNC_N, FN_VI1_HSYNC_N_B, FN_VI2_R7,
+                FN_SSI_SCK78_C, FN_SSI_WS78_B, 0, 0,
+                /* IP5_26_24 [3] */
+                FN_EX_WAIT0, FN_IRQ3, FN_INTC_IRQ3_N,
+                FN_VI3_CLK, FN_SCIFA0_RTS_N_B, FN_HRX0_B,
+                FN_MSIOF0_SCK_B, 0,
+                /* IP5_23_21 [3] */
+                FN_WE1_N, FN_IERX, FN_CAN1_RX, FN_VI1_G4,
+                FN_VI1_G4_B, FN_VI2_R6, FN_SCIFA0_CTS_N_B,
+                FN_IERX_C, 0,
+                /* IP5_20_18 [3] */
+                FN_WE0_N, FN_IECLK, FN_CAN_CLK,
+                FN_VI2_VSYNC_N, FN_SCIFA0_TXD_B, FN_VI2_VSYNC_N_B, 0, 0,
+                /* IP5_17_15 [3] */
+                FN_RD_WR_N, FN_VI1_G3, FN_VI1_G3_B, FN_VI2_R5, FN_SCIFA0_RXD_B,
+                FN_INTC_IRQ4_N, 0, 0,
+                /* IP5_14_13 [2] */
+                FN_RD_N, FN_CAN0_TX, FN_SCIFA0_SCK_B, 0,
+                /* IP5_12_10 [3] */
+                FN_BS_N, FN_IETX, FN_HTX1_B, FN_CAN1_TX, FN_DRACK0, FN_IETX_C,
+                0, 0,
+                /* IP5_9_6 [4] */
+                FN_EX_CS5_N, FN_CAN0_RX, FN_MSIOF1_RXD_B, FN_VI3_VSYNC_N,
+                FN_VI1_G2, FN_VI1_G2_B, FN_VI2_R4, FN_SDA1, FN_INTC_EN1_N,
+                FN_SDA1_CIS, 0, 0, 0, 0, 0, 0,
+                /* IP5_5_3 [3] */
+                FN_EX_CS4_N, FN_MSIOF1_SCK_B, FN_VI3_HSYNC_N,
+                FN_VI2_HSYNC_N, FN_SCL1, FN_VI2_HSYNC_N_B,
+                FN_INTC_EN0_N, FN_SCL1_CIS,
+                /* IP5_2_0 [3] */
+                FN_EX_CS3_N, FN_GPS_MAG, FN_VI3_FIELD, FN_VI1_G1, FN_VI1_G1_B,
+                FN_VI2_R3, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
+                             3, 3, 3, 3, 3, 3, 3, 2, 3, 3, 3) {
+                /* IP6_31_29 [3] */
+                FN_ETH_REF_CLK, FN_RMII_REF_CLK, FN_HCTS0_N_E,
+                FN_STP_IVCXO27_1_B, FN_HRX0_F, 0, 0, 0,
+                /* IP6_28_26 [3] */
+                FN_ETH_LINK, FN_RMII_LINK, FN_HTX0_E,
+                FN_STP_IVCXO27_0_B, FN_SCIFB1_TXD_G, FN_TX1_E, 0, 0,
+                /* IP6_25_23 [3] */
+                FN_ETH_RXD1, FN_RMII_RXD1, FN_HRX0_E, FN_STP_ISSYNC_0_B,
+                FN_TS_SCK0_D, FN_GLO_I1_C, FN_SCIFB1_RXD_G, FN_RX1_E,
+                /* IP6_22_20 [3] */
+                FN_ETH_RXD0, FN_RMII_RXD0, FN_STP_ISEN_0_B, FN_TS_SDAT0_D,
+                FN_GLO_I0_C, FN_SCIFB1_SCK_G, FN_SCK1_E, 0,
+                /* IP6_19_17 [3] */
+                FN_ETH_RX_ER, FN_RMII_RX_ER, FN_STP_ISD_0_B,
+                FN_TS_SPSYNC0_D, FN_GLO_Q1_C, FN_SDA2_E, FN_SDA2_CIS_E, 0,
+                /* IP6_16_14 [3] */
+                FN_ETH_CRS_DV, FN_RMII_CRS_DV, FN_STP_ISCLK_0_B,
+                FN_TS_SDEN0_D, FN_GLO_Q0_C, FN_SCL2_E,
+                FN_SCL2_CIS_E, 0,
+                /* IP6_13_11 [3] */
+                FN_DACK2, FN_IRQ2, FN_INTC_IRQ2_N,
+                FN_SSI_SDATA6_B, FN_HRTS0_N_B, FN_MSIOF0_RXD_B, 0, 0,
+                /* IP6_10_9 [2] */
+                FN_DREQ2_N, FN_HSCK1_B, FN_HCTS0_N_B, FN_MSIOF0_TXD_B,
+                /* IP6_8_6 [3] */
+                FN_DACK1, FN_IRQ1, FN_INTC_IRQ1_N, FN_SSI_WS6_B,
+                FN_SSI_SDATA8_C, 0, 0, 0,
+                /* IP6_5_3 [3] */
+                FN_DREQ1_N, FN_VI1_CLKENB, FN_VI1_CLKENB_B,
+                FN_SSI_SDATA7_C, FN_SSI_SCK78_B, 0, 0, 0,
+                /* IP6_2_0 [3] */
+                FN_DACK0, FN_IRQ0, FN_INTC_IRQ0_N, FN_SSI_SCK6_B,
+                FN_VI1_VSYNC_N, FN_VI1_VSYNC_N_B, FN_SSI_WS78_C, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
+                             1, 2, 2, 2, 3, 3, 3, 3, 3, 2, 2, 3, 3) {
+                /* IP7_31 [1] */
+                0, 0,
+                /* IP7_30_29 [2] */
+                FN_VI0_DATA0_VI0_B0, FN_ATACS10_N, FN_AVB_RXD2,
+                FN_MII_RXD2,
+                /* IP7_28_27 [2] */
+                FN_VI0_CLK, FN_ATACS00_N, FN_AVB_RXD1, FN_MII_RXD1,
+                /* IP7_26_25 [2] */
+                FN_DU1_DOTCLKIN, FN_AUDIO_CLKC, FN_AUDIO_CLKOUT_C, 0,
+                /* IP7_24_22 [3] */
+                FN_PWM2, FN_PWMFSW0, FN_SCIFA2_RXD_C, FN_PCMWE_N, FN_IECLK_C,
+                0, 0, 0,
+                /* IP7_21_19 [3] */
+                FN_PWM1, FN_SCIFA2_TXD_C, FN_STP_ISSYNC_1_B, FN_TS_SCK1_C,
+                FN_GLO_RFON_C, FN_PCMOE_N, 0, 0,
+                /* IP7_18_16 [3] */
+                FN_PWM0, FN_SCIFA2_SCK_C, FN_STP_ISEN_1_B, FN_TS_SDAT1_C,
+                FN_GLO_SS_C, 0, 0, 0,
+                /* IP7_15_13 [3] */
+                FN_ETH_MDC, FN_RMII_MDC, FN_STP_ISD_1_B,
+                FN_TS_SPSYNC1_C, FN_GLO_SDATA_C, 0, 0, 0,
+                /* IP7_12_10 [3] */
+                FN_ETH_TXD0, FN_RMII_TXD0, FN_STP_ISCLK_1_B, FN_TS_SDEN1_C,
+                FN_GLO_SCLK_C, 0, 0, 0,
+                /* IP7_9_8 [2] */
+                FN_ETH_MAGIC, FN_RMII_MAGIC, FN_SIM0_RST_C, 0,
+                /* IP7_7_6 [2] */
+                FN_ETH_TX_EN, FN_RMII_TX_EN, FN_SIM0_CLK_C, FN_HRTS0_N_F,
+                /* IP7_5_3 [3] */
+                FN_ETH_TXD1, FN_RMII_TXD1, FN_HTX0_F, FN_BPFCLK_G, FN_RDS_CLK_F,
+                0, 0, 0,
+                /* IP7_2_0 [3] */
+                FN_ETH_MDIO, FN_RMII_MDIO, FN_HRTS0_N_E,
+                FN_SIM0_D_C, FN_HCTS0_N_F, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
+                             1, 2, 1, 1, 1, 2, 2, 2, 2, 2, 2,
+                             2, 2, 2, 2, 2, 2, 2) {
+                /* IP8_31 [1] */
+                0, 0,
+                /* IP8_30_29 [2] */
+                FN_SD0_CMD, FN_SCIFB1_SCK_B, FN_VI1_DATA1_VI1_B1_B, 0,
+                /* IP8_28 [1] */
+                FN_SD0_CLK, FN_VI1_DATA0_VI1_B0_B,
+                /* IP8_27 [1] */
+                FN_VI1_DATA6_VI1_B6, FN_AVB_GTXREFCLK,
+                /* IP8_26 [1] */
+                FN_VI1_DATA5_VI1_B5, FN_AVB_PHY_INT,
+                /* IP8_25_24 [2] */
+                FN_VI1_DATA4_VI1_B4, FN_SCIFA1_RTS_N_D,
+                FN_AVB_MAGIC, FN_MII_MAGIC,
+                /* IP8_23_22 [2] */
+                FN_VI1_DATA3_VI1_B3, FN_SCIFA1_CTS_N_D, FN_AVB_GTX_CLK, 0,
+                /* IP8_21_20 [2] */
+                FN_VI1_DATA2_VI1_B2, FN_SCIFA1_TXD_D, FN_AVB_MDIO,
+                FN_MII_MDIO,
+                /* IP8_19_18 [2] */
+                FN_VI1_DATA1_VI1_B1, FN_SCIFA1_RXD_D, FN_AVB_MDC, FN_MII_MDC,
+                /* IP8_17_16 [2] */
+                FN_VI1_DATA0_VI1_B0, FN_SCIFA1_SCK_D, FN_AVB_CRS, FN_MII_CRS,
+                /* IP8_15_14 [2] */
+                FN_VI1_CLK, FN_AVB_RX_DV, FN_MII_RX_DV, 0,
+                /* IP8_13_12 [2] */
+                FN_VI0_DATA7_VI0_B7, FN_AVB_RX_CLK, FN_MII_RX_CLK, 0,
+                /* IP8_11_10 [2] */
+                FN_VI0_DATA6_VI0_B6, FN_AVB_RX_ER, FN_MII_RX_ER, 0,
+                /* IP8_9_8 [2] */
+                FN_VI0_DATA5_VI0_B5, FN_EX_WAIT1, FN_AVB_RXD7, 0,
+                /* IP8_7_6 [2] */
+                FN_VI0_DATA4_VI0_B4, FN_ATAG0_N, FN_AVB_RXD6, 0,
+                /* IP8_5_4 [2] */
+                FN_VI0_DATA3_VI0_B3, FN_ATADIR0_N, FN_AVB_RXD5, 0,
+                /* IP8_3_2 [2] */
+                FN_VI0_DATA2_VI0_B2, FN_ATAWR0_N, FN_AVB_RXD4, 0,
+                /* IP8_1_0 [2] */
+                FN_VI0_DATA1_VI0_B1, FN_ATARD0_N, FN_AVB_RXD3, FN_MII_RXD3, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
+                             4, 2, 2, 2, 2, 2, 2, 4, 4, 2, 2, 2, 2) {
+                /* IP9_31_28 [4] */
+                FN_SD1_CD, FN_MMC1_D6, FN_TS_SDEN1, FN_USB1_EXTP,
+                FN_GLO_SS, FN_VI0_CLK_B, FN_SCL2_D, FN_SCL2_CIS_D,
+                FN_SIM0_CLK_B, FN_VI3_CLK_B, 0, 0, 0, 0, 0, 0,
+                /* IP9_27_26 [2] */
+                FN_SD1_DAT3, FN_AVB_RXD0, FN_MII_RXD0, FN_SCIFB0_RTS_N_B,
+                /* IP9_25_24 [2] */
+                FN_SD1_DAT2, FN_AVB_COL, FN_MII_COL, FN_SCIFB0_CTS_N_B,
+                /* IP9_23_22 [2] */
+                FN_SD1_DAT1, FN_AVB_LINK, FN_MII_LINK, FN_SCIFB0_TXD_B,
+                /* IP9_21_20 [2] */
+                FN_SD1_DAT0, FN_AVB_TX_CLK, FN_MII_TX_CLK, FN_SCIFB0_RXD_B,
+                /* IP9_19_18 [2] */
+                FN_SD1_CMD, FN_AVB_TX_ER, FN_MII_TX_ER, FN_SCIFB0_SCK_B,
+                /* IP9_17_16 [2] */
+                FN_SD1_CLK, FN_AVB_TX_EN, FN_MII_TX_EN, 0,
+                /* IP9_15_12 [4] */
+                FN_SD0_WP, FN_MMC0_D7, FN_TS_SPSYNC0_B, FN_USB0_IDIN,
+                FN_GLO_SDATA, FN_VI1_DATA7_VI1_B7_B, FN_SDA1_B,
+                FN_SDA1_CIS_B, FN_VI2_DATA7_VI2_B7_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_11_8 [4] */
+                FN_SD0_CD, FN_MMC0_D6, FN_TS_SDEN0_B, FN_USB0_EXTP,
+                FN_GLO_SCLK, FN_VI1_DATA6_VI1_B6_B, FN_SCL1_B,
+                FN_SCL1_CIS_B, FN_VI2_DATA6_VI2_B6_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP9_7_6 [2] */
+                FN_SD0_DAT3, FN_SCIFB1_RTS_N_B, FN_VI1_DATA5_VI1_B5_B, 0,
+                /* IP9_5_4 [2] */
+                FN_SD0_DAT2, FN_SCIFB1_CTS_N_B, FN_VI1_DATA4_VI1_B4_B, 0,
+                /* IP9_3_2 [2] */
+                FN_SD0_DAT1, FN_SCIFB1_TXD_B, FN_VI1_DATA3_VI1_B3_B, 0,
+                /* IP9_1_0 [2] */
+                FN_SD0_DAT0, FN_SCIFB1_RXD_B, FN_VI1_DATA2_VI1_B2_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
+                             2, 4, 3, 4, 4, 4, 4, 3, 4) {
+                /* IP10_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP10_29_26 [4] */
+                FN_SD2_CD, FN_MMC0_D4, FN_TS_SDAT0_B, FN_USB2_EXTP, FN_GLO_I0,
+                FN_VI0_DATA6_VI0_B6_B, FN_HCTS0_N_D, FN_TS_SDAT1_B,
+                FN_GLO_I0_B, FN_VI3_DATA6_B, 0, 0, 0, 0, 0, 0,
+                /* IP10_25_23 [3] */
+                FN_SD2_DAT3, FN_MMC0_D3, FN_SIM0_RST, FN_VI0_DATA5_VI0_B5_B,
+                FN_HTX0_D, FN_TS_SPSYNC1_B, FN_GLO_Q1_B, FN_VI3_DATA5_B,
+                /* IP10_22_19 [4] */
+                FN_SD2_DAT2, FN_MMC0_D2, FN_BPFCLK_B, FN_RDS_CLK,
+                FN_VI0_DATA4_VI0_B4_B, FN_HRX0_D, FN_TS_SDEN1_B,
+                FN_GLO_Q0_B, FN_VI3_DATA4_B, 0, 0, 0, 0, 0, 0, 0,
+                /* IP10_18_15 [4] */
+                FN_SD2_DAT1, FN_MMC0_D1, FN_FMIN_B, FN_RDS_DATA,
+                FN_VI0_DATA3_VI0_B3_B, FN_SCIFB1_TXD_E, FN_TX1_D,
+                FN_TS_SCK0_C, FN_GLO_RFON_B, FN_VI3_DATA3_B,
+                0, 0, 0, 0, 0, 0,
+                /* IP10_14_11 [4] */
+                FN_SD2_DAT0, FN_MMC0_D0, FN_FMCLK_B,
+                FN_VI0_DATA2_VI0_B2_B, FN_SCIFB1_RXD_E, FN_RX1_D,
+                FN_TS_SDAT0_C, FN_GLO_SS_B, FN_VI3_DATA2_B,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_10_7 [4] */
+                FN_SD2_CMD, FN_MMC0_CMD, FN_SIM0_D,
+                FN_VI0_DATA1_VI0_B1_B, FN_SCIFB1_SCK_E, FN_SCK1_D,
+                FN_TS_SPSYNC0_C, FN_GLO_SDATA_B, FN_VI3_DATA1_B,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP10_6_4 [3] */
+                FN_SD2_CLK, FN_MMC0_CLK, FN_SIM0_CLK,
+                FN_VI0_DATA0_VI0_B0_B, FN_TS_SDEN0_C, FN_GLO_SCLK_B,
+                FN_VI3_DATA0_B, 0,
+                /* IP10_3_0 [4] */
+                FN_SD1_WP, FN_MMC1_D7, FN_TS_SPSYNC1, FN_USB1_IDIN,
+                FN_GLO_RFON, FN_VI1_CLK_B, FN_SDA2_D, FN_SDA2_CIS_D,
+                FN_SIM0_D_B, 0, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
+                             2, 3, 3, 2, 4, 3, 2, 2, 2, 2, 2, 1, 4) {
+                /* IP11_31_30 [2] */
+                FN_SSI_SCK0129, FN_CAN_CLK_B, FN_MOUT0, 0,
+                /* IP11_29_27 [3] */
+                FN_MLB_DAT, FN_SPV_EVEN, FN_SCIFB1_TXD_D, FN_TX1_C, FN_BPFCLK_C,
+                FN_RDS_CLK_B, 0, 0,
+                /* IP11_26_24 [3] */
+                FN_MLB_SIG, FN_SCIFB1_RXD_D, FN_RX1_C, FN_SDA2_B, FN_SDA2_CIS_B,
+                0, 0, 0,
+                /* IP11_23_22 [2] */
+                FN_MLB_CLK, FN_SCL2_B, FN_SCL2_CIS_B, 0,
+                /* IP11_21_18 [4] */
+                FN_SD3_WP, FN_MMC1_D5, FN_TS_SCK1, FN_GLO_Q1, FN_FMIN_C,
+                FN_RDS_DATA_B, FN_FMIN_E, FN_RDS_DATA_D, FN_FMIN_F,
+                FN_RDS_DATA_E, 0, 0, 0, 0, 0, 0,
+                /* IP11_17_15 [3] */
+                FN_SD3_CD, FN_MMC1_D4, FN_TS_SDAT1,
+                FN_VSP, FN_GLO_Q0, FN_SIM0_RST_B, 0, 0,
+                /* IP11_14_13 [2] */
+                FN_SD3_DAT3, FN_MMC1_D3, FN_SCKZ, 0,
+                /* IP11_12_11 [2] */
+                FN_SD3_DAT2, FN_MMC1_D2, FN_SDATA, 0,
+                /* IP11_10_9 [2] */
+                FN_SD3_DAT1, FN_MMC1_D1, FN_MDATA, 0,
+                /* IP11_8_7 [2] */
+                FN_SD3_DAT0, FN_MMC1_D0, FN_STM_N, 0,
+                /* IP11_6_5 [2] */
+                FN_SD3_CMD, FN_MMC1_CMD, FN_MTS_N, 0,
+                /* IP11_4 [1] */
+                FN_SD3_CLK, FN_MMC1_CLK,
+                /* IP11_3_0 [4] */
+                FN_SD2_WP, FN_MMC0_D5, FN_TS_SCK0_B, FN_USB2_IDIN,
+                FN_GLO_I1, FN_VI0_DATA7_VI0_B7_B, FN_HRTS0_N_D,
+                FN_TS_SCK1_B, FN_GLO_I1_B, FN_VI3_DATA7_B, 0, 0, 0, 0, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
+                             1, 3, 3, 2, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
+                /* IP12_31 [1] */
+                0, 0,
+                /* IP12_30_28 [3] */
+                FN_SSI_WS5, FN_SCIFB1_RXD, FN_IECLK_B,
+                FN_DU2_EXVSYNC_DU2_VSYNC, FN_QSTB_QHE,
+                FN_CAN_DEBUGOUT4, 0, 0,
+                /* IP12_27_25 [3] */
+                FN_SSI_SCK5, FN_SCIFB1_SCK,
+                FN_IERX_B, FN_DU2_EXHSYNC_DU2_HSYNC, FN_QSTH_QHS,
+                FN_CAN_DEBUGOUT3, 0, 0,
+                /* IP12_24_23 [2] */
+                FN_SSI_SDATA4, FN_STP_ISSYNC_0, FN_MSIOF1_RXD,
+                FN_CAN_DEBUGOUT2,
+                /* IP12_22_20 [3] */
+                FN_SSI_WS4, FN_STP_ISEN_0, FN_SCIFB0_RTS_N,
+                FN_MSIOF1_TXD, FN_SSI_WS5_C, FN_CAN_DEBUGOUT1, 0, 0,
+                /* IP12_19_17 [3] */
+                FN_SSI_SCK4, FN_STP_ISD_0, FN_SCIFB0_CTS_N,
+                FN_MSIOF1_SS2, FN_SSI_SCK5_C, FN_CAN_DEBUGOUT0, 0, 0,
+                /* IP12_16_14 [3] */
+                FN_SSI_SDATA3, FN_STP_ISCLK_0,
+                FN_SCIFB0_TXD, FN_MSIOF1_SS1, FN_CAN_TXCLK, 0, 0, 0,
+                /* IP12_13_11 [3] */
+                FN_SSI_WS34, FN_STP_IVCXO27_0, FN_SCIFB0_RXD, FN_MSIOF1_SYNC,
+                FN_CAN_STEP0, 0, 0, 0,
+                /* IP12_10_8 [3] */
+                FN_SSI_SCK34, FN_STP_OPWM_0, FN_SCIFB0_SCK,
+                FN_MSIOF1_SCK, FN_CAN_DEBUG_HW_TRIGGER, 0, 0, 0,
+                /* IP12_7_6 [2] */
+                FN_SSI_SDATA2, FN_CAN1_RX_B, FN_SSI_SCK1, FN_MOUT6,
+                /* IP12_5_4 [2] */
+                FN_SSI_SDATA1, FN_CAN1_TX_B, FN_MOUT5, 0,
+                /* IP12_3_2 [2] */
+                FN_SSI_SDATA0, FN_CAN0_RX_B, FN_MOUT2, 0,
+                /* IP12_1_0 [2] */
+                FN_SSI_WS0129, FN_CAN0_TX_B, FN_MOUT1, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
+                             1, 2, 3, 3, 4, 3, 3, 3, 3, 4, 3) {
+                /* IP13_31 [1] */
+                0, 0,
+                /* IP13_30_29 [2] */
+                FN_AUDIO_CLKA, FN_SCIFB2_RTS_N, FN_CAN_DEBUGOUT14, 0,
+                /* IP13_28_26 [3] */
+                FN_SSI_SDATA9, FN_STP_ISSYNC_1, FN_SCIFB2_CTS_N, FN_SSI_WS1,
+                FN_SSI_SDATA5_C, FN_CAN_DEBUGOUT13, 0, 0,
+                /* IP13_25_23 [3] */
+                FN_SSI_SDATA8, FN_STP_ISEN_1, FN_SCIFB2_TXD, FN_CAN0_TX_C,
+                FN_CAN_DEBUGOUT12, FN_SSI_SDATA8_B, 0, 0,
+                /* IP13_22_19 [4] */
+                FN_SSI_SDATA7, FN_STP_ISD_1, FN_SCIFB2_RXD, FN_SCIFA2_RTS_N,
+                FN_TCLK2, FN_QSTVA_QVS, FN_CAN_DEBUGOUT11, FN_BPFCLK_E,
+                FN_RDS_CLK_D, FN_SSI_SDATA7_B, FN_FMIN_G, FN_RDS_DATA_F,
+                0, 0, 0, 0,
+                /* IP13_18_16 [3] */
+                FN_SSI_WS78, FN_STP_ISCLK_1, FN_SCIFB2_SCK, FN_SCIFA2_CTS_N,
+                FN_DU2_DR7, FN_LCDOUT7, FN_CAN_DEBUGOUT10, 0,
+                /* IP13_15_13 [3] */
+                FN_SSI_SCK78, FN_STP_IVCXO27_1, FN_SCK1, FN_SCIFA1_SCK,
+                FN_DU2_DR6, FN_LCDOUT6, FN_CAN_DEBUGOUT9, 0,
+                /* IP13_12_10 [3] */
+                FN_SSI_SDATA6, FN_FMIN_D, FN_RDS_DATA_C, FN_DU2_DR5, FN_LCDOUT5,
+                FN_CAN_DEBUGOUT8, 0, 0,
+                /* IP13_9_7 [3] */
+                FN_SSI_WS6, FN_SCIFB1_RTS_N, FN_CAN0_TX_D, FN_DU2_DR4,
+                FN_LCDOUT4, FN_CAN_DEBUGOUT7, 0, 0,
+                /* IP13_6_3 [4] */
+                FN_SSI_SCK6, FN_SCIFB1_CTS_N, FN_BPFCLK_D, FN_RDS_CLK_C,
+                FN_DU2_DR3, FN_LCDOUT3, FN_CAN_DEBUGOUT6,
+                FN_BPFCLK_F, FN_RDS_CLK_E, 0, 0, 0, 0, 0, 0, 0,
+                /* IP13_2_0 [3] */
+                FN_SSI_SDATA5, FN_SCIFB1_TXD, FN_IETX_B, FN_DU2_DR2,
+                FN_LCDOUT2, FN_CAN_DEBUGOUT5, 0, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
+                             1, 3, 3, 3, 3, 3, 4, 3, 3, 3, 3) {
+                /* IP14_30 [1] */
+                0, 0,
+                /* IP14_30_28 [3] */
+                FN_SCIFA1_RTS_N, FN_AD_NCS_N, FN_RTS1_N_TANS,
+                FN_MSIOF3_TXD, FN_DU1_DOTCLKOUT, FN_QSTVB_QVE,
+                FN_HRTS0_N_C, 0,
+                /* IP14_27_25 [3] */
+                FN_SCIFA1_CTS_N, FN_AD_CLK, FN_CTS1_N, FN_MSIOF3_RXD,
+                FN_DU0_DOTCLKOUT, FN_QCLK, 0, 0,
+                /* IP14_24_22 [3] */
+                FN_SCIFA1_TXD, FN_AD_DO, FN_TX1, FN_DU2_DG1,
+                FN_LCDOUT9, 0, 0, 0,
+                /* IP14_21_19 [3] */
+                FN_SCIFA1_RXD, FN_AD_DI, FN_RX1,
+                FN_DU2_EXODDF_DU2_ODDF_DISP_CDE, FN_QCPV_QDE, 0, 0, 0,
+                /* IP14_18_16 [3] */
+                FN_SCIFA0_RTS_N, FN_HRTS1_N, FN_RTS0_N_TANS,
+                FN_MSIOF3_SS1, FN_DU2_DG0, FN_LCDOUT8, FN_PWM1_B, 0,
+                /* IP14_15_12 [4] */
+                FN_SCIFA0_CTS_N, FN_HCTS1_N, FN_CTS0_N, FN_MSIOF3_SYNC,
+                FN_DU2_DG3, FN_LCDOUT11, FN_PWM0_B, FN_SCL1_C, FN_SCL1_CIS_C,
+                0, 0, 0, 0, 0, 0, 0,
+                /* IP14_11_9 [3] */
+                FN_SCIFA0_TXD, FN_HTX1, FN_TX0, FN_DU2_DR1, FN_LCDOUT1,
+                0, 0, 0,
+                /* IP14_8_6 [3] */
+                FN_SCIFA0_RXD, FN_HRX1, FN_RX0, FN_DU2_DR0, FN_LCDOUT0,
+                0, 0, 0,
+                /* IP14_5_3 [3] */
+                FN_SCIFA0_SCK, FN_HSCK1, FN_SCK0, FN_MSIOF3_SS2, FN_DU2_DG2,
+                FN_LCDOUT10, FN_SDA1_C, FN_SDA1_CIS_C,
+                /* IP14_2_0 [3] */
+                FN_AUDIO_CLKB, FN_SCIF_CLK, FN_CAN0_RX_D,
+                FN_DVC_MUTE, FN_CAN0_RX_C, FN_CAN_DEBUGOUT15,
+                FN_REMOCON, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
+                             2, 2, 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3) {
+                /* IP15_31_30 [2] */
+                0, 0, 0, 0,
+                /* IP15_29_28 [2] */
+                FN_MSIOF0_TXD, FN_ADICHS1, FN_DU2_DG6, FN_LCDOUT14,
+                /* IP15_27_26 [2] */
+                FN_MSIOF0_SS1, FN_ADICHS0, FN_DU2_DG5, FN_LCDOUT13,
+                /* IP15_25_23 [3] */
+                FN_MSIOF0_SYNC, FN_TS_SCK0, FN_SSI_SCK2, FN_ADIDATA,
+                FN_DU2_DB7, FN_LCDOUT23, FN_SCIFA2_RXD_B, 0,
+                /* IP15_22_20 [3] */
+                FN_MSIOF0_SCK, FN_TS_SDAT0, FN_ADICLK,
+                FN_DU2_DB6, FN_LCDOUT22, 0, 0, 0,
+                /* IP15_19_18 [2] */
+                FN_HRTS0_N, FN_SSI_WS9, FN_DU2_DB5, FN_LCDOUT21,
+                /* IP15_17_16 [2] */
+                FN_HCTS0_N, FN_SSI_SCK9, FN_DU2_DB4, FN_LCDOUT20,
+                /* IP15_15_14 [2] */
+                FN_HTX0, FN_DU2_DB3, FN_LCDOUT19, 0,
+                /* IP15_13_12 [2] */
+                FN_HRX0, FN_DU2_DB2, FN_LCDOUT18, 0,
+                /* IP15_11_9 [3] */
+                FN_HSCK0, FN_TS_SDEN0, FN_DU2_DG4, FN_LCDOUT12, FN_HCTS0_N_C,
+                0, 0, 0,
+                /* IP15_8_6 [3] */
+                FN_SCIFA2_TXD, FN_BPFCLK, 0, FN_DU2_DB1, FN_LCDOUT17,
+                FN_SDA2, FN_SDA2_CIS, 0,
+                /* IP15_5_3 [3] */
+                FN_SCIFA2_RXD, FN_FMIN, 0, FN_DU2_DB0, FN_LCDOUT16,
+                FN_SCL2, FN_SCL2_CIS, 0,
+                /* IP15_2_0 [3] */
+                FN_SCIFA2_SCK, FN_FMCLK, 0, FN_MSIOF3_SCK, FN_DU2_DG7,
+                FN_LCDOUT15, FN_SCIF_CLK_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
+                             4, 4, 4, 4, 4, 4, 1, 1, 3, 3) {
+                /* IP16_31_28 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_27_24 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_23_20 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_19_16 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_15_12 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_11_8 [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* IP16_7 [1] */
+                FN_USB1_OVC, FN_TCLK1_B,
+                /* IP16_6 [1] */
+                FN_USB1_PWEN, FN_AUDIO_CLKOUT_D,
+                /* IP16_5_3 [3] */
+                FN_MSIOF0_RXD, FN_TS_SPSYNC0, FN_SSI_WS2,
+                FN_ADICS_SAMP, FN_DU2_CDE, FN_QPOLB, FN_HRX0_C, 0,
+                /* IP16_2_0 [3] */
+                FN_MSIOF0_SS2, FN_AUDIO_CLKOUT, FN_ADICHS2,
+                FN_DU2_DISP, FN_QPOLA, FN_HTX0_C, FN_SCIFA2_TXD_B, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
+                             3, 2, 2, 3, 2, 1, 1, 1, 2, 1,
+                             2, 1, 1, 1, 1, 2, 1, 1, 2, 1, 1) {
+                /* SEL_SCIF1 [3] */
+                FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
+                FN_SEL_SCIF1_4, 0, 0, 0,
+                /* SEL_SCIFB [2] */
+                FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, 0,
+                /* SEL_SCIFB2 [2] */
+                FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, 0,
+                /* SEL_SCIFB1 [3] */
+                FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2,
+                FN_SEL_SCIFB1_3, FN_SEL_SCIFB1_4, FN_SEL_SCIFB1_5,
+                FN_SEL_SCIFB1_6, 0,
+                /* SEL_SCIFA1 [2] */
+                FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
+                FN_SEL_SCIFA1_3,
+                /* SEL_SCIF0 [1] */
+                FN_SEL_SCIF0_0, FN_SEL_SCIF0_1,
+                /* SEL_SCIFA [1] */
+                FN_SEL_SCFA_0, FN_SEL_SCFA_1,
+                /* SEL_SOF1 [1] */
+                FN_SEL_SOF1_0, FN_SEL_SOF1_1,
+                /* SEL_SSI7 [2] */
+                FN_SEL_SSI7_0, FN_SEL_SSI7_1, FN_SEL_SSI7_2, 0,
+                /* SEL_SSI6 [1] */
+                FN_SEL_SSI6_0, FN_SEL_SSI6_1,
+                /* SEL_SSI5 [2] */
+                FN_SEL_SSI5_0, FN_SEL_SSI5_1, FN_SEL_SSI5_2, 0,
+                /* SEL_VI3 [1] */
+                FN_SEL_VI3_0, FN_SEL_VI3_1,
+                /* SEL_VI2 [1] */
+                FN_SEL_VI2_0, FN_SEL_VI2_1,
+                /* SEL_VI1 [1] */
+                FN_SEL_VI1_0, FN_SEL_VI1_1,
+                /* SEL_VI0 [1] */
+                FN_SEL_VI0_0, FN_SEL_VI0_1,
+                /* SEL_TSIF1 [2] */
+                FN_SEL_TSIF1_0, FN_SEL_TSIF1_1, FN_SEL_TSIF1_2, 0,
+                /* RESERVED [1] */
+                0, 0,
+                /* SEL_LBS [1] */
+                FN_SEL_LBS_0, FN_SEL_LBS_1,
+                /* SEL_TSIF0 [2] */
+                FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
+                /* SEL_SOF3 [1] */
+                FN_SEL_SOF3_0, FN_SEL_SOF3_1,
+                /* SEL_SOF0 [1] */
+                FN_SEL_SOF0_0, FN_SEL_SOF0_1, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
+                             3, 1, 1, 1, 2, 1, 2, 1, 2,
+                             1, 1, 1, 3, 3, 2, 3, 2, 2) {
+                /* RESERVED [3] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* SEL_TMU1 [1] */
+                FN_SEL_TMU1_0, FN_SEL_TMU1_1,
+                /* SEL_HSCIF1 [1] */
+                FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1,
+                /* SEL_SCIFCLK [1] */
+                FN_SEL_SCIFCLK_0, FN_SEL_SCIFCLK_1,
+                /* SEL_CAN0 [2] */
+                FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
+                /* SEL_CANCLK [1] */
+                FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
+                /* SEL_SCIFA2 [2] */
+                FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1, FN_SEL_SCIFA2_2, 0,
+                /* SEL_CAN1 [1] */
+                FN_SEL_CAN1_0, FN_SEL_CAN1_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* RESERVED [1] (actually TX2, RX2 vs. TX2_B, RX2_B of SCIF2) */
+                0, 0,
+                /* SEL_ADI [1] */
+                FN_SEL_ADI_0, FN_SEL_ADI_1,
+                /* SEL_SSP [1] */
+                FN_SEL_SSP_0, FN_SEL_SSP_1,
+                /* SEL_FM [3] */
+                FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3,
+                FN_SEL_FM_4, FN_SEL_FM_5, FN_SEL_FM_6, 0,
+                /* SEL_HSCIF0 [3] */
+                FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
+                FN_SEL_HSCIF0_3, FN_SEL_HSCIF0_4, FN_SEL_HSCIF0_5, 0, 0,
+                /* SEL_GPS [2] */
+                FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, 0,
+                /* SEL_RDS [3] */
+                FN_SEL_RDS_0, FN_SEL_RDS_1, FN_SEL_RDS_2,
+                FN_SEL_RDS_3, FN_SEL_RDS_4, FN_SEL_RDS_5, 0, 0,
+                /* SEL_SIM [2] */
+                FN_SEL_SIM_0, FN_SEL_SIM_1, FN_SEL_SIM_2, 0,
+                /* SEL_SSI8 [2] */
+                FN_SEL_SSI8_0, FN_SEL_SSI8_1, FN_SEL_SSI8_2, 0, }
+        },
+        { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
+                             1, 1, 2, 4, 4, 2, 2,
+                             4, 2, 3, 2, 3, 2) {
+                /* SEL_IICDVFS [1] */
+                FN_SEL_IICDVFS_0, FN_SEL_IICDVFS_1,
+                /* SEL_IIC0 [1] */
+                FN_SEL_IIC0_0, FN_SEL_IIC0_1,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_IEB [2] */
+                FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
+                /* RESERVED [4] */
+                0, 0, 0, 0, 0, 0, 0, 0,
+                0, 0, 0, 0, 0, 0, 0, 0,
+                /* RESERVED [2] */
+                0, 0, 0, 0,
+                /* SEL_IIC2 [3] */
+                FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
+                FN_SEL_IIC2_4, 0, 0, 0,
+                /* SEL_IIC1 [2] */
+                FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, 0,
+                /* SEL_I2C2 [3] */
+                FN_SEL_I2C2_0, FN_SEL_I2C2_1, FN_SEL_I2C2_2, FN_SEL_I2C2_3,
+                FN_SEL_I2C2_4, 0, 0, 0,
+                /* SEL_I2C1 [2] */
+                FN_SEL_I2C1_0, FN_SEL_I2C1_1, FN_SEL_I2C1_2, 0, }
+        },
+        { },
+};
+
+const struct sh_pfc_soc_info r8a7790_pinmux_info = {
+        .name = "r8a77900_pfc",
+        .unlock_reg = 0xe6060000, /* PMMR */
+
+        .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
+
+        .pins = pinmux_pins,
+        .nr_pins = ARRAY_SIZE(pinmux_pins),
+        .groups = pinmux_groups,
+        .nr_groups = ARRAY_SIZE(pinmux_groups),
+        .functions = pinmux_functions,
+        .nr_functions = ARRAY_SIZE(pinmux_functions),
+
+        .cfg_regs = pinmux_config_regs,
+
+        .gpio_data = pinmux_data,
+        .gpio_data_size = ARRAY_SIZE(pinmux_data),
+};
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index df0ae21a5ac8..6dfb18772574 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -20,10 +20,14 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  */
+#include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/pinctrl/pinconf-generic.h>
+
 #include <mach/irqs.h>
 #include <mach/sh7372.h>
 
+#include "core.h"
 #include "sh_pfc.h"
 
 #define CPU_ALL_PORT(fn, pfx, sfx) \
@@ -34,6 +38,35 @@
         PORT_10(fn, pfx##16, sfx),      PORT_10(fn, pfx##17, sfx), \
         PORT_10(fn, pfx##18, sfx),      PORT_1(fn, pfx##190, sfx)
 
+#undef _GPIO_PORT
+#define _GPIO_PORT(gpio, sfx)                                           \
+        [gpio] = {                                                      \
+                .name = __stringify(PORT##gpio),                        \
+                .enum_id = PORT##gpio##_DATA,                           \
+        }
+
+#define IRQC_PIN_MUX(irq, pin)                                          \
+static const unsigned int intc_irq##irq##_pins[] = {                    \
+        pin,                                                            \
+};                                                                      \
+static const unsigned int intc_irq##irq##_mux[] = {                     \
+        IRQ##irq##_MARK,                                                \
+}
+
+#define IRQC_PINS_MUX(irq, pin0, pin1)                                  \
+static const unsigned int intc_irq##irq##_0_pins[] = {                  \
+        pin0,                                                           \
+};                                                                      \
+static const unsigned int intc_irq##irq##_0_mux[] = {                   \
+        IRQ##irq##_##pin0##_MARK,                                       \
+};                                                                      \
+static const unsigned int intc_irq##irq##_1_pins[] = {                  \
+        pin1,                                                           \
+};                                                                      \
+static const unsigned int intc_irq##irq##_1_mux[] = {                   \
+        IRQ##irq##_##pin1##_MARK,                                       \
+}
+
 enum {
         PINMUX_RESERVED = 0,
 
@@ -47,16 +80,6 @@ enum {
         PORT_ALL(IN),
         PINMUX_INPUT_END,
 
-        /* PORT0_IN_PU -> PORT190_IN_PU */
-        PINMUX_INPUT_PULLUP_BEGIN,
-        PORT_ALL(IN_PU),
-        PINMUX_INPUT_PULLUP_END,
-
-        /* PORT0_IN_PD -> PORT190_IN_PD */
-        PINMUX_INPUT_PULLDOWN_BEGIN,
-        PORT_ALL(IN_PD),
-        PINMUX_INPUT_PULLDOWN_END,
-
         /* PORT0_OUT -> PORT190_OUT */
         PINMUX_OUTPUT_BEGIN,
         PORT_ALL(OUT),
@@ -368,124 +391,11 @@ enum {
         PINMUX_MARK_END,
 };
 
-static const pinmux_enum_t pinmux_data[] = {
+#define _PORT_DATA(pfx, sfx)    PORT_DATA_IO(pfx)
+#define PINMUX_DATA_GP_ALL()    CPU_ALL_PORT(_PORT_DATA, , unused)
 
-        /* specify valid pin states for each pin in GPIO mode */
-        PORT_DATA_IO_PD(0),             PORT_DATA_IO_PD(1),
-        PORT_DATA_O(2),                 PORT_DATA_I_PD(3),
-        PORT_DATA_I_PD(4),              PORT_DATA_I_PD(5),
-        PORT_DATA_IO_PU_PD(6),          PORT_DATA_I_PD(7),
-        PORT_DATA_IO_PD(8),             PORT_DATA_O(9),
-
-        PORT_DATA_O(10),                PORT_DATA_O(11),
-        PORT_DATA_IO_PU_PD(12),         PORT_DATA_IO_PD(13),
-        PORT_DATA_IO_PD(14),            PORT_DATA_O(15),
-        PORT_DATA_IO_PD(16),            PORT_DATA_IO_PD(17),
-        PORT_DATA_I_PD(18),             PORT_DATA_IO(19),
-
-        PORT_DATA_IO(20),               PORT_DATA_IO(21),
-        PORT_DATA_IO(22),               PORT_DATA_IO(23),
-        PORT_DATA_IO(24),               PORT_DATA_IO(25),
-        PORT_DATA_IO(26),               PORT_DATA_IO(27),
-        PORT_DATA_IO(28),               PORT_DATA_IO(29),
-
-        PORT_DATA_IO(30),               PORT_DATA_IO(31),
-        PORT_DATA_IO(32),               PORT_DATA_IO(33),
-        PORT_DATA_IO(34),               PORT_DATA_IO(35),
-        PORT_DATA_IO(36),               PORT_DATA_IO(37),
-        PORT_DATA_IO(38),               PORT_DATA_IO(39),
-
-        PORT_DATA_IO(40),               PORT_DATA_IO(41),
-        PORT_DATA_IO(42),               PORT_DATA_IO(43),
-        PORT_DATA_IO(44),               PORT_DATA_IO(45),
-        PORT_DATA_IO_PU(46),            PORT_DATA_IO_PU(47),
-        PORT_DATA_IO_PU(48),            PORT_DATA_IO_PU(49),
-
-        PORT_DATA_IO_PU(50),            PORT_DATA_IO_PU(51),
-        PORT_DATA_IO_PU(52),            PORT_DATA_IO_PU(53),
-        PORT_DATA_IO_PU(54),            PORT_DATA_IO_PU(55),
-        PORT_DATA_IO_PU(56),            PORT_DATA_IO_PU(57),
-        PORT_DATA_IO_PU(58),            PORT_DATA_IO_PU(59),
-
-        PORT_DATA_IO_PU(60),            PORT_DATA_IO_PU(61),
-        PORT_DATA_IO(62),               PORT_DATA_O(63),
-        PORT_DATA_O(64),                PORT_DATA_IO_PU(65),
-        PORT_DATA_O(66),                PORT_DATA_IO_PU(67),  /*66?*/
-        PORT_DATA_O(68),                PORT_DATA_IO(69),
-
-        PORT_DATA_IO(70),               PORT_DATA_IO(71),
-        PORT_DATA_O(72),                PORT_DATA_I_PU(73),
-        PORT_DATA_I_PU_PD(74),          PORT_DATA_IO_PU_PD(75),
-        PORT_DATA_IO_PU_PD(76),         PORT_DATA_IO_PU_PD(77),
-        PORT_DATA_IO_PU_PD(78),         PORT_DATA_IO_PU_PD(79),
-
-        PORT_DATA_IO_PU_PD(80),         PORT_DATA_IO_PU_PD(81),
-        PORT_DATA_IO_PU_PD(82),         PORT_DATA_IO_PU_PD(83),
-        PORT_DATA_IO_PU_PD(84),         PORT_DATA_IO_PU_PD(85),
-        PORT_DATA_IO_PU_PD(86),         PORT_DATA_IO_PU_PD(87),
-        PORT_DATA_IO_PU_PD(88),         PORT_DATA_IO_PU_PD(89),
-
-        PORT_DATA_IO_PU_PD(90),         PORT_DATA_IO_PU_PD(91),
-        PORT_DATA_IO_PU_PD(92),         PORT_DATA_IO_PU_PD(93),
-        PORT_DATA_IO_PU_PD(94),         PORT_DATA_IO_PU_PD(95),
-        PORT_DATA_IO_PU(96),            PORT_DATA_IO_PU_PD(97),
-        PORT_DATA_IO_PU_PD(98),         PORT_DATA_O(99), /*99?*/
-
-        PORT_DATA_IO_PD(100),           PORT_DATA_IO_PD(101),
-        PORT_DATA_IO_PD(102),           PORT_DATA_IO_PD(103),
-        PORT_DATA_IO_PD(104),           PORT_DATA_IO_PD(105),
-        PORT_DATA_IO_PU(106),           PORT_DATA_IO_PU(107),
-        PORT_DATA_IO_PU(108),           PORT_DATA_IO_PU(109),
-
-        PORT_DATA_IO_PU(110),           PORT_DATA_IO_PU(111),
-        PORT_DATA_IO_PD(112),           PORT_DATA_IO_PD(113),
-        PORT_DATA_IO_PU(114),           PORT_DATA_IO_PU(115),
-        PORT_DATA_IO_PU(116),           PORT_DATA_IO_PU(117),
-        PORT_DATA_IO_PU(118),           PORT_DATA_IO_PU(119),
-
-        PORT_DATA_IO_PU(120),           PORT_DATA_IO_PD(121),
-        PORT_DATA_IO_PD(122),           PORT_DATA_IO_PD(123),
-        PORT_DATA_IO_PD(124),           PORT_DATA_IO_PD(125),
-        PORT_DATA_IO_PD(126),           PORT_DATA_IO_PD(127),
-        PORT_DATA_IO_PD(128),           PORT_DATA_IO_PU_PD(129),
-
-        PORT_DATA_IO_PU_PD(130),        PORT_DATA_IO_PU_PD(131),
-        PORT_DATA_IO_PU_PD(132),        PORT_DATA_IO_PU_PD(133),
-        PORT_DATA_IO_PU_PD(134),        PORT_DATA_IO_PU_PD(135),
-        PORT_DATA_IO_PD(136),           PORT_DATA_IO_PD(137),
-        PORT_DATA_IO_PD(138),           PORT_DATA_IO_PD(139),
-
-        PORT_DATA_IO_PD(140),           PORT_DATA_IO_PD(141),
-        PORT_DATA_IO_PD(142),           PORT_DATA_IO_PU_PD(143),
-        PORT_DATA_IO_PD(144),           PORT_DATA_IO_PD(145),
-        PORT_DATA_IO_PD(146),           PORT_DATA_IO_PD(147),
-        PORT_DATA_IO_PD(148),           PORT_DATA_IO_PD(149),
-
-        PORT_DATA_IO_PD(150),           PORT_DATA_IO_PD(151),
-        PORT_DATA_IO_PU_PD(152),        PORT_DATA_I_PD(153),
-        PORT_DATA_IO_PU_PD(154),        PORT_DATA_I_PD(155),
-        PORT_DATA_IO_PD(156),           PORT_DATA_IO_PD(157),
-        PORT_DATA_I_PD(158),            PORT_DATA_IO_PD(159),
-
-        PORT_DATA_O(160),               PORT_DATA_IO_PD(161),
-        PORT_DATA_IO_PD(162),           PORT_DATA_IO_PD(163),
-        PORT_DATA_I_PD(164),            PORT_DATA_IO_PD(165),
-        PORT_DATA_I_PD(166),            PORT_DATA_I_PD(167),
-        PORT_DATA_I_PD(168),            PORT_DATA_I_PD(169),
-
-        PORT_DATA_I_PD(170),            PORT_DATA_O(171),
-        PORT_DATA_IO_PU_PD(172),        PORT_DATA_IO_PU_PD(173),
-        PORT_DATA_IO_PU_PD(174),        PORT_DATA_IO_PU_PD(175),
-        PORT_DATA_IO_PU_PD(176),        PORT_DATA_IO_PU_PD(177),
-        PORT_DATA_IO_PU_PD(178),        PORT_DATA_O(179),
-
-        PORT_DATA_IO_PU_PD(180),        PORT_DATA_IO_PU_PD(181),
-        PORT_DATA_IO_PU_PD(182),        PORT_DATA_IO_PU_PD(183),
-        PORT_DATA_IO_PU_PD(184),        PORT_DATA_O(185),
-        PORT_DATA_IO_PU_PD(186),        PORT_DATA_IO_PU_PD(187),
-        PORT_DATA_IO_PU_PD(188),        PORT_DATA_IO_PU_PD(189),
-
-        PORT_DATA_IO_PU_PD(190),
+static const pinmux_enum_t pinmux_data[] = {
+        PINMUX_DATA_GP_ALL(),
 
         /* IRQ */
         PINMUX_DATA(IRQ0_6_MARK,        PORT6_FN0,      MSEL1CR_0_0),
@@ -929,10 +839,582 @@ static const pinmux_enum_t pinmux_data[] = {
         PINMUX_DATA(MFIv4_MARK,         MSEL4CR_6_1),
 };
 
+#define SH7372_PIN(pin, cfgs)                                           \
+        {                                                               \
+                .name = __stringify(PORT##pin),                         \
+                .enum_id = PORT##pin##_DATA,                            \
+                .configs = cfgs,                                        \
+        }
+
+#define __I             (SH_PFC_PIN_CFG_INPUT)
+#define __O             (SH_PFC_PIN_CFG_OUTPUT)
+#define __IO            (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
+#define __PD            (SH_PFC_PIN_CFG_PULL_DOWN)
+#define __PU            (SH_PFC_PIN_CFG_PULL_UP)
+#define __PUD           (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
+
+#define SH7372_PIN_I_PD(pin)            SH7372_PIN(pin, __I | __PD)
+#define SH7372_PIN_I_PU(pin)            SH7372_PIN(pin, __I | __PU)
+#define SH7372_PIN_I_PU_PD(pin)         SH7372_PIN(pin, __I | __PUD)
+#define SH7372_PIN_IO(pin)              SH7372_PIN(pin, __IO)
+#define SH7372_PIN_IO_PD(pin)           SH7372_PIN(pin, __IO | __PD)
+#define SH7372_PIN_IO_PU(pin)           SH7372_PIN(pin, __IO | __PU)
+#define SH7372_PIN_IO_PU_PD(pin)        SH7372_PIN(pin, __IO | __PUD)
+#define SH7372_PIN_O(pin)               SH7372_PIN(pin, __O)
+#define SH7372_PIN_O_PU_PD(pin)         SH7372_PIN(pin, __O | __PUD)
+
 static struct sh_pfc_pin pinmux_pins[] = {
-        GPIO_PORT_ALL(),
+        /* Table 57-1 (I/O and Pull U/D) */
+        SH7372_PIN_IO_PD(0),            SH7372_PIN_IO_PD(1),
+        SH7372_PIN_O(2),                SH7372_PIN_I_PD(3),
+        SH7372_PIN_I_PD(4),             SH7372_PIN_I_PD(5),
+        SH7372_PIN_IO_PU_PD(6),         SH7372_PIN_I_PD(7),
+        SH7372_PIN_IO_PD(8),            SH7372_PIN_O(9),
+        SH7372_PIN_O(10),               SH7372_PIN_O(11),
+        SH7372_PIN_IO_PU_PD(12),        SH7372_PIN_IO_PD(13),
+        SH7372_PIN_IO_PD(14),           SH7372_PIN_O(15),
+        SH7372_PIN_IO_PD(16),           SH7372_PIN_IO_PD(17),
+        SH7372_PIN_I_PD(18),            SH7372_PIN_IO(19),
+        SH7372_PIN_IO(20),              SH7372_PIN_IO(21),
+        SH7372_PIN_IO(22),              SH7372_PIN_IO(23),
+        SH7372_PIN_IO(24),              SH7372_PIN_IO(25),
+        SH7372_PIN_IO(26),              SH7372_PIN_IO(27),
+        SH7372_PIN_IO(28),              SH7372_PIN_IO(29),
+        SH7372_PIN_IO(30),              SH7372_PIN_IO(31),
+        SH7372_PIN_IO(32),              SH7372_PIN_IO(33),
+        SH7372_PIN_IO(34),              SH7372_PIN_IO(35),
+        SH7372_PIN_IO(36),              SH7372_PIN_IO(37),
+        SH7372_PIN_IO(38),              SH7372_PIN_IO(39),
+        SH7372_PIN_IO(40),              SH7372_PIN_IO(41),
+        SH7372_PIN_IO(42),              SH7372_PIN_IO(43),
+        SH7372_PIN_IO(44),              SH7372_PIN_IO(45),
+        SH7372_PIN_IO_PU(46),           SH7372_PIN_IO_PU(47),
+        SH7372_PIN_IO_PU(48),           SH7372_PIN_IO_PU(49),
+        SH7372_PIN_IO_PU(50),           SH7372_PIN_IO_PU(51),
+        SH7372_PIN_IO_PU(52),           SH7372_PIN_IO_PU(53),
+        SH7372_PIN_IO_PU(54),           SH7372_PIN_IO_PU(55),
+        SH7372_PIN_IO_PU(56),           SH7372_PIN_IO_PU(57),
+        SH7372_PIN_IO_PU(58),           SH7372_PIN_IO_PU(59),
+        SH7372_PIN_IO_PU(60),           SH7372_PIN_IO_PU(61),
+        SH7372_PIN_IO(62),              SH7372_PIN_O(63),
+        SH7372_PIN_O(64),               SH7372_PIN_IO_PU(65),
+        SH7372_PIN_O_PU_PD(66),         SH7372_PIN_IO_PU(67),
+        SH7372_PIN_O(68),               SH7372_PIN_IO(69),
+        SH7372_PIN_IO(70),              SH7372_PIN_IO(71),
+        SH7372_PIN_O(72),               SH7372_PIN_I_PU(73),
+        SH7372_PIN_I_PU_PD(74),         SH7372_PIN_IO_PU_PD(75),
+        SH7372_PIN_IO_PU_PD(76),        SH7372_PIN_IO_PU_PD(77),
+        SH7372_PIN_IO_PU_PD(78),        SH7372_PIN_IO_PU_PD(79),
+        SH7372_PIN_IO_PU_PD(80),        SH7372_PIN_IO_PU_PD(81),
+        SH7372_PIN_IO_PU_PD(82),        SH7372_PIN_IO_PU_PD(83),
+        SH7372_PIN_IO_PU_PD(84),        SH7372_PIN_IO_PU_PD(85),
+        SH7372_PIN_IO_PU_PD(86),        SH7372_PIN_IO_PU_PD(87),
+        SH7372_PIN_IO_PU_PD(88),        SH7372_PIN_IO_PU_PD(89),
+        SH7372_PIN_IO_PU_PD(90),        SH7372_PIN_IO_PU_PD(91),
+        SH7372_PIN_IO_PU_PD(92),        SH7372_PIN_IO_PU_PD(93),
+        SH7372_PIN_IO_PU_PD(94),        SH7372_PIN_IO_PU_PD(95),
+        SH7372_PIN_IO_PU(96),           SH7372_PIN_IO_PU_PD(97),
+        SH7372_PIN_IO_PU_PD(98),        SH7372_PIN_O_PU_PD(99),
+        SH7372_PIN_IO_PD(100),          SH7372_PIN_IO_PD(101),
+        SH7372_PIN_IO_PD(102),          SH7372_PIN_IO_PD(103),
+        SH7372_PIN_IO_PD(104),          SH7372_PIN_IO_PD(105),
+        SH7372_PIN_IO_PU(106),          SH7372_PIN_IO_PU(107),
+        SH7372_PIN_IO_PU(108),          SH7372_PIN_IO_PU(109),
+        SH7372_PIN_IO_PU(110),          SH7372_PIN_IO_PU(111),
+        SH7372_PIN_IO_PD(112),          SH7372_PIN_IO_PD(113),
+        SH7372_PIN_IO_PU(114),          SH7372_PIN_IO_PU(115),
+        SH7372_PIN_IO_PU(116),          SH7372_PIN_IO_PU(117),
+        SH7372_PIN_IO_PU(118),          SH7372_PIN_IO_PU(119),
+        SH7372_PIN_IO_PU(120),          SH7372_PIN_IO_PD(121),
+        SH7372_PIN_IO_PD(122),          SH7372_PIN_IO_PD(123),
+        SH7372_PIN_IO_PD(124),          SH7372_PIN_IO_PD(125),
+        SH7372_PIN_IO_PD(126),          SH7372_PIN_IO_PD(127),
+        SH7372_PIN_IO_PD(128),          SH7372_PIN_IO_PU_PD(129),
+        SH7372_PIN_IO_PU_PD(130),       SH7372_PIN_IO_PU_PD(131),
+        SH7372_PIN_IO_PU_PD(132),       SH7372_PIN_IO_PU_PD(133),
+        SH7372_PIN_IO_PU_PD(134),       SH7372_PIN_IO_PU_PD(135),
+        SH7372_PIN_IO_PD(136),          SH7372_PIN_IO_PD(137),
+        SH7372_PIN_IO_PD(138),          SH7372_PIN_IO_PD(139),
+        SH7372_PIN_IO_PD(140),          SH7372_PIN_IO_PD(141),
+        SH7372_PIN_IO_PD(142),          SH7372_PIN_IO_PU_PD(143),
+        SH7372_PIN_IO_PD(144),          SH7372_PIN_IO_PD(145),
+        SH7372_PIN_IO_PD(146),          SH7372_PIN_IO_PD(147),
+        SH7372_PIN_IO_PD(148),          SH7372_PIN_IO_PD(149),
+        SH7372_PIN_IO_PD(150),          SH7372_PIN_IO_PD(151),
+        SH7372_PIN_IO_PU_PD(152),       SH7372_PIN_I_PD(153),
+        SH7372_PIN_IO_PU_PD(154),       SH7372_PIN_I_PD(155),
+        SH7372_PIN_IO_PD(156),          SH7372_PIN_IO_PD(157),
+        SH7372_PIN_I_PD(158),           SH7372_PIN_IO_PD(159),
+        SH7372_PIN_O(160),              SH7372_PIN_IO_PD(161),
+        SH7372_PIN_IO_PD(162),          SH7372_PIN_IO_PD(163),
+        SH7372_PIN_I_PD(164),           SH7372_PIN_IO_PD(165),
+        SH7372_PIN_I_PD(166),           SH7372_PIN_I_PD(167),
+        SH7372_PIN_I_PD(168),           SH7372_PIN_I_PD(169),
+        SH7372_PIN_I_PD(170),           SH7372_PIN_O(171),
+        SH7372_PIN_IO_PU_PD(172),       SH7372_PIN_IO_PU_PD(173),
+        SH7372_PIN_IO_PU_PD(174),       SH7372_PIN_IO_PU_PD(175),
+        SH7372_PIN_IO_PU_PD(176),       SH7372_PIN_IO_PU_PD(177),
+        SH7372_PIN_IO_PU_PD(178),       SH7372_PIN_O(179),
+        SH7372_PIN_IO_PU_PD(180),       SH7372_PIN_IO_PU_PD(181),
+        SH7372_PIN_IO_PU_PD(182),       SH7372_PIN_IO_PU_PD(183),
+        SH7372_PIN_IO_PU_PD(184),       SH7372_PIN_O(185),
+        SH7372_PIN_IO_PU_PD(186),       SH7372_PIN_IO_PU_PD(187),
+        SH7372_PIN_IO_PU_PD(188),       SH7372_PIN_IO_PU_PD(189),
+        SH7372_PIN_IO_PU_PD(190),
 };
 
+/* - BSC -------------------------------------------------------------------- */
+static const unsigned int bsc_data8_pins[] = {
+        /* D[0:7] */
+        46, 47, 48, 49, 50, 51, 52, 53,
+};
+static const unsigned int bsc_data8_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+};
+static const unsigned int bsc_data16_pins[] = {
+        /* D[0:15] */
+        46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int bsc_data16_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int bsc_cs0_pins[] = {
+        /* CS */
+        62,
+};
+static const unsigned int bsc_cs0_mux[] = {
+        CS0_MARK,
+};
+static const unsigned int bsc_cs2_pins[] = {
+        /* CS */
+        63,
+};
+static const unsigned int bsc_cs2_mux[] = {
+        CS2_MARK,
+};
+static const unsigned int bsc_cs4_pins[] = {
+        /* CS */
+        64,
+};
+static const unsigned int bsc_cs4_mux[] = {
+        CS4_MARK,
+};
+static const unsigned int bsc_cs5a_pins[] = {
+        /* CS */
+        65,
+};
+static const unsigned int bsc_cs5a_mux[] = {
+        CS5A_MARK,
+};
+static const unsigned int bsc_cs5b_pins[] = {
+        /* CS */
+        66,
+};
+static const unsigned int bsc_cs5b_mux[] = {
+        CS5B_MARK,
+};
+static const unsigned int bsc_cs6a_pins[] = {
+        /* CS */
+        67,
+};
+static const unsigned int bsc_cs6a_mux[] = {
+        CS6A_MARK,
+};
+static const unsigned int bsc_rd_we8_pins[] = {
+        /* RD, WE[0] */
+        69, 70,
+};
+static const unsigned int bsc_rd_we8_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK,
+};
+static const unsigned int bsc_rd_we16_pins[] = {
+        /* RD, WE[0:1] */
+        69, 70, 71,
+};
+static const unsigned int bsc_rd_we16_mux[] = {
+        RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
+};
+static const unsigned int bsc_bs_pins[] = {
+        /* BS */
+        19,
+};
+static const unsigned int bsc_bs_mux[] = {
+        BS_MARK,
+};
+static const unsigned int bsc_rdwr_pins[] = {
+        /* RDWR */
+        75,
+};
+static const unsigned int bsc_rdwr_mux[] = {
+        RDWR_MARK,
+};
+static const unsigned int bsc_wait_pins[] = {
+        /* WAIT */
+        74,
+};
+static const unsigned int bsc_wait_mux[] = {
+        WAIT_MARK,
+};
+/* - CEU -------------------------------------------------------------------- */
+static const unsigned int ceu_data_0_7_pins[] = {
+        /* D[0:7] */
+        102, 103, 104, 105, 106, 107, 108, 109,
+};
+static const unsigned int ceu_data_0_7_mux[] = {
+        VIO_D0_MARK, VIO_D1_MARK, VIO_D2_MARK, VIO_D3_MARK,
+        VIO_D4_MARK, VIO_D5_MARK, VIO_D6_MARK, VIO_D7_MARK,
+};
+static const unsigned int ceu_data_8_15_pins[] = {
+        /* D[8:15] */
+        110, 111, 112, 113, 114, 115, 116, 117,
+};
+static const unsigned int ceu_data_8_15_mux[] = {
+        VIO_D8_MARK, VIO_D9_MARK, VIO_D10_MARK, VIO_D11_MARK,
+        VIO_D12_MARK, VIO_D13_MARK, VIO_D14_MARK, VIO_D15_MARK,
+};
+static const unsigned int ceu_clk_0_pins[] = {
+        /* CKO */
+        120,
+};
+static const unsigned int ceu_clk_0_mux[] = {
+        VIO_CKO_MARK,
+};
+static const unsigned int ceu_clk_1_pins[] = {
+        /* CKO */
+        16,
+};
+static const unsigned int ceu_clk_1_mux[] = {
+        VIO_CKO1_MARK,
+};
+static const unsigned int ceu_clk_2_pins[] = {
+        /* CKO */
+        17,
+};
+static const unsigned int ceu_clk_2_mux[] = {
+        VIO_CKO2_MARK,
+};
+static const unsigned int ceu_sync_pins[] = {
+        /* CLK, VD, HD */
+        118, 100, 101,
+};
+static const unsigned int ceu_sync_mux[] = {
+        VIO_CLK_MARK, VIO_VD_MARK, VIO_HD_MARK,
+};
+static const unsigned int ceu_field_pins[] = {
+        /* FIELD */
+        119,
+};
+static const unsigned int ceu_field_mux[] = {
+        VIO_FIELD_MARK,
+};
+/* - FLCTL ------------------------------------------------------------------ */
+static const unsigned int flctl_data_pins[] = {
+        /* NAF[0:15] */
+        46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+};
+static const unsigned int flctl_data_mux[] = {
+        D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
+        D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
+        D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
+        D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
+};
+static const unsigned int flctl_ce0_pins[] = {
+        /* CE */
+        68,
+};
+static const unsigned int flctl_ce0_mux[] = {
+        FCE0_MARK,
+};
+static const unsigned int flctl_ce1_pins[] = {
+        /* CE */
+        66,
+};
+static const unsigned int flctl_ce1_mux[] = {
+        FCE1_MARK,
+};
+static const unsigned int flctl_ctrl_pins[] = {
+        /* FCDE, FOE, FSC, FWE, FRB */
+        24, 23, 69, 70, 73,
+};
+static const unsigned int flctl_ctrl_mux[] = {
+        A5_FCDE_MARK, A4_FOE_MARK, RD_FSC_MARK, WE0_FWE_MARK, FRB_MARK,
+};
+/* - FSIA ------------------------------------------------------------------- */
+static const unsigned int fsia_mclk_in_pins[] = {
+        /* CK */
+        4,
+};
+static const unsigned int fsia_mclk_in_mux[] = {
+        FSIACK_MARK,
+};
+static const unsigned int fsia_mclk_out_pins[] = {
+        /* OMC */
+        8,
+};
+static const unsigned int fsia_mclk_out_mux[] = {
+        FSIAOMC_MARK,
+};
+static const unsigned int fsia_sclk_in_pins[] = {
+        /* ILR, IBT */
+        5, 6,
+};
+static const unsigned int fsia_sclk_in_mux[] = {
+        FSIAILR_MARK, FSIAIBT_MARK,
+};
+static const unsigned int fsia_sclk_out_pins[] = {
+        /* OLR, OBT */
+        9, 10,
+};
+static const unsigned int fsia_sclk_out_mux[] = {
+        FSIAOLR_MARK, FSIAOBT_MARK,
+};
+static const unsigned int fsia_data_in_pins[] = {
+        /* ISLD */
+        7,
+};
+static const unsigned int fsia_data_in_mux[] = {
+        FSIAISLD_MARK,
+};
+static const unsigned int fsia_data_out_pins[] = {
+        /* OSLD */
+        11,
+};
+static const unsigned int fsia_data_out_mux[] = {
+        FSIAOSLD_MARK,
+};
+static const unsigned int fsia_spdif_0_pins[] = {
+        /* SPDIF */
+        11,
+};
+static const unsigned int fsia_spdif_0_mux[] = {
+        FSIASPDIF_11_MARK,
+};
+static const unsigned int fsia_spdif_1_pins[] = {
+        /* SPDIF */
+        15,
+};
+static const unsigned int fsia_spdif_1_mux[] = {
+        FSIASPDIF_15_MARK,
+};
+/* - FSIB ------------------------------------------------------------------- */
+static const unsigned int fsib_mclk_in_pins[] = {
+        /* CK */
+        4,
+};
+static const unsigned int fsib_mclk_in_mux[] = {
+        FSIBCK_MARK,
+};
+/* - HDMI ------------------------------------------------------------------- */
+static const unsigned int hdmi_pins[] = {
+        /* HPD, CEC */
+        169, 170,
+};
+static const unsigned int hdmi_mux[] = {
+        HDMI_HPD_MARK, HDMI_CEC_MARK,
+};
+/* - INTC ------------------------------------------------------------------- */
+IRQC_PINS_MUX(0, 6, 162);
+IRQC_PIN_MUX(1, 12);
+IRQC_PINS_MUX(2, 4, 5);
+IRQC_PINS_MUX(3, 8, 16);
+IRQC_PINS_MUX(4, 17, 163);
+IRQC_PIN_MUX(5, 18);
+IRQC_PINS_MUX(6, 39, 164);
+IRQC_PINS_MUX(7, 40, 167);
+IRQC_PINS_MUX(8, 41, 168);
+IRQC_PINS_MUX(9, 42, 169);
+IRQC_PIN_MUX(10, 65);
+IRQC_PIN_MUX(11, 67);
+IRQC_PINS_MUX(12, 80, 137);
+IRQC_PINS_MUX(13, 81, 145);
+IRQC_PINS_MUX(14, 82, 146);
+IRQC_PINS_MUX(15, 83, 147);
+IRQC_PINS_MUX(16, 84, 170);
+IRQC_PIN_MUX(17, 85);
+IRQC_PIN_MUX(18, 86);
+IRQC_PIN_MUX(19, 87);
+IRQC_PIN_MUX(20, 92);
+IRQC_PIN_MUX(21, 93);
+IRQC_PIN_MUX(22, 94);
+IRQC_PIN_MUX(23, 95);
+IRQC_PIN_MUX(24, 112);
+IRQC_PIN_MUX(25, 119);
+IRQC_PINS_MUX(26, 121, 172);
+IRQC_PINS_MUX(27, 122, 180);
+IRQC_PINS_MUX(28, 123, 181);
+IRQC_PINS_MUX(29, 129, 182);
+IRQC_PINS_MUX(30, 130, 183);
+IRQC_PINS_MUX(31, 138, 184);
+/* - KEYSC ------------------------------------------------------------------ */
+static const unsigned int keysc_in04_0_pins[] = {
+        /* KEYIN[0:4] */
+        136, 135, 134, 133, 132,
+};
+static const unsigned int keysc_in04_0_mux[] = {
+        KEYIN0_136_MARK, KEYIN1_135_MARK, KEYIN2_134_MARK, KEYIN3_133_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in04_1_pins[] = {
+        /* KEYIN[0:4] */
+        121, 122, 123, 124, 132,
+};
+static const unsigned int keysc_in04_1_mux[] = {
+        KEYIN0_121_MARK, KEYIN1_122_MARK, KEYIN2_123_MARK, KEYIN3_124_MARK,
+        KEYIN4_MARK,
+};
+static const unsigned int keysc_in5_pins[] = {
+        /* KEYIN5 */
+        131,
+};
+static const unsigned int keysc_in5_mux[] = {
+        KEYIN5_MARK,
+};
+static const unsigned int keysc_in6_pins[] = {
+        /* KEYIN6 */
+        130,
+};
+static const unsigned int keysc_in6_mux[] = {
+        KEYIN6_MARK,
+};
+static const unsigned int keysc_in7_pins[] = {
+        /* KEYIN7 */
+        129,
+};
+static const unsigned int keysc_in7_mux[] = {
+        KEYIN7_MARK,
+};
+static const unsigned int keysc_out4_pins[] = {
+        /* KEYOUT[0:3] */
+        128, 127, 126, 125,
+};
+static const unsigned int keysc_out4_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+};
+static const unsigned int keysc_out5_pins[] = {
+        /* KEYOUT[0:4] */
+        128, 127, 126, 125, 124,
+};
+static const unsigned int keysc_out5_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK,
+};
+static const unsigned int keysc_out6_pins[] = {
+        /* KEYOUT[0:5] */
+        128, 127, 126, 125, 124, 123,
+};
+static const unsigned int keysc_out6_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK, KEYOUT5_MARK,
+};
+static const unsigned int keysc_out8_pins[] = {
+        /* KEYOUT[0:7] */
+        128, 127, 126, 125, 124, 123, 122, 121,
+};
+static const unsigned int keysc_out8_mux[] = {
+        KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
+        KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
+};
+/* - LCD -------------------------------------------------------------------- */
+static const unsigned int lcd_data8_pins[] = {
+        /* D[0:7] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+};
+static const unsigned int lcd_data8_mux[] = {
+        /* LCDC */
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+};
+static const unsigned int lcd_data9_pins[] = {
+        /* D[0:8] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129,
+        137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data9_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK,
+};
+static const unsigned int lcd_data12_pins[] = {
+        /* D[0:11] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132,
+};
+static const unsigned int lcd_data12_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+};
+static const unsigned int lcd_data16_pins[] = {
+        /* D[0:15] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+};
+static const unsigned int lcd_data16_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+};
+static const unsigned int lcd_data18_pins[] = {
+        /* D[0:17] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+        137, 138,
+};
+static const unsigned int lcd_data18_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK,
+};
+static const unsigned int lcd_data24_pins[] = {
+        /* D[0:23] */
+        121, 122, 123, 124, 125, 126, 127, 128,
+        129, 130, 131, 132, 133, 134, 135, 136,
+        137, 138, 139, 140, 141, 142, 143, 144,
+};
+static const unsigned int lcd_data24_mux[] = {
+        LCDD0_MARK, LCDD1_MARK, LCDD2_MARK, LCDD3_MARK,
+        LCDD4_MARK, LCDD5_MARK, LCDD6_MARK, LCDD7_MARK,
+        LCDD8_MARK, LCDD9_MARK, LCDD10_MARK, LCDD11_MARK,
+        LCDD12_MARK, LCDD13_MARK, LCDD14_MARK, LCDD15_MARK,
+        LCDD16_MARK, LCDD17_MARK, LCDD18_MARK, LCDD19_MARK,
+        LCDD20_MARK, LCDD21_MARK, LCDD22_MARK, LCDD23_MARK,
+};
+static const unsigned int lcd_display_pins[] = {
+        /* DON */
+        151,
+};
+static const unsigned int lcd_display_mux[] = {
+        LCDDON_MARK,
+};
+static const unsigned int lcd_lclk_pins[] = {
+        /* LCLK */
+        150,
+};
+static const unsigned int lcd_lclk_mux[] = {
+        LCDLCLK_MARK,
+};
+static const unsigned int lcd_sync_pins[] = {
+        /* VSYN, HSYN, DCK, DISP */
+        146, 145, 147, 149,
+};
+static const unsigned int lcd_sync_mux[] = {
+        LCDVSYN_MARK, LCDHSYN_MARK, LCDDCK_MARK, LCDDISP_MARK,
+};
+static const unsigned int lcd_sys_pins[] = {
+        /* CS, WR, RD, RS */
+        145, 147, 148, 149,
+};
+static const unsigned int lcd_sys_mux[] = {
+        LCDCS_MARK, LCDWR_MARK, LCDRD_MARK, LCDRS_MARK,
+};
 /* - MMCIF ------------------------------------------------------------------ */
 static const unsigned int mmc0_data1_0_pins[] = {
         /* D[0] */
@@ -993,6 +1475,139 @@ static const unsigned int mmc0_ctrl_1_pins[] = {
 static const unsigned int mmc0_ctrl_1_mux[] = {
         MMCCMD1_MARK, MMCCLK1_MARK,
 };
+/* - SCIFA0 ----------------------------------------------------------------- */
+static const unsigned int scifa0_data_pins[] = {
+        /* RXD, TXD */
+        153, 152,
+};
+static const unsigned int scifa0_data_mux[] = {
+        SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
+};
+static const unsigned int scifa0_clk_pins[] = {
+        /* SCK */
+        156,
+};
+static const unsigned int scifa0_clk_mux[] = {
+        SCIFA0_SCK_MARK,
+};
+static const unsigned int scifa0_ctrl_pins[] = {
+        /* RTS, CTS */
+        157, 158,
+};
+static const unsigned int scifa0_ctrl_mux[] = {
+        SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
+};
+/* - SCIFA1 ----------------------------------------------------------------- */
+static const unsigned int scifa1_data_pins[] = {
+        /* RXD, TXD */
+        155, 154,
+};
+static const unsigned int scifa1_data_mux[] = {
+        SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
+};
+static const unsigned int scifa1_clk_pins[] = {
+        /* SCK */
+        159,
+};
+static const unsigned int scifa1_clk_mux[] = {
+        SCIFA1_SCK_MARK,
+};
+static const unsigned int scifa1_ctrl_pins[] = {
+        /* RTS, CTS */
+        160, 161,
+};
+static const unsigned int scifa1_ctrl_mux[] = {
+        SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
+};
+/* - SCIFA2 ----------------------------------------------------------------- */
+static const unsigned int scifa2_data_pins[] = {
+        /* RXD, TXD */
+        97, 96,
+};
+static const unsigned int scifa2_data_mux[] = {
+        SCIFA2_RXD1_MARK, SCIFA2_TXD1_MARK,
+};
+static const unsigned int scifa2_clk_pins[] = {
+        /* SCK */
+        98,
+};
+static const unsigned int scifa2_clk_mux[] = {
+        SCIFA2_SCK1_MARK,
+};
+static const unsigned int scifa2_ctrl_pins[] = {
+        /* RTS, CTS */
+        95, 94,
+};
+static const unsigned int scifa2_ctrl_mux[] = {
+        SCIFA2_RTS1_MARK, SCIFA2_CTS1_MARK,
+};
+/* - SCIFA3 ----------------------------------------------------------------- */
+static const unsigned int scifa3_data_pins[] = {
+        /* RXD, TXD */
+        144, 143,
+};
+static const unsigned int scifa3_data_mux[] = {
+        SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
+};
+static const unsigned int scifa3_clk_pins[] = {
+        /* SCK */
+        142,
+};
+static const unsigned int scifa3_clk_mux[] = {
+        SCIFA3_SCK_MARK,
+};
+static const unsigned int scifa3_ctrl_0_pins[] = {
+        /* RTS, CTS */
+        44, 43,
+};
+static const unsigned int scifa3_ctrl_0_mux[] = {
+        SCIFA3_RTS_44_MARK, SCIFA3_CTS_43_MARK,
+};
+static const unsigned int scifa3_ctrl_1_pins[] = {
+        /* RTS, CTS */
+        141, 140,
+};
+static const unsigned int scifa3_ctrl_1_mux[] = {
+        SCIFA3_RTS_141_MARK, SCIFA3_CTS_140_MARK,
+};
+/* - SCIFA4 ----------------------------------------------------------------- */
+static const unsigned int scifa4_data_pins[] = {
+        /* RXD, TXD */
+        5, 6,
+};
+static const unsigned int scifa4_data_mux[] = {
+        SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
+};
+/* - SCIFA5 ----------------------------------------------------------------- */
+static const unsigned int scifa5_data_pins[] = {
+        /* RXD, TXD */
+        8, 12,
+};
+static const unsigned int scifa5_data_mux[] = {
+        SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
+};
+/* - SCIFB ------------------------------------------------------------------ */
+static const unsigned int scifb_data_pins[] = {
+        /* RXD, TXD */
+        166, 165,
+};
+static const unsigned int scifb_data_mux[] = {
+        SCIFB_RXD_MARK, SCIFB_TXD_MARK,
+};
+static const unsigned int scifb_clk_pins[] = {
+        /* SCK */
+        162,
+};
+static const unsigned int scifb_clk_mux[] = {
+        SCIFB_SCK_MARK,
+};
+static const unsigned int scifb_ctrl_pins[] = {
+        /* RTS, CTS */
+        163, 164,
+};
+static const unsigned int scifb_ctrl_mux[] = {
+        SCIFB_RTS_MARK, SCIFB_CTS_MARK,
+};
 /* - SDHI0 ------------------------------------------------------------------ */
 static const unsigned int sdhi0_data1_pins[] = {
         /* D0 */
@@ -1073,8 +1688,169 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
         SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - USB0 ------------------------------------------------------------------- */
+static const unsigned int usb0_vbus_pins[] = {
+        /* VBUS */
+        167,
+};
+static const unsigned int usb0_vbus_mux[] = {
+        VBUS0_0_MARK,
+};
+static const unsigned int usb0_otg_id_pins[] = {
+        /* IDIN */
+        113,
+};
+static const unsigned int usb0_otg_id_mux[] = {
+        IDIN_0_MARK,
+};
+static const unsigned int usb0_otg_ctrl_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        116, 114, 117, 115,
+};
+static const unsigned int usb0_otg_ctrl_mux[] = {
+        PWEN_0_MARK, EXTLP_0_MARK, OVCN_0_MARK, OVCN2_0_MARK,
+};
+/* - USB1 ------------------------------------------------------------------- */
+static const unsigned int usb1_vbus_pins[] = {
+        /* VBUS */
+        168,
+};
+static const unsigned int usb1_vbus_mux[] = {
+        VBUS0_1_MARK,
+};
+static const unsigned int usb1_otg_id_0_pins[] = {
+        /* IDIN */
+        113,
+};
+static const unsigned int usb1_otg_id_0_mux[] = {
+        IDIN_1_113_MARK,
+};
+static const unsigned int usb1_otg_id_1_pins[] = {
+        /* IDIN */
+        18,
+};
+static const unsigned int usb1_otg_id_1_mux[] = {
+        IDIN_1_18_MARK,
+};
+static const unsigned int usb1_otg_ctrl_0_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        115, 116, 114, 117, 113,
+};
+static const unsigned int usb1_otg_ctrl_0_mux[] = {
+        PWEN_1_115_MARK, EXTLP_1_MARK, OVCN_1_114_MARK, OVCN2_1_MARK,
+};
+static const unsigned int usb1_otg_ctrl_1_pins[] = {
+        /* PWEN, EXTLP, OVCN, OVCN2 */
+        138, 116, 162, 117, 18,
+};
+static const unsigned int usb1_otg_ctrl_1_mux[] = {
+        PWEN_1_138_MARK, EXTLP_1_MARK, OVCN_1_162_MARK, OVCN2_1_MARK,
+};
 
 static const struct sh_pfc_pin_group pinmux_groups[] = {
+        SH_PFC_PIN_GROUP(bsc_data8),
+        SH_PFC_PIN_GROUP(bsc_data16),
+        SH_PFC_PIN_GROUP(bsc_cs0),
+        SH_PFC_PIN_GROUP(bsc_cs2),
+        SH_PFC_PIN_GROUP(bsc_cs4),
+        SH_PFC_PIN_GROUP(bsc_cs5a),
+        SH_PFC_PIN_GROUP(bsc_cs5b),
+        SH_PFC_PIN_GROUP(bsc_cs6a),
+        SH_PFC_PIN_GROUP(bsc_rd_we8),
+        SH_PFC_PIN_GROUP(bsc_rd_we16),
+        SH_PFC_PIN_GROUP(bsc_bs),
+        SH_PFC_PIN_GROUP(bsc_rdwr),
+        SH_PFC_PIN_GROUP(ceu_data_0_7),
+        SH_PFC_PIN_GROUP(ceu_data_8_15),
+        SH_PFC_PIN_GROUP(ceu_clk_0),
+        SH_PFC_PIN_GROUP(ceu_clk_1),
+        SH_PFC_PIN_GROUP(ceu_clk_2),
+        SH_PFC_PIN_GROUP(ceu_sync),
+        SH_PFC_PIN_GROUP(ceu_field),
+        SH_PFC_PIN_GROUP(flctl_data),
+        SH_PFC_PIN_GROUP(flctl_ce0),
+        SH_PFC_PIN_GROUP(flctl_ce1),
+        SH_PFC_PIN_GROUP(flctl_ctrl),
+        SH_PFC_PIN_GROUP(fsia_mclk_in),
+        SH_PFC_PIN_GROUP(fsia_mclk_out),
+        SH_PFC_PIN_GROUP(fsia_sclk_in),
+        SH_PFC_PIN_GROUP(fsia_sclk_out),
+        SH_PFC_PIN_GROUP(fsia_data_in),
+        SH_PFC_PIN_GROUP(fsia_data_out),
+        SH_PFC_PIN_GROUP(fsia_spdif_0),
+        SH_PFC_PIN_GROUP(fsia_spdif_1),
+        SH_PFC_PIN_GROUP(fsib_mclk_in),
+        SH_PFC_PIN_GROUP(hdmi),
+        SH_PFC_PIN_GROUP(intc_irq0_0),
+        SH_PFC_PIN_GROUP(intc_irq0_1),
+        SH_PFC_PIN_GROUP(intc_irq1),
+        SH_PFC_PIN_GROUP(intc_irq2_0),
+        SH_PFC_PIN_GROUP(intc_irq2_1),
+        SH_PFC_PIN_GROUP(intc_irq3_0),
+        SH_PFC_PIN_GROUP(intc_irq3_1),
+        SH_PFC_PIN_GROUP(intc_irq4_0),
+        SH_PFC_PIN_GROUP(intc_irq4_1),
+        SH_PFC_PIN_GROUP(intc_irq5),
+        SH_PFC_PIN_GROUP(intc_irq6_0),
+        SH_PFC_PIN_GROUP(intc_irq6_1),
+        SH_PFC_PIN_GROUP(intc_irq7_0),
+        SH_PFC_PIN_GROUP(intc_irq7_1),
+        SH_PFC_PIN_GROUP(intc_irq8_0),
+        SH_PFC_PIN_GROUP(intc_irq8_1),
+        SH_PFC_PIN_GROUP(intc_irq9_0),
+        SH_PFC_PIN_GROUP(intc_irq9_1),
+        SH_PFC_PIN_GROUP(intc_irq10),
+        SH_PFC_PIN_GROUP(intc_irq11),
+        SH_PFC_PIN_GROUP(intc_irq12_0),
+        SH_PFC_PIN_GROUP(intc_irq12_1),
+        SH_PFC_PIN_GROUP(intc_irq13_0),
+        SH_PFC_PIN_GROUP(intc_irq13_1),
+        SH_PFC_PIN_GROUP(intc_irq14_0),
+        SH_PFC_PIN_GROUP(intc_irq14_1),
+        SH_PFC_PIN_GROUP(intc_irq15_0),
+        SH_PFC_PIN_GROUP(intc_irq15_1),
+        SH_PFC_PIN_GROUP(intc_irq16_0),
+        SH_PFC_PIN_GROUP(intc_irq16_1),
+        SH_PFC_PIN_GROUP(intc_irq17),
+        SH_PFC_PIN_GROUP(intc_irq18),
+        SH_PFC_PIN_GROUP(intc_irq19),
+        SH_PFC_PIN_GROUP(intc_irq20),
+        SH_PFC_PIN_GROUP(intc_irq21),
+        SH_PFC_PIN_GROUP(intc_irq22),
+        SH_PFC_PIN_GROUP(intc_irq23),
+        SH_PFC_PIN_GROUP(intc_irq24),
+        SH_PFC_PIN_GROUP(intc_irq25),
+        SH_PFC_PIN_GROUP(intc_irq26_0),
+        SH_PFC_PIN_GROUP(intc_irq26_1),
+        SH_PFC_PIN_GROUP(intc_irq27_0),
+        SH_PFC_PIN_GROUP(intc_irq27_1),
+        SH_PFC_PIN_GROUP(intc_irq28_0),
+        SH_PFC_PIN_GROUP(intc_irq28_1),
+        SH_PFC_PIN_GROUP(intc_irq29_0),
+        SH_PFC_PIN_GROUP(intc_irq29_1),
+        SH_PFC_PIN_GROUP(intc_irq30_0),
+        SH_PFC_PIN_GROUP(intc_irq30_1),
+        SH_PFC_PIN_GROUP(intc_irq31_0),
+        SH_PFC_PIN_GROUP(intc_irq31_1),
+        SH_PFC_PIN_GROUP(keysc_in04_0),
+        SH_PFC_PIN_GROUP(keysc_in04_1),
+        SH_PFC_PIN_GROUP(keysc_in5),
+        SH_PFC_PIN_GROUP(keysc_in6),
+        SH_PFC_PIN_GROUP(keysc_in7),
+        SH_PFC_PIN_GROUP(keysc_out4),
+        SH_PFC_PIN_GROUP(keysc_out5),
+        SH_PFC_PIN_GROUP(keysc_out6),
+        SH_PFC_PIN_GROUP(keysc_out8),
+        SH_PFC_PIN_GROUP(lcd_data8),
+        SH_PFC_PIN_GROUP(lcd_data9),
+        SH_PFC_PIN_GROUP(lcd_data12),
+        SH_PFC_PIN_GROUP(lcd_data16),
+        SH_PFC_PIN_GROUP(lcd_data18),
+        SH_PFC_PIN_GROUP(lcd_data24),
+        SH_PFC_PIN_GROUP(lcd_display),
+        SH_PFC_PIN_GROUP(lcd_lclk),
+        SH_PFC_PIN_GROUP(lcd_sync),
+        SH_PFC_PIN_GROUP(lcd_sys),
         SH_PFC_PIN_GROUP(mmc0_data1_0),
         SH_PFC_PIN_GROUP(mmc0_data4_0),
         SH_PFC_PIN_GROUP(mmc0_data8_0),
@@ -1083,6 +1859,24 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(mmc0_data4_1),
         SH_PFC_PIN_GROUP(mmc0_data8_1),
         SH_PFC_PIN_GROUP(mmc0_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa0_data),
+        SH_PFC_PIN_GROUP(scifa0_clk),
+        SH_PFC_PIN_GROUP(scifa0_ctrl),
+        SH_PFC_PIN_GROUP(scifa1_data),
+        SH_PFC_PIN_GROUP(scifa1_clk),
+        SH_PFC_PIN_GROUP(scifa1_ctrl),
+        SH_PFC_PIN_GROUP(scifa2_data),
+        SH_PFC_PIN_GROUP(scifa2_clk),
+        SH_PFC_PIN_GROUP(scifa2_ctrl),
+        SH_PFC_PIN_GROUP(scifa3_data),
+        SH_PFC_PIN_GROUP(scifa3_clk),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_0),
+        SH_PFC_PIN_GROUP(scifa3_ctrl_1),
+        SH_PFC_PIN_GROUP(scifa4_data),
+        SH_PFC_PIN_GROUP(scifa5_data),
+        SH_PFC_PIN_GROUP(scifb_data),
+        SH_PFC_PIN_GROUP(scifb_clk),
+        SH_PFC_PIN_GROUP(scifb_ctrl),
         SH_PFC_PIN_GROUP(sdhi0_data1),
         SH_PFC_PIN_GROUP(sdhi0_data4),
         SH_PFC_PIN_GROUP(sdhi0_ctrl),
@@ -1094,6 +1888,144 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_data1),
         SH_PFC_PIN_GROUP(sdhi2_data4),
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(usb0_vbus),
+        SH_PFC_PIN_GROUP(usb0_otg_id),
+        SH_PFC_PIN_GROUP(usb0_otg_ctrl),
+        SH_PFC_PIN_GROUP(usb1_vbus),
+        SH_PFC_PIN_GROUP(usb1_otg_id_0),
+        SH_PFC_PIN_GROUP(usb1_otg_id_1),
+        SH_PFC_PIN_GROUP(usb1_otg_ctrl_0),
+        SH_PFC_PIN_GROUP(usb1_otg_ctrl_1),
+};
+
+static const char * const bsc_groups[] = {
+        "bsc_data8",
+        "bsc_data16",
+        "bsc_cs0",
+        "bsc_cs2",
+        "bsc_cs4",
+        "bsc_cs5a",
+        "bsc_cs5b",
+        "bsc_cs6a",
+        "bsc_rd_we8",
+        "bsc_rd_we16",
+        "bsc_bs",
+        "bsc_rdwr",
+};
+
+static const char * const ceu_groups[] = {
+        "ceu_data_0_7",
+        "ceu_data_8_15",
+        "ceu_clk_0",
+        "ceu_clk_1",
+        "ceu_clk_2",
+        "ceu_sync",
+        "ceu_field",
+};
+
+static const char * const flctl_groups[] = {
+        "flctl_data",
+        "flctl_ce0",
+        "flctl_ce1",
+        "flctl_ctrl",
+};
+
+static const char * const fsia_groups[] = {
+        "fsia_mclk_in",
+        "fsia_mclk_out",
+        "fsia_sclk_in",
+        "fsia_sclk_out",
+        "fsia_data_in",
+        "fsia_data_out",
+        "fsia_spdif_0",
+        "fsia_spdif_1",
+};
+
+static const char * const fsib_groups[] = {
+        "fsib_mclk_in",
+};
+
+static const char * const hdmi_groups[] = {
+        "hdmi",
+};
+
+static const char * const intc_groups[] = {
+        "intc_irq0_0",
+        "intc_irq0_1",
+        "intc_irq1",
+        "intc_irq2_0",
+        "intc_irq2_1",
+        "intc_irq3_0",
+        "intc_irq3_1",
+        "intc_irq4_0",
+        "intc_irq4_1",
+        "intc_irq5",
+        "intc_irq6_0",
+        "intc_irq6_1",
+        "intc_irq7_0",
+        "intc_irq7_1",
+        "intc_irq8_0",
+        "intc_irq8_1",
+        "intc_irq9_0",
+        "intc_irq9_1",
+        "intc_irq10",
+        "intc_irq11",
+        "intc_irq12_0",
+        "intc_irq12_1",
+        "intc_irq13_0",
+        "intc_irq13_1",
+        "intc_irq14_0",
+        "intc_irq14_1",
+        "intc_irq15_0",
+        "intc_irq15_1",
+        "intc_irq16_0",
+        "intc_irq16_1",
+        "intc_irq17",
+        "intc_irq18",
+        "intc_irq19",
+        "intc_irq20",
+        "intc_irq21",
+        "intc_irq22",
+        "intc_irq23",
+        "intc_irq24",
+        "intc_irq25",
+        "intc_irq26_0",
+        "intc_irq26_1",
+        "intc_irq27_0",
+        "intc_irq27_1",
+        "intc_irq28_0",
+        "intc_irq28_1",
+        "intc_irq29_0",
+        "intc_irq29_1",
+        "intc_irq30_0",
+        "intc_irq30_1",
+        "intc_irq31_0",
+        "intc_irq31_1",
+};
+
+static const char * const keysc_groups[] = {
+        "keysc_in04_0",
+        "keysc_in04_1",
+        "keysc_in5",
+        "keysc_in6",
+        "keysc_in7",
+        "keysc_out4",
+        "keysc_out5",
+        "keysc_out6",
+        "keysc_out8",
+};
+
+static const char * const lcd_groups[] = {
+        "lcd_data8",
+        "lcd_data9",
+        "lcd_data12",
+        "lcd_data16",
+        "lcd_data18",
+        "lcd_data24",
+        "lcd_display",
+        "lcd_lclk",
+        "lcd_sync",
+        "lcd_sys",
 };
 
 static const char * const mmc0_groups[] = {
@@ -1107,6 +2039,45 @@ static const char * const mmc0_groups[] = {
         "mmc0_ctrl_1",
 };
 
+static const char * const scifa0_groups[] = {
+        "scifa0_data",
+        "scifa0_clk",
+        "scifa0_ctrl",
+};
+
+static const char * const scifa1_groups[] = {
+        "scifa1_data",
+        "scifa1_clk",
+        "scifa1_ctrl",
+};
+
+static const char * const scifa2_groups[] = {
+        "scifa2_data",
+        "scifa2_clk",
+        "scifa2_ctrl",
+};
+
+static const char * const scifa3_groups[] = {
+        "scifa3_data",
+        "scifa3_clk",
+        "scifa3_ctrl_0",
+        "scifa3_ctrl_1",
+};
+
+static const char * const scifa4_groups[] = {
+        "scifa4_data",
+};
+
+static const char * const scifa5_groups[] = {
+        "scifa5_data",
+};
+
+static const char * const scifb_groups[] = {
+        "scifb_data",
+        "scifb_clk",
+        "scifb_ctrl",
+};
+
 static const char * const sdhi0_groups[] = {
         "sdhi0_data1",
         "sdhi0_data4",
@@ -1127,256 +2098,55 @@ static const char * const sdhi2_groups[] = {
         "sdhi2_ctrl",
 };
 
+static const char * const usb0_groups[] = {
+        "usb0_vbus",
+        "usb0_otg_id",
+        "usb0_otg_ctrl",
+};
+
+static const char * const usb1_groups[] = {
+        "usb1_vbus",
+        "usb1_otg_id_0",
+        "usb1_otg_id_1",
+        "usb1_otg_ctrl_0",
+        "usb1_otg_ctrl_1",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
+        SH_PFC_FUNCTION(bsc),
+        SH_PFC_FUNCTION(ceu),
+        SH_PFC_FUNCTION(flctl),
+        SH_PFC_FUNCTION(fsia),
+        SH_PFC_FUNCTION(fsib),
+        SH_PFC_FUNCTION(hdmi),
+        SH_PFC_FUNCTION(intc),
+        SH_PFC_FUNCTION(keysc),
+        SH_PFC_FUNCTION(lcd),
         SH_PFC_FUNCTION(mmc0),
+        SH_PFC_FUNCTION(scifa0),
+        SH_PFC_FUNCTION(scifa1),
+        SH_PFC_FUNCTION(scifa2),
+        SH_PFC_FUNCTION(scifa3),
+        SH_PFC_FUNCTION(scifa4),
+        SH_PFC_FUNCTION(scifa5),
+        SH_PFC_FUNCTION(scifb),
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(usb0),
+        SH_PFC_FUNCTION(usb1),
 };
 
-#define PINMUX_FN_BASE  ARRAY_SIZE(pinmux_pins)
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* IRQ */
-        GPIO_FN(IRQ0_6),        GPIO_FN(IRQ0_162),      GPIO_FN(IRQ1),
-        GPIO_FN(IRQ2_4),        GPIO_FN(IRQ2_5),        GPIO_FN(IRQ3_8),
-        GPIO_FN(IRQ3_16),       GPIO_FN(IRQ4_17),       GPIO_FN(IRQ4_163),
-        GPIO_FN(IRQ5),          GPIO_FN(IRQ6_39),       GPIO_FN(IRQ6_164),
-        GPIO_FN(IRQ7_40),       GPIO_FN(IRQ7_167),      GPIO_FN(IRQ8_41),
-        GPIO_FN(IRQ8_168),      GPIO_FN(IRQ9_42),       GPIO_FN(IRQ9_169),
-        GPIO_FN(IRQ10),         GPIO_FN(IRQ11),         GPIO_FN(IRQ12_80),
-        GPIO_FN(IRQ12_137),     GPIO_FN(IRQ13_81),      GPIO_FN(IRQ13_145),
-        GPIO_FN(IRQ14_82),      GPIO_FN(IRQ14_146),     GPIO_FN(IRQ15_83),
-        GPIO_FN(IRQ15_147),     GPIO_FN(IRQ16_84),      GPIO_FN(IRQ16_170),
-        GPIO_FN(IRQ17),         GPIO_FN(IRQ18),         GPIO_FN(IRQ19),
-        GPIO_FN(IRQ20),         GPIO_FN(IRQ21),         GPIO_FN(IRQ22),
-        GPIO_FN(IRQ23),         GPIO_FN(IRQ24),         GPIO_FN(IRQ25),
-        GPIO_FN(IRQ26_121),     GPIO_FN(IRQ26_172),     GPIO_FN(IRQ27_122),
-        GPIO_FN(IRQ27_180),     GPIO_FN(IRQ28_123),     GPIO_FN(IRQ28_181),
-        GPIO_FN(IRQ29_129),     GPIO_FN(IRQ29_182),     GPIO_FN(IRQ30_130),
-        GPIO_FN(IRQ30_183),     GPIO_FN(IRQ31_138),     GPIO_FN(IRQ31_184),
-
-        /* MSIOF0 */
-        GPIO_FN(MSIOF0_TSYNC),  GPIO_FN(MSIOF0_TSCK),   GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(MSIOF0_RSCK),   GPIO_FN(MSIOF0_RSYNC),  GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(MSIOF0_MCK1),   GPIO_FN(MSIOF0_SS1),    GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(MSIOF0_TXD),
-
-        /* MSIOF1 */
-        GPIO_FN(MSIOF1_TSCK_39),        GPIO_FN(MSIOF1_TSCK_88),
-        GPIO_FN(MSIOF1_TSYNC_40),       GPIO_FN(MSIOF1_TSYNC_89),
-        GPIO_FN(MSIOF1_TXD_41),         GPIO_FN(MSIOF1_TXD_90),
-        GPIO_FN(MSIOF1_RXD_42),         GPIO_FN(MSIOF1_RXD_91),
-        GPIO_FN(MSIOF1_SS1_43),         GPIO_FN(MSIOF1_SS1_92),
-        GPIO_FN(MSIOF1_SS2_44),         GPIO_FN(MSIOF1_SS2_93),
-        GPIO_FN(MSIOF1_RSCK),           GPIO_FN(MSIOF1_RSYNC),
-        GPIO_FN(MSIOF1_MCK0),           GPIO_FN(MSIOF1_MCK1),
-
-        /* MSIOF2 */
-        GPIO_FN(MSIOF2_RSCK),   GPIO_FN(MSIOF2_RSYNC),  GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),   GPIO_FN(MSIOF2_SS1),    GPIO_FN(MSIOF2_SS2),
-        GPIO_FN(MSIOF2_TSYNC),  GPIO_FN(MSIOF2_TSCK),   GPIO_FN(MSIOF2_RXD),
-        GPIO_FN(MSIOF2_TXD),
-
-        /* BBIF1 */
-        GPIO_FN(BBIF1_RXD),     GPIO_FN(BBIF1_TSYNC),   GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(BBIF1_TXD),     GPIO_FN(BBIF1_RSCK),    GPIO_FN(BBIF1_RSYNC),
-        GPIO_FN(BBIF1_FLOW),    GPIO_FN(BB_RX_FLOW_N),
-
-        /* BBIF2 */
-        GPIO_FN(BBIF2_TSCK1),   GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TXD1),    GPIO_FN(BBIF2_RXD),
-
-        /* FSI */
-        GPIO_FN(FSIACK),        GPIO_FN(FSIBCK),        GPIO_FN(FSIAILR),
-        GPIO_FN(FSIAIBT),       GPIO_FN(FSIAISLD),      GPIO_FN(FSIAOMC),
-        GPIO_FN(FSIAOLR),       GPIO_FN(FSIAOBT),       GPIO_FN(FSIAOSLD),
-        GPIO_FN(FSIASPDIF_11),  GPIO_FN(FSIASPDIF_15),
-
-        /* FMSI */
-        GPIO_FN(FMSOCK),        GPIO_FN(FMSOOLR),       GPIO_FN(FMSIOLR),
-        GPIO_FN(FMSOOBT),       GPIO_FN(FMSIOBT),       GPIO_FN(FMSOSLD),
-        GPIO_FN(FMSOILR),       GPIO_FN(FMSIILR),       GPIO_FN(FMSOIBT),
-        GPIO_FN(FMSIIBT),       GPIO_FN(FMSISLD),       GPIO_FN(FMSICK),
-
-        /* SCIFA0 */
-        GPIO_FN(SCIFA0_TXD),    GPIO_FN(SCIFA0_RXD),    GPIO_FN(SCIFA0_SCK),
-        GPIO_FN(SCIFA0_RTS),    GPIO_FN(SCIFA0_CTS),
-
-        /* SCIFA1 */
-        GPIO_FN(SCIFA1_TXD),    GPIO_FN(SCIFA1_RXD),    GPIO_FN(SCIFA1_SCK),
-        GPIO_FN(SCIFA1_RTS),    GPIO_FN(SCIFA1_CTS),
-
-        /* SCIFA2 */
-        GPIO_FN(SCIFA2_CTS1),   GPIO_FN(SCIFA2_RTS1),   GPIO_FN(SCIFA2_TXD1),
-        GPIO_FN(SCIFA2_RXD1),   GPIO_FN(SCIFA2_SCK1),
-
-        /* SCIFA3 */
-        GPIO_FN(SCIFA3_CTS_43),         GPIO_FN(SCIFA3_CTS_140),
-        GPIO_FN(SCIFA3_RTS_44),         GPIO_FN(SCIFA3_RTS_141),
-        GPIO_FN(SCIFA3_SCK),            GPIO_FN(SCIFA3_TXD),
-        GPIO_FN(SCIFA3_RXD),
-
-        /* SCIFA4 */
-        GPIO_FN(SCIFA4_RXD),    GPIO_FN(SCIFA4_TXD),
-
-        /* SCIFA5 */
-        GPIO_FN(SCIFA5_RXD),    GPIO_FN(SCIFA5_TXD),
-
-        /* SCIFB */
-        GPIO_FN(SCIFB_SCK),     GPIO_FN(SCIFB_RTS),     GPIO_FN(SCIFB_CTS),
-        GPIO_FN(SCIFB_TXD),     GPIO_FN(SCIFB_RXD),
-
-        /* CEU */
-        GPIO_FN(VIO_HD),        GPIO_FN(VIO_CKO1),      GPIO_FN(VIO_CKO2),
-        GPIO_FN(VIO_VD),        GPIO_FN(VIO_CLK),       GPIO_FN(VIO_FIELD),
-        GPIO_FN(VIO_CKO),       GPIO_FN(VIO_D0),        GPIO_FN(VIO_D1),
-        GPIO_FN(VIO_D2),        GPIO_FN(VIO_D3),        GPIO_FN(VIO_D4),
-        GPIO_FN(VIO_D5),        GPIO_FN(VIO_D6),        GPIO_FN(VIO_D7),
-        GPIO_FN(VIO_D8),        GPIO_FN(VIO_D9),        GPIO_FN(VIO_D10),
-        GPIO_FN(VIO_D11),       GPIO_FN(VIO_D12),       GPIO_FN(VIO_D13),
-        GPIO_FN(VIO_D14),       GPIO_FN(VIO_D15),
-
-        /* USB0 */
-        GPIO_FN(IDIN_0),        GPIO_FN(EXTLP_0),       GPIO_FN(OVCN2_0),
-        GPIO_FN(PWEN_0),        GPIO_FN(OVCN_0),        GPIO_FN(VBUS0_0),
-
-        /* USB1 */
-        GPIO_FN(IDIN_1_18),     GPIO_FN(IDIN_1_113),
-        GPIO_FN(OVCN_1_114),    GPIO_FN(OVCN_1_162),
-        GPIO_FN(PWEN_1_115),    GPIO_FN(PWEN_1_138),
-        GPIO_FN(EXTLP_1),       GPIO_FN(OVCN2_1),
-        GPIO_FN(VBUS0_1),
-
-        /* GPIO */
-        GPIO_FN(GPI0),  GPIO_FN(GPI1),  GPIO_FN(GPO0),  GPIO_FN(GPO1),
-
-        /* BSC */
-        GPIO_FN(BS),    GPIO_FN(WE1),   GPIO_FN(CKO),
-        GPIO_FN(WAIT),  GPIO_FN(RDWR),
-
-        GPIO_FN(A0),    GPIO_FN(A1),    GPIO_FN(A2),
-        GPIO_FN(A3),    GPIO_FN(A6),    GPIO_FN(A7),
-        GPIO_FN(A8),    GPIO_FN(A9),    GPIO_FN(A10),
-        GPIO_FN(A11),   GPIO_FN(A12),   GPIO_FN(A13),
-        GPIO_FN(A14),   GPIO_FN(A15),   GPIO_FN(A16),
-        GPIO_FN(A17),   GPIO_FN(A18),   GPIO_FN(A19),
-        GPIO_FN(A20),   GPIO_FN(A21),   GPIO_FN(A22),
-        GPIO_FN(A23),   GPIO_FN(A24),   GPIO_FN(A25),
-        GPIO_FN(A26),
-
-        GPIO_FN(CS0),   GPIO_FN(CS2),   GPIO_FN(CS4),
-        GPIO_FN(CS5A),  GPIO_FN(CS5B),  GPIO_FN(CS6A),
-
-        /* BSC/FLCTL */
-        GPIO_FN(RD_FSC),        GPIO_FN(WE0_FWE),       GPIO_FN(A4_FOE),
-        GPIO_FN(A5_FCDE),       GPIO_FN(D0_NAF0),       GPIO_FN(D1_NAF1),
-        GPIO_FN(D2_NAF2),       GPIO_FN(D3_NAF3),       GPIO_FN(D4_NAF4),
-        GPIO_FN(D5_NAF5),       GPIO_FN(D6_NAF6),       GPIO_FN(D7_NAF7),
-        GPIO_FN(D8_NAF8),       GPIO_FN(D9_NAF9),       GPIO_FN(D10_NAF10),
-        GPIO_FN(D11_NAF11),     GPIO_FN(D12_NAF12),     GPIO_FN(D13_NAF13),
-        GPIO_FN(D14_NAF14),     GPIO_FN(D15_NAF15),
-
-        /* SPU2 */
-        GPIO_FN(VINT_I),
-
-        /* FLCTL */
-        GPIO_FN(FCE1),  GPIO_FN(FCE0),  GPIO_FN(FRB),
-
-        /* HSI */
-        GPIO_FN(GP_RX_FLAG),    GPIO_FN(GP_RX_DATA),    GPIO_FN(GP_TX_READY),
-        GPIO_FN(GP_RX_WAKE),    GPIO_FN(MP_TX_FLAG),    GPIO_FN(MP_TX_DATA),
-        GPIO_FN(MP_RX_READY),   GPIO_FN(MP_TX_WAKE),
-
-        /* MFI */
-        GPIO_FN(MFIv6),
-        GPIO_FN(MFIv4),
-
-        GPIO_FN(MEMC_BUSCLK_MEMC_A0),   GPIO_FN(MEMC_ADV_MEMC_DREQ0),
-        GPIO_FN(MEMC_WAIT_MEMC_DREQ1),  GPIO_FN(MEMC_CS1_MEMC_A1),
-        GPIO_FN(MEMC_CS0),      GPIO_FN(MEMC_NOE),
-        GPIO_FN(MEMC_NWE),      GPIO_FN(MEMC_INT),
-
-        GPIO_FN(MEMC_AD0),      GPIO_FN(MEMC_AD1),      GPIO_FN(MEMC_AD2),
-        GPIO_FN(MEMC_AD3),      GPIO_FN(MEMC_AD4),      GPIO_FN(MEMC_AD5),
-        GPIO_FN(MEMC_AD6),      GPIO_FN(MEMC_AD7),      GPIO_FN(MEMC_AD8),
-        GPIO_FN(MEMC_AD9),      GPIO_FN(MEMC_AD10),     GPIO_FN(MEMC_AD11),
-        GPIO_FN(MEMC_AD12),     GPIO_FN(MEMC_AD13),     GPIO_FN(MEMC_AD14),
-        GPIO_FN(MEMC_AD15),
-
-        /* SIM */
-        GPIO_FN(SIM_RST),       GPIO_FN(SIM_CLK),       GPIO_FN(SIM_D),
-
-        /* TPU */
-        GPIO_FN(TPU0TO0),       GPIO_FN(TPU0TO1),       GPIO_FN(TPU0TO2_93),
-        GPIO_FN(TPU0TO2_99),    GPIO_FN(TPU0TO3),
-
-        /* I2C2 */
-        GPIO_FN(I2C_SCL2),      GPIO_FN(I2C_SDA2),
-
-        /* I2C3(1) */
-        GPIO_FN(I2C_SCL3),      GPIO_FN(I2C_SDA3),
-
-        /* I2C3(2) */
-        GPIO_FN(I2C_SCL3S),     GPIO_FN(I2C_SDA3S),
-
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4),      GPIO_FN(I2C_SDA4),
-
-        /* I2C4(2) */
-        GPIO_FN(I2C_SCL4S),     GPIO_FN(I2C_SDA4S),
-
-        /* KEYSC */
-        GPIO_FN(KEYOUT0),       GPIO_FN(KEYIN0_121),    GPIO_FN(KEYIN0_136),
-        GPIO_FN(KEYOUT1),       GPIO_FN(KEYIN1_122),    GPIO_FN(KEYIN1_135),
-        GPIO_FN(KEYOUT2),       GPIO_FN(KEYIN2_123),    GPIO_FN(KEYIN2_134),
-        GPIO_FN(KEYOUT3),       GPIO_FN(KEYIN3_124),    GPIO_FN(KEYIN3_133),
-        GPIO_FN(KEYOUT4),       GPIO_FN(KEYIN4),        GPIO_FN(KEYOUT5),
-        GPIO_FN(KEYIN5),        GPIO_FN(KEYOUT6),       GPIO_FN(KEYIN6),
-        GPIO_FN(KEYOUT7),       GPIO_FN(KEYIN7),
-
-        /* LCDC */
-        GPIO_FN(LCDHSYN),       GPIO_FN(LCDCS), GPIO_FN(LCDVSYN),
-        GPIO_FN(LCDDCK),        GPIO_FN(LCDWR), GPIO_FN(LCDRD),
-        GPIO_FN(LCDDISP),       GPIO_FN(LCDRS), GPIO_FN(LCDLCLK),
-        GPIO_FN(LCDDON),
-
-        GPIO_FN(LCDD0),         GPIO_FN(LCDD1),         GPIO_FN(LCDD2),
-        GPIO_FN(LCDD3),         GPIO_FN(LCDD4),         GPIO_FN(LCDD5),
-        GPIO_FN(LCDD6),         GPIO_FN(LCDD7),         GPIO_FN(LCDD8),
-        GPIO_FN(LCDD9),         GPIO_FN(LCDD10),        GPIO_FN(LCDD11),
-        GPIO_FN(LCDD12),        GPIO_FN(LCDD13),        GPIO_FN(LCDD14),
-        GPIO_FN(LCDD15),        GPIO_FN(LCDD16),        GPIO_FN(LCDD17),
-        GPIO_FN(LCDD18),        GPIO_FN(LCDD19),        GPIO_FN(LCDD20),
-        GPIO_FN(LCDD21),        GPIO_FN(LCDD22),        GPIO_FN(LCDD23),
-
-        GPIO_FN(LCDC0_SELECT),
-        GPIO_FN(LCDC1_SELECT),
-
-        /* IRDA */
-        GPIO_FN(IRDA_OUT),      GPIO_FN(IRDA_IN),       GPIO_FN(IRDA_FIRSEL),
-        GPIO_FN(IROUT_139),     GPIO_FN(IROUT_140),
-
-        /* TSIF1 */
-        GPIO_FN(TS0_1SELECT),
-        GPIO_FN(TS0_2SELECT),
-        GPIO_FN(TS1_1SELECT),
-        GPIO_FN(TS1_2SELECT),
-
-        GPIO_FN(TS_SPSYNC1),    GPIO_FN(TS_SDAT1),
-        GPIO_FN(TS_SDEN1),      GPIO_FN(TS_SCK1),
-
-        /* TSIF2 */
-        GPIO_FN(TS_SPSYNC2),    GPIO_FN(TS_SDAT2),
-        GPIO_FN(TS_SDEN2),      GPIO_FN(TS_SCK2),
-
-        /* HDMI */
-        GPIO_FN(HDMI_HPD),      GPIO_FN(HDMI_CEC),
-
-        /* SDENC */
-        GPIO_FN(SDENC_CPG),
-        GPIO_FN(SDENC_DV_CLKI),
-};
+#undef PORTCR
+#define PORTCR(nr, reg)                                                 \
+        {                                                               \
+                PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) {             \
+                        _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT),     \
+                                PORT##nr##_FN0, PORT##nr##_FN1,         \
+                                PORT##nr##_FN2, PORT##nr##_FN3,         \
+                                PORT##nr##_FN4, PORT##nr##_FN5,         \
+                                PORT##nr##_FN6, PORT##nr##_FN7 }        \
+        }
 
 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
         PORTCR(0,       0xE6051000), /* PORT0CR */
@@ -1776,45 +2546,114 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
 #define EXT_IRQ16L(n) evt2irq(0x200 + ((n) << 5))
 #define EXT_IRQ16H(n) evt2irq(0x3200 + (((n) - 16) << 5))
 static const struct pinmux_irq pinmux_irqs[] = {
-        PINMUX_IRQ(EXT_IRQ16L(0), GPIO_PORT6, GPIO_PORT162),
-        PINMUX_IRQ(EXT_IRQ16L(1), GPIO_PORT12),
-        PINMUX_IRQ(EXT_IRQ16L(2), GPIO_PORT4, GPIO_PORT5),
-        PINMUX_IRQ(EXT_IRQ16L(3), GPIO_PORT8, GPIO_PORT16),
-        PINMUX_IRQ(EXT_IRQ16L(4), GPIO_PORT17, GPIO_PORT163),
-        PINMUX_IRQ(EXT_IRQ16L(5), GPIO_PORT18),
-        PINMUX_IRQ(EXT_IRQ16L(6), GPIO_PORT39, GPIO_PORT164),
-        PINMUX_IRQ(EXT_IRQ16L(7), GPIO_PORT40, GPIO_PORT167),
-        PINMUX_IRQ(EXT_IRQ16L(8), GPIO_PORT41, GPIO_PORT168),
-        PINMUX_IRQ(EXT_IRQ16L(9), GPIO_PORT42, GPIO_PORT169),
-        PINMUX_IRQ(EXT_IRQ16L(10), GPIO_PORT65),
-        PINMUX_IRQ(EXT_IRQ16L(11), GPIO_PORT67),
-        PINMUX_IRQ(EXT_IRQ16L(12), GPIO_PORT80, GPIO_PORT137),
-        PINMUX_IRQ(EXT_IRQ16L(13), GPIO_PORT81, GPIO_PORT145),
-        PINMUX_IRQ(EXT_IRQ16L(14), GPIO_PORT82, GPIO_PORT146),
-        PINMUX_IRQ(EXT_IRQ16L(15), GPIO_PORT83, GPIO_PORT147),
-        PINMUX_IRQ(EXT_IRQ16H(16), GPIO_PORT84, GPIO_PORT170),
-        PINMUX_IRQ(EXT_IRQ16H(17), GPIO_PORT85),
-        PINMUX_IRQ(EXT_IRQ16H(18), GPIO_PORT86),
-        PINMUX_IRQ(EXT_IRQ16H(19), GPIO_PORT87),
-        PINMUX_IRQ(EXT_IRQ16H(20), GPIO_PORT92),
-        PINMUX_IRQ(EXT_IRQ16H(21), GPIO_PORT93),
-        PINMUX_IRQ(EXT_IRQ16H(22), GPIO_PORT94),
-        PINMUX_IRQ(EXT_IRQ16H(23), GPIO_PORT95),
-        PINMUX_IRQ(EXT_IRQ16H(24), GPIO_PORT112),
-        PINMUX_IRQ(EXT_IRQ16H(25), GPIO_PORT119),
-        PINMUX_IRQ(EXT_IRQ16H(26), GPIO_PORT121, GPIO_PORT172),
-        PINMUX_IRQ(EXT_IRQ16H(27), GPIO_PORT122, GPIO_PORT180),
-        PINMUX_IRQ(EXT_IRQ16H(28), GPIO_PORT123, GPIO_PORT181),
-        PINMUX_IRQ(EXT_IRQ16H(29), GPIO_PORT129, GPIO_PORT182),
-        PINMUX_IRQ(EXT_IRQ16H(30), GPIO_PORT130, GPIO_PORT183),
-        PINMUX_IRQ(EXT_IRQ16H(31), GPIO_PORT138, GPIO_PORT184),
+        PINMUX_IRQ(EXT_IRQ16L(0), 6, 162),
+        PINMUX_IRQ(EXT_IRQ16L(1), 12),
+        PINMUX_IRQ(EXT_IRQ16L(2), 4, 5),
+        PINMUX_IRQ(EXT_IRQ16L(3), 8, 16),
+        PINMUX_IRQ(EXT_IRQ16L(4), 17, 163),
+        PINMUX_IRQ(EXT_IRQ16L(5), 18),
+        PINMUX_IRQ(EXT_IRQ16L(6), 39, 164),
+        PINMUX_IRQ(EXT_IRQ16L(7), 40, 167),
+        PINMUX_IRQ(EXT_IRQ16L(8), 41, 168),
+        PINMUX_IRQ(EXT_IRQ16L(9), 42, 169),
+        PINMUX_IRQ(EXT_IRQ16L(10), 65),
+        PINMUX_IRQ(EXT_IRQ16L(11), 67),
+        PINMUX_IRQ(EXT_IRQ16L(12), 80, 137),
+        PINMUX_IRQ(EXT_IRQ16L(13), 81, 145),
+        PINMUX_IRQ(EXT_IRQ16L(14), 82, 146),
+        PINMUX_IRQ(EXT_IRQ16L(15), 83, 147),
+        PINMUX_IRQ(EXT_IRQ16H(16), 84, 170),
+        PINMUX_IRQ(EXT_IRQ16H(17), 85),
+        PINMUX_IRQ(EXT_IRQ16H(18), 86),
+        PINMUX_IRQ(EXT_IRQ16H(19), 87),
+        PINMUX_IRQ(EXT_IRQ16H(20), 92),
+        PINMUX_IRQ(EXT_IRQ16H(21), 93),
+        PINMUX_IRQ(EXT_IRQ16H(22), 94),
+        PINMUX_IRQ(EXT_IRQ16H(23), 95),
+        PINMUX_IRQ(EXT_IRQ16H(24), 112),
+        PINMUX_IRQ(EXT_IRQ16H(25), 119),
+        PINMUX_IRQ(EXT_IRQ16H(26), 121, 172),
+        PINMUX_IRQ(EXT_IRQ16H(27), 122, 180),
+        PINMUX_IRQ(EXT_IRQ16H(28), 123, 181),
+        PINMUX_IRQ(EXT_IRQ16H(29), 129, 182),
+        PINMUX_IRQ(EXT_IRQ16H(30), 130, 183),
+        PINMUX_IRQ(EXT_IRQ16H(31), 138, 184),
+};
+
+#define PORTnCR_PULMD_OFF       (0 << 6)
+#define PORTnCR_PULMD_DOWN      (2 << 6)
+#define PORTnCR_PULMD_UP        (3 << 6)
+#define PORTnCR_PULMD_MASK      (3 << 6)
+
+struct sh7372_portcr_group {
+        unsigned int end_pin;
+        unsigned int offset;
+};
+
+static const struct sh7372_portcr_group sh7372_portcr_offsets[] = {
+        { 45,  0x1000 }, { 75,  0x2000 }, { 99,  0x0000 }, { 120, 0x3000 },
+        { 151, 0x0000 }, { 155, 0x3000 }, { 166, 0x0000 }, { 190, 0x2000 },
+};
+
+static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
+{
+        unsigned int i;
+
+        for (i = 0; i < ARRAY_SIZE(sh7372_portcr_offsets); ++i) {
+                const struct sh7372_portcr_group *group =
+                        &sh7372_portcr_offsets[i];
+
+                if (i <= group->end_pin)
+                        return pfc->window->virt + group->offset + pin;
+        }
+
+        return NULL;
+}
+
+static unsigned int sh7372_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
+{
+        void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
+
+        switch (value) {
+        case PORTnCR_PULMD_UP:
+                return PIN_CONFIG_BIAS_PULL_UP;
+        case PORTnCR_PULMD_DOWN:
+                return PIN_CONFIG_BIAS_PULL_DOWN;
+        case PORTnCR_PULMD_OFF:
+        default:
+                return PIN_CONFIG_BIAS_DISABLE;
+        }
+}
+
+static void sh7372_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
+                                   unsigned int bias)
+{
+        void __iomem *addr = sh7372_pinmux_portcr(pfc, pin);
+        u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
+
+        switch (bias) {
+        case PIN_CONFIG_BIAS_PULL_UP:
+                value |= PORTnCR_PULMD_UP;
+                break;
+        case PIN_CONFIG_BIAS_PULL_DOWN:
+                value |= PORTnCR_PULMD_DOWN;
+                break;
+        }
+
+        iowrite8(value, addr);
+}
+
+static const struct sh_pfc_soc_operations sh7372_pinmux_ops = {
+        .get_bias = sh7372_pinmux_get_bias,
+        .set_bias = sh7372_pinmux_set_bias,
 };
 
 const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .name = "sh7372_pfc",
+        .ops = &sh7372_pinmux_ops,
+
         .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
-        .input_pu = { PINMUX_INPUT_PULLUP_BEGIN, PINMUX_INPUT_PULLUP_END },
-        .input_pd = { PINMUX_INPUT_PULLDOWN_BEGIN, PINMUX_INPUT_PULLDOWN_END },
         .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
         .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
 
@@ -1825,9 +2664,6 @@ const struct sh_pfc_soc_info sh7372_pinmux_info = {
         .functions = pinmux_functions,
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios = pinmux_func_gpios,
-        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 587f7772abf2..7956df58d751 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -20,9 +20,12 @@
  */
 #include <linux/io.h>
 #include <linux/kernel.h>
+#include <linux/module.h>
 #include <linux/pinctrl/pinconf-generic.h>
+#include <linux/regulator/driver.h>
+#include <linux/regulator/machine.h>
+#include <linux/slab.h>
 
-#include <mach/sh73a0.h>
 #include <mach/irqs.h>
 
 #include "core.h"
@@ -2538,6 +2541,157 @@ static const unsigned int sdhi2_ctrl_pins[] = {
 static const unsigned int sdhi2_ctrl_mux[] = {
         SDHICMD2_MARK, SDHICLK2_MARK,
 };
+/* - TPU0 ------------------------------------------------------------------- */
+static const unsigned int tpu0_to0_pins[] = {
+        /* TO */
+        55,
+};
+static const unsigned int tpu0_to0_mux[] = {
+        TPU0TO0_MARK,
+};
+static const unsigned int tpu0_to1_pins[] = {
+        /* TO */
+        59,
+};
+static const unsigned int tpu0_to1_mux[] = {
+        TPU0TO1_MARK,
+};
+static const unsigned int tpu0_to2_pins[] = {
+        /* TO */
+        140,
+};
+static const unsigned int tpu0_to2_mux[] = {
+        TPU0TO2_MARK,
+};
+static const unsigned int tpu0_to3_pins[] = {
+        /* TO */
+        141,
+};
+static const unsigned int tpu0_to3_mux[] = {
+        TPU0TO3_MARK,
+};
+/* - TPU1 ------------------------------------------------------------------- */
+static const unsigned int tpu1_to0_pins[] = {
+        /* TO */
+        246,
+};
+static const unsigned int tpu1_to0_mux[] = {
+        TPU1TO0_MARK,
+};
+static const unsigned int tpu1_to1_0_pins[] = {
+        /* TO */
+        28,
+};
+static const unsigned int tpu1_to1_0_mux[] = {
+        PORT28_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to1_1_pins[] = {
+        /* TO */
+        29,
+};
+static const unsigned int tpu1_to1_1_mux[] = {
+        PORT29_TPU1TO1_MARK,
+};
+static const unsigned int tpu1_to2_pins[] = {
+        /* TO */
+        153,
+};
+static const unsigned int tpu1_to2_mux[] = {
+        TPU1TO2_MARK,
+};
+static const unsigned int tpu1_to3_pins[] = {
+        /* TO */
+        145,
+};
+static const unsigned int tpu1_to3_mux[] = {
+        TPU1TO3_MARK,
+};
+/* - TPU2 ------------------------------------------------------------------- */
+static const unsigned int tpu2_to0_pins[] = {
+        /* TO */
+        248,
+};
+static const unsigned int tpu2_to0_mux[] = {
+        TPU2TO0_MARK,
+};
+static const unsigned int tpu2_to1_pins[] = {
+        /* TO */
+        197,
+};
+static const unsigned int tpu2_to1_mux[] = {
+        TPU2TO1_MARK,
+};
+static const unsigned int tpu2_to2_pins[] = {
+        /* TO */
+        50,
+};
+static const unsigned int tpu2_to2_mux[] = {
+        TPU2TO2_MARK,
+};
+static const unsigned int tpu2_to3_pins[] = {
+        /* TO */
+        51,
+};
+static const unsigned int tpu2_to3_mux[] = {
+        TPU2TO3_MARK,
+};
+/* - TPU3 ------------------------------------------------------------------- */
+static const unsigned int tpu3_to0_pins[] = {
+        /* TO */
+        163,
+};
+static const unsigned int tpu3_to0_mux[] = {
+        TPU3TO0_MARK,
+};
+static const unsigned int tpu3_to1_pins[] = {
+        /* TO */
+        247,
+};
+static const unsigned int tpu3_to1_mux[] = {
+        TPU3TO1_MARK,
+};
+static const unsigned int tpu3_to2_pins[] = {
+        /* TO */
+        54,
+};
+static const unsigned int tpu3_to2_mux[] = {
+        TPU3TO2_MARK,
+};
+static const unsigned int tpu3_to3_pins[] = {
+        /* TO */
+        53,
+};
+static const unsigned int tpu3_to3_mux[] = {
+        TPU3TO3_MARK,
+};
+/* - TPU4 ------------------------------------------------------------------- */
+static const unsigned int tpu4_to0_pins[] = {
+        /* TO */
+        241,
+};
+static const unsigned int tpu4_to0_mux[] = {
+        TPU4TO0_MARK,
+};
+static const unsigned int tpu4_to1_pins[] = {
+        /* TO */
+        199,
+};
+static const unsigned int tpu4_to1_mux[] = {
+        TPU4TO1_MARK,
+};
+static const unsigned int tpu4_to2_pins[] = {
+        /* TO */
+        58,
+};
+static const unsigned int tpu4_to2_mux[] = {
+        TPU4TO2_MARK,
+};
+static const unsigned int tpu4_to3_pins[] = {
+        /* TO */
+};
+static const unsigned int tpu4_to3_mux[] = {
+        TPU4TO3_MARK,
+};
 /* - USB -------------------------------------------------------------------- */
 static const unsigned int usb_vbus_pins[] = {
         /* VBUS */
@@ -2689,6 +2843,27 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
         SH_PFC_PIN_GROUP(sdhi2_data1),
         SH_PFC_PIN_GROUP(sdhi2_data4),
         SH_PFC_PIN_GROUP(sdhi2_ctrl),
+        SH_PFC_PIN_GROUP(tpu0_to0),
+        SH_PFC_PIN_GROUP(tpu0_to1),
+        SH_PFC_PIN_GROUP(tpu0_to2),
+        SH_PFC_PIN_GROUP(tpu0_to3),
+        SH_PFC_PIN_GROUP(tpu1_to0),
+        SH_PFC_PIN_GROUP(tpu1_to1_0),
+        SH_PFC_PIN_GROUP(tpu1_to1_1),
+        SH_PFC_PIN_GROUP(tpu1_to2),
+        SH_PFC_PIN_GROUP(tpu1_to3),
+        SH_PFC_PIN_GROUP(tpu2_to0),
+        SH_PFC_PIN_GROUP(tpu2_to1),
+        SH_PFC_PIN_GROUP(tpu2_to2),
+        SH_PFC_PIN_GROUP(tpu2_to3),
+        SH_PFC_PIN_GROUP(tpu3_to0),
+        SH_PFC_PIN_GROUP(tpu3_to1),
+        SH_PFC_PIN_GROUP(tpu3_to2),
+        SH_PFC_PIN_GROUP(tpu3_to3),
+        SH_PFC_PIN_GROUP(tpu4_to0),
+        SH_PFC_PIN_GROUP(tpu4_to1),
+        SH_PFC_PIN_GROUP(tpu4_to2),
+        SH_PFC_PIN_GROUP(tpu4_to3),
         SH_PFC_PIN_GROUP(usb_vbus),
 };
 
@@ -2908,6 +3083,42 @@ static const char * const usb_groups[] = {
         "usb_vbus",
 };
 
+static const char * const tpu0_groups[] = {
+        "tpu0_to0",
+        "tpu0_to1",
+        "tpu0_to2",
+        "tpu0_to3",
+};
+
+static const char * const tpu1_groups[] = {
+        "tpu1_to0",
+        "tpu1_to1_0",
+        "tpu1_to1_1",
+        "tpu1_to2",
+        "tpu1_to3",
+};
+
+static const char * const tpu2_groups[] = {
+        "tpu2_to0",
+        "tpu2_to1",
+        "tpu2_to2",
+        "tpu2_to3",
+};
+
+static const char * const tpu3_groups[] = {
+        "tpu3_to0",
+        "tpu3_to1",
+        "tpu3_to2",
+        "tpu3_to3",
+};
+
+static const char * const tpu4_groups[] = {
+        "tpu4_to0",
+        "tpu4_to1",
+        "tpu4_to2",
+        "tpu4_to3",
+};
+
 static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(bsc),
         SH_PFC_FUNCTION(fsia),
@@ -2933,400 +3144,14 @@ static const struct sh_pfc_function pinmux_functions[] = {
         SH_PFC_FUNCTION(sdhi0),
         SH_PFC_FUNCTION(sdhi1),
         SH_PFC_FUNCTION(sdhi2),
+        SH_PFC_FUNCTION(tpu0),
+        SH_PFC_FUNCTION(tpu1),
+        SH_PFC_FUNCTION(tpu2),
+        SH_PFC_FUNCTION(tpu3),
+        SH_PFC_FUNCTION(tpu4),
         SH_PFC_FUNCTION(usb),
 };
 
-#define PINMUX_FN_BASE  GPIO_FN_GPI0
-
-static const struct pinmux_func pinmux_func_gpios[] = {
-        /* Table 25-1 (Functions 0-7) */
-        GPIO_FN(GPI0),
-        GPIO_FN(GPI1),
-        GPIO_FN(GPI2),
-        GPIO_FN(GPI3),
-        GPIO_FN(GPI4),
-        GPIO_FN(GPI5),
-        GPIO_FN(GPI6),
-        GPIO_FN(GPI7),
-        GPIO_FN(GPO7), \
-        GPIO_FN(MFG0_OUT2),
-        GPIO_FN(GPO6), \
-        GPIO_FN(MFG1_OUT2),
-        GPIO_FN(GPO5), \
-        GPIO_FN(PORT16_VIO_CKOR),
-        GPIO_FN(PORT19_VIO_CKO2),
-        GPIO_FN(GPO0),
-        GPIO_FN(GPO1),
-        GPIO_FN(GPO2), \
-        GPIO_FN(STATUS0),
-        GPIO_FN(GPO3), \
-        GPIO_FN(STATUS1),
-        GPIO_FN(GPO4), \
-        GPIO_FN(STATUS2),
-        GPIO_FN(VINT),
-        GPIO_FN(TCKON),
-        GPIO_FN(XDVFS1), \
-        GPIO_FN(MFG0_OUT1), \
-        GPIO_FN(PORT27_IROUT),
-        GPIO_FN(XDVFS2), \
-        GPIO_FN(PORT28_TPU1TO1),
-        GPIO_FN(SIM_RST), \
-        GPIO_FN(PORT29_TPU1TO1),
-        GPIO_FN(SIM_CLK), \
-        GPIO_FN(PORT30_VIO_CKOR),
-        GPIO_FN(SIM_D), \
-        GPIO_FN(PORT31_IROUT),
-        GPIO_FN(XWUP),
-        GPIO_FN(VACK),
-        GPIO_FN(XTAL1L),
-        GPIO_FN(PORT49_IROUT), \
-        GPIO_FN(BBIF2_TSYNC2), \
-        GPIO_FN(TPU2TO2), \
-
-        GPIO_FN(BBIF2_TSCK2), \
-        GPIO_FN(TPU2TO3), \
-        GPIO_FN(BBIF2_TXD2),
-        GPIO_FN(TPU3TO3), \
-        GPIO_FN(TPU3TO2), \
-        GPIO_FN(TPU0TO0),
-        GPIO_FN(A0), \
-        GPIO_FN(BS_),
-        GPIO_FN(A12), \
-        GPIO_FN(TPU4TO2),
-        GPIO_FN(A13), \
-        GPIO_FN(TPU0TO1),
-        GPIO_FN(A14), \
-        GPIO_FN(A15), \
-        GPIO_FN(A16), \
-        GPIO_FN(MSIOF0_SS1),
-        GPIO_FN(A17), \
-        GPIO_FN(MSIOF0_TSYNC),
-        GPIO_FN(A18), \
-        GPIO_FN(MSIOF0_TSCK),
-        GPIO_FN(A19), \
-        GPIO_FN(MSIOF0_TXD),
-        GPIO_FN(A20), \
-        GPIO_FN(MSIOF0_RSCK),
-        GPIO_FN(A21), \
-        GPIO_FN(MSIOF0_RSYNC),
-        GPIO_FN(A22), \
-        GPIO_FN(MSIOF0_MCK0),
-        GPIO_FN(A23), \
-        GPIO_FN(MSIOF0_MCK1),
-        GPIO_FN(A24), \
-        GPIO_FN(MSIOF0_RXD),
-        GPIO_FN(A25), \
-        GPIO_FN(MSIOF0_SS2),
-        GPIO_FN(A26), \
-        GPIO_FN(FCE1_),
-        GPIO_FN(DACK0),
-        GPIO_FN(FCE0_), \
-        GPIO_FN(WAIT_), \
-        GPIO_FN(DREQ0),
-        GPIO_FN(FRB),
-        GPIO_FN(CKO),
-        GPIO_FN(NBRSTOUT_),
-        GPIO_FN(NBRST_),
-        GPIO_FN(BBIF2_TXD),
-        GPIO_FN(BBIF2_RXD),
-        GPIO_FN(BBIF2_SYNC),
-        GPIO_FN(BBIF2_SCK),
-        GPIO_FN(MFG3_IN2),
-        GPIO_FN(MFG3_IN1),
-        GPIO_FN(BBIF1_SS2), \
-        GPIO_FN(MFG3_OUT1),
-        GPIO_FN(HSI_RX_DATA), \
-        GPIO_FN(BBIF1_RXD),
-        GPIO_FN(HSI_TX_WAKE), \
-        GPIO_FN(BBIF1_TSCK),
-        GPIO_FN(HSI_TX_DATA), \
-        GPIO_FN(BBIF1_TSYNC),
-        GPIO_FN(HSI_TX_READY), \
-        GPIO_FN(BBIF1_TXD),
-        GPIO_FN(HSI_RX_READY), \
-        GPIO_FN(BBIF1_RSCK), \
-        GPIO_FN(HSI_RX_WAKE), \
-        GPIO_FN(BBIF1_RSYNC), \
-        GPIO_FN(HSI_RX_FLAG), \
-        GPIO_FN(BBIF1_SS1), \
-        GPIO_FN(BBIF1_FLOW),
-        GPIO_FN(HSI_TX_FLAG),
-        GPIO_FN(VIO_VD), \
-        GPIO_FN(VIO2_VD), \
-
-        GPIO_FN(VIO_HD), \
-        GPIO_FN(VIO2_HD), \
-        GPIO_FN(VIO_D0), \
-        GPIO_FN(PORT130_MSIOF2_RXD), \
-        GPIO_FN(VIO_D1), \
-        GPIO_FN(PORT131_MSIOF2_SS1), \
-        GPIO_FN(VIO_D2), \
-        GPIO_FN(PORT132_MSIOF2_SS2), \
-        GPIO_FN(VIO_D3), \
-        GPIO_FN(MSIOF2_TSYNC), \
-        GPIO_FN(VIO_D4), \
-        GPIO_FN(MSIOF2_TXD), \
-        GPIO_FN(VIO_D5), \
-        GPIO_FN(MSIOF2_TSCK), \
-        GPIO_FN(VIO_D6), \
-        GPIO_FN(VIO_D7), \
-        GPIO_FN(VIO_D8), \
-        GPIO_FN(VIO2_D0), \
-        GPIO_FN(VIO_D9), \
-        GPIO_FN(VIO2_D1), \
-        GPIO_FN(VIO_D10), \
-        GPIO_FN(TPU0TO2), \
-        GPIO_FN(VIO2_D2), \
-        GPIO_FN(VIO_D11), \
-        GPIO_FN(TPU0TO3), \
-        GPIO_FN(VIO2_D3), \
-        GPIO_FN(VIO_D12), \
-        GPIO_FN(VIO2_D4), \
-        GPIO_FN(VIO_D13), \
-        GPIO_FN(VIO2_D5), \
-        GPIO_FN(VIO_D14), \
-        GPIO_FN(VIO2_D6), \
-        GPIO_FN(VIO_D15), \
-        GPIO_FN(TPU1TO3), \
-        GPIO_FN(VIO2_D7), \
-        GPIO_FN(VIO_CLK), \
-        GPIO_FN(VIO2_CLK), \
-        GPIO_FN(VIO_FIELD), \
-        GPIO_FN(VIO2_FIELD), \
-        GPIO_FN(VIO_CKO),
-        GPIO_FN(A27), \
-        GPIO_FN(MFG0_IN1), \
-        GPIO_FN(MFG0_IN2),
-        GPIO_FN(TS_SPSYNC3), \
-        GPIO_FN(MSIOF2_RSCK),
-        GPIO_FN(TS_SDAT3), \
-        GPIO_FN(MSIOF2_RSYNC),
-        GPIO_FN(TPU1TO2), \
-        GPIO_FN(TS_SDEN3), \
-        GPIO_FN(PORT153_MSIOF2_SS1),
-        GPIO_FN(MSIOF2_MCK0),
-        GPIO_FN(MSIOF2_MCK1),
-        GPIO_FN(PORT156_MSIOF2_SS2),
-        GPIO_FN(PORT157_MSIOF2_RXD),
-        GPIO_FN(DINT_), \
-        GPIO_FN(TS_SCK3),
-        GPIO_FN(NMI),
-        GPIO_FN(TPU3TO0),
-        GPIO_FN(BBIF2_TSYNC1),
-        GPIO_FN(BBIF2_TSCK1),
-        GPIO_FN(BBIF2_TXD1),
-        GPIO_FN(MFG2_OUT2), \
-        GPIO_FN(TPU2TO1),
-        GPIO_FN(TPU4TO1), \
-        GPIO_FN(MFG4_OUT2),
-        GPIO_FN(D16),
-        GPIO_FN(D17),
-        GPIO_FN(D18),
-        GPIO_FN(D19),
-        GPIO_FN(D20),
-        GPIO_FN(D21),
-        GPIO_FN(D22),
-        GPIO_FN(PORT207_MSIOF0L_SS1), \
-        GPIO_FN(D23),
-        GPIO_FN(PORT208_MSIOF0L_SS2), \
-        GPIO_FN(D24),
-        GPIO_FN(D25),
-        GPIO_FN(DREQ2), \
-        GPIO_FN(PORT210_MSIOF0L_SS1), \
-        GPIO_FN(D26),
-        GPIO_FN(PORT211_MSIOF0L_SS2), \
-        GPIO_FN(D27),
-        GPIO_FN(TS_SPSYNC1), \
-        GPIO_FN(MSIOF0L_MCK0), \
-        GPIO_FN(D28),
-        GPIO_FN(TS_SDAT1), \
-        GPIO_FN(MSIOF0L_MCK1), \
-        GPIO_FN(D29),
-        GPIO_FN(TS_SDEN1), \
-        GPIO_FN(MSIOF0L_RSCK), \
-        GPIO_FN(D30),
-        GPIO_FN(TS_SCK1), \
-        GPIO_FN(MSIOF0L_RSYNC), \
-        GPIO_FN(D31),
-        GPIO_FN(DACK2), \
-        GPIO_FN(MSIOF0L_TSYNC), \
-        GPIO_FN(VIO2_FIELD3), \
-        GPIO_FN(DACK3), \
-        GPIO_FN(PORT218_VIO_CKOR),
-        GPIO_FN(DREQ3), \
-        GPIO_FN(MSIOF0L_TSCK), \
-        GPIO_FN(VIO2_CLK3), \
-        GPIO_FN(DREQ1), \
-        GPIO_FN(PWEN), \
-        GPIO_FN(MSIOF0L_RXD), \
-        GPIO_FN(VIO2_HD3), \
-        GPIO_FN(DACK1), \
-        GPIO_FN(OVCN), \
-        GPIO_FN(MSIOF0L_TXD), \
-        GPIO_FN(VIO2_VD3), \
-
-        GPIO_FN(OVCN2),
-        GPIO_FN(EXTLP), \
-        GPIO_FN(PORT226_VIO_CKO2),
-        GPIO_FN(IDIN),
-        GPIO_FN(MFG1_IN1),
-        GPIO_FN(MSIOF1_TXD), \
-        GPIO_FN(MSIOF1_TSYNC), \
-        GPIO_FN(MSIOF1_TSCK), \
-        GPIO_FN(MSIOF1_RXD), \
-        GPIO_FN(MSIOF1_RSCK), \
-        GPIO_FN(VIO2_CLK2), \
-        GPIO_FN(MSIOF1_RSYNC), \
-        GPIO_FN(MFG1_IN2), \
-        GPIO_FN(VIO2_VD2), \
-        GPIO_FN(MSIOF1_MCK0), \
-        GPIO_FN(MSIOF1_MCK1), \
-        GPIO_FN(MSIOF1_SS1), \
-        GPIO_FN(VIO2_FIELD2), \
-        GPIO_FN(MSIOF1_SS2), \
-        GPIO_FN(VIO2_HD2), \
-        GPIO_FN(PORT241_IROUT), \
-        GPIO_FN(MFG4_OUT1), \
-        GPIO_FN(TPU4TO0),
-        GPIO_FN(MFG4_IN2),
-        GPIO_FN(PORT243_VIO_CKO2),
-        GPIO_FN(MFG2_IN1), \
-        GPIO_FN(MSIOF2R_RXD),
-        GPIO_FN(MFG2_IN2), \
-        GPIO_FN(MSIOF2R_TXD),
-        GPIO_FN(MFG1_OUT1), \
-        GPIO_FN(TPU1TO0),
-        GPIO_FN(MFG3_OUT2), \
-        GPIO_FN(TPU3TO1),
-        GPIO_FN(MFG2_OUT1), \
-        GPIO_FN(TPU2TO0), \
-        GPIO_FN(MSIOF2R_TSCK),
-        GPIO_FN(PORT249_IROUT), \
-        GPIO_FN(MFG4_IN1), \
-        GPIO_FN(MSIOF2R_TSYNC),
-        GPIO_FN(SDHICLK0),
-        GPIO_FN(SDHICD0),
-        GPIO_FN(SDHID0_0),
-        GPIO_FN(SDHID0_1),
-        GPIO_FN(SDHID0_2),
-        GPIO_FN(SDHID0_3),
-        GPIO_FN(SDHICMD0),
-        GPIO_FN(SDHIWP0),
-        GPIO_FN(SDHICLK1),
-        GPIO_FN(SDHID1_0), \
-        GPIO_FN(TS_SPSYNC2),
-        GPIO_FN(SDHID1_1), \
-        GPIO_FN(TS_SDAT2),
-        GPIO_FN(SDHID1_2), \
-        GPIO_FN(TS_SDEN2),
-        GPIO_FN(SDHID1_3), \
-        GPIO_FN(TS_SCK2),
-        GPIO_FN(SDHICMD1),
-        GPIO_FN(SDHICLK2),
-        GPIO_FN(SDHID2_0), \
-        GPIO_FN(TS_SPSYNC4),
-        GPIO_FN(SDHID2_1), \
-        GPIO_FN(TS_SDAT4),
-        GPIO_FN(SDHID2_2), \
-        GPIO_FN(TS_SDEN4),
-        GPIO_FN(SDHID2_3), \
-        GPIO_FN(TS_SCK4),
-        GPIO_FN(SDHICMD2),
-        GPIO_FN(MMCCLK0),
-        GPIO_FN(MMCD0_0),
-        GPIO_FN(MMCD0_1),
-        GPIO_FN(MMCD0_2),
-        GPIO_FN(MMCD0_3),
-        GPIO_FN(MMCD0_4), \
-        GPIO_FN(TS_SPSYNC5),
-        GPIO_FN(MMCD0_5), \
-        GPIO_FN(TS_SDAT5),
-        GPIO_FN(MMCD0_6), \
-        GPIO_FN(TS_SDEN5),
-        GPIO_FN(MMCD0_7), \
-        GPIO_FN(TS_SCK5),
-        GPIO_FN(MMCCMD0),
-        GPIO_FN(RESETOUTS_), \
-        GPIO_FN(EXTAL2OUT),
-        GPIO_FN(MCP_WAIT__MCP_FRB),
-        GPIO_FN(MCP_CKO), \
-        GPIO_FN(MMCCLK1),
-        GPIO_FN(MCP_D15_MCP_NAF15),
-        GPIO_FN(MCP_D14_MCP_NAF14),
-        GPIO_FN(MCP_D13_MCP_NAF13),
-        GPIO_FN(MCP_D12_MCP_NAF12),
-        GPIO_FN(MCP_D11_MCP_NAF11),
-        GPIO_FN(MCP_D10_MCP_NAF10),
-        GPIO_FN(MCP_D9_MCP_NAF9),
-        GPIO_FN(MCP_D8_MCP_NAF8), \
-        GPIO_FN(MMCCMD1),
-        GPIO_FN(MCP_D7_MCP_NAF7), \
-        GPIO_FN(MMCD1_7),
-
-        GPIO_FN(MCP_D6_MCP_NAF6), \
-        GPIO_FN(MMCD1_6),
-        GPIO_FN(MCP_D5_MCP_NAF5), \
-        GPIO_FN(MMCD1_5),
-        GPIO_FN(MCP_D4_MCP_NAF4), \
-        GPIO_FN(MMCD1_4),
-        GPIO_FN(MCP_D3_MCP_NAF3), \
-        GPIO_FN(MMCD1_3),
-        GPIO_FN(MCP_D2_MCP_NAF2), \
-        GPIO_FN(MMCD1_2),
-        GPIO_FN(MCP_D1_MCP_NAF1), \
-        GPIO_FN(MMCD1_1),
-        GPIO_FN(MCP_D0_MCP_NAF0), \
-        GPIO_FN(MMCD1_0),
-        GPIO_FN(MCP_NBRSTOUT_),
-        GPIO_FN(MCP_WE0__MCP_FWE), \
-        GPIO_FN(MCP_RDWR_MCP_FWE),
-
-        /* MSEL2 special cases */
-        GPIO_FN(TSIF2_TS_XX1),
-        GPIO_FN(TSIF2_TS_XX2),
-        GPIO_FN(TSIF2_TS_XX3),
-        GPIO_FN(TSIF2_TS_XX4),
-        GPIO_FN(TSIF2_TS_XX5),
-        GPIO_FN(TSIF1_TS_XX1),
-        GPIO_FN(TSIF1_TS_XX2),
-        GPIO_FN(TSIF1_TS_XX3),
-        GPIO_FN(TSIF1_TS_XX4),
-        GPIO_FN(TSIF1_TS_XX5),
-        GPIO_FN(TSIF0_TS_XX1),
-        GPIO_FN(TSIF0_TS_XX2),
-        GPIO_FN(TSIF0_TS_XX3),
-        GPIO_FN(TSIF0_TS_XX4),
-        GPIO_FN(TSIF0_TS_XX5),
-        GPIO_FN(MST1_TS_XX1),
-        GPIO_FN(MST1_TS_XX2),
-        GPIO_FN(MST1_TS_XX3),
-        GPIO_FN(MST1_TS_XX4),
-        GPIO_FN(MST1_TS_XX5),
-        GPIO_FN(MST0_TS_XX1),
-        GPIO_FN(MST0_TS_XX2),
-        GPIO_FN(MST0_TS_XX3),
-        GPIO_FN(MST0_TS_XX4),
-        GPIO_FN(MST0_TS_XX5),
-
-        /* MSEL3 special cases */
-        GPIO_FN(SDHI0_VCCQ_MC0_ON),
-        GPIO_FN(SDHI0_VCCQ_MC0_OFF),
-        GPIO_FN(DEBUG_MON_VIO),
-        GPIO_FN(DEBUG_MON_LCDD),
-        GPIO_FN(LCDC_LCDC0),
-        GPIO_FN(LCDC_LCDC1),
-
-        /* MSEL4 special cases */
-        GPIO_FN(IRQ9_MEM_INT),
-        GPIO_FN(IRQ9_MCP_INT),
-        GPIO_FN(A11),
-        GPIO_FN(TPU4TO3),
-        GPIO_FN(RESETA_N_PU_ON),
-        GPIO_FN(RESETA_N_PU_OFF),
-        GPIO_FN(EDBGREQ_PD),
-        GPIO_FN(EDBGREQ_PU),
-};
-
 #undef PORTCR
 #define PORTCR(nr, reg)                                                 \
         {                                                               \
@@ -3888,6 +3713,92 @@ static const struct pinmux_irq pinmux_irqs[] = {
         PINMUX_IRQ(EXT_IRQ16L(9), 308),
 };
 
+/* -----------------------------------------------------------------------------
+ * VCCQ MC0 regulator
+ */
+
+static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
+{
+        struct sh_pfc *pfc = reg->reg_data;
+        void __iomem *addr = pfc->window[1].virt + 4;
+        unsigned long flags;
+        u32 value;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+
+        value = ioread32(addr);
+
+        if (enable)
+                value |= BIT(28);
+        else
+                value &= ~BIT(28);
+
+        iowrite32(value, addr);
+
+        spin_unlock_irqrestore(&pfc->lock, flags);
+}
+
+static int sh73a0_vccq_mc0_enable(struct regulator_dev *reg)
+{
+        sh73a0_vccq_mc0_endisable(reg, true);
+        return 0;
+}
+
+static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
+{
+        sh73a0_vccq_mc0_endisable(reg, false);
+        return 0;
+}
+
+static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
+{
+        struct sh_pfc *pfc = reg->reg_data;
+        void __iomem *addr = pfc->window[1].virt + 4;
+        unsigned long flags;
+        u32 value;
+
+        spin_lock_irqsave(&pfc->lock, flags);
+        value = ioread32(addr);
+        spin_unlock_irqrestore(&pfc->lock, flags);
+
+        return !!(value & BIT(28));
+}
+
+static int sh73a0_vccq_mc0_get_voltage(struct regulator_dev *reg)
+{
+        return 3300000;
+}
+
+static struct regulator_ops sh73a0_vccq_mc0_ops = {
+        .enable = sh73a0_vccq_mc0_enable,
+        .disable = sh73a0_vccq_mc0_disable,
+        .is_enabled = sh73a0_vccq_mc0_is_enabled,
+        .get_voltage = sh73a0_vccq_mc0_get_voltage,
+};
+
+static const struct regulator_desc sh73a0_vccq_mc0_desc = {
+        .owner = THIS_MODULE,
+        .name = "vccq_mc0",
+        .type = REGULATOR_VOLTAGE,
+        .ops = &sh73a0_vccq_mc0_ops,
+};
+
+static struct regulator_consumer_supply sh73a0_vccq_mc0_consumers[] = {
+        REGULATOR_SUPPLY("vqmmc", "sh_mobile_sdhi.0"),
+};
+
+static const struct regulator_init_data sh73a0_vccq_mc0_init_data = {
+        .constraints = {
+                .valid_ops_mask = REGULATOR_CHANGE_STATUS,
+        },
+        .num_consumer_supplies = ARRAY_SIZE(sh73a0_vccq_mc0_consumers),
+        .consumer_supplies = sh73a0_vccq_mc0_consumers,
+};
+
+/* -----------------------------------------------------------------------------
+ * Pin bias
+ */
+
 #define PORTnCR_PULMD_OFF       (0 << 6)
 #define PORTnCR_PULMD_DOWN      (2 << 6)
 #define PORTnCR_PULMD_UP        (3 << 6)
@@ -3934,7 +3845,51 @@ static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
         iowrite8(value, addr);
 }
 
+/* -----------------------------------------------------------------------------
+ * SoC information
+ */
+
+struct sh73a0_pinmux_data {
+        struct regulator_dev *vccq_mc0;
+};
+
+static int sh73a0_pinmux_soc_init(struct sh_pfc *pfc)
+{
+        struct sh73a0_pinmux_data *data;
+        struct regulator_config cfg = { };
+        int ret;
+
+        data = devm_kzalloc(pfc->dev, sizeof(*data), GFP_KERNEL);
+        if (data == NULL)
+                return -ENOMEM;
+
+        cfg.dev = pfc->dev;
+        cfg.init_data = &sh73a0_vccq_mc0_init_data;
+        cfg.driver_data = pfc;
+
+        data->vccq_mc0 = regulator_register(&sh73a0_vccq_mc0_desc, &cfg);
+        if (IS_ERR(data->vccq_mc0)) {
+                ret = PTR_ERR(data->vccq_mc0);
+                dev_err(pfc->dev, "Failed to register VCCQ MC0 regulator: %d\n",
+                        ret);
+                return ret;
+        }
+
+        pfc->soc_data = data;
+
+        return 0;
+}
+
+static void sh73a0_pinmux_soc_exit(struct sh_pfc *pfc)
+{
+        struct sh73a0_pinmux_data *data = pfc->soc_data;
+
+        regulator_unregister(data->vccq_mc0);
+}
+
 static const struct sh_pfc_soc_operations sh73a0_pinmux_ops = {
+        .init = sh73a0_pinmux_soc_init,
+        .exit = sh73a0_pinmux_soc_exit,
         .get_bias = sh73a0_pinmux_get_bias,
         .set_bias = sh73a0_pinmux_set_bias,
 };
@@ -3956,9 +3911,6 @@ const struct sh_pfc_soc_info sh73a0_pinmux_info = {
         .functions = pinmux_functions,
         .nr_functions = ARRAY_SIZE(pinmux_functions),
 
-        .func_gpios = pinmux_func_gpios,
-        .nr_func_gpios = ARRAY_SIZE(pinmux_func_gpios),
-
         .cfg_regs = pinmux_config_regs,
         .data_regs = pinmux_data_regs,
 
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index 3b785fc428d5..830ae1ffd0b5 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -11,8 +11,8 @@
 #ifndef __SH_PFC_H
 #define __SH_PFC_H
 
+#include <linux/bug.h>
 #include <linux/stringify.h>
-#include <asm-generic/gpio.h>
 
 typedef unsigned short pinmux_enum_t;
 
@@ -129,6 +129,8 @@ struct pinmux_range {
 struct sh_pfc;
 
 struct sh_pfc_soc_operations {
+        int (*init)(struct sh_pfc *pfc);
+        void (*exit)(struct sh_pfc *pfc);
         unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
         void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
                          unsigned int bias);
diff --git a/drivers/pinctrl/vt8500/pinctrl-wmt.c b/drivers/pinctrl/vt8500/pinctrl-wmt.c
index ab63104e8dc9..70d986e04afb 100644
--- a/drivers/pinctrl/vt8500/pinctrl-wmt.c
+++ b/drivers/pinctrl/vt8500/pinctrl-wmt.c
@@ -609,8 +609,7 @@ int wmt_pinctrl_probe(struct platform_device *pdev,
         return 0;
 
 fail_range:
-        err = gpiochip_remove(&data->gpio_chip);
-        if (err)
+        if (gpiochip_remove(&data->gpio_chip))
                 dev_err(&pdev->dev, "failed to remove gpio chip\n");
 fail_gpio:
         pinctrl_unregister(data->pctl_dev);
diff --git a/drivers/platform/x86/hp-wmi.c b/drivers/platform/x86/hp-wmi.c
index 8df0c5a21be2..d111c8687f9b 100644
--- a/drivers/platform/x86/hp-wmi.c
+++ b/drivers/platform/x86/hp-wmi.c
@@ -703,7 +703,7 @@ static int hp_wmi_rfkill_setup(struct platform_device *device)
                 }
                 rfkill_init_sw_state(gps_rfkill,
                                      hp_wmi_get_sw_state(HPWMI_GPS));
-                rfkill_set_hw_state(bluetooth_rfkill,
+                rfkill_set_hw_state(gps_rfkill,
                                     hp_wmi_get_hw_state(HPWMI_GPS));
                 err = rfkill_register(gps_rfkill);
                 if (err)
diff --git a/drivers/ptp/ptp_pch.c b/drivers/ptp/ptp_pch.c
index bea94510ad2d..71a2559278d7 100644
--- a/drivers/ptp/ptp_pch.c
+++ b/drivers/ptp/ptp_pch.c
@@ -628,9 +628,10 @@ pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 
         chip->caps = ptp_pch_caps;
         chip->ptp_clock = ptp_clock_register(&chip->caps, &pdev->dev);
-
-        if (IS_ERR(chip->ptp_clock))
-                return PTR_ERR(chip->ptp_clock);
+        if (IS_ERR(chip->ptp_clock)) {
+                ret = PTR_ERR(chip->ptp_clock);
+                goto err_ptp_clock_reg;
+        }
 
         spin_lock_init(&chip->register_lock);
 
@@ -669,6 +670,7 @@ pch_probe(struct pci_dev *pdev, const struct pci_device_id *id)
 
 err_req_irq:
         ptp_clock_unregister(chip->ptp_clock);
+err_ptp_clock_reg:
         iounmap(chip->regs);
         chip->regs = NULL;
 
diff --git a/drivers/regulator/core.c b/drivers/regulator/core.c
index 6e5017841582..815d6df8bd5f 100644
--- a/drivers/regulator/core.c
+++ b/drivers/regulator/core.c
@@ -1539,7 +1539,10 @@ static void regulator_ena_gpio_free(struct regulator_dev *rdev)
 }
 
 /**
- * Balance enable_count of each GPIO and actual GPIO pin control.
+ * regulator_ena_gpio_ctrl - balance enable_count of each GPIO and actual GPIO pin control
+ * @rdev: regulator_dev structure
+ * @enable: enable GPIO at initial use?
+ *
  * GPIO is enabled in case of initial use. (enable_count is 0)
  * GPIO is disabled when it is not shared any more. (enable_count <= 1)
  */
@@ -2702,7 +2705,7 @@ EXPORT_SYMBOL_GPL(regulator_get_voltage);
 /**
  * regulator_set_current_limit - set regulator output current limit
  * @regulator: regulator source
- * @min_uA: Minimuum supported current in uA
+ * @min_uA: Minimum supported current in uA
  * @max_uA: Maximum supported current in uA
  *
  * Sets current sink to the desired output current. This can be set during
diff --git a/drivers/regulator/dbx500-prcmu.c b/drivers/regulator/dbx500-prcmu.c
index 89bd2faaef8c..ce89f7848a57 100644
--- a/drivers/regulator/dbx500-prcmu.c
+++ b/drivers/regulator/dbx500-prcmu.c
@@ -24,18 +24,6 @@
 static int power_state_active_cnt; /* will initialize to zero */
 static DEFINE_SPINLOCK(power_state_active_lock);
 
-int power_state_active_get(void)
-{
-        unsigned long flags;
-        int cnt;
-
-        spin_lock_irqsave(&power_state_active_lock, flags);
-        cnt = power_state_active_cnt;
-        spin_unlock_irqrestore(&power_state_active_lock, flags);
-
-        return cnt;
-}
-
 void power_state_active_enable(void)
 {
         unsigned long flags;
@@ -65,6 +53,18 @@ out:
 
 #ifdef CONFIG_REGULATOR_DEBUG
 
+static int power_state_active_get(void)
+{
+        unsigned long flags;
+        int cnt;
+
+        spin_lock_irqsave(&power_state_active_lock, flags);
+        cnt = power_state_active_cnt;
+        spin_unlock_irqrestore(&power_state_active_lock, flags);
+
+        return cnt;
+}
+
 static struct ux500_regulator_debug {
         struct dentry *dir;
         struct dentry *status_file;
diff --git a/drivers/regulator/palmas-regulator.c b/drivers/regulator/palmas-regulator.c
index 92ceed0fc65e..3ae44ac12a94 100644
--- a/drivers/regulator/palmas-regulator.c
+++ b/drivers/regulator/palmas-regulator.c
@@ -840,7 +840,7 @@ static int palmas_regulators_probe(struct platform_device *pdev)
                         break;
                 }
 
-                if ((id == PALMAS_REG_SMPS6) && (id == PALMAS_REG_SMPS8))
+                if ((id == PALMAS_REG_SMPS6) || (id == PALMAS_REG_SMPS8))
                         ramp_delay_support = true;
 
                 if (ramp_delay_support) {
@@ -878,7 +878,7 @@ static int palmas_regulators_probe(struct platform_device *pdev)
                         pmic->desc[id].vsel_mask = SMPS10_VSEL;
                         pmic->desc[id].enable_reg =
                                         PALMAS_BASE_TO_REG(PALMAS_SMPS_BASE,
-                                                        PALMAS_SMPS10_STATUS);
+                                                        PALMAS_SMPS10_CTRL);
                         pmic->desc[id].enable_mask = SMPS10_BOOST_EN;
                         pmic->desc[id].min_uV = 3750000;
                         pmic->desc[id].uV_step = 1250000;
diff --git a/drivers/rtc/rtc-at91rm9200.c b/drivers/rtc/rtc-at91rm9200.c
index 0eab77b22340..f296f3f7db9b 100644
--- a/drivers/rtc/rtc-at91rm9200.c
+++ b/drivers/rtc/rtc-at91rm9200.c
@@ -25,6 +25,7 @@
 #include <linux/rtc.h>
 #include <linux/bcd.h>
 #include <linux/interrupt.h>
+#include <linux/spinlock.h>
 #include <linux/ioctl.h>
 #include <linux/completion.h>
 #include <linux/io.h>
@@ -42,10 +43,65 @@
 
 #define AT91_RTC_EPOCH          1900UL  /* just like arch/arm/common/rtctime.c */
 
+struct at91_rtc_config {
+        bool use_shadow_imr;
+};
+
+static const struct at91_rtc_config *at91_rtc_config;
 static DECLARE_COMPLETION(at91_rtc_updated);
 static unsigned int at91_alarm_year = AT91_RTC_EPOCH;
 static void __iomem *at91_rtc_regs;
 static int irq;
+static DEFINE_SPINLOCK(at91_rtc_lock);
+static u32 at91_rtc_shadow_imr;
+
+static void at91_rtc_write_ier(u32 mask)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&at91_rtc_lock, flags);
+        at91_rtc_shadow_imr |= mask;
+        at91_rtc_write(AT91_RTC_IER, mask);
+        spin_unlock_irqrestore(&at91_rtc_lock, flags);
+}
+
+static void at91_rtc_write_idr(u32 mask)
+{
+        unsigned long flags;
+
+        spin_lock_irqsave(&at91_rtc_lock, flags);
+        at91_rtc_write(AT91_RTC_IDR, mask);
+        /*
+         * Register read back (of any RTC-register) needed to make sure
+         * IDR-register write has reached the peripheral before updating
+         * shadow mask.
+         *
+         * Note that there is still a possibility that the mask is updated
+         * before interrupts have actually been disabled in hardware. The only
+         * way to be certain would be to poll the IMR-register, which is is
+         * the very register we are trying to emulate. The register read back
+         * is a reasonable heuristic.
+         */
+        at91_rtc_read(AT91_RTC_SR);
+        at91_rtc_shadow_imr &= ~mask;
+        spin_unlock_irqrestore(&at91_rtc_lock, flags);
+}
+
+static u32 at91_rtc_read_imr(void)
+{
+        unsigned long flags;
+        u32 mask;
+
+        if (at91_rtc_config->use_shadow_imr) {
+                spin_lock_irqsave(&at91_rtc_lock, flags);
+                mask = at91_rtc_shadow_imr;
+                spin_unlock_irqrestore(&at91_rtc_lock, flags);
+        } else {
+                mask = at91_rtc_read(AT91_RTC_IMR);
+        }
+
+        return mask;
+}
 
 /*
  * Decode time/date into rtc_time structure
@@ -110,9 +166,9 @@ static int at91_rtc_settime(struct device *dev, struct rtc_time *tm)
         cr = at91_rtc_read(AT91_RTC_CR);
         at91_rtc_write(AT91_RTC_CR, cr | AT91_RTC_UPDCAL | AT91_RTC_UPDTIM);
 
-        at91_rtc_write(AT91_RTC_IER, AT91_RTC_ACKUPD);
+        at91_rtc_write_ier(AT91_RTC_ACKUPD);
         wait_for_completion(&at91_rtc_updated); /* wait for ACKUPD interrupt */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD);
+        at91_rtc_write_idr(AT91_RTC_ACKUPD);
 
         at91_rtc_write(AT91_RTC_TIMR,
                           bin2bcd(tm->tm_sec) << 0
@@ -144,7 +200,7 @@ static int at91_rtc_readalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm->tm_yday = rtc_year_days(tm->tm_mday, tm->tm_mon, tm->tm_year);
         tm->tm_year = at91_alarm_year - 1900;
 
-        alrm->enabled = (at91_rtc_read(AT91_RTC_IMR) & AT91_RTC_ALARM)
+        alrm->enabled = (at91_rtc_read_imr() & AT91_RTC_ALARM)
                         ? 1 : 0;
 
         dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -169,7 +225,7 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
         tm.tm_min = alrm->time.tm_min;
         tm.tm_sec = alrm->time.tm_sec;
 
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+        at91_rtc_write_idr(AT91_RTC_ALARM);
         at91_rtc_write(AT91_RTC_TIMALR,
                   bin2bcd(tm.tm_sec) << 0
                 | bin2bcd(tm.tm_min) << 8
@@ -182,7 +238,7 @@ static int at91_rtc_setalarm(struct device *dev, struct rtc_wkalrm *alrm)
 
         if (alrm->enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
+                at91_rtc_write_ier(AT91_RTC_ALARM);
         }
 
         dev_dbg(dev, "%s(): %4d-%02d-%02d %02d:%02d:%02d\n", __func__,
@@ -198,9 +254,9 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
 
         if (enabled) {
                 at91_rtc_write(AT91_RTC_SCCR, AT91_RTC_ALARM);
-                at91_rtc_write(AT91_RTC_IER, AT91_RTC_ALARM);
+                at91_rtc_write_ier(AT91_RTC_ALARM);
         } else
-                at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ALARM);
+                at91_rtc_write_idr(AT91_RTC_ALARM);
 
         return 0;
 }
@@ -209,7 +265,7 @@ static int at91_rtc_alarm_irq_enable(struct device *dev, unsigned int enabled)
  */
 static int at91_rtc_proc(struct device *dev, struct seq_file *seq)
 {
-        unsigned long imr = at91_rtc_read(AT91_RTC_IMR);
+        unsigned long imr = at91_rtc_read_imr();
 
         seq_printf(seq, "update_IRQ\t: %s\n",
                         (imr & AT91_RTC_ACKUPD) ? "yes" : "no");
@@ -229,7 +285,7 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
         unsigned int rtsr;
         unsigned long events = 0;
 
-        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read(AT91_RTC_IMR);
+        rtsr = at91_rtc_read(AT91_RTC_SR) & at91_rtc_read_imr();
         if (rtsr) {             /* this interrupt is shared!  Is it ours? */
                 if (rtsr & AT91_RTC_ALARM)
                         events |= (RTC_AF | RTC_IRQF);
@@ -250,6 +306,43 @@ static irqreturn_t at91_rtc_interrupt(int irq, void *dev_id)
         return IRQ_NONE;                /* not handled */
 }
 
+static const struct at91_rtc_config at91rm9200_config = {
+};
+
+static const struct at91_rtc_config at91sam9x5_config = {
+        .use_shadow_imr = true,
+};
+
+#ifdef CONFIG_OF
+static const struct of_device_id at91_rtc_dt_ids[] = {
+        {
+                .compatible = "atmel,at91rm9200-rtc",
+                .data = &at91rm9200_config,
+        }, {
+                .compatible = "atmel,at91sam9x5-rtc",
+                .data = &at91sam9x5_config,
+        }, {
+                /* sentinel */
+        }
+};
+MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
+#endif
+
+static const struct at91_rtc_config *
+at91_rtc_get_config(struct platform_device *pdev)
+{
+        const struct of_device_id *match;
+
+        if (pdev->dev.of_node) {
+                match = of_match_node(at91_rtc_dt_ids, pdev->dev.of_node);
+                if (!match)
+                        return NULL;
+                return (const struct at91_rtc_config *)match->data;
+        }
+
+        return &at91rm9200_config;
+}
+
 static const struct rtc_class_ops at91_rtc_ops = {
         .read_time      = at91_rtc_readtime,
         .set_time       = at91_rtc_settime,
@@ -268,6 +361,10 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
         struct resource *regs;
         int ret = 0;
 
+        at91_rtc_config = at91_rtc_get_config(pdev);
+        if (!at91_rtc_config)
+                return -ENODEV;
+
         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
         if (!regs) {
                 dev_err(&pdev->dev, "no mmio resource defined\n");
@@ -290,7 +387,7 @@ static int __init at91_rtc_probe(struct platform_device *pdev)
         at91_rtc_write(AT91_RTC_MR, 0);         /* 24 hour mode */
 
         /* Disable all interrupts */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+        at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
 
@@ -335,7 +432,7 @@ static int __exit at91_rtc_remove(struct platform_device *pdev)
         struct rtc_device *rtc = platform_get_drvdata(pdev);
 
         /* Disable all interrupts */
-        at91_rtc_write(AT91_RTC_IDR, AT91_RTC_ACKUPD | AT91_RTC_ALARM |
+        at91_rtc_write_idr(AT91_RTC_ACKUPD | AT91_RTC_ALARM |
                                         AT91_RTC_SECEV | AT91_RTC_TIMEV |
                                         AT91_RTC_CALEV);
         free_irq(irq, pdev);
@@ -358,13 +455,13 @@ static int at91_rtc_suspend(struct device *dev)
         /* this IRQ is shared with DBGU and other hardware which isn't
          * necessarily doing PM like we are...
          */
-        at91_rtc_imr = at91_rtc_read(AT91_RTC_IMR)
+        at91_rtc_imr = at91_rtc_read_imr()
                         & (AT91_RTC_ALARM|AT91_RTC_SECEV);
         if (at91_rtc_imr) {
                 if (device_may_wakeup(dev))
                         enable_irq_wake(irq);
                 else
-                        at91_rtc_write(AT91_RTC_IDR, at91_rtc_imr);
+                        at91_rtc_write_idr(at91_rtc_imr);
         }
         return 0;
 }
@@ -375,7 +472,7 @@ static int at91_rtc_resume(struct device *dev)
                 if (device_may_wakeup(dev))
                         disable_irq_wake(irq);
                 else
-                        at91_rtc_write(AT91_RTC_IER, at91_rtc_imr);
+                        at91_rtc_write_ier(at91_rtc_imr);
         }
         return 0;
 }
@@ -383,12 +480,6 @@ static int at91_rtc_resume(struct device *dev)
 
 static SIMPLE_DEV_PM_OPS(at91_rtc_pm_ops, at91_rtc_suspend, at91_rtc_resume);
 
-static const struct of_device_id at91_rtc_dt_ids[] = {
-        { .compatible = "atmel,at91rm9200-rtc" },
-        { /* sentinel */ }
-};
-MODULE_DEVICE_TABLE(of, at91_rtc_dt_ids);
-
 static struct platform_driver at91_rtc_driver = {
         .remove         = __exit_p(at91_rtc_remove),
         .driver         = {
diff --git a/drivers/rtc/rtc-cmos.c b/drivers/rtc/rtc-cmos.c
index cc5bea9c4b1c..f1cb706445c7 100644
--- a/drivers/rtc/rtc-cmos.c
+++ b/drivers/rtc/rtc-cmos.c
@@ -854,6 +854,9 @@ static int cmos_resume(struct device *dev)
                 }
 
                 spin_lock_irq(&rtc_lock);
+                if (device_may_wakeup(dev))
+                        hpet_rtc_timer_init();
+
                 do {
                         CMOS_WRITE(tmp, RTC_CONTROL);
                         hpet_set_rtc_irq_bit(tmp & RTC_IRQMASK);
@@ -869,7 +872,6 @@ static int cmos_resume(struct device *dev)
                         rtc_update_irq(cmos->rtc, 1, mask);
                         tmp &= ~RTC_AIE;
                         hpet_mask_rtc_irq_bit(RTC_AIE);
-                        hpet_rtc_timer_init();
                 } while (mask & RTC_AIE);
                 spin_unlock_irq(&rtc_lock);
         }
diff --git a/drivers/rtc/rtc-coh901331.c b/drivers/rtc/rtc-coh901331.c
index 93c06588ddca..ad6863a76af9 100644
--- a/drivers/rtc/rtc-coh901331.c
+++ b/drivers/rtc/rtc-coh901331.c
@@ -274,11 +274,17 @@ static void coh901331_shutdown(struct platform_device *pdev)
         clk_disable_unprepare(rtap->clk);
 }
 
+static const struct of_device_id coh901331_dt_match[] = {
+        { .compatible = "stericsson,coh901331" },
+        {},
+};
+
 static struct platform_driver coh901331_driver = {
         .driver = {
                 .name = "rtc-coh901331",
                 .owner = THIS_MODULE,
                 .pm = &coh901331_pm_ops,
+                .of_match_table = coh901331_dt_match,
         },
         .remove = __exit_p(coh901331_remove),
         .shutdown = coh901331_shutdown,
diff --git a/drivers/rtc/rtc-tps6586x.c b/drivers/rtc/rtc-tps6586x.c
index 459c2ffc95a6..426901cef14f 100644
--- a/drivers/rtc/rtc-tps6586x.c
+++ b/drivers/rtc/rtc-tps6586x.c
@@ -273,6 +273,8 @@ static int tps6586x_rtc_probe(struct platform_device *pdev)
                 return ret;
         }
 
+        device_init_wakeup(&pdev->dev, 1);
+
         platform_set_drvdata(pdev, rtc);
         rtc->rtc = devm_rtc_device_register(&pdev->dev, dev_name(&pdev->dev),
                                        &tps6586x_rtc_ops, THIS_MODULE);
@@ -292,7 +294,6 @@ static int tps6586x_rtc_probe(struct platform_device *pdev)
                 goto fail_rtc_register;
         }
         disable_irq(rtc->irq);
-        device_set_wakeup_capable(&pdev->dev, 1);
         return 0;
 
 fail_rtc_register:
diff --git a/drivers/rtc/rtc-twl.c b/drivers/rtc/rtc-twl.c
index 8751a5240c99..b2eab34f38d9 100644
--- a/drivers/rtc/rtc-twl.c
+++ b/drivers/rtc/rtc-twl.c
@@ -524,6 +524,7 @@ static int twl_rtc_probe(struct platform_device *pdev)
         }
 
         platform_set_drvdata(pdev, rtc);
+        device_init_wakeup(&pdev->dev, 1);
         return 0;
 
 out2:
diff --git a/drivers/s390/block/dasd.c b/drivers/s390/block/dasd.c
index 4361d9772c42..d72a9216ee2e 100644
--- a/drivers/s390/block/dasd.c
+++ b/drivers/s390/block/dasd.c
@@ -3440,8 +3440,16 @@ void dasd_generic_path_event(struct ccw_device *cdev, int *path_event)
                         device->path_data.opm &= ~eventlpm;
                         device->path_data.ppm &= ~eventlpm;
                         device->path_data.npm &= ~eventlpm;
-                        if (oldopm && !device->path_data.opm)
-                                dasd_generic_last_path_gone(device);
+                        if (oldopm && !device->path_data.opm) {
+                                dev_warn(&device->cdev->dev,
+                                         "No verified channel paths remain "
+                                         "for the device\n");
+                                DBF_DEV_EVENT(DBF_WARNING, device,
+                                              "%s", "last verified path gone");
+                                dasd_eer_write(device, NULL, DASD_EER_NOPATH);
+                                dasd_device_set_stop_bits(device,
+                                                          DASD_STOPPED_DC_WAIT);
+                        }
                 }
                 if (path_event[chp] & PE_PATH_AVAILABLE) {
                         device->path_data.opm &= ~eventlpm;
diff --git a/drivers/s390/net/netiucv.c b/drivers/s390/net/netiucv.c
index 4ffa66c87ea5..9ca3996f65b2 100644
--- a/drivers/s390/net/netiucv.c
+++ b/drivers/s390/net/netiucv.c
@@ -2040,6 +2040,7 @@ static struct net_device *netiucv_init_netdevice(char *username, char *userdata)
                            netiucv_setup_netdevice);
         if (!dev)
                 return NULL;
+        rtnl_lock();
         if (dev_alloc_name(dev, dev->name) < 0)
                 goto out_netdev;
 
@@ -2061,6 +2062,7 @@ static struct net_device *netiucv_init_netdevice(char *username, char *userdata)
 out_fsm:
         kfree_fsm(privptr->fsm);
 out_netdev:
+        rtnl_unlock();
         free_netdev(dev);
         return NULL;
 }
@@ -2100,6 +2102,7 @@ static ssize_t conn_write(struct device_driver *drv,
 
         rc = netiucv_register_device(dev);
         if (rc) {
+                rtnl_unlock();
                 IUCV_DBF_TEXT_(setup, 2,
                         "ret %d from netiucv_register_device\n", rc);
                 goto out_free_ndev;
@@ -2109,7 +2112,8 @@ static ssize_t conn_write(struct device_driver *drv,
         priv = netdev_priv(dev);
         SET_NETDEV_DEV(dev, priv->dev);
 
-        rc = register_netdev(dev);
+        rc = register_netdevice(dev);
+        rtnl_unlock();
         if (rc)
                 goto out_unreg;
 
diff --git a/drivers/scsi/qla2xxx/tcm_qla2xxx.c b/drivers/scsi/qla2xxx/tcm_qla2xxx.c
index d182c96e17ea..7a3870f385f6 100644
--- a/drivers/scsi/qla2xxx/tcm_qla2xxx.c
+++ b/drivers/scsi/qla2xxx/tcm_qla2xxx.c
@@ -1370,7 +1370,7 @@ static void tcm_qla2xxx_free_session(struct qla_tgt_sess *sess)
                 dump_stack();
                 return;
         }
-        target_wait_for_sess_cmds(se_sess, 0);
+        target_wait_for_sess_cmds(se_sess);
 
         transport_deregister_session_configfs(sess->se_sess);
         transport_deregister_session(sess->se_sess);
diff --git a/drivers/scsi/scsi_proc.c b/drivers/scsi/scsi_proc.c
index db66357211ed..86f0c5d5c116 100644
--- a/drivers/scsi/scsi_proc.c
+++ b/drivers/scsi/scsi_proc.c
@@ -84,6 +84,7 @@ static int proc_scsi_host_open(struct inode *inode, struct file *file)
 
 static const struct file_operations proc_scsi_fops = {
         .open = proc_scsi_host_open,
+        .release = single_release,
         .read = seq_read,
         .llseek = seq_lseek,
         .write = proc_scsi_host_write
diff --git a/drivers/spi/spi-pl022.c b/drivers/spi/spi-pl022.c
index 371cc66f1a0e..3b246543282f 100644
--- a/drivers/spi/spi-pl022.c
+++ b/drivers/spi/spi-pl022.c
@@ -2083,6 +2083,7 @@ pl022_platform_data_dt_get(struct device *dev)
         }
 
         pd->bus_id = -1;
+        pd->enable_dma = 1;
         of_property_read_u32(np, "num-cs", &tmp);
         pd->num_chipselect = tmp;
         of_property_read_u32(np, "pl022,autosuspend-delay",
diff --git a/drivers/spi/spi-sh-hspi.c b/drivers/spi/spi-sh-hspi.c
index 60cfae51c713..eab593eaaafa 100644
--- a/drivers/spi/spi-sh-hspi.c
+++ b/drivers/spi/spi-sh-hspi.c
@@ -89,7 +89,7 @@ static int hspi_status_check_timeout(struct hspi_priv *hspi, u32 mask, u32 val)
                 if ((mask & hspi_read(hspi, SPSR)) == val)
                         return 0;
 
-                msleep(20);
+                udelay(10);
         }
 
         dev_err(hspi->dev, "timeout\n");
diff --git a/drivers/spi/spi-topcliff-pch.c b/drivers/spi/spi-topcliff-pch.c
index 35f60bd252dd..637d728fbeb5 100644
--- a/drivers/spi/spi-topcliff-pch.c
+++ b/drivers/spi/spi-topcliff-pch.c
@@ -1487,7 +1487,7 @@ static int pch_spi_pd_probe(struct platform_device *plat_dev)
         return 0;
 
 err_spi_register_master:
-        free_irq(board_dat->pdev->irq, board_dat);
+        free_irq(board_dat->pdev->irq, data);
 err_request_irq:
         pch_spi_free_resources(board_dat, data);
 err_spi_get_resources:
@@ -1667,6 +1667,7 @@ static int pch_spi_probe(struct pci_dev *pdev,
                 pd_dev = platform_device_alloc("pch-spi", i);
                 if (!pd_dev) {
                         dev_err(&pdev->dev, "platform_device_alloc failed\n");
+                        retval = -ENOMEM;
                         goto err_platform_device;
                 }
                 pd_dev_save->pd_save[i] = pd_dev;
diff --git a/drivers/spi/spi-xilinx.c b/drivers/spi/spi-xilinx.c
index e1d769607425..34d18dcfa0db 100644
--- a/drivers/spi/spi-xilinx.c
+++ b/drivers/spi/spi-xilinx.c
@@ -267,7 +267,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
 {
         struct xilinx_spi *xspi = spi_master_get_devdata(spi->master);
         u32 ipif_ier;
-        u16 cr;
 
         /* We get here with transmitter inhibited */
 
@@ -276,7 +275,6 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
         xspi->remaining_bytes = t->len;
         INIT_COMPLETION(xspi->done);
 
-        xilinx_spi_fill_tx_fifo(xspi);
 
         /* Enable the transmit empty interrupt, which we use to determine
          * progress on the transmission.
@@ -285,12 +283,41 @@ static int xilinx_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t)
         xspi->write_fn(ipif_ier | XSPI_INTR_TX_EMPTY,
                 xspi->regs + XIPIF_V123B_IIER_OFFSET);
 
-        /* Start the transfer by not inhibiting the transmitter any longer */
-        cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
-                ~XSPI_CR_TRANS_INHIBIT;
-        xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
+        for (;;) {
+                u16 cr;
+                u8 sr;
+
+                xilinx_spi_fill_tx_fifo(xspi);
+
+                /* Start the transfer by not inhibiting the transmitter any
+                 * longer
+                 */
+                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET) &
+                                                        ~XSPI_CR_TRANS_INHIBIT;
+                xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
+
+                wait_for_completion(&xspi->done);
+
+                /* A transmit has just completed. Process received data and
+                 * check for more data to transmit. Always inhibit the
+                 * transmitter while the Isr refills the transmit register/FIFO,
+                 * or make sure it is stopped if we're done.
+                 */
+                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
+                xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
+                               xspi->regs + XSPI_CR_OFFSET);
+
+                /* Read out all the data from the Rx FIFO */
+                sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
+                while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
+                        xspi->rx_fn(xspi);
+                        sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
+                }
 
-        wait_for_completion(&xspi->done);
+                /* See if there is more data to send */
+                if (!xspi->remaining_bytes > 0)
+                        break;
+        }
 
         /* Disable the transmit empty interrupt */
         xspi->write_fn(ipif_ier, xspi->regs + XIPIF_V123B_IIER_OFFSET);
@@ -314,38 +341,7 @@ static irqreturn_t xilinx_spi_irq(int irq, void *dev_id)
         xspi->write_fn(ipif_isr, xspi->regs + XIPIF_V123B_IISR_OFFSET);
 
         if (ipif_isr & XSPI_INTR_TX_EMPTY) {    /* Transmission completed */
-                u16 cr;
-                u8 sr;
-
-                /* A transmit has just completed. Process received data and
-                 * check for more data to transmit. Always inhibit the
-                 * transmitter while the Isr refills the transmit register/FIFO,
-                 * or make sure it is stopped if we're done.
-                 */
-                cr = xspi->read_fn(xspi->regs + XSPI_CR_OFFSET);
-                xspi->write_fn(cr | XSPI_CR_TRANS_INHIBIT,
-                        xspi->regs + XSPI_CR_OFFSET);
-
-                /* Read out all the data from the Rx FIFO */
-                sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
-                while ((sr & XSPI_SR_RX_EMPTY_MASK) == 0) {
-                        xspi->rx_fn(xspi);
-                        sr = xspi->read_fn(xspi->regs + XSPI_SR_OFFSET);
-                }
-
-                /* See if there is more data to send */
-                if (xspi->remaining_bytes > 0) {
-                        xilinx_spi_fill_tx_fifo(xspi);
-                        /* Start the transfer by not inhibiting the
-                         * transmitter any longer
-                         */
-                        xspi->write_fn(cr, xspi->regs + XSPI_CR_OFFSET);
-                } else {
-                        /* No more data to send.
-                         * Indicate the transfer is completed.
-                         */
-                        complete(&xspi->done);
-                }
+                complete(&xspi->done);
         }
 
         return IRQ_HANDLED;
diff --git a/drivers/staging/android/alarm-dev.c b/drivers/staging/android/alarm-dev.c
index ceb1c643753d..6dc27dac679d 100644
--- a/drivers/staging/android/alarm-dev.c
+++ b/drivers/staging/android/alarm-dev.c
@@ -264,6 +264,8 @@ static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
         }
 
         rv = alarm_do_ioctl(file, cmd, &ts);
+        if (rv)
+                return rv;
 
         switch (ANDROID_ALARM_BASE_CMD(cmd)) {
         case ANDROID_ALARM_GET_TIME(0):
@@ -272,7 +274,7 @@ static long alarm_ioctl(struct file *file, unsigned int cmd, unsigned long arg)
                 break;
         }
 
-        return rv;
+        return 0;
 }
 #ifdef CONFIG_COMPAT
 static long alarm_compat_ioctl(struct file *file, unsigned int cmd,
@@ -295,6 +297,8 @@ static long alarm_compat_ioctl(struct file *file, unsigned int cmd,
         }
 
         rv = alarm_do_ioctl(file, cmd, &ts);
+        if (rv)
+                return rv;
 
         switch (ANDROID_ALARM_BASE_CMD(cmd)) {
         case ANDROID_ALARM_GET_TIME(0): /* NOTE: we modified cmd above */
@@ -303,7 +307,7 @@ static long alarm_compat_ioctl(struct file *file, unsigned int cmd,
                 break;
         }
 
-        return rv;
+        return 0;
 }
 #endif
 
diff --git a/drivers/staging/dwc2/hcd.c b/drivers/staging/dwc2/hcd.c
index 827ab781ae9b..8551ccedf037 100644
--- a/drivers/staging/dwc2/hcd.c
+++ b/drivers/staging/dwc2/hcd.c
@@ -2804,9 +2804,8 @@ int dwc2_hcd_init(struct dwc2_hsotg *hsotg, int irq,
 
         /* Set device flags indicating whether the HCD supports DMA */
         if (hsotg->core_params->dma_enable > 0) {
-                if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)
-                        dev_warn(hsotg->dev,
-                                 "can't enable workaround for >2GB RAM\n");
+                if (dma_set_mask(hsotg->dev, DMA_BIT_MASK(32)) < 0)
+                        dev_warn(hsotg->dev, "can't set DMA mask\n");
                 if (dma_set_coherent_mask(hsotg->dev, DMA_BIT_MASK(31)) < 0)
                         dev_warn(hsotg->dev,
                                  "can't enable workaround for >2GB RAM\n");
diff --git a/drivers/staging/imx-drm/ipuv3-crtc.c b/drivers/staging/imx-drm/ipuv3-crtc.c
index ea61c869110f..ff5c63350932 100644
--- a/drivers/staging/imx-drm/ipuv3-crtc.c
+++ b/drivers/staging/imx-drm/ipuv3-crtc.c
@@ -316,31 +316,14 @@ static int ipu_crtc_mode_set(struct drm_crtc *crtc,
 
 static void ipu_crtc_handle_pageflip(struct ipu_crtc *ipu_crtc)
 {
-        struct drm_pending_vblank_event *e;
-        struct timeval now;
         unsigned long flags;
         struct drm_device *drm = ipu_crtc->base.dev;
 
         spin_lock_irqsave(&drm->event_lock, flags);
-
-        e = ipu_crtc->page_flip_event;
-        if (!e) {
-                spin_unlock_irqrestore(&drm->event_lock, flags);
-                return;
-        }
-
-        do_gettimeofday(&now);
-        e->event.sequence = 0;
-        e->event.tv_sec = now.tv_sec;
-        e->event.tv_usec = now.tv_usec;
+        if (ipu_crtc->page_flip_event)
+                drm_send_vblank_event(drm, -1, ipu_crtc->page_flip_event);
         ipu_crtc->page_flip_event = NULL;
-
         imx_drm_crtc_vblank_put(ipu_crtc->imx_crtc);
-
-        list_add_tail(&e->base.link, &e->base.file_priv->event_list);
-
-        wake_up_interruptible(&e->base.file_priv->event_wait);
-
         spin_unlock_irqrestore(&drm->event_lock, flags);
 }
 
diff --git a/drivers/staging/zcache/ramster.h b/drivers/staging/zcache/ramster.h
index e1f91d5a0f6a..a858666eae68 100644
--- a/drivers/staging/zcache/ramster.h
+++ b/drivers/staging/zcache/ramster.h
@@ -11,10 +11,6 @@
 #ifndef _ZCACHE_RAMSTER_H_
 #define _ZCACHE_RAMSTER_H_
 
-#ifdef CONFIG_RAMSTER_MODULE
-#define CONFIG_RAMSTER
-#endif
-
 #ifdef CONFIG_RAMSTER
 #include "ramster/ramster.h"
 #else
diff --git a/drivers/staging/zcache/ramster/debug.c b/drivers/staging/zcache/ramster/debug.c
index 327e4f0d98e1..5b26ee977c2f 100644
--- a/drivers/staging/zcache/ramster/debug.c
+++ b/drivers/staging/zcache/ramster/debug.c
@@ -1,6 +1,8 @@
 #include <linux/atomic.h>
 #include "debug.h"
 
+ssize_t ramster_foreign_eph_pages;
+ssize_t ramster_foreign_pers_pages;
 #ifdef CONFIG_DEBUG_FS
 #include <linux/debugfs.h>
 
diff --git a/drivers/staging/zcache/ramster/ramster.c b/drivers/staging/zcache/ramster/ramster.c
index b18b887db79f..a937ce1fa27a 100644
--- a/drivers/staging/zcache/ramster/ramster.c
+++ b/drivers/staging/zcache/ramster/ramster.c
@@ -66,8 +66,6 @@ static int ramster_remote_target_nodenum __read_mostly = -1;
 
 /* Used by this code. */
 long ramster_flnodes;
-ssize_t ramster_foreign_eph_pages;
-ssize_t ramster_foreign_pers_pages;
 /* FIXME frontswap selfshrinking knobs in debugfs? */
 
 static LIST_HEAD(ramster_rem_op_list);
@@ -399,14 +397,18 @@ void ramster_count_foreign_pages(bool eph, int count)
                         inc_ramster_foreign_eph_pages();
                 } else {
                         dec_ramster_foreign_eph_pages();
+#ifdef CONFIG_RAMSTER_DEBUG
                         WARN_ON_ONCE(ramster_foreign_eph_pages < 0);
+#endif
                 }
         } else {
                 if (count > 0) {
                         inc_ramster_foreign_pers_pages();
                 } else {
                         dec_ramster_foreign_pers_pages();
+#ifdef CONFIG_RAMSTER_DEBUG
                         WARN_ON_ONCE(ramster_foreign_pers_pages < 0);
+#endif
                 }
         }
 }
diff --git a/drivers/target/iscsi/iscsi_target.c b/drivers/target/iscsi/iscsi_target.c
index 262ef1f23b38..d7705e5824fb 100644
--- a/drivers/target/iscsi/iscsi_target.c
+++ b/drivers/target/iscsi/iscsi_target.c
@@ -651,7 +651,7 @@ static int iscsit_add_reject(
         cmd->buf_ptr = kmemdup(buf, ISCSI_HDR_LEN, GFP_KERNEL);
         if (!cmd->buf_ptr) {
                 pr_err("Unable to allocate memory for cmd->buf_ptr\n");
-                iscsit_release_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
                 return -1;
         }
 
@@ -697,7 +697,7 @@ int iscsit_add_reject_from_cmd(
         cmd->buf_ptr = kmemdup(buf, ISCSI_HDR_LEN, GFP_KERNEL);
         if (!cmd->buf_ptr) {
                 pr_err("Unable to allocate memory for cmd->buf_ptr\n");
-                iscsit_release_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
                 return -1;
         }
 
@@ -1743,7 +1743,7 @@ int iscsit_handle_nop_out(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
         return 0;
 out:
         if (cmd)
-                iscsit_release_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
 ping_out:
         kfree(ping_data);
         return ret;
@@ -2251,7 +2251,7 @@ iscsit_handle_logout_cmd(struct iscsi_conn *conn, struct iscsi_cmd *cmd,
         if (conn->conn_state != TARG_CONN_STATE_LOGGED_IN) {
                 pr_err("Received logout request on connection that"
                         " is not in logged in state, ignoring request.\n");
-                iscsit_release_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
                 return 0;
         }
 
@@ -3665,7 +3665,7 @@ iscsit_immediate_queue(struct iscsi_conn *conn, struct iscsi_cmd *cmd, int state
                 list_del(&cmd->i_conn_node);
                 spin_unlock_bh(&conn->cmd_lock);
 
-                iscsit_free_cmd(cmd);
+                iscsit_free_cmd(cmd, false);
                 break;
         case ISTATE_SEND_NOPIN_WANT_RESPONSE:
                 iscsit_mod_nopin_response_timer(conn);
@@ -4122,7 +4122,7 @@ static void iscsit_release_commands_from_conn(struct iscsi_conn *conn)
 
                 iscsit_increment_maxcmdsn(cmd, sess);
 
-                iscsit_free_cmd(cmd);
+                iscsit_free_cmd(cmd, true);
 
                 spin_lock_bh(&conn->cmd_lock);
         }
diff --git a/drivers/target/iscsi/iscsi_target_erl2.c b/drivers/target/iscsi/iscsi_target_erl2.c
index ba6091bf93fc..45a5afd5ea13 100644
--- a/drivers/target/iscsi/iscsi_target_erl2.c
+++ b/drivers/target/iscsi/iscsi_target_erl2.c
@@ -143,7 +143,7 @@ void iscsit_free_connection_recovery_entires(struct iscsi_session *sess)
                         list_del(&cmd->i_conn_node);
                         cmd->conn = NULL;
                         spin_unlock(&cr->conn_recovery_cmd_lock);
-                        iscsit_free_cmd(cmd);
+                        iscsit_free_cmd(cmd, true);
                         spin_lock(&cr->conn_recovery_cmd_lock);
                 }
                 spin_unlock(&cr->conn_recovery_cmd_lock);
@@ -165,7 +165,7 @@ void iscsit_free_connection_recovery_entires(struct iscsi_session *sess)
                         list_del(&cmd->i_conn_node);
                         cmd->conn = NULL;
                         spin_unlock(&cr->conn_recovery_cmd_lock);
-                        iscsit_free_cmd(cmd);
+                        iscsit_free_cmd(cmd, true);
                         spin_lock(&cr->conn_recovery_cmd_lock);
                 }
                 spin_unlock(&cr->conn_recovery_cmd_lock);
@@ -248,7 +248,7 @@ void iscsit_discard_cr_cmds_by_expstatsn(
                 iscsit_remove_cmd_from_connection_recovery(cmd, sess);
 
                 spin_unlock(&cr->conn_recovery_cmd_lock);
-                iscsit_free_cmd(cmd);
+                iscsit_free_cmd(cmd, true);
                 spin_lock(&cr->conn_recovery_cmd_lock);
         }
         spin_unlock(&cr->conn_recovery_cmd_lock);
@@ -302,7 +302,7 @@ int iscsit_discard_unacknowledged_ooo_cmdsns_for_conn(struct iscsi_conn *conn)
                 list_del(&cmd->i_conn_node);
 
                 spin_unlock_bh(&conn->cmd_lock);
-                iscsit_free_cmd(cmd);
+                iscsit_free_cmd(cmd, true);
                 spin_lock_bh(&conn->cmd_lock);
         }
         spin_unlock_bh(&conn->cmd_lock);
@@ -355,7 +355,7 @@ int iscsit_prepare_cmds_for_realligance(struct iscsi_conn *conn)
 
                         list_del(&cmd->i_conn_node);
                         spin_unlock_bh(&conn->cmd_lock);
-                        iscsit_free_cmd(cmd);
+                        iscsit_free_cmd(cmd, true);
                         spin_lock_bh(&conn->cmd_lock);
                         continue;
                 }
@@ -375,7 +375,7 @@ int iscsit_prepare_cmds_for_realligance(struct iscsi_conn *conn)
                      iscsi_sna_gte(cmd->cmd_sn, conn->sess->exp_cmd_sn)) {
                         list_del(&cmd->i_conn_node);
                         spin_unlock_bh(&conn->cmd_lock);
-                        iscsit_free_cmd(cmd);
+                        iscsit_free_cmd(cmd, true);
                         spin_lock_bh(&conn->cmd_lock);
                         continue;
                 }
diff --git a/drivers/target/iscsi/iscsi_target_parameters.c b/drivers/target/iscsi/iscsi_target_parameters.c
index c2185fc31136..e38222191a33 100644
--- a/drivers/target/iscsi/iscsi_target_parameters.c
+++ b/drivers/target/iscsi/iscsi_target_parameters.c
@@ -758,9 +758,9 @@ static int iscsi_add_notunderstood_response(
         }
         INIT_LIST_HEAD(&extra_response->er_list);
 
-        strncpy(extra_response->key, key, strlen(key) + 1);
-        strncpy(extra_response->value, NOTUNDERSTOOD,
-                        strlen(NOTUNDERSTOOD) + 1);
+        strlcpy(extra_response->key, key, sizeof(extra_response->key));
+        strlcpy(extra_response->value, NOTUNDERSTOOD,
+                sizeof(extra_response->value));
 
         list_add_tail(&extra_response->er_list,
                         &param_list->extra_response_list);
@@ -1629,8 +1629,6 @@ int iscsi_decode_text_input(
 
                 if (phase & PHASE_SECURITY) {
                         if (iscsi_check_for_auth_key(key) > 0) {
-                                char *tmpptr = key + strlen(key);
-                                *tmpptr = '=';
                                 kfree(tmpbuf);
                                 return 1;
                         }
diff --git a/drivers/target/iscsi/iscsi_target_parameters.h b/drivers/target/iscsi/iscsi_target_parameters.h
index 915b06798505..a47046a752aa 100644
--- a/drivers/target/iscsi/iscsi_target_parameters.h
+++ b/drivers/target/iscsi/iscsi_target_parameters.h
@@ -1,8 +1,10 @@
 #ifndef ISCSI_PARAMETERS_H
 #define ISCSI_PARAMETERS_H
 
+#include <scsi/iscsi_proto.h>
+
 struct iscsi_extra_response {
-        char key[64];
+        char key[KEY_MAXLEN];
         char value[32];
         struct list_head er_list;
 } ____cacheline_aligned;
diff --git a/drivers/target/iscsi/iscsi_target_util.c b/drivers/target/iscsi/iscsi_target_util.c
index 2cc6c9a3ffb8..08a3bacef0c5 100644
--- a/drivers/target/iscsi/iscsi_target_util.c
+++ b/drivers/target/iscsi/iscsi_target_util.c
@@ -676,40 +676,56 @@ void iscsit_free_queue_reqs_for_conn(struct iscsi_conn *conn)
 
 void iscsit_release_cmd(struct iscsi_cmd *cmd)
 {
-        struct iscsi_conn *conn = cmd->conn;
-
-        iscsit_free_r2ts_from_list(cmd);
-        iscsit_free_all_datain_reqs(cmd);
-
         kfree(cmd->buf_ptr);
         kfree(cmd->pdu_list);
         kfree(cmd->seq_list);
         kfree(cmd->tmr_req);
         kfree(cmd->iov_data);
 
-        if (conn) {
+        kmem_cache_free(lio_cmd_cache, cmd);
+}
+
+static void __iscsit_free_cmd(struct iscsi_cmd *cmd, bool scsi_cmd,
+                              bool check_queues)
+{
+        struct iscsi_conn *conn = cmd->conn;
+
+        if (scsi_cmd) {
+                if (cmd->data_direction == DMA_TO_DEVICE) {
+                        iscsit_stop_dataout_timer(cmd);
+                        iscsit_free_r2ts_from_list(cmd);
+                }
+                if (cmd->data_direction == DMA_FROM_DEVICE)
+                        iscsit_free_all_datain_reqs(cmd);
+        }
+
+        if (conn && check_queues) {
                 iscsit_remove_cmd_from_immediate_queue(cmd, conn);
                 iscsit_remove_cmd_from_response_queue(cmd, conn);
         }
-
-        kmem_cache_free(lio_cmd_cache, cmd);
 }
 
-void iscsit_free_cmd(struct iscsi_cmd *cmd)
+void iscsit_free_cmd(struct iscsi_cmd *cmd, bool shutdown)
 {
+        struct se_cmd *se_cmd = NULL;
+        int rc;
         /*
          * Determine if a struct se_cmd is associated with
          * this struct iscsi_cmd.
          */
         switch (cmd->iscsi_opcode) {
         case ISCSI_OP_SCSI_CMD:
-                if (cmd->data_direction == DMA_TO_DEVICE)
-                        iscsit_stop_dataout_timer(cmd);
+                se_cmd = &cmd->se_cmd;
+                __iscsit_free_cmd(cmd, true, shutdown);
                 /*
                  * Fallthrough
                  */
         case ISCSI_OP_SCSI_TMFUNC:
-                transport_generic_free_cmd(&cmd->se_cmd, 1);
+                rc = transport_generic_free_cmd(&cmd->se_cmd, 1);
+                if (!rc && shutdown && se_cmd && se_cmd->se_sess) {
+                        __iscsit_free_cmd(cmd, true, shutdown);
+                        target_put_sess_cmd(se_cmd->se_sess, se_cmd);
+                }
                 break;
         case ISCSI_OP_REJECT:
                 /*
@@ -718,11 +734,19 @@ void iscsit_free_cmd(struct iscsi_cmd *cmd)
                  * associated cmd->se_cmd needs to be released.
                  */
                 if (cmd->se_cmd.se_tfo != NULL) {
-                        transport_generic_free_cmd(&cmd->se_cmd, 1);
+                        se_cmd = &cmd->se_cmd;
+                        __iscsit_free_cmd(cmd, true, shutdown);
+
+                        rc = transport_generic_free_cmd(&cmd->se_cmd, 1);
+                        if (!rc && shutdown && se_cmd->se_sess) {
+                                __iscsit_free_cmd(cmd, true, shutdown);
+                                target_put_sess_cmd(se_cmd->se_sess, se_cmd);
+                        }
                         break;
                 }
                 /* Fall-through */
         default:
+                __iscsit_free_cmd(cmd, false, shutdown);
                 cmd->release_cmd(cmd);
                 break;
         }
diff --git a/drivers/target/iscsi/iscsi_target_util.h b/drivers/target/iscsi/iscsi_target_util.h
index 4f8e01a47081..a4422659d049 100644
--- a/drivers/target/iscsi/iscsi_target_util.h
+++ b/drivers/target/iscsi/iscsi_target_util.h
@@ -29,7 +29,7 @@ extern void iscsit_remove_cmd_from_tx_queues(struct iscsi_cmd *, struct iscsi_co
 extern bool iscsit_conn_all_queues_empty(struct iscsi_conn *);
 extern void iscsit_free_queue_reqs_for_conn(struct iscsi_conn *);
 extern void iscsit_release_cmd(struct iscsi_cmd *);
-extern void iscsit_free_cmd(struct iscsi_cmd *);
+extern void iscsit_free_cmd(struct iscsi_cmd *, bool);
 extern int iscsit_check_session_usage_count(struct iscsi_session *);
 extern void iscsit_dec_session_usage_count(struct iscsi_session *);
 extern void iscsit_inc_session_usage_count(struct iscsi_session *);
diff --git a/drivers/target/target_core_file.c b/drivers/target/target_core_file.c
index 1b1d544e927a..b11890d85120 100644
--- a/drivers/target/target_core_file.c
+++ b/drivers/target/target_core_file.c
@@ -153,6 +153,7 @@ static int fd_configure_device(struct se_device *dev)
                 struct request_queue *q = bdev_get_queue(inode->i_bdev);
                 unsigned long long dev_size;
 
+                fd_dev->fd_block_size = bdev_logical_block_size(inode->i_bdev);
                 /*
                  * Determine the number of bytes from i_size_read() minus
                  * one (1) logical sector from underlying struct block_device
@@ -199,6 +200,7 @@ static int fd_configure_device(struct se_device *dev)
                         goto fail;
                 }
 
+                fd_dev->fd_block_size = FD_BLOCKSIZE;
                 /*
                  * Limit UNMAP emulation to 8k Number of LBAs (NoLB)
                  */
@@ -217,9 +219,7 @@ static int fd_configure_device(struct se_device *dev)
                 dev->dev_attrib.max_write_same_len = 0x1000;
         }
 
-        fd_dev->fd_block_size = dev->dev_attrib.hw_block_size;
-
-        dev->dev_attrib.hw_block_size = FD_BLOCKSIZE;
+        dev->dev_attrib.hw_block_size = fd_dev->fd_block_size;
         dev->dev_attrib.hw_max_sectors = FD_MAX_SECTORS;
         dev->dev_attrib.hw_queue_depth = FD_MAX_DEVICE_QUEUE_DEPTH;
 
@@ -694,11 +694,12 @@ static sector_t fd_get_blocks(struct se_device *dev)
          * to handle underlying block_device resize operations.
          */
         if (S_ISBLK(i->i_mode))
-                dev_size = (i_size_read(i) - fd_dev->fd_block_size);
+                dev_size = i_size_read(i);
         else
                 dev_size = fd_dev->fd_dev_size;
 
-        return div_u64(dev_size, dev->dev_attrib.block_size);
+        return div_u64(dev_size - dev->dev_attrib.block_size,
+                       dev->dev_attrib.block_size);
 }
 
 static struct sbc_ops fd_sbc_ops = {
diff --git a/drivers/target/target_core_transport.c b/drivers/target/target_core_transport.c
index 4a793362309d..21e315874a54 100644
--- a/drivers/target/target_core_transport.c
+++ b/drivers/target/target_core_transport.c
@@ -65,7 +65,7 @@ static void transport_complete_task_attr(struct se_cmd *cmd);
 static void transport_handle_queue_full(struct se_cmd *cmd,
                 struct se_device *dev);
 static int transport_generic_get_mem(struct se_cmd *cmd);
-static void transport_put_cmd(struct se_cmd *cmd);
+static int transport_put_cmd(struct se_cmd *cmd);
 static void target_complete_ok_work(struct work_struct *work);
 
 int init_se_kmem_caches(void)
@@ -221,6 +221,7 @@ struct se_session *transport_init_session(void)
         INIT_LIST_HEAD(&se_sess->sess_list);
         INIT_LIST_HEAD(&se_sess->sess_acl_list);
         INIT_LIST_HEAD(&se_sess->sess_cmd_list);
+        INIT_LIST_HEAD(&se_sess->sess_wait_list);
         spin_lock_init(&se_sess->sess_cmd_lock);
         kref_init(&se_sess->sess_kref);
 
@@ -1943,7 +1944,7 @@ static inline void transport_free_pages(struct se_cmd *cmd)
  * This routine unconditionally frees a command, and reference counting
  * or list removal must be done in the caller.
  */
-static void transport_release_cmd(struct se_cmd *cmd)
+static int transport_release_cmd(struct se_cmd *cmd)
 {
         BUG_ON(!cmd->se_tfo);
 
@@ -1955,11 +1956,11 @@ static void transport_release_cmd(struct se_cmd *cmd)
          * If this cmd has been setup with target_get_sess_cmd(), drop
          * the kref and call ->release_cmd() in kref callback.
          */
-         if (cmd->check_release != 0) {
-                target_put_sess_cmd(cmd->se_sess, cmd);
-                return;
-        }
+         if (cmd->check_release != 0)
+                return target_put_sess_cmd(cmd->se_sess, cmd);
+
         cmd->se_tfo->release_cmd(cmd);
+        return 1;
 }
 
 /**
@@ -1968,7 +1969,7 @@ static void transport_release_cmd(struct se_cmd *cmd)
  *
  * This routine releases our reference to the command and frees it if possible.
  */
-static void transport_put_cmd(struct se_cmd *cmd)
+static int transport_put_cmd(struct se_cmd *cmd)
 {
         unsigned long flags;
 
@@ -1976,7 +1977,7 @@ static void transport_put_cmd(struct se_cmd *cmd)
         if (atomic_read(&cmd->t_fe_count) &&
             !atomic_dec_and_test(&cmd->t_fe_count)) {
                 spin_unlock_irqrestore(&cmd->t_state_lock, flags);
-                return;
+                return 0;
         }
 
         if (cmd->transport_state & CMD_T_DEV_ACTIVE) {
@@ -1986,8 +1987,7 @@ static void transport_put_cmd(struct se_cmd *cmd)
         spin_unlock_irqrestore(&cmd->t_state_lock, flags);
 
         transport_free_pages(cmd);
-        transport_release_cmd(cmd);
-        return;
+        return transport_release_cmd(cmd);
 }
 
 void *transport_kmap_data_sg(struct se_cmd *cmd)
@@ -2152,13 +2152,15 @@ static void transport_write_pending_qf(struct se_cmd *cmd)
         }
 }
 
-void transport_generic_free_cmd(struct se_cmd *cmd, int wait_for_tasks)
+int transport_generic_free_cmd(struct se_cmd *cmd, int wait_for_tasks)
 {
+        int ret = 0;
+
         if (!(cmd->se_cmd_flags & SCF_SE_LUN_CMD)) {
                 if (wait_for_tasks && (cmd->se_cmd_flags & SCF_SCSI_TMR_CDB))
                          transport_wait_for_tasks(cmd);
 
-                transport_release_cmd(cmd);
+                ret = transport_release_cmd(cmd);
         } else {
                 if (wait_for_tasks)
                         transport_wait_for_tasks(cmd);
@@ -2166,8 +2168,9 @@ void transport_generic_free_cmd(struct se_cmd *cmd, int wait_for_tasks)
                 if (cmd->se_lun)
                         transport_lun_remove_cmd(cmd);
 
-                transport_put_cmd(cmd);
+                ret = transport_put_cmd(cmd);
         }
+        return ret;
 }
 EXPORT_SYMBOL(transport_generic_free_cmd);
 
@@ -2250,11 +2253,14 @@ void target_sess_cmd_list_set_waiting(struct se_session *se_sess)
         unsigned long flags;
 
         spin_lock_irqsave(&se_sess->sess_cmd_lock, flags);
-
-        WARN_ON(se_sess->sess_tearing_down);
+        if (se_sess->sess_tearing_down) {
+                spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags);
+                return;
+        }
         se_sess->sess_tearing_down = 1;
+        list_splice_init(&se_sess->sess_cmd_list, &se_sess->sess_wait_list);
 
-        list_for_each_entry(se_cmd, &se_sess->sess_cmd_list, se_cmd_list)
+        list_for_each_entry(se_cmd, &se_sess->sess_wait_list, se_cmd_list)
                 se_cmd->cmd_wait_set = 1;
 
         spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags);
@@ -2263,44 +2269,32 @@ EXPORT_SYMBOL(target_sess_cmd_list_set_waiting);
 
 /* target_wait_for_sess_cmds - Wait for outstanding descriptors
  * @se_sess:    session to wait for active I/O
- * @wait_for_tasks:     Make extra transport_wait_for_tasks call
  */
-void target_wait_for_sess_cmds(
-        struct se_session *se_sess,
-        int wait_for_tasks)
+void target_wait_for_sess_cmds(struct se_session *se_sess)
 {
         struct se_cmd *se_cmd, *tmp_cmd;
-        bool rc = false;
+        unsigned long flags;
 
         list_for_each_entry_safe(se_cmd, tmp_cmd,
-                                &se_sess->sess_cmd_list, se_cmd_list) {
+                                &se_sess->sess_wait_list, se_cmd_list) {
                 list_del(&se_cmd->se_cmd_list);
 
                 pr_debug("Waiting for se_cmd: %p t_state: %d, fabric state:"
                         " %d\n", se_cmd, se_cmd->t_state,
                         se_cmd->se_tfo->get_cmd_state(se_cmd));
 
-                if (wait_for_tasks) {
-                        pr_debug("Calling transport_wait_for_tasks se_cmd: %p t_state: %d,"
-                                " fabric state: %d\n", se_cmd, se_cmd->t_state,
-                                se_cmd->se_tfo->get_cmd_state(se_cmd));
-
-                        rc = transport_wait_for_tasks(se_cmd);
-
-                        pr_debug("After transport_wait_for_tasks se_cmd: %p t_state: %d,"
-                                " fabric state: %d\n", se_cmd, se_cmd->t_state,
-                                se_cmd->se_tfo->get_cmd_state(se_cmd));
-                }
-
-                if (!rc) {
-                        wait_for_completion(&se_cmd->cmd_wait_comp);
-                        pr_debug("After cmd_wait_comp: se_cmd: %p t_state: %d"
-                                " fabric state: %d\n", se_cmd, se_cmd->t_state,
-                                se_cmd->se_tfo->get_cmd_state(se_cmd));
-                }
+                wait_for_completion(&se_cmd->cmd_wait_comp);
+                pr_debug("After cmd_wait_comp: se_cmd: %p t_state: %d"
+                        " fabric state: %d\n", se_cmd, se_cmd->t_state,
+                        se_cmd->se_tfo->get_cmd_state(se_cmd));
 
                 se_cmd->se_tfo->release_cmd(se_cmd);
         }
+
+        spin_lock_irqsave(&se_sess->sess_cmd_lock, flags);
+        WARN_ON(!list_empty(&se_sess->sess_cmd_list));
+        spin_unlock_irqrestore(&se_sess->sess_cmd_lock, flags);
+
 }
 EXPORT_SYMBOL(target_wait_for_sess_cmds);
 
diff --git a/drivers/thermal/exynos_thermal.c b/drivers/thermal/exynos_thermal.c
index 788b1ddcac6c..4cbe3eea6deb 100644
--- a/drivers/thermal/exynos_thermal.c
+++ b/drivers/thermal/exynos_thermal.c
@@ -817,7 +817,8 @@ static struct exynos_tmu_platform_data const exynos4210_default_tmu_data = {
 #define EXYNOS4210_TMU_DRV_DATA (NULL)
 #endif
 
-#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412)
+#if defined(CONFIG_SOC_EXYNOS5250) || defined(CONFIG_SOC_EXYNOS4412) || \
+        defined(CONFIG_SOC_EXYNOS4212)
 static struct exynos_tmu_platform_data const exynos_default_tmu_data = {
         .threshold_falling = 10,
         .trigger_levels[0] = 85,
diff --git a/drivers/tty/serial/8250/8250_core.c b/drivers/tty/serial/8250/8250_core.c
index 46528d57be72..86c00b1c5583 100644
--- a/drivers/tty/serial/8250/8250_core.c
+++ b/drivers/tty/serial/8250/8250_core.c
@@ -2755,7 +2755,7 @@ static void __init serial8250_isa_init_ports(void)
         if (nr_uarts > UART_NR)
                 nr_uarts = UART_NR;
 
-        for (i = 0; i < UART_NR; i++) {
+        for (i = 0; i < nr_uarts; i++) {
                 struct uart_8250_port *up = &serial8250_ports[i];
                 struct uart_port *port = &up->port;
 
@@ -2916,7 +2916,7 @@ static int __init serial8250_console_setup(struct console *co, char *options)
          * if so, search for the first available port that does have
          * console support.
          */
-        if (co->index >= UART_NR)
+        if (co->index >= nr_uarts)
                 co->index = 0;
         port = &serial8250_ports[co->index].port;
         if (!port->iobase && !port->membase)
@@ -2957,7 +2957,7 @@ int serial8250_find_port(struct uart_port *p)
         int line;
         struct uart_port *port;
 
-        for (line = 0; line < UART_NR; line++) {
+        for (line = 0; line < nr_uarts; line++) {
                 port = &serial8250_ports[line].port;
                 if (uart_match_port(p, port))
                         return line;
@@ -3110,7 +3110,7 @@ static int serial8250_remove(struct platform_device *dev)
 {
         int i;
 
-        for (i = 0; i < UART_NR; i++) {
+        for (i = 0; i < nr_uarts; i++) {
                 struct uart_8250_port *up = &serial8250_ports[i];
 
                 if (up->port.dev == &dev->dev)
@@ -3178,7 +3178,7 @@ static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *
         /*
          * First, find a port entry which matches.
          */
-        for (i = 0; i < UART_NR; i++)
+        for (i = 0; i < nr_uarts; i++)
                 if (uart_match_port(&serial8250_ports[i].port, port))
                         return &serial8250_ports[i];
 
@@ -3187,7 +3187,7 @@ static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *
          * free entry.  We look for one which hasn't been previously
          * used (indicated by zero iobase).
          */
-        for (i = 0; i < UART_NR; i++)
+        for (i = 0; i < nr_uarts; i++)
                 if (serial8250_ports[i].port.type == PORT_UNKNOWN &&
                     serial8250_ports[i].port.iobase == 0)
                         return &serial8250_ports[i];
@@ -3196,7 +3196,7 @@ static struct uart_8250_port *serial8250_find_match_or_unused(struct uart_port *
          * That also failed.  Last resort is to find any entry which
          * doesn't have a real port associated with it.
          */
-        for (i = 0; i < UART_NR; i++)
+        for (i = 0; i < nr_uarts; i++)
                 if (serial8250_ports[i].port.type == PORT_UNKNOWN)
                         return &serial8250_ports[i];
 
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c
index 147c9e193595..8cdfbd365892 100644
--- a/drivers/tty/serial/imx.c
+++ b/drivers/tty/serial/imx.c
@@ -761,6 +761,8 @@ static int imx_startup(struct uart_port *port)
 
         temp = readl(sport->port.membase + UCR2);
         temp |= (UCR2_RXEN | UCR2_TXEN);
+        if (!sport->have_rtscts)
+                temp |= UCR2_IRTS;
         writel(temp, sport->port.membase + UCR2);
 
         if (USE_IRDA(sport)) {
diff --git a/drivers/tty/serial/samsung.c b/drivers/tty/serial/samsung.c
index 89429410a245..0c8a9fa2be6c 100644
--- a/drivers/tty/serial/samsung.c
+++ b/drivers/tty/serial/samsung.c
@@ -1166,6 +1166,18 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
                 ourport->tx_irq = ret;
 
         ourport->clk    = clk_get(&platdev->dev, "uart");
+        if (IS_ERR(ourport->clk)) {
+                pr_err("%s: Controller clock not found\n",
+                                dev_name(&platdev->dev));
+                return PTR_ERR(ourport->clk);
+        }
+
+        ret = clk_prepare_enable(ourport->clk);
+        if (ret) {
+                pr_err("uart: clock failed to prepare+enable: %d\n", ret);
+                clk_put(ourport->clk);
+                return ret;
+        }
 
         /* Keep all interrupts masked and cleared */
         if (s3c24xx_serial_has_interrupt_mask(port)) {
@@ -1180,6 +1192,7 @@ static int s3c24xx_serial_init_port(struct s3c24xx_uart_port *ourport,
 
         /* reset the fifos (and setup the uart) */
         s3c24xx_serial_resetport(port, cfg);
+        clk_disable_unprepare(ourport->clk);
         return 0;
 }
 
diff --git a/drivers/tty/serial/xilinx_uartps.c b/drivers/tty/serial/xilinx_uartps.c
index 4e5c77834c50..a4a3028103e3 100644
--- a/drivers/tty/serial/xilinx_uartps.c
+++ b/drivers/tty/serial/xilinx_uartps.c
@@ -14,6 +14,7 @@
 #include <linux/platform_device.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/slab.h>
 #include <linux/tty.h>
 #include <linux/tty_flip.h>
 #include <linux/console.h>
@@ -139,6 +140,16 @@
 #define XUARTPS_SR_RXTRIG       0x00000001 /* Rx Trigger */
 
 /**
+ * struct xuartps - device data
+ * @refclk      Reference clock
+ * @aperclk     APB clock
+ */
+struct xuartps {
+        struct clk              *refclk;
+        struct clk              *aperclk;
+};
+
+/**
  * xuartps_isr - Interrupt handler
  * @irq: Irq number
  * @dev_id: Id of the port
@@ -936,34 +947,55 @@ static int xuartps_probe(struct platform_device *pdev)
         int rc;
         struct uart_port *port;
         struct resource *res, *res2;
-        struct clk *clk;
+        struct xuartps *xuartps_data;
 
-        clk = of_clk_get(pdev->dev.of_node, 0);
-        if (IS_ERR(clk)) {
-                dev_err(&pdev->dev, "no clock specified\n");
-                return PTR_ERR(clk);
+        xuartps_data = kzalloc(sizeof(*xuartps_data), GFP_KERNEL);
+        if (!xuartps_data)
+                return -ENOMEM;
+
+        xuartps_data->aperclk = clk_get(&pdev->dev, "aper_clk");
+        if (IS_ERR(xuartps_data->aperclk)) {
+                dev_err(&pdev->dev, "aper_clk clock not found.\n");
+                rc = PTR_ERR(xuartps_data->aperclk);
+                goto err_out_free;
+        }
+        xuartps_data->refclk = clk_get(&pdev->dev, "ref_clk");
+        if (IS_ERR(xuartps_data->refclk)) {
+                dev_err(&pdev->dev, "ref_clk clock not found.\n");
+                rc = PTR_ERR(xuartps_data->refclk);
+                goto err_out_clk_put_aper;
         }
 
-        rc = clk_prepare_enable(clk);
+        rc = clk_prepare_enable(xuartps_data->aperclk);
+        if (rc) {
+                dev_err(&pdev->dev, "Unable to enable APER clock.\n");
+                goto err_out_clk_put;
+        }
+        rc = clk_prepare_enable(xuartps_data->refclk);
         if (rc) {
-                dev_err(&pdev->dev, "could not enable clock\n");
-                return -EBUSY;
+                dev_err(&pdev->dev, "Unable to enable device clock.\n");
+                goto err_out_clk_dis_aper;
         }
 
         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        if (!res)
-                return -ENODEV;
+        if (!res) {
+                rc = -ENODEV;
+                goto err_out_clk_disable;
+        }
 
         res2 = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
-        if (!res2)
-                return -ENODEV;
+        if (!res2) {
+                rc = -ENODEV;
+                goto err_out_clk_disable;
+        }
 
         /* Initialize the port structure */
         port = xuartps_get_port();
 
         if (!port) {
                 dev_err(&pdev->dev, "Cannot get uart_port structure\n");
-                return -ENODEV;
+                rc = -ENODEV;
+                goto err_out_clk_disable;
         } else {
                 /* Register the port.
                  * This function also registers this device with the tty layer
@@ -972,18 +1004,31 @@ static int xuartps_probe(struct platform_device *pdev)
                 port->mapbase = res->start;
                 port->irq = res2->start;
                 port->dev = &pdev->dev;
-                port->uartclk = clk_get_rate(clk);
-                port->private_data = clk;
+                port->uartclk = clk_get_rate(xuartps_data->refclk);
+                port->private_data = xuartps_data;
                 dev_set_drvdata(&pdev->dev, port);
                 rc = uart_add_one_port(&xuartps_uart_driver, port);
                 if (rc) {
                         dev_err(&pdev->dev,
                                 "uart_add_one_port() failed; err=%i\n", rc);
                         dev_set_drvdata(&pdev->dev, NULL);
-                        return rc;
+                        goto err_out_clk_disable;
                 }
                 return 0;
         }
+
+err_out_clk_disable:
+        clk_disable_unprepare(xuartps_data->refclk);
+err_out_clk_dis_aper:
+        clk_disable_unprepare(xuartps_data->aperclk);
+err_out_clk_put:
+        clk_put(xuartps_data->refclk);
+err_out_clk_put_aper:
+        clk_put(xuartps_data->aperclk);
+err_out_free:
+        kfree(xuartps_data);
+
+        return rc;
 }
 
 /**
@@ -995,14 +1040,18 @@ static int xuartps_probe(struct platform_device *pdev)
 static int xuartps_remove(struct platform_device *pdev)
 {
         struct uart_port *port = dev_get_drvdata(&pdev->dev);
-        struct clk *clk = port->private_data;
+        struct xuartps *xuartps_data = port->private_data;
         int rc;
 
         /* Remove the xuartps port from the serial core */
         rc = uart_remove_one_port(&xuartps_uart_driver, port);
         dev_set_drvdata(&pdev->dev, NULL);
         port->mapbase = 0;
-        clk_disable_unprepare(clk);
+        clk_disable_unprepare(xuartps_data->refclk);
+        clk_disable_unprepare(xuartps_data->aperclk);
+        clk_put(xuartps_data->refclk);
+        clk_put(xuartps_data->aperclk);
+        kfree(xuartps_data);
         return rc;
 }
 
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 92e1dc94ecc8..a3b48b5ea8d3 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -43,6 +43,7 @@ config USB_ARCH_HAS_EHCI
         default y if ARCH_VT8500
         default y if PLAT_SPEAR
         default y if PLAT_S5P
+        default y if ARCH_EXYNOS
         default y if ARCH_MSM
         default y if MICROBLAZE
         default y if SPARC_LEON
diff --git a/drivers/usb/chipidea/core.c b/drivers/usb/chipidea/core.c
index 49b098bedf9b..475c9c114689 100644
--- a/drivers/usb/chipidea/core.c
+++ b/drivers/usb/chipidea/core.c
@@ -276,8 +276,9 @@ static void ci_role_work(struct work_struct *work)
 
                 ci_role_stop(ci);
                 ci_role_start(ci, role);
-                enable_irq(ci->irq);
         }
+
+        enable_irq(ci->irq);
 }
 
 static irqreturn_t ci_irq(int irq, void *data)
diff --git a/drivers/usb/chipidea/udc.c b/drivers/usb/chipidea/udc.c
index 519ead2443c5..b501346484ae 100644
--- a/drivers/usb/chipidea/udc.c
+++ b/drivers/usb/chipidea/udc.c
@@ -1678,8 +1678,11 @@ static int udc_start(struct ci13xxx *ci)
 
         ci->gadget.ep0 = &ci->ep0in->ep;
 
-        if (ci->global_phy)
+        if (ci->global_phy) {
                 ci->transceiver = usb_get_phy(USB_PHY_TYPE_USB2);
+                if (IS_ERR(ci->transceiver))
+                        ci->transceiver = NULL;
+        }
 
         if (ci->platdata->flags & CI13XXX_REQUIRE_TRANSCEIVER) {
                 if (ci->transceiver == NULL) {
@@ -1694,7 +1697,7 @@ static int udc_start(struct ci13xxx *ci)
                         goto put_transceiver;
         }
 
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 retval = otg_set_peripheral(ci->transceiver->otg,
                                                 &ci->gadget);
                 if (retval)
@@ -1711,7 +1714,7 @@ static int udc_start(struct ci13xxx *ci)
         return retval;
 
 remove_trans:
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 otg_set_peripheral(ci->transceiver->otg, NULL);
                 if (ci->global_phy)
                         usb_put_phy(ci->transceiver);
@@ -1719,7 +1722,7 @@ remove_trans:
 
         dev_err(dev, "error = %i\n", retval);
 put_transceiver:
-        if (!IS_ERR_OR_NULL(ci->transceiver) && ci->global_phy)
+        if (ci->transceiver && ci->global_phy)
                 usb_put_phy(ci->transceiver);
 destroy_eps:
         destroy_eps(ci);
@@ -1747,7 +1750,7 @@ static void udc_stop(struct ci13xxx *ci)
         dma_pool_destroy(ci->td_pool);
         dma_pool_destroy(ci->qh_pool);
 
-        if (!IS_ERR_OR_NULL(ci->transceiver)) {
+        if (ci->transceiver) {
                 otg_set_peripheral(ci->transceiver->otg, NULL);
                 if (ci->global_phy)
                         usb_put_phy(ci->transceiver);
diff --git a/drivers/usb/core/devio.c b/drivers/usb/core/devio.c
index caefc800f298..c88c4fb9459d 100644
--- a/drivers/usb/core/devio.c
+++ b/drivers/usb/core/devio.c
@@ -1287,9 +1287,13 @@ static int proc_do_submiturb(struct dev_state *ps, struct usbdevfs_urb *uurb,
                         goto error;
                 }
                 for (totlen = u = 0; u < uurb->number_of_packets; u++) {
-                        /* arbitrary limit,
-                         * sufficient for USB 2.0 high-bandwidth iso */
-                        if (isopkt[u].length > 8192) {
+                        /*
+                         * arbitrary limit need for USB 3.0
+                         * bMaxBurst (0~15 allowed, 1~16 packets)
+                         * bmAttributes (bit 1:0, mult 0~2, 1~3 packets)
+                         * sizemax: 1024 * 16 * 3 = 49152
+                         */
+                        if (isopkt[u].length > 49152) {
                                 ret = -EINVAL;
                                 goto error;
                         }
diff --git a/drivers/usb/dwc3/dwc3-exynos.c b/drivers/usb/dwc3/dwc3-exynos.c
index 929e7dd6e58b..8ce9d7fd6cfc 100644
--- a/drivers/usb/dwc3/dwc3-exynos.c
+++ b/drivers/usb/dwc3/dwc3-exynos.c
@@ -164,9 +164,9 @@ static int dwc3_exynos_remove(struct platform_device *pdev)
 {
         struct dwc3_exynos      *exynos = platform_get_drvdata(pdev);
 
+        device_for_each_child(&pdev->dev, NULL, dwc3_exynos_remove_child);
         platform_device_unregister(exynos->usb2_phy);
         platform_device_unregister(exynos->usb3_phy);
-        device_for_each_child(&pdev->dev, NULL, dwc3_exynos_remove_child);
 
         clk_disable_unprepare(exynos->clk);
 
diff --git a/drivers/usb/dwc3/dwc3-pci.c b/drivers/usb/dwc3/dwc3-pci.c
index 227d4a7acad7..eba9e2baf32b 100644
--- a/drivers/usb/dwc3/dwc3-pci.c
+++ b/drivers/usb/dwc3/dwc3-pci.c
@@ -196,9 +196,9 @@ static void dwc3_pci_remove(struct pci_dev *pci)
 {
         struct dwc3_pci *glue = pci_get_drvdata(pci);
 
+        platform_device_unregister(glue->dwc3);
         platform_device_unregister(glue->usb2_phy);
         platform_device_unregister(glue->usb3_phy);
-        platform_device_unregister(glue->dwc3);
         pci_set_drvdata(pci, NULL);
         pci_disable_device(pci);
 }
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c
index 2b6e7e001207..b5e5b35df49c 100644
--- a/drivers/usb/dwc3/gadget.c
+++ b/drivers/usb/dwc3/gadget.c
@@ -1706,11 +1706,19 @@ static void dwc3_gadget_free_endpoints(struct dwc3 *dwc)
                 dep = dwc->eps[epnum];
                 if (!dep)
                         continue;
-
-                dwc3_free_trb_pool(dep);
-
-                if (epnum != 0 && epnum != 1)
+                /*
+                 * Physical endpoints 0 and 1 are special; they form the
+                 * bi-directional USB endpoint 0.
+                 *
+                 * For those two physical endpoints, we don't allocate a TRB
+                 * pool nor do we add them the endpoints list. Due to that, we
+                 * shouldn't do these two operations otherwise we would end up
+                 * with all sorts of bugs when removing dwc3.ko.
+                 */
+                if (epnum != 0 && epnum != 1) {
+                        dwc3_free_trb_pool(dep);
                         list_del(&dep->endpoint.ep_list);
+                }
 
                 kfree(dep);
         }
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index 344d5e2f87d7..922a65d361c8 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -225,7 +225,7 @@ config USB_EHCI_SH
 
 config USB_EHCI_S5P
        tristate "EHCI support for Samsung S5P/EXYNOS SoC Series"
-       depends on PLAT_S5P
+       depends on PLAT_S5P || ARCH_EXYNOS
        help
         Enable support for the Samsung S5Pxxxx and Exynos3/4/5 SOC's
         on-chip EHCI controller.
diff --git a/drivers/usb/host/ehci-platform.c b/drivers/usb/host/ehci-platform.c
index f47f2594c9d4..d1f5cea435aa 100644
--- a/drivers/usb/host/ehci-platform.c
+++ b/drivers/usb/host/ehci-platform.c
@@ -48,6 +48,12 @@ static int ehci_platform_reset(struct usb_hcd *hcd)
         ehci->big_endian_desc = pdata->big_endian_desc;
         ehci->big_endian_mmio = pdata->big_endian_mmio;
 
+        if (pdata->pre_setup) {
+                retval = pdata->pre_setup(hcd);
+                if (retval < 0)
+                        return retval;
+        }
+
         ehci->caps = hcd->regs + pdata->caps_offset;
         retval = ehci_setup(hcd);
         if (retval)
diff --git a/drivers/usb/host/ehci-sched.c b/drivers/usb/host/ehci-sched.c
index acff5b8f6e89..f80d0330d548 100644
--- a/drivers/usb/host/ehci-sched.c
+++ b/drivers/usb/host/ehci-sched.c
@@ -213,7 +213,7 @@ static inline unsigned char tt_start_uframe(struct ehci_hcd *ehci, __hc32 mask)
 }
 
 static const unsigned char
-max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 125, 25 };
+max_tt_usecs[] = { 125, 125, 125, 125, 125, 125, 30, 0 };
 
 /* carryover low/fullspeed bandwidth that crosses uframe boundries */
 static inline void carryover_tt_bandwidth(unsigned short tt_usecs[8])
@@ -646,6 +646,10 @@ static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
         /* reschedule QH iff another request is queued */
         if (!list_empty(&qh->qtd_list) && ehci->rh_state == EHCI_RH_RUNNING) {
                 rc = qh_schedule(ehci, qh);
+                if (rc == 0) {
+                        qh_refresh(ehci, qh);
+                        qh_link_periodic(ehci, qh);
+                }
 
                 /* An error here likely indicates handshake failure
                  * or no space left in the schedule.  Neither fault
@@ -653,9 +657,10 @@ static void end_unlink_intr(struct ehci_hcd *ehci, struct ehci_qh *qh)
                  *
                  * FIXME kill the now-dysfunctional queued urbs
                  */
-                if (rc != 0)
+                else {
                         ehci_err(ehci, "can't reschedule qh %p, err %d\n",
                                         qh, rc);
+                }
         }
 
         /* maybe turn off periodic schedule */
diff --git a/drivers/usb/host/xhci-mem.c b/drivers/usb/host/xhci-mem.c
index 2cfc465925bd..fbf75e57628b 100644
--- a/drivers/usb/host/xhci-mem.c
+++ b/drivers/usb/host/xhci-mem.c
@@ -1827,6 +1827,9 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
         }
         spin_unlock_irqrestore(&xhci->lock, flags);
 
+        if (!xhci->rh_bw)
+                goto no_bw;
+
         num_ports = HCS_MAX_PORTS(xhci->hcs_params1);
         for (i = 0; i < num_ports; i++) {
                 struct xhci_interval_bw_table *bwt = &xhci->rh_bw[i].bw_table;
@@ -1845,6 +1848,7 @@ void xhci_mem_cleanup(struct xhci_hcd *xhci)
                 }
         }
 
+no_bw:
         xhci->num_usb2_ports = 0;
         xhci->num_usb3_ports = 0;
         xhci->num_active_eps = 0;
@@ -2256,6 +2260,9 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
         u32 page_size, temp;
         int i;
 
+        INIT_LIST_HEAD(&xhci->lpm_failed_devs);
+        INIT_LIST_HEAD(&xhci->cancel_cmd_list);
+
         page_size = xhci_readl(xhci, &xhci->op_regs->page_size);
         xhci_dbg(xhci, "Supported page size register = 0x%x\n", page_size);
         for (i = 0; i < 16; i++) {
@@ -2334,7 +2341,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
         xhci->cmd_ring = xhci_ring_alloc(xhci, 1, 1, TYPE_COMMAND, flags);
         if (!xhci->cmd_ring)
                 goto fail;
-        INIT_LIST_HEAD(&xhci->cancel_cmd_list);
         xhci_dbg(xhci, "Allocated command ring at %p\n", xhci->cmd_ring);
         xhci_dbg(xhci, "First segment DMA is 0x%llx\n",
                         (unsigned long long)xhci->cmd_ring->first_seg->dma);
@@ -2445,8 +2451,6 @@ int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags)
         if (xhci_setup_port_arrays(xhci, flags))
                 goto fail;
 
-        INIT_LIST_HEAD(&xhci->lpm_failed_devs);
-
         /* Enable USB 3.0 device notifications for function remote wake, which
          * is necessary for allowing USB 3.0 devices to do remote wakeup from
          * U3 (device suspend).
diff --git a/drivers/usb/host/xhci-pci.c b/drivers/usb/host/xhci-pci.c
index 1a30c380043c..cc24e39b97d5 100644
--- a/drivers/usb/host/xhci-pci.c
+++ b/drivers/usb/host/xhci-pci.c
@@ -221,6 +221,14 @@ static void xhci_pci_remove(struct pci_dev *dev)
 static int xhci_pci_suspend(struct usb_hcd *hcd, bool do_wakeup)
 {
         struct xhci_hcd *xhci = hcd_to_xhci(hcd);
+        struct pci_dev          *pdev = to_pci_dev(hcd->self.controller);
+
+        /*
+         * Systems with the TI redriver that loses port status change events
+         * need to have the registers polled during D3, so avoid D3cold.
+         */
+        if (xhci_compliance_mode_recovery_timer_quirk_check())
+                pdev->no_d3cold = true;
 
         return xhci_suspend(xhci);
 }
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index b4aa79d154b2..d8f640b12dd9 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -466,7 +466,7 @@ static void compliance_mode_recovery_timer_init(struct xhci_hcd *xhci)
  * Systems:
  * Vendor: Hewlett-Packard -> System Models: Z420, Z620 and Z820
  */
-static bool compliance_mode_recovery_timer_quirk_check(void)
+bool xhci_compliance_mode_recovery_timer_quirk_check(void)
 {
         const char *dmi_product_name, *dmi_sys_vendor;
 
@@ -517,7 +517,7 @@ int xhci_init(struct usb_hcd *hcd)
         xhci_dbg(xhci, "Finished xhci_init\n");
 
         /* Initializing Compliance Mode Recovery Data If Needed */
-        if (compliance_mode_recovery_timer_quirk_check()) {
+        if (xhci_compliance_mode_recovery_timer_quirk_check()) {
                 xhci->quirks |= XHCI_COMP_MODE_QUIRK;
                 compliance_mode_recovery_timer_init(xhci);
         }
@@ -956,6 +956,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
         struct usb_hcd          *hcd = xhci_to_hcd(xhci);
         struct usb_hcd          *secondary_hcd;
         int                     retval = 0;
+        bool                    comp_timer_running = false;
 
         /* Wait a bit if either of the roothubs need to settle from the
          * transition into bus suspend.
@@ -993,6 +994,13 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
 
         /* If restore operation fails, re-initialize the HC during resume */
         if ((temp & STS_SRE) || hibernated) {
+
+                if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) &&
+                                !(xhci_all_ports_seen_u0(xhci))) {
+                        del_timer_sync(&xhci->comp_mode_recovery_timer);
+                        xhci_dbg(xhci, "Compliance Mode Recovery Timer deleted!\n");
+                }
+
                 /* Let the USB core know _both_ roothubs lost power. */
                 usb_root_hub_lost_power(xhci->main_hcd->self.root_hub);
                 usb_root_hub_lost_power(xhci->shared_hcd->self.root_hub);
@@ -1035,6 +1043,8 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
                 retval = xhci_init(hcd->primary_hcd);
                 if (retval)
                         return retval;
+                comp_timer_running = true;
+
                 xhci_dbg(xhci, "Start the primary HCD\n");
                 retval = xhci_run(hcd->primary_hcd);
                 if (!retval) {
@@ -1076,7 +1086,7 @@ int xhci_resume(struct xhci_hcd *xhci, bool hibernated)
          * to suffer the Compliance Mode issue again. It doesn't matter if
          * ports have entered previously to U0 before system's suspension.
          */
-        if (xhci->quirks & XHCI_COMP_MODE_QUIRK)
+        if ((xhci->quirks & XHCI_COMP_MODE_QUIRK) && !comp_timer_running)
                 compliance_mode_recovery_timer_init(xhci);
 
         /* Re-enable port polling. */
diff --git a/drivers/usb/host/xhci.h b/drivers/usb/host/xhci.h
index 29c978e37135..77600cefcaf1 100644
--- a/drivers/usb/host/xhci.h
+++ b/drivers/usb/host/xhci.h
@@ -1853,4 +1853,7 @@ struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_hcd *xhci,
 struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
 struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
 
+/* xHCI quirks */
+bool xhci_compliance_mode_recovery_timer_quirk_check(void);
+
 #endif /* __LINUX_XHCI_HCD_H */
diff --git a/drivers/usb/musb/musb_host.c b/drivers/usb/musb/musb_host.c
index 8914dec49f01..9d3044bdebe5 100644
--- a/drivers/usb/musb/musb_host.c
+++ b/drivers/usb/musb/musb_host.c
@@ -1232,7 +1232,6 @@ void musb_host_tx(struct musb *musb, u8 epnum)
         void __iomem            *mbase = musb->mregs;
         struct dma_channel      *dma;
         bool                    transfer_pending = false;
-        static bool use_sg;
 
         musb_ep_select(mbase, epnum);
         tx_csr = musb_readw(epio, MUSB_TXCSR);
@@ -1463,9 +1462,9 @@ done:
          * NULL.
          */
         if (!urb->transfer_buffer)
-                use_sg = true;
+                qh->use_sg = true;
 
-        if (use_sg) {
+        if (qh->use_sg) {
                 /* sg_miter_start is already done in musb_ep_program */
                 if (!sg_miter_next(&qh->sg_miter)) {
                         dev_err(musb->controller, "error: sg list empty\n");
@@ -1484,9 +1483,9 @@ done:
 
         qh->segsize = length;
 
-        if (use_sg) {
+        if (qh->use_sg) {
                 if (offset + length >= urb->transfer_buffer_length)
-                        use_sg = false;
+                        qh->use_sg = false;
         }
 
         musb_ep_select(mbase, epnum);
@@ -1552,7 +1551,6 @@ void musb_host_rx(struct musb *musb, u8 epnum)
         bool                    done = false;
         u32                     status;
         struct dma_channel      *dma;
-        static bool use_sg;
         unsigned int sg_flags = SG_MITER_ATOMIC | SG_MITER_TO_SG;
 
         musb_ep_select(mbase, epnum);
@@ -1878,12 +1876,12 @@ void musb_host_rx(struct musb *musb, u8 epnum)
                          * NULL.
                          */
                         if (!urb->transfer_buffer) {
-                                use_sg = true;
+                                qh->use_sg = true;
                                 sg_miter_start(&qh->sg_miter, urb->sg, 1,
                                                 sg_flags);
                         }
 
-                        if (use_sg) {
+                        if (qh->use_sg) {
                                 if (!sg_miter_next(&qh->sg_miter)) {
                                         dev_err(musb->controller, "error: sg list empty\n");
                                         sg_miter_stop(&qh->sg_miter);
@@ -1913,8 +1911,8 @@ finish:
         urb->actual_length += xfer_len;
         qh->offset += xfer_len;
         if (done) {
-                if (use_sg)
-                        use_sg = false;
+                if (qh->use_sg)
+                        qh->use_sg = false;
 
                 if (urb->status == -EINPROGRESS)
                         urb->status = status;
diff --git a/drivers/usb/musb/musb_host.h b/drivers/usb/musb/musb_host.h
index 5a9c8feec10c..738f7eb60df9 100644
--- a/drivers/usb/musb/musb_host.h
+++ b/drivers/usb/musb/musb_host.h
@@ -74,6 +74,7 @@ struct musb_qh {
         u16                     frame;          /* for periodic schedule */
         unsigned                iso_idx;        /* in urb->iso_frame_desc[] */
         struct sg_mapping_iter sg_miter;        /* for highmem in PIO mode */
+        bool                    use_sg;         /* to track urb using sglist */
 };
 
 /* map from control or bulk queue head to the first qh on that ring */
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index 7ef3eb8617a6..13c09c299f15 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -180,15 +180,15 @@ config USB_MXS_PHY
           MXS Phy is used by some of the i.MX SoCs, for example imx23/28/6x.
 
 config USB_RCAR_PHY
-        tristate "Renesas R-Car USB phy support"
+        tristate "Renesas R-Car USB PHY support"
         depends on USB || USB_GADGET
         help
-          Say Y here to add support for the Renesas R-Car USB phy driver.
-          This chip is typically used as USB phy for USB host, gadget.
-          This driver supports: R8A7779
+          Say Y here to add support for the Renesas R-Car USB common PHY driver.
+          This chip is typically used as USB PHY for USB host, gadget.
+          This driver supports R8A7778 and R8A7779.
 
           To compile this driver as a module, choose M here: the
-          module will be called rcar-phy.
+          module will be called phy-rcar-usb.
 
 config USB_ULPI
         bool "Generic ULPI Transceiver Driver"
diff --git a/drivers/usb/phy/phy-rcar-usb.c b/drivers/usb/phy/phy-rcar-usb.c
index a35681b0c501..ae909408958d 100644
--- a/drivers/usb/phy/phy-rcar-usb.c
+++ b/drivers/usb/phy/phy-rcar-usb.c
@@ -1,8 +1,9 @@
 /*
  * Renesas R-Car USB phy driver
  *
- * Copyright (C) 2012 Renesas Solutions Corp.
+ * Copyright (C) 2012-2013 Renesas Solutions Corp.
  * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
+ * Copyright (C) 2013 Cogent Embedded, Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 as
@@ -15,17 +16,41 @@
 #include <linux/platform_device.h>
 #include <linux/spinlock.h>
 #include <linux/module.h>
-
-/* USBH common register */
-#define USBPCTRL0       0x0800
-#define USBPCTRL1       0x0804
-#define USBST           0x0808
-#define USBEH0          0x080C
-#define USBOH0          0x081C
-#define USBCTL0         0x0858
-#define EIIBC1          0x0094
-#define EIIBC2          0x009C
-
+#include <linux/platform_data/usb-rcar-phy.h>
+
+/* REGS block */
+#define USBPCTRL0       0x00
+#define USBPCTRL1       0x04
+#define USBST           0x08
+#define USBEH0          0x0C
+#define USBOH0          0x1C
+#define USBCTL0         0x58
+
+/* High-speed signal quality characteristic control registers (R8A7778 only) */
+#define HSQCTL1         0x24
+#define HSQCTL2         0x28
+
+/* USBPCTRL0 */
+#define OVC2            (1 << 10) /* (R8A7779 only)                     */
+                                /* Switches the OVC input pin for port 2: */
+                                /* 1: USB_OVC2, 0: OVC2                 */
+#define OVC1_VBUS1      (1 << 9) /* Switches the OVC input pin for port 1: */
+                                /* 1: USB_OVC1, 0: OVC1/VBUS1           */
+                                /* Function mode: set to 0              */
+#define OVC0            (1 << 8) /* Switches the OVC input pin for port 0: */
+                                /* 1: USB_OVC0 pin, 0: OVC0             */
+#define OVC2_ACT        (1 << 6) /* (R8A7779 only)                      */
+                                /* Host mode: OVC2 polarity:            */
+                                /* 1: active-high, 0: active-low        */
+#define PENC            (1 << 4) /* Function mode: output level of PENC1 pin: */
+                                /* 1: high, 0: low                      */
+#define OVC0_ACT        (1 << 3) /* Host mode: OVC0 polarity:           */
+                                /* 1: active-high, 0: active-low        */
+#define OVC1_ACT        (1 << 1) /* Host mode: OVC1 polarity:           */
+                                /* 1: active-high, 0: active-low        */
+                                /* Function mode: be sure to set to 1   */
+#define PORT1           (1 << 0) /* Selects port 1 mode:                */
+                                /* 1: function, 0: host                 */
 /* USBPCTRL1 */
 #define PHY_RST         (1 << 2)
 #define PLL_ENB         (1 << 1)
@@ -58,8 +83,10 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
 {
         struct rcar_usb_phy_priv *priv = usb_phy_to_priv(phy);
         struct device *dev = phy->dev;
+        struct rcar_phy_platform_data *pdata = dev->platform_data;
         void __iomem *reg0 = priv->reg0;
         void __iomem *reg1 = priv->reg1;
+        static const u8 ovcn_act[] = { OVC0_ACT, OVC1_ACT, OVC2_ACT };
         int i;
         u32 val;
         unsigned long flags;
@@ -77,7 +104,16 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
                 /* (2) start USB-PHY internal PLL */
                 iowrite32(PHY_ENB | PLL_ENB, (reg0 + USBPCTRL1));
 
-                /* (3) USB module status check */
+                /* (3) set USB-PHY in accord with the conditions of usage */
+                if (reg1) {
+                        u32 hsqctl1 = pdata->ferrite_bead ? 0x41 : 0;
+                        u32 hsqctl2 = pdata->ferrite_bead ? 0x0d : 7;
+
+                        iowrite32(hsqctl1, reg1 + HSQCTL1);
+                        iowrite32(hsqctl2, reg1 + HSQCTL2);
+                }
+
+                /* (4) USB module status check */
                 for (i = 0; i < 1024; i++) {
                         udelay(10);
                         val = ioread32(reg0 + USBST);
@@ -90,24 +126,24 @@ static int rcar_usb_phy_init(struct usb_phy *phy)
                         goto phy_init_end;
                 }
 
-                /* (4) USB-PHY reset clear */
+                /* (5) USB-PHY reset clear */
                 iowrite32(PHY_ENB | PLL_ENB | PHY_RST, (reg0 + USBPCTRL1));
 
-                /* set platform specific port settings */
-                iowrite32(0x00000000, (reg0 + USBPCTRL0));
-
-                /*
-                 * EHCI IP internal buffer setting
-                 * EHCI IP internal buffer enable
-                 *
-                 * These are recommended value of a datasheet
-                 * see [USB :: EHCI internal buffer setting]
-                 */
-                iowrite32(0x00ff0040, (reg0 + EIIBC1));
-                iowrite32(0x00ff0040, (reg1 + EIIBC1));
-
-                iowrite32(0x00000001, (reg0 + EIIBC2));
-                iowrite32(0x00000001, (reg1 + EIIBC2));
+                /* Board specific port settings */
+                val = 0;
+                if (pdata->port1_func)
+                        val |= PORT1;
+                if (pdata->penc1)
+                        val |= PENC;
+                for (i = 0; i < 3; i++) {
+                        /* OVCn bits follow each other in the right order */
+                        if (pdata->ovc_pin[i].select_3_3v)
+                                val |= OVC0 << i;
+                        /* OVCn_ACT bits are spaced by irregular intervals */
+                        if (pdata->ovc_pin[i].active_high)
+                                val |= ovcn_act[i];
+                }
+                iowrite32(val, (reg0 + USBPCTRL0));
 
                 /*
                  * Bus alignment settings
@@ -134,10 +170,8 @@ static void rcar_usb_phy_shutdown(struct usb_phy *phy)
 
         spin_lock_irqsave(&priv->lock, flags);
 
-        if (priv->counter-- == 1) { /* last user */
-                iowrite32(0x00000000, (reg0 + USBPCTRL0));
+        if (priv->counter-- == 1)       /* last user */
                 iowrite32(0x00000000, (reg0 + USBPCTRL1));
-        }
 
         spin_unlock_irqrestore(&priv->lock, flags);
 }
@@ -147,27 +181,29 @@ static int rcar_usb_phy_probe(struct platform_device *pdev)
         struct rcar_usb_phy_priv *priv;
         struct resource *res0, *res1;
         struct device *dev = &pdev->dev;
-        void __iomem *reg0, *reg1;
+        void __iomem *reg0, *reg1 = NULL;
         int ret;
 
+        if (!pdev->dev.platform_data) {
+                dev_err(dev, "No platform data\n");
+                return -EINVAL;
+        }
+
         res0 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-        res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-        if (!res0 || !res1) {
+        if (!res0) {
                 dev_err(dev, "Not enough platform resources\n");
                 return -EINVAL;
         }
 
-        /*
-         * CAUTION
-         *
-         * Because this phy address is also mapped under OHCI/EHCI address area,
-         * this driver can't use devm_request_and_ioremap(dev, res) here
-         */
-        reg0 = devm_ioremap_nocache(dev, res0->start, resource_size(res0));
-        reg1 = devm_ioremap_nocache(dev, res1->start, resource_size(res1));
-        if (!reg0 || !reg1) {
-                dev_err(dev, "ioremap error\n");
-                return -ENOMEM;
+        reg0 = devm_ioremap_resource(dev, res0);
+        if (IS_ERR(reg0))
+                return PTR_ERR(reg0);
+
+        res1 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
+        if (res1) {
+                reg1 = devm_ioremap_resource(dev, res1);
+                if (IS_ERR(reg1))
+                        return PTR_ERR(reg1);
         }
 
         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
diff --git a/drivers/usb/serial/ark3116.c b/drivers/usb/serial/ark3116.c
index 3b16118cbf62..40e7fd94646f 100644
--- a/drivers/usb/serial/ark3116.c
+++ b/drivers/usb/serial/ark3116.c
@@ -43,7 +43,7 @@
 #define DRIVER_NAME "ark3116"
 
 /* usb timeout of 1 second */
-#define ARK_TIMEOUT (1*HZ)
+#define ARK_TIMEOUT 1000
 
 static const struct usb_device_id id_table[] = {
         { USB_DEVICE(0x6547, 0x0232) },
diff --git a/drivers/usb/serial/cypress_m8.c b/drivers/usb/serial/cypress_m8.c
index d341555d37d8..082120198f87 100644
--- a/drivers/usb/serial/cypress_m8.c
+++ b/drivers/usb/serial/cypress_m8.c
@@ -65,6 +65,7 @@ static const struct usb_device_id id_table_earthmate[] = {
 static const struct usb_device_id id_table_cyphidcomrs232[] = {
         { USB_DEVICE(VENDOR_ID_CYPRESS, PRODUCT_ID_CYPHIDCOM) },
         { USB_DEVICE(VENDOR_ID_POWERCOM, PRODUCT_ID_UPS) },
+        { USB_DEVICE(VENDOR_ID_FRWD, PRODUCT_ID_CYPHIDCOM_FRWD) },
         { }                                             /* Terminating entry */
 };
 
@@ -78,6 +79,7 @@ static const struct usb_device_id id_table_combined[] = {
         { USB_DEVICE(VENDOR_ID_DELORME, PRODUCT_ID_EARTHMATEUSB_LT20) },
         { USB_DEVICE(VENDOR_ID_CYPRESS, PRODUCT_ID_CYPHIDCOM) },
         { USB_DEVICE(VENDOR_ID_POWERCOM, PRODUCT_ID_UPS) },
+        { USB_DEVICE(VENDOR_ID_FRWD, PRODUCT_ID_CYPHIDCOM_FRWD) },
         { USB_DEVICE(VENDOR_ID_DAZZLE, PRODUCT_ID_CA42) },
         { }                                             /* Terminating entry */
 };
@@ -229,6 +231,12 @@ static struct usb_serial_driver * const serial_drivers[] = {
  * Cypress serial helper functions
  *****************************************************************************/
 
+/* FRWD Dongle hidcom needs to skip reset and speed checks */
+static inline bool is_frwd(struct usb_device *dev)
+{
+        return ((le16_to_cpu(dev->descriptor.idVendor) == VENDOR_ID_FRWD) &&
+                (le16_to_cpu(dev->descriptor.idProduct) == PRODUCT_ID_CYPHIDCOM_FRWD));
+}
 
 static int analyze_baud_rate(struct usb_serial_port *port, speed_t new_rate)
 {
@@ -238,6 +246,10 @@ static int analyze_baud_rate(struct usb_serial_port *port, speed_t new_rate)
         if (unstable_bauds)
                 return new_rate;
 
+        /* FRWD Dongle uses 115200 bps */
+        if (is_frwd(port->serial->dev))
+                return new_rate;
+
         /*
          * The general purpose firmware for the Cypress M8 allows for
          * a maximum speed of 57600bps (I have no idea whether DeLorme
@@ -448,7 +460,11 @@ static int cypress_generic_port_probe(struct usb_serial_port *port)
                 return -ENOMEM;
         }
 
-        usb_reset_configuration(serial->dev);
+        /* Skip reset for FRWD device. It is a workaound:
+           device hangs if it receives SET_CONFIGURE in Configured
+           state. */
+        if (!is_frwd(serial->dev))
+                usb_reset_configuration(serial->dev);
 
         priv->cmd_ctrl = 0;
         priv->line_control = 0;
diff --git a/drivers/usb/serial/cypress_m8.h b/drivers/usb/serial/cypress_m8.h
index 67cf60826884..b461311a2ae7 100644
--- a/drivers/usb/serial/cypress_m8.h
+++ b/drivers/usb/serial/cypress_m8.h
@@ -24,6 +24,10 @@
 #define VENDOR_ID_CYPRESS               0x04b4
 #define PRODUCT_ID_CYPHIDCOM            0x5500
 
+/* FRWD Dongle - a GPS sports watch */
+#define VENDOR_ID_FRWD                  0x6737
+#define PRODUCT_ID_CYPHIDCOM_FRWD       0x0001
+
 /* Powercom UPS, chip CY7C63723 */
 #define VENDOR_ID_POWERCOM              0x0d9f
 #define PRODUCT_ID_UPS                  0x0002
diff --git a/drivers/usb/serial/f81232.c b/drivers/usb/serial/f81232.c
index 090b411d893f..7d8dd5aad236 100644
--- a/drivers/usb/serial/f81232.c
+++ b/drivers/usb/serial/f81232.c
@@ -165,11 +165,12 @@ static void f81232_set_termios(struct tty_struct *tty,
         /* FIXME - Stubbed out for now */
 
         /* Don't change anything if nothing has changed */
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         /* Do the real work here... */
-        tty_termios_copy_hw(&tty->termios, old_termios);
+        if (old_termios)
+                tty_termios_copy_hw(&tty->termios, old_termios);
 }
 
 static int f81232_tiocmget(struct tty_struct *tty)
@@ -187,12 +188,11 @@ static int f81232_tiocmset(struct tty_struct *tty,
 
 static int f81232_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         int result;
 
         /* Setup termios */
         if (tty)
-                f81232_set_termios(tty, port, &tmp_termios);
+                f81232_set_termios(tty, port, NULL);
 
         result = usb_submit_urb(port->interrupt_in_urb, GFP_KERNEL);
         if (result) {
diff --git a/drivers/usb/serial/iuu_phoenix.c b/drivers/usb/serial/iuu_phoenix.c
index 9d74c278b7b5..790673e5faa7 100644
--- a/drivers/usb/serial/iuu_phoenix.c
+++ b/drivers/usb/serial/iuu_phoenix.c
@@ -287,7 +287,7 @@ static int bulk_immediate(struct usb_serial_port *port, u8 *buf, u8 count)
             usb_bulk_msg(serial->dev,
                          usb_sndbulkpipe(serial->dev,
                                          port->bulk_out_endpointAddress), buf,
-                         count, &actual, HZ * 1);
+                         count, &actual, 1000);
 
         if (status != IUU_OPERATION_OK)
                 dev_dbg(&port->dev, "%s - error = %2x\n", __func__, status);
@@ -307,7 +307,7 @@ static int read_immediate(struct usb_serial_port *port, u8 *buf, u8 count)
             usb_bulk_msg(serial->dev,
                          usb_rcvbulkpipe(serial->dev,
                                          port->bulk_in_endpointAddress), buf,
-                         count, &actual, HZ * 1);
+                         count, &actual, 1000);
 
         if (status != IUU_OPERATION_OK)
                 dev_dbg(&port->dev, "%s - error = %2x\n", __func__, status);
diff --git a/drivers/usb/serial/keyspan.c b/drivers/usb/serial/keyspan.c
index eb30d7b01f36..3549d073df22 100644
--- a/drivers/usb/serial/keyspan.c
+++ b/drivers/usb/serial/keyspan.c
@@ -1548,7 +1548,6 @@ static int keyspan_usa26_send_setup(struct usb_serial *serial,
         struct keyspan_serial_private           *s_priv;
         struct keyspan_port_private             *p_priv;
         const struct keyspan_device_details     *d_details;
-        int                                     outcont_urb;
         struct urb                              *this_urb;
         int                                     device_port, err;
 
@@ -1559,7 +1558,6 @@ static int keyspan_usa26_send_setup(struct usb_serial *serial,
         d_details = s_priv->device_details;
         device_port = port->number - port->serial->minor;
 
-        outcont_urb = d_details->outcont_endpoints[port->number];
         this_urb = p_priv->outcont_urb;
 
         dev_dbg(&port->dev, "%s - endpoint %d\n", __func__, usb_pipeendpoint(this_urb->pipe));
@@ -1685,14 +1683,6 @@ static int keyspan_usa26_send_setup(struct usb_serial *serial,
         err = usb_submit_urb(this_urb, GFP_ATOMIC);
         if (err != 0)
                 dev_dbg(&port->dev, "%s - usb_submit_urb(setup) failed (%d)\n", __func__, err);
-#if 0
-        else {
-                dev_dbg(&port->dev, "%s - usb_submit_urb(%d) OK %d bytes (end %d)\n", __func__
-                        outcont_urb, this_urb->transfer_buffer_length,
-                        usb_pipeendpoint(this_urb->pipe));
-        }
-#endif
-
         return 0;
 }
 
diff --git a/drivers/usb/serial/mos7720.c b/drivers/usb/serial/mos7720.c
index cc0e54345df9..f27c621a9297 100644
--- a/drivers/usb/serial/mos7720.c
+++ b/drivers/usb/serial/mos7720.c
@@ -40,7 +40,7 @@
 #define DRIVER_DESC "Moschip USB Serial Driver"
 
 /* default urb timeout */
-#define MOS_WDR_TIMEOUT (HZ * 5)
+#define MOS_WDR_TIMEOUT 5000
 
 #define MOS_MAX_PORT    0x02
 #define MOS_WRITE       0x0E
@@ -227,11 +227,22 @@ static int read_mos_reg(struct usb_serial *serial, unsigned int serial_portnum,
         __u8 requesttype = (__u8)0xc0;
         __u16 index = get_reg_index(reg);
         __u16 value = get_reg_value(reg, serial_portnum);
-        int status = usb_control_msg(usbdev, pipe, request, requesttype, value,
-                                     index, data, 1, MOS_WDR_TIMEOUT);
-        if (status < 0)
+        u8 *buf;
+        int status;
+
+        buf = kmalloc(1, GFP_KERNEL);
+        if (!buf)
+                return -ENOMEM;
+
+        status = usb_control_msg(usbdev, pipe, request, requesttype, value,
+                                     index, buf, 1, MOS_WDR_TIMEOUT);
+        if (status == 1)
+                *data = *buf;
+        else if (status < 0)
                 dev_err(&usbdev->dev,
                         "mos7720: usb_control_msg() failed: %d", status);
+        kfree(buf);
+
         return status;
 }
 
@@ -1618,7 +1629,7 @@ static void change_port_settings(struct tty_struct *tty,
                 mos7720_port->shadowMCR |= (UART_MCR_XONANY);
                 /* To set hardware flow control to the specified *
                  * serial port, in SP1/2_CONTROL_REG             */
-                if (port->number)
+                if (port_number)
                         write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x01);
                 else
                         write_mos_reg(serial, dummy, SP_CONTROL_REG, 0x02);
@@ -1927,7 +1938,7 @@ static int mos7720_startup(struct usb_serial *serial)
 
         /* setting configuration feature to one */
         usb_control_msg(serial->dev, usb_sndctrlpipe(serial->dev, 0),
-                        (__u8)0x03, 0x00, 0x01, 0x00, NULL, 0x00, 5*HZ);
+                        (__u8)0x03, 0x00, 0x01, 0x00, NULL, 0x00, 5000);
 
         /* start the interrupt urb */
         ret_val = usb_submit_urb(serial->port[0]->interrupt_in_urb, GFP_KERNEL);
@@ -1970,7 +1981,7 @@ static void mos7720_release(struct usb_serial *serial)
                 /* wait for synchronous usb calls to return */
                 if (mos_parport->msg_pending)
                         wait_for_completion_timeout(&mos_parport->syncmsg_compl,
-                                                    MOS_WDR_TIMEOUT);
+                                            msecs_to_jiffies(MOS_WDR_TIMEOUT));
 
                 parport_remove_port(mos_parport->pp);
                 usb_set_serial_data(serial, NULL);
diff --git a/drivers/usb/serial/mos7840.c b/drivers/usb/serial/mos7840.c
index a0d5ea545982..7e998081e1cd 100644
--- a/drivers/usb/serial/mos7840.c
+++ b/drivers/usb/serial/mos7840.c
@@ -2142,13 +2142,21 @@ static int mos7840_ioctl(struct tty_struct *tty,
 static int mos7810_check(struct usb_serial *serial)
 {
         int i, pass_count = 0;
+        u8 *buf;
         __u16 data = 0, mcr_data = 0;
         __u16 test_pattern = 0x55AA;
+        int res;
+
+        buf = kmalloc(VENDOR_READ_LENGTH, GFP_KERNEL);
+        if (!buf)
+                return 0;       /* failed to identify 7810 */
 
         /* Store MCR setting */
-        usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
+        res = usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
                 MCS_RDREQ, MCS_RD_RTYPE, 0x0300, MODEM_CONTROL_REGISTER,
-                &mcr_data, VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+                buf, VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+        if (res == VENDOR_READ_LENGTH)
+                mcr_data = *buf;
 
         for (i = 0; i < 16; i++) {
                 /* Send the 1-bit test pattern out to MCS7810 test pin */
@@ -2158,9 +2166,12 @@ static int mos7810_check(struct usb_serial *serial)
                         MODEM_CONTROL_REGISTER, NULL, 0, MOS_WDR_TIMEOUT);
 
                 /* Read the test pattern back */
-                usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
-                        MCS_RDREQ, MCS_RD_RTYPE, 0, GPIO_REGISTER, &data,
-                        VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+                res = usb_control_msg(serial->dev,
+                                usb_rcvctrlpipe(serial->dev, 0), MCS_RDREQ,
+                                MCS_RD_RTYPE, 0, GPIO_REGISTER, buf,
+                                VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+                if (res == VENDOR_READ_LENGTH)
+                        data = *buf;
 
                 /* If this is a MCS7810 device, both test patterns must match */
                 if (((test_pattern >> i) ^ (~data >> 1)) & 0x0001)
@@ -2174,6 +2185,8 @@ static int mos7810_check(struct usb_serial *serial)
                 MCS_WR_RTYPE, 0x0300 | mcr_data, MODEM_CONTROL_REGISTER, NULL,
                 0, MOS_WDR_TIMEOUT);
 
+        kfree(buf);
+
         if (pass_count == 16)
                 return 1;
 
@@ -2183,11 +2196,17 @@ static int mos7810_check(struct usb_serial *serial)
 static int mos7840_calc_num_ports(struct usb_serial *serial)
 {
         __u16 data = 0x00;
+        u8 *buf;
         int mos7840_num_ports;
 
-        usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
-                MCS_RDREQ, MCS_RD_RTYPE, 0, GPIO_REGISTER, &data,
-                VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+        buf = kzalloc(VENDOR_READ_LENGTH, GFP_KERNEL);
+        if (buf) {
+                usb_control_msg(serial->dev, usb_rcvctrlpipe(serial->dev, 0),
+                        MCS_RDREQ, MCS_RD_RTYPE, 0, GPIO_REGISTER, buf,
+                        VENDOR_READ_LENGTH, MOS_WDR_TIMEOUT);
+                data = *buf;
+                kfree(buf);
+        }
 
         if (serial->dev->descriptor.idProduct == MOSCHIP_DEVICE_ID_7810 ||
                 serial->dev->descriptor.idProduct == MOSCHIP_DEVICE_ID_7820) {
diff --git a/drivers/usb/serial/option.c b/drivers/usb/serial/option.c
index 93d02bc4eb52..bd4323ddae1a 100644
--- a/drivers/usb/serial/option.c
+++ b/drivers/usb/serial/option.c
@@ -250,13 +250,7 @@ static void option_instat_callback(struct urb *urb);
 #define ZTE_PRODUCT_MF622                       0x0001
 #define ZTE_PRODUCT_MF628                       0x0015
 #define ZTE_PRODUCT_MF626                       0x0031
-#define ZTE_PRODUCT_CDMA_TECH                   0xfffe
-#define ZTE_PRODUCT_AC8710                      0xfff1
-#define ZTE_PRODUCT_AC2726                      0xfff5
-#define ZTE_PRODUCT_AC8710T                     0xffff
 #define ZTE_PRODUCT_MC2718                      0xffe8
-#define ZTE_PRODUCT_AD3812                      0xffeb
-#define ZTE_PRODUCT_MC2716                      0xffed
 
 #define BENQ_VENDOR_ID                          0x04a5
 #define BENQ_PRODUCT_H10                        0x4068
@@ -495,18 +489,10 @@ static const struct option_blacklist_info zte_k3765_z_blacklist = {
         .reserved = BIT(4),
 };
 
-static const struct option_blacklist_info zte_ad3812_z_blacklist = {
-        .sendsetup = BIT(0) | BIT(1) | BIT(2),
-};
-
 static const struct option_blacklist_info zte_mc2718_z_blacklist = {
         .sendsetup = BIT(1) | BIT(2) | BIT(3) | BIT(4),
 };
 
-static const struct option_blacklist_info zte_mc2716_z_blacklist = {
-        .sendsetup = BIT(1) | BIT(2) | BIT(3),
-};
-
 static const struct option_blacklist_info huawei_cdc12_blacklist = {
         .reserved = BIT(1) | BIT(2),
 };
@@ -593,6 +579,8 @@ static const struct usb_device_id option_ids[] = {
                 .driver_info = (kernel_ulong_t) &huawei_cdc12_blacklist },
         { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_K3765, 0xff, 0xff, 0xff),
                 .driver_info = (kernel_ulong_t) &huawei_cdc12_blacklist },
+        { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, 0x14ac, 0xff, 0xff, 0xff),    /* Huawei E1820 */
+                .driver_info = (kernel_ulong_t) &net_intf1_blacklist },
         { USB_DEVICE_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, HUAWEI_PRODUCT_K4605, 0xff, 0xff, 0xff),
                 .driver_info = (kernel_ulong_t) &huawei_cdc12_blacklist },
         { USB_VENDOR_AND_INTERFACE_INFO(HUAWEI_VENDOR_ID, 0xff, 0xff, 0xff) },
@@ -797,7 +785,6 @@ static const struct usb_device_id option_ids[] = {
         { USB_DEVICE_INTERFACE_CLASS(BANDRICH_VENDOR_ID, BANDRICH_PRODUCT_1012, 0xff) },
         { USB_DEVICE(KYOCERA_VENDOR_ID, KYOCERA_PRODUCT_KPC650) },
         { USB_DEVICE(KYOCERA_VENDOR_ID, KYOCERA_PRODUCT_KPC680) },
-        { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6000)}, /* ZTE AC8700 */
         { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x6613)}, /* Onda H600/ZTE MF330 */
         { USB_DEVICE(QUALCOMM_VENDOR_ID, 0x9000)}, /* SIMCom SIM5218 */
         { USB_DEVICE(CMOTECH_VENDOR_ID, CMOTECH_PRODUCT_6280) }, /* BP3-USB & BP3-EXT HSDPA */
@@ -1199,16 +1186,9 @@ static const struct usb_device_id option_ids[] = {
         { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0x0178, 0xff, 0xff, 0xff),
                 .driver_info = (kernel_ulong_t)&net_intf3_blacklist },
 
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_CDMA_TECH, 0xff, 0xff, 0xff) },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC8710, 0xff, 0xff, 0xff) },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC2726, 0xff, 0xff, 0xff) },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AC8710T, 0xff, 0xff, 0xff) },
+        /* NOTE: most ZTE CDMA devices should be driven by zte_ev, not option */
         { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_MC2718, 0xff, 0xff, 0xff),
          .driver_info = (kernel_ulong_t)&zte_mc2718_z_blacklist },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_AD3812, 0xff, 0xff, 0xff),
-         .driver_info = (kernel_ulong_t)&zte_ad3812_z_blacklist },
-        { USB_DEVICE_AND_INTERFACE_INFO(ZTE_VENDOR_ID, ZTE_PRODUCT_MC2716, 0xff, 0xff, 0xff),
-         .driver_info = (kernel_ulong_t)&zte_mc2716_z_blacklist },
         { USB_VENDOR_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff, 0x02, 0x01) },
         { USB_VENDOR_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff, 0x02, 0x05) },
         { USB_VENDOR_AND_INTERFACE_INFO(ZTE_VENDOR_ID, 0xff, 0x86, 0x10) },
diff --git a/drivers/usb/serial/pl2303.c b/drivers/usb/serial/pl2303.c
index 7151659367a0..048cd44d51b1 100644
--- a/drivers/usb/serial/pl2303.c
+++ b/drivers/usb/serial/pl2303.c
@@ -284,7 +284,7 @@ static void pl2303_set_termios(struct tty_struct *tty,
            serial settings even to the same values as before. Thus
            we actually need to filter in this specific case */
 
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         cflag = tty->termios.c_cflag;
@@ -293,7 +293,8 @@ static void pl2303_set_termios(struct tty_struct *tty,
         if (!buf) {
                 dev_err(&port->dev, "%s - out of memory.\n", __func__);
                 /* Report back no change occurred */
-                tty->termios = *old_termios;
+                if (old_termios)
+                        tty->termios = *old_termios;
                 return;
         }
 
@@ -433,7 +434,7 @@ static void pl2303_set_termios(struct tty_struct *tty,
         control = priv->line_control;
         if ((cflag & CBAUD) == B0)
                 priv->line_control &= ~(CONTROL_DTR | CONTROL_RTS);
-        else if ((old_termios->c_cflag & CBAUD) == B0)
+        else if (old_termios && (old_termios->c_cflag & CBAUD) == B0)
                 priv->line_control |= (CONTROL_DTR | CONTROL_RTS);
         if (control != priv->line_control) {
                 control = priv->line_control;
@@ -492,7 +493,6 @@ static void pl2303_close(struct usb_serial_port *port)
 
 static int pl2303_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         struct usb_serial *serial = port->serial;
         struct pl2303_serial_private *spriv = usb_get_serial_data(serial);
         int result;
@@ -508,7 +508,7 @@ static int pl2303_open(struct tty_struct *tty, struct usb_serial_port *port)
 
         /* Setup termios */
         if (tty)
-                pl2303_set_termios(tty, port, &tmp_termios);
+                pl2303_set_termios(tty, port, NULL);
 
         result = usb_submit_urb(port->interrupt_in_urb, GFP_KERNEL);
         if (result) {
diff --git a/drivers/usb/serial/qcserial.c b/drivers/usb/serial/qcserial.c
index 59b32b782126..bd794b43898c 100644
--- a/drivers/usb/serial/qcserial.c
+++ b/drivers/usb/serial/qcserial.c
@@ -118,6 +118,7 @@ static const struct usb_device_id id_table[] = {
         {USB_DEVICE(0x1199, 0x901b)},   /* Sierra Wireless MC7770 */
         {USB_DEVICE(0x12D1, 0x14F0)},   /* Sony Gobi 3000 QDL */
         {USB_DEVICE(0x12D1, 0x14F1)},   /* Sony Gobi 3000 Composite */
+        {USB_DEVICE(0x0AF0, 0x8120)},   /* Option GTM681W */
 
         /* non Gobi Qualcomm serial devices */
         {USB_DEVICE_INTERFACE_NUMBER(0x0f3d, 0x68a2, 0)},       /* Sierra Wireless MC7700 Device Management */
diff --git a/drivers/usb/serial/spcp8x5.c b/drivers/usb/serial/spcp8x5.c
index cf3df793c2b7..ddf6c47137dc 100644
--- a/drivers/usb/serial/spcp8x5.c
+++ b/drivers/usb/serial/spcp8x5.c
@@ -291,7 +291,6 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
         struct spcp8x5_private *priv = usb_get_serial_port_data(port);
         unsigned long flags;
         unsigned int cflag = tty->termios.c_cflag;
-        unsigned int old_cflag = old_termios->c_cflag;
         unsigned short uartdata;
         unsigned char buf[2] = {0, 0};
         int baud;
@@ -299,15 +298,15 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
         u8 control;
 
         /* check that they really want us to change something */
-        if (!tty_termios_hw_change(&tty->termios, old_termios))
+        if (old_termios && !tty_termios_hw_change(&tty->termios, old_termios))
                 return;
 
         /* set DTR/RTS active */
         spin_lock_irqsave(&priv->lock, flags);
         control = priv->line_control;
-        if ((old_cflag & CBAUD) == B0) {
+        if (old_termios && (old_termios->c_cflag & CBAUD) == B0) {
                 priv->line_control |= MCR_DTR;
-                if (!(old_cflag & CRTSCTS))
+                if (!(old_termios->c_cflag & CRTSCTS))
                         priv->line_control |= MCR_RTS;
         }
         if (control != priv->line_control) {
@@ -394,7 +393,6 @@ static void spcp8x5_set_termios(struct tty_struct *tty,
 
 static int spcp8x5_open(struct tty_struct *tty, struct usb_serial_port *port)
 {
-        struct ktermios tmp_termios;
         struct usb_serial *serial = port->serial;
         struct spcp8x5_private *priv = usb_get_serial_port_data(port);
         int ret;
@@ -411,7 +409,7 @@ static int spcp8x5_open(struct tty_struct *tty, struct usb_serial_port *port)
         spcp8x5_set_ctrl_line(port, priv->line_control);
 
         if (tty)
-                spcp8x5_set_termios(tty, port, &tmp_termios);
+                spcp8x5_set_termios(tty, port, NULL);
 
         port->port.drain_delay = 256;
 
diff --git a/drivers/usb/serial/usb-serial.c b/drivers/usb/serial/usb-serial.c
index 4753c005cfb6..5f6b1ff9d29e 100644
--- a/drivers/usb/serial/usb-serial.c
+++ b/drivers/usb/serial/usb-serial.c
@@ -408,7 +408,7 @@ static int serial_ioctl(struct tty_struct *tty,
                                         unsigned int cmd, unsigned long arg)
 {
         struct usb_serial_port *port = tty->driver_data;
-        int retval = -ENODEV;
+        int retval = -ENOIOCTLCMD;
 
         dev_dbg(tty->dev, "%s - cmd 0x%.4x\n", __func__, cmd);
 
@@ -420,8 +420,6 @@ static int serial_ioctl(struct tty_struct *tty,
         default:
                 if (port->serial->type->ioctl)
                         retval = port->serial->type->ioctl(tty, cmd, arg);
-                else
-                        retval = -ENOIOCTLCMD;
         }
 
         return retval;
diff --git a/drivers/usb/serial/visor.c b/drivers/usb/serial/visor.c
index 7573ec8a084f..9910aa2edf4b 100644
--- a/drivers/usb/serial/visor.c
+++ b/drivers/usb/serial/visor.c
@@ -560,10 +560,19 @@ static int treo_attach(struct usb_serial *serial)
         */
 #define COPY_PORT(dest, src)                                            \
         do { \
+                int i;                                                  \
+                                                                        \
+                for (i = 0; i < ARRAY_SIZE(src->read_urbs); ++i) {      \
+                        dest->read_urbs[i] = src->read_urbs[i];         \
+                        dest->read_urbs[i]->context = dest;             \
+                        dest->bulk_in_buffers[i] = src->bulk_in_buffers[i]; \
+                }                                                       \
                 dest->read_urb = src->read_urb;                         \
                 dest->bulk_in_endpointAddress = src->bulk_in_endpointAddress;\
                 dest->bulk_in_buffer = src->bulk_in_buffer;             \
+                dest->bulk_in_size = src->bulk_in_size;                 \
                 dest->interrupt_in_urb = src->interrupt_in_urb;         \
+                dest->interrupt_in_urb->context = dest;                 \
                 dest->interrupt_in_endpointAddress = \
                                         src->interrupt_in_endpointAddress;\
                 dest->interrupt_in_buffer = src->interrupt_in_buffer;   \
diff --git a/drivers/usb/serial/whiteheat.c b/drivers/usb/serial/whiteheat.c
index b9fca3586d74..347caad47a12 100644
--- a/drivers/usb/serial/whiteheat.c
+++ b/drivers/usb/serial/whiteheat.c
@@ -649,7 +649,7 @@ static void firm_setup_port(struct tty_struct *tty)
         struct whiteheat_port_settings port_settings;
         unsigned int cflag = tty->termios.c_cflag;
 
-        port_settings.port = port->number + 1;
+        port_settings.port = port->number - port->serial->minor + 1;
 
         /* get the byte size */
         switch (cflag & CSIZE) {
diff --git a/drivers/usb/serial/zte_ev.c b/drivers/usb/serial/zte_ev.c
index 39ee7373b4ee..fca4c752a4ed 100644
--- a/drivers/usb/serial/zte_ev.c
+++ b/drivers/usb/serial/zte_ev.c
@@ -41,9 +41,6 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         int len;
         unsigned char *buf;
 
-        if (port->number != 0)
-                return -ENODEV;
-
         buf = kmalloc(MAX_SETUP_DATA_SIZE, GFP_KERNEL);
         if (!buf)
                 return -ENOMEM;
@@ -53,7 +50,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0001, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send  2st cmd and recieve data */
@@ -65,7 +62,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
                                  0x21, 0xa1,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 3 cmd */
@@ -84,7 +81,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x20, 0x21,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 4 cmd */
@@ -95,7 +92,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0003, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send 5 cmd */
@@ -107,7 +104,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
                                  0x21, 0xa1,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 6 cmd */
@@ -126,7 +123,7 @@ static int zte_ev_usb_serial_open(struct tty_struct *tty,
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x20, 0x21,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
         kfree(buf);
 
@@ -166,9 +163,6 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         int len;
         unsigned char *buf;
 
-        if (port->number != 0)
-                return;
-
         buf = kmalloc(MAX_SETUP_DATA_SIZE, GFP_KERNEL);
         if (!buf)
                 return;
@@ -178,7 +172,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0002, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send 2st ctl cmd(CTL    21 22 03 00  00 00 00 00 ) */
@@ -186,7 +180,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0003, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send  3st cmd and recieve data */
@@ -198,7 +192,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
                                  0x21, 0xa1,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 4 cmd */
@@ -217,7 +211,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x20, 0x21,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 5 cmd */
@@ -228,7 +222,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0003, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         /* send 6 cmd */
@@ -240,7 +234,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
                                  0x21, 0xa1,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 7 cmd */
@@ -259,7 +253,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x20, 0x21,
                                  0x0000, 0x0000, buf, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         debug_data(dev, __func__, len, buf, result);
 
         /* send 8 cmd */
@@ -270,7 +264,7 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
         result = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
                                  0x22, 0x21,
                                  0x0003, 0x0000, NULL, len,
-                                 HZ * USB_CTRL_GET_TIMEOUT);
+                                 USB_CTRL_GET_TIMEOUT);
         dev_dbg(dev, "result = %d\n", result);
 
         kfree(buf);
@@ -279,11 +273,29 @@ static void zte_ev_usb_serial_close(struct usb_serial_port *port)
 }
 
 static const struct usb_device_id id_table[] = {
-        { USB_DEVICE(0x19d2, 0xffff) }, /* AC8700 */
-        { USB_DEVICE(0x19d2, 0xfffe) },
-        { USB_DEVICE(0x19d2, 0xfffd) }, /* MG880 */
+        /* AC8710, AC8710T */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xffff, 0xff, 0xff, 0xff) },
+         /* AC8700 */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xfffe, 0xff, 0xff, 0xff) },
+        /* MG880 */
+        { USB_DEVICE(0x19d2, 0xfffd) },
+        { USB_DEVICE(0x19d2, 0xfffc) },
+        { USB_DEVICE(0x19d2, 0xfffb) },
+        /* AC2726, AC8710_V3 */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xfff1, 0xff, 0xff, 0xff) },
+        { USB_DEVICE(0x19d2, 0xfff6) },
+        { USB_DEVICE(0x19d2, 0xfff7) },
+        { USB_DEVICE(0x19d2, 0xfff8) },
+        { USB_DEVICE(0x19d2, 0xfff9) },
+        { USB_DEVICE(0x19d2, 0xffee) },
+        /* AC2716, MC2716 */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xffed, 0xff, 0xff, 0xff) },
+        /* AD3812 */
+        { USB_DEVICE_AND_INTERFACE_INFO(0x19d2, 0xffeb, 0xff, 0xff, 0xff) },
+        { USB_DEVICE(0x19d2, 0xffec) },
         { USB_DEVICE(0x05C6, 0x3197) },
         { USB_DEVICE(0x05C6, 0x6000) },
+        { USB_DEVICE(0x05C6, 0x9008) },
         { },
 };
 MODULE_DEVICE_TABLE(usb, id_table);
diff --git a/drivers/vfio/vfio.c b/drivers/vfio/vfio.c
index acb7121a9316..6d78736563de 100644
--- a/drivers/vfio/vfio.c
+++ b/drivers/vfio/vfio.c
@@ -1360,7 +1360,7 @@ static const struct file_operations vfio_device_fops = {
  */
 static char *vfio_devnode(struct device *dev, umode_t *mode)
 {
-        if (MINOR(dev->devt) == 0)
+        if (mode && (MINOR(dev->devt) == 0))
                 *mode = S_IRUGO | S_IWUGO;
 
         return kasprintf(GFP_KERNEL, "vfio/%s", dev_name(dev));
diff --git a/drivers/vhost/net.c b/drivers/vhost/net.c
index 2b51e2336aa2..f80d3dd41d8c 100644
--- a/drivers/vhost/net.c
+++ b/drivers/vhost/net.c
@@ -155,14 +155,11 @@ static void vhost_net_ubuf_put_and_wait(struct vhost_net_ubuf_ref *ubufs)
 
 static void vhost_net_clear_ubuf_info(struct vhost_net *n)
 {
-
-        bool zcopy;
         int i;
 
-        for (i = 0; i < n->dev.nvqs; ++i) {
-                zcopy = vhost_net_zcopy_mask & (0x1 << i);
-                if (zcopy)
-                        kfree(n->vqs[i].ubuf_info);
+        for (i = 0; i < VHOST_NET_VQ_MAX; ++i) {
+                kfree(n->vqs[i].ubuf_info);
+                n->vqs[i].ubuf_info = NULL;
         }
 }
 
@@ -171,7 +168,7 @@ int vhost_net_set_ubuf_info(struct vhost_net *n)
         bool zcopy;
         int i;
 
-        for (i = 0; i < n->dev.nvqs; ++i) {
+        for (i = 0; i < VHOST_NET_VQ_MAX; ++i) {
                 zcopy = vhost_net_zcopy_mask & (0x1 << i);
                 if (!zcopy)
                         continue;
@@ -183,12 +180,7 @@ int vhost_net_set_ubuf_info(struct vhost_net *n)
         return 0;
 
 err:
-        while (i--) {
-                zcopy = vhost_net_zcopy_mask & (0x1 << i);
-                if (!zcopy)
-                        continue;
-                kfree(n->vqs[i].ubuf_info);
-        }
+        vhost_net_clear_ubuf_info(n);
         return -ENOMEM;
 }
 
@@ -196,12 +188,12 @@ void vhost_net_vq_reset(struct vhost_net *n)
 {
         int i;
 
+        vhost_net_clear_ubuf_info(n);
+
         for (i = 0; i < VHOST_NET_VQ_MAX; i++) {
                 n->vqs[i].done_idx = 0;
                 n->vqs[i].upend_idx = 0;
                 n->vqs[i].ubufs = NULL;
-                kfree(n->vqs[i].ubuf_info);
-                n->vqs[i].ubuf_info = NULL;
                 n->vqs[i].vhost_hlen = 0;
                 n->vqs[i].sock_hlen = 0;
         }
@@ -436,7 +428,8 @@ static void handle_tx(struct vhost_net *net)
                                 kref_get(&ubufs->kref);
                         }
                         nvq->upend_idx = (nvq->upend_idx + 1) % UIO_MAXIOV;
-                }
+                } else
+                        msg.msg_control = NULL;
                 /* TODO: Check specific error and bomb out unless ENOBUFS? */
                 err = sock->ops->sendmsg(NULL, sock, &msg, len);
                 if (unlikely(err < 0)) {
@@ -1053,6 +1046,10 @@ static long vhost_net_set_owner(struct vhost_net *n)
         int r;
 
         mutex_lock(&n->dev.mutex);
+        if (vhost_dev_has_owner(&n->dev)) {
+                r = -EBUSY;
+                goto out;
+        }
         r = vhost_net_set_ubuf_info(n);
         if (r)
                 goto out;
diff --git a/drivers/vhost/vhost.c b/drivers/vhost/vhost.c
index beee7f5787e6..60aa5ad09a2f 100644
--- a/drivers/vhost/vhost.c
+++ b/drivers/vhost/vhost.c
@@ -344,13 +344,19 @@ static int vhost_attach_cgroups(struct vhost_dev *dev)
 }
 
 /* Caller should have device mutex */
+bool vhost_dev_has_owner(struct vhost_dev *dev)
+{
+        return dev->mm;
+}
+
+/* Caller should have device mutex */
 long vhost_dev_set_owner(struct vhost_dev *dev)
 {
         struct task_struct *worker;
         int err;
 
         /* Is there an owner already? */
-        if (dev->mm) {
+        if (vhost_dev_has_owner(dev)) {
                 err = -EBUSY;
                 goto err_mm;
         }
diff --git a/drivers/vhost/vhost.h b/drivers/vhost/vhost.h
index a7ad63592987..64adcf99ff33 100644
--- a/drivers/vhost/vhost.h
+++ b/drivers/vhost/vhost.h
@@ -133,6 +133,7 @@ struct vhost_dev {
 
 long vhost_dev_init(struct vhost_dev *, struct vhost_virtqueue **vqs, int nvqs);
 long vhost_dev_set_owner(struct vhost_dev *dev);
+bool vhost_dev_has_owner(struct vhost_dev *dev);
 long vhost_dev_check_owner(struct vhost_dev *);
 struct vhost_memory *vhost_dev_reset_owner_prepare(void);
 void vhost_dev_reset_owner(struct vhost_dev *, struct vhost_memory *);
diff --git a/drivers/video/atmel_lcdfb.c b/drivers/video/atmel_lcdfb.c
index 540909de6247..effdb373b8db 100644
--- a/drivers/video/atmel_lcdfb.c
+++ b/drivers/video/atmel_lcdfb.c
@@ -223,8 +223,14 @@ static void init_backlight(struct atmel_lcdfb_info *sinfo)
 
 static void exit_backlight(struct atmel_lcdfb_info *sinfo)
 {
-        if (sinfo->backlight)
-                backlight_device_unregister(sinfo->backlight);
+        if (!sinfo->backlight)
+                return;
+
+        if (sinfo->backlight->ops) {
+                sinfo->backlight->props.power = FB_BLANK_POWERDOWN;
+                sinfo->backlight->ops->update_status(sinfo->backlight);
+        }
+        backlight_device_unregister(sinfo->backlight);
 }
 
 #else
@@ -461,8 +467,11 @@ static int atmel_lcdfb_check_var(struct fb_var_screeninfo *var,
         if (info->fix.smem_len) {
                 unsigned int smem_len = (var->xres_virtual * var->yres_virtual
                                          * ((var->bits_per_pixel + 7) / 8));
-                if (smem_len > info->fix.smem_len)
+                if (smem_len > info->fix.smem_len) {
+                        dev_err(dev, "Frame buffer is too small (%u) for screen size (need at least %u)\n",
+                                info->fix.smem_len, smem_len);
                         return -EINVAL;
+                }
         }
 
         /* Saturate vertical and horizontal timings at maximum values */
diff --git a/drivers/video/omap2/dss/core.c b/drivers/video/omap2/dss/core.c
index 60cc6fee6548..c9c2252e3719 100644
--- a/drivers/video/omap2/dss/core.c
+++ b/drivers/video/omap2/dss/core.c
@@ -53,6 +53,8 @@ static char *def_disp_name;
 module_param_named(def_disp, def_disp_name, charp, 0);
 MODULE_PARM_DESC(def_disp, "default display name");
 
+static bool dss_initialized;
+
 const char *omapdss_get_default_display_name(void)
 {
         return core.default_display_name;
@@ -66,6 +68,12 @@ enum omapdss_version omapdss_get_version(void)
 }
 EXPORT_SYMBOL(omapdss_get_version);
 
+bool omapdss_is_initialized(void)
+{
+        return dss_initialized;
+}
+EXPORT_SYMBOL(omapdss_is_initialized);
+
 struct platform_device *dss_get_core_pdev(void)
 {
         return core.pdev;
@@ -603,6 +611,8 @@ static int __init omap_dss_init(void)
                 return r;
         }
 
+        dss_initialized = true;
+
         return 0;
 }
 
@@ -633,7 +643,15 @@ static int __init omap_dss_init(void)
 
 static int __init omap_dss_init2(void)
 {
-        return omap_dss_register_drivers();
+        int r;
+
+        r = omap_dss_register_drivers();
+        if (r)
+                return r;
+
+        dss_initialized = true;
+
+        return 0;
 }
 
 core_initcall(omap_dss_init);
diff --git a/drivers/video/omap2/omapfb/omapfb-main.c b/drivers/video/omap2/omapfb/omapfb-main.c
index c84bb8a4d0c4..856917b33616 100644
--- a/drivers/video/omap2/omapfb/omapfb-main.c
+++ b/drivers/video/omap2/omapfb/omapfb-main.c
@@ -2416,6 +2416,9 @@ static int omapfb_probe(struct platform_device *pdev)
 
         DBG("omapfb_probe\n");
 
+        if (omapdss_is_initialized() == false)
+                return -EPROBE_DEFER;
+
         if (pdev->num_resources != 0) {
                 dev_err(&pdev->dev, "probed for an unknown device\n");
                 r = -ENODEV;
diff --git a/drivers/video/ps3fb.c b/drivers/video/ps3fb.c
index d9f08c653d62..dbfe2c18a434 100644
--- a/drivers/video/ps3fb.c
+++ b/drivers/video/ps3fb.c
@@ -710,7 +710,7 @@ static int ps3fb_mmap(struct fb_info *info, struct vm_area_struct *vma)
         r = vm_iomap_memory(vma, info->fix.smem_start, info->fix.smem_len);
 
         dev_dbg(info->device, "ps3fb: mmap framebuffer P(%lx)->V(%lx)\n",
-                info->fix.smem_start + vma->vm_pgoff << PAGE_SHIFT,
+                info->fix.smem_start + (vma->vm_pgoff << PAGE_SHIFT),
                 vma->vm_start);
 
         return r;
diff --git a/drivers/watchdog/coh901327_wdt.c b/drivers/watchdog/coh901327_wdt.c
index b9b8a8be6f12..4bd070f524e5 100644
--- a/drivers/watchdog/coh901327_wdt.c
+++ b/drivers/watchdog/coh901327_wdt.c
@@ -354,9 +354,9 @@ static int __init coh901327_probe(struct platform_device *pdev)
 
         clk_disable(clk);
 
-        if (margin < 1 || margin > 327)
-                margin = 60;
-        coh901327_wdt.timeout = margin;
+        ret = watchdog_init_timeout(&coh901327_wdt, margin, &pdev->dev);
+        if (ret < 0)
+                coh901327_wdt.timeout = 60;
 
         ret = watchdog_register_device(&coh901327_wdt);
         if (ret == 0)
@@ -441,10 +441,16 @@ void coh901327_watchdog_reset(void)
         /* Return and await doom */
 }
 
+static const struct of_device_id coh901327_dt_match[] = {
+        { .compatible = "stericsson,coh901327" },
+        {},
+};
+
 static struct platform_driver coh901327_driver = {
         .driver = {
                 .owner  = THIS_MODULE,
                 .name   = "coh901327_wdog",
+                .of_match_table = coh901327_dt_match,
         },
         .remove         = __exit_p(coh901327_remove),
         .suspend        = coh901327_suspend,
diff --git a/drivers/xen/tmem.c b/drivers/xen/tmem.c
index 18e8bd8fa947..0f0493c63371 100644
--- a/drivers/xen/tmem.c
+++ b/drivers/xen/tmem.c
@@ -41,6 +41,8 @@ module_param(selfballooning, bool, S_IRUGO);
 #ifdef CONFIG_FRONTSWAP
 static bool frontswap __read_mostly = true;
 module_param(frontswap, bool, S_IRUGO);
+#else /* CONFIG_FRONTSWAP */
+#define frontswap (0)
 #endif /* CONFIG_FRONTSWAP */
 
 #ifdef CONFIG_XEN_SELFBALLOONING
@@ -377,10 +379,10 @@ static int xen_tmem_init(void)
 #ifdef CONFIG_FRONTSWAP
         if (tmem_enabled && frontswap) {
                 char *s = "";
-                struct frontswap_ops *old_ops =
-                        frontswap_register_ops(&tmem_frontswap_ops);
+                struct frontswap_ops *old_ops;
 
                 tmem_frontswap_poolid = -1;
+                old_ops = frontswap_register_ops(&tmem_frontswap_ops);
                 if (IS_ERR(old_ops) || old_ops) {
                         if (IS_ERR(old_ops))
                                 return PTR_ERR(old_ops);
diff --git a/drivers/xen/xen-pciback/pci_stub.c b/drivers/xen/xen-pciback/pci_stub.c
index a2278ba7fb27..4e8ba38aa0c9 100644
--- a/drivers/xen/xen-pciback/pci_stub.c
+++ b/drivers/xen/xen-pciback/pci_stub.c
@@ -106,7 +106,7 @@ static void pcistub_device_release(struct kref *kref)
         else
                 pci_restore_state(dev);
 
-        if (pci_find_capability(dev, PCI_CAP_ID_MSIX)) {
+        if (dev->msix_cap) {
                 struct physdev_pci_device ppdev = {
                         .seg = pci_domain_nr(dev->bus),
                         .bus = dev->bus->number,
@@ -371,7 +371,7 @@ static int pcistub_init_device(struct pci_dev *dev)
         if (err)
                 goto config_release;
 
-        if (pci_find_capability(dev, PCI_CAP_ID_MSIX)) {
+        if (dev->msix_cap) {
                 struct physdev_pci_device ppdev = {
                         .seg = pci_domain_nr(dev->bus),
                         .bus = dev->bus->number,
diff --git a/drivers/xen/xenbus/xenbus_client.c b/drivers/xen/xenbus/xenbus_client.c
index 61786be9138b..ec097d6f964d 100644
--- a/drivers/xen/xenbus/xenbus_client.c
+++ b/drivers/xen/xenbus/xenbus_client.c
@@ -534,7 +534,7 @@ static int xenbus_map_ring_valloc_hvm(struct xenbus_device *dev,
 
         err = xenbus_map_ring(dev, gnt_ref, &node->handle, addr);
         if (err)
-                goto out_err;
+                goto out_err_free_ballooned_pages;
 
         spin_lock(&xenbus_valloc_lock);
         list_add(&node->next, &xenbus_valloc_pages);
@@ -543,8 +543,9 @@ static int xenbus_map_ring_valloc_hvm(struct xenbus_device *dev,
         *vaddr = addr;
         return 0;
 
- out_err:
+ out_err_free_ballooned_pages:
         free_xenballooned_pages(1, &node->page);
+ out_err:
         kfree(node);
         return err;
 }
diff --git a/drivers/xen/xenbus/xenbus_comms.h b/drivers/xen/xenbus/xenbus_comms.h
index c8abd3b8a6c4..e74f9c1fbd80 100644
--- a/drivers/xen/xenbus/xenbus_comms.h
+++ b/drivers/xen/xenbus/xenbus_comms.h
@@ -45,6 +45,7 @@ int xb_wait_for_data_to_read(void);
 int xs_input_avail(void);
 extern struct xenstore_domain_interface *xen_store_interface;
 extern int xen_store_evtchn;
+extern enum xenstore_init xen_store_domain_type;
 
 extern const struct file_operations xen_xenbus_fops;
 
diff --git a/drivers/xen/xenbus/xenbus_probe.c b/drivers/xen/xenbus/xenbus_probe.c
index 3325884c693f..56cfaaa9d006 100644
--- a/drivers/xen/xenbus/xenbus_probe.c
+++ b/drivers/xen/xenbus/xenbus_probe.c
@@ -69,6 +69,9 @@ EXPORT_SYMBOL_GPL(xen_store_evtchn);
 struct xenstore_domain_interface *xen_store_interface;
 EXPORT_SYMBOL_GPL(xen_store_interface);
 
+enum xenstore_init xen_store_domain_type;
+EXPORT_SYMBOL_GPL(xen_store_domain_type);
+
 static unsigned long xen_store_mfn;
 
 static BLOCKING_NOTIFIER_HEAD(xenstore_chain);
@@ -719,17 +722,11 @@ static int __init xenstored_local_init(void)
         return err;
 }
 
-enum xenstore_init {
-        UNKNOWN,
-        PV,
-        HVM,
-        LOCAL,
-};
 static int __init xenbus_init(void)
 {
         int err = 0;
-        enum xenstore_init usage = UNKNOWN;
         uint64_t v = 0;
+        xen_store_domain_type = XS_UNKNOWN;
 
         if (!xen_domain())
                 return -ENODEV;
@@ -737,29 +734,29 @@ static int __init xenbus_init(void)
         xenbus_ring_ops_init();
 
         if (xen_pv_domain())
-                usage = PV;
+                xen_store_domain_type = XS_PV;
         if (xen_hvm_domain())
-                usage = HVM;
+                xen_store_domain_type = XS_HVM;
         if (xen_hvm_domain() && xen_initial_domain())
-                usage = LOCAL;
+                xen_store_domain_type = XS_LOCAL;
         if (xen_pv_domain() && !xen_start_info->store_evtchn)
-                usage = LOCAL;
+                xen_store_domain_type = XS_LOCAL;
         if (xen_pv_domain() && xen_start_info->store_evtchn)
                 xenstored_ready = 1;
 
-        switch (usage) {
-        case LOCAL:
+        switch (xen_store_domain_type) {
+        case XS_LOCAL:
                 err = xenstored_local_init();
                 if (err)
                         goto out_error;
                 xen_store_interface = mfn_to_virt(xen_store_mfn);
                 break;
-        case PV:
+        case XS_PV:
                 xen_store_evtchn = xen_start_info->store_evtchn;
                 xen_store_mfn = xen_start_info->store_mfn;
                 xen_store_interface = mfn_to_virt(xen_store_mfn);
                 break;
-        case HVM:
+        case XS_HVM:
                 err = hvm_get_parameter(HVM_PARAM_STORE_EVTCHN, &v);
                 if (err)
                         goto out_error;
diff --git a/drivers/xen/xenbus/xenbus_probe.h b/drivers/xen/xenbus/xenbus_probe.h
index bb4f92ed8730..146f857a36f8 100644
--- a/drivers/xen/xenbus/xenbus_probe.h
+++ b/drivers/xen/xenbus/xenbus_probe.h
@@ -47,6 +47,13 @@ struct xen_bus_type {
         struct bus_type bus;
 };
 
+enum xenstore_init {
+        XS_UNKNOWN,
+        XS_PV,
+        XS_HVM,
+        XS_LOCAL,
+};
+
 extern struct device_attribute xenbus_dev_attrs[];
 
 extern int xenbus_match(struct device *_dev, struct device_driver *_drv);
diff --git a/drivers/xen/xenbus/xenbus_probe_frontend.c b/drivers/xen/xenbus/xenbus_probe_frontend.c
index 3159a37d966d..a7e25073de19 100644
--- a/drivers/xen/xenbus/xenbus_probe_frontend.c
+++ b/drivers/xen/xenbus/xenbus_probe_frontend.c
@@ -29,6 +29,8 @@
 #include "xenbus_probe.h"
 
 
+static struct workqueue_struct *xenbus_frontend_wq;
+
 /* device/<type>/<id> => <type>-<id> */
 static int frontend_bus_id(char bus_id[XEN_BUS_ID_SIZE], const char *nodename)
 {
@@ -89,9 +91,40 @@ static void backend_changed(struct xenbus_watch *watch,
         xenbus_otherend_changed(watch, vec, len, 1);
 }
 
+static void xenbus_frontend_delayed_resume(struct work_struct *w)
+{
+        struct xenbus_device *xdev = container_of(w, struct xenbus_device, work);
+
+        xenbus_dev_resume(&xdev->dev);
+}
+
+static int xenbus_frontend_dev_resume(struct device *dev)
+{
+        /*
+         * If xenstored is running in this domain, we cannot access the backend
+         * state at the moment, so we need to defer xenbus_dev_resume
+         */
+        if (xen_store_domain_type == XS_LOCAL) {
+                struct xenbus_device *xdev = to_xenbus_device(dev);
+
+                if (!xenbus_frontend_wq) {
+                        pr_err("%s: no workqueue to process delayed resume\n",
+                               xdev->nodename);
+                        return -EFAULT;
+                }
+
+                INIT_WORK(&xdev->work, xenbus_frontend_delayed_resume);
+                queue_work(xenbus_frontend_wq, &xdev->work);
+
+                return 0;
+        }
+
+        return xenbus_dev_resume(dev);
+}
+
 static const struct dev_pm_ops xenbus_pm_ops = {
         .suspend        = xenbus_dev_suspend,
-        .resume         = xenbus_dev_resume,
+        .resume         = xenbus_frontend_dev_resume,
         .freeze         = xenbus_dev_suspend,
         .thaw           = xenbus_dev_cancel,
         .restore        = xenbus_dev_resume,
@@ -440,6 +473,8 @@ static int __init xenbus_probe_frontend_init(void)
 
         register_xenstore_notifier(&xenstore_notifier);
 
+        xenbus_frontend_wq = create_workqueue("xenbus_frontend");
+
         return 0;
 }
 subsys_initcall(xenbus_probe_frontend_init);