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-rw-r--r--drivers/gpio/Kconfig4
-rw-r--r--drivers/gpio/Makefile1
-rw-r--r--drivers/gpio/gpio-tb10x.c328
-rw-r--r--drivers/gpio/gpiolib-of.c63
-rw-r--r--drivers/gpio/gpiolib.c47
-rw-r--r--drivers/pinctrl/Kconfig54
-rw-r--r--drivers/pinctrl/Makefile8
-rw-r--r--drivers/pinctrl/core.c14
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-370.c2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-armada-xp.c2
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-dove.c4
-rw-r--r--drivers/pinctrl/mvebu/pinctrl-kirkwood.c2
-rw-r--r--drivers/pinctrl/pinctrl-adi2-bf54x.c592
-rw-r--r--drivers/pinctrl/pinctrl-adi2-bf60x.c521
-rw-r--r--drivers/pinctrl/pinctrl-adi2.c1164
-rw-r--r--drivers/pinctrl/pinctrl-adi2.h75
-rw-r--r--drivers/pinctrl/pinctrl-as3722.c630
-rw-r--r--drivers/pinctrl/pinctrl-at91.c37
-rw-r--r--drivers/pinctrl/pinctrl-exynos5440.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx.c6
-rw-r--r--drivers/pinctrl/pinctrl-imx1-core.c653
-rw-r--r--drivers/pinctrl/pinctrl-imx1.h73
-rw-r--r--drivers/pinctrl/pinctrl-imx27.c477
-rw-r--r--drivers/pinctrl/pinctrl-imx35.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx50.c426
-rw-r--r--drivers/pinctrl/pinctrl-imx51.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx53.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx6dl.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx6q.c2
-rw-r--r--drivers/pinctrl/pinctrl-imx6sl.c2
-rw-r--r--drivers/pinctrl/pinctrl-palmas.c20
-rw-r--r--drivers/pinctrl/pinctrl-rockchip.c292
-rw-r--r--drivers/pinctrl/pinctrl-samsung.c2
-rw-r--r--drivers/pinctrl/pinctrl-tb10x.c875
-rw-r--r--drivers/pinctrl/pinctrl-vf610.c2
-rw-r--r--drivers/pinctrl/pinmux.c4
-rw-r--r--drivers/pinctrl/sh-pfc/Kconfig5
-rw-r--r--drivers/pinctrl/sh-pfc/Makefile1
-rw-r--r--drivers/pinctrl/sh-pfc/core.c9
-rw-r--r--drivers/pinctrl/sh-pfc/core.h1
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c180
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c110
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c4214
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c56
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c115
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c8
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.h6
-rw-r--r--drivers/pinctrl/spear/pinctrl-plgpio.c2
48 files changed, 10967 insertions, 132 deletions
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index b6ed304863eb..661ca82814e5 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -360,6 +360,10 @@ config GPIO_GRGPIO
360 Select this to support Aeroflex Gaisler GRGPIO cores from the GRLIB 360 Select this to support Aeroflex Gaisler GRGPIO cores from the GRLIB
361 VHDL IP core library. 361 VHDL IP core library.
362 362
363config GPIO_TB10X
364 bool
365 select OF_GPIO
366
363comment "I2C GPIO expanders:" 367comment "I2C GPIO expanders:"
364 368
365config GPIO_ARIZONA 369config GPIO_ARIZONA
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 98e23ebba2cf..2931c996e71f 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -71,6 +71,7 @@ obj-$(CONFIG_GPIO_STA2X11) += gpio-sta2x11.o
71obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o 71obj-$(CONFIG_GPIO_STMPE) += gpio-stmpe.o
72obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o 72obj-$(CONFIG_GPIO_STP_XWAY) += gpio-stp-xway.o
73obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o 73obj-$(CONFIG_GPIO_SX150X) += gpio-sx150x.o
74obj-$(CONFIG_GPIO_TB10X) += gpio-tb10x.o
74obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o 75obj-$(CONFIG_GPIO_TC3589X) += gpio-tc3589x.o
75obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o 76obj-$(CONFIG_ARCH_TEGRA) += gpio-tegra.o
76obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o 77obj-$(CONFIG_GPIO_TIMBERDALE) += gpio-timberdale.o
diff --git a/drivers/gpio/gpio-tb10x.c b/drivers/gpio/gpio-tb10x.c
new file mode 100644
index 000000000000..0502b9a041a5
--- /dev/null
+++ b/drivers/gpio/gpio-tb10x.c
@@ -0,0 +1,328 @@
1/* Abilis Systems MODULE DESCRIPTION
2 *
3 * Copyright (C) Abilis Systems 2013
4 *
5 * Authors: Sascha Leuenberger <sascha.leuenberger@abilis.com>
6 * Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/kernel.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/gpio.h>
26#include <linux/slab.h>
27#include <linux/irq.h>
28#include <linux/irqdomain.h>
29#include <linux/interrupt.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/of_platform.h>
33#include <linux/of_gpio.h>
34#include <linux/spinlock.h>
35#include <linux/bitops.h>
36#include <linux/pinctrl/consumer.h>
37
38#define TB10X_GPIO_DIR_IN (0x00000000)
39#define TB10X_GPIO_DIR_OUT (0x00000001)
40#define OFFSET_TO_REG_DDR (0x00)
41#define OFFSET_TO_REG_DATA (0x04)
42#define OFFSET_TO_REG_INT_EN (0x08)
43#define OFFSET_TO_REG_CHANGE (0x0C)
44#define OFFSET_TO_REG_WRMASK (0x10)
45#define OFFSET_TO_REG_INT_TYPE (0x14)
46
47
48/**
49 * @spinlock: used for atomic read/modify/write of registers
50 * @base: register base address
51 * @domain: IRQ domain of GPIO generated interrupts managed by this controller
52 * @irq: Interrupt line of parent interrupt controller
53 * @gc: gpio_chip structure associated to this GPIO controller
54 */
55struct tb10x_gpio {
56 spinlock_t spinlock;
57 void __iomem *base;
58 struct irq_domain *domain;
59 int irq;
60 struct gpio_chip gc;
61};
62
63static inline u32 tb10x_reg_read(struct tb10x_gpio *gpio, unsigned int offs)
64{
65 return ioread32(gpio->base + offs);
66}
67
68static inline void tb10x_reg_write(struct tb10x_gpio *gpio, unsigned int offs,
69 u32 val)
70{
71 iowrite32(val, gpio->base + offs);
72}
73
74static inline void tb10x_set_bits(struct tb10x_gpio *gpio, unsigned int offs,
75 u32 mask, u32 val)
76{
77 u32 r;
78 unsigned long flags;
79
80 spin_lock_irqsave(&gpio->spinlock, flags);
81
82 r = tb10x_reg_read(gpio, offs);
83 r = (r & ~mask) | (val & mask);
84
85 tb10x_reg_write(gpio, offs, r);
86
87 spin_unlock_irqrestore(&gpio->spinlock, flags);
88}
89
90static inline struct tb10x_gpio *to_tb10x_gpio(struct gpio_chip *chip)
91{
92 return container_of(chip, struct tb10x_gpio, gc);
93}
94
95static int tb10x_gpio_direction_in(struct gpio_chip *chip, unsigned offset)
96{
97 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
98 int mask = BIT(offset);
99 int val = TB10X_GPIO_DIR_IN << offset;
100
101 tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
102
103 return 0;
104}
105
106static int tb10x_gpio_get(struct gpio_chip *chip, unsigned offset)
107{
108 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
109 int val;
110
111 val = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_DATA);
112
113 if (val & BIT(offset))
114 return 1;
115 else
116 return 0;
117}
118
119static void tb10x_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
120{
121 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
122 int mask = BIT(offset);
123 int val = value << offset;
124
125 tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DATA, mask, val);
126}
127
128static int tb10x_gpio_direction_out(struct gpio_chip *chip,
129 unsigned offset, int value)
130{
131 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
132 int mask = BIT(offset);
133 int val = TB10X_GPIO_DIR_OUT << offset;
134
135 tb10x_set_bits(tb10x_gpio, OFFSET_TO_REG_DDR, mask, val);
136
137 return 0;
138}
139
140static int tb10x_gpio_request(struct gpio_chip *chip, unsigned offset)
141{
142 return pinctrl_request_gpio(chip->base + offset);
143}
144
145static void tb10x_gpio_free(struct gpio_chip *chip, unsigned offset)
146{
147 pinctrl_free_gpio(chip->base + offset);
148}
149
150static int tb10x_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
151{
152 struct tb10x_gpio *tb10x_gpio = to_tb10x_gpio(chip);
153
154 return irq_create_mapping(tb10x_gpio->domain, offset);
155}
156
157static int tb10x_gpio_irq_set_type(struct irq_data *data, unsigned int type)
158{
159 if ((type & IRQF_TRIGGER_MASK) != IRQ_TYPE_EDGE_BOTH) {
160 pr_err("Only (both) edge triggered interrupts supported.\n");
161 return -EINVAL;
162 }
163
164 irqd_set_trigger_type(data, type);
165
166 return IRQ_SET_MASK_OK;
167}
168
169static irqreturn_t tb10x_gpio_irq_cascade(int irq, void *data)
170{
171 struct tb10x_gpio *tb10x_gpio = data;
172 u32 r = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_CHANGE);
173 u32 m = tb10x_reg_read(tb10x_gpio, OFFSET_TO_REG_INT_EN);
174 const unsigned long bits = r & m;
175 int i;
176
177 for_each_set_bit(i, &bits, 32)
178 generic_handle_irq(irq_find_mapping(tb10x_gpio->domain, i));
179
180 return IRQ_HANDLED;
181}
182
183static int tb10x_gpio_probe(struct platform_device *pdev)
184{
185 struct tb10x_gpio *tb10x_gpio;
186 struct resource *mem;
187 struct device_node *dn = pdev->dev.of_node;
188 int ret = -EBUSY;
189 u32 ngpio;
190
191 if (!dn)
192 return -EINVAL;
193
194 if (of_property_read_u32(dn, "abilis,ngpio", &ngpio))
195 return -EINVAL;
196
197 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
198 if (!mem) {
199 dev_err(&pdev->dev, "No memory resource defined.\n");
200 return -EINVAL;
201 }
202
203 tb10x_gpio = devm_kzalloc(&pdev->dev, sizeof(*tb10x_gpio), GFP_KERNEL);
204 if (tb10x_gpio == NULL)
205 return -ENOMEM;
206
207 spin_lock_init(&tb10x_gpio->spinlock);
208
209 tb10x_gpio->base = devm_ioremap_resource(&pdev->dev, mem);
210 if (IS_ERR(tb10x_gpio->base))
211 return PTR_ERR(tb10x_gpio->base);
212
213 tb10x_gpio->gc.label = of_node_full_name(dn);
214 tb10x_gpio->gc.dev = &pdev->dev;
215 tb10x_gpio->gc.owner = THIS_MODULE;
216 tb10x_gpio->gc.direction_input = tb10x_gpio_direction_in;
217 tb10x_gpio->gc.get = tb10x_gpio_get;
218 tb10x_gpio->gc.direction_output = tb10x_gpio_direction_out;
219 tb10x_gpio->gc.set = tb10x_gpio_set;
220 tb10x_gpio->gc.request = tb10x_gpio_request;
221 tb10x_gpio->gc.free = tb10x_gpio_free;
222 tb10x_gpio->gc.base = -1;
223 tb10x_gpio->gc.ngpio = ngpio;
224 tb10x_gpio->gc.can_sleep = 0;
225
226
227 ret = gpiochip_add(&tb10x_gpio->gc);
228 if (ret < 0) {
229 dev_err(&pdev->dev, "Could not add gpiochip.\n");
230 goto fail_gpiochip_registration;
231 }
232
233 platform_set_drvdata(pdev, tb10x_gpio);
234
235 if (of_find_property(dn, "interrupt-controller", NULL)) {
236 struct irq_chip_generic *gc;
237
238 ret = platform_get_irq(pdev, 0);
239 if (ret < 0) {
240 dev_err(&pdev->dev, "No interrupt specified.\n");
241 goto fail_get_irq;
242 }
243
244 tb10x_gpio->gc.to_irq = tb10x_gpio_to_irq;
245 tb10x_gpio->irq = ret;
246
247 ret = devm_request_irq(&pdev->dev, ret, tb10x_gpio_irq_cascade,
248 IRQF_TRIGGER_NONE | IRQF_SHARED,
249 dev_name(&pdev->dev), tb10x_gpio);
250 if (ret != 0)
251 goto fail_request_irq;
252
253 tb10x_gpio->domain = irq_domain_add_linear(dn,
254 tb10x_gpio->gc.ngpio,
255 &irq_generic_chip_ops, NULL);
256 if (!tb10x_gpio->domain) {
257 ret = -ENOMEM;
258 goto fail_irq_domain;
259 }
260
261 ret = irq_alloc_domain_generic_chips(tb10x_gpio->domain,
262 tb10x_gpio->gc.ngpio, 1, tb10x_gpio->gc.label,
263 handle_edge_irq, IRQ_NOREQUEST, IRQ_NOPROBE,
264 IRQ_GC_INIT_MASK_CACHE);
265 if (ret)
266 goto fail_irq_domain;
267
268 gc = tb10x_gpio->domain->gc->gc[0];
269 gc->reg_base = tb10x_gpio->base;
270 gc->chip_types[0].type = IRQ_TYPE_EDGE_BOTH;
271 gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;
272 gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;
273 gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;
274 gc->chip_types[0].chip.irq_set_type = tb10x_gpio_irq_set_type;
275 gc->chip_types[0].regs.ack = OFFSET_TO_REG_CHANGE;
276 gc->chip_types[0].regs.mask = OFFSET_TO_REG_INT_EN;
277 }
278
279 return 0;
280
281fail_irq_domain:
282fail_request_irq:
283fail_get_irq:
284 gpiochip_remove(&tb10x_gpio->gc);
285fail_gpiochip_registration:
286fail_ioremap:
287 return ret;
288}
289
290static int __exit tb10x_gpio_remove(struct platform_device *pdev)
291{
292 struct tb10x_gpio *tb10x_gpio = platform_get_drvdata(pdev);
293 int ret;
294
295 if (tb10x_gpio->gc.to_irq) {
296 irq_remove_generic_chip(tb10x_gpio->domain->gc->gc[0],
297 BIT(tb10x_gpio->gc.ngpio) - 1, 0, 0);
298 kfree(tb10x_gpio->domain->gc);
299 irq_domain_remove(tb10x_gpio->domain);
300 free_irq(tb10x_gpio->irq, tb10x_gpio);
301 }
302 ret = gpiochip_remove(&tb10x_gpio->gc);
303 if (ret)
304 return ret;
305
306 return 0;
307}
308
309static const struct of_device_id tb10x_gpio_dt_ids[] = {
310 { .compatible = "abilis,tb10x-gpio" },
311 { }
312};
313MODULE_DEVICE_TABLE(of, tb10x_gpio_dt_ids);
314
315static struct platform_driver tb10x_gpio_driver = {
316 .probe = tb10x_gpio_probe,
317 .remove = tb10x_gpio_remove,
318 .driver = {
319 .name = "tb10x-gpio",
320 .of_match_table = of_match_ptr(tb10x_gpio_dt_ids),
321 .owner = THIS_MODULE,
322 }
323};
324
325module_platform_driver(tb10x_gpio_driver);
326MODULE_LICENSE("GPL");
327MODULE_DESCRIPTION("tb10x gpio.");
328MODULE_VERSION("0.0.1");
diff --git a/drivers/gpio/gpiolib-of.c b/drivers/gpio/gpiolib-of.c
index 0dfaf20e4dad..e78760921bd7 100644
--- a/drivers/gpio/gpiolib-of.c
+++ b/drivers/gpio/gpiolib-of.c
@@ -190,10 +190,15 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
190 struct of_phandle_args pinspec; 190 struct of_phandle_args pinspec;
191 struct pinctrl_dev *pctldev; 191 struct pinctrl_dev *pctldev;
192 int index = 0, ret; 192 int index = 0, ret;
193 const char *name;
194 static const char group_names_propname[] = "gpio-ranges-group-names";
195 struct property *group_names;
193 196
194 if (!np) 197 if (!np)
195 return; 198 return;
196 199
200 group_names = of_find_property(np, group_names_propname, NULL);
201
197 for (;; index++) { 202 for (;; index++) {
198 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3, 203 ret = of_parse_phandle_with_fixed_args(np, "gpio-ranges", 3,
199 index, &pinspec); 204 index, &pinspec);
@@ -204,14 +209,56 @@ static void of_gpiochip_add_pin_range(struct gpio_chip *chip)
204 if (!pctldev) 209 if (!pctldev)
205 break; 210 break;
206 211
207 ret = gpiochip_add_pin_range(chip, 212 if (pinspec.args[2]) {
208 pinctrl_dev_get_devname(pctldev), 213 if (group_names) {
209 pinspec.args[0], 214 ret = of_property_read_string_index(np,
210 pinspec.args[1], 215 group_names_propname,
211 pinspec.args[2]); 216 index, &name);
212 217 if (strlen(name)) {
213 if (ret) 218 pr_err("%s: Group name of numeric GPIO ranges must be the empty string.\n",
214 break; 219 np->full_name);
220 break;
221 }
222 }
223 /* npins != 0: linear range */
224 ret = gpiochip_add_pin_range(chip,
225 pinctrl_dev_get_devname(pctldev),
226 pinspec.args[0],
227 pinspec.args[1],
228 pinspec.args[2]);
229 if (ret)
230 break;
231 } else {
232 /* npins == 0: special range */
233 if (pinspec.args[1]) {
234 pr_err("%s: Illegal gpio-range format.\n",
235 np->full_name);
236 break;
237 }
238
239 if (!group_names) {
240 pr_err("%s: GPIO group range requested but no %s property.\n",
241 np->full_name, group_names_propname);
242 break;
243 }
244
245 ret = of_property_read_string_index(np,
246 group_names_propname,
247 index, &name);
248 if (ret)
249 break;
250
251 if (!strlen(name)) {
252 pr_err("%s: Group name of GPIO group range cannot be the empty string.\n",
253 np->full_name);
254 break;
255 }
256
257 ret = gpiochip_add_pingroup_range(chip, pctldev,
258 pinspec.args[0], name);
259 if (ret)
260 break;
261 }
215 } 262 }
216} 263}
217 264
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index dadbac277267..4a34ca9c1768 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1320,6 +1320,53 @@ EXPORT_SYMBOL_GPL(gpiochip_find);
1320#ifdef CONFIG_PINCTRL 1320#ifdef CONFIG_PINCTRL
1321 1321
1322/** 1322/**
1323 * gpiochip_add_pingroup_range() - add a range for GPIO <-> pin mapping
1324 * @chip: the gpiochip to add the range for
1325 * @pinctrl: the dev_name() of the pin controller to map to
1326 * @gpio_offset: the start offset in the current gpio_chip number space
1327 * @pin_group: name of the pin group inside the pin controller
1328 */
1329int gpiochip_add_pingroup_range(struct gpio_chip *chip,
1330 struct pinctrl_dev *pctldev,
1331 unsigned int gpio_offset, const char *pin_group)
1332{
1333 struct gpio_pin_range *pin_range;
1334 int ret;
1335
1336 pin_range = kzalloc(sizeof(*pin_range), GFP_KERNEL);
1337 if (!pin_range) {
1338 pr_err("%s: GPIO chip: failed to allocate pin ranges\n",
1339 chip->label);
1340 return -ENOMEM;
1341 }
1342
1343 /* Use local offset as range ID */
1344 pin_range->range.id = gpio_offset;
1345 pin_range->range.gc = chip;
1346 pin_range->range.name = chip->label;
1347 pin_range->range.base = chip->base + gpio_offset;
1348 pin_range->pctldev = pctldev;
1349
1350 ret = pinctrl_get_group_pins(pctldev, pin_group,
1351 &pin_range->range.pins,
1352 &pin_range->range.npins);
1353 if (ret < 0)
1354 return ret;
1355
1356 pinctrl_add_gpio_range(pctldev, &pin_range->range);
1357
1358 pr_debug("GPIO chip %s: created GPIO range %d->%d ==> %s PINGRP %s\n",
1359 chip->label, gpio_offset,
1360 gpio_offset + pin_range->range.npins - 1,
1361 pinctrl_dev_get_devname(pctldev), pin_group);
1362
1363 list_add_tail(&pin_range->node, &chip->pin_ranges);
1364
1365 return 0;
1366}
1367EXPORT_SYMBOL_GPL(gpiochip_add_pingroup_range);
1368
1369/**
1323 * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping 1370 * gpiochip_add_pin_range() - add a range for GPIO <-> pin mapping
1324 * @chip: the gpiochip to add the range for 1371 * @chip: the gpiochip to add the range for
1325 * @pinctrl_name: the dev_name() of the pin controller to map to 1372 * @pinctrl_name: the dev_name() of the pin controller to map to
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index b6e864e8c9e8..33f9dc1f14fd 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -49,6 +49,35 @@ config PINCTRL_AB8505
49 bool "AB8505 pin controller driver" 49 bool "AB8505 pin controller driver"
50 depends on PINCTRL_ABX500 && ARCH_U8500 50 depends on PINCTRL_ABX500 && ARCH_U8500
51 51
52config PINCTRL_ADI2
53 bool "ADI pin controller driver"
54 depends on BLACKFIN
55 select PINMUX
56 select IRQ_DOMAIN
57 help
58 This is the pin controller and gpio driver for ADI BF54x, BF60x and
59 future processors. This option is selected automatically when specific
60 machine and arch are selected to build.
61
62config PINCTRL_AS3722
63 bool "Pinctrl and GPIO driver for ams AS3722 PMIC"
64 depends on MFD_AS3722 && GPIOLIB
65 select PINMUX
66 select GENERIC_PINCONF
67 help
68 AS3722 device supports the configuration of GPIO pins for different
69 functionality. This driver supports the pinmux, push-pull and
70 open drain configuration for the GPIO pins of AS3722 devices. It also
71 supports the GPIO functionality through gpiolib.
72
73config PINCTRL_BF54x
74 def_bool y if BF54x
75 select PINCTRL_ADI2
76
77config PINCTRL_BF60x
78 def_bool y if BF60x
79 select PINCTRL_ADI2
80
52config PINCTRL_AT91 81config PINCTRL_AT91
53 bool "AT91 pinctrl driver" 82 bool "AT91 pinctrl driver"
54 depends on OF 83 depends on OF
@@ -80,6 +109,19 @@ config PINCTRL_IMX
80 select PINMUX 109 select PINMUX
81 select PINCONF 110 select PINCONF
82 111
112config PINCTRL_IMX1_CORE
113 bool
114 select PINMUX
115 select PINCONF
116
117config PINCTRL_IMX27
118 bool "IMX27 pinctrl driver"
119 depends on OF
120 depends on SOC_IMX27
121 select PINCTRL_IMX1_CORE
122 help
123 Say Y here to enable the imx27 pinctrl driver
124
83config PINCTRL_IMX35 125config PINCTRL_IMX35
84 bool "IMX35 pinctrl driver" 126 bool "IMX35 pinctrl driver"
85 depends on OF 127 depends on OF
@@ -88,6 +130,14 @@ config PINCTRL_IMX35
88 help 130 help
89 Say Y here to enable the imx35 pinctrl driver 131 Say Y here to enable the imx35 pinctrl driver
90 132
133config PINCTRL_IMX50
134 bool "IMX50 pinctrl driver"
135 depends on OF
136 depends on SOC_IMX50
137 select PINCTRL_IMX
138 help
139 Say Y here to enable the imx50 pinctrl driver
140
91config PINCTRL_IMX51 141config PINCTRL_IMX51
92 bool "IMX51 pinctrl driver" 142 bool "IMX51 pinctrl driver"
93 depends on OF 143 depends on OF
@@ -292,6 +342,10 @@ config PINCTRL_XWAY
292 depends on SOC_TYPE_XWAY 342 depends on SOC_TYPE_XWAY
293 depends on PINCTRL_LANTIQ 343 depends on PINCTRL_LANTIQ
294 344
345config PINCTRL_TB10X
346 bool
347 depends on ARC_PLAT_TB10X
348
295endmenu 349endmenu
296 350
297endif 351endif
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 496d9bf9e1b9..4f7be2921aa5 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -14,11 +14,18 @@ obj-$(CONFIG_PINCTRL_AB8500) += pinctrl-ab8500.o
14obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o 14obj-$(CONFIG_PINCTRL_AB8540) += pinctrl-ab8540.o
15obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o 15obj-$(CONFIG_PINCTRL_AB9540) += pinctrl-ab9540.o
16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o 16obj-$(CONFIG_PINCTRL_AB8505) += pinctrl-ab8505.o
17obj-$(CONFIG_PINCTRL_ADI2) += pinctrl-adi2.o
18obj-$(CONFIG_PINCTRL_AS3722) += pinctrl-as3722.o
19obj-$(CONFIG_PINCTRL_BF54x) += pinctrl-adi2-bf54x.o
20obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
17obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 21obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
18obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 22obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
19obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 23obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
20obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o 24obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
25obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
26obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
21obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o 27obj-$(CONFIG_PINCTRL_IMX35) += pinctrl-imx35.o
28obj-$(CONFIG_PINCTRL_IMX50) += pinctrl-imx50.o
22obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o 29obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
23obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o 30obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
24obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o 31obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
@@ -52,6 +59,7 @@ obj-$(CONFIG_PINCTRL_S3C24XX) += pinctrl-s3c24xx.o
52obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o 59obj-$(CONFIG_PINCTRL_S3C64XX) += pinctrl-s3c64xx.o
53obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o 60obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
54obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o 61obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
62obj-$(CONFIG_PINCTRL_TB10X) += pinctrl-tb10x.o
55obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o 63obj-$(CONFIG_PINCTRL_ST) += pinctrl-st.o
56obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o 64obj-$(CONFIG_PINCTRL_VF610) += pinctrl-vf610.o
57 65
diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c
index 92f86ab30a13..5ee61a470016 100644
--- a/drivers/pinctrl/core.c
+++ b/drivers/pinctrl/core.c
@@ -462,6 +462,20 @@ struct pinctrl_dev *pinctrl_find_and_add_gpio_range(const char *devname,
462} 462}
463EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range); 463EXPORT_SYMBOL_GPL(pinctrl_find_and_add_gpio_range);
464 464
465int pinctrl_get_group_pins(struct pinctrl_dev *pctldev, const char *pin_group,
466 const unsigned **pins, unsigned *num_pins)
467{
468 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
469 int gs;
470
471 gs = pinctrl_get_group_selector(pctldev, pin_group);
472 if (gs < 0)
473 return gs;
474
475 return pctlops->get_group_pins(pctldev, gs, pins, num_pins);
476}
477EXPORT_SYMBOL_GPL(pinctrl_get_group_pins);
478
465/** 479/**
466 * pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin 480 * pinctrl_find_gpio_range_from_pin() - locate the GPIO range for a pin
467 * @pctldev: the pin controller device to look in 481 * @pctldev: the pin controller device to look in
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-370.c b/drivers/pinctrl/mvebu/pinctrl-armada-370.c
index 48e21a229483..ae1f760cbdd2 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-370.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-370.c
@@ -408,7 +408,7 @@ static struct platform_driver armada_370_pinctrl_driver = {
408 .driver = { 408 .driver = {
409 .name = "armada-370-pinctrl", 409 .name = "armada-370-pinctrl",
410 .owner = THIS_MODULE, 410 .owner = THIS_MODULE,
411 .of_match_table = of_match_ptr(armada_370_pinctrl_of_match), 411 .of_match_table = armada_370_pinctrl_of_match,
412 }, 412 },
413 .probe = armada_370_pinctrl_probe, 413 .probe = armada_370_pinctrl_probe,
414 .remove = armada_370_pinctrl_remove, 414 .remove = armada_370_pinctrl_remove,
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
index ab5dc04b3e8a..843a51f9d129 100644
--- a/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
+++ b/drivers/pinctrl/mvebu/pinctrl-armada-xp.c
@@ -455,7 +455,7 @@ static struct platform_driver armada_xp_pinctrl_driver = {
455 .driver = { 455 .driver = {
456 .name = "armada-xp-pinctrl", 456 .name = "armada-xp-pinctrl",
457 .owner = THIS_MODULE, 457 .owner = THIS_MODULE,
458 .of_match_table = of_match_ptr(armada_xp_pinctrl_of_match), 458 .of_match_table = armada_xp_pinctrl_of_match,
459 }, 459 },
460 .probe = armada_xp_pinctrl_probe, 460 .probe = armada_xp_pinctrl_probe,
461 .remove = armada_xp_pinctrl_remove, 461 .remove = armada_xp_pinctrl_remove,
diff --git a/drivers/pinctrl/mvebu/pinctrl-dove.c b/drivers/pinctrl/mvebu/pinctrl-dove.c
index 29f7e4fc7ca5..47268393af34 100644
--- a/drivers/pinctrl/mvebu/pinctrl-dove.c
+++ b/drivers/pinctrl/mvebu/pinctrl-dove.c
@@ -335,7 +335,7 @@ static int dove_twsi_ctrl_set(struct mvebu_mpp_ctrl *ctrl,
335 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2); 335 unsigned long gcfg2 = readl(DOVE_GLOBAL_CONFIG_2);
336 336
337 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1; 337 gcfg1 &= ~DOVE_TWSI_ENABLE_OPTION1;
338 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION2); 338 gcfg2 &= ~(DOVE_TWSI_ENABLE_OPTION2 | DOVE_TWSI_ENABLE_OPTION3);
339 339
340 switch (config) { 340 switch (config) {
341 case 1: 341 case 1:
@@ -806,7 +806,7 @@ static struct platform_driver dove_pinctrl_driver = {
806 .driver = { 806 .driver = {
807 .name = "dove-pinctrl", 807 .name = "dove-pinctrl",
808 .owner = THIS_MODULE, 808 .owner = THIS_MODULE,
809 .of_match_table = of_match_ptr(dove_pinctrl_of_match), 809 .of_match_table = dove_pinctrl_of_match,
810 }, 810 },
811 .probe = dove_pinctrl_probe, 811 .probe = dove_pinctrl_probe,
812 .remove = dove_pinctrl_remove, 812 .remove = dove_pinctrl_remove,
diff --git a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
index cdd483df673e..6b504b5935a5 100644
--- a/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
+++ b/drivers/pinctrl/mvebu/pinctrl-kirkwood.c
@@ -471,7 +471,7 @@ static struct platform_driver kirkwood_pinctrl_driver = {
471 .driver = { 471 .driver = {
472 .name = "kirkwood-pinctrl", 472 .name = "kirkwood-pinctrl",
473 .owner = THIS_MODULE, 473 .owner = THIS_MODULE,
474 .of_match_table = of_match_ptr(kirkwood_pinctrl_of_match), 474 .of_match_table = kirkwood_pinctrl_of_match,
475 }, 475 },
476 .probe = kirkwood_pinctrl_probe, 476 .probe = kirkwood_pinctrl_probe,
477 .remove = kirkwood_pinctrl_remove, 477 .remove = kirkwood_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-adi2-bf54x.c b/drivers/pinctrl/pinctrl-adi2-bf54x.c
new file mode 100644
index 000000000000..ea9d9ab9cda1
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi2-bf54x.c
@@ -0,0 +1,592 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#include <asm/portmux.h>
10#include "pinctrl-adi2.h"
11
12static const struct pinctrl_pin_desc adi_pads[] = {
13 PINCTRL_PIN(0, "PA0"),
14 PINCTRL_PIN(1, "PA1"),
15 PINCTRL_PIN(2, "PA2"),
16 PINCTRL_PIN(3, "PG3"),
17 PINCTRL_PIN(4, "PA4"),
18 PINCTRL_PIN(5, "PA5"),
19 PINCTRL_PIN(6, "PA6"),
20 PINCTRL_PIN(7, "PA7"),
21 PINCTRL_PIN(8, "PA8"),
22 PINCTRL_PIN(9, "PA9"),
23 PINCTRL_PIN(10, "PA10"),
24 PINCTRL_PIN(11, "PA11"),
25 PINCTRL_PIN(12, "PA12"),
26 PINCTRL_PIN(13, "PA13"),
27 PINCTRL_PIN(14, "PA14"),
28 PINCTRL_PIN(15, "PA15"),
29 PINCTRL_PIN(16, "PB0"),
30 PINCTRL_PIN(17, "PB1"),
31 PINCTRL_PIN(18, "PB2"),
32 PINCTRL_PIN(19, "PB3"),
33 PINCTRL_PIN(20, "PB4"),
34 PINCTRL_PIN(21, "PB5"),
35 PINCTRL_PIN(22, "PB6"),
36 PINCTRL_PIN(23, "PB7"),
37 PINCTRL_PIN(24, "PB8"),
38 PINCTRL_PIN(25, "PB9"),
39 PINCTRL_PIN(26, "PB10"),
40 PINCTRL_PIN(27, "PB11"),
41 PINCTRL_PIN(28, "PB12"),
42 PINCTRL_PIN(29, "PB13"),
43 PINCTRL_PIN(30, "PB14"),
44 PINCTRL_PIN(32, "PC0"),
45 PINCTRL_PIN(33, "PC1"),
46 PINCTRL_PIN(34, "PC2"),
47 PINCTRL_PIN(35, "PC3"),
48 PINCTRL_PIN(36, "PC4"),
49 PINCTRL_PIN(37, "PC5"),
50 PINCTRL_PIN(38, "PC6"),
51 PINCTRL_PIN(39, "PC7"),
52 PINCTRL_PIN(40, "PC8"),
53 PINCTRL_PIN(41, "PC9"),
54 PINCTRL_PIN(42, "PC10"),
55 PINCTRL_PIN(43, "PC11"),
56 PINCTRL_PIN(44, "PC12"),
57 PINCTRL_PIN(45, "PC13"),
58 PINCTRL_PIN(48, "PD0"),
59 PINCTRL_PIN(49, "PD1"),
60 PINCTRL_PIN(50, "PD2"),
61 PINCTRL_PIN(51, "PD3"),
62 PINCTRL_PIN(52, "PD4"),
63 PINCTRL_PIN(53, "PD5"),
64 PINCTRL_PIN(54, "PD6"),
65 PINCTRL_PIN(55, "PD7"),
66 PINCTRL_PIN(56, "PD8"),
67 PINCTRL_PIN(57, "PD9"),
68 PINCTRL_PIN(58, "PD10"),
69 PINCTRL_PIN(59, "PD11"),
70 PINCTRL_PIN(60, "PD12"),
71 PINCTRL_PIN(61, "PD13"),
72 PINCTRL_PIN(62, "PD14"),
73 PINCTRL_PIN(63, "PD15"),
74 PINCTRL_PIN(64, "PE0"),
75 PINCTRL_PIN(65, "PE1"),
76 PINCTRL_PIN(66, "PE2"),
77 PINCTRL_PIN(67, "PE3"),
78 PINCTRL_PIN(68, "PE4"),
79 PINCTRL_PIN(69, "PE5"),
80 PINCTRL_PIN(70, "PE6"),
81 PINCTRL_PIN(71, "PE7"),
82 PINCTRL_PIN(72, "PE8"),
83 PINCTRL_PIN(73, "PE9"),
84 PINCTRL_PIN(74, "PE10"),
85 PINCTRL_PIN(75, "PE11"),
86 PINCTRL_PIN(76, "PE12"),
87 PINCTRL_PIN(77, "PE13"),
88 PINCTRL_PIN(78, "PE14"),
89 PINCTRL_PIN(79, "PE15"),
90 PINCTRL_PIN(80, "PF0"),
91 PINCTRL_PIN(81, "PF1"),
92 PINCTRL_PIN(82, "PF2"),
93 PINCTRL_PIN(83, "PF3"),
94 PINCTRL_PIN(84, "PF4"),
95 PINCTRL_PIN(85, "PF5"),
96 PINCTRL_PIN(86, "PF6"),
97 PINCTRL_PIN(87, "PF7"),
98 PINCTRL_PIN(88, "PF8"),
99 PINCTRL_PIN(89, "PF9"),
100 PINCTRL_PIN(90, "PF10"),
101 PINCTRL_PIN(91, "PF11"),
102 PINCTRL_PIN(92, "PF12"),
103 PINCTRL_PIN(93, "PF13"),
104 PINCTRL_PIN(94, "PF14"),
105 PINCTRL_PIN(95, "PF15"),
106 PINCTRL_PIN(96, "PG0"),
107 PINCTRL_PIN(97, "PG1"),
108 PINCTRL_PIN(98, "PG2"),
109 PINCTRL_PIN(99, "PG3"),
110 PINCTRL_PIN(100, "PG4"),
111 PINCTRL_PIN(101, "PG5"),
112 PINCTRL_PIN(102, "PG6"),
113 PINCTRL_PIN(103, "PG7"),
114 PINCTRL_PIN(104, "PG8"),
115 PINCTRL_PIN(105, "PG9"),
116 PINCTRL_PIN(106, "PG10"),
117 PINCTRL_PIN(107, "PG11"),
118 PINCTRL_PIN(108, "PG12"),
119 PINCTRL_PIN(109, "PG13"),
120 PINCTRL_PIN(110, "PG14"),
121 PINCTRL_PIN(111, "PG15"),
122 PINCTRL_PIN(112, "PH0"),
123 PINCTRL_PIN(113, "PH1"),
124 PINCTRL_PIN(114, "PH2"),
125 PINCTRL_PIN(115, "PH3"),
126 PINCTRL_PIN(116, "PH4"),
127 PINCTRL_PIN(117, "PH5"),
128 PINCTRL_PIN(118, "PH6"),
129 PINCTRL_PIN(119, "PH7"),
130 PINCTRL_PIN(120, "PH8"),
131 PINCTRL_PIN(121, "PH9"),
132 PINCTRL_PIN(122, "PH10"),
133 PINCTRL_PIN(123, "PH11"),
134 PINCTRL_PIN(124, "PH12"),
135 PINCTRL_PIN(125, "PH13"),
136 PINCTRL_PIN(128, "PI0"),
137 PINCTRL_PIN(129, "PI1"),
138 PINCTRL_PIN(130, "PI2"),
139 PINCTRL_PIN(131, "PI3"),
140 PINCTRL_PIN(132, "PI4"),
141 PINCTRL_PIN(133, "PI5"),
142 PINCTRL_PIN(134, "PI6"),
143 PINCTRL_PIN(135, "PI7"),
144 PINCTRL_PIN(136, "PI8"),
145 PINCTRL_PIN(137, "PI9"),
146 PINCTRL_PIN(138, "PI10"),
147 PINCTRL_PIN(139, "PI11"),
148 PINCTRL_PIN(140, "PI12"),
149 PINCTRL_PIN(141, "PI13"),
150 PINCTRL_PIN(142, "PI14"),
151 PINCTRL_PIN(143, "PI15"),
152 PINCTRL_PIN(144, "PJ0"),
153 PINCTRL_PIN(145, "PJ1"),
154 PINCTRL_PIN(146, "PJ2"),
155 PINCTRL_PIN(147, "PJ3"),
156 PINCTRL_PIN(148, "PJ4"),
157 PINCTRL_PIN(149, "PJ5"),
158 PINCTRL_PIN(150, "PJ6"),
159 PINCTRL_PIN(151, "PJ7"),
160 PINCTRL_PIN(152, "PJ8"),
161 PINCTRL_PIN(153, "PJ9"),
162 PINCTRL_PIN(154, "PJ10"),
163 PINCTRL_PIN(155, "PJ11"),
164 PINCTRL_PIN(156, "PJ12"),
165 PINCTRL_PIN(157, "PJ13"),
166};
167
168static const unsigned uart0_pins[] = {
169 GPIO_PE7, GPIO_PE8,
170};
171
172static const unsigned uart1_pins[] = {
173 GPIO_PH0, GPIO_PH1,
174};
175
176static const unsigned uart1_ctsrts_pins[] = {
177 GPIO_PE9, GPIO_PE10,
178};
179
180static const unsigned uart2_pins[] = {
181 GPIO_PB4, GPIO_PB5,
182};
183
184static const unsigned uart3_pins[] = {
185 GPIO_PB6, GPIO_PB7,
186};
187
188static const unsigned uart3_ctsrts_pins[] = {
189 GPIO_PB2, GPIO_PB3,
190};
191
192static const unsigned rsi0_pins[] = {
193 GPIO_PC8, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12, GPIO_PC13,
194};
195
196static const unsigned spi0_pins[] = {
197 GPIO_PE0, GPIO_PE1, GPIO_PE2,
198};
199
200static const unsigned spi1_pins[] = {
201 GPIO_PG8, GPIO_PG9, GPIO_PG10,
202};
203
204static const unsigned twi0_pins[] = {
205 GPIO_PE14, GPIO_PE15,
206};
207
208static const unsigned twi1_pins[] = {
209 GPIO_PB0, GPIO_PB1,
210};
211
212static const unsigned rotary_pins[] = {
213 GPIO_PH4, GPIO_PH3, GPIO_PH5,
214};
215
216static const unsigned can0_pins[] = {
217 GPIO_PG13, GPIO_PG12,
218};
219
220static const unsigned can1_pins[] = {
221 GPIO_PG14, GPIO_PG15,
222};
223
224static const unsigned smc0_pins[] = {
225 GPIO_PH8, GPIO_PH9, GPIO_PH10, GPIO_PH11, GPIO_PH12, GPIO_PH13,
226 GPIO_PI0, GPIO_PI1, GPIO_PI2, GPIO_PI3, GPIO_PI4, GPIO_PI5, GPIO_PI6,
227 GPIO_PI7, GPIO_PI8, GPIO_PI9, GPIO_PI10, GPIO_PI11,
228 GPIO_PI12, GPIO_PI13, GPIO_PI14, GPIO_PI15,
229};
230
231static const unsigned sport0_pins[] = {
232 GPIO_PC0, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC6, GPIO_PC7,
233};
234
235static const unsigned sport1_pins[] = {
236 GPIO_PD0, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD6, GPIO_PD7,
237};
238
239static const unsigned sport2_pins[] = {
240 GPIO_PA0, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA6, GPIO_PA7,
241};
242
243static const unsigned sport3_pins[] = {
244 GPIO_PA8, GPIO_PA10, GPIO_PA11, GPIO_PA12, GPIO_PA14, GPIO_PA15,
245};
246
247static const unsigned ppi0_8b_pins[] = {
248 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
249 GPIO_PF7, GPIO_PF13, GPIO_PG0, GPIO_PG1, GPIO_PG2,
250};
251
252static const unsigned ppi0_16b_pins[] = {
253 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
254 GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
255 GPIO_PF13, GPIO_PF14, GPIO_PF15,
256 GPIO_PG0, GPIO_PG1, GPIO_PG2,
257};
258
259static const unsigned ppi0_24b_pins[] = {
260 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
261 GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
262 GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PD0, GPIO_PD1, GPIO_PD2,
263 GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PG3, GPIO_PG4,
264 GPIO_PG0, GPIO_PG1, GPIO_PG2,
265};
266
267static const unsigned ppi1_8b_pins[] = {
268 GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6,
269 GPIO_PD7, GPIO_PE11, GPIO_PE12, GPIO_PE13,
270};
271
272static const unsigned ppi1_16b_pins[] = {
273 GPIO_PD0, GPIO_PD1, GPIO_PD2, GPIO_PD3, GPIO_PD4, GPIO_PD5, GPIO_PD6,
274 GPIO_PD7, GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12,
275 GPIO_PD13, GPIO_PD14, GPIO_PD15,
276 GPIO_PE11, GPIO_PE12, GPIO_PE13,
277};
278
279static const unsigned ppi2_8b_pins[] = {
280 GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11, GPIO_PD12,
281 GPIO_PD13, GPIO_PD14, GPIO_PD15,
282 GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3,
283};
284
285static const unsigned atapi_pins[] = {
286 GPIO_PH2, GPIO_PJ3, GPIO_PJ4, GPIO_PJ5, GPIO_PJ6,
287 GPIO_PJ7, GPIO_PJ8, GPIO_PJ9, GPIO_PJ10,
288};
289
290static const unsigned atapi_alter_pins[] = {
291 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
292 GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
293 GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PG2, GPIO_PG3, GPIO_PG4,
294};
295
296static const unsigned nfc0_pins[] = {
297 GPIO_PJ1, GPIO_PJ2,
298};
299
300static const unsigned keys_4x4_pins[] = {
301 GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11,
302 GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15,
303};
304
305static const unsigned keys_8x8_pins[] = {
306 GPIO_PD8, GPIO_PD9, GPIO_PD10, GPIO_PD11,
307 GPIO_PD12, GPIO_PD13, GPIO_PD14, GPIO_PD15,
308 GPIO_PE0, GPIO_PE1, GPIO_PE2, GPIO_PE3,
309 GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7,
310};
311
312static const struct adi_pin_group adi_pin_groups[] = {
313 ADI_PIN_GROUP("uart0grp", uart0_pins),
314 ADI_PIN_GROUP("uart1grp", uart1_pins),
315 ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
316 ADI_PIN_GROUP("uart2grp", uart2_pins),
317 ADI_PIN_GROUP("uart3grp", uart3_pins),
318 ADI_PIN_GROUP("uart3ctsrtsgrp", uart3_ctsrts_pins),
319 ADI_PIN_GROUP("rsi0grp", rsi0_pins),
320 ADI_PIN_GROUP("spi0grp", spi0_pins),
321 ADI_PIN_GROUP("spi1grp", spi1_pins),
322 ADI_PIN_GROUP("twi0grp", twi0_pins),
323 ADI_PIN_GROUP("twi1grp", twi1_pins),
324 ADI_PIN_GROUP("rotarygrp", rotary_pins),
325 ADI_PIN_GROUP("can0grp", can0_pins),
326 ADI_PIN_GROUP("can1grp", can1_pins),
327 ADI_PIN_GROUP("smc0grp", smc0_pins),
328 ADI_PIN_GROUP("sport0grp", sport0_pins),
329 ADI_PIN_GROUP("sport1grp", sport1_pins),
330 ADI_PIN_GROUP("sport2grp", sport2_pins),
331 ADI_PIN_GROUP("sport3grp", sport3_pins),
332 ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
333 ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
334 ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
335 ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
336 ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
337 ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
338 ADI_PIN_GROUP("atapigrp", atapi_pins),
339 ADI_PIN_GROUP("atapialtergrp", atapi_alter_pins),
340 ADI_PIN_GROUP("nfc0grp", nfc0_pins),
341 ADI_PIN_GROUP("keys_4x4grp", keys_4x4_pins),
342 ADI_PIN_GROUP("keys_8x8grp", keys_8x8_pins),
343};
344
345static const unsigned short uart0_mux[] = {
346 P_UART0_TX, P_UART0_RX,
347 0
348};
349
350static const unsigned short uart1_mux[] = {
351 P_UART1_TX, P_UART1_RX,
352 0
353};
354
355static const unsigned short uart1_ctsrts_mux[] = {
356 P_UART1_RTS, P_UART1_CTS,
357 0
358};
359
360static const unsigned short uart2_mux[] = {
361 P_UART2_TX, P_UART2_RX,
362 0
363};
364
365static const unsigned short uart3_mux[] = {
366 P_UART3_TX, P_UART3_RX,
367 0
368};
369
370static const unsigned short uart3_ctsrts_mux[] = {
371 P_UART3_RTS, P_UART3_CTS,
372 0
373};
374
375static const unsigned short rsi0_mux[] = {
376 P_SD_D0, P_SD_D1, P_SD_D2, P_SD_D3, P_SD_CLK, P_SD_CMD,
377 0
378};
379
380static const unsigned short spi0_mux[] = {
381 P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0
382};
383
384static const unsigned short spi1_mux[] = {
385 P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0
386};
387
388static const unsigned short twi0_mux[] = {
389 P_TWI0_SCL, P_TWI0_SDA, 0
390};
391
392static const unsigned short twi1_mux[] = {
393 P_TWI1_SCL, P_TWI1_SDA, 0
394};
395
396static const unsigned short rotary_mux[] = {
397 P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0
398};
399
400static const unsigned short sport0_mux[] = {
401 P_SPORT0_TFS, P_SPORT0_DTPRI, P_SPORT0_TSCLK, P_SPORT0_RFS,
402 P_SPORT0_DRPRI, P_SPORT0_RSCLK, 0
403};
404
405static const unsigned short sport1_mux[] = {
406 P_SPORT1_TFS, P_SPORT1_DTPRI, P_SPORT1_TSCLK, P_SPORT1_RFS,
407 P_SPORT1_DRPRI, P_SPORT1_RSCLK, 0
408};
409
410static const unsigned short sport2_mux[] = {
411 P_SPORT2_TFS, P_SPORT2_DTPRI, P_SPORT2_TSCLK, P_SPORT2_RFS,
412 P_SPORT2_DRPRI, P_SPORT2_RSCLK, 0
413};
414
415static const unsigned short sport3_mux[] = {
416 P_SPORT3_TFS, P_SPORT3_DTPRI, P_SPORT3_TSCLK, P_SPORT3_RFS,
417 P_SPORT3_DRPRI, P_SPORT3_RSCLK, 0
418};
419
420static const unsigned short can0_mux[] = {
421 P_CAN0_RX, P_CAN0_TX, 0
422};
423
424static const unsigned short can1_mux[] = {
425 P_CAN1_RX, P_CAN1_TX, 0
426};
427
428static const unsigned short smc0_mux[] = {
429 P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
430 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
431 P_A22, P_A23, P_A24, P_A25, P_NOR_CLK, 0,
432};
433
434static const unsigned short ppi0_8b_mux[] = {
435 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
436 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
437 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
438 0,
439};
440
441static const unsigned short ppi0_16b_mux[] = {
442 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
443 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
444 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
445 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
446 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
447 0,
448};
449
450static const unsigned short ppi0_24b_mux[] = {
451 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
452 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
453 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
454 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
455 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
456 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
457 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
458 0,
459};
460
461static const unsigned short ppi1_8b_mux[] = {
462 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
463 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
464 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
465 0,
466};
467
468static const unsigned short ppi1_16b_mux[] = {
469 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
470 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
471 P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11,
472 P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15,
473 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
474 0,
475};
476
477static const unsigned short ppi2_8b_mux[] = {
478 P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
479 P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
480 P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
481 0,
482};
483
484static const unsigned short atapi_mux[] = {
485 P_ATAPI_RESET, P_ATAPI_DIOR, P_ATAPI_DIOW, P_ATAPI_CS0, P_ATAPI_CS1,
486 P_ATAPI_DMACK, P_ATAPI_DMARQ, P_ATAPI_INTRQ, P_ATAPI_IORDY,
487};
488
489static const unsigned short atapi_alter_mux[] = {
490 P_ATAPI_D0A, P_ATAPI_D1A, P_ATAPI_D2A, P_ATAPI_D3A, P_ATAPI_D4A,
491 P_ATAPI_D5A, P_ATAPI_D6A, P_ATAPI_D7A, P_ATAPI_D8A, P_ATAPI_D9A,
492 P_ATAPI_D10A, P_ATAPI_D11A, P_ATAPI_D12A, P_ATAPI_D13A, P_ATAPI_D14A,
493 P_ATAPI_D15A, P_ATAPI_A0A, P_ATAPI_A1A, P_ATAPI_A2A,
494 0
495};
496
497static const unsigned short nfc0_mux[] = {
498 P_NAND_CE, P_NAND_RB,
499 0
500};
501
502static const unsigned short keys_4x4_mux[] = {
503 P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0,
504 P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0,
505 0
506};
507
508static const unsigned short keys_8x8_mux[] = {
509 P_KEY_ROW7, P_KEY_ROW6, P_KEY_ROW5, P_KEY_ROW4,
510 P_KEY_ROW3, P_KEY_ROW2, P_KEY_ROW1, P_KEY_ROW0,
511 P_KEY_COL7, P_KEY_COL6, P_KEY_COL5, P_KEY_COL4,
512 P_KEY_COL3, P_KEY_COL2, P_KEY_COL1, P_KEY_COL0,
513 0
514};
515
516static const char * const uart0grp[] = { "uart0grp" };
517static const char * const uart1grp[] = { "uart1grp" };
518static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
519static const char * const uart2grp[] = { "uart2grp" };
520static const char * const uart3grp[] = { "uart3grp" };
521static const char * const uart3ctsrtsgrp[] = { "uart3ctsrtsgrp" };
522static const char * const rsi0grp[] = { "rsi0grp" };
523static const char * const spi0grp[] = { "spi0grp" };
524static const char * const spi1grp[] = { "spi1grp" };
525static const char * const twi0grp[] = { "twi0grp" };
526static const char * const twi1grp[] = { "twi1grp" };
527static const char * const rotarygrp[] = { "rotarygrp" };
528static const char * const can0grp[] = { "can0grp" };
529static const char * const can1grp[] = { "can1grp" };
530static const char * const smc0grp[] = { "smc0grp" };
531static const char * const sport0grp[] = { "sport0grp" };
532static const char * const sport1grp[] = { "sport1grp" };
533static const char * const sport2grp[] = { "sport2grp" };
534static const char * const sport3grp[] = { "sport3grp" };
535static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" };
536static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" };
537static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" };
538static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" };
539static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" };
540static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" };
541static const char * const atapigrp[] = { "atapigrp" };
542static const char * const atapialtergrp[] = { "atapialtergrp" };
543static const char * const nfc0grp[] = { "nfc0grp" };
544static const char * const keys_4x4grp[] = { "keys_4x4grp" };
545static const char * const keys_8x8grp[] = { "keys_8x8grp" };
546
547static const struct adi_pmx_func adi_pmx_functions[] = {
548 ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux),
549 ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux),
550 ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux),
551 ADI_PMX_FUNCTION("uart2", uart2grp, uart2_mux),
552 ADI_PMX_FUNCTION("uart3", uart3grp, uart3_mux),
553 ADI_PMX_FUNCTION("uart3_ctsrts", uart3ctsrtsgrp, uart3_ctsrts_mux),
554 ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux),
555 ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux),
556 ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux),
557 ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux),
558 ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux),
559 ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux),
560 ADI_PMX_FUNCTION("can0", can0grp, can0_mux),
561 ADI_PMX_FUNCTION("can1", can1grp, can1_mux),
562 ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux),
563 ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux),
564 ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux),
565 ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux),
566 ADI_PMX_FUNCTION("sport3", sport3grp, sport3_mux),
567 ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux),
568 ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux),
569 ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux),
570 ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux),
571 ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux),
572 ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux),
573 ADI_PMX_FUNCTION("atapi", atapigrp, atapi_mux),
574 ADI_PMX_FUNCTION("atapi_alter", atapialtergrp, atapi_alter_mux),
575 ADI_PMX_FUNCTION("nfc0", nfc0grp, nfc0_mux),
576 ADI_PMX_FUNCTION("keys_4x4", keys_4x4grp, keys_4x4_mux),
577 ADI_PMX_FUNCTION("keys_8x8", keys_8x8grp, keys_8x8_mux),
578};
579
580static const struct adi_pinctrl_soc_data adi_bf54x_soc = {
581 .functions = adi_pmx_functions,
582 .nfunctions = ARRAY_SIZE(adi_pmx_functions),
583 .groups = adi_pin_groups,
584 .ngroups = ARRAY_SIZE(adi_pin_groups),
585 .pins = adi_pads,
586 .npins = ARRAY_SIZE(adi_pads),
587};
588
589void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc)
590{
591 *soc = &adi_bf54x_soc;
592}
diff --git a/drivers/pinctrl/pinctrl-adi2-bf60x.c b/drivers/pinctrl/pinctrl-adi2-bf60x.c
new file mode 100644
index 000000000000..bf57aea2826c
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi2-bf60x.c
@@ -0,0 +1,521 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#include <asm/portmux.h>
10#include "pinctrl-adi2.h"
11
12static const struct pinctrl_pin_desc adi_pads[] = {
13 PINCTRL_PIN(0, "PA0"),
14 PINCTRL_PIN(1, "PA1"),
15 PINCTRL_PIN(2, "PA2"),
16 PINCTRL_PIN(3, "PG3"),
17 PINCTRL_PIN(4, "PA4"),
18 PINCTRL_PIN(5, "PA5"),
19 PINCTRL_PIN(6, "PA6"),
20 PINCTRL_PIN(7, "PA7"),
21 PINCTRL_PIN(8, "PA8"),
22 PINCTRL_PIN(9, "PA9"),
23 PINCTRL_PIN(10, "PA10"),
24 PINCTRL_PIN(11, "PA11"),
25 PINCTRL_PIN(12, "PA12"),
26 PINCTRL_PIN(13, "PA13"),
27 PINCTRL_PIN(14, "PA14"),
28 PINCTRL_PIN(15, "PA15"),
29 PINCTRL_PIN(16, "PB0"),
30 PINCTRL_PIN(17, "PB1"),
31 PINCTRL_PIN(18, "PB2"),
32 PINCTRL_PIN(19, "PB3"),
33 PINCTRL_PIN(20, "PB4"),
34 PINCTRL_PIN(21, "PB5"),
35 PINCTRL_PIN(22, "PB6"),
36 PINCTRL_PIN(23, "PB7"),
37 PINCTRL_PIN(24, "PB8"),
38 PINCTRL_PIN(25, "PB9"),
39 PINCTRL_PIN(26, "PB10"),
40 PINCTRL_PIN(27, "PB11"),
41 PINCTRL_PIN(28, "PB12"),
42 PINCTRL_PIN(29, "PB13"),
43 PINCTRL_PIN(30, "PB14"),
44 PINCTRL_PIN(31, "PB15"),
45 PINCTRL_PIN(32, "PC0"),
46 PINCTRL_PIN(33, "PC1"),
47 PINCTRL_PIN(34, "PC2"),
48 PINCTRL_PIN(35, "PC3"),
49 PINCTRL_PIN(36, "PC4"),
50 PINCTRL_PIN(37, "PC5"),
51 PINCTRL_PIN(38, "PC6"),
52 PINCTRL_PIN(39, "PC7"),
53 PINCTRL_PIN(40, "PC8"),
54 PINCTRL_PIN(41, "PC9"),
55 PINCTRL_PIN(42, "PC10"),
56 PINCTRL_PIN(43, "PC11"),
57 PINCTRL_PIN(44, "PC12"),
58 PINCTRL_PIN(45, "PC13"),
59 PINCTRL_PIN(46, "PC14"),
60 PINCTRL_PIN(47, "PC15"),
61 PINCTRL_PIN(48, "PD0"),
62 PINCTRL_PIN(49, "PD1"),
63 PINCTRL_PIN(50, "PD2"),
64 PINCTRL_PIN(51, "PD3"),
65 PINCTRL_PIN(52, "PD4"),
66 PINCTRL_PIN(53, "PD5"),
67 PINCTRL_PIN(54, "PD6"),
68 PINCTRL_PIN(55, "PD7"),
69 PINCTRL_PIN(56, "PD8"),
70 PINCTRL_PIN(57, "PD9"),
71 PINCTRL_PIN(58, "PD10"),
72 PINCTRL_PIN(59, "PD11"),
73 PINCTRL_PIN(60, "PD12"),
74 PINCTRL_PIN(61, "PD13"),
75 PINCTRL_PIN(62, "PD14"),
76 PINCTRL_PIN(63, "PD15"),
77 PINCTRL_PIN(64, "PE0"),
78 PINCTRL_PIN(65, "PE1"),
79 PINCTRL_PIN(66, "PE2"),
80 PINCTRL_PIN(67, "PE3"),
81 PINCTRL_PIN(68, "PE4"),
82 PINCTRL_PIN(69, "PE5"),
83 PINCTRL_PIN(70, "PE6"),
84 PINCTRL_PIN(71, "PE7"),
85 PINCTRL_PIN(72, "PE8"),
86 PINCTRL_PIN(73, "PE9"),
87 PINCTRL_PIN(74, "PE10"),
88 PINCTRL_PIN(75, "PE11"),
89 PINCTRL_PIN(76, "PE12"),
90 PINCTRL_PIN(77, "PE13"),
91 PINCTRL_PIN(78, "PE14"),
92 PINCTRL_PIN(79, "PE15"),
93 PINCTRL_PIN(80, "PF0"),
94 PINCTRL_PIN(81, "PF1"),
95 PINCTRL_PIN(82, "PF2"),
96 PINCTRL_PIN(83, "PF3"),
97 PINCTRL_PIN(84, "PF4"),
98 PINCTRL_PIN(85, "PF5"),
99 PINCTRL_PIN(86, "PF6"),
100 PINCTRL_PIN(87, "PF7"),
101 PINCTRL_PIN(88, "PF8"),
102 PINCTRL_PIN(89, "PF9"),
103 PINCTRL_PIN(90, "PF10"),
104 PINCTRL_PIN(91, "PF11"),
105 PINCTRL_PIN(92, "PF12"),
106 PINCTRL_PIN(93, "PF13"),
107 PINCTRL_PIN(94, "PF14"),
108 PINCTRL_PIN(95, "PF15"),
109 PINCTRL_PIN(96, "PG0"),
110 PINCTRL_PIN(97, "PG1"),
111 PINCTRL_PIN(98, "PG2"),
112 PINCTRL_PIN(99, "PG3"),
113 PINCTRL_PIN(100, "PG4"),
114 PINCTRL_PIN(101, "PG5"),
115 PINCTRL_PIN(102, "PG6"),
116 PINCTRL_PIN(103, "PG7"),
117 PINCTRL_PIN(104, "PG8"),
118 PINCTRL_PIN(105, "PG9"),
119 PINCTRL_PIN(106, "PG10"),
120 PINCTRL_PIN(107, "PG11"),
121 PINCTRL_PIN(108, "PG12"),
122 PINCTRL_PIN(109, "PG13"),
123 PINCTRL_PIN(110, "PG14"),
124 PINCTRL_PIN(111, "PG15"),
125};
126
127static const unsigned uart0_pins[] = {
128 GPIO_PD7, GPIO_PD8,
129};
130
131static const unsigned uart0_ctsrts_pins[] = {
132 GPIO_PD9, GPIO_PD10,
133};
134
135static const unsigned uart1_pins[] = {
136 GPIO_PG15, GPIO_PG14,
137};
138
139static const unsigned uart1_ctsrts_pins[] = {
140 GPIO_PG10, GPIO_PG13,
141};
142
143static const unsigned rsi0_pins[] = {
144 GPIO_PG3, GPIO_PG2, GPIO_PG0, GPIO_PE15, GPIO_PG5, GPIO_PG6,
145};
146
147static const unsigned eth0_pins[] = {
148 GPIO_PC6, GPIO_PC7, GPIO_PC2, GPIO_PC0, GPIO_PC3, GPIO_PC1,
149 GPIO_PB13, GPIO_PD6, GPIO_PC5, GPIO_PC4, GPIO_PB14, GPIO_PB15,
150};
151
152static const unsigned eth1_pins[] = {
153 GPIO_PE10, GPIO_PE11, GPIO_PG3, GPIO_PG0, GPIO_PG2, GPIO_PE15,
154 GPIO_PG5, GPIO_PE12, GPIO_PE13, GPIO_PE14, GPIO_PG6, GPIO_PC9,
155};
156
157static const unsigned spi0_pins[] = {
158 GPIO_PD4, GPIO_PD2, GPIO_PD3,
159};
160
161static const unsigned spi1_pins[] = {
162 GPIO_PD5, GPIO_PD14, GPIO_PD13,
163};
164
165static const unsigned twi0_pins[] = {
166};
167
168static const unsigned twi1_pins[] = {
169};
170
171static const unsigned rotary_pins[] = {
172 GPIO_PG7, GPIO_PG11, GPIO_PG12,
173};
174
175static const unsigned can0_pins[] = {
176 GPIO_PG1, GPIO_PG4,
177};
178
179static const unsigned smc0_pins[] = {
180 GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
181 GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PB2, GPIO_PA10, GPIO_PA11,
182 GPIO_PB3, GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB6,
183 GPIO_PB7, GPIO_PB8, GPIO_PB10, GPIO_PB11, GPIO_PB0,
184};
185
186static const unsigned sport0_pins[] = {
187 GPIO_PB5, GPIO_PB4, GPIO_PB9, GPIO_PB8, GPIO_PB7, GPIO_PB11,
188};
189
190static const unsigned sport1_pins[] = {
191 GPIO_PE2, GPIO_PE5, GPIO_PD15, GPIO_PE4, GPIO_PE3, GPIO_PE1,
192};
193
194static const unsigned sport2_pins[] = {
195 GPIO_PG4, GPIO_PG1, GPIO_PG9, GPIO_PG10, GPIO_PG7, GPIO_PB12,
196};
197
198static const unsigned ppi0_8b_pins[] = {
199 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
200 GPIO_PF7, GPIO_PF13, GPIO_PF14, GPIO_PF15,
201 GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9,
202};
203
204static const unsigned ppi0_16b_pins[] = {
205 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
206 GPIO_PF7, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
207 GPIO_PF13, GPIO_PF14, GPIO_PF15,
208 GPIO_PE6, GPIO_PE7, GPIO_PE8, GPIO_PE9,
209};
210
211static const unsigned ppi0_24b_pins[] = {
212 GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3, GPIO_PF4, GPIO_PF5, GPIO_PF6,
213 GPIO_PF7, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11, GPIO_PF12,
214 GPIO_PF13, GPIO_PF14, GPIO_PF15, GPIO_PE0, GPIO_PE1, GPIO_PE2,
215 GPIO_PE3, GPIO_PE4, GPIO_PE5, GPIO_PE6, GPIO_PE7, GPIO_PE8,
216 GPIO_PE9, GPIO_PD12, GPIO_PD15,
217};
218
219static const unsigned ppi1_8b_pins[] = {
220 GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6,
221 GPIO_PC7, GPIO_PC8, GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6,
222};
223
224static const unsigned ppi1_16b_pins[] = {
225 GPIO_PC0, GPIO_PC1, GPIO_PC2, GPIO_PC3, GPIO_PC4, GPIO_PC5, GPIO_PC6,
226 GPIO_PC7, GPIO_PC9, GPIO_PC10, GPIO_PC11, GPIO_PC12,
227 GPIO_PC13, GPIO_PC14, GPIO_PC15,
228 GPIO_PB13, GPIO_PB14, GPIO_PB15, GPIO_PD6,
229};
230
231static const unsigned ppi2_8b_pins[] = {
232 GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
233 GPIO_PA7, GPIO_PB0, GPIO_PB1, GPIO_PB2, GPIO_PB3,
234};
235
236static const unsigned ppi2_16b_pins[] = {
237 GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3, GPIO_PA4, GPIO_PA5, GPIO_PA6,
238 GPIO_PA7, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11, GPIO_PA12,
239 GPIO_PA13, GPIO_PA14, GPIO_PA15, GPIO_PB0, GPIO_PB1, GPIO_PB2,
240};
241
242static const unsigned lp0_pins[] = {
243 GPIO_PB0, GPIO_PB1, GPIO_PA0, GPIO_PA1, GPIO_PA2, GPIO_PA3,
244 GPIO_PA4, GPIO_PA5, GPIO_PA6, GPIO_PA7,
245};
246
247static const unsigned lp1_pins[] = {
248 GPIO_PB3, GPIO_PB2, GPIO_PA8, GPIO_PA9, GPIO_PA10, GPIO_PA11,
249 GPIO_PA12, GPIO_PA13, GPIO_PA14, GPIO_PA15,
250};
251
252static const unsigned lp2_pins[] = {
253 GPIO_PE6, GPIO_PE7, GPIO_PF0, GPIO_PF1, GPIO_PF2, GPIO_PF3,
254 GPIO_PF4, GPIO_PF5, GPIO_PF6, GPIO_PF7,
255};
256
257static const unsigned lp3_pins[] = {
258 GPIO_PE9, GPIO_PE8, GPIO_PF8, GPIO_PF9, GPIO_PF10, GPIO_PF11,
259 GPIO_PF12, GPIO_PF13, GPIO_PF14, GPIO_PF15,
260};
261
262static const struct adi_pin_group adi_pin_groups[] = {
263 ADI_PIN_GROUP("uart0grp", uart0_pins),
264 ADI_PIN_GROUP("uart0ctsrtsgrp", uart0_ctsrts_pins),
265 ADI_PIN_GROUP("uart1grp", uart1_pins),
266 ADI_PIN_GROUP("uart1ctsrtsgrp", uart1_ctsrts_pins),
267 ADI_PIN_GROUP("rsi0grp", rsi0_pins),
268 ADI_PIN_GROUP("eth0grp", eth0_pins),
269 ADI_PIN_GROUP("eth1grp", eth1_pins),
270 ADI_PIN_GROUP("spi0grp", spi0_pins),
271 ADI_PIN_GROUP("spi1grp", spi1_pins),
272 ADI_PIN_GROUP("twi0grp", twi0_pins),
273 ADI_PIN_GROUP("twi1grp", twi1_pins),
274 ADI_PIN_GROUP("rotarygrp", rotary_pins),
275 ADI_PIN_GROUP("can0grp", can0_pins),
276 ADI_PIN_GROUP("smc0grp", smc0_pins),
277 ADI_PIN_GROUP("sport0grp", sport0_pins),
278 ADI_PIN_GROUP("sport1grp", sport1_pins),
279 ADI_PIN_GROUP("sport2grp", sport2_pins),
280 ADI_PIN_GROUP("ppi0_8bgrp", ppi0_8b_pins),
281 ADI_PIN_GROUP("ppi0_16bgrp", ppi0_16b_pins),
282 ADI_PIN_GROUP("ppi0_24bgrp", ppi0_24b_pins),
283 ADI_PIN_GROUP("ppi1_8bgrp", ppi1_8b_pins),
284 ADI_PIN_GROUP("ppi1_16bgrp", ppi1_16b_pins),
285 ADI_PIN_GROUP("ppi2_8bgrp", ppi2_8b_pins),
286 ADI_PIN_GROUP("ppi2_16bgrp", ppi2_16b_pins),
287 ADI_PIN_GROUP("lp0grp", lp0_pins),
288 ADI_PIN_GROUP("lp1grp", lp1_pins),
289 ADI_PIN_GROUP("lp2grp", lp2_pins),
290 ADI_PIN_GROUP("lp3grp", lp3_pins),
291};
292
293static const unsigned short uart0_mux[] = {
294 P_UART0_TX, P_UART0_RX,
295 0
296};
297
298static const unsigned short uart0_ctsrts_mux[] = {
299 P_UART0_RTS, P_UART0_CTS,
300 0
301};
302
303static const unsigned short uart1_mux[] = {
304 P_UART1_TX, P_UART1_RX,
305 0
306};
307
308static const unsigned short uart1_ctsrts_mux[] = {
309 P_UART1_RTS, P_UART1_CTS,
310 0
311};
312
313static const unsigned short rsi0_mux[] = {
314 P_RSI_DATA0, P_RSI_DATA1, P_RSI_DATA2, P_RSI_DATA3,
315 P_RSI_CMD, P_RSI_CLK, 0
316};
317
318static const unsigned short eth0_mux[] = P_RMII0;
319static const unsigned short eth1_mux[] = P_RMII1;
320
321static const unsigned short spi0_mux[] = {
322 P_SPI0_SCK, P_SPI0_MISO, P_SPI0_MOSI, 0
323};
324
325static const unsigned short spi1_mux[] = {
326 P_SPI1_SCK, P_SPI1_MISO, P_SPI1_MOSI, 0
327};
328
329static const unsigned short twi0_mux[] = {
330 P_TWI0_SCL, P_TWI0_SDA, 0
331};
332
333static const unsigned short twi1_mux[] = {
334 P_TWI1_SCL, P_TWI1_SDA, 0
335};
336
337static const unsigned short rotary_mux[] = {
338 P_CNT_CUD, P_CNT_CDG, P_CNT_CZM, 0
339};
340
341static const unsigned short sport0_mux[] = {
342 P_SPORT0_ACLK, P_SPORT0_AFS, P_SPORT0_AD0, P_SPORT0_BCLK,
343 P_SPORT0_BFS, P_SPORT0_BD0, 0,
344};
345
346static const unsigned short sport1_mux[] = {
347 P_SPORT1_ACLK, P_SPORT1_AFS, P_SPORT1_AD0, P_SPORT1_BCLK,
348 P_SPORT1_BFS, P_SPORT1_BD0, 0,
349};
350
351static const unsigned short sport2_mux[] = {
352 P_SPORT2_ACLK, P_SPORT2_AFS, P_SPORT2_AD0, P_SPORT2_BCLK,
353 P_SPORT2_BFS, P_SPORT2_BD0, 0,
354};
355
356static const unsigned short can0_mux[] = {
357 P_CAN0_RX, P_CAN0_TX, 0
358};
359
360static const unsigned short smc0_mux[] = {
361 P_A3, P_A4, P_A5, P_A6, P_A7, P_A8, P_A9, P_A10, P_A11, P_A12,
362 P_A13, P_A14, P_A15, P_A16, P_A17, P_A18, P_A19, P_A20, P_A21,
363 P_A22, P_A23, P_A24, P_A25, P_NORCK, 0,
364};
365
366static const unsigned short ppi0_8b_mux[] = {
367 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
368 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
369 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
370 0,
371};
372
373static const unsigned short ppi0_16b_mux[] = {
374 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
375 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
376 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
377 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
378 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
379 0,
380};
381
382static const unsigned short ppi0_24b_mux[] = {
383 P_PPI0_D0, P_PPI0_D1, P_PPI0_D2, P_PPI0_D3,
384 P_PPI0_D4, P_PPI0_D5, P_PPI0_D6, P_PPI0_D7,
385 P_PPI0_D8, P_PPI0_D9, P_PPI0_D10, P_PPI0_D11,
386 P_PPI0_D12, P_PPI0_D13, P_PPI0_D14, P_PPI0_D15,
387 P_PPI0_D16, P_PPI0_D17, P_PPI0_D18, P_PPI0_D19,
388 P_PPI0_D20, P_PPI0_D21, P_PPI0_D22, P_PPI0_D23,
389 P_PPI0_CLK, P_PPI0_FS1, P_PPI0_FS2,
390 0,
391};
392
393static const unsigned short ppi1_8b_mux[] = {
394 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
395 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
396 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
397 0,
398};
399
400static const unsigned short ppi1_16b_mux[] = {
401 P_PPI1_D0, P_PPI1_D1, P_PPI1_D2, P_PPI1_D3,
402 P_PPI1_D4, P_PPI1_D5, P_PPI1_D6, P_PPI1_D7,
403 P_PPI1_D8, P_PPI1_D9, P_PPI1_D10, P_PPI1_D11,
404 P_PPI1_D12, P_PPI1_D13, P_PPI1_D14, P_PPI1_D15,
405 P_PPI1_CLK, P_PPI1_FS1, P_PPI1_FS2,
406 0,
407};
408
409static const unsigned short ppi2_8b_mux[] = {
410 P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
411 P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
412 P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
413 0,
414};
415
416static const unsigned short ppi2_16b_mux[] = {
417 P_PPI2_D0, P_PPI2_D1, P_PPI2_D2, P_PPI2_D3,
418 P_PPI2_D4, P_PPI2_D5, P_PPI2_D6, P_PPI2_D7,
419 P_PPI2_D8, P_PPI2_D9, P_PPI2_D10, P_PPI2_D11,
420 P_PPI2_D12, P_PPI2_D13, P_PPI2_D14, P_PPI2_D15,
421 P_PPI2_CLK, P_PPI2_FS1, P_PPI2_FS2,
422 0,
423};
424
425static const unsigned short lp0_mux[] = {
426 P_LP0_CLK, P_LP0_ACK, P_LP0_D0, P_LP0_D1, P_LP0_D2,
427 P_LP0_D3, P_LP0_D4, P_LP0_D5, P_LP0_D6, P_LP0_D7,
428 0
429};
430
431static const unsigned short lp1_mux[] = {
432 P_LP1_CLK, P_LP1_ACK, P_LP1_D0, P_LP1_D1, P_LP1_D2,
433 P_LP1_D3, P_LP1_D4, P_LP1_D5, P_LP1_D6, P_LP1_D7,
434 0
435};
436
437static const unsigned short lp2_mux[] = {
438 P_LP2_CLK, P_LP2_ACK, P_LP2_D0, P_LP2_D1, P_LP2_D2,
439 P_LP2_D3, P_LP2_D4, P_LP2_D5, P_LP2_D6, P_LP2_D7,
440 0
441};
442
443static const unsigned short lp3_mux[] = {
444 P_LP3_CLK, P_LP3_ACK, P_LP3_D0, P_LP3_D1, P_LP3_D2,
445 P_LP3_D3, P_LP3_D4, P_LP3_D5, P_LP3_D6, P_LP3_D7,
446 0
447};
448
449static const char * const uart0grp[] = { "uart0grp" };
450static const char * const uart0ctsrtsgrp[] = { "uart0ctsrtsgrp" };
451static const char * const uart1grp[] = { "uart1grp" };
452static const char * const uart1ctsrtsgrp[] = { "uart1ctsrtsgrp" };
453static const char * const rsi0grp[] = { "rsi0grp" };
454static const char * const eth0grp[] = { "eth0grp" };
455static const char * const eth1grp[] = { "eth1grp" };
456static const char * const spi0grp[] = { "spi0grp" };
457static const char * const spi1grp[] = { "spi1grp" };
458static const char * const twi0grp[] = { "twi0grp" };
459static const char * const twi1grp[] = { "twi1grp" };
460static const char * const rotarygrp[] = { "rotarygrp" };
461static const char * const can0grp[] = { "can0grp" };
462static const char * const smc0grp[] = { "smc0grp" };
463static const char * const sport0grp[] = { "sport0grp" };
464static const char * const sport1grp[] = { "sport1grp" };
465static const char * const sport2grp[] = { "sport2grp" };
466static const char * const ppi0_8bgrp[] = { "ppi0_8bgrp" };
467static const char * const ppi0_16bgrp[] = { "ppi0_16bgrp" };
468static const char * const ppi0_24bgrp[] = { "ppi0_24bgrp" };
469static const char * const ppi1_8bgrp[] = { "ppi1_8bgrp" };
470static const char * const ppi1_16bgrp[] = { "ppi1_16bgrp" };
471static const char * const ppi2_8bgrp[] = { "ppi2_8bgrp" };
472static const char * const ppi2_16bgrp[] = { "ppi2_16bgrp" };
473static const char * const lp0grp[] = { "lp0grp" };
474static const char * const lp1grp[] = { "lp1grp" };
475static const char * const lp2grp[] = { "lp2grp" };
476static const char * const lp3grp[] = { "lp3grp" };
477
478static const struct adi_pmx_func adi_pmx_functions[] = {
479 ADI_PMX_FUNCTION("uart0", uart0grp, uart0_mux),
480 ADI_PMX_FUNCTION("uart0_ctsrts", uart0ctsrtsgrp, uart0_ctsrts_mux),
481 ADI_PMX_FUNCTION("uart1", uart1grp, uart1_mux),
482 ADI_PMX_FUNCTION("uart1_ctsrts", uart1ctsrtsgrp, uart1_ctsrts_mux),
483 ADI_PMX_FUNCTION("rsi0", rsi0grp, rsi0_mux),
484 ADI_PMX_FUNCTION("eth0", eth0grp, eth0_mux),
485 ADI_PMX_FUNCTION("eth1", eth1grp, eth1_mux),
486 ADI_PMX_FUNCTION("spi0", spi0grp, spi0_mux),
487 ADI_PMX_FUNCTION("spi1", spi1grp, spi1_mux),
488 ADI_PMX_FUNCTION("twi0", twi0grp, twi0_mux),
489 ADI_PMX_FUNCTION("twi1", twi1grp, twi1_mux),
490 ADI_PMX_FUNCTION("rotary", rotarygrp, rotary_mux),
491 ADI_PMX_FUNCTION("can0", can0grp, can0_mux),
492 ADI_PMX_FUNCTION("smc0", smc0grp, smc0_mux),
493 ADI_PMX_FUNCTION("sport0", sport0grp, sport0_mux),
494 ADI_PMX_FUNCTION("sport1", sport1grp, sport1_mux),
495 ADI_PMX_FUNCTION("sport2", sport2grp, sport2_mux),
496 ADI_PMX_FUNCTION("ppi0_8b", ppi0_8bgrp, ppi0_8b_mux),
497 ADI_PMX_FUNCTION("ppi0_16b", ppi0_16bgrp, ppi0_16b_mux),
498 ADI_PMX_FUNCTION("ppi0_24b", ppi0_24bgrp, ppi0_24b_mux),
499 ADI_PMX_FUNCTION("ppi1_8b", ppi1_8bgrp, ppi1_8b_mux),
500 ADI_PMX_FUNCTION("ppi1_16b", ppi1_16bgrp, ppi1_16b_mux),
501 ADI_PMX_FUNCTION("ppi2_8b", ppi2_8bgrp, ppi2_8b_mux),
502 ADI_PMX_FUNCTION("ppi2_16b", ppi2_16bgrp, ppi2_16b_mux),
503 ADI_PMX_FUNCTION("lp0", lp0grp, lp0_mux),
504 ADI_PMX_FUNCTION("lp1", lp1grp, lp1_mux),
505 ADI_PMX_FUNCTION("lp2", lp2grp, lp2_mux),
506 ADI_PMX_FUNCTION("lp3", lp3grp, lp3_mux),
507};
508
509static const struct adi_pinctrl_soc_data adi_bf60x_soc = {
510 .functions = adi_pmx_functions,
511 .nfunctions = ARRAY_SIZE(adi_pmx_functions),
512 .groups = adi_pin_groups,
513 .ngroups = ARRAY_SIZE(adi_pin_groups),
514 .pins = adi_pads,
515 .npins = ARRAY_SIZE(adi_pads),
516};
517
518void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc)
519{
520 *soc = &adi_bf60x_soc;
521}
diff --git a/drivers/pinctrl/pinctrl-adi2.c b/drivers/pinctrl/pinctrl-adi2.c
new file mode 100644
index 000000000000..7a39562c3e42
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi2.c
@@ -0,0 +1,1164 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#include <linux/bitops.h>
10#include <linux/delay.h>
11#include <linux/module.h>
12#include <linux/err.h>
13#include <linux/debugfs.h>
14#include <linux/seq_file.h>
15#include <linux/irq.h>
16#include <linux/platform_data/pinctrl-adi2.h>
17#include <linux/irqdomain.h>
18#include <linux/irqchip/chained_irq.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21#include <linux/pinctrl/consumer.h>
22#include <linux/pinctrl/machine.h>
23#include <linux/syscore_ops.h>
24#include <linux/gpio.h>
25#include <asm/portmux.h>
26#include "pinctrl-adi2.h"
27#include "core.h"
28
29/*
30According to the BF54x HRM, pint means "pin interrupt".
31http://www.analog.com/static/imported-files/processor_manuals/ADSP-BF54x_hwr_rev1.2.pdf
32
33ADSP-BF54x processor Blackfin processors have four SIC interrupt chan-
34nels dedicated to pin interrupt purposes. These channels are managed by
35four hardware blocks, called PINT0, PINT1, PINT2, and PINT3. Every PINTx
36block can sense to up to 32 pins. While PINT0 and PINT1 can sense the
37pins of port A and port B, PINT2 and PINT3 manage all the pins from port
38C to port J as shown in Figure 9-2.
39
40n BF54x HRM:
41The ten GPIO ports are subdivided into 8-bit half ports, resulting in lower and
42upper half 8-bit units. The PINTx_ASSIGN registers control the 8-bit multi-
43plexers shown in Figure 9-3. Lower half units of eight pins can be
44forwarded to either byte 0 or byte 2 of either associated PINTx block.
45Upper half units can be forwarded to either byte 1 or byte 3 of the pin
46interrupt blocks, without further restrictions.
47
48All MMR registers in the pin interrupt module are 32 bits wide. To simply the
49mapping logic, this driver only maps a 16-bit gpio port to the upper or lower
5016 bits of a PINTx block. You can find the Figure 9-3 on page 583.
51
52Each IRQ domain is binding to a GPIO bank device. 2 GPIO bank devices can map
53to one PINT device. Two in "struct gpio_pint" are used to ease the PINT
54interrupt handler.
55
56The GPIO bank mapping to the lower 16 bits of the PINT device set its IRQ
57domain pointer in domain[0]. The IRQ domain pointer of the other bank is set
58to domain[1]. PINT interrupt handler adi_gpio_handle_pint_irq() finds out
59the current domain pointer according to whether the interrupt request mask
60is in lower 16 bits (domain[0]) or upper 16bits (domain[1]).
61
62A PINT device is not part of a GPIO port device in Blackfin. Multiple GPIO
63port devices can be mapped to the same PINT device.
64
65*/
66
67static LIST_HEAD(adi_pint_list);
68static LIST_HEAD(adi_gpio_port_list);
69
70#define DRIVER_NAME "pinctrl-adi2"
71
72#define PINT_HI_OFFSET 16
73
74/**
75 * struct gpio_port_saved - GPIO port registers that should be saved between
76 * power suspend and resume operations.
77 *
78 * @fer: PORTx_FER register
79 * @data: PORTx_DATA register
80 * @dir: PORTx_DIR register
81 * @inen: PORTx_INEN register
82 * @mux: PORTx_MUX register
83 */
84struct gpio_port_saved {
85 u16 fer;
86 u16 data;
87 u16 dir;
88 u16 inen;
89 u32 mux;
90};
91
92/**
93 * struct gpio_pint - Pin interrupt controller device. Multiple ADI GPIO
94 * banks can be mapped into one Pin interrupt controller.
95 *
96 * @node: All gpio_pint instances are added to a global list.
97 * @base: PINT device register base address
98 * @irq: IRQ of the PINT device, it is the parent IRQ of all
99 * GPIO IRQs mapping to this device.
100 * @domain: [0] irq domain of the gpio port, whose hardware interrupts are
101 * mapping to the low 16-bit of the pint registers.
102 * [1] irq domain of the gpio port, whose hardware interrupts are
103 * mapping to the high 16-bit of the pint registers.
104 * @regs: address pointer to the PINT device
105 * @map_count: No more than 2 GPIO banks can be mapped to this PINT device.
106 * @lock: This lock make sure the irq_chip operations to one PINT device
107 * for different GPIO interrrupts are atomic.
108 * @pint_map_port: Set up the mapping between one PINT device and
109 * multiple GPIO banks.
110 */
111struct gpio_pint {
112 struct list_head node;
113 void __iomem *base;
114 int irq;
115 struct irq_domain *domain[2];
116 struct gpio_pint_regs *regs;
117 struct adi_pm_pint_save saved_data;
118 int map_count;
119 spinlock_t lock;
120
121 int (*pint_map_port)(struct gpio_pint *pint, bool assign,
122 u8 map, struct irq_domain *domain);
123};
124
125/**
126 * ADI pin controller
127 *
128 * @dev: a pointer back to containing device
129 * @pctl: the pinctrl device
130 * @soc: SoC data for this specific chip
131 */
132struct adi_pinctrl {
133 struct device *dev;
134 struct pinctrl_dev *pctl;
135 const struct adi_pinctrl_soc_data *soc;
136};
137
138/**
139 * struct gpio_port - GPIO bank device. Multiple ADI GPIO banks can be mapped
140 * into one pin interrupt controller.
141 *
142 * @node: All gpio_port instances are added to a list.
143 * @base: GPIO bank device register base address
144 * @irq_base: base IRQ of the GPIO bank device
145 * @width: PIN number of the GPIO bank device
146 * @regs: address pointer to the GPIO bank device
147 * @saved_data: registers that should be saved between PM operations.
148 * @dev: device structure of this GPIO bank
149 * @pint: GPIO PINT device that this GPIO bank mapped to
150 * @pint_map: GIOP bank mapping code in PINT device
151 * @pint_assign: The 32-bit PINT registers can be divided into 2 parts. A
152 * GPIO bank can be mapped into either low 16 bits[0] or high 16
153 * bits[1] of each PINT register.
154 * @lock: This lock make sure the irq_chip operations to one PINT device
155 * for different GPIO interrrupts are atomic.
156 * @chip: abstract a GPIO controller
157 * @domain: The irq domain owned by the GPIO port.
158 * @rsvmap: Reservation map array for each pin in the GPIO bank
159 */
160struct gpio_port {
161 struct list_head node;
162 void __iomem *base;
163 unsigned int irq_base;
164 unsigned int width;
165 struct gpio_port_t *regs;
166 struct gpio_port_saved saved_data;
167 struct device *dev;
168
169 struct gpio_pint *pint;
170 u8 pint_map;
171 bool pint_assign;
172
173 spinlock_t lock;
174 struct gpio_chip chip;
175 struct irq_domain *domain;
176};
177
178static inline u8 pin_to_offset(struct pinctrl_gpio_range *range, unsigned pin)
179{
180 return pin - range->pin_base;
181}
182
183static inline u32 hwirq_to_pintbit(struct gpio_port *port, int hwirq)
184{
185 return port->pint_assign ? BIT(hwirq) << PINT_HI_OFFSET : BIT(hwirq);
186}
187
188static struct gpio_pint *find_gpio_pint(unsigned id)
189{
190 struct gpio_pint *pint;
191 int i = 0;
192
193 list_for_each_entry(pint, &adi_pint_list, node) {
194 if (id == i)
195 return pint;
196 i++;
197 }
198
199 return NULL;
200}
201
202static inline void port_setup(struct gpio_port *port, unsigned offset,
203 bool use_for_gpio)
204{
205 struct gpio_port_t *regs = port->regs;
206
207 if (use_for_gpio)
208 writew(readw(&regs->port_fer) & ~BIT(offset),
209 &regs->port_fer);
210 else
211 writew(readw(&regs->port_fer) | BIT(offset), &regs->port_fer);
212}
213
214static inline void portmux_setup(struct gpio_port *port, unsigned offset,
215 unsigned short function)
216{
217 struct gpio_port_t *regs = port->regs;
218 u32 pmux;
219
220 pmux = readl(&regs->port_mux);
221
222 /* The function field of each pin has 2 consecutive bits in
223 * the mux register.
224 */
225 pmux &= ~(0x3 << (2 * offset));
226 pmux |= (function & 0x3) << (2 * offset);
227
228 writel(pmux, &regs->port_mux);
229}
230
231static inline u16 get_portmux(struct gpio_port *port, unsigned offset)
232{
233 struct gpio_port_t *regs = port->regs;
234 u32 pmux = readl(&regs->port_mux);
235
236 /* The function field of each pin has 2 consecutive bits in
237 * the mux register.
238 */
239 return pmux >> (2 * offset) & 0x3;
240}
241
242static void adi_gpio_ack_irq(struct irq_data *d)
243{
244 unsigned long flags;
245 struct gpio_port *port = irq_data_get_irq_chip_data(d);
246 struct gpio_pint_regs *regs = port->pint->regs;
247 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
248
249 spin_lock_irqsave(&port->lock, flags);
250 spin_lock(&port->pint->lock);
251
252 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
253 if (readl(&regs->invert_set) & pintbit)
254 writel(pintbit, &regs->invert_clear);
255 else
256 writel(pintbit, &regs->invert_set);
257 }
258
259 writel(pintbit, &regs->request);
260
261 spin_unlock(&port->pint->lock);
262 spin_unlock_irqrestore(&port->lock, flags);
263}
264
265static void adi_gpio_mask_ack_irq(struct irq_data *d)
266{
267 unsigned long flags;
268 struct gpio_port *port = irq_data_get_irq_chip_data(d);
269 struct gpio_pint_regs *regs = port->pint->regs;
270 unsigned pintbit = hwirq_to_pintbit(port, d->hwirq);
271
272 spin_lock_irqsave(&port->lock, flags);
273 spin_lock(&port->pint->lock);
274
275 if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
276 if (readl(&regs->invert_set) & pintbit)
277 writel(pintbit, &regs->invert_clear);
278 else
279 writel(pintbit, &regs->invert_set);
280 }
281
282 writel(pintbit, &regs->request);
283 writel(pintbit, &regs->mask_clear);
284
285 spin_unlock(&port->pint->lock);
286 spin_unlock_irqrestore(&port->lock, flags);
287}
288
289static void adi_gpio_mask_irq(struct irq_data *d)
290{
291 unsigned long flags;
292 struct gpio_port *port = irq_data_get_irq_chip_data(d);
293 struct gpio_pint_regs *regs = port->pint->regs;
294
295 spin_lock_irqsave(&port->lock, flags);
296 spin_lock(&port->pint->lock);
297
298 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_clear);
299
300 spin_unlock(&port->pint->lock);
301 spin_unlock_irqrestore(&port->lock, flags);
302}
303
304static void adi_gpio_unmask_irq(struct irq_data *d)
305{
306 unsigned long flags;
307 struct gpio_port *port = irq_data_get_irq_chip_data(d);
308 struct gpio_pint_regs *regs = port->pint->regs;
309
310 spin_lock_irqsave(&port->lock, flags);
311 spin_lock(&port->pint->lock);
312
313 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_set);
314
315 spin_unlock(&port->pint->lock);
316 spin_unlock_irqrestore(&port->lock, flags);
317}
318
319static unsigned int adi_gpio_irq_startup(struct irq_data *d)
320{
321 unsigned long flags;
322 struct gpio_port *port = irq_data_get_irq_chip_data(d);
323 struct gpio_pint_regs *regs;
324
325 if (!port) {
326 pr_err("GPIO IRQ %d :Not exist\n", d->irq);
327 return -ENODEV;
328 }
329
330 regs = port->pint->regs;
331
332 spin_lock_irqsave(&port->lock, flags);
333 spin_lock(&port->pint->lock);
334
335 port_setup(port, d->hwirq, true);
336 writew(BIT(d->hwirq), &port->regs->dir_clear);
337 writew(readw(&port->regs->inen) | BIT(d->hwirq), &port->regs->inen);
338
339 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_set);
340
341 spin_unlock(&port->pint->lock);
342 spin_unlock_irqrestore(&port->lock, flags);
343
344 return 0;
345}
346
347static void adi_gpio_irq_shutdown(struct irq_data *d)
348{
349 unsigned long flags;
350 struct gpio_port *port = irq_data_get_irq_chip_data(d);
351 struct gpio_pint_regs *regs = port->pint->regs;
352
353 spin_lock_irqsave(&port->lock, flags);
354 spin_lock(&port->pint->lock);
355
356 writel(hwirq_to_pintbit(port, d->hwirq), &regs->mask_clear);
357
358 spin_unlock(&port->pint->lock);
359 spin_unlock_irqrestore(&port->lock, flags);
360}
361
362static int adi_gpio_irq_type(struct irq_data *d, unsigned int type)
363{
364 unsigned long flags;
365 struct gpio_port *port = irq_data_get_irq_chip_data(d);
366 struct gpio_pint_regs *pint_regs;
367 unsigned pintmask;
368 unsigned int irq = d->irq;
369 int ret = 0;
370 char buf[16];
371
372 if (!port) {
373 pr_err("GPIO IRQ %d :Not exist\n", d->irq);
374 return -ENODEV;
375 }
376
377 pint_regs = port->pint->regs;
378
379 pintmask = hwirq_to_pintbit(port, d->hwirq);
380
381 spin_lock_irqsave(&port->lock, flags);
382 spin_lock(&port->pint->lock);
383
384 /* In case of interrupt autodetect, set irq type to edge sensitive. */
385 if (type == IRQ_TYPE_PROBE)
386 type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING;
387
388 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
389 IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) {
390 snprintf(buf, 16, "gpio-irq%d", irq);
391 port_setup(port, d->hwirq, true);
392 } else
393 goto out;
394
395 /* The GPIO interrupt is triggered only when its input value
396 * transfer from 0 to 1. So, invert the input value if the
397 * irq type is low or falling
398 */
399 if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW)))
400 writel(pintmask, &pint_regs->invert_set);
401 else
402 writel(pintmask, &pint_regs->invert_clear);
403
404 /* In edge sensitive case, if the input value of the requested irq
405 * is already 1, invert it.
406 */
407 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
408 if (gpio_get_value(port->chip.base + d->hwirq))
409 writel(pintmask, &pint_regs->invert_set);
410 else
411 writel(pintmask, &pint_regs->invert_clear);
412 }
413
414 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
415 writel(pintmask, &pint_regs->edge_set);
416 __irq_set_handler_locked(irq, handle_edge_irq);
417 } else {
418 writel(pintmask, &pint_regs->edge_clear);
419 __irq_set_handler_locked(irq, handle_level_irq);
420 }
421
422out:
423 spin_unlock(&port->pint->lock);
424 spin_unlock_irqrestore(&port->lock, flags);
425
426 return ret;
427}
428
429#ifdef CONFIG_PM
430static int adi_gpio_set_wake(struct irq_data *d, unsigned int state)
431{
432 struct gpio_port *port = irq_data_get_irq_chip_data(d);
433
434 if (!port || !port->pint || port->pint->irq != d->irq)
435 return -EINVAL;
436
437#ifndef SEC_GCTL
438 adi_internal_set_wake(port->pint->irq, state);
439#endif
440
441 return 0;
442}
443
444static int adi_pint_suspend(void)
445{
446 struct gpio_pint *pint;
447
448 list_for_each_entry(pint, &adi_pint_list, node) {
449 writel(0xffffffff, &pint->regs->mask_clear);
450 pint->saved_data.assign = readl(&pint->regs->assign);
451 pint->saved_data.edge_set = readl(&pint->regs->edge_set);
452 pint->saved_data.invert_set = readl(&pint->regs->invert_set);
453 }
454
455 return 0;
456}
457
458static void adi_pint_resume(void)
459{
460 struct gpio_pint *pint;
461
462 list_for_each_entry(pint, &adi_pint_list, node) {
463 writel(pint->saved_data.assign, &pint->regs->assign);
464 writel(pint->saved_data.edge_set, &pint->regs->edge_set);
465 writel(pint->saved_data.invert_set, &pint->regs->invert_set);
466 }
467}
468
469static int adi_gpio_suspend(void)
470{
471 struct gpio_port *port;
472
473 list_for_each_entry(port, &adi_gpio_port_list, node) {
474 port->saved_data.fer = readw(&port->regs->port_fer);
475 port->saved_data.mux = readl(&port->regs->port_mux);
476 port->saved_data.data = readw(&port->regs->data);
477 port->saved_data.inen = readw(&port->regs->inen);
478 port->saved_data.dir = readw(&port->regs->dir_set);
479 }
480
481 return adi_pint_suspend();
482}
483
484static void adi_gpio_resume(void)
485{
486 struct gpio_port *port;
487
488 adi_pint_resume();
489
490 list_for_each_entry(port, &adi_gpio_port_list, node) {
491 writel(port->saved_data.mux, &port->regs->port_mux);
492 writew(port->saved_data.fer, &port->regs->port_fer);
493 writew(port->saved_data.inen, &port->regs->inen);
494 writew(port->saved_data.data & port->saved_data.dir,
495 &port->regs->data_set);
496 writew(port->saved_data.dir, &port->regs->dir_set);
497 }
498
499}
500
501static struct syscore_ops gpio_pm_syscore_ops = {
502 .suspend = adi_gpio_suspend,
503 .resume = adi_gpio_resume,
504};
505#else /* CONFIG_PM */
506#define adi_gpio_set_wake NULL
507#endif /* CONFIG_PM */
508
509#ifdef CONFIG_IRQ_PREFLOW_FASTEOI
510static inline void preflow_handler(struct irq_desc *desc)
511{
512 if (desc->preflow_handler)
513 desc->preflow_handler(&desc->irq_data);
514}
515#else
516static inline void preflow_handler(struct irq_desc *desc) { }
517#endif
518
519static void adi_gpio_handle_pint_irq(unsigned int inta_irq,
520 struct irq_desc *desc)
521{
522 u32 request;
523 u32 level_mask, hwirq;
524 bool umask = false;
525 struct gpio_pint *pint = irq_desc_get_handler_data(desc);
526 struct irq_chip *chip = irq_desc_get_chip(desc);
527 struct gpio_pint_regs *regs = pint->regs;
528 struct irq_domain *domain;
529
530 preflow_handler(desc);
531 chained_irq_enter(chip, desc);
532
533 request = readl(&regs->request);
534 level_mask = readl(&regs->edge_set) & request;
535
536 hwirq = 0;
537 domain = pint->domain[0];
538 while (request) {
539 /* domain pointer need to be changed only once at IRQ 16 when
540 * we go through IRQ requests from bit 0 to bit 31.
541 */
542 if (hwirq == PINT_HI_OFFSET)
543 domain = pint->domain[1];
544
545 if (request & 1) {
546 if (level_mask & BIT(hwirq)) {
547 umask = true;
548 chained_irq_exit(chip, desc);
549 }
550 generic_handle_irq(irq_find_mapping(domain,
551 hwirq % PINT_HI_OFFSET));
552 }
553
554 hwirq++;
555 request >>= 1;
556 }
557
558 if (!umask)
559 chained_irq_exit(chip, desc);
560}
561
562static struct irq_chip adi_gpio_irqchip = {
563 .name = "GPIO",
564 .irq_ack = adi_gpio_ack_irq,
565 .irq_mask = adi_gpio_mask_irq,
566 .irq_mask_ack = adi_gpio_mask_ack_irq,
567 .irq_unmask = adi_gpio_unmask_irq,
568 .irq_disable = adi_gpio_mask_irq,
569 .irq_enable = adi_gpio_unmask_irq,
570 .irq_set_type = adi_gpio_irq_type,
571 .irq_startup = adi_gpio_irq_startup,
572 .irq_shutdown = adi_gpio_irq_shutdown,
573 .irq_set_wake = adi_gpio_set_wake,
574};
575
576static int adi_get_groups_count(struct pinctrl_dev *pctldev)
577{
578 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
579
580 return pinctrl->soc->ngroups;
581}
582
583static const char *adi_get_group_name(struct pinctrl_dev *pctldev,
584 unsigned selector)
585{
586 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
587
588 return pinctrl->soc->groups[selector].name;
589}
590
591static int adi_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
592 const unsigned **pins,
593 unsigned *num_pins)
594{
595 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
596
597 *pins = pinctrl->soc->groups[selector].pins;
598 *num_pins = pinctrl->soc->groups[selector].num;
599 return 0;
600}
601
602static struct pinctrl_ops adi_pctrl_ops = {
603 .get_groups_count = adi_get_groups_count,
604 .get_group_name = adi_get_group_name,
605 .get_group_pins = adi_get_group_pins,
606};
607
608static int adi_pinmux_enable(struct pinctrl_dev *pctldev, unsigned selector,
609 unsigned group)
610{
611 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
612 struct gpio_port *port;
613 struct pinctrl_gpio_range *range;
614 unsigned long flags;
615 unsigned short *mux, pin;
616
617 mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
618
619 while (*mux) {
620 pin = P_IDENT(*mux);
621
622 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
623 if (range == NULL) /* should not happen */
624 return -ENODEV;
625
626 port = container_of(range->gc, struct gpio_port, chip);
627
628 spin_lock_irqsave(&port->lock, flags);
629
630 portmux_setup(port, pin_to_offset(range, pin),
631 P_FUNCT2MUX(*mux));
632 port_setup(port, pin_to_offset(range, pin), false);
633 mux++;
634
635 spin_unlock_irqrestore(&port->lock, flags);
636 }
637
638 return 0;
639}
640
641static void adi_pinmux_disable(struct pinctrl_dev *pctldev, unsigned selector,
642 unsigned group)
643{
644 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
645 struct gpio_port *port;
646 struct pinctrl_gpio_range *range;
647 unsigned long flags;
648 unsigned short *mux, pin;
649
650 mux = (unsigned short *)pinctrl->soc->functions[selector].mux;
651
652 while (*mux) {
653 pin = P_IDENT(*mux);
654
655 range = pinctrl_find_gpio_range_from_pin(pctldev, pin);
656 if (range == NULL) /* should not happen */
657 return;
658
659 port = container_of(range->gc, struct gpio_port, chip);
660
661 spin_lock_irqsave(&port->lock, flags);
662
663 port_setup(port, pin_to_offset(range, pin), true);
664 mux++;
665
666 spin_unlock_irqrestore(&port->lock, flags);
667 }
668}
669
670static int adi_pinmux_get_funcs_count(struct pinctrl_dev *pctldev)
671{
672 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
673
674 return pinctrl->soc->nfunctions;
675}
676
677static const char *adi_pinmux_get_func_name(struct pinctrl_dev *pctldev,
678 unsigned selector)
679{
680 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
681
682 return pinctrl->soc->functions[selector].name;
683}
684
685static int adi_pinmux_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
686 const char * const **groups,
687 unsigned * const num_groups)
688{
689 struct adi_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctldev);
690
691 *groups = pinctrl->soc->functions[selector].groups;
692 *num_groups = pinctrl->soc->functions[selector].num_groups;
693 return 0;
694}
695
696static int adi_pinmux_request_gpio(struct pinctrl_dev *pctldev,
697 struct pinctrl_gpio_range *range, unsigned pin)
698{
699 struct gpio_port *port;
700 unsigned long flags;
701 u8 offset;
702
703 port = container_of(range->gc, struct gpio_port, chip);
704 offset = pin_to_offset(range, pin);
705
706 spin_lock_irqsave(&port->lock, flags);
707
708 port_setup(port, offset, true);
709
710 spin_unlock_irqrestore(&port->lock, flags);
711
712 return 0;
713}
714
715static struct pinmux_ops adi_pinmux_ops = {
716 .enable = adi_pinmux_enable,
717 .disable = adi_pinmux_disable,
718 .get_functions_count = adi_pinmux_get_funcs_count,
719 .get_function_name = adi_pinmux_get_func_name,
720 .get_function_groups = adi_pinmux_get_groups,
721 .gpio_request_enable = adi_pinmux_request_gpio,
722};
723
724
725static struct pinctrl_desc adi_pinmux_desc = {
726 .name = DRIVER_NAME,
727 .pctlops = &adi_pctrl_ops,
728 .pmxops = &adi_pinmux_ops,
729 .owner = THIS_MODULE,
730};
731
732static int adi_gpio_request(struct gpio_chip *chip, unsigned offset)
733{
734 return pinctrl_request_gpio(chip->base + offset);
735}
736
737static void adi_gpio_free(struct gpio_chip *chip, unsigned offset)
738{
739 pinctrl_free_gpio(chip->base + offset);
740}
741
742static int adi_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
743{
744 struct gpio_port *port;
745 unsigned long flags;
746
747 port = container_of(chip, struct gpio_port, chip);
748
749 spin_lock_irqsave(&port->lock, flags);
750
751 writew(BIT(offset), &port->regs->dir_clear);
752 writew(readw(&port->regs->inen) | BIT(offset), &port->regs->inen);
753
754 spin_unlock_irqrestore(&port->lock, flags);
755
756 return 0;
757}
758
759static void adi_gpio_set_value(struct gpio_chip *chip, unsigned offset,
760 int value)
761{
762 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
763 struct gpio_port_t *regs = port->regs;
764 unsigned long flags;
765
766 spin_lock_irqsave(&port->lock, flags);
767
768 if (value)
769 writew(BIT(offset), &regs->data_set);
770 else
771 writew(BIT(offset), &regs->data_clear);
772
773 spin_unlock_irqrestore(&port->lock, flags);
774}
775
776static int adi_gpio_direction_output(struct gpio_chip *chip, unsigned offset,
777 int value)
778{
779 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
780 struct gpio_port_t *regs = port->regs;
781 unsigned long flags;
782
783 spin_lock_irqsave(&port->lock, flags);
784
785 writew(readw(&regs->inen) & ~BIT(offset), &regs->inen);
786 if (value)
787 writew(BIT(offset), &regs->data_set);
788 else
789 writew(BIT(offset), &regs->data_clear);
790 writew(BIT(offset), &regs->dir_set);
791
792 spin_unlock_irqrestore(&port->lock, flags);
793
794 return 0;
795}
796
797static int adi_gpio_get_value(struct gpio_chip *chip, unsigned offset)
798{
799 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
800 struct gpio_port_t *regs = port->regs;
801 unsigned long flags;
802 int ret;
803
804 spin_lock_irqsave(&port->lock, flags);
805
806 ret = !!(readw(&regs->data) & BIT(offset));
807
808 spin_unlock_irqrestore(&port->lock, flags);
809
810 return ret;
811}
812
813static int adi_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
814{
815 struct gpio_port *port = container_of(chip, struct gpio_port, chip);
816
817 if (port->irq_base >= 0)
818 return irq_find_mapping(port->domain, offset);
819 else
820 return irq_create_mapping(port->domain, offset);
821}
822
823static int adi_pint_map_port(struct gpio_pint *pint, bool assign, u8 map,
824 struct irq_domain *domain)
825{
826 struct gpio_pint_regs *regs = pint->regs;
827 u32 map_mask;
828
829 if (pint->map_count > 1)
830 return -EINVAL;
831
832 pint->map_count++;
833
834 /* The map_mask of each gpio port is a 16-bit duplicate
835 * of the 8-bit map. It can be set to either high 16 bits or low
836 * 16 bits of the pint assignment register.
837 */
838 map_mask = (map << 8) | map;
839 if (assign) {
840 map_mask <<= PINT_HI_OFFSET;
841 writel((readl(&regs->assign) & 0xFFFF) | map_mask,
842 &regs->assign);
843 } else
844 writel((readl(&regs->assign) & 0xFFFF0000) | map_mask,
845 &regs->assign);
846
847 pint->domain[assign] = domain;
848
849 return 0;
850}
851
852static int adi_gpio_pint_probe(struct platform_device *pdev)
853{
854 struct device *dev = &pdev->dev;
855 struct resource *res;
856 struct gpio_pint *pint;
857
858 pint = devm_kzalloc(dev, sizeof(struct gpio_pint), GFP_KERNEL);
859 if (!pint) {
860 dev_err(dev, "Memory alloc failed\n");
861 return -ENOMEM;
862 }
863
864 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
865 pint->base = devm_ioremap_resource(dev, res);
866 if (IS_ERR(pint->base))
867 return PTR_ERR(pint->base);
868
869 pint->regs = (struct gpio_pint_regs *)pint->base;
870
871 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
872 if (!res) {
873 dev_err(dev, "Invalid IRQ resource\n");
874 return -ENODEV;
875 }
876
877 spin_lock_init(&pint->lock);
878
879 pint->irq = res->start;
880 pint->pint_map_port = adi_pint_map_port;
881 platform_set_drvdata(pdev, pint);
882
883 irq_set_chained_handler(pint->irq, adi_gpio_handle_pint_irq);
884 irq_set_handler_data(pint->irq, pint);
885
886 list_add_tail(&pint->node, &adi_pint_list);
887
888 return 0;
889}
890
891static int adi_gpio_pint_remove(struct platform_device *pdev)
892{
893 struct gpio_pint *pint = platform_get_drvdata(pdev);
894
895 list_del(&pint->node);
896 irq_set_handler(pint->irq, handle_simple_irq);
897
898 return 0;
899}
900
901static int adi_gpio_irq_map(struct irq_domain *d, unsigned int irq,
902 irq_hw_number_t hwirq)
903{
904 struct gpio_port *port = d->host_data;
905
906 if (!port)
907 return -EINVAL;
908
909 irq_set_chip_data(irq, port);
910 irq_set_chip_and_handler(irq, &adi_gpio_irqchip,
911 handle_level_irq);
912
913 return 0;
914}
915
916const struct irq_domain_ops adi_gpio_irq_domain_ops = {
917 .map = adi_gpio_irq_map,
918 .xlate = irq_domain_xlate_onecell,
919};
920
921static int adi_gpio_init_int(struct gpio_port *port)
922{
923 struct device_node *node = port->dev->of_node;
924 struct gpio_pint *pint = port->pint;
925 int ret;
926
927 port->domain = irq_domain_add_linear(node, port->width,
928 &adi_gpio_irq_domain_ops, port);
929 if (!port->domain) {
930 dev_err(port->dev, "Failed to create irqdomain\n");
931 return -ENOSYS;
932 }
933
934 /* According to BF54x and BF60x HRM, pin interrupt devices are not
935 * part of the GPIO port device. in GPIO interrupt mode, the GPIO
936 * pins of multiple port devices can be routed into one pin interrupt
937 * device. The mapping can be configured by setting pint assignment
938 * register with the mapping value of different GPIO port. This is
939 * done via function pint_map_port().
940 */
941 ret = pint->pint_map_port(port->pint, port->pint_assign,
942 port->pint_map, port->domain);
943 if (ret)
944 return ret;
945
946 if (port->irq_base >= 0) {
947 ret = irq_create_strict_mappings(port->domain, port->irq_base,
948 0, port->width);
949 if (ret) {
950 dev_err(port->dev, "Couldn't associate to domain\n");
951 return ret;
952 }
953 }
954
955 return 0;
956}
957
958#define DEVNAME_SIZE 16
959
960static int adi_gpio_probe(struct platform_device *pdev)
961{
962 struct device *dev = &pdev->dev;
963 const struct adi_pinctrl_gpio_platform_data *pdata;
964 struct resource *res;
965 struct gpio_port *port;
966 char pinctrl_devname[DEVNAME_SIZE];
967 static int gpio;
968 int ret = 0, ret1;
969
970 pdata = dev->platform_data;
971 if (!pdata)
972 return -EINVAL;
973
974 port = devm_kzalloc(dev, sizeof(struct gpio_port), GFP_KERNEL);
975 if (!port) {
976 dev_err(dev, "Memory alloc failed\n");
977 return -ENOMEM;
978 }
979
980 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
981 port->base = devm_ioremap_resource(dev, res);
982 if (IS_ERR(port->base))
983 return PTR_ERR(port->base);
984
985 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
986 if (!res)
987 port->irq_base = -1;
988 else
989 port->irq_base = res->start;
990
991 port->width = pdata->port_width;
992 port->dev = dev;
993 port->regs = (struct gpio_port_t *)port->base;
994 port->pint_assign = pdata->pint_assign;
995 port->pint_map = pdata->pint_map;
996
997 port->pint = find_gpio_pint(pdata->pint_id);
998 if (port->pint) {
999 ret = adi_gpio_init_int(port);
1000 if (ret)
1001 return ret;
1002 }
1003
1004 spin_lock_init(&port->lock);
1005
1006 platform_set_drvdata(pdev, port);
1007
1008 port->chip.label = "adi-gpio";
1009 port->chip.direction_input = adi_gpio_direction_input;
1010 port->chip.get = adi_gpio_get_value;
1011 port->chip.direction_output = adi_gpio_direction_output;
1012 port->chip.set = adi_gpio_set_value;
1013 port->chip.request = adi_gpio_request;
1014 port->chip.free = adi_gpio_free;
1015 port->chip.to_irq = adi_gpio_to_irq;
1016 if (pdata->port_gpio_base > 0)
1017 port->chip.base = pdata->port_gpio_base;
1018 else
1019 port->chip.base = gpio;
1020 port->chip.ngpio = port->width;
1021 gpio = port->chip.base + port->width;
1022
1023 ret = gpiochip_add(&port->chip);
1024 if (ret) {
1025 dev_err(&pdev->dev, "Fail to add GPIO chip.\n");
1026 goto out_remove_domain;
1027 }
1028
1029 /* Add gpio pin range */
1030 snprintf(pinctrl_devname, DEVNAME_SIZE, "pinctrl-adi2.%d",
1031 pdata->pinctrl_id);
1032 pinctrl_devname[DEVNAME_SIZE - 1] = 0;
1033 ret = gpiochip_add_pin_range(&port->chip, pinctrl_devname,
1034 0, pdata->port_pin_base, port->width);
1035 if (ret) {
1036 dev_err(&pdev->dev, "Fail to add pin range to %s.\n",
1037 pinctrl_devname);
1038 goto out_remove_gpiochip;
1039 }
1040
1041 list_add_tail(&port->node, &adi_gpio_port_list);
1042
1043 return 0;
1044
1045out_remove_gpiochip:
1046 ret1 = gpiochip_remove(&port->chip);
1047out_remove_domain:
1048 if (port->pint)
1049 irq_domain_remove(port->domain);
1050
1051 return ret;
1052}
1053
1054static int adi_gpio_remove(struct platform_device *pdev)
1055{
1056 struct gpio_port *port = platform_get_drvdata(pdev);
1057 int ret;
1058 u8 offset;
1059
1060 list_del(&port->node);
1061 gpiochip_remove_pin_ranges(&port->chip);
1062 ret = gpiochip_remove(&port->chip);
1063 if (port->pint) {
1064 for (offset = 0; offset < port->width; offset++)
1065 irq_dispose_mapping(irq_find_mapping(port->domain,
1066 offset));
1067 irq_domain_remove(port->domain);
1068 }
1069
1070 return ret;
1071}
1072
1073static int adi_pinctrl_probe(struct platform_device *pdev)
1074{
1075 struct adi_pinctrl *pinctrl;
1076
1077 pinctrl = devm_kzalloc(&pdev->dev, sizeof(*pinctrl), GFP_KERNEL);
1078 if (!pinctrl)
1079 return -ENOMEM;
1080
1081 pinctrl->dev = &pdev->dev;
1082
1083 adi_pinctrl_soc_init(&pinctrl->soc);
1084
1085 adi_pinmux_desc.pins = pinctrl->soc->pins;
1086 adi_pinmux_desc.npins = pinctrl->soc->npins;
1087
1088 /* Now register the pin controller and all pins it handles */
1089 pinctrl->pctl = pinctrl_register(&adi_pinmux_desc, &pdev->dev, pinctrl);
1090 if (!pinctrl->pctl) {
1091 dev_err(&pdev->dev, "could not register pinctrl ADI2 driver\n");
1092 return -EINVAL;
1093 }
1094
1095 platform_set_drvdata(pdev, pinctrl);
1096
1097 return 0;
1098}
1099
1100static int adi_pinctrl_remove(struct platform_device *pdev)
1101{
1102 struct adi_pinctrl *pinctrl = platform_get_drvdata(pdev);
1103
1104 pinctrl_unregister(pinctrl->pctl);
1105
1106 return 0;
1107}
1108
1109static struct platform_driver adi_pinctrl_driver = {
1110 .probe = adi_pinctrl_probe,
1111 .remove = adi_pinctrl_remove,
1112 .driver = {
1113 .name = DRIVER_NAME,
1114 },
1115};
1116
1117static struct platform_driver adi_gpio_pint_driver = {
1118 .probe = adi_gpio_pint_probe,
1119 .remove = adi_gpio_pint_remove,
1120 .driver = {
1121 .name = "adi-gpio-pint",
1122 },
1123};
1124
1125static struct platform_driver adi_gpio_driver = {
1126 .probe = adi_gpio_probe,
1127 .remove = adi_gpio_remove,
1128 .driver = {
1129 .name = "adi-gpio",
1130 },
1131};
1132
1133static int __init adi_pinctrl_setup(void)
1134{
1135 int ret;
1136
1137 ret = platform_driver_register(&adi_pinctrl_driver);
1138 if (ret)
1139 return ret;
1140
1141 ret = platform_driver_register(&adi_gpio_pint_driver);
1142 if (ret)
1143 goto pint_error;
1144
1145 ret = platform_driver_register(&adi_gpio_driver);
1146 if (ret)
1147 goto gpio_error;
1148
1149#ifdef CONFIG_PM
1150 register_syscore_ops(&gpio_pm_syscore_ops);
1151#endif
1152 return ret;
1153gpio_error:
1154 platform_driver_unregister(&adi_gpio_pint_driver);
1155pint_error:
1156 platform_driver_unregister(&adi_pinctrl_driver);
1157
1158 return ret;
1159}
1160arch_initcall(adi_pinctrl_setup);
1161
1162MODULE_AUTHOR("Sonic Zhang <sonic.zhang@analog.com>");
1163MODULE_DESCRIPTION("ADI gpio2 pin control driver");
1164MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-adi2.h b/drivers/pinctrl/pinctrl-adi2.h
new file mode 100644
index 000000000000..1f06f8df1fa3
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-adi2.h
@@ -0,0 +1,75 @@
1/*
2 * Pinctrl Driver for ADI GPIO2 controller
3 *
4 * Copyright 2007-2013 Analog Devices Inc.
5 *
6 * Licensed under the GPLv2 or later
7 */
8
9#ifndef PINCTRL_PINCTRL_ADI2_H
10#define PINCTRL_PINCTRL_ADI2_H
11
12#include <linux/pinctrl/pinctrl.h>
13
14 /**
15 * struct adi_pin_group - describes a pin group
16 * @name: the name of this pin group
17 * @pins: an array of pins
18 * @num: the number of pins in this array
19 */
20struct adi_pin_group {
21 const char *name;
22 const unsigned *pins;
23 const unsigned num;
24};
25
26#define ADI_PIN_GROUP(n, p) \
27 { \
28 .name = n, \
29 .pins = p, \
30 .num = ARRAY_SIZE(p), \
31 }
32
33 /**
34 * struct adi_pmx_func - describes function mux setting of pin groups
35 * @name: the name of this function mux setting
36 * @groups: an array of pin groups
37 * @num_groups: the number of pin groups in this array
38 * @mux: the function mux setting array, end by zero
39 */
40struct adi_pmx_func {
41 const char *name;
42 const char * const *groups;
43 const unsigned num_groups;
44 const unsigned short *mux;
45};
46
47#define ADI_PMX_FUNCTION(n, g, m) \
48 { \
49 .name = n, \
50 .groups = g, \
51 .num_groups = ARRAY_SIZE(g), \
52 .mux = m, \
53 }
54
55/**
56 * struct adi_pinctrl_soc_data - ADI pin controller per-SoC configuration
57 * @functions: The functions supported on this SoC.
58 * @nfunction: The number of entries in @functions.
59 * @groups: An array describing all pin groups the pin SoC supports.
60 * @ngroups: The number of entries in @groups.
61 * @pins: An array describing all pins the pin controller affects.
62 * @npins: The number of entries in @pins.
63 */
64struct adi_pinctrl_soc_data {
65 const struct adi_pmx_func *functions;
66 int nfunctions;
67 const struct adi_pin_group *groups;
68 int ngroups;
69 const struct pinctrl_pin_desc *pins;
70 int npins;
71};
72
73void adi_pinctrl_soc_init(const struct adi_pinctrl_soc_data **soc);
74
75#endif /* PINCTRL_PINCTRL_ADI2_H */
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
new file mode 100644
index 000000000000..01bffc1d52fd
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -0,0 +1,630 @@
1/*
2 * ams AS3722 pin control and GPIO driver.
3 *
4 * Copyright (c) 2013, NVIDIA Corporation.
5 *
6 * Author: Laxman Dewangan <ldewangan@nvidia.com>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation version 2.
11 *
12 * This program is distributed "as is" WITHOUT ANY WARRANTY of any kind,
13 * whether express or implied; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA
20 * 02111-1307, USA
21 */
22
23#include <linux/delay.h>
24#include <linux/gpio.h>
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/mfd/as3722.h>
28#include <linux/of.h>
29#include <linux/of_device.h>
30#include <linux/platform_device.h>
31#include <linux/pinctrl/consumer.h>
32#include <linux/pinctrl/machine.h>
33#include <linux/pinctrl/pinctrl.h>
34#include <linux/pinctrl/pinconf-generic.h>
35#include <linux/pinctrl/pinconf.h>
36#include <linux/pinctrl/pinmux.h>
37#include <linux/pm.h>
38#include <linux/slab.h>
39
40#include "core.h"
41#include "pinconf.h"
42#include "pinctrl-utils.h"
43
44#define AS3722_PIN_GPIO0 0
45#define AS3722_PIN_GPIO1 1
46#define AS3722_PIN_GPIO2 2
47#define AS3722_PIN_GPIO3 3
48#define AS3722_PIN_GPIO4 4
49#define AS3722_PIN_GPIO5 5
50#define AS3722_PIN_GPIO6 6
51#define AS3722_PIN_GPIO7 7
52#define AS3722_PIN_NUM (AS3722_PIN_GPIO7 + 1)
53
54#define AS3722_GPIO_MODE_PULL_UP BIT(PIN_CONFIG_BIAS_PULL_UP)
55#define AS3722_GPIO_MODE_PULL_DOWN BIT(PIN_CONFIG_BIAS_PULL_DOWN)
56#define AS3722_GPIO_MODE_HIGH_IMPED BIT(PIN_CONFIG_BIAS_HIGH_IMPEDANCE)
57#define AS3722_GPIO_MODE_OPEN_DRAIN BIT(PIN_CONFIG_DRIVE_OPEN_DRAIN)
58
59struct as3722_pin_function {
60 const char *name;
61 const char * const *groups;
62 unsigned ngroups;
63 int mux_option;
64};
65
66struct as3722_gpio_pin_control {
67 bool enable_gpio_invert;
68 unsigned mode_prop;
69 int io_function;
70};
71
72struct as3722_pingroup {
73 const char *name;
74 const unsigned pins[1];
75 unsigned npins;
76};
77
78struct as3722_pctrl_info {
79 struct device *dev;
80 struct pinctrl_dev *pctl;
81 struct as3722 *as3722;
82 struct gpio_chip gpio_chip;
83 int pins_current_opt[AS3722_PIN_NUM];
84 const struct as3722_pin_function *functions;
85 unsigned num_functions;
86 const struct as3722_pingroup *pin_groups;
87 int num_pin_groups;
88 const struct pinctrl_pin_desc *pins;
89 unsigned num_pins;
90 struct as3722_gpio_pin_control gpio_control[AS3722_PIN_NUM];
91};
92
93static const struct pinctrl_pin_desc as3722_pins_desc[] = {
94 PINCTRL_PIN(AS3722_PIN_GPIO0, "gpio0"),
95 PINCTRL_PIN(AS3722_PIN_GPIO1, "gpio1"),
96 PINCTRL_PIN(AS3722_PIN_GPIO2, "gpio2"),
97 PINCTRL_PIN(AS3722_PIN_GPIO3, "gpio3"),
98 PINCTRL_PIN(AS3722_PIN_GPIO4, "gpio4"),
99 PINCTRL_PIN(AS3722_PIN_GPIO5, "gpio5"),
100 PINCTRL_PIN(AS3722_PIN_GPIO6, "gpio6"),
101 PINCTRL_PIN(AS3722_PIN_GPIO7, "gpio7"),
102};
103
104static const char * const gpio_groups[] = {
105 "gpio0",
106 "gpio1",
107 "gpio2",
108 "gpio3",
109 "gpio4",
110 "gpio5",
111 "gpio6",
112 "gpio7",
113};
114
115enum as3722_pinmux_option {
116 AS3722_PINMUX_GPIO = 0,
117 AS3722_PINMUX_INTERRUPT_OUT = 1,
118 AS3722_PINMUX_VSUB_VBAT_UNDEB_LOW_OUT = 2,
119 AS3722_PINMUX_GPIO_INTERRUPT = 3,
120 AS3722_PINMUX_PWM_INPUT = 4,
121 AS3722_PINMUX_VOLTAGE_IN_STBY = 5,
122 AS3722_PINMUX_OC_PG_SD0 = 6,
123 AS3722_PINMUX_PG_OUT = 7,
124 AS3722_PINMUX_CLK32K_OUT = 8,
125 AS3722_PINMUX_WATCHDOG_INPUT = 9,
126 AS3722_PINMUX_SOFT_RESET_IN = 11,
127 AS3722_PINMUX_PWM_OUTPUT = 12,
128 AS3722_PINMUX_VSUB_VBAT_LOW_DEB_OUT = 13,
129 AS3722_PINMUX_OC_PG_SD6 = 14,
130};
131
132#define FUNCTION_GROUP(fname, mux) \
133 { \
134 .name = #fname, \
135 .groups = gpio_groups, \
136 .ngroups = ARRAY_SIZE(gpio_groups), \
137 .mux_option = AS3722_PINMUX_##mux, \
138 }
139
140static const struct as3722_pin_function as3722_pin_function[] = {
141 FUNCTION_GROUP(gpio, GPIO),
142 FUNCTION_GROUP(interrupt-out, INTERRUPT_OUT),
143 FUNCTION_GROUP(gpio-in-interrupt, GPIO_INTERRUPT),
144 FUNCTION_GROUP(vsup-vbat-low-undebounce-out, VSUB_VBAT_UNDEB_LOW_OUT),
145 FUNCTION_GROUP(vsup-vbat-low-debounce-out, VSUB_VBAT_LOW_DEB_OUT),
146 FUNCTION_GROUP(voltage-in-standby, VOLTAGE_IN_STBY),
147 FUNCTION_GROUP(oc-pg-sd0, OC_PG_SD0),
148 FUNCTION_GROUP(oc-pg-sd6, OC_PG_SD6),
149 FUNCTION_GROUP(powergood-out, PG_OUT),
150 FUNCTION_GROUP(pwm-in, PWM_INPUT),
151 FUNCTION_GROUP(pwm-out, PWM_OUTPUT),
152 FUNCTION_GROUP(clk32k-out, CLK32K_OUT),
153 FUNCTION_GROUP(watchdog-in, WATCHDOG_INPUT),
154 FUNCTION_GROUP(soft-reset-in, SOFT_RESET_IN),
155};
156
157#define AS3722_PINGROUP(pg_name, pin_id) \
158 { \
159 .name = #pg_name, \
160 .pins = {AS3722_PIN_##pin_id}, \
161 .npins = 1, \
162 }
163
164static const struct as3722_pingroup as3722_pingroups[] = {
165 AS3722_PINGROUP(gpio0, GPIO0),
166 AS3722_PINGROUP(gpio1, GPIO1),
167 AS3722_PINGROUP(gpio2, GPIO2),
168 AS3722_PINGROUP(gpio3, GPIO3),
169 AS3722_PINGROUP(gpio4, GPIO4),
170 AS3722_PINGROUP(gpio5, GPIO5),
171 AS3722_PINGROUP(gpio6, GPIO6),
172 AS3722_PINGROUP(gpio7, GPIO7),
173};
174
175static int as3722_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
176{
177 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
178
179 return as_pci->num_pin_groups;
180}
181
182static const char *as3722_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
183 unsigned group)
184{
185 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
186
187 return as_pci->pin_groups[group].name;
188}
189
190static int as3722_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
191 unsigned group, const unsigned **pins, unsigned *num_pins)
192{
193 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
194
195 *pins = as_pci->pin_groups[group].pins;
196 *num_pins = as_pci->pin_groups[group].npins;
197 return 0;
198}
199
200static const struct pinctrl_ops as3722_pinctrl_ops = {
201 .get_groups_count = as3722_pinctrl_get_groups_count,
202 .get_group_name = as3722_pinctrl_get_group_name,
203 .get_group_pins = as3722_pinctrl_get_group_pins,
204 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
205 .dt_free_map = pinctrl_utils_dt_free_map,
206};
207
208static int as3722_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
209{
210 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
211
212 return as_pci->num_functions;
213}
214
215static const char *as3722_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
216 unsigned function)
217{
218 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
219
220 return as_pci->functions[function].name;
221}
222
223static int as3722_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
224 unsigned function, const char * const **groups,
225 unsigned * const num_groups)
226{
227 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
228
229 *groups = as_pci->functions[function].groups;
230 *num_groups = as_pci->functions[function].ngroups;
231 return 0;
232}
233
234static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
235 unsigned group)
236{
237 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
238 int gpio_cntr_reg = AS3722_GPIOn_CONTROL_REG(group);
239 u8 val = AS3722_GPIO_IOSF_VAL(as_pci->functions[function].mux_option);
240 int ret;
241
242 dev_dbg(as_pci->dev, "%s(): GPIO %u pin to function %u and val %u\n",
243 __func__, group, function, val);
244
245 ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
246 AS3722_GPIO_IOSF_MASK, val);
247 if (ret < 0) {
248 dev_err(as_pci->dev, "GPIO%d_CTRL_REG update failed %d\n",
249 group, ret);
250 return ret;
251 }
252 as_pci->gpio_control[group].io_function = function;
253 return ret;
254}
255
256static int as3722_pinctrl_gpio_get_mode(unsigned gpio_mode_prop, bool input)
257{
258 if (gpio_mode_prop & AS3722_GPIO_MODE_HIGH_IMPED)
259 return -EINVAL;
260
261 if (gpio_mode_prop & AS3722_GPIO_MODE_OPEN_DRAIN) {
262 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
263 return AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP;
264 return AS3722_GPIO_MODE_IO_OPEN_DRAIN;
265 }
266 if (input) {
267 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_UP)
268 return AS3722_GPIO_MODE_INPUT_PULL_UP;
269 else if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
270 return AS3722_GPIO_MODE_INPUT_PULL_DOWN;
271 return AS3722_GPIO_MODE_INPUT;
272 }
273 if (gpio_mode_prop & AS3722_GPIO_MODE_PULL_DOWN)
274 return AS3722_GPIO_MODE_OUTPUT_VDDL;
275 return AS3722_GPIO_MODE_OUTPUT_VDDH;
276}
277
278static int as3722_pinctrl_gpio_request_enable(struct pinctrl_dev *pctldev,
279 struct pinctrl_gpio_range *range, unsigned offset)
280{
281 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
282
283 if (as_pci->gpio_control[offset].io_function)
284 return -EBUSY;
285 return 0;
286}
287
288static int as3722_pinctrl_gpio_set_direction(struct pinctrl_dev *pctldev,
289 struct pinctrl_gpio_range *range, unsigned offset, bool input)
290{
291 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
292 struct as3722 *as3722 = as_pci->as3722;
293 int mode;
294
295 mode = as3722_pinctrl_gpio_get_mode(
296 as_pci->gpio_control[offset].mode_prop, input);
297 if (mode < 0) {
298 dev_err(as_pci->dev, "%s direction for GPIO %d not supported\n",
299 (input) ? "Input" : "Output", offset);
300 return mode;
301 }
302
303 if (as_pci->gpio_control[offset].enable_gpio_invert)
304 mode |= AS3722_GPIO_INV;
305
306 return as3722_write(as3722, AS3722_GPIOn_CONTROL_REG(offset), mode);
307}
308
309static const struct pinmux_ops as3722_pinmux_ops = {
310 .get_functions_count = as3722_pinctrl_get_funcs_count,
311 .get_function_name = as3722_pinctrl_get_func_name,
312 .get_function_groups = as3722_pinctrl_get_func_groups,
313 .enable = as3722_pinctrl_enable,
314 .gpio_request_enable = as3722_pinctrl_gpio_request_enable,
315 .gpio_set_direction = as3722_pinctrl_gpio_set_direction,
316};
317
318static int as3722_pinconf_get(struct pinctrl_dev *pctldev,
319 unsigned pin, unsigned long *config)
320{
321 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
322 enum pin_config_param param = pinconf_to_config_param(*config);
323 int arg = 0;
324 u16 prop;
325
326 switch (param) {
327 case PIN_CONFIG_BIAS_DISABLE:
328 prop = AS3722_GPIO_MODE_PULL_UP |
329 AS3722_GPIO_MODE_PULL_DOWN;
330 if (!(as_pci->gpio_control[pin].mode_prop & prop))
331 arg = 1;
332 prop = 0;
333 break;
334
335 case PIN_CONFIG_BIAS_PULL_UP:
336 prop = AS3722_GPIO_MODE_PULL_UP;
337 break;
338
339 case PIN_CONFIG_BIAS_PULL_DOWN:
340 prop = AS3722_GPIO_MODE_PULL_DOWN;
341 break;
342
343 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
344 prop = AS3722_GPIO_MODE_OPEN_DRAIN;
345 break;
346
347 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
348 prop = AS3722_GPIO_MODE_HIGH_IMPED;
349 break;
350
351 default:
352 dev_err(as_pci->dev, "Properties not supported\n");
353 return -ENOTSUPP;
354 }
355
356 if (as_pci->gpio_control[pin].mode_prop & prop)
357 arg = 1;
358
359 *config = pinconf_to_config_packed(param, (u16)arg);
360 return 0;
361}
362
363static int as3722_pinconf_set(struct pinctrl_dev *pctldev,
364 unsigned pin, unsigned long *configs,
365 unsigned num_configs)
366{
367 struct as3722_pctrl_info *as_pci = pinctrl_dev_get_drvdata(pctldev);
368 enum pin_config_param param;
369 int mode_prop;
370 int i;
371
372 for (i = 0; i < num_configs; i++) {
373 param = pinconf_to_config_param(configs[i]);
374 mode_prop = as_pci->gpio_control[pin].mode_prop;
375
376 switch (param) {
377 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
378 break;
379
380 case PIN_CONFIG_BIAS_DISABLE:
381 mode_prop &= ~(AS3722_GPIO_MODE_PULL_UP |
382 AS3722_GPIO_MODE_PULL_DOWN);
383 break;
384 case PIN_CONFIG_BIAS_PULL_UP:
385 mode_prop |= AS3722_GPIO_MODE_PULL_UP;
386 break;
387
388 case PIN_CONFIG_BIAS_PULL_DOWN:
389 mode_prop |= AS3722_GPIO_MODE_PULL_DOWN;
390 break;
391
392 case PIN_CONFIG_BIAS_HIGH_IMPEDANCE:
393 mode_prop |= AS3722_GPIO_MODE_HIGH_IMPED;
394 break;
395
396 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
397 mode_prop |= AS3722_GPIO_MODE_OPEN_DRAIN;
398 break;
399
400 default:
401 dev_err(as_pci->dev, "Properties not supported\n");
402 return -ENOTSUPP;
403 }
404
405 as_pci->gpio_control[pin].mode_prop = mode_prop;
406 }
407 return 0;
408}
409
410static const struct pinconf_ops as3722_pinconf_ops = {
411 .pin_config_get = as3722_pinconf_get,
412 .pin_config_set = as3722_pinconf_set,
413};
414
415static struct pinctrl_desc as3722_pinctrl_desc = {
416 .pctlops = &as3722_pinctrl_ops,
417 .pmxops = &as3722_pinmux_ops,
418 .confops = &as3722_pinconf_ops,
419 .owner = THIS_MODULE,
420};
421
422static inline struct as3722_pctrl_info *to_as_pci(struct gpio_chip *chip)
423{
424 return container_of(chip, struct as3722_pctrl_info, gpio_chip);
425}
426
427static int as3722_gpio_get(struct gpio_chip *chip, unsigned offset)
428{
429 struct as3722_pctrl_info *as_pci = to_as_pci(chip);
430 struct as3722 *as3722 = as_pci->as3722;
431 int ret;
432 u32 reg;
433 u32 control;
434 u32 val;
435 int mode;
436 int invert_enable;
437
438 ret = as3722_read(as3722, AS3722_GPIOn_CONTROL_REG(offset), &control);
439 if (ret < 0) {
440 dev_err(as_pci->dev,
441 "GPIO_CONTROL%d_REG read failed: %d\n", offset, ret);
442 return ret;
443 }
444
445 invert_enable = !!(control & AS3722_GPIO_INV);
446 mode = control & AS3722_GPIO_MODE_MASK;
447 switch (mode) {
448 case AS3722_GPIO_MODE_INPUT:
449 case AS3722_GPIO_MODE_INPUT_PULL_UP:
450 case AS3722_GPIO_MODE_INPUT_PULL_DOWN:
451 case AS3722_GPIO_MODE_IO_OPEN_DRAIN:
452 case AS3722_GPIO_MODE_IO_OPEN_DRAIN_PULL_UP:
453 reg = AS3722_GPIO_SIGNAL_IN_REG;
454 break;
455 case AS3722_GPIO_MODE_OUTPUT_VDDH:
456 case AS3722_GPIO_MODE_OUTPUT_VDDL:
457 reg = AS3722_GPIO_SIGNAL_OUT_REG;
458 break;
459 default:
460 return -EINVAL;
461 }
462
463 ret = as3722_read(as3722, reg, &val);
464 if (ret < 0) {
465 dev_err(as_pci->dev,
466 "GPIO_SIGNAL_IN_REG read failed: %d\n", ret);
467 return ret;
468 }
469
470 val = !!(val & AS3722_GPIOn_SIGNAL(offset));
471 return (invert_enable) ? !val : val;
472}
473
474static void as3722_gpio_set(struct gpio_chip *chip, unsigned offset,
475 int value)
476{
477 struct as3722_pctrl_info *as_pci = to_as_pci(chip);
478 struct as3722 *as3722 = as_pci->as3722;
479 int en_invert = as_pci->gpio_control[offset].enable_gpio_invert;
480 u32 val;
481 int ret;
482
483 if (value)
484 val = (en_invert) ? 0 : AS3722_GPIOn_SIGNAL(offset);
485 else
486 val = (en_invert) ? AS3722_GPIOn_SIGNAL(offset) : 0;
487
488 ret = as3722_update_bits(as3722, AS3722_GPIO_SIGNAL_OUT_REG,
489 AS3722_GPIOn_SIGNAL(offset), val);
490 if (ret < 0)
491 dev_err(as_pci->dev,
492 "GPIO_SIGNAL_OUT_REG update failed: %d\n", ret);
493}
494
495static int as3722_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
496{
497 return pinctrl_gpio_direction_input(chip->base + offset);
498}
499
500static int as3722_gpio_direction_output(struct gpio_chip *chip,
501 unsigned offset, int value)
502{
503 as3722_gpio_set(chip, offset, value);
504 return pinctrl_gpio_direction_output(chip->base + offset);
505}
506
507static int as3722_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
508{
509 struct as3722_pctrl_info *as_pci = to_as_pci(chip);
510
511 return as3722_irq_get_virq(as_pci->as3722, offset);
512}
513
514static int as3722_gpio_request(struct gpio_chip *chip, unsigned offset)
515{
516 return pinctrl_request_gpio(chip->base + offset);
517}
518
519static void as3722_gpio_free(struct gpio_chip *chip, unsigned offset)
520{
521 pinctrl_free_gpio(chip->base + offset);
522}
523
524static const struct gpio_chip as3722_gpio_chip = {
525 .label = "as3722-gpio",
526 .owner = THIS_MODULE,
527 .request = as3722_gpio_request,
528 .free = as3722_gpio_free,
529 .get = as3722_gpio_get,
530 .set = as3722_gpio_set,
531 .direction_input = as3722_gpio_direction_input,
532 .direction_output = as3722_gpio_direction_output,
533 .to_irq = as3722_gpio_to_irq,
534 .can_sleep = 1,
535 .ngpio = AS3722_PIN_NUM,
536 .base = -1,
537};
538
539static int as3722_pinctrl_probe(struct platform_device *pdev)
540{
541 struct as3722_pctrl_info *as_pci;
542 int ret;
543 int tret;
544
545 as_pci = devm_kzalloc(&pdev->dev, sizeof(*as_pci), GFP_KERNEL);
546 if (!as_pci)
547 return -ENOMEM;
548
549 as_pci->dev = &pdev->dev;
550 as_pci->dev->of_node = pdev->dev.parent->of_node;
551 as_pci->as3722 = dev_get_drvdata(pdev->dev.parent);
552 platform_set_drvdata(pdev, as_pci);
553
554 as_pci->pins = as3722_pins_desc;
555 as_pci->num_pins = ARRAY_SIZE(as3722_pins_desc);
556 as_pci->functions = as3722_pin_function;
557 as_pci->num_functions = ARRAY_SIZE(as3722_pin_function);
558 as_pci->pin_groups = as3722_pingroups;
559 as_pci->num_pin_groups = ARRAY_SIZE(as3722_pingroups);
560 as3722_pinctrl_desc.name = dev_name(&pdev->dev);
561 as3722_pinctrl_desc.pins = as3722_pins_desc;
562 as3722_pinctrl_desc.npins = ARRAY_SIZE(as3722_pins_desc);
563 as_pci->pctl = pinctrl_register(&as3722_pinctrl_desc,
564 &pdev->dev, as_pci);
565 if (!as_pci->pctl) {
566 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
567 return -EINVAL;
568 }
569
570 as_pci->gpio_chip = as3722_gpio_chip;
571 as_pci->gpio_chip.dev = &pdev->dev;
572 as_pci->gpio_chip.of_node = pdev->dev.parent->of_node;
573 ret = gpiochip_add(&as_pci->gpio_chip);
574 if (ret < 0) {
575 dev_err(&pdev->dev, "Couldn't register gpiochip, %d\n", ret);
576 goto fail_chip_add;
577 }
578
579 ret = gpiochip_add_pin_range(&as_pci->gpio_chip, dev_name(&pdev->dev),
580 0, 0, AS3722_PIN_NUM);
581 if (ret < 0) {
582 dev_err(&pdev->dev, "Couldn't add pin range, %d\n", ret);
583 goto fail_range_add;
584 }
585
586 return 0;
587
588fail_range_add:
589 tret = gpiochip_remove(&as_pci->gpio_chip);
590 if (tret < 0)
591 dev_warn(&pdev->dev, "Couldn't remove gpio chip, %d\n", tret);
592
593fail_chip_add:
594 pinctrl_unregister(as_pci->pctl);
595 return ret;
596}
597
598static int as3722_pinctrl_remove(struct platform_device *pdev)
599{
600 struct as3722_pctrl_info *as_pci = platform_get_drvdata(pdev);
601 int ret;
602
603 ret = gpiochip_remove(&as_pci->gpio_chip);
604 if (ret < 0)
605 return ret;
606 pinctrl_unregister(as_pci->pctl);
607 return 0;
608}
609
610static struct of_device_id as3722_pinctrl_of_match[] = {
611 { .compatible = "ams,as3722-pinctrl", },
612 { },
613};
614MODULE_DEVICE_TABLE(of, as3722_pinctrl_of_match);
615
616static struct platform_driver as3722_pinctrl_driver = {
617 .driver = {
618 .name = "as3722-pinctrl",
619 .owner = THIS_MODULE,
620 .of_match_table = as3722_pinctrl_of_match,
621 },
622 .probe = as3722_pinctrl_probe,
623 .remove = as3722_pinctrl_remove,
624};
625module_platform_driver(as3722_pinctrl_driver);
626
627MODULE_ALIAS("platform:as3722-pinctrl");
628MODULE_DESCRIPTION("AS3722 pin control and GPIO driver");
629MODULE_AUTHOR("Laxman Dewangan<ldewangan@nvidia.com>");
630MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index f350fd2e170e..a7549c4c83b4 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -33,6 +33,7 @@
33 33
34#include "core.h" 34#include "core.h"
35 35
36#define MAX_GPIO_BANKS 5
36#define MAX_NB_GPIO_PER_BANK 32 37#define MAX_NB_GPIO_PER_BANK 32
37 38
38struct at91_pinctrl_mux_ops; 39struct at91_pinctrl_mux_ops;
@@ -144,11 +145,11 @@ struct at91_pinctrl_mux_ops {
144 void (*mux_C_periph)(void __iomem *pio, unsigned mask); 145 void (*mux_C_periph)(void __iomem *pio, unsigned mask);
145 void (*mux_D_periph)(void __iomem *pio, unsigned mask); 146 void (*mux_D_periph)(void __iomem *pio, unsigned mask);
146 bool (*get_deglitch)(void __iomem *pio, unsigned pin); 147 bool (*get_deglitch)(void __iomem *pio, unsigned pin);
147 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool in_on); 148 void (*set_deglitch)(void __iomem *pio, unsigned mask, bool is_on);
148 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div); 149 bool (*get_debounce)(void __iomem *pio, unsigned pin, u32 *div);
149 void (*set_debounce)(void __iomem *pio, unsigned mask, bool in_on, u32 div); 150 void (*set_debounce)(void __iomem *pio, unsigned mask, bool is_on, u32 div);
150 bool (*get_pulldown)(void __iomem *pio, unsigned pin); 151 bool (*get_pulldown)(void __iomem *pio, unsigned pin);
151 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool in_on); 152 void (*set_pulldown)(void __iomem *pio, unsigned mask, bool is_on);
152 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin); 153 bool (*get_schmitt_trig)(void __iomem *pio, unsigned pin);
153 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask); 154 void (*disable_schmitt_trig)(void __iomem *pio, unsigned mask);
154 /* irq */ 155 /* irq */
@@ -243,7 +244,7 @@ static int at91_dt_node_to_map(struct pinctrl_dev *pctldev,
243 int i; 244 int i;
244 245
245 /* 246 /*
246 * first find the group of this node and check if we need create 247 * first find the group of this node and check if we need to create
247 * config maps for pins 248 * config maps for pins
248 */ 249 */
249 grp = at91_pinctrl_find_group_by_name(info, np->name); 250 grp = at91_pinctrl_find_group_by_name(info, np->name);
@@ -417,6 +418,14 @@ static void at91_mux_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
417 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR)); 418 __raw_writel(mask, pio + (is_on ? PIO_IFER : PIO_IFDR));
418} 419}
419 420
421static bool at91_mux_pio3_get_deglitch(void __iomem *pio, unsigned pin)
422{
423 if ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1)
424 return !((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
425
426 return false;
427}
428
420static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on) 429static void at91_mux_pio3_set_deglitch(void __iomem *pio, unsigned mask, bool is_on)
421{ 430{
422 if (is_on) 431 if (is_on)
@@ -428,7 +437,8 @@ static bool at91_mux_pio3_get_debounce(void __iomem *pio, unsigned pin, u32 *div
428{ 437{
429 *div = __raw_readl(pio + PIO_SCDR); 438 *div = __raw_readl(pio + PIO_SCDR);
430 439
431 return (__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1; 440 return ((__raw_readl(pio + PIO_IFSR) >> pin) & 0x1) &&
441 ((__raw_readl(pio + PIO_IFSCSR) >> pin) & 0x1);
432} 442}
433 443
434static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask, 444static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
@@ -438,9 +448,8 @@ static void at91_mux_pio3_set_debounce(void __iomem *pio, unsigned mask,
438 __raw_writel(mask, pio + PIO_IFSCER); 448 __raw_writel(mask, pio + PIO_IFSCER);
439 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR); 449 __raw_writel(div & PIO_SCDR_DIV, pio + PIO_SCDR);
440 __raw_writel(mask, pio + PIO_IFER); 450 __raw_writel(mask, pio + PIO_IFER);
441 } else { 451 } else
442 __raw_writel(mask, pio + PIO_IFDR); 452 __raw_writel(mask, pio + PIO_IFSCDR);
443 }
444} 453}
445 454
446static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin) 455static bool at91_mux_pio3_get_pulldown(void __iomem *pio, unsigned pin)
@@ -478,7 +487,7 @@ static struct at91_pinctrl_mux_ops at91sam9x5_ops = {
478 .mux_B_periph = at91_mux_pio3_set_B_periph, 487 .mux_B_periph = at91_mux_pio3_set_B_periph,
479 .mux_C_periph = at91_mux_pio3_set_C_periph, 488 .mux_C_periph = at91_mux_pio3_set_C_periph,
480 .mux_D_periph = at91_mux_pio3_set_D_periph, 489 .mux_D_periph = at91_mux_pio3_set_D_periph,
481 .get_deglitch = at91_mux_get_deglitch, 490 .get_deglitch = at91_mux_pio3_get_deglitch,
482 .set_deglitch = at91_mux_pio3_set_deglitch, 491 .set_deglitch = at91_mux_pio3_set_deglitch,
483 .get_debounce = at91_mux_pio3_get_debounce, 492 .get_debounce = at91_mux_pio3_get_debounce,
484 .set_debounce = at91_mux_pio3_set_debounce, 493 .set_debounce = at91_mux_pio3_set_debounce,
@@ -564,7 +573,7 @@ static int at91_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
564 info->functions[selector].name, info->groups[group].name); 573 info->functions[selector].name, info->groups[group].name);
565 574
566 /* first check that all the pins of the group are valid with a valid 575 /* first check that all the pins of the group are valid with a valid
567 * paramter */ 576 * parameter */
568 for (i = 0; i < npins; i++) { 577 for (i = 0; i < npins; i++) {
569 pin = &pins_conf[i]; 578 pin = &pins_conf[i];
570 ret = pin_check_config(info, info->groups[group].name, i, pin); 579 ret = pin_check_config(info, info->groups[group].name, i, pin);
@@ -958,7 +967,7 @@ static int at91_pinctrl_probe_dt(struct platform_device *pdev,
958 at91_pinctrl_child_count(info, np); 967 at91_pinctrl_child_count(info, np);
959 968
960 if (info->nbanks < 1) { 969 if (info->nbanks < 1) {
961 dev_err(&pdev->dev, "you need to specify atleast one gpio-controller\n"); 970 dev_err(&pdev->dev, "you need to specify at least one gpio-controller\n");
962 return -EINVAL; 971 return -EINVAL;
963 } 972 }
964 973
@@ -1495,7 +1504,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
1495 if (at91_gpio->pioc_idx) 1504 if (at91_gpio->pioc_idx)
1496 prev = gpio_chips[at91_gpio->pioc_idx - 1]; 1505 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1497 1506
1498 /* The toplevel handler handles one bank of GPIOs, except 1507 /* The top level handler handles one bank of GPIOs, except
1499 * on some SoC it can handles up to three... 1508 * on some SoC it can handles up to three...
1500 * We only set up the handler for the first of the list. 1509 * We only set up the handler for the first of the list.
1501 */ 1510 */
@@ -1671,7 +1680,7 @@ static struct platform_driver at91_gpio_driver = {
1671 .driver = { 1680 .driver = {
1672 .name = "gpio-at91", 1681 .name = "gpio-at91",
1673 .owner = THIS_MODULE, 1682 .owner = THIS_MODULE,
1674 .of_match_table = of_match_ptr(at91_gpio_of_match), 1683 .of_match_table = at91_gpio_of_match,
1675 }, 1684 },
1676 .probe = at91_gpio_probe, 1685 .probe = at91_gpio_probe,
1677}; 1686};
@@ -1680,7 +1689,7 @@ static struct platform_driver at91_pinctrl_driver = {
1680 .driver = { 1689 .driver = {
1681 .name = "pinctrl-at91", 1690 .name = "pinctrl-at91",
1682 .owner = THIS_MODULE, 1691 .owner = THIS_MODULE,
1683 .of_match_table = of_match_ptr(at91_pinctrl_of_match), 1692 .of_match_table = at91_pinctrl_of_match,
1684 }, 1693 },
1685 .probe = at91_pinctrl_probe, 1694 .probe = at91_pinctrl_probe,
1686 .remove = at91_pinctrl_remove, 1695 .remove = at91_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-exynos5440.c b/drivers/pinctrl/pinctrl-exynos5440.c
index 544d469c5a7b..8fe2ab0a7698 100644
--- a/drivers/pinctrl/pinctrl-exynos5440.c
+++ b/drivers/pinctrl/pinctrl-exynos5440.c
@@ -1048,7 +1048,7 @@ static struct platform_driver exynos5440_pinctrl_driver = {
1048 .driver = { 1048 .driver = {
1049 .name = "exynos5440-pinctrl", 1049 .name = "exynos5440-pinctrl",
1050 .owner = THIS_MODULE, 1050 .owner = THIS_MODULE,
1051 .of_match_table = of_match_ptr(exynos5440_pinctrl_dt_match), 1051 .of_match_table = exynos5440_pinctrl_dt_match,
1052 }, 1052 },
1053}; 1053};
1054 1054
diff --git a/drivers/pinctrl/pinctrl-imx.c b/drivers/pinctrl/pinctrl-imx.c
index d78dd813bff9..4779b8e0eee8 100644
--- a/drivers/pinctrl/pinctrl-imx.c
+++ b/drivers/pinctrl/pinctrl-imx.c
@@ -245,11 +245,11 @@ static int imx_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
245 * The input_reg[i] here is actually some IOMUXC general 245 * The input_reg[i] here is actually some IOMUXC general
246 * purpose register, not regular select input register. 246 * purpose register, not regular select input register.
247 */ 247 */
248 val = readl(ipctl->base + pin->input_val); 248 val = readl(ipctl->base + pin->input_reg);
249 val &= ~mask; 249 val &= ~mask;
250 val |= select << shift; 250 val |= select << shift;
251 writel(val, ipctl->base + pin->input_val); 251 writel(val, ipctl->base + pin->input_reg);
252 } else if (pin->input_val) { 252 } else if (pin->input_reg) {
253 /* 253 /*
254 * Regular select input register can never be at offset 254 * Regular select input register can never be at offset
255 * 0, and we only print register value for regular case. 255 * 0, and we only print register value for regular case.
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c
new file mode 100644
index 000000000000..f77914ac081a
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -0,0 +1,653 @@
1/*
2 * Core driver for the imx pin controller in imx1/21/27
3 *
4 * Copyright (C) 2013 Pengutronix
5 * Author: Markus Pargmann <mpa@pengutronix.de>
6 *
7 * Based on pinctrl-imx.c:
8 * Author: Dong Aisheng <dong.aisheng@linaro.org>
9 * Copyright (C) 2012 Freescale Semiconductor, Inc.
10 * Copyright (C) 2012 Linaro Ltd.
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 */
17
18#include <linux/bitops.h>
19#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/io.h>
22#include <linux/module.h>
23#include <linux/of.h>
24#include <linux/of_device.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/pinctrl/pinconf.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/slab.h>
30
31#include "core.h"
32#include "pinctrl-imx1.h"
33
34struct imx1_pinctrl {
35 struct device *dev;
36 struct pinctrl_dev *pctl;
37 void __iomem *base;
38 const struct imx1_pinctrl_soc_info *info;
39};
40
41/*
42 * MX1 register offsets
43 */
44
45#define MX1_DDIR 0x00
46#define MX1_OCR 0x04
47#define MX1_ICONFA 0x0c
48#define MX1_ICONFB 0x10
49#define MX1_GIUS 0x20
50#define MX1_GPR 0x38
51#define MX1_PUEN 0x40
52
53#define MX1_PORT_STRIDE 0x100
54
55
56/*
57 * MUX_ID format defines
58 */
59#define MX1_MUX_FUNCTION(val) (BIT(0) & val)
60#define MX1_MUX_GPIO(val) ((BIT(1) & val) >> 1)
61#define MX1_MUX_DIR(val) ((BIT(2) & val) >> 2)
62#define MX1_MUX_OCONF(val) (((BIT(4) | BIT(5)) & val) >> 4)
63#define MX1_MUX_ICONFA(val) (((BIT(8) | BIT(9)) & val) >> 8)
64#define MX1_MUX_ICONFB(val) (((BIT(10) | BIT(11)) & val) >> 10)
65
66
67/*
68 * IMX1 IOMUXC manages the pins based on ports. Each port has 32 pins. IOMUX
69 * control register are seperated into function, output configuration, input
70 * configuration A, input configuration B, GPIO in use and data direction.
71 *
72 * Those controls that are represented by 1 bit have a direct mapping between
73 * bit position and pin id. If they are represented by 2 bit, the lower 16 pins
74 * are in the first register and the upper 16 pins in the second (next)
75 * register. pin_id is stored in bit (pin_id%16)*2 and the bit above.
76 */
77
78/*
79 * Calculates the register offset from a pin_id
80 */
81static void __iomem *imx1_mem(struct imx1_pinctrl *ipctl, unsigned int pin_id)
82{
83 unsigned int port = pin_id / 32;
84 return ipctl->base + port * MX1_PORT_STRIDE;
85}
86
87/*
88 * Write to a register with 2 bits per pin. The function will automatically
89 * use the next register if the pin is managed in the second register.
90 */
91static void imx1_write_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
92 u32 value, u32 reg_offset)
93{
94 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
95 int offset = (pin_id % 16) * 2; /* offset, regardless of register used */
96 int mask = ~(0x3 << offset); /* Mask for 2 bits at offset */
97 u32 old_val;
98 u32 new_val;
99
100 dev_dbg(ipctl->dev, "write: register 0x%p offset %d value 0x%x\n",
101 reg, offset, value);
102
103 /* Use the next register if the pin's port pin number is >=16 */
104 if (pin_id % 32 >= 16)
105 reg += 0x04;
106
107 /* Get current state of pins */
108 old_val = readl(reg);
109 old_val &= mask;
110
111 new_val = value & 0x3; /* Make sure value is really 2 bit */
112 new_val <<= offset;
113 new_val |= old_val;/* Set new state for pin_id */
114
115 writel(new_val, reg);
116}
117
118static void imx1_write_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
119 u32 value, u32 reg_offset)
120{
121 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
122 int offset = pin_id % 32;
123 int mask = ~BIT_MASK(offset);
124 u32 old_val;
125 u32 new_val;
126
127 /* Get current state of pins */
128 old_val = readl(reg);
129 old_val &= mask;
130
131 new_val = value & 0x1; /* Make sure value is really 1 bit */
132 new_val <<= offset;
133 new_val |= old_val;/* Set new state for pin_id */
134
135 writel(new_val, reg);
136}
137
138static int imx1_read_2bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
139 u32 reg_offset)
140{
141 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
142 int offset = pin_id % 16;
143
144 /* Use the next register if the pin's port pin number is >=16 */
145 if (pin_id % 32 >= 16)
146 reg += 0x04;
147
148 return (readl(reg) & (BIT(offset) | BIT(offset+1))) >> offset;
149}
150
151static int imx1_read_bit(struct imx1_pinctrl *ipctl, unsigned int pin_id,
152 u32 reg_offset)
153{
154 void __iomem *reg = imx1_mem(ipctl, pin_id) + reg_offset;
155 int offset = pin_id % 32;
156
157 return !!(readl(reg) & BIT(offset));
158}
159
160static const inline struct imx1_pin_group *imx1_pinctrl_find_group_by_name(
161 const struct imx1_pinctrl_soc_info *info,
162 const char *name)
163{
164 const struct imx1_pin_group *grp = NULL;
165 int i;
166
167 for (i = 0; i < info->ngroups; i++) {
168 if (!strcmp(info->groups[i].name, name)) {
169 grp = &info->groups[i];
170 break;
171 }
172 }
173
174 return grp;
175}
176
177static int imx1_get_groups_count(struct pinctrl_dev *pctldev)
178{
179 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
180 const struct imx1_pinctrl_soc_info *info = ipctl->info;
181
182 return info->ngroups;
183}
184
185static const char *imx1_get_group_name(struct pinctrl_dev *pctldev,
186 unsigned selector)
187{
188 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
189 const struct imx1_pinctrl_soc_info *info = ipctl->info;
190
191 return info->groups[selector].name;
192}
193
194static int imx1_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector,
195 const unsigned int **pins,
196 unsigned *npins)
197{
198 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
199 const struct imx1_pinctrl_soc_info *info = ipctl->info;
200
201 if (selector >= info->ngroups)
202 return -EINVAL;
203
204 *pins = info->groups[selector].pin_ids;
205 *npins = info->groups[selector].npins;
206
207 return 0;
208}
209
210static void imx1_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s,
211 unsigned offset)
212{
213 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
214
215 seq_printf(s, "GPIO %d, function %d, direction %d, oconf %d, iconfa %d, iconfb %d",
216 imx1_read_bit(ipctl, offset, MX1_GIUS),
217 imx1_read_bit(ipctl, offset, MX1_GPR),
218 imx1_read_bit(ipctl, offset, MX1_DDIR),
219 imx1_read_2bit(ipctl, offset, MX1_OCR),
220 imx1_read_2bit(ipctl, offset, MX1_ICONFA),
221 imx1_read_2bit(ipctl, offset, MX1_ICONFB));
222}
223
224static int imx1_dt_node_to_map(struct pinctrl_dev *pctldev,
225 struct device_node *np,
226 struct pinctrl_map **map, unsigned *num_maps)
227{
228 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
229 const struct imx1_pinctrl_soc_info *info = ipctl->info;
230 const struct imx1_pin_group *grp;
231 struct pinctrl_map *new_map;
232 struct device_node *parent;
233 int map_num = 1;
234 int i, j;
235
236 /*
237 * first find the group of this node and check if we need create
238 * config maps for pins
239 */
240 grp = imx1_pinctrl_find_group_by_name(info, np->name);
241 if (!grp) {
242 dev_err(info->dev, "unable to find group for node %s\n",
243 np->name);
244 return -EINVAL;
245 }
246
247 for (i = 0; i < grp->npins; i++)
248 map_num++;
249
250 new_map = kmalloc(sizeof(struct pinctrl_map) * map_num, GFP_KERNEL);
251 if (!new_map)
252 return -ENOMEM;
253
254 *map = new_map;
255 *num_maps = map_num;
256
257 /* create mux map */
258 parent = of_get_parent(np);
259 if (!parent) {
260 kfree(new_map);
261 return -EINVAL;
262 }
263 new_map[0].type = PIN_MAP_TYPE_MUX_GROUP;
264 new_map[0].data.mux.function = parent->name;
265 new_map[0].data.mux.group = np->name;
266 of_node_put(parent);
267
268 /* create config map */
269 new_map++;
270 for (i = j = 0; i < grp->npins; i++) {
271 new_map[j].type = PIN_MAP_TYPE_CONFIGS_PIN;
272 new_map[j].data.configs.group_or_pin =
273 pin_get_name(pctldev, grp->pins[i].pin_id);
274 new_map[j].data.configs.configs = &grp->pins[i].config;
275 new_map[j].data.configs.num_configs = 1;
276 j++;
277 }
278
279 dev_dbg(pctldev->dev, "maps: function %s group %s num %d\n",
280 (*map)->data.mux.function, (*map)->data.mux.group, map_num);
281
282 return 0;
283}
284
285static void imx1_dt_free_map(struct pinctrl_dev *pctldev,
286 struct pinctrl_map *map, unsigned num_maps)
287{
288 kfree(map);
289}
290
291static const struct pinctrl_ops imx1_pctrl_ops = {
292 .get_groups_count = imx1_get_groups_count,
293 .get_group_name = imx1_get_group_name,
294 .get_group_pins = imx1_get_group_pins,
295 .pin_dbg_show = imx1_pin_dbg_show,
296 .dt_node_to_map = imx1_dt_node_to_map,
297 .dt_free_map = imx1_dt_free_map,
298
299};
300
301static int imx1_pmx_enable(struct pinctrl_dev *pctldev, unsigned selector,
302 unsigned group)
303{
304 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
305 const struct imx1_pinctrl_soc_info *info = ipctl->info;
306 const struct imx1_pin *pins;
307 unsigned int npins;
308 int i;
309
310 /*
311 * Configure the mux mode for each pin in the group for a specific
312 * function.
313 */
314 pins = info->groups[group].pins;
315 npins = info->groups[group].npins;
316
317 WARN_ON(!pins || !npins);
318
319 dev_dbg(ipctl->dev, "enable function %s group %s\n",
320 info->functions[selector].name, info->groups[group].name);
321
322 for (i = 0; i < npins; i++) {
323 unsigned int mux = pins[i].mux_id;
324 unsigned int pin_id = pins[i].pin_id;
325 unsigned int afunction = MX1_MUX_FUNCTION(mux);
326 unsigned int gpio_in_use = MX1_MUX_GPIO(mux);
327 unsigned int direction = MX1_MUX_DIR(mux);
328 unsigned int gpio_oconf = MX1_MUX_OCONF(mux);
329 unsigned int gpio_iconfa = MX1_MUX_ICONFA(mux);
330 unsigned int gpio_iconfb = MX1_MUX_ICONFB(mux);
331
332 dev_dbg(pctldev->dev, "%s, pin 0x%x, function %d, gpio %d, direction %d, oconf %d, iconfa %d, iconfb %d\n",
333 __func__, pin_id, afunction, gpio_in_use,
334 direction, gpio_oconf, gpio_iconfa,
335 gpio_iconfb);
336
337 imx1_write_bit(ipctl, pin_id, gpio_in_use, MX1_GIUS);
338 imx1_write_bit(ipctl, pin_id, direction, MX1_DDIR);
339
340 if (gpio_in_use) {
341 imx1_write_2bit(ipctl, pin_id, gpio_oconf, MX1_OCR);
342 imx1_write_2bit(ipctl, pin_id, gpio_iconfa,
343 MX1_ICONFA);
344 imx1_write_2bit(ipctl, pin_id, gpio_iconfb,
345 MX1_ICONFB);
346 } else {
347 imx1_write_bit(ipctl, pin_id, afunction, MX1_GPR);
348 }
349 }
350
351 return 0;
352}
353
354static int imx1_pmx_get_funcs_count(struct pinctrl_dev *pctldev)
355{
356 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
357 const struct imx1_pinctrl_soc_info *info = ipctl->info;
358
359 return info->nfunctions;
360}
361
362static const char *imx1_pmx_get_func_name(struct pinctrl_dev *pctldev,
363 unsigned selector)
364{
365 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
366 const struct imx1_pinctrl_soc_info *info = ipctl->info;
367
368 return info->functions[selector].name;
369}
370
371static int imx1_pmx_get_groups(struct pinctrl_dev *pctldev, unsigned selector,
372 const char * const **groups,
373 unsigned * const num_groups)
374{
375 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
376 const struct imx1_pinctrl_soc_info *info = ipctl->info;
377
378 *groups = info->functions[selector].groups;
379 *num_groups = info->functions[selector].num_groups;
380
381 return 0;
382}
383
384static const struct pinmux_ops imx1_pmx_ops = {
385 .get_functions_count = imx1_pmx_get_funcs_count,
386 .get_function_name = imx1_pmx_get_func_name,
387 .get_function_groups = imx1_pmx_get_groups,
388 .enable = imx1_pmx_enable,
389};
390
391static int imx1_pinconf_get(struct pinctrl_dev *pctldev,
392 unsigned pin_id, unsigned long *config)
393{
394 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
395
396 *config = imx1_read_bit(ipctl, pin_id, MX1_PUEN);
397
398 return 0;
399}
400
401static int imx1_pinconf_set(struct pinctrl_dev *pctldev,
402 unsigned pin_id, unsigned long *configs,
403 unsigned num_configs)
404{
405 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
406 const struct imx1_pinctrl_soc_info *info = ipctl->info;
407 int i;
408
409 for (i = 0; i != num_configs; ++i) {
410 imx1_write_bit(ipctl, pin_id, configs[i] & 0x01, MX1_PUEN);
411
412 dev_dbg(ipctl->dev, "pinconf set pullup pin %s\n",
413 info->pins[pin_id].name);
414 }
415
416 return 0;
417}
418
419static void imx1_pinconf_dbg_show(struct pinctrl_dev *pctldev,
420 struct seq_file *s, unsigned pin_id)
421{
422 unsigned long config;
423
424 imx1_pinconf_get(pctldev, pin_id, &config);
425 seq_printf(s, "0x%lx", config);
426}
427
428static void imx1_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
429 struct seq_file *s, unsigned group)
430{
431 struct imx1_pinctrl *ipctl = pinctrl_dev_get_drvdata(pctldev);
432 const struct imx1_pinctrl_soc_info *info = ipctl->info;
433 struct imx1_pin_group *grp;
434 unsigned long config;
435 const char *name;
436 int i, ret;
437
438 if (group > info->ngroups)
439 return;
440
441 seq_puts(s, "\n");
442 grp = &info->groups[group];
443 for (i = 0; i < grp->npins; i++) {
444 name = pin_get_name(pctldev, grp->pins[i].pin_id);
445 ret = imx1_pinconf_get(pctldev, grp->pins[i].pin_id, &config);
446 if (ret)
447 return;
448 seq_printf(s, "%s: 0x%lx", name, config);
449 }
450}
451
452static const struct pinconf_ops imx1_pinconf_ops = {
453 .pin_config_get = imx1_pinconf_get,
454 .pin_config_set = imx1_pinconf_set,
455 .pin_config_dbg_show = imx1_pinconf_dbg_show,
456 .pin_config_group_dbg_show = imx1_pinconf_group_dbg_show,
457};
458
459static struct pinctrl_desc imx1_pinctrl_desc = {
460 .pctlops = &imx1_pctrl_ops,
461 .pmxops = &imx1_pmx_ops,
462 .confops = &imx1_pinconf_ops,
463 .owner = THIS_MODULE,
464};
465
466static int imx1_pinctrl_parse_groups(struct device_node *np,
467 struct imx1_pin_group *grp,
468 struct imx1_pinctrl_soc_info *info,
469 u32 index)
470{
471 int size;
472 const __be32 *list;
473 int i;
474
475 dev_dbg(info->dev, "group(%d): %s\n", index, np->name);
476
477 /* Initialise group */
478 grp->name = np->name;
479
480 /*
481 * the binding format is fsl,pins = <PIN MUX_ID CONFIG>
482 */
483 list = of_get_property(np, "fsl,pins", &size);
484 /* we do not check return since it's safe node passed down */
485 if (!size || size % 12) {
486 dev_notice(info->dev, "Not a valid fsl,pins property (%s)\n",
487 np->name);
488 return -EINVAL;
489 }
490
491 grp->npins = size / 12;
492 grp->pins = devm_kzalloc(info->dev,
493 grp->npins * sizeof(struct imx1_pin), GFP_KERNEL);
494 grp->pin_ids = devm_kzalloc(info->dev,
495 grp->npins * sizeof(unsigned int), GFP_KERNEL);
496
497 if (!grp->pins || !grp->pin_ids)
498 return -ENOMEM;
499
500 for (i = 0; i < grp->npins; i++) {
501 grp->pins[i].pin_id = be32_to_cpu(*list++);
502 grp->pins[i].mux_id = be32_to_cpu(*list++);
503 grp->pins[i].config = be32_to_cpu(*list++);
504
505 grp->pin_ids[i] = grp->pins[i].pin_id;
506 }
507
508 return 0;
509}
510
511static int imx1_pinctrl_parse_functions(struct device_node *np,
512 struct imx1_pinctrl_soc_info *info,
513 u32 index)
514{
515 struct device_node *child;
516 struct imx1_pmx_func *func;
517 struct imx1_pin_group *grp;
518 int ret;
519 static u32 grp_index;
520 u32 i = 0;
521
522 dev_dbg(info->dev, "parse function(%d): %s\n", index, np->name);
523
524 func = &info->functions[index];
525
526 /* Initialise function */
527 func->name = np->name;
528 func->num_groups = of_get_child_count(np);
529 if (func->num_groups <= 0)
530 return -EINVAL;
531
532 func->groups = devm_kzalloc(info->dev,
533 func->num_groups * sizeof(char *), GFP_KERNEL);
534
535 if (!func->groups)
536 return -ENOMEM;
537
538 for_each_child_of_node(np, child) {
539 func->groups[i] = child->name;
540 grp = &info->groups[grp_index++];
541 ret = imx1_pinctrl_parse_groups(child, grp, info, i++);
542 if (ret == -ENOMEM)
543 return ret;
544 }
545
546 return 0;
547}
548
549static int imx1_pinctrl_parse_dt(struct platform_device *pdev,
550 struct imx1_pinctrl *pctl, struct imx1_pinctrl_soc_info *info)
551{
552 struct device_node *np = pdev->dev.of_node;
553 struct device_node *child;
554 int ret;
555 u32 nfuncs = 0;
556 u32 ngroups = 0;
557 u32 ifunc = 0;
558
559 if (!np)
560 return -ENODEV;
561
562 for_each_child_of_node(np, child) {
563 ++nfuncs;
564 ngroups += of_get_child_count(child);
565 }
566
567 if (!nfuncs) {
568 dev_err(&pdev->dev, "No pin functions defined\n");
569 return -EINVAL;
570 }
571
572 info->nfunctions = nfuncs;
573 info->functions = devm_kzalloc(&pdev->dev,
574 nfuncs * sizeof(struct imx1_pmx_func), GFP_KERNEL);
575
576 info->ngroups = ngroups;
577 info->groups = devm_kzalloc(&pdev->dev,
578 ngroups * sizeof(struct imx1_pin_group), GFP_KERNEL);
579
580
581 if (!info->functions || !info->groups)
582 return -ENOMEM;
583
584 for_each_child_of_node(np, child) {
585 ret = imx1_pinctrl_parse_functions(child, info, ifunc++);
586 if (ret == -ENOMEM)
587 return -ENOMEM;
588 }
589
590 return 0;
591}
592
593int imx1_pinctrl_core_probe(struct platform_device *pdev,
594 struct imx1_pinctrl_soc_info *info)
595{
596 struct imx1_pinctrl *ipctl;
597 struct resource *res;
598 struct pinctrl_desc *pctl_desc;
599 int ret;
600
601 if (!info || !info->pins || !info->npins) {
602 dev_err(&pdev->dev, "wrong pinctrl info\n");
603 return -EINVAL;
604 }
605 info->dev = &pdev->dev;
606
607 /* Create state holders etc for this driver */
608 ipctl = devm_kzalloc(&pdev->dev, sizeof(*ipctl), GFP_KERNEL);
609 if (!ipctl)
610 return -ENOMEM;
611
612 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
613 if (!res)
614 return -ENOENT;
615
616 ipctl->base = devm_ioremap_nocache(&pdev->dev, res->start,
617 resource_size(res));
618 if (!ipctl->base)
619 return -ENOMEM;
620
621 pctl_desc = &imx1_pinctrl_desc;
622 pctl_desc->name = dev_name(&pdev->dev);
623 pctl_desc->pins = info->pins;
624 pctl_desc->npins = info->npins;
625
626 ret = imx1_pinctrl_parse_dt(pdev, ipctl, info);
627 if (ret) {
628 dev_err(&pdev->dev, "fail to probe dt properties\n");
629 return ret;
630 }
631
632 ipctl->info = info;
633 ipctl->dev = info->dev;
634 platform_set_drvdata(pdev, ipctl);
635 ipctl->pctl = pinctrl_register(pctl_desc, &pdev->dev, ipctl);
636 if (!ipctl->pctl) {
637 dev_err(&pdev->dev, "could not register IMX pinctrl driver\n");
638 return -EINVAL;
639 }
640
641 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
642
643 return 0;
644}
645
646int imx1_pinctrl_core_remove(struct platform_device *pdev)
647{
648 struct imx1_pinctrl *ipctl = platform_get_drvdata(pdev);
649
650 pinctrl_unregister(ipctl->pctl);
651
652 return 0;
653}
diff --git a/drivers/pinctrl/pinctrl-imx1.h b/drivers/pinctrl/pinctrl-imx1.h
new file mode 100644
index 000000000000..692a54c15cda
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx1.h
@@ -0,0 +1,73 @@
1/*
2 * IMX pinmux core definitions
3 *
4 * Copyright (C) 2012 Freescale Semiconductor, Inc.
5 * Copyright (C) 2012 Linaro Ltd.
6 *
7 * Author: Dong Aisheng <dong.aisheng@linaro.org>
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as published by
11 * the Free Software Foundation; either version 2 of the License, or
12 * (at your option) any later version.
13 */
14
15#ifndef __DRIVERS_PINCTRL_IMX1_H
16#define __DRIVERS_PINCTRL_IMX1_H
17
18struct platform_device;
19
20/**
21 * struct imx1_pin - describes an IMX1/21/27 pin.
22 * @pin_id: ID of the described pin.
23 * @mux_id: ID of the mux setup.
24 * @config: Configuration of the pin (currently only pullup-enable).
25 */
26struct imx1_pin {
27 unsigned int pin_id;
28 unsigned int mux_id;
29 unsigned long config;
30};
31
32/**
33 * struct imx1_pin_group - describes an IMX pin group
34 * @name: the name of this specific pin group
35 * @pins: an array of imx1_pin structs used in this group
36 * @npins: the number of pins in this group array, i.e. the number of
37 * elements in .pins so we can iterate over that array
38 */
39struct imx1_pin_group {
40 const char *name;
41 unsigned int *pin_ids;
42 struct imx1_pin *pins;
43 unsigned npins;
44};
45
46/**
47 * struct imx1_pmx_func - describes IMX pinmux functions
48 * @name: the name of this specific function
49 * @groups: corresponding pin groups
50 * @num_groups: the number of groups
51 */
52struct imx1_pmx_func {
53 const char *name;
54 const char **groups;
55 unsigned num_groups;
56};
57
58struct imx1_pinctrl_soc_info {
59 struct device *dev;
60 const struct pinctrl_pin_desc *pins;
61 unsigned int npins;
62 struct imx1_pin_group *groups;
63 unsigned int ngroups;
64 struct imx1_pmx_func *functions;
65 unsigned int nfunctions;
66};
67
68#define IMX_PINCTRL_PIN(pin) PINCTRL_PIN(pin, #pin)
69
70int imx1_pinctrl_core_probe(struct platform_device *pdev,
71 struct imx1_pinctrl_soc_info *info);
72int imx1_pinctrl_core_remove(struct platform_device *pdev);
73#endif /* __DRIVERS_PINCTRL_IMX1_H */
diff --git a/drivers/pinctrl/pinctrl-imx27.c b/drivers/pinctrl/pinctrl-imx27.c
new file mode 100644
index 000000000000..417c99205bc2
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx27.c
@@ -0,0 +1,477 @@
1/*
2 * imx27 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2013 Pengutronix
5 *
6 * Author: Markus Pargmann <mpa@pengutronix.de>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/err.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/pinctrl/pinctrl.h>
21
22#include "pinctrl-imx1.h"
23
24#define PAD_ID(port, pin) (port*32 + pin)
25#define PA 0
26#define PB 1
27#define PC 2
28#define PD 3
29#define PE 4
30#define PF 5
31
32enum imx27_pads {
33 MX27_PAD_USBH2_CLK = PAD_ID(PA, 0),
34 MX27_PAD_USBH2_DIR = PAD_ID(PA, 1),
35 MX27_PAD_USBH2_DATA7 = PAD_ID(PA, 2),
36 MX27_PAD_USBH2_NXT = PAD_ID(PA, 3),
37 MX27_PAD_USBH2_STP = PAD_ID(PA, 4),
38 MX27_PAD_LSCLK = PAD_ID(PA, 5),
39 MX27_PAD_LD0 = PAD_ID(PA, 6),
40 MX27_PAD_LD1 = PAD_ID(PA, 7),
41 MX27_PAD_LD2 = PAD_ID(PA, 8),
42 MX27_PAD_LD3 = PAD_ID(PA, 9),
43 MX27_PAD_LD4 = PAD_ID(PA, 10),
44 MX27_PAD_LD5 = PAD_ID(PA, 11),
45 MX27_PAD_LD6 = PAD_ID(PA, 12),
46 MX27_PAD_LD7 = PAD_ID(PA, 13),
47 MX27_PAD_LD8 = PAD_ID(PA, 14),
48 MX27_PAD_LD9 = PAD_ID(PA, 15),
49 MX27_PAD_LD10 = PAD_ID(PA, 16),
50 MX27_PAD_LD11 = PAD_ID(PA, 17),
51 MX27_PAD_LD12 = PAD_ID(PA, 18),
52 MX27_PAD_LD13 = PAD_ID(PA, 19),
53 MX27_PAD_LD14 = PAD_ID(PA, 20),
54 MX27_PAD_LD15 = PAD_ID(PA, 21),
55 MX27_PAD_LD16 = PAD_ID(PA, 22),
56 MX27_PAD_LD17 = PAD_ID(PA, 23),
57 MX27_PAD_REV = PAD_ID(PA, 24),
58 MX27_PAD_CLS = PAD_ID(PA, 25),
59 MX27_PAD_PS = PAD_ID(PA, 26),
60 MX27_PAD_SPL_SPR = PAD_ID(PA, 27),
61 MX27_PAD_HSYNC = PAD_ID(PA, 28),
62 MX27_PAD_VSYNC = PAD_ID(PA, 29),
63 MX27_PAD_CONTRAST = PAD_ID(PA, 30),
64 MX27_PAD_OE_ACD = PAD_ID(PA, 31),
65
66 MX27_PAD_UNUSED0 = PAD_ID(PB, 0),
67 MX27_PAD_UNUSED1 = PAD_ID(PB, 1),
68 MX27_PAD_UNUSED2 = PAD_ID(PB, 2),
69 MX27_PAD_UNUSED3 = PAD_ID(PB, 3),
70 MX27_PAD_SD2_D0 = PAD_ID(PB, 4),
71 MX27_PAD_SD2_D1 = PAD_ID(PB, 5),
72 MX27_PAD_SD2_D2 = PAD_ID(PB, 6),
73 MX27_PAD_SD2_D3 = PAD_ID(PB, 7),
74 MX27_PAD_SD2_CMD = PAD_ID(PB, 8),
75 MX27_PAD_SD2_CLK = PAD_ID(PB, 9),
76 MX27_PAD_CSI_D0 = PAD_ID(PB, 10),
77 MX27_PAD_CSI_D1 = PAD_ID(PB, 11),
78 MX27_PAD_CSI_D2 = PAD_ID(PB, 12),
79 MX27_PAD_CSI_D3 = PAD_ID(PB, 13),
80 MX27_PAD_CSI_D4 = PAD_ID(PB, 14),
81 MX27_PAD_CSI_MCLK = PAD_ID(PB, 15),
82 MX27_PAD_CSI_PIXCLK = PAD_ID(PB, 16),
83 MX27_PAD_CSI_D5 = PAD_ID(PB, 17),
84 MX27_PAD_CSI_D6 = PAD_ID(PB, 18),
85 MX27_PAD_CSI_D7 = PAD_ID(PB, 19),
86 MX27_PAD_CSI_VSYNC = PAD_ID(PB, 20),
87 MX27_PAD_CSI_HSYNC = PAD_ID(PB, 21),
88 MX27_PAD_USBH1_SUSP = PAD_ID(PB, 22),
89 MX27_PAD_USB_PWR = PAD_ID(PB, 23),
90 MX27_PAD_USB_OC_B = PAD_ID(PB, 24),
91 MX27_PAD_USBH1_RCV = PAD_ID(PB, 25),
92 MX27_PAD_USBH1_FS = PAD_ID(PB, 26),
93 MX27_PAD_USBH1_OE_B = PAD_ID(PB, 27),
94 MX27_PAD_USBH1_TXDM = PAD_ID(PB, 28),
95 MX27_PAD_USBH1_TXDP = PAD_ID(PB, 29),
96 MX27_PAD_USBH1_RXDM = PAD_ID(PB, 30),
97 MX27_PAD_USBH1_RXDP = PAD_ID(PB, 31),
98
99 MX27_PAD_UNUSED4 = PAD_ID(PC, 0),
100 MX27_PAD_UNUSED5 = PAD_ID(PC, 1),
101 MX27_PAD_UNUSED6 = PAD_ID(PC, 2),
102 MX27_PAD_UNUSED7 = PAD_ID(PC, 3),
103 MX27_PAD_UNUSED8 = PAD_ID(PC, 4),
104 MX27_PAD_I2C2_SDA = PAD_ID(PC, 5),
105 MX27_PAD_I2C2_SCL = PAD_ID(PC, 6),
106 MX27_PAD_USBOTG_DATA5 = PAD_ID(PC, 7),
107 MX27_PAD_USBOTG_DATA6 = PAD_ID(PC, 8),
108 MX27_PAD_USBOTG_DATA0 = PAD_ID(PC, 9),
109 MX27_PAD_USBOTG_DATA2 = PAD_ID(PC, 10),
110 MX27_PAD_USBOTG_DATA1 = PAD_ID(PC, 11),
111 MX27_PAD_USBOTG_DATA4 = PAD_ID(PC, 12),
112 MX27_PAD_USBOTG_DATA3 = PAD_ID(PC, 13),
113 MX27_PAD_TOUT = PAD_ID(PC, 14),
114 MX27_PAD_TIN = PAD_ID(PC, 15),
115 MX27_PAD_SSI4_FS = PAD_ID(PC, 16),
116 MX27_PAD_SSI4_RXDAT = PAD_ID(PC, 17),
117 MX27_PAD_SSI4_TXDAT = PAD_ID(PC, 18),
118 MX27_PAD_SSI4_CLK = PAD_ID(PC, 19),
119 MX27_PAD_SSI1_FS = PAD_ID(PC, 20),
120 MX27_PAD_SSI1_RXDAT = PAD_ID(PC, 21),
121 MX27_PAD_SSI1_TXDAT = PAD_ID(PC, 22),
122 MX27_PAD_SSI1_CLK = PAD_ID(PC, 23),
123 MX27_PAD_SSI2_FS = PAD_ID(PC, 24),
124 MX27_PAD_SSI2_RXDAT = PAD_ID(PC, 25),
125 MX27_PAD_SSI2_TXDAT = PAD_ID(PC, 26),
126 MX27_PAD_SSI2_CLK = PAD_ID(PC, 27),
127 MX27_PAD_SSI3_FS = PAD_ID(PC, 28),
128 MX27_PAD_SSI3_RXDAT = PAD_ID(PC, 29),
129 MX27_PAD_SSI3_TXDAT = PAD_ID(PC, 30),
130 MX27_PAD_SSI3_CLK = PAD_ID(PC, 31),
131
132 MX27_PAD_SD3_CMD = PAD_ID(PD, 0),
133 MX27_PAD_SD3_CLK = PAD_ID(PD, 1),
134 MX27_PAD_ATA_DATA0 = PAD_ID(PD, 2),
135 MX27_PAD_ATA_DATA1 = PAD_ID(PD, 3),
136 MX27_PAD_ATA_DATA2 = PAD_ID(PD, 4),
137 MX27_PAD_ATA_DATA3 = PAD_ID(PD, 5),
138 MX27_PAD_ATA_DATA4 = PAD_ID(PD, 6),
139 MX27_PAD_ATA_DATA5 = PAD_ID(PD, 7),
140 MX27_PAD_ATA_DATA6 = PAD_ID(PD, 8),
141 MX27_PAD_ATA_DATA7 = PAD_ID(PD, 9),
142 MX27_PAD_ATA_DATA8 = PAD_ID(PD, 10),
143 MX27_PAD_ATA_DATA9 = PAD_ID(PD, 11),
144 MX27_PAD_ATA_DATA10 = PAD_ID(PD, 12),
145 MX27_PAD_ATA_DATA11 = PAD_ID(PD, 13),
146 MX27_PAD_ATA_DATA12 = PAD_ID(PD, 14),
147 MX27_PAD_ATA_DATA13 = PAD_ID(PD, 15),
148 MX27_PAD_ATA_DATA14 = PAD_ID(PD, 16),
149 MX27_PAD_I2C_DATA = PAD_ID(PD, 17),
150 MX27_PAD_I2C_CLK = PAD_ID(PD, 18),
151 MX27_PAD_CSPI2_SS2 = PAD_ID(PD, 19),
152 MX27_PAD_CSPI2_SS1 = PAD_ID(PD, 20),
153 MX27_PAD_CSPI2_SS0 = PAD_ID(PD, 21),
154 MX27_PAD_CSPI2_SCLK = PAD_ID(PD, 22),
155 MX27_PAD_CSPI2_MISO = PAD_ID(PD, 23),
156 MX27_PAD_CSPI2_MOSI = PAD_ID(PD, 24),
157 MX27_PAD_CSPI1_RDY = PAD_ID(PD, 25),
158 MX27_PAD_CSPI1_SS2 = PAD_ID(PD, 26),
159 MX27_PAD_CSPI1_SS1 = PAD_ID(PD, 27),
160 MX27_PAD_CSPI1_SS0 = PAD_ID(PD, 28),
161 MX27_PAD_CSPI1_SCLK = PAD_ID(PD, 29),
162 MX27_PAD_CSPI1_MISO = PAD_ID(PD, 30),
163 MX27_PAD_CSPI1_MOSI = PAD_ID(PD, 31),
164
165 MX27_PAD_USBOTG_NXT = PAD_ID(PE, 0),
166 MX27_PAD_USBOTG_STP = PAD_ID(PE, 1),
167 MX27_PAD_USBOTG_DIR = PAD_ID(PE, 2),
168 MX27_PAD_UART2_CTS = PAD_ID(PE, 3),
169 MX27_PAD_UART2_RTS = PAD_ID(PE, 4),
170 MX27_PAD_PWMO = PAD_ID(PE, 5),
171 MX27_PAD_UART2_TXD = PAD_ID(PE, 6),
172 MX27_PAD_UART2_RXD = PAD_ID(PE, 7),
173 MX27_PAD_UART3_TXD = PAD_ID(PE, 8),
174 MX27_PAD_UART3_RXD = PAD_ID(PE, 9),
175 MX27_PAD_UART3_CTS = PAD_ID(PE, 10),
176 MX27_PAD_UART3_RTS = PAD_ID(PE, 11),
177 MX27_PAD_UART1_TXD = PAD_ID(PE, 12),
178 MX27_PAD_UART1_RXD = PAD_ID(PE, 13),
179 MX27_PAD_UART1_CTS = PAD_ID(PE, 14),
180 MX27_PAD_UART1_RTS = PAD_ID(PE, 15),
181 MX27_PAD_RTCK = PAD_ID(PE, 16),
182 MX27_PAD_RESET_OUT_B = PAD_ID(PE, 17),
183 MX27_PAD_SD1_D0 = PAD_ID(PE, 18),
184 MX27_PAD_SD1_D1 = PAD_ID(PE, 19),
185 MX27_PAD_SD1_D2 = PAD_ID(PE, 20),
186 MX27_PAD_SD1_D3 = PAD_ID(PE, 21),
187 MX27_PAD_SD1_CMD = PAD_ID(PE, 22),
188 MX27_PAD_SD1_CLK = PAD_ID(PE, 23),
189 MX27_PAD_USBOTG_CLK = PAD_ID(PE, 24),
190 MX27_PAD_USBOTG_DATA7 = PAD_ID(PE, 25),
191 MX27_PAD_UNUSED9 = PAD_ID(PE, 26),
192 MX27_PAD_UNUSED10 = PAD_ID(PE, 27),
193 MX27_PAD_UNUSED11 = PAD_ID(PE, 28),
194 MX27_PAD_UNUSED12 = PAD_ID(PE, 29),
195 MX27_PAD_UNUSED13 = PAD_ID(PE, 30),
196 MX27_PAD_UNUSED14 = PAD_ID(PE, 31),
197
198 MX27_PAD_NFRB = PAD_ID(PF, 0),
199 MX27_PAD_NFCLE = PAD_ID(PF, 1),
200 MX27_PAD_NFWP_B = PAD_ID(PF, 2),
201 MX27_PAD_NFCE_B = PAD_ID(PF, 3),
202 MX27_PAD_NFALE = PAD_ID(PF, 4),
203 MX27_PAD_NFRE_B = PAD_ID(PF, 5),
204 MX27_PAD_NFWE_B = PAD_ID(PF, 6),
205 MX27_PAD_PC_POE = PAD_ID(PF, 7),
206 MX27_PAD_PC_RW_B = PAD_ID(PF, 8),
207 MX27_PAD_IOIS16 = PAD_ID(PF, 9),
208 MX27_PAD_PC_RST = PAD_ID(PF, 10),
209 MX27_PAD_PC_BVD2 = PAD_ID(PF, 11),
210 MX27_PAD_PC_BVD1 = PAD_ID(PF, 12),
211 MX27_PAD_PC_VS2 = PAD_ID(PF, 13),
212 MX27_PAD_PC_VS1 = PAD_ID(PF, 14),
213 MX27_PAD_CLKO = PAD_ID(PF, 15),
214 MX27_PAD_PC_PWRON = PAD_ID(PF, 16),
215 MX27_PAD_PC_READY = PAD_ID(PF, 17),
216 MX27_PAD_PC_WAIT_B = PAD_ID(PF, 18),
217 MX27_PAD_PC_CD2_B = PAD_ID(PF, 19),
218 MX27_PAD_PC_CD1_B = PAD_ID(PF, 20),
219 MX27_PAD_CS4_B = PAD_ID(PF, 21),
220 MX27_PAD_CS5_B = PAD_ID(PF, 22),
221 MX27_PAD_ATA_DATA15 = PAD_ID(PF, 23),
222 MX27_PAD_UNUSED15 = PAD_ID(PF, 24),
223 MX27_PAD_UNUSED16 = PAD_ID(PF, 25),
224 MX27_PAD_UNUSED17 = PAD_ID(PF, 26),
225 MX27_PAD_UNUSED18 = PAD_ID(PF, 27),
226 MX27_PAD_UNUSED19 = PAD_ID(PF, 28),
227 MX27_PAD_UNUSED20 = PAD_ID(PF, 29),
228 MX27_PAD_UNUSED21 = PAD_ID(PF, 30),
229 MX27_PAD_UNUSED22 = PAD_ID(PF, 31),
230};
231
232/* Pad names for the pinmux subsystem */
233static const struct pinctrl_pin_desc imx27_pinctrl_pads[] = {
234 IMX_PINCTRL_PIN(MX27_PAD_USBH2_CLK),
235 IMX_PINCTRL_PIN(MX27_PAD_USBH2_DIR),
236 IMX_PINCTRL_PIN(MX27_PAD_USBH2_DATA7),
237 IMX_PINCTRL_PIN(MX27_PAD_USBH2_NXT),
238 IMX_PINCTRL_PIN(MX27_PAD_USBH2_STP),
239 IMX_PINCTRL_PIN(MX27_PAD_LSCLK),
240 IMX_PINCTRL_PIN(MX27_PAD_LD0),
241 IMX_PINCTRL_PIN(MX27_PAD_LD1),
242 IMX_PINCTRL_PIN(MX27_PAD_LD2),
243 IMX_PINCTRL_PIN(MX27_PAD_LD3),
244 IMX_PINCTRL_PIN(MX27_PAD_LD4),
245 IMX_PINCTRL_PIN(MX27_PAD_LD5),
246 IMX_PINCTRL_PIN(MX27_PAD_LD6),
247 IMX_PINCTRL_PIN(MX27_PAD_LD7),
248 IMX_PINCTRL_PIN(MX27_PAD_LD8),
249 IMX_PINCTRL_PIN(MX27_PAD_LD9),
250 IMX_PINCTRL_PIN(MX27_PAD_LD10),
251 IMX_PINCTRL_PIN(MX27_PAD_LD11),
252 IMX_PINCTRL_PIN(MX27_PAD_LD12),
253 IMX_PINCTRL_PIN(MX27_PAD_LD13),
254 IMX_PINCTRL_PIN(MX27_PAD_LD14),
255 IMX_PINCTRL_PIN(MX27_PAD_LD15),
256 IMX_PINCTRL_PIN(MX27_PAD_LD16),
257 IMX_PINCTRL_PIN(MX27_PAD_LD17),
258 IMX_PINCTRL_PIN(MX27_PAD_REV),
259 IMX_PINCTRL_PIN(MX27_PAD_CLS),
260 IMX_PINCTRL_PIN(MX27_PAD_PS),
261 IMX_PINCTRL_PIN(MX27_PAD_SPL_SPR),
262 IMX_PINCTRL_PIN(MX27_PAD_HSYNC),
263 IMX_PINCTRL_PIN(MX27_PAD_VSYNC),
264 IMX_PINCTRL_PIN(MX27_PAD_CONTRAST),
265 IMX_PINCTRL_PIN(MX27_PAD_OE_ACD),
266
267 IMX_PINCTRL_PIN(MX27_PAD_UNUSED0),
268 IMX_PINCTRL_PIN(MX27_PAD_UNUSED1),
269 IMX_PINCTRL_PIN(MX27_PAD_UNUSED2),
270 IMX_PINCTRL_PIN(MX27_PAD_UNUSED3),
271 IMX_PINCTRL_PIN(MX27_PAD_SD2_D0),
272 IMX_PINCTRL_PIN(MX27_PAD_SD2_D1),
273 IMX_PINCTRL_PIN(MX27_PAD_SD2_D2),
274 IMX_PINCTRL_PIN(MX27_PAD_SD2_D3),
275 IMX_PINCTRL_PIN(MX27_PAD_SD2_CMD),
276 IMX_PINCTRL_PIN(MX27_PAD_SD2_CLK),
277 IMX_PINCTRL_PIN(MX27_PAD_CSI_D0),
278 IMX_PINCTRL_PIN(MX27_PAD_CSI_D1),
279 IMX_PINCTRL_PIN(MX27_PAD_CSI_D2),
280 IMX_PINCTRL_PIN(MX27_PAD_CSI_D3),
281 IMX_PINCTRL_PIN(MX27_PAD_CSI_D4),
282 IMX_PINCTRL_PIN(MX27_PAD_CSI_MCLK),
283 IMX_PINCTRL_PIN(MX27_PAD_CSI_PIXCLK),
284 IMX_PINCTRL_PIN(MX27_PAD_CSI_D5),
285 IMX_PINCTRL_PIN(MX27_PAD_CSI_D6),
286 IMX_PINCTRL_PIN(MX27_PAD_CSI_D7),
287 IMX_PINCTRL_PIN(MX27_PAD_CSI_VSYNC),
288 IMX_PINCTRL_PIN(MX27_PAD_CSI_HSYNC),
289 IMX_PINCTRL_PIN(MX27_PAD_USBH1_SUSP),
290 IMX_PINCTRL_PIN(MX27_PAD_USB_PWR),
291 IMX_PINCTRL_PIN(MX27_PAD_USB_OC_B),
292 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RCV),
293 IMX_PINCTRL_PIN(MX27_PAD_USBH1_FS),
294 IMX_PINCTRL_PIN(MX27_PAD_USBH1_OE_B),
295 IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDM),
296 IMX_PINCTRL_PIN(MX27_PAD_USBH1_TXDP),
297 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDM),
298 IMX_PINCTRL_PIN(MX27_PAD_USBH1_RXDP),
299
300 IMX_PINCTRL_PIN(MX27_PAD_UNUSED4),
301 IMX_PINCTRL_PIN(MX27_PAD_UNUSED5),
302 IMX_PINCTRL_PIN(MX27_PAD_UNUSED6),
303 IMX_PINCTRL_PIN(MX27_PAD_UNUSED7),
304 IMX_PINCTRL_PIN(MX27_PAD_UNUSED8),
305 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SDA),
306 IMX_PINCTRL_PIN(MX27_PAD_I2C2_SCL),
307 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA5),
308 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA6),
309 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA0),
310 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA2),
311 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA1),
312 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA4),
313 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA3),
314 IMX_PINCTRL_PIN(MX27_PAD_TOUT),
315 IMX_PINCTRL_PIN(MX27_PAD_TIN),
316 IMX_PINCTRL_PIN(MX27_PAD_SSI4_FS),
317 IMX_PINCTRL_PIN(MX27_PAD_SSI4_RXDAT),
318 IMX_PINCTRL_PIN(MX27_PAD_SSI4_TXDAT),
319 IMX_PINCTRL_PIN(MX27_PAD_SSI4_CLK),
320 IMX_PINCTRL_PIN(MX27_PAD_SSI1_FS),
321 IMX_PINCTRL_PIN(MX27_PAD_SSI1_RXDAT),
322 IMX_PINCTRL_PIN(MX27_PAD_SSI1_TXDAT),
323 IMX_PINCTRL_PIN(MX27_PAD_SSI1_CLK),
324 IMX_PINCTRL_PIN(MX27_PAD_SSI2_FS),
325 IMX_PINCTRL_PIN(MX27_PAD_SSI2_RXDAT),
326 IMX_PINCTRL_PIN(MX27_PAD_SSI2_TXDAT),
327 IMX_PINCTRL_PIN(MX27_PAD_SSI2_CLK),
328 IMX_PINCTRL_PIN(MX27_PAD_SSI3_FS),
329 IMX_PINCTRL_PIN(MX27_PAD_SSI3_RXDAT),
330 IMX_PINCTRL_PIN(MX27_PAD_SSI3_TXDAT),
331 IMX_PINCTRL_PIN(MX27_PAD_SSI3_CLK),
332
333 IMX_PINCTRL_PIN(MX27_PAD_SD3_CMD),
334 IMX_PINCTRL_PIN(MX27_PAD_SD3_CLK),
335 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA0),
336 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA1),
337 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA2),
338 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA3),
339 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA4),
340 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA5),
341 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA6),
342 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA7),
343 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA8),
344 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA9),
345 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA10),
346 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA11),
347 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA12),
348 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA13),
349 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA14),
350 IMX_PINCTRL_PIN(MX27_PAD_I2C_DATA),
351 IMX_PINCTRL_PIN(MX27_PAD_I2C_CLK),
352 IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS2),
353 IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS1),
354 IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SS0),
355 IMX_PINCTRL_PIN(MX27_PAD_CSPI2_SCLK),
356 IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MISO),
357 IMX_PINCTRL_PIN(MX27_PAD_CSPI2_MOSI),
358 IMX_PINCTRL_PIN(MX27_PAD_CSPI1_RDY),
359 IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS2),
360 IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS1),
361 IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SS0),
362 IMX_PINCTRL_PIN(MX27_PAD_CSPI1_SCLK),
363 IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MISO),
364 IMX_PINCTRL_PIN(MX27_PAD_CSPI1_MOSI),
365
366 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_NXT),
367 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_STP),
368 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DIR),
369 IMX_PINCTRL_PIN(MX27_PAD_UART2_CTS),
370 IMX_PINCTRL_PIN(MX27_PAD_UART2_RTS),
371 IMX_PINCTRL_PIN(MX27_PAD_PWMO),
372 IMX_PINCTRL_PIN(MX27_PAD_UART2_TXD),
373 IMX_PINCTRL_PIN(MX27_PAD_UART2_RXD),
374 IMX_PINCTRL_PIN(MX27_PAD_UART3_TXD),
375 IMX_PINCTRL_PIN(MX27_PAD_UART3_RXD),
376 IMX_PINCTRL_PIN(MX27_PAD_UART3_CTS),
377 IMX_PINCTRL_PIN(MX27_PAD_UART3_RTS),
378 IMX_PINCTRL_PIN(MX27_PAD_UART1_TXD),
379 IMX_PINCTRL_PIN(MX27_PAD_UART1_RXD),
380 IMX_PINCTRL_PIN(MX27_PAD_UART1_CTS),
381 IMX_PINCTRL_PIN(MX27_PAD_UART1_RTS),
382 IMX_PINCTRL_PIN(MX27_PAD_RTCK),
383 IMX_PINCTRL_PIN(MX27_PAD_RESET_OUT_B),
384 IMX_PINCTRL_PIN(MX27_PAD_SD1_D0),
385 IMX_PINCTRL_PIN(MX27_PAD_SD1_D1),
386 IMX_PINCTRL_PIN(MX27_PAD_SD1_D2),
387 IMX_PINCTRL_PIN(MX27_PAD_SD1_D3),
388 IMX_PINCTRL_PIN(MX27_PAD_SD1_CMD),
389 IMX_PINCTRL_PIN(MX27_PAD_SD1_CLK),
390 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_CLK),
391 IMX_PINCTRL_PIN(MX27_PAD_USBOTG_DATA7),
392 IMX_PINCTRL_PIN(MX27_PAD_UNUSED9),
393 IMX_PINCTRL_PIN(MX27_PAD_UNUSED10),
394 IMX_PINCTRL_PIN(MX27_PAD_UNUSED11),
395 IMX_PINCTRL_PIN(MX27_PAD_UNUSED12),
396 IMX_PINCTRL_PIN(MX27_PAD_UNUSED13),
397 IMX_PINCTRL_PIN(MX27_PAD_UNUSED14),
398
399 IMX_PINCTRL_PIN(MX27_PAD_NFRB),
400 IMX_PINCTRL_PIN(MX27_PAD_NFCLE),
401 IMX_PINCTRL_PIN(MX27_PAD_NFWP_B),
402 IMX_PINCTRL_PIN(MX27_PAD_NFCE_B),
403 IMX_PINCTRL_PIN(MX27_PAD_NFALE),
404 IMX_PINCTRL_PIN(MX27_PAD_NFRE_B),
405 IMX_PINCTRL_PIN(MX27_PAD_NFWE_B),
406 IMX_PINCTRL_PIN(MX27_PAD_PC_POE),
407 IMX_PINCTRL_PIN(MX27_PAD_PC_RW_B),
408 IMX_PINCTRL_PIN(MX27_PAD_IOIS16),
409 IMX_PINCTRL_PIN(MX27_PAD_PC_RST),
410 IMX_PINCTRL_PIN(MX27_PAD_PC_BVD2),
411 IMX_PINCTRL_PIN(MX27_PAD_PC_BVD1),
412 IMX_PINCTRL_PIN(MX27_PAD_PC_VS2),
413 IMX_PINCTRL_PIN(MX27_PAD_PC_VS1),
414 IMX_PINCTRL_PIN(MX27_PAD_CLKO),
415 IMX_PINCTRL_PIN(MX27_PAD_PC_PWRON),
416 IMX_PINCTRL_PIN(MX27_PAD_PC_READY),
417 IMX_PINCTRL_PIN(MX27_PAD_PC_WAIT_B),
418 IMX_PINCTRL_PIN(MX27_PAD_PC_CD2_B),
419 IMX_PINCTRL_PIN(MX27_PAD_PC_CD1_B),
420 IMX_PINCTRL_PIN(MX27_PAD_CS4_B),
421 IMX_PINCTRL_PIN(MX27_PAD_CS5_B),
422 IMX_PINCTRL_PIN(MX27_PAD_ATA_DATA15),
423 IMX_PINCTRL_PIN(MX27_PAD_UNUSED15),
424 IMX_PINCTRL_PIN(MX27_PAD_UNUSED16),
425 IMX_PINCTRL_PIN(MX27_PAD_UNUSED17),
426 IMX_PINCTRL_PIN(MX27_PAD_UNUSED18),
427 IMX_PINCTRL_PIN(MX27_PAD_UNUSED19),
428 IMX_PINCTRL_PIN(MX27_PAD_UNUSED20),
429 IMX_PINCTRL_PIN(MX27_PAD_UNUSED21),
430 IMX_PINCTRL_PIN(MX27_PAD_UNUSED22),
431};
432
433static struct imx1_pinctrl_soc_info imx27_pinctrl_info = {
434 .pins = imx27_pinctrl_pads,
435 .npins = ARRAY_SIZE(imx27_pinctrl_pads),
436};
437
438static struct of_device_id imx27_pinctrl_of_match[] = {
439 { .compatible = "fsl,imx27-iomuxc", },
440 { /* sentinel */ }
441};
442
443struct imx27_pinctrl_private {
444 int num_gpio_childs;
445 struct platform_device **gpio_dev;
446 struct mxc_gpio_platform_data *gpio_pdata;
447};
448
449static int imx27_pinctrl_probe(struct platform_device *pdev)
450{
451 return imx1_pinctrl_core_probe(pdev, &imx27_pinctrl_info);
452}
453
454static struct platform_driver imx27_pinctrl_driver = {
455 .driver = {
456 .name = "imx27-pinctrl",
457 .owner = THIS_MODULE,
458 .of_match_table = of_match_ptr(imx27_pinctrl_of_match),
459 },
460 .probe = imx27_pinctrl_probe,
461 .remove = imx1_pinctrl_core_remove,
462};
463
464static int __init imx27_pinctrl_init(void)
465{
466 return platform_driver_register(&imx27_pinctrl_driver);
467}
468arch_initcall(imx27_pinctrl_init);
469
470static void __exit imx27_pinctrl_exit(void)
471{
472 platform_driver_unregister(&imx27_pinctrl_driver);
473}
474module_exit(imx27_pinctrl_exit);
475MODULE_AUTHOR("Markus Pargmann <mpa@pengutronix.de>");
476MODULE_DESCRIPTION("Freescale IMX27 pinctrl driver");
477MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx35.c b/drivers/pinctrl/pinctrl-imx35.c
index c4549829fc47..278a04ae8940 100644
--- a/drivers/pinctrl/pinctrl-imx35.c
+++ b/drivers/pinctrl/pinctrl-imx35.c
@@ -1019,7 +1019,7 @@ static struct platform_driver imx35_pinctrl_driver = {
1019 .driver = { 1019 .driver = {
1020 .name = "imx35-pinctrl", 1020 .name = "imx35-pinctrl",
1021 .owner = THIS_MODULE, 1021 .owner = THIS_MODULE,
1022 .of_match_table = of_match_ptr(imx35_pinctrl_of_match), 1022 .of_match_table = imx35_pinctrl_of_match,
1023 }, 1023 },
1024 .probe = imx35_pinctrl_probe, 1024 .probe = imx35_pinctrl_probe,
1025 .remove = imx_pinctrl_remove, 1025 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx50.c b/drivers/pinctrl/pinctrl-imx50.c
new file mode 100644
index 000000000000..b06feed1b038
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx50.c
@@ -0,0 +1,426 @@
1/*
2 * imx50 pinctrl driver based on imx pinmux core
3 *
4 * Copyright (C) 2013 Greg Ungerer <gerg@uclinux.org>
5 * Copyright (C) 2012 Freescale Semiconductor, Inc.
6 * Copyright (C) 2012 Linaro, Inc.
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 */
13
14#include <linux/err.h>
15#include <linux/init.h>
16#include <linux/io.h>
17#include <linux/module.h>
18#include <linux/of.h>
19#include <linux/of_device.h>
20#include <linux/pinctrl/pinctrl.h>
21
22#include "pinctrl-imx.h"
23
24enum imx50_pads {
25 MX50_PAD_RESERVE0 = 0,
26 MX50_PAD_RESERVE1 = 1,
27 MX50_PAD_RESERVE2 = 2,
28 MX50_PAD_RESERVE3 = 3,
29 MX50_PAD_RESERVE4 = 4,
30 MX50_PAD_RESERVE5 = 5,
31 MX50_PAD_RESERVE6 = 6,
32 MX50_PAD_RESERVE7 = 7,
33 MX50_PAD_KEY_COL0 = 8,
34 MX50_PAD_KEY_ROW0 = 9,
35 MX50_PAD_KEY_COL1 = 10,
36 MX50_PAD_KEY_ROW1 = 11,
37 MX50_PAD_KEY_COL2 = 12,
38 MX50_PAD_KEY_ROW2 = 13,
39 MX50_PAD_KEY_COL3 = 14,
40 MX50_PAD_KEY_ROW3 = 15,
41 MX50_PAD_I2C1_SCL = 16,
42 MX50_PAD_I2C1_SDA = 17,
43 MX50_PAD_I2C2_SCL = 18,
44 MX50_PAD_I2C2_SDA = 19,
45 MX50_PAD_I2C3_SCL = 20,
46 MX50_PAD_I2C3_SDA = 21,
47 MX50_PAD_PWM1 = 22,
48 MX50_PAD_PWM2 = 23,
49 MX50_PAD_0WIRE = 24,
50 MX50_PAD_EPITO = 25,
51 MX50_PAD_WDOG = 26,
52 MX50_PAD_SSI_TXFS = 27,
53 MX50_PAD_SSI_TXC = 28,
54 MX50_PAD_SSI_TXD = 29,
55 MX50_PAD_SSI_RXD = 30,
56 MX50_PAD_SSI_RXF = 31,
57 MX50_PAD_SSI_RXC = 32,
58 MX50_PAD_UART1_TXD = 33,
59 MX50_PAD_UART1_RXD = 34,
60 MX50_PAD_UART1_CTS = 35,
61 MX50_PAD_UART1_RTS = 36,
62 MX50_PAD_UART2_TXD = 37,
63 MX50_PAD_UART2_RXD = 38,
64 MX50_PAD_UART2_CTS = 39,
65 MX50_PAD_UART2_RTS = 40,
66 MX50_PAD_UART3_TXD = 41,
67 MX50_PAD_UART3_RXD = 42,
68 MX50_PAD_UART4_TXD = 43,
69 MX50_PAD_UART4_RXD = 44,
70 MX50_PAD_CSPI_CLK = 45,
71 MX50_PAD_CSPI_MOSI = 46,
72 MX50_PAD_CSPI_MISO = 47,
73 MX50_PAD_CSPI_SS0 = 48,
74 MX50_PAD_ECSPI1_CLK = 49,
75 MX50_PAD_ECSPI1_MOSI = 50,
76 MX50_PAD_ECSPI1_MISO = 51,
77 MX50_PAD_ECSPI1_SS0 = 52,
78 MX50_PAD_ECSPI2_CLK = 53,
79 MX50_PAD_ECSPI2_MOSI = 54,
80 MX50_PAD_ECSPI2_MISO = 55,
81 MX50_PAD_ECSPI2_SS0 = 56,
82 MX50_PAD_SD1_CLK = 57,
83 MX50_PAD_SD1_CMD = 58,
84 MX50_PAD_SD1_D0 = 59,
85 MX50_PAD_SD1_D1 = 60,
86 MX50_PAD_SD1_D2 = 61,
87 MX50_PAD_SD1_D3 = 62,
88 MX50_PAD_SD2_CLK = 63,
89 MX50_PAD_SD2_CMD = 64,
90 MX50_PAD_SD2_D0 = 65,
91 MX50_PAD_SD2_D1 = 66,
92 MX50_PAD_SD2_D2 = 67,
93 MX50_PAD_SD2_D3 = 68,
94 MX50_PAD_SD2_D4 = 69,
95 MX50_PAD_SD2_D5 = 70,
96 MX50_PAD_SD2_D6 = 71,
97 MX50_PAD_SD2_D7 = 72,
98 MX50_PAD_SD2_WP = 73,
99 MX50_PAD_SD2_CD = 74,
100 MX50_PAD_DISP_D0 = 75,
101 MX50_PAD_DISP_D1 = 76,
102 MX50_PAD_DISP_D2 = 77,
103 MX50_PAD_DISP_D3 = 78,
104 MX50_PAD_DISP_D4 = 79,
105 MX50_PAD_DISP_D5 = 80,
106 MX50_PAD_DISP_D6 = 81,
107 MX50_PAD_DISP_D7 = 82,
108 MX50_PAD_DISP_WR = 83,
109 MX50_PAD_DISP_RD = 84,
110 MX50_PAD_DISP_RS = 85,
111 MX50_PAD_DISP_CS = 86,
112 MX50_PAD_DISP_BUSY = 87,
113 MX50_PAD_DISP_RESET = 88,
114 MX50_PAD_SD3_CLK = 89,
115 MX50_PAD_SD3_CMD = 90,
116 MX50_PAD_SD3_D0 = 91,
117 MX50_PAD_SD3_D1 = 92,
118 MX50_PAD_SD3_D2 = 93,
119 MX50_PAD_SD3_D3 = 94,
120 MX50_PAD_SD3_D4 = 95,
121 MX50_PAD_SD3_D5 = 96,
122 MX50_PAD_SD3_D6 = 97,
123 MX50_PAD_SD3_D7 = 98,
124 MX50_PAD_SD3_WP = 99,
125 MX50_PAD_DISP_D8 = 100,
126 MX50_PAD_DISP_D9 = 101,
127 MX50_PAD_DISP_D10 = 102,
128 MX50_PAD_DISP_D11 = 103,
129 MX50_PAD_DISP_D12 = 104,
130 MX50_PAD_DISP_D13 = 105,
131 MX50_PAD_DISP_D14 = 106,
132 MX50_PAD_DISP_D15 = 107,
133 MX50_PAD_EPDC_D0 = 108,
134 MX50_PAD_EPDC_D1 = 109,
135 MX50_PAD_EPDC_D2 = 110,
136 MX50_PAD_EPDC_D3 = 111,
137 MX50_PAD_EPDC_D4 = 112,
138 MX50_PAD_EPDC_D5 = 113,
139 MX50_PAD_EPDC_D6 = 114,
140 MX50_PAD_EPDC_D7 = 115,
141 MX50_PAD_EPDC_D8 = 116,
142 MX50_PAD_EPDC_D9 = 117,
143 MX50_PAD_EPDC_D10 = 118,
144 MX50_PAD_EPDC_D11 = 119,
145 MX50_PAD_EPDC_D12 = 120,
146 MX50_PAD_EPDC_D13 = 121,
147 MX50_PAD_EPDC_D14 = 122,
148 MX50_PAD_EPDC_D15 = 123,
149 MX50_PAD_EPDC_GDCLK = 124,
150 MX50_PAD_EPDC_GDSP = 125,
151 MX50_PAD_EPDC_GDOE = 126,
152 MX50_PAD_EPDC_GDRL = 127,
153 MX50_PAD_EPDC_SDCLK = 128,
154 MX50_PAD_EPDC_SDOEZ = 129,
155 MX50_PAD_EPDC_SDOED = 130,
156 MX50_PAD_EPDC_SDOE = 131,
157 MX50_PAD_EPDC_SDLE = 132,
158 MX50_PAD_EPDC_SDCLKN = 133,
159 MX50_PAD_EPDC_SDSHR = 134,
160 MX50_PAD_EPDC_PWRCOM = 135,
161 MX50_PAD_EPDC_PWRSTAT = 136,
162 MX50_PAD_EPDC_PWRCTRL0 = 137,
163 MX50_PAD_EPDC_PWRCTRL1 = 138,
164 MX50_PAD_EPDC_PWRCTRL2 = 139,
165 MX50_PAD_EPDC_PWRCTRL3 = 140,
166 MX50_PAD_EPDC_VCOM0 = 141,
167 MX50_PAD_EPDC_VCOM1 = 142,
168 MX50_PAD_EPDC_BDR0 = 143,
169 MX50_PAD_EPDC_BDR1 = 144,
170 MX50_PAD_EPDC_SDCE0 = 145,
171 MX50_PAD_EPDC_SDCE1 = 146,
172 MX50_PAD_EPDC_SDCE2 = 147,
173 MX50_PAD_EPDC_SDCE3 = 148,
174 MX50_PAD_EPDC_SDCE4 = 149,
175 MX50_PAD_EPDC_SDCE5 = 150,
176 MX50_PAD_EIM_DA0 = 151,
177 MX50_PAD_EIM_DA1 = 152,
178 MX50_PAD_EIM_DA2 = 153,
179 MX50_PAD_EIM_DA3 = 154,
180 MX50_PAD_EIM_DA4 = 155,
181 MX50_PAD_EIM_DA5 = 156,
182 MX50_PAD_EIM_DA6 = 157,
183 MX50_PAD_EIM_DA7 = 158,
184 MX50_PAD_EIM_DA8 = 159,
185 MX50_PAD_EIM_DA9 = 160,
186 MX50_PAD_EIM_DA10 = 161,
187 MX50_PAD_EIM_DA11 = 162,
188 MX50_PAD_EIM_DA12 = 163,
189 MX50_PAD_EIM_DA13 = 164,
190 MX50_PAD_EIM_DA14 = 165,
191 MX50_PAD_EIM_DA15 = 166,
192 MX50_PAD_EIM_CS2 = 167,
193 MX50_PAD_EIM_CS1 = 168,
194 MX50_PAD_EIM_CS0 = 169,
195 MX50_PAD_EIM_EB0 = 170,
196 MX50_PAD_EIM_EB1 = 171,
197 MX50_PAD_EIM_WAIT = 172,
198 MX50_PAD_EIM_BCLK = 173,
199 MX50_PAD_EIM_RDY = 174,
200 MX50_PAD_EIM_OE = 175,
201 MX50_PAD_EIM_RW = 176,
202 MX50_PAD_EIM_LBA = 177,
203 MX50_PAD_EIM_CRE = 178,
204};
205
206/* Pad names for the pinmux subsystem */
207static const struct pinctrl_pin_desc imx50_pinctrl_pads[] = {
208 IMX_PINCTRL_PIN(MX50_PAD_RESERVE0),
209 IMX_PINCTRL_PIN(MX50_PAD_RESERVE1),
210 IMX_PINCTRL_PIN(MX50_PAD_RESERVE2),
211 IMX_PINCTRL_PIN(MX50_PAD_RESERVE3),
212 IMX_PINCTRL_PIN(MX50_PAD_RESERVE4),
213 IMX_PINCTRL_PIN(MX50_PAD_RESERVE5),
214 IMX_PINCTRL_PIN(MX50_PAD_RESERVE6),
215 IMX_PINCTRL_PIN(MX50_PAD_RESERVE7),
216 IMX_PINCTRL_PIN(MX50_PAD_KEY_COL0),
217 IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW0),
218 IMX_PINCTRL_PIN(MX50_PAD_KEY_COL1),
219 IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW1),
220 IMX_PINCTRL_PIN(MX50_PAD_KEY_COL2),
221 IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW2),
222 IMX_PINCTRL_PIN(MX50_PAD_KEY_COL3),
223 IMX_PINCTRL_PIN(MX50_PAD_KEY_ROW3),
224 IMX_PINCTRL_PIN(MX50_PAD_I2C1_SCL),
225 IMX_PINCTRL_PIN(MX50_PAD_I2C1_SDA),
226 IMX_PINCTRL_PIN(MX50_PAD_I2C2_SCL),
227 IMX_PINCTRL_PIN(MX50_PAD_I2C2_SDA),
228 IMX_PINCTRL_PIN(MX50_PAD_I2C3_SCL),
229 IMX_PINCTRL_PIN(MX50_PAD_I2C3_SDA),
230 IMX_PINCTRL_PIN(MX50_PAD_PWM1),
231 IMX_PINCTRL_PIN(MX50_PAD_PWM2),
232 IMX_PINCTRL_PIN(MX50_PAD_0WIRE),
233 IMX_PINCTRL_PIN(MX50_PAD_EPITO),
234 IMX_PINCTRL_PIN(MX50_PAD_WDOG),
235 IMX_PINCTRL_PIN(MX50_PAD_SSI_TXFS),
236 IMX_PINCTRL_PIN(MX50_PAD_SSI_TXC),
237 IMX_PINCTRL_PIN(MX50_PAD_SSI_TXD),
238 IMX_PINCTRL_PIN(MX50_PAD_SSI_RXD),
239 IMX_PINCTRL_PIN(MX50_PAD_SSI_RXF),
240 IMX_PINCTRL_PIN(MX50_PAD_SSI_RXC),
241 IMX_PINCTRL_PIN(MX50_PAD_UART1_TXD),
242 IMX_PINCTRL_PIN(MX50_PAD_UART1_RXD),
243 IMX_PINCTRL_PIN(MX50_PAD_UART1_CTS),
244 IMX_PINCTRL_PIN(MX50_PAD_UART1_RTS),
245 IMX_PINCTRL_PIN(MX50_PAD_UART2_TXD),
246 IMX_PINCTRL_PIN(MX50_PAD_UART2_RXD),
247 IMX_PINCTRL_PIN(MX50_PAD_UART2_CTS),
248 IMX_PINCTRL_PIN(MX50_PAD_UART2_RTS),
249 IMX_PINCTRL_PIN(MX50_PAD_UART3_TXD),
250 IMX_PINCTRL_PIN(MX50_PAD_UART3_RXD),
251 IMX_PINCTRL_PIN(MX50_PAD_UART4_TXD),
252 IMX_PINCTRL_PIN(MX50_PAD_UART4_RXD),
253 IMX_PINCTRL_PIN(MX50_PAD_CSPI_CLK),
254 IMX_PINCTRL_PIN(MX50_PAD_CSPI_MOSI),
255 IMX_PINCTRL_PIN(MX50_PAD_CSPI_MISO),
256 IMX_PINCTRL_PIN(MX50_PAD_CSPI_SS0),
257 IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_CLK),
258 IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MOSI),
259 IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_MISO),
260 IMX_PINCTRL_PIN(MX50_PAD_ECSPI1_SS0),
261 IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_CLK),
262 IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MOSI),
263 IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_MISO),
264 IMX_PINCTRL_PIN(MX50_PAD_ECSPI2_SS0),
265 IMX_PINCTRL_PIN(MX50_PAD_SD1_CLK),
266 IMX_PINCTRL_PIN(MX50_PAD_SD1_CMD),
267 IMX_PINCTRL_PIN(MX50_PAD_SD1_D0),
268 IMX_PINCTRL_PIN(MX50_PAD_SD1_D1),
269 IMX_PINCTRL_PIN(MX50_PAD_SD1_D2),
270 IMX_PINCTRL_PIN(MX50_PAD_SD1_D3),
271 IMX_PINCTRL_PIN(MX50_PAD_SD2_CLK),
272 IMX_PINCTRL_PIN(MX50_PAD_SD2_CMD),
273 IMX_PINCTRL_PIN(MX50_PAD_SD2_D0),
274 IMX_PINCTRL_PIN(MX50_PAD_SD2_D1),
275 IMX_PINCTRL_PIN(MX50_PAD_SD2_D2),
276 IMX_PINCTRL_PIN(MX50_PAD_SD2_D3),
277 IMX_PINCTRL_PIN(MX50_PAD_SD2_D4),
278 IMX_PINCTRL_PIN(MX50_PAD_SD2_D5),
279 IMX_PINCTRL_PIN(MX50_PAD_SD2_D6),
280 IMX_PINCTRL_PIN(MX50_PAD_SD2_D7),
281 IMX_PINCTRL_PIN(MX50_PAD_SD2_WP),
282 IMX_PINCTRL_PIN(MX50_PAD_SD2_CD),
283 IMX_PINCTRL_PIN(MX50_PAD_DISP_D0),
284 IMX_PINCTRL_PIN(MX50_PAD_DISP_D1),
285 IMX_PINCTRL_PIN(MX50_PAD_DISP_D2),
286 IMX_PINCTRL_PIN(MX50_PAD_DISP_D3),
287 IMX_PINCTRL_PIN(MX50_PAD_DISP_D4),
288 IMX_PINCTRL_PIN(MX50_PAD_DISP_D5),
289 IMX_PINCTRL_PIN(MX50_PAD_DISP_D6),
290 IMX_PINCTRL_PIN(MX50_PAD_DISP_D7),
291 IMX_PINCTRL_PIN(MX50_PAD_DISP_WR),
292 IMX_PINCTRL_PIN(MX50_PAD_DISP_RD),
293 IMX_PINCTRL_PIN(MX50_PAD_DISP_RS),
294 IMX_PINCTRL_PIN(MX50_PAD_DISP_CS),
295 IMX_PINCTRL_PIN(MX50_PAD_DISP_BUSY),
296 IMX_PINCTRL_PIN(MX50_PAD_DISP_RESET),
297 IMX_PINCTRL_PIN(MX50_PAD_SD3_CLK),
298 IMX_PINCTRL_PIN(MX50_PAD_SD3_CMD),
299 IMX_PINCTRL_PIN(MX50_PAD_SD3_D0),
300 IMX_PINCTRL_PIN(MX50_PAD_SD3_D1),
301 IMX_PINCTRL_PIN(MX50_PAD_SD3_D2),
302 IMX_PINCTRL_PIN(MX50_PAD_SD3_D3),
303 IMX_PINCTRL_PIN(MX50_PAD_SD3_D4),
304 IMX_PINCTRL_PIN(MX50_PAD_SD3_D5),
305 IMX_PINCTRL_PIN(MX50_PAD_SD3_D6),
306 IMX_PINCTRL_PIN(MX50_PAD_SD3_D7),
307 IMX_PINCTRL_PIN(MX50_PAD_SD3_WP),
308 IMX_PINCTRL_PIN(MX50_PAD_DISP_D8),
309 IMX_PINCTRL_PIN(MX50_PAD_DISP_D9),
310 IMX_PINCTRL_PIN(MX50_PAD_DISP_D10),
311 IMX_PINCTRL_PIN(MX50_PAD_DISP_D11),
312 IMX_PINCTRL_PIN(MX50_PAD_DISP_D12),
313 IMX_PINCTRL_PIN(MX50_PAD_DISP_D13),
314 IMX_PINCTRL_PIN(MX50_PAD_DISP_D14),
315 IMX_PINCTRL_PIN(MX50_PAD_DISP_D15),
316 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D0),
317 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D1),
318 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D2),
319 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D3),
320 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D4),
321 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D5),
322 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D6),
323 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D7),
324 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D8),
325 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D9),
326 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D10),
327 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D11),
328 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D12),
329 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D13),
330 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D14),
331 IMX_PINCTRL_PIN(MX50_PAD_EPDC_D15),
332 IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDCLK),
333 IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDSP),
334 IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDOE),
335 IMX_PINCTRL_PIN(MX50_PAD_EPDC_GDRL),
336 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLK),
337 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOEZ),
338 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOED),
339 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDOE),
340 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDLE),
341 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCLKN),
342 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDSHR),
343 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCOM),
344 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRSTAT),
345 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL0),
346 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL1),
347 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL2),
348 IMX_PINCTRL_PIN(MX50_PAD_EPDC_PWRCTRL3),
349 IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM0),
350 IMX_PINCTRL_PIN(MX50_PAD_EPDC_VCOM1),
351 IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR0),
352 IMX_PINCTRL_PIN(MX50_PAD_EPDC_BDR1),
353 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE0),
354 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE1),
355 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE2),
356 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE3),
357 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE4),
358 IMX_PINCTRL_PIN(MX50_PAD_EPDC_SDCE5),
359 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA0),
360 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA1),
361 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA2),
362 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA3),
363 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA4),
364 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA5),
365 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA6),
366 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA7),
367 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA8),
368 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA9),
369 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA10),
370 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA11),
371 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA12),
372 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA13),
373 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA14),
374 IMX_PINCTRL_PIN(MX50_PAD_EIM_DA15),
375 IMX_PINCTRL_PIN(MX50_PAD_EIM_CS2),
376 IMX_PINCTRL_PIN(MX50_PAD_EIM_CS1),
377 IMX_PINCTRL_PIN(MX50_PAD_EIM_CS0),
378 IMX_PINCTRL_PIN(MX50_PAD_EIM_EB0),
379 IMX_PINCTRL_PIN(MX50_PAD_EIM_EB1),
380 IMX_PINCTRL_PIN(MX50_PAD_EIM_WAIT),
381 IMX_PINCTRL_PIN(MX50_PAD_EIM_BCLK),
382 IMX_PINCTRL_PIN(MX50_PAD_EIM_RDY),
383 IMX_PINCTRL_PIN(MX50_PAD_EIM_OE),
384 IMX_PINCTRL_PIN(MX50_PAD_EIM_RW),
385 IMX_PINCTRL_PIN(MX50_PAD_EIM_LBA),
386 IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
387};
388
389static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
390 .pins = imx50_pinctrl_pads,
391 .npins = ARRAY_SIZE(imx50_pinctrl_pads),
392};
393
394static struct of_device_id imx50_pinctrl_of_match[] = {
395 { .compatible = "fsl,imx50-iomuxc", },
396 { /* sentinel */ }
397};
398
399static int imx50_pinctrl_probe(struct platform_device *pdev)
400{
401 return imx_pinctrl_probe(pdev, &imx50_pinctrl_info);
402}
403
404static struct platform_driver imx50_pinctrl_driver = {
405 .driver = {
406 .name = "imx50-pinctrl",
407 .owner = THIS_MODULE,
408 .of_match_table = of_match_ptr(imx50_pinctrl_of_match),
409 },
410 .probe = imx50_pinctrl_probe,
411 .remove = imx_pinctrl_remove,
412};
413
414static int __init imx50_pinctrl_init(void)
415{
416 return platform_driver_register(&imx50_pinctrl_driver);
417}
418arch_initcall(imx50_pinctrl_init);
419
420static void __exit imx50_pinctrl_exit(void)
421{
422 platform_driver_unregister(&imx50_pinctrl_driver);
423}
424module_exit(imx50_pinctrl_exit);
425MODULE_DESCRIPTION("Freescale IMX50 pinctrl driver");
426MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx51.c b/drivers/pinctrl/pinctrl-imx51.c
index db268b920079..19ab182bef61 100644
--- a/drivers/pinctrl/pinctrl-imx51.c
+++ b/drivers/pinctrl/pinctrl-imx51.c
@@ -782,7 +782,7 @@ static struct platform_driver imx51_pinctrl_driver = {
782 .driver = { 782 .driver = {
783 .name = "imx51-pinctrl", 783 .name = "imx51-pinctrl",
784 .owner = THIS_MODULE, 784 .owner = THIS_MODULE,
785 .of_match_table = of_match_ptr(imx51_pinctrl_of_match), 785 .of_match_table = imx51_pinctrl_of_match,
786 }, 786 },
787 .probe = imx51_pinctrl_probe, 787 .probe = imx51_pinctrl_probe,
788 .remove = imx_pinctrl_remove, 788 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx53.c b/drivers/pinctrl/pinctrl-imx53.c
index 17562ae9005c..f8d45c4cfde7 100644
--- a/drivers/pinctrl/pinctrl-imx53.c
+++ b/drivers/pinctrl/pinctrl-imx53.c
@@ -468,7 +468,7 @@ static struct platform_driver imx53_pinctrl_driver = {
468 .driver = { 468 .driver = {
469 .name = "imx53-pinctrl", 469 .name = "imx53-pinctrl",
470 .owner = THIS_MODULE, 470 .owner = THIS_MODULE,
471 .of_match_table = of_match_ptr(imx53_pinctrl_of_match), 471 .of_match_table = imx53_pinctrl_of_match,
472 }, 472 },
473 .probe = imx53_pinctrl_probe, 473 .probe = imx53_pinctrl_probe,
474 .remove = imx_pinctrl_remove, 474 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx6dl.c b/drivers/pinctrl/pinctrl-imx6dl.c
index a76b72427936..db2a1489bd99 100644
--- a/drivers/pinctrl/pinctrl-imx6dl.c
+++ b/drivers/pinctrl/pinctrl-imx6dl.c
@@ -474,7 +474,7 @@ static struct platform_driver imx6dl_pinctrl_driver = {
474 .driver = { 474 .driver = {
475 .name = "imx6dl-pinctrl", 475 .name = "imx6dl-pinctrl",
476 .owner = THIS_MODULE, 476 .owner = THIS_MODULE,
477 .of_match_table = of_match_ptr(imx6dl_pinctrl_of_match), 477 .of_match_table = imx6dl_pinctrl_of_match,
478 }, 478 },
479 .probe = imx6dl_pinctrl_probe, 479 .probe = imx6dl_pinctrl_probe,
480 .remove = imx_pinctrl_remove, 480 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx6q.c b/drivers/pinctrl/pinctrl-imx6q.c
index 76dd9c4949f4..8eb5ac1bd5f6 100644
--- a/drivers/pinctrl/pinctrl-imx6q.c
+++ b/drivers/pinctrl/pinctrl-imx6q.c
@@ -480,7 +480,7 @@ static struct platform_driver imx6q_pinctrl_driver = {
480 .driver = { 480 .driver = {
481 .name = "imx6q-pinctrl", 481 .name = "imx6q-pinctrl",
482 .owner = THIS_MODULE, 482 .owner = THIS_MODULE,
483 .of_match_table = of_match_ptr(imx6q_pinctrl_of_match), 483 .of_match_table = imx6q_pinctrl_of_match,
484 }, 484 },
485 .probe = imx6q_pinctrl_probe, 485 .probe = imx6q_pinctrl_probe,
486 .remove = imx_pinctrl_remove, 486 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-imx6sl.c b/drivers/pinctrl/pinctrl-imx6sl.c
index 4eb7ccab5f2d..f21b7389df3c 100644
--- a/drivers/pinctrl/pinctrl-imx6sl.c
+++ b/drivers/pinctrl/pinctrl-imx6sl.c
@@ -380,7 +380,7 @@ static struct platform_driver imx6sl_pinctrl_driver = {
380 .driver = { 380 .driver = {
381 .name = "imx6sl-pinctrl", 381 .name = "imx6sl-pinctrl",
382 .owner = THIS_MODULE, 382 .owner = THIS_MODULE,
383 .of_match_table = of_match_ptr(imx6sl_pinctrl_of_match), 383 .of_match_table = imx6sl_pinctrl_of_match,
384 }, 384 },
385 .probe = imx6sl_pinctrl_probe, 385 .probe = imx6sl_pinctrl_probe,
386 .remove = imx_pinctrl_remove, 386 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinctrl-palmas.c b/drivers/pinctrl/pinctrl-palmas.c
index 30c4d356cb33..f13d0e78a41c 100644
--- a/drivers/pinctrl/pinctrl-palmas.c
+++ b/drivers/pinctrl/pinctrl-palmas.c
@@ -891,9 +891,6 @@ static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
891 param = pinconf_to_config_param(configs[i]); 891 param = pinconf_to_config_param(configs[i]);
892 param_val = pinconf_to_config_argument(configs[i]); 892 param_val = pinconf_to_config_argument(configs[i]);
893 893
894 if (param == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
895 continue;
896
897 switch (param) { 894 switch (param) {
898 case PIN_CONFIG_BIAS_DISABLE: 895 case PIN_CONFIG_BIAS_DISABLE:
899 case PIN_CONFIG_BIAS_PULL_UP: 896 case PIN_CONFIG_BIAS_PULL_UP:
@@ -962,26 +959,9 @@ static int palmas_pinconf_set(struct pinctrl_dev *pctldev,
962 return 0; 959 return 0;
963} 960}
964 961
965static int palmas_pinconf_group_get(struct pinctrl_dev *pctldev,
966 unsigned group, unsigned long *config)
967{
968 dev_err(pctldev->dev, "palmas_pinconf_group_get op not supported\n");
969 return -ENOTSUPP;
970}
971
972static int palmas_pinconf_group_set(struct pinctrl_dev *pctldev,
973 unsigned group, unsigned long *configs,
974 unsigned num_configs)
975{
976 dev_err(pctldev->dev, "palmas_pinconf_group_set op not supported\n");
977 return -ENOTSUPP;
978}
979
980static const struct pinconf_ops palmas_pinconf_ops = { 962static const struct pinconf_ops palmas_pinconf_ops = {
981 .pin_config_get = palmas_pinconf_get, 963 .pin_config_get = palmas_pinconf_get,
982 .pin_config_set = palmas_pinconf_set, 964 .pin_config_set = palmas_pinconf_set,
983 .pin_config_group_get = palmas_pinconf_group_get,
984 .pin_config_group_set = palmas_pinconf_group_set,
985}; 965};
986 966
987static struct pinctrl_desc palmas_pinctrl_desc = { 967static struct pinctrl_desc palmas_pinctrl_desc = {
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index e0718b7c4abc..e939c28cbf1f 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -56,8 +56,20 @@
56#define GPIO_EXT_PORT 0x50 56#define GPIO_EXT_PORT 0x50
57#define GPIO_LS_SYNC 0x60 57#define GPIO_LS_SYNC 0x60
58 58
59enum rockchip_pinctrl_type {
60 RK2928,
61 RK3066B,
62 RK3188,
63};
64
65enum rockchip_pin_bank_type {
66 COMMON_BANK,
67 RK3188_BANK0,
68};
69
59/** 70/**
60 * @reg_base: register base of the gpio bank 71 * @reg_base: register base of the gpio bank
72 * @reg_pull: optional separate register for additional pull settings
61 * @clk: clock of the gpio bank 73 * @clk: clock of the gpio bank
62 * @irq: interrupt of the gpio bank 74 * @irq: interrupt of the gpio bank
63 * @pin_base: first pin number 75 * @pin_base: first pin number
@@ -74,12 +86,14 @@
74 */ 86 */
75struct rockchip_pin_bank { 87struct rockchip_pin_bank {
76 void __iomem *reg_base; 88 void __iomem *reg_base;
89 void __iomem *reg_pull;
77 struct clk *clk; 90 struct clk *clk;
78 int irq; 91 int irq;
79 u32 pin_base; 92 u32 pin_base;
80 u8 nr_pins; 93 u8 nr_pins;
81 char *name; 94 char *name;
82 u8 bank_num; 95 u8 bank_num;
96 enum rockchip_pin_bank_type bank_type;
83 bool valid; 97 bool valid;
84 struct device_node *of_node; 98 struct device_node *of_node;
85 struct rockchip_pinctrl *drvdata; 99 struct rockchip_pinctrl *drvdata;
@@ -87,7 +101,7 @@ struct rockchip_pin_bank {
87 struct gpio_chip gpio_chip; 101 struct gpio_chip gpio_chip;
88 struct pinctrl_gpio_range grange; 102 struct pinctrl_gpio_range grange;
89 spinlock_t slock; 103 spinlock_t slock;
90 104 u32 toggle_edge_mode;
91}; 105};
92 106
93#define PIN_BANK(id, pins, label) \ 107#define PIN_BANK(id, pins, label) \
@@ -98,18 +112,16 @@ struct rockchip_pin_bank {
98 } 112 }
99 113
100/** 114/**
101 * @pull_auto: some SoCs don't allow pulls to be specified as up or down, but
102 * instead decide this automatically based on the pad-type.
103 */ 115 */
104struct rockchip_pin_ctrl { 116struct rockchip_pin_ctrl {
105 struct rockchip_pin_bank *pin_banks; 117 struct rockchip_pin_bank *pin_banks;
106 u32 nr_banks; 118 u32 nr_banks;
107 u32 nr_pins; 119 u32 nr_pins;
108 char *label; 120 char *label;
121 enum rockchip_pinctrl_type type;
109 int mux_offset; 122 int mux_offset;
110 int pull_offset; 123 void (*pull_calc_reg)(struct rockchip_pin_bank *bank, int pin_num,
111 bool pull_auto; 124 void __iomem **reg, u8 *bit);
112 int pull_bank_stride;
113}; 125};
114 126
115struct rockchip_pin_config { 127struct rockchip_pin_config {
@@ -148,6 +160,7 @@ struct rockchip_pmx_func {
148 160
149struct rockchip_pinctrl { 161struct rockchip_pinctrl {
150 void __iomem *reg_base; 162 void __iomem *reg_base;
163 void __iomem *reg_pull;
151 struct device *dev; 164 struct device *dev;
152 struct rockchip_pin_ctrl *ctrl; 165 struct rockchip_pin_ctrl *ctrl;
153 struct pinctrl_desc pctl; 166 struct pinctrl_desc pctl;
@@ -354,31 +367,92 @@ static void rockchip_set_mux(struct rockchip_pin_bank *bank, int pin, int mux)
354 spin_unlock_irqrestore(&bank->slock, flags); 367 spin_unlock_irqrestore(&bank->slock, flags);
355} 368}
356 369
370#define RK2928_PULL_OFFSET 0x118
371#define RK2928_PULL_PINS_PER_REG 16
372#define RK2928_PULL_BANK_STRIDE 8
373
374static void rk2928_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
375 int pin_num, void __iomem **reg, u8 *bit)
376{
377 struct rockchip_pinctrl *info = bank->drvdata;
378
379 *reg = info->reg_base + RK2928_PULL_OFFSET;
380 *reg += bank->bank_num * RK2928_PULL_BANK_STRIDE;
381 *reg += (pin_num / RK2928_PULL_PINS_PER_REG) * 4;
382
383 *bit = pin_num % RK2928_PULL_PINS_PER_REG;
384};
385
386#define RK3188_PULL_BITS_PER_PIN 2
387#define RK3188_PULL_PINS_PER_REG 8
388#define RK3188_PULL_BANK_STRIDE 16
389
390static void rk3188_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
391 int pin_num, void __iomem **reg, u8 *bit)
392{
393 struct rockchip_pinctrl *info = bank->drvdata;
394
395 /* The first 12 pins of the first bank are located elsewhere */
396 if (bank->bank_type == RK3188_BANK0 && pin_num < 12) {
397 *reg = bank->reg_pull +
398 ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
399 *bit = pin_num % RK3188_PULL_PINS_PER_REG;
400 *bit *= RK3188_PULL_BITS_PER_PIN;
401 } else {
402 *reg = info->reg_pull - 4;
403 *reg += bank->bank_num * RK3188_PULL_BANK_STRIDE;
404 *reg += ((pin_num / RK3188_PULL_PINS_PER_REG) * 4);
405
406 /*
407 * The bits in these registers have an inverse ordering
408 * with the lowest pin being in bits 15:14 and the highest
409 * pin in bits 1:0
410 */
411 *bit = 7 - (pin_num % RK3188_PULL_PINS_PER_REG);
412 *bit *= RK3188_PULL_BITS_PER_PIN;
413 }
414}
415
357static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) 416static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
358{ 417{
359 struct rockchip_pinctrl *info = bank->drvdata; 418 struct rockchip_pinctrl *info = bank->drvdata;
360 struct rockchip_pin_ctrl *ctrl = info->ctrl; 419 struct rockchip_pin_ctrl *ctrl = info->ctrl;
361 void __iomem *reg; 420 void __iomem *reg;
362 u8 bit; 421 u8 bit;
422 u32 data;
363 423
364 /* rk3066b does support any pulls */ 424 /* rk3066b does support any pulls */
365 if (!ctrl->pull_offset) 425 if (ctrl->type == RK3066B)
366 return PIN_CONFIG_BIAS_DISABLE; 426 return PIN_CONFIG_BIAS_DISABLE;
367 427
368 reg = info->reg_base + ctrl->pull_offset; 428 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
369
370 if (ctrl->pull_auto) {
371 reg += bank->bank_num * ctrl->pull_bank_stride;
372 reg += (pin_num / 16) * 4;
373 bit = pin_num % 16;
374 429
430 switch (ctrl->type) {
431 case RK2928:
375 return !(readl_relaxed(reg) & BIT(bit)) 432 return !(readl_relaxed(reg) & BIT(bit))
376 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT 433 ? PIN_CONFIG_BIAS_PULL_PIN_DEFAULT
377 : PIN_CONFIG_BIAS_DISABLE; 434 : PIN_CONFIG_BIAS_DISABLE;
378 } else { 435 case RK3188:
379 dev_err(info->dev, "pull support for rk31xx not implemented\n"); 436 data = readl_relaxed(reg) >> bit;
437 data &= (1 << RK3188_PULL_BITS_PER_PIN) - 1;
438
439 switch (data) {
440 case 0:
441 return PIN_CONFIG_BIAS_DISABLE;
442 case 1:
443 return PIN_CONFIG_BIAS_PULL_UP;
444 case 2:
445 return PIN_CONFIG_BIAS_PULL_DOWN;
446 case 3:
447 return PIN_CONFIG_BIAS_BUS_HOLD;
448 }
449
450 dev_err(info->dev, "unknown pull setting\n");
380 return -EIO; 451 return -EIO;
381 } 452 default:
453 dev_err(info->dev, "unsupported pinctrl type\n");
454 return -EINVAL;
455 };
382} 456}
383 457
384static int rockchip_set_pull(struct rockchip_pin_bank *bank, 458static int rockchip_set_pull(struct rockchip_pin_bank *bank,
@@ -395,22 +469,13 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
395 bank->bank_num, pin_num, pull); 469 bank->bank_num, pin_num, pull);
396 470
397 /* rk3066b does support any pulls */ 471 /* rk3066b does support any pulls */
398 if (!ctrl->pull_offset) 472 if (ctrl->type == RK3066B)
399 return pull ? -EINVAL : 0; 473 return pull ? -EINVAL : 0;
400 474
401 reg = info->reg_base + ctrl->pull_offset; 475 ctrl->pull_calc_reg(bank, pin_num, &reg, &bit);
402
403 if (ctrl->pull_auto) {
404 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
405 pull != PIN_CONFIG_BIAS_DISABLE) {
406 dev_err(info->dev, "only PIN_DEFAULT and DISABLE allowed\n");
407 return -EINVAL;
408 }
409
410 reg += bank->bank_num * ctrl->pull_bank_stride;
411 reg += (pin_num / 16) * 4;
412 bit = pin_num % 16;
413 476
477 switch (ctrl->type) {
478 case RK2928:
414 spin_lock_irqsave(&bank->slock, flags); 479 spin_lock_irqsave(&bank->slock, flags);
415 480
416 data = BIT(bit + 16); 481 data = BIT(bit + 16);
@@ -419,14 +484,38 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
419 writel(data, reg); 484 writel(data, reg);
420 485
421 spin_unlock_irqrestore(&bank->slock, flags); 486 spin_unlock_irqrestore(&bank->slock, flags);
422 } else { 487 break;
423 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT) { 488 case RK3188:
424 dev_err(info->dev, "pull direction (up/down) needs to be specified\n"); 489 spin_lock_irqsave(&bank->slock, flags);
490
491 /* enable the write to the equivalent lower bits */
492 data = ((1 << RK3188_PULL_BITS_PER_PIN) - 1) << (bit + 16);
493
494 switch (pull) {
495 case PIN_CONFIG_BIAS_DISABLE:
496 break;
497 case PIN_CONFIG_BIAS_PULL_UP:
498 data |= (1 << bit);
499 break;
500 case PIN_CONFIG_BIAS_PULL_DOWN:
501 data |= (2 << bit);
502 break;
503 case PIN_CONFIG_BIAS_BUS_HOLD:
504 data |= (3 << bit);
505 break;
506 default:
507 dev_err(info->dev, "unsupported pull setting %d\n",
508 pull);
425 return -EINVAL; 509 return -EINVAL;
426 } 510 }
427 511
428 dev_err(info->dev, "pull support for rk31xx not implemented\n"); 512 writel(data, reg);
429 return -EIO; 513
514 spin_unlock_irqrestore(&bank->slock, flags);
515 break;
516 default:
517 dev_err(info->dev, "unsupported pinctrl type\n");
518 return -EINVAL;
430 } 519 }
431 520
432 return 0; 521 return 0;
@@ -556,20 +645,17 @@ static const struct pinmux_ops rockchip_pmx_ops = {
556static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, 645static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
557 enum pin_config_param pull) 646 enum pin_config_param pull)
558{ 647{
559 /* rk3066b does support any pulls */ 648 switch (ctrl->type) {
560 if (!ctrl->pull_offset) 649 case RK2928:
650 return (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT ||
651 pull == PIN_CONFIG_BIAS_DISABLE);
652 case RK3066B:
561 return pull ? false : true; 653 return pull ? false : true;
562 654 case RK3188:
563 if (ctrl->pull_auto) { 655 return (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT);
564 if (pull != PIN_CONFIG_BIAS_PULL_PIN_DEFAULT &&
565 pull != PIN_CONFIG_BIAS_DISABLE)
566 return false;
567 } else {
568 if (pull == PIN_CONFIG_BIAS_PULL_PIN_DEFAULT)
569 return false;
570 } 656 }
571 657
572 return true; 658 return false;
573} 659}
574 660
575/* set the pin config settings for a specified pin */ 661/* set the pin config settings for a specified pin */
@@ -597,6 +683,7 @@ static int rockchip_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
597 case PIN_CONFIG_BIAS_PULL_UP: 683 case PIN_CONFIG_BIAS_PULL_UP:
598 case PIN_CONFIG_BIAS_PULL_DOWN: 684 case PIN_CONFIG_BIAS_PULL_DOWN:
599 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 685 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
686 case PIN_CONFIG_BIAS_BUS_HOLD:
600 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 687 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
601 return -ENOTSUPP; 688 return -ENOTSUPP;
602 689
@@ -635,6 +722,7 @@ static int rockchip_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
635 case PIN_CONFIG_BIAS_PULL_UP: 722 case PIN_CONFIG_BIAS_PULL_UP:
636 case PIN_CONFIG_BIAS_PULL_DOWN: 723 case PIN_CONFIG_BIAS_PULL_DOWN:
637 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT: 724 case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
725 case PIN_CONFIG_BIAS_BUS_HOLD:
638 if (!rockchip_pinconf_pull_valid(info->ctrl, param)) 726 if (!rockchip_pinconf_pull_valid(info->ctrl, param))
639 return -ENOTSUPP; 727 return -ENOTSUPP;
640 728
@@ -656,7 +744,11 @@ static const struct pinconf_ops rockchip_pinconf_ops = {
656 .pin_config_set = rockchip_pinconf_set, 744 .pin_config_set = rockchip_pinconf_set,
657}; 745};
658 746
659static const char *gpio_compat = "rockchip,gpio-bank"; 747static const struct of_device_id rockchip_bank_match[] = {
748 { .compatible = "rockchip,gpio-bank" },
749 { .compatible = "rockchip,rk3188-gpio-bank0" },
750 {},
751};
660 752
661static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info, 753static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
662 struct device_node *np) 754 struct device_node *np)
@@ -664,7 +756,7 @@ static void rockchip_pinctrl_child_count(struct rockchip_pinctrl *info,
664 struct device_node *child; 756 struct device_node *child;
665 757
666 for_each_child_of_node(np, child) { 758 for_each_child_of_node(np, child) {
667 if (of_device_is_compatible(child, gpio_compat)) 759 if (of_match_node(rockchip_bank_match, child))
668 continue; 760 continue;
669 761
670 info->nfunctions++; 762 info->nfunctions++;
@@ -807,8 +899,9 @@ static int rockchip_pinctrl_parse_dt(struct platform_device *pdev,
807 i = 0; 899 i = 0;
808 900
809 for_each_child_of_node(np, child) { 901 for_each_child_of_node(np, child) {
810 if (of_device_is_compatible(child, gpio_compat)) 902 if (of_match_node(rockchip_bank_match, child))
811 continue; 903 continue;
904
812 ret = rockchip_pinctrl_parse_functions(child, info, i++); 905 ret = rockchip_pinctrl_parse_functions(child, info, i++);
813 if (ret) { 906 if (ret) {
814 dev_err(&pdev->dev, "failed to parse function\n"); 907 dev_err(&pdev->dev, "failed to parse function\n");
@@ -985,7 +1078,9 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
985{ 1078{
986 struct irq_chip *chip = irq_get_chip(irq); 1079 struct irq_chip *chip = irq_get_chip(irq);
987 struct rockchip_pin_bank *bank = irq_get_handler_data(irq); 1080 struct rockchip_pin_bank *bank = irq_get_handler_data(irq);
1081 u32 polarity = 0, data = 0;
988 u32 pend; 1082 u32 pend;
1083 bool edge_changed = false;
989 1084
990 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name); 1085 dev_dbg(bank->drvdata->dev, "got irq for bank %s\n", bank->name);
991 1086
@@ -993,6 +1088,12 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
993 1088
994 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS); 1089 pend = readl_relaxed(bank->reg_base + GPIO_INT_STATUS);
995 1090
1091 if (bank->toggle_edge_mode) {
1092 polarity = readl_relaxed(bank->reg_base +
1093 GPIO_INT_POLARITY);
1094 data = readl_relaxed(bank->reg_base + GPIO_EXT_PORT);
1095 }
1096
996 while (pend) { 1097 while (pend) {
997 unsigned int virq; 1098 unsigned int virq;
998 1099
@@ -1007,9 +1108,30 @@ static void rockchip_irq_demux(unsigned int irq, struct irq_desc *desc)
1007 1108
1008 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq); 1109 dev_dbg(bank->drvdata->dev, "handling irq %d\n", irq);
1009 1110
1111 /*
1112 * Triggering IRQ on both rising and falling edge
1113 * needs manual intervention.
1114 */
1115 if (bank->toggle_edge_mode & BIT(irq)) {
1116 if (data & BIT(irq))
1117 polarity &= ~BIT(irq);
1118 else
1119 polarity |= BIT(irq);
1120
1121 edge_changed = true;
1122 }
1123
1010 generic_handle_irq(virq); 1124 generic_handle_irq(virq);
1011 } 1125 }
1012 1126
1127 if (bank->toggle_edge_mode && edge_changed) {
1128 /* Interrupt params should only be set with ints disabled */
1129 data = readl_relaxed(bank->reg_base + GPIO_INTEN);
1130 writel_relaxed(0, bank->reg_base + GPIO_INTEN);
1131 writel(polarity, bank->reg_base + GPIO_INT_POLARITY);
1132 writel(data, bank->reg_base + GPIO_INTEN);
1133 }
1134
1013 chained_irq_exit(chip, desc); 1135 chained_irq_exit(chip, desc);
1014} 1136}
1015 1137
@@ -1022,6 +1144,12 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1022 u32 level; 1144 u32 level;
1023 u32 data; 1145 u32 data;
1024 1146
1147 /* make sure the pin is configured as gpio input */
1148 rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1149 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1150 data &= ~mask;
1151 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1152
1025 if (type & IRQ_TYPE_EDGE_BOTH) 1153 if (type & IRQ_TYPE_EDGE_BOTH)
1026 __irq_set_handler_locked(d->irq, handle_edge_irq); 1154 __irq_set_handler_locked(d->irq, handle_edge_irq);
1027 else 1155 else
@@ -1033,19 +1161,37 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1033 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY); 1161 polarity = readl_relaxed(gc->reg_base + GPIO_INT_POLARITY);
1034 1162
1035 switch (type) { 1163 switch (type) {
1164 case IRQ_TYPE_EDGE_BOTH:
1165 bank->toggle_edge_mode |= mask;
1166 level |= mask;
1167
1168 /*
1169 * Determine gpio state. If 1 next interrupt should be falling
1170 * otherwise rising.
1171 */
1172 data = readl(bank->reg_base + GPIO_EXT_PORT);
1173 if (data & mask)
1174 polarity &= ~mask;
1175 else
1176 polarity |= mask;
1177 break;
1036 case IRQ_TYPE_EDGE_RISING: 1178 case IRQ_TYPE_EDGE_RISING:
1179 bank->toggle_edge_mode &= ~mask;
1037 level |= mask; 1180 level |= mask;
1038 polarity |= mask; 1181 polarity |= mask;
1039 break; 1182 break;
1040 case IRQ_TYPE_EDGE_FALLING: 1183 case IRQ_TYPE_EDGE_FALLING:
1184 bank->toggle_edge_mode &= ~mask;
1041 level |= mask; 1185 level |= mask;
1042 polarity &= ~mask; 1186 polarity &= ~mask;
1043 break; 1187 break;
1044 case IRQ_TYPE_LEVEL_HIGH: 1188 case IRQ_TYPE_LEVEL_HIGH:
1189 bank->toggle_edge_mode &= ~mask;
1045 level &= ~mask; 1190 level &= ~mask;
1046 polarity |= mask; 1191 polarity |= mask;
1047 break; 1192 break;
1048 case IRQ_TYPE_LEVEL_LOW: 1193 case IRQ_TYPE_LEVEL_LOW:
1194 bank->toggle_edge_mode &= ~mask;
1049 level &= ~mask; 1195 level &= ~mask;
1050 polarity &= ~mask; 1196 polarity &= ~mask;
1051 break; 1197 break;
@@ -1059,12 +1205,6 @@ static int rockchip_irq_set_type(struct irq_data *d, unsigned int type)
1059 1205
1060 irq_gc_unlock(gc); 1206 irq_gc_unlock(gc);
1061 1207
1062 /* make sure the pin is configured as gpio input */
1063 rockchip_set_mux(bank, d->hwirq, RK_FUNC_GPIO);
1064 data = readl_relaxed(bank->reg_base + GPIO_SWPORT_DDR);
1065 data &= ~mask;
1066 writel_relaxed(data, bank->reg_base + GPIO_SWPORT_DDR);
1067
1068 return 0; 1208 return 0;
1069} 1209}
1070 1210
@@ -1205,6 +1345,26 @@ static int rockchip_get_bank_data(struct rockchip_pin_bank *bank,
1205 if (IS_ERR(bank->reg_base)) 1345 if (IS_ERR(bank->reg_base))
1206 return PTR_ERR(bank->reg_base); 1346 return PTR_ERR(bank->reg_base);
1207 1347
1348 /*
1349 * special case, where parts of the pull setting-registers are
1350 * part of the PMU register space
1351 */
1352 if (of_device_is_compatible(bank->of_node,
1353 "rockchip,rk3188-gpio-bank0")) {
1354 bank->bank_type = RK3188_BANK0;
1355
1356 if (of_address_to_resource(bank->of_node, 1, &res)) {
1357 dev_err(dev, "cannot find IO resource for bank\n");
1358 return -ENOENT;
1359 }
1360
1361 bank->reg_pull = devm_ioremap_resource(dev, &res);
1362 if (IS_ERR(bank->reg_pull))
1363 return PTR_ERR(bank->reg_pull);
1364 } else {
1365 bank->bank_type = COMMON_BANK;
1366 }
1367
1208 bank->irq = irq_of_parse_and_map(bank->of_node, 0); 1368 bank->irq = irq_of_parse_and_map(bank->of_node, 0);
1209 1369
1210 bank->clk = of_clk_get(bank->of_node, 0); 1370 bank->clk = of_clk_get(bank->of_node, 0);
@@ -1289,6 +1449,14 @@ static int rockchip_pinctrl_probe(struct platform_device *pdev)
1289 if (IS_ERR(info->reg_base)) 1449 if (IS_ERR(info->reg_base))
1290 return PTR_ERR(info->reg_base); 1450 return PTR_ERR(info->reg_base);
1291 1451
1452 /* The RK3188 has its pull registers in a separate place */
1453 if (ctrl->type == RK3188) {
1454 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1455 info->reg_pull = devm_ioremap_resource(&pdev->dev, res);
1456 if (IS_ERR(info->reg_base))
1457 return PTR_ERR(info->reg_base);
1458 }
1459
1292 ret = rockchip_gpiolib_register(pdev, info); 1460 ret = rockchip_gpiolib_register(pdev, info);
1293 if (ret) 1461 if (ret)
1294 return ret; 1462 return ret;
@@ -1315,10 +1483,9 @@ static struct rockchip_pin_ctrl rk2928_pin_ctrl = {
1315 .pin_banks = rk2928_pin_banks, 1483 .pin_banks = rk2928_pin_banks,
1316 .nr_banks = ARRAY_SIZE(rk2928_pin_banks), 1484 .nr_banks = ARRAY_SIZE(rk2928_pin_banks),
1317 .label = "RK2928-GPIO", 1485 .label = "RK2928-GPIO",
1486 .type = RK2928,
1318 .mux_offset = 0xa8, 1487 .mux_offset = 0xa8,
1319 .pull_offset = 0x118, 1488 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1320 .pull_auto = 1,
1321 .pull_bank_stride = 8,
1322}; 1489};
1323 1490
1324static struct rockchip_pin_bank rk3066a_pin_banks[] = { 1491static struct rockchip_pin_bank rk3066a_pin_banks[] = {
@@ -1334,10 +1501,9 @@ static struct rockchip_pin_ctrl rk3066a_pin_ctrl = {
1334 .pin_banks = rk3066a_pin_banks, 1501 .pin_banks = rk3066a_pin_banks,
1335 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks), 1502 .nr_banks = ARRAY_SIZE(rk3066a_pin_banks),
1336 .label = "RK3066a-GPIO", 1503 .label = "RK3066a-GPIO",
1504 .type = RK2928,
1337 .mux_offset = 0xa8, 1505 .mux_offset = 0xa8,
1338 .pull_offset = 0x118, 1506 .pull_calc_reg = rk2928_calc_pull_reg_and_bit,
1339 .pull_auto = 1,
1340 .pull_bank_stride = 8,
1341}; 1507};
1342 1508
1343static struct rockchip_pin_bank rk3066b_pin_banks[] = { 1509static struct rockchip_pin_bank rk3066b_pin_banks[] = {
@@ -1351,8 +1517,8 @@ static struct rockchip_pin_ctrl rk3066b_pin_ctrl = {
1351 .pin_banks = rk3066b_pin_banks, 1517 .pin_banks = rk3066b_pin_banks,
1352 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks), 1518 .nr_banks = ARRAY_SIZE(rk3066b_pin_banks),
1353 .label = "RK3066b-GPIO", 1519 .label = "RK3066b-GPIO",
1520 .type = RK3066B,
1354 .mux_offset = 0x60, 1521 .mux_offset = 0x60,
1355 .pull_offset = -EINVAL,
1356}; 1522};
1357 1523
1358static struct rockchip_pin_bank rk3188_pin_banks[] = { 1524static struct rockchip_pin_bank rk3188_pin_banks[] = {
@@ -1366,9 +1532,9 @@ static struct rockchip_pin_ctrl rk3188_pin_ctrl = {
1366 .pin_banks = rk3188_pin_banks, 1532 .pin_banks = rk3188_pin_banks,
1367 .nr_banks = ARRAY_SIZE(rk3188_pin_banks), 1533 .nr_banks = ARRAY_SIZE(rk3188_pin_banks),
1368 .label = "RK3188-GPIO", 1534 .label = "RK3188-GPIO",
1535 .type = RK3188,
1369 .mux_offset = 0x68, 1536 .mux_offset = 0x68,
1370 .pull_offset = 0x164, 1537 .pull_calc_reg = rk3188_calc_pull_reg_and_bit,
1371 .pull_bank_stride = 16,
1372}; 1538};
1373 1539
1374static const struct of_device_id rockchip_pinctrl_dt_match[] = { 1540static const struct of_device_id rockchip_pinctrl_dt_match[] = {
diff --git a/drivers/pinctrl/pinctrl-samsung.c b/drivers/pinctrl/pinctrl-samsung.c
index 92a9d6c8db0a..47ec2e8741e4 100644
--- a/drivers/pinctrl/pinctrl-samsung.c
+++ b/drivers/pinctrl/pinctrl-samsung.c
@@ -1148,7 +1148,7 @@ static struct platform_driver samsung_pinctrl_driver = {
1148 .driver = { 1148 .driver = {
1149 .name = "samsung-pinctrl", 1149 .name = "samsung-pinctrl",
1150 .owner = THIS_MODULE, 1150 .owner = THIS_MODULE,
1151 .of_match_table = of_match_ptr(samsung_pinctrl_dt_match), 1151 .of_match_table = samsung_pinctrl_dt_match,
1152 }, 1152 },
1153}; 1153};
1154 1154
diff --git a/drivers/pinctrl/pinctrl-tb10x.c b/drivers/pinctrl/pinctrl-tb10x.c
new file mode 100644
index 000000000000..c5e0f6973a3b
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-tb10x.c
@@ -0,0 +1,875 @@
1/*
2 * Abilis Systems TB10x pin control driver
3 *
4 * Copyright (C) Abilis Systems 2012
5 *
6 * Author: Christian Ruppert <christian.ruppert@abilis.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
22#include <linux/stringify.h>
23#include <linux/pinctrl/pinctrl.h>
24#include <linux/pinctrl/pinmux.h>
25#include <linux/pinctrl/machine.h>
26#include <linux/platform_device.h>
27#include <linux/module.h>
28#include <linux/mutex.h>
29#include <linux/err.h>
30#include <linux/io.h>
31#include <linux/of.h>
32#include <linux/slab.h>
33
34#include "pinctrl-utils.h"
35
36#define TB10X_PORT1 (0)
37#define TB10X_PORT2 (16)
38#define TB10X_PORT3 (32)
39#define TB10X_PORT4 (48)
40#define TB10X_PORT5 (128)
41#define TB10X_PORT6 (64)
42#define TB10X_PORT7 (80)
43#define TB10X_PORT8 (96)
44#define TB10X_PORT9 (112)
45#define TB10X_GPIOS (256)
46
47#define PCFG_PORT_BITWIDTH (2)
48#define PCFG_PORT_MASK(PORT) \
49 (((1 << PCFG_PORT_BITWIDTH) - 1) << (PCFG_PORT_BITWIDTH * (PORT)))
50
51static const struct pinctrl_pin_desc tb10x_pins[] = {
52 /* Port 1 */
53 PINCTRL_PIN(TB10X_PORT1 + 0, "MICLK_S0"),
54 PINCTRL_PIN(TB10X_PORT1 + 1, "MISTRT_S0"),
55 PINCTRL_PIN(TB10X_PORT1 + 2, "MIVAL_S0"),
56 PINCTRL_PIN(TB10X_PORT1 + 3, "MDI_S0"),
57 PINCTRL_PIN(TB10X_PORT1 + 4, "GPIOA0"),
58 PINCTRL_PIN(TB10X_PORT1 + 5, "GPIOA1"),
59 PINCTRL_PIN(TB10X_PORT1 + 6, "GPIOA2"),
60 PINCTRL_PIN(TB10X_PORT1 + 7, "MDI_S1"),
61 PINCTRL_PIN(TB10X_PORT1 + 8, "MIVAL_S1"),
62 PINCTRL_PIN(TB10X_PORT1 + 9, "MISTRT_S1"),
63 PINCTRL_PIN(TB10X_PORT1 + 10, "MICLK_S1"),
64 /* Port 2 */
65 PINCTRL_PIN(TB10X_PORT2 + 0, "MICLK_S2"),
66 PINCTRL_PIN(TB10X_PORT2 + 1, "MISTRT_S2"),
67 PINCTRL_PIN(TB10X_PORT2 + 2, "MIVAL_S2"),
68 PINCTRL_PIN(TB10X_PORT2 + 3, "MDI_S2"),
69 PINCTRL_PIN(TB10X_PORT2 + 4, "GPIOC0"),
70 PINCTRL_PIN(TB10X_PORT2 + 5, "GPIOC1"),
71 PINCTRL_PIN(TB10X_PORT2 + 6, "GPIOC2"),
72 PINCTRL_PIN(TB10X_PORT2 + 7, "MDI_S3"),
73 PINCTRL_PIN(TB10X_PORT2 + 8, "MIVAL_S3"),
74 PINCTRL_PIN(TB10X_PORT2 + 9, "MISTRT_S3"),
75 PINCTRL_PIN(TB10X_PORT2 + 10, "MICLK_S3"),
76 /* Port 3 */
77 PINCTRL_PIN(TB10X_PORT3 + 0, "MICLK_S4"),
78 PINCTRL_PIN(TB10X_PORT3 + 1, "MISTRT_S4"),
79 PINCTRL_PIN(TB10X_PORT3 + 2, "MIVAL_S4"),
80 PINCTRL_PIN(TB10X_PORT3 + 3, "MDI_S4"),
81 PINCTRL_PIN(TB10X_PORT3 + 4, "GPIOE0"),
82 PINCTRL_PIN(TB10X_PORT3 + 5, "GPIOE1"),
83 PINCTRL_PIN(TB10X_PORT3 + 6, "GPIOE2"),
84 PINCTRL_PIN(TB10X_PORT3 + 7, "MDI_S5"),
85 PINCTRL_PIN(TB10X_PORT3 + 8, "MIVAL_S5"),
86 PINCTRL_PIN(TB10X_PORT3 + 9, "MISTRT_S5"),
87 PINCTRL_PIN(TB10X_PORT3 + 10, "MICLK_S5"),
88 /* Port 4 */
89 PINCTRL_PIN(TB10X_PORT4 + 0, "MICLK_S6"),
90 PINCTRL_PIN(TB10X_PORT4 + 1, "MISTRT_S6"),
91 PINCTRL_PIN(TB10X_PORT4 + 2, "MIVAL_S6"),
92 PINCTRL_PIN(TB10X_PORT4 + 3, "MDI_S6"),
93 PINCTRL_PIN(TB10X_PORT4 + 4, "GPIOG0"),
94 PINCTRL_PIN(TB10X_PORT4 + 5, "GPIOG1"),
95 PINCTRL_PIN(TB10X_PORT4 + 6, "GPIOG2"),
96 PINCTRL_PIN(TB10X_PORT4 + 7, "MDI_S7"),
97 PINCTRL_PIN(TB10X_PORT4 + 8, "MIVAL_S7"),
98 PINCTRL_PIN(TB10X_PORT4 + 9, "MISTRT_S7"),
99 PINCTRL_PIN(TB10X_PORT4 + 10, "MICLK_S7"),
100 /* Port 5 */
101 PINCTRL_PIN(TB10X_PORT5 + 0, "PC_CE1N"),
102 PINCTRL_PIN(TB10X_PORT5 + 1, "PC_CE2N"),
103 PINCTRL_PIN(TB10X_PORT5 + 2, "PC_REGN"),
104 PINCTRL_PIN(TB10X_PORT5 + 3, "PC_INPACKN"),
105 PINCTRL_PIN(TB10X_PORT5 + 4, "PC_OEN"),
106 PINCTRL_PIN(TB10X_PORT5 + 5, "PC_WEN"),
107 PINCTRL_PIN(TB10X_PORT5 + 6, "PC_IORDN"),
108 PINCTRL_PIN(TB10X_PORT5 + 7, "PC_IOWRN"),
109 PINCTRL_PIN(TB10X_PORT5 + 8, "PC_RDYIRQN"),
110 PINCTRL_PIN(TB10X_PORT5 + 9, "PC_WAITN"),
111 PINCTRL_PIN(TB10X_PORT5 + 10, "PC_A0"),
112 PINCTRL_PIN(TB10X_PORT5 + 11, "PC_A1"),
113 PINCTRL_PIN(TB10X_PORT5 + 12, "PC_A2"),
114 PINCTRL_PIN(TB10X_PORT5 + 13, "PC_A3"),
115 PINCTRL_PIN(TB10X_PORT5 + 14, "PC_A4"),
116 PINCTRL_PIN(TB10X_PORT5 + 15, "PC_A5"),
117 PINCTRL_PIN(TB10X_PORT5 + 16, "PC_A6"),
118 PINCTRL_PIN(TB10X_PORT5 + 17, "PC_A7"),
119 PINCTRL_PIN(TB10X_PORT5 + 18, "PC_A8"),
120 PINCTRL_PIN(TB10X_PORT5 + 19, "PC_A9"),
121 PINCTRL_PIN(TB10X_PORT5 + 20, "PC_A10"),
122 PINCTRL_PIN(TB10X_PORT5 + 21, "PC_A11"),
123 PINCTRL_PIN(TB10X_PORT5 + 22, "PC_A12"),
124 PINCTRL_PIN(TB10X_PORT5 + 23, "PC_A13"),
125 PINCTRL_PIN(TB10X_PORT5 + 24, "PC_A14"),
126 PINCTRL_PIN(TB10X_PORT5 + 25, "PC_D0"),
127 PINCTRL_PIN(TB10X_PORT5 + 26, "PC_D1"),
128 PINCTRL_PIN(TB10X_PORT5 + 27, "PC_D2"),
129 PINCTRL_PIN(TB10X_PORT5 + 28, "PC_D3"),
130 PINCTRL_PIN(TB10X_PORT5 + 29, "PC_D4"),
131 PINCTRL_PIN(TB10X_PORT5 + 30, "PC_D5"),
132 PINCTRL_PIN(TB10X_PORT5 + 31, "PC_D6"),
133 PINCTRL_PIN(TB10X_PORT5 + 32, "PC_D7"),
134 PINCTRL_PIN(TB10X_PORT5 + 33, "PC_MOSTRT"),
135 PINCTRL_PIN(TB10X_PORT5 + 34, "PC_MOVAL"),
136 PINCTRL_PIN(TB10X_PORT5 + 35, "PC_MDO0"),
137 PINCTRL_PIN(TB10X_PORT5 + 36, "PC_MDO1"),
138 PINCTRL_PIN(TB10X_PORT5 + 37, "PC_MDO2"),
139 PINCTRL_PIN(TB10X_PORT5 + 38, "PC_MDO3"),
140 PINCTRL_PIN(TB10X_PORT5 + 39, "PC_MDO4"),
141 PINCTRL_PIN(TB10X_PORT5 + 40, "PC_MDO5"),
142 PINCTRL_PIN(TB10X_PORT5 + 41, "PC_MDO6"),
143 PINCTRL_PIN(TB10X_PORT5 + 42, "PC_MDO7"),
144 PINCTRL_PIN(TB10X_PORT5 + 43, "PC_MISTRT"),
145 PINCTRL_PIN(TB10X_PORT5 + 44, "PC_MIVAL"),
146 PINCTRL_PIN(TB10X_PORT5 + 45, "PC_MDI0"),
147 PINCTRL_PIN(TB10X_PORT5 + 46, "PC_MDI1"),
148 PINCTRL_PIN(TB10X_PORT5 + 47, "PC_MDI2"),
149 PINCTRL_PIN(TB10X_PORT5 + 48, "PC_MDI3"),
150 PINCTRL_PIN(TB10X_PORT5 + 49, "PC_MDI4"),
151 PINCTRL_PIN(TB10X_PORT5 + 50, "PC_MDI5"),
152 PINCTRL_PIN(TB10X_PORT5 + 51, "PC_MDI6"),
153 PINCTRL_PIN(TB10X_PORT5 + 52, "PC_MDI7"),
154 PINCTRL_PIN(TB10X_PORT5 + 53, "PC_MICLK"),
155 /* Port 6 */
156 PINCTRL_PIN(TB10X_PORT6 + 0, "T_MOSTRT_S0"),
157 PINCTRL_PIN(TB10X_PORT6 + 1, "T_MOVAL_S0"),
158 PINCTRL_PIN(TB10X_PORT6 + 2, "T_MDO_S0"),
159 PINCTRL_PIN(TB10X_PORT6 + 3, "T_MOSTRT_S1"),
160 PINCTRL_PIN(TB10X_PORT6 + 4, "T_MOVAL_S1"),
161 PINCTRL_PIN(TB10X_PORT6 + 5, "T_MDO_S1"),
162 PINCTRL_PIN(TB10X_PORT6 + 6, "T_MOSTRT_S2"),
163 PINCTRL_PIN(TB10X_PORT6 + 7, "T_MOVAL_S2"),
164 PINCTRL_PIN(TB10X_PORT6 + 8, "T_MDO_S2"),
165 PINCTRL_PIN(TB10X_PORT6 + 9, "T_MOSTRT_S3"),
166 /* Port 7 */
167 PINCTRL_PIN(TB10X_PORT7 + 0, "UART0_TXD"),
168 PINCTRL_PIN(TB10X_PORT7 + 1, "UART0_RXD"),
169 PINCTRL_PIN(TB10X_PORT7 + 2, "UART0_CTS"),
170 PINCTRL_PIN(TB10X_PORT7 + 3, "UART0_RTS"),
171 PINCTRL_PIN(TB10X_PORT7 + 4, "UART1_TXD"),
172 PINCTRL_PIN(TB10X_PORT7 + 5, "UART1_RXD"),
173 PINCTRL_PIN(TB10X_PORT7 + 6, "UART1_CTS"),
174 PINCTRL_PIN(TB10X_PORT7 + 7, "UART1_RTS"),
175 /* Port 8 */
176 PINCTRL_PIN(TB10X_PORT8 + 0, "SPI3_CLK"),
177 PINCTRL_PIN(TB10X_PORT8 + 1, "SPI3_MISO"),
178 PINCTRL_PIN(TB10X_PORT8 + 2, "SPI3_MOSI"),
179 PINCTRL_PIN(TB10X_PORT8 + 3, "SPI3_SSN"),
180 /* Port 9 */
181 PINCTRL_PIN(TB10X_PORT9 + 0, "SPI1_CLK"),
182 PINCTRL_PIN(TB10X_PORT9 + 1, "SPI1_MISO"),
183 PINCTRL_PIN(TB10X_PORT9 + 2, "SPI1_MOSI"),
184 PINCTRL_PIN(TB10X_PORT9 + 3, "SPI1_SSN0"),
185 PINCTRL_PIN(TB10X_PORT9 + 4, "SPI1_SSN1"),
186 /* Unmuxed GPIOs */
187 PINCTRL_PIN(TB10X_GPIOS + 0, "GPIOB0"),
188 PINCTRL_PIN(TB10X_GPIOS + 1, "GPIOB1"),
189
190 PINCTRL_PIN(TB10X_GPIOS + 2, "GPIOD0"),
191 PINCTRL_PIN(TB10X_GPIOS + 3, "GPIOD1"),
192
193 PINCTRL_PIN(TB10X_GPIOS + 4, "GPIOF0"),
194 PINCTRL_PIN(TB10X_GPIOS + 5, "GPIOF1"),
195
196 PINCTRL_PIN(TB10X_GPIOS + 6, "GPIOH0"),
197 PINCTRL_PIN(TB10X_GPIOS + 7, "GPIOH1"),
198
199 PINCTRL_PIN(TB10X_GPIOS + 8, "GPIOI0"),
200 PINCTRL_PIN(TB10X_GPIOS + 9, "GPIOI1"),
201 PINCTRL_PIN(TB10X_GPIOS + 10, "GPIOI2"),
202 PINCTRL_PIN(TB10X_GPIOS + 11, "GPIOI3"),
203 PINCTRL_PIN(TB10X_GPIOS + 12, "GPIOI4"),
204 PINCTRL_PIN(TB10X_GPIOS + 13, "GPIOI5"),
205 PINCTRL_PIN(TB10X_GPIOS + 14, "GPIOI6"),
206 PINCTRL_PIN(TB10X_GPIOS + 15, "GPIOI7"),
207 PINCTRL_PIN(TB10X_GPIOS + 16, "GPIOI8"),
208 PINCTRL_PIN(TB10X_GPIOS + 17, "GPIOI9"),
209 PINCTRL_PIN(TB10X_GPIOS + 18, "GPIOI10"),
210 PINCTRL_PIN(TB10X_GPIOS + 19, "GPIOI11"),
211
212 PINCTRL_PIN(TB10X_GPIOS + 20, "GPION0"),
213 PINCTRL_PIN(TB10X_GPIOS + 21, "GPION1"),
214 PINCTRL_PIN(TB10X_GPIOS + 22, "GPION2"),
215 PINCTRL_PIN(TB10X_GPIOS + 23, "GPION3"),
216#define MAX_PIN (TB10X_GPIOS + 24)
217 PINCTRL_PIN(MAX_PIN, "GPION4"),
218};
219
220
221/* Port 1 */
222static const unsigned mis0_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1,
223 TB10X_PORT1 + 2, TB10X_PORT1 + 3};
224static const unsigned gpioa_pins[] = { TB10X_PORT1 + 4, TB10X_PORT1 + 5,
225 TB10X_PORT1 + 6};
226static const unsigned mis1_pins[] = { TB10X_PORT1 + 7, TB10X_PORT1 + 8,
227 TB10X_PORT1 + 9, TB10X_PORT1 + 10};
228static const unsigned mip1_pins[] = { TB10X_PORT1 + 0, TB10X_PORT1 + 1,
229 TB10X_PORT1 + 2, TB10X_PORT1 + 3,
230 TB10X_PORT1 + 4, TB10X_PORT1 + 5,
231 TB10X_PORT1 + 6, TB10X_PORT1 + 7,
232 TB10X_PORT1 + 8, TB10X_PORT1 + 9,
233 TB10X_PORT1 + 10};
234
235/* Port 2 */
236static const unsigned mis2_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1,
237 TB10X_PORT2 + 2, TB10X_PORT2 + 3};
238static const unsigned gpioc_pins[] = { TB10X_PORT2 + 4, TB10X_PORT2 + 5,
239 TB10X_PORT2 + 6};
240static const unsigned mis3_pins[] = { TB10X_PORT2 + 7, TB10X_PORT2 + 8,
241 TB10X_PORT2 + 9, TB10X_PORT2 + 10};
242static const unsigned mip3_pins[] = { TB10X_PORT2 + 0, TB10X_PORT2 + 1,
243 TB10X_PORT2 + 2, TB10X_PORT2 + 3,
244 TB10X_PORT2 + 4, TB10X_PORT2 + 5,
245 TB10X_PORT2 + 6, TB10X_PORT2 + 7,
246 TB10X_PORT2 + 8, TB10X_PORT2 + 9,
247 TB10X_PORT2 + 10};
248
249/* Port 3 */
250static const unsigned mis4_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1,
251 TB10X_PORT3 + 2, TB10X_PORT3 + 3};
252static const unsigned gpioe_pins[] = { TB10X_PORT3 + 4, TB10X_PORT3 + 5,
253 TB10X_PORT3 + 6};
254static const unsigned mis5_pins[] = { TB10X_PORT3 + 7, TB10X_PORT3 + 8,
255 TB10X_PORT3 + 9, TB10X_PORT3 + 10};
256static const unsigned mip5_pins[] = { TB10X_PORT3 + 0, TB10X_PORT3 + 1,
257 TB10X_PORT3 + 2, TB10X_PORT3 + 3,
258 TB10X_PORT3 + 4, TB10X_PORT3 + 5,
259 TB10X_PORT3 + 6, TB10X_PORT3 + 7,
260 TB10X_PORT3 + 8, TB10X_PORT3 + 9,
261 TB10X_PORT3 + 10};
262
263/* Port 4 */
264static const unsigned mis6_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1,
265 TB10X_PORT4 + 2, TB10X_PORT4 + 3};
266static const unsigned gpiog_pins[] = { TB10X_PORT4 + 4, TB10X_PORT4 + 5,
267 TB10X_PORT4 + 6};
268static const unsigned mis7_pins[] = { TB10X_PORT4 + 7, TB10X_PORT4 + 8,
269 TB10X_PORT4 + 9, TB10X_PORT4 + 10};
270static const unsigned mip7_pins[] = { TB10X_PORT4 + 0, TB10X_PORT4 + 1,
271 TB10X_PORT4 + 2, TB10X_PORT4 + 3,
272 TB10X_PORT4 + 4, TB10X_PORT4 + 5,
273 TB10X_PORT4 + 6, TB10X_PORT4 + 7,
274 TB10X_PORT4 + 8, TB10X_PORT4 + 9,
275 TB10X_PORT4 + 10};
276
277/* Port 6 */
278static const unsigned mop_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1,
279 TB10X_PORT6 + 2, TB10X_PORT6 + 3,
280 TB10X_PORT6 + 4, TB10X_PORT6 + 5,
281 TB10X_PORT6 + 6, TB10X_PORT6 + 7,
282 TB10X_PORT6 + 8, TB10X_PORT6 + 9};
283static const unsigned mos0_pins[] = { TB10X_PORT6 + 0, TB10X_PORT6 + 1,
284 TB10X_PORT6 + 2};
285static const unsigned mos1_pins[] = { TB10X_PORT6 + 3, TB10X_PORT6 + 4,
286 TB10X_PORT6 + 5};
287static const unsigned mos2_pins[] = { TB10X_PORT6 + 6, TB10X_PORT6 + 7,
288 TB10X_PORT6 + 8};
289static const unsigned mos3_pins[] = { TB10X_PORT6 + 9};
290
291/* Port 7 */
292static const unsigned uart0_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1,
293 TB10X_PORT7 + 2, TB10X_PORT7 + 3};
294static const unsigned uart1_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5,
295 TB10X_PORT7 + 6, TB10X_PORT7 + 7};
296static const unsigned gpiol_pins[] = { TB10X_PORT7 + 0, TB10X_PORT7 + 1,
297 TB10X_PORT7 + 2, TB10X_PORT7 + 3};
298static const unsigned gpiom_pins[] = { TB10X_PORT7 + 4, TB10X_PORT7 + 5,
299 TB10X_PORT7 + 6, TB10X_PORT7 + 7};
300
301/* Port 8 */
302static const unsigned spi3_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1,
303 TB10X_PORT8 + 2, TB10X_PORT8 + 3};
304static const unsigned jtag_pins[] = { TB10X_PORT8 + 0, TB10X_PORT8 + 1,
305 TB10X_PORT8 + 2, TB10X_PORT8 + 3};
306
307/* Port 9 */
308static const unsigned spi1_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1,
309 TB10X_PORT9 + 2, TB10X_PORT9 + 3,
310 TB10X_PORT9 + 4};
311static const unsigned gpion_pins[] = { TB10X_PORT9 + 0, TB10X_PORT9 + 1,
312 TB10X_PORT9 + 2, TB10X_PORT9 + 3,
313 TB10X_PORT9 + 4};
314
315/* Port 5 */
316static const unsigned gpioj_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
317 TB10X_PORT5 + 2, TB10X_PORT5 + 3,
318 TB10X_PORT5 + 4, TB10X_PORT5 + 5,
319 TB10X_PORT5 + 6, TB10X_PORT5 + 7,
320 TB10X_PORT5 + 8, TB10X_PORT5 + 9,
321 TB10X_PORT5 + 10, TB10X_PORT5 + 11,
322 TB10X_PORT5 + 12, TB10X_PORT5 + 13,
323 TB10X_PORT5 + 14, TB10X_PORT5 + 15,
324 TB10X_PORT5 + 16, TB10X_PORT5 + 17,
325 TB10X_PORT5 + 18, TB10X_PORT5 + 19,
326 TB10X_PORT5 + 20, TB10X_PORT5 + 21,
327 TB10X_PORT5 + 22, TB10X_PORT5 + 23,
328 TB10X_PORT5 + 24, TB10X_PORT5 + 25,
329 TB10X_PORT5 + 26, TB10X_PORT5 + 27,
330 TB10X_PORT5 + 28, TB10X_PORT5 + 29,
331 TB10X_PORT5 + 30, TB10X_PORT5 + 31};
332static const unsigned gpiok_pins[] = { TB10X_PORT5 + 32, TB10X_PORT5 + 33,
333 TB10X_PORT5 + 34, TB10X_PORT5 + 35,
334 TB10X_PORT5 + 36, TB10X_PORT5 + 37,
335 TB10X_PORT5 + 38, TB10X_PORT5 + 39,
336 TB10X_PORT5 + 40, TB10X_PORT5 + 41,
337 TB10X_PORT5 + 42, TB10X_PORT5 + 43,
338 TB10X_PORT5 + 44, TB10X_PORT5 + 45,
339 TB10X_PORT5 + 46, TB10X_PORT5 + 47,
340 TB10X_PORT5 + 48, TB10X_PORT5 + 49,
341 TB10X_PORT5 + 50, TB10X_PORT5 + 51,
342 TB10X_PORT5 + 52, TB10X_PORT5 + 53};
343static const unsigned ciplus_pins[] = { TB10X_PORT5 + 0, TB10X_PORT5 + 1,
344 TB10X_PORT5 + 2, TB10X_PORT5 + 3,
345 TB10X_PORT5 + 4, TB10X_PORT5 + 5,
346 TB10X_PORT5 + 6, TB10X_PORT5 + 7,
347 TB10X_PORT5 + 8, TB10X_PORT5 + 9,
348 TB10X_PORT5 + 10, TB10X_PORT5 + 11,
349 TB10X_PORT5 + 12, TB10X_PORT5 + 13,
350 TB10X_PORT5 + 14, TB10X_PORT5 + 15,
351 TB10X_PORT5 + 16, TB10X_PORT5 + 17,
352 TB10X_PORT5 + 18, TB10X_PORT5 + 19,
353 TB10X_PORT5 + 20, TB10X_PORT5 + 21,
354 TB10X_PORT5 + 22, TB10X_PORT5 + 23,
355 TB10X_PORT5 + 24, TB10X_PORT5 + 25,
356 TB10X_PORT5 + 26, TB10X_PORT5 + 27,
357 TB10X_PORT5 + 28, TB10X_PORT5 + 29,
358 TB10X_PORT5 + 30, TB10X_PORT5 + 31,
359 TB10X_PORT5 + 32, TB10X_PORT5 + 33,
360 TB10X_PORT5 + 34, TB10X_PORT5 + 35,
361 TB10X_PORT5 + 36, TB10X_PORT5 + 37,
362 TB10X_PORT5 + 38, TB10X_PORT5 + 39,
363 TB10X_PORT5 + 40, TB10X_PORT5 + 41,
364 TB10X_PORT5 + 42, TB10X_PORT5 + 43,
365 TB10X_PORT5 + 44, TB10X_PORT5 + 45,
366 TB10X_PORT5 + 46, TB10X_PORT5 + 47,
367 TB10X_PORT5 + 48, TB10X_PORT5 + 49,
368 TB10X_PORT5 + 50, TB10X_PORT5 + 51,
369 TB10X_PORT5 + 52, TB10X_PORT5 + 53};
370static const unsigned mcard_pins[] = { TB10X_PORT5 + 3, TB10X_PORT5 + 10,
371 TB10X_PORT5 + 11, TB10X_PORT5 + 12,
372 TB10X_PORT5 + 22, TB10X_PORT5 + 23,
373 TB10X_PORT5 + 33, TB10X_PORT5 + 35,
374 TB10X_PORT5 + 36, TB10X_PORT5 + 37,
375 TB10X_PORT5 + 38, TB10X_PORT5 + 39,
376 TB10X_PORT5 + 40, TB10X_PORT5 + 41,
377 TB10X_PORT5 + 42, TB10X_PORT5 + 43,
378 TB10X_PORT5 + 45, TB10X_PORT5 + 46,
379 TB10X_PORT5 + 47, TB10X_PORT5 + 48,
380 TB10X_PORT5 + 49, TB10X_PORT5 + 50,
381 TB10X_PORT5 + 51, TB10X_PORT5 + 52,
382 TB10X_PORT5 + 53};
383static const unsigned stc0_pins[] = { TB10X_PORT5 + 34, TB10X_PORT5 + 35,
384 TB10X_PORT5 + 36, TB10X_PORT5 + 37,
385 TB10X_PORT5 + 38, TB10X_PORT5 + 39,
386 TB10X_PORT5 + 40};
387static const unsigned stc1_pins[] = { TB10X_PORT5 + 25, TB10X_PORT5 + 26,
388 TB10X_PORT5 + 27, TB10X_PORT5 + 28,
389 TB10X_PORT5 + 29, TB10X_PORT5 + 30,
390 TB10X_PORT5 + 44};
391
392/* Unmuxed GPIOs */
393static const unsigned gpiob_pins[] = { TB10X_GPIOS + 0, TB10X_GPIOS + 1};
394static const unsigned gpiod_pins[] = { TB10X_GPIOS + 2, TB10X_GPIOS + 3};
395static const unsigned gpiof_pins[] = { TB10X_GPIOS + 4, TB10X_GPIOS + 5};
396static const unsigned gpioh_pins[] = { TB10X_GPIOS + 6, TB10X_GPIOS + 7};
397static const unsigned gpioi_pins[] = { TB10X_GPIOS + 8, TB10X_GPIOS + 9,
398 TB10X_GPIOS + 10, TB10X_GPIOS + 11,
399 TB10X_GPIOS + 12, TB10X_GPIOS + 13,
400 TB10X_GPIOS + 14, TB10X_GPIOS + 15,
401 TB10X_GPIOS + 16, TB10X_GPIOS + 17,
402 TB10X_GPIOS + 18, TB10X_GPIOS + 19};
403
404struct tb10x_pinfuncgrp {
405 const char *name;
406 const unsigned int *pins;
407 const unsigned int pincnt;
408 const int port;
409 const unsigned int mode;
410 const int isgpio;
411};
412#define DEFPINFUNCGRP(NAME, PORT, MODE, ISGPIO) { \
413 .name = __stringify(NAME), \
414 .pins = NAME##_pins, .pincnt = ARRAY_SIZE(NAME##_pins), \
415 .port = (PORT), .mode = (MODE), \
416 .isgpio = (ISGPIO), \
417 }
418static const struct tb10x_pinfuncgrp tb10x_pingroups[] = {
419 DEFPINFUNCGRP(mis0, 0, 0, 0),
420 DEFPINFUNCGRP(gpioa, 0, 0, 1),
421 DEFPINFUNCGRP(mis1, 0, 0, 0),
422 DEFPINFUNCGRP(mip1, 0, 1, 0),
423 DEFPINFUNCGRP(mis2, 1, 0, 0),
424 DEFPINFUNCGRP(gpioc, 1, 0, 1),
425 DEFPINFUNCGRP(mis3, 1, 0, 0),
426 DEFPINFUNCGRP(mip3, 1, 1, 0),
427 DEFPINFUNCGRP(mis4, 2, 0, 0),
428 DEFPINFUNCGRP(gpioe, 2, 0, 1),
429 DEFPINFUNCGRP(mis5, 2, 0, 0),
430 DEFPINFUNCGRP(mip5, 2, 1, 0),
431 DEFPINFUNCGRP(mis6, 3, 0, 0),
432 DEFPINFUNCGRP(gpiog, 3, 0, 1),
433 DEFPINFUNCGRP(mis7, 3, 0, 0),
434 DEFPINFUNCGRP(mip7, 3, 1, 0),
435 DEFPINFUNCGRP(gpioj, 4, 0, 1),
436 DEFPINFUNCGRP(gpiok, 4, 0, 1),
437 DEFPINFUNCGRP(ciplus, 4, 1, 0),
438 DEFPINFUNCGRP(mcard, 4, 2, 0),
439 DEFPINFUNCGRP(stc0, 4, 3, 0),
440 DEFPINFUNCGRP(stc1, 4, 3, 0),
441 DEFPINFUNCGRP(mop, 5, 0, 0),
442 DEFPINFUNCGRP(mos0, 5, 1, 0),
443 DEFPINFUNCGRP(mos1, 5, 1, 0),
444 DEFPINFUNCGRP(mos2, 5, 1, 0),
445 DEFPINFUNCGRP(mos3, 5, 1, 0),
446 DEFPINFUNCGRP(uart0, 6, 0, 0),
447 DEFPINFUNCGRP(uart1, 6, 0, 0),
448 DEFPINFUNCGRP(gpiol, 6, 1, 1),
449 DEFPINFUNCGRP(gpiom, 6, 1, 1),
450 DEFPINFUNCGRP(spi3, 7, 0, 0),
451 DEFPINFUNCGRP(jtag, 7, 1, 0),
452 DEFPINFUNCGRP(spi1, 8, 0, 0),
453 DEFPINFUNCGRP(gpion, 8, 1, 1),
454 DEFPINFUNCGRP(gpiob, -1, 0, 1),
455 DEFPINFUNCGRP(gpiod, -1, 0, 1),
456 DEFPINFUNCGRP(gpiof, -1, 0, 1),
457 DEFPINFUNCGRP(gpioh, -1, 0, 1),
458 DEFPINFUNCGRP(gpioi, -1, 0, 1),
459};
460#undef DEFPINFUNCGRP
461
462struct tb10x_of_pinfunc {
463 const char *name;
464 const char *group;
465};
466
467#define TB10X_PORTS (9)
468
469/**
470 * struct tb10x_port - state of an I/O port
471 * @mode: Node this port is currently in.
472 * @count: Number of enabled functions which require this port to be
473 * configured in @mode.
474 */
475struct tb10x_port {
476 unsigned int mode;
477 unsigned int count;
478};
479
480/**
481 * struct tb10x_pinctrl - TB10x pin controller internal state
482 * @pctl: pointer to the pinctrl_dev structure of this pin controller.
483 * @base: register set base address.
484 * @pingroups: pointer to an array of the pin groups this driver manages.
485 * @pinfuncgrpcnt: number of pingroups in @pingroups.
486 * @pinfuncs: pointer to an array of pin functions this driver manages.
487 * @pinfuncnt: number of pin functions in @pinfuncs.
488 * @mutex: mutex for exclusive access to a pin controller's state.
489 * @ports: current state of each port.
490 * @gpios: Indicates if a given pin is currently used as GPIO (1) or not (0).
491 */
492struct tb10x_pinctrl {
493 struct pinctrl_dev *pctl;
494 void *base;
495 const struct tb10x_pinfuncgrp *pingroups;
496 unsigned int pinfuncgrpcnt;
497 struct tb10x_of_pinfunc *pinfuncs;
498 unsigned int pinfuncnt;
499 struct mutex mutex;
500 struct tb10x_port ports[TB10X_PORTS];
501 DECLARE_BITMAP(gpios, MAX_PIN + 1);
502};
503
504static inline void tb10x_pinctrl_set_config(struct tb10x_pinctrl *state,
505 unsigned int port, unsigned int mode)
506{
507 u32 pcfg;
508
509 if (state->ports[port].count)
510 return;
511
512 state->ports[port].mode = mode;
513
514 pcfg = ioread32(state->base) & ~(PCFG_PORT_MASK(port));
515 pcfg |= (mode << (PCFG_PORT_BITWIDTH * port)) & PCFG_PORT_MASK(port);
516 iowrite32(pcfg, state->base);
517}
518
519static inline unsigned int tb10x_pinctrl_get_config(
520 struct tb10x_pinctrl *state,
521 unsigned int port)
522{
523 return (ioread32(state->base) & PCFG_PORT_MASK(port))
524 >> (PCFG_PORT_BITWIDTH * port);
525}
526
527static int tb10x_get_groups_count(struct pinctrl_dev *pctl)
528{
529 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
530 return state->pinfuncgrpcnt;
531}
532
533static const char *tb10x_get_group_name(struct pinctrl_dev *pctl, unsigned n)
534{
535 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
536 return state->pingroups[n].name;
537}
538
539static int tb10x_get_group_pins(struct pinctrl_dev *pctl, unsigned n,
540 unsigned const **pins,
541 unsigned * const num_pins)
542{
543 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
544
545 *pins = state->pingroups[n].pins;
546 *num_pins = state->pingroups[n].pincnt;
547
548 return 0;
549}
550
551static int tb10x_dt_node_to_map(struct pinctrl_dev *pctl,
552 struct device_node *np_config,
553 struct pinctrl_map **map, unsigned *num_maps)
554{
555 const char *string;
556 unsigned reserved_maps = 0;
557 int ret = 0;
558
559 if (of_property_read_string(np_config, "abilis,function", &string)) {
560 pr_err("%s: No abilis,function property in device tree.\n",
561 np_config->full_name);
562 return -EINVAL;
563 }
564
565 *map = NULL;
566 *num_maps = 0;
567
568 ret = pinctrl_utils_reserve_map(pctl, map, &reserved_maps,
569 num_maps, 1);
570 if (ret)
571 goto out;
572
573 ret = pinctrl_utils_add_map_mux(pctl, map, &reserved_maps,
574 num_maps, string, np_config->name);
575
576out:
577 return ret;
578}
579
580static struct pinctrl_ops tb10x_pinctrl_ops = {
581 .get_groups_count = tb10x_get_groups_count,
582 .get_group_name = tb10x_get_group_name,
583 .get_group_pins = tb10x_get_group_pins,
584 .dt_node_to_map = tb10x_dt_node_to_map,
585 .dt_free_map = pinctrl_utils_dt_free_map,
586};
587
588static int tb10x_get_functions_count(struct pinctrl_dev *pctl)
589{
590 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
591 return state->pinfuncnt;
592}
593
594static const char *tb10x_get_function_name(struct pinctrl_dev *pctl,
595 unsigned n)
596{
597 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
598 return state->pinfuncs[n].name;
599}
600
601static int tb10x_get_function_groups(struct pinctrl_dev *pctl,
602 unsigned n, const char * const **groups,
603 unsigned * const num_groups)
604{
605 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
606
607 *groups = &state->pinfuncs[n].group;
608 *num_groups = 1;
609
610 return 0;
611}
612
613static int tb10x_gpio_request_enable(struct pinctrl_dev *pctl,
614 struct pinctrl_gpio_range *range,
615 unsigned pin)
616{
617 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
618 int muxport = -1;
619 int muxmode = -1;
620 int i;
621
622 mutex_lock(&state->mutex);
623
624 /*
625 * Figure out to which port the requested GPIO belongs and how to
626 * configure that port.
627 * This loop also checks for pin conflicts between GPIOs and other
628 * functions.
629 */
630 for (i = 0; i < state->pinfuncgrpcnt; i++) {
631 const struct tb10x_pinfuncgrp *pfg = &state->pingroups[i];
632 unsigned int port = pfg->port;
633 unsigned int mode = pfg->mode;
634 int j;
635
636 /*
637 * Skip pin groups which are always mapped and don't need
638 * to be configured.
639 */
640 if (port < 0)
641 continue;
642
643 for (j = 0; j < pfg->pincnt; j++) {
644 if (pin == pfg->pins[j]) {
645 if (pfg->isgpio) {
646 /*
647 * Remember the GPIO-only setting of
648 * the port this pin belongs to.
649 */
650 muxport = port;
651 muxmode = mode;
652 } else if (state->ports[port].count
653 && (state->ports[port].mode == mode)) {
654 /*
655 * Error: The requested pin is already
656 * used for something else.
657 */
658 mutex_unlock(&state->mutex);
659 return -EBUSY;
660 }
661 break;
662 }
663 }
664 }
665
666 /*
667 * If we haven't returned an error at this point, the GPIO pin is not
668 * used by another function and the GPIO request can be granted:
669 * Register pin as being used as GPIO so we don't allocate it to
670 * another function later.
671 */
672 set_bit(pin, state->gpios);
673
674 /*
675 * Potential conflicts between GPIOs and pin functions were caught
676 * earlier in this function and tb10x_pinctrl_set_config will do the
677 * Right Thing, either configure the port in GPIO only mode or leave
678 * another mode compatible with this GPIO request untouched.
679 */
680 if (muxport >= 0)
681 tb10x_pinctrl_set_config(state, muxport, muxmode);
682
683 mutex_unlock(&state->mutex);
684
685 return 0;
686}
687
688static void tb10x_gpio_disable_free(struct pinctrl_dev *pctl,
689 struct pinctrl_gpio_range *range,
690 unsigned pin)
691{
692 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
693
694 mutex_lock(&state->mutex);
695
696 clear_bit(pin, state->gpios);
697
698 mutex_unlock(&state->mutex);
699}
700
701static int tb10x_pctl_enable(struct pinctrl_dev *pctl,
702 unsigned func_selector, unsigned group_selector)
703{
704 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
705 const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
706 int i;
707
708 if (grp->port < 0)
709 return 0;
710
711 mutex_lock(&state->mutex);
712
713 /*
714 * Check if the requested function is compatible with previously
715 * requested functions.
716 */
717 if (state->ports[grp->port].count
718 && (state->ports[grp->port].mode != grp->mode)) {
719 mutex_unlock(&state->mutex);
720 return -EBUSY;
721 }
722
723 /*
724 * Check if the requested function is compatible with previously
725 * requested GPIOs.
726 */
727 for (i = 0; i < grp->pincnt; i++)
728 if (test_bit(grp->pins[i], state->gpios)) {
729 mutex_unlock(&state->mutex);
730 return -EBUSY;
731 }
732
733 tb10x_pinctrl_set_config(state, grp->port, grp->mode);
734
735 state->ports[grp->port].count++;
736
737 mutex_unlock(&state->mutex);
738
739 return 0;
740}
741
742static void tb10x_pctl_disable(struct pinctrl_dev *pctl,
743 unsigned func_selector, unsigned group_selector)
744{
745 struct tb10x_pinctrl *state = pinctrl_dev_get_drvdata(pctl);
746 const struct tb10x_pinfuncgrp *grp = &state->pingroups[group_selector];
747
748 if (grp->port < 0)
749 return;
750
751 mutex_lock(&state->mutex);
752
753 state->ports[grp->port].count--;
754
755 mutex_unlock(&state->mutex);
756}
757
758static struct pinmux_ops tb10x_pinmux_ops = {
759 .get_functions_count = tb10x_get_functions_count,
760 .get_function_name = tb10x_get_function_name,
761 .get_function_groups = tb10x_get_function_groups,
762 .gpio_request_enable = tb10x_gpio_request_enable,
763 .gpio_disable_free = tb10x_gpio_disable_free,
764 .enable = tb10x_pctl_enable,
765 .disable = tb10x_pctl_disable,
766};
767
768static struct pinctrl_desc tb10x_pindesc = {
769 .name = "TB10x",
770 .pins = tb10x_pins,
771 .npins = ARRAY_SIZE(tb10x_pins),
772 .owner = THIS_MODULE,
773 .pctlops = &tb10x_pinctrl_ops,
774 .pmxops = &tb10x_pinmux_ops,
775};
776
777static int tb10x_pinctrl_probe(struct platform_device *pdev)
778{
779 int ret = -EINVAL;
780 struct resource *mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
781 struct device *dev = &pdev->dev;
782 struct device_node *of_node = dev->of_node;
783 struct device_node *child;
784 struct tb10x_pinctrl *state;
785 int i;
786
787 if (!of_node) {
788 dev_err(dev, "No device tree node found.\n");
789 return -EINVAL;
790 }
791
792 if (!mem) {
793 dev_err(dev, "No memory resource defined.\n");
794 return -EINVAL;
795 }
796
797 state = devm_kzalloc(dev, sizeof(struct tb10x_pinctrl) +
798 of_get_child_count(of_node)
799 * sizeof(struct tb10x_of_pinfunc),
800 GFP_KERNEL);
801 if (!state)
802 return -ENOMEM;
803
804 platform_set_drvdata(pdev, state);
805 state->pinfuncs = (struct tb10x_of_pinfunc *)(state + 1);
806 mutex_init(&state->mutex);
807
808 state->base = devm_ioremap_resource(dev, mem);
809 if (IS_ERR(state->base)) {
810 ret = PTR_ERR(state->base);
811 goto fail;
812 }
813
814 state->pingroups = tb10x_pingroups;
815 state->pinfuncgrpcnt = ARRAY_SIZE(tb10x_pingroups);
816
817 for (i = 0; i < TB10X_PORTS; i++)
818 state->ports[i].mode = tb10x_pinctrl_get_config(state, i);
819
820 for_each_child_of_node(of_node, child) {
821 const char *name;
822
823 if (!of_property_read_string(child, "abilis,function",
824 &name)) {
825 state->pinfuncs[state->pinfuncnt].name = child->name;
826 state->pinfuncs[state->pinfuncnt].group = name;
827 state->pinfuncnt++;
828 }
829 }
830
831 state->pctl = pinctrl_register(&tb10x_pindesc, dev, state);
832 if (!state->pctl) {
833 dev_err(dev, "could not register TB10x pin driver\n");
834 ret = -EINVAL;
835 goto fail;
836 }
837
838 return 0;
839
840fail:
841 mutex_destroy(&state->mutex);
842 return ret;
843}
844
845static int tb10x_pinctrl_remove(struct platform_device *pdev)
846{
847 struct tb10x_pinctrl *state = platform_get_drvdata(pdev);
848
849 pinctrl_unregister(state->pctl);
850 mutex_destroy(&state->mutex);
851
852 return 0;
853}
854
855
856static const struct of_device_id tb10x_pinctrl_dt_ids[] = {
857 { .compatible = "abilis,tb10x-iomux" },
858 { }
859};
860MODULE_DEVICE_TABLE(of, tb10x_pinctrl_dt_ids);
861
862static struct platform_driver tb10x_pinctrl_pdrv = {
863 .probe = tb10x_pinctrl_probe,
864 .remove = tb10x_pinctrl_remove,
865 .driver = {
866 .name = "tb10x_pinctrl",
867 .of_match_table = of_match_ptr(tb10x_pinctrl_dt_ids),
868 .owner = THIS_MODULE
869 }
870};
871
872module_platform_driver(tb10x_pinctrl_pdrv);
873
874MODULE_AUTHOR("Christian Ruppert <christian.ruppert@abilis.com>");
875MODULE_LICENSE("GPL");
diff --git a/drivers/pinctrl/pinctrl-vf610.c b/drivers/pinctrl/pinctrl-vf610.c
index 68a970b1dbcf..bddd913d28ba 100644
--- a/drivers/pinctrl/pinctrl-vf610.c
+++ b/drivers/pinctrl/pinctrl-vf610.c
@@ -316,7 +316,7 @@ static struct platform_driver vf610_pinctrl_driver = {
316 .driver = { 316 .driver = {
317 .name = "vf610-pinctrl", 317 .name = "vf610-pinctrl",
318 .owner = THIS_MODULE, 318 .owner = THIS_MODULE,
319 .of_match_table = of_match_ptr(vf610_pinctrl_of_match), 319 .of_match_table = vf610_pinctrl_of_match,
320 }, 320 },
321 .probe = vf610_pinctrl_probe, 321 .probe = vf610_pinctrl_probe,
322 .remove = imx_pinctrl_remove, 322 .remove = imx_pinctrl_remove,
diff --git a/drivers/pinctrl/pinmux.c b/drivers/pinctrl/pinmux.c
index 9d144a263dc2..9248ce4efed4 100644
--- a/drivers/pinctrl/pinmux.c
+++ b/drivers/pinctrl/pinmux.c
@@ -505,16 +505,14 @@ void pinmux_disable_setting(struct pinctrl_setting const *setting)
505 pin_free(pctldev, pins[i], NULL); 505 pin_free(pctldev, pins[i], NULL);
506 } else { 506 } else {
507 const char *gname; 507 const char *gname;
508 const char *pname;
509 508
510 pname = desc ? desc->name : "non-existing";
511 gname = pctlops->get_group_name(pctldev, 509 gname = pctlops->get_group_name(pctldev,
512 setting->data.mux.group); 510 setting->data.mux.group);
513 dev_warn(pctldev->dev, 511 dev_warn(pctldev->dev,
514 "not freeing pin %d (%s) as part of " 512 "not freeing pin %d (%s) as part of "
515 "deactivating group %s - it is already " 513 "deactivating group %s - it is already "
516 "used for some other setting", 514 "used for some other setting",
517 pins[i], pname, gname); 515 pins[i], desc->name, gname);
518 } 516 }
519 } 517 }
520 518
diff --git a/drivers/pinctrl/sh-pfc/Kconfig b/drivers/pinctrl/sh-pfc/Kconfig
index 636a882b406e..26187aa5cf5b 100644
--- a/drivers/pinctrl/sh-pfc/Kconfig
+++ b/drivers/pinctrl/sh-pfc/Kconfig
@@ -45,6 +45,11 @@ config PINCTRL_PFC_R8A7790
45 depends on ARCH_R8A7790 45 depends on ARCH_R8A7790
46 select PINCTRL_SH_PFC 46 select PINCTRL_SH_PFC
47 47
48config PINCTRL_PFC_R8A7791
49 def_bool y
50 depends on ARCH_R8A7791
51 select PINCTRL_SH_PFC
52
48config PINCTRL_PFC_SH7203 53config PINCTRL_PFC_SH7203
49 def_bool y 54 def_bool y
50 depends on CPU_SUBTYPE_SH7203 55 depends on CPU_SUBTYPE_SH7203
diff --git a/drivers/pinctrl/sh-pfc/Makefile b/drivers/pinctrl/sh-pfc/Makefile
index 5e0c222c12d7..ad8f4cf9faaa 100644
--- a/drivers/pinctrl/sh-pfc/Makefile
+++ b/drivers/pinctrl/sh-pfc/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_PINCTRL_PFC_R8A7740) += pfc-r8a7740.o
8obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o 8obj-$(CONFIG_PINCTRL_PFC_R8A7778) += pfc-r8a7778.o
9obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o 9obj-$(CONFIG_PINCTRL_PFC_R8A7779) += pfc-r8a7779.o
10obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o 10obj-$(CONFIG_PINCTRL_PFC_R8A7790) += pfc-r8a7790.o
11obj-$(CONFIG_PINCTRL_PFC_R8A7791) += pfc-r8a7791.o
11obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o 12obj-$(CONFIG_PINCTRL_PFC_SH7203) += pfc-sh7203.o
12obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o 13obj-$(CONFIG_PINCTRL_PFC_SH7264) += pfc-sh7264.o
13obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o 14obj-$(CONFIG_PINCTRL_PFC_SH7269) += pfc-sh7269.o
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index 738f14f65cff..d77ece5217f0 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -431,6 +431,12 @@ static const struct of_device_id sh_pfc_of_table[] = {
431 .data = &r8a7790_pinmux_info, 431 .data = &r8a7790_pinmux_info,
432 }, 432 },
433#endif 433#endif
434#ifdef CONFIG_PINCTRL_PFC_R8A7791
435 {
436 .compatible = "renesas,pfc-r8a7791",
437 .data = &r8a7791_pinmux_info,
438 },
439#endif
434#ifdef CONFIG_PINCTRL_PFC_SH7372 440#ifdef CONFIG_PINCTRL_PFC_SH7372
435 { 441 {
436 .compatible = "renesas,pfc-sh7372", 442 .compatible = "renesas,pfc-sh7372",
@@ -558,6 +564,9 @@ static const struct platform_device_id sh_pfc_id_table[] = {
558#ifdef CONFIG_PINCTRL_PFC_R8A7790 564#ifdef CONFIG_PINCTRL_PFC_R8A7790
559 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info }, 565 { "pfc-r8a7790", (kernel_ulong_t)&r8a7790_pinmux_info },
560#endif 566#endif
567#ifdef CONFIG_PINCTRL_PFC_R8A7791
568 { "pfc-r8a7791", (kernel_ulong_t)&r8a7791_pinmux_info },
569#endif
561#ifdef CONFIG_PINCTRL_PFC_SH7203 570#ifdef CONFIG_PINCTRL_PFC_SH7203
562 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info }, 571 { "pfc-sh7203", (kernel_ulong_t)&sh7203_pinmux_info },
563#endif 572#endif
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index a1b23762ac90..11ea87268658 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -69,6 +69,7 @@ extern const struct sh_pfc_soc_info r8a7740_pinmux_info;
69extern const struct sh_pfc_soc_info r8a7778_pinmux_info; 69extern const struct sh_pfc_soc_info r8a7778_pinmux_info;
70extern const struct sh_pfc_soc_info r8a7779_pinmux_info; 70extern const struct sh_pfc_soc_info r8a7779_pinmux_info;
71extern const struct sh_pfc_soc_info r8a7790_pinmux_info; 71extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
72extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
72extern const struct sh_pfc_soc_info sh7203_pinmux_info; 73extern const struct sh_pfc_soc_info sh7203_pinmux_info;
73extern const struct sh_pfc_soc_info sh7264_pinmux_info; 74extern const struct sh_pfc_soc_info sh7264_pinmux_info;
74extern const struct sh_pfc_soc_info sh7269_pinmux_info; 75extern const struct sh_pfc_soc_info sh7269_pinmux_info;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 428d2a6857ef..8b1881c20598 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1288,6 +1288,49 @@ static struct sh_pfc_pin pinmux_pins[] = {
1288 arg5##_MARK, arg6##_MARK, \ 1288 arg5##_MARK, arg6##_MARK, \
1289 arg7##_MARK, arg8##_MARK, } 1289 arg7##_MARK, arg8##_MARK, }
1290 1290
1291/* - AUDIO macro -------------------------------------------------------------*/
1292#define AUDIO_PFC_PIN(name, pin) SH_PFC_PINS(name, pin)
1293#define AUDIO_PFC_DAT(name, pin) SH_PFC_MUX1(name, pin)
1294
1295/* - AUDIO clock -------------------------------------------------------------*/
1296AUDIO_PFC_PIN(audio_clk_a, RCAR_GP_PIN(2, 22));
1297AUDIO_PFC_DAT(audio_clk_a, AUDIO_CLKA);
1298AUDIO_PFC_PIN(audio_clk_b, RCAR_GP_PIN(2, 23));
1299AUDIO_PFC_DAT(audio_clk_b, AUDIO_CLKB);
1300AUDIO_PFC_PIN(audio_clk_c, RCAR_GP_PIN(2, 7));
1301AUDIO_PFC_DAT(audio_clk_c, AUDIO_CLKC);
1302AUDIO_PFC_PIN(audio_clkout_a, RCAR_GP_PIN(2, 16));
1303AUDIO_PFC_DAT(audio_clkout_a, AUDIO_CLKOUT_A);
1304AUDIO_PFC_PIN(audio_clkout_b, RCAR_GP_PIN(1, 16));
1305AUDIO_PFC_DAT(audio_clkout_b, AUDIO_CLKOUT_B);
1306
1307/* - CAN macro --------_----------------------------------------------------- */
1308#define CAN_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1309#define CAN_PFC_DATA(name, tx, rx) SH_PFC_MUX2(name, tx, rx)
1310#define CAN_PFC_CLK(name, clk) SH_PFC_MUX1(name, clk)
1311
1312/* - CAN0 ------------------------------------------------------------------- */
1313CAN_PFC_PINS(can0_data_a, RCAR_GP_PIN(1, 30), RCAR_GP_PIN(1, 31));
1314CAN_PFC_DATA(can0_data_a, CAN0_TX_A, CAN0_RX_A);
1315CAN_PFC_PINS(can0_data_b, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(2, 27));
1316CAN_PFC_DATA(can0_data_b, CAN0_TX_B, CAN0_RX_B);
1317
1318/* - CAN1 ------------------------------------------------------------------- */
1319CAN_PFC_PINS(can1_data_a, RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 19));
1320CAN_PFC_DATA(can1_data_a, CAN1_TX_A, CAN1_RX_A);
1321CAN_PFC_PINS(can1_data_b, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
1322CAN_PFC_DATA(can1_data_b, CAN1_TX_B, CAN1_RX_B);
1323
1324/* - CAN_CLK --------------------------------------------------------------- */
1325CAN_PFC_PINS(can_clk_a, RCAR_GP_PIN(3, 24));
1326CAN_PFC_CLK(can_clk_a, CAN_CLK_A);
1327CAN_PFC_PINS(can_clk_b, RCAR_GP_PIN(1, 16));
1328CAN_PFC_CLK(can_clk_b, CAN_CLK_B);
1329CAN_PFC_PINS(can_clk_c, RCAR_GP_PIN(4, 24));
1330CAN_PFC_CLK(can_clk_c, CAN_CLK_C);
1331CAN_PFC_PINS(can_clk_d, RCAR_GP_PIN(2, 25));
1332CAN_PFC_CLK(can_clk_d, CAN_CLK_D);
1333
1291/* - Ether ------------------------------------------------------------------ */ 1334/* - Ether ------------------------------------------------------------------ */
1292SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11), 1335SH_PFC_PINS(ether_rmii, RCAR_GP_PIN(4, 10), RCAR_GP_PIN(4, 11),
1293 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9), 1336 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 9),
@@ -1577,6 +1620,59 @@ SDHI_PFC_WPPN(sdhi2_wp_a, SD2_WP_A);
1577SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28)); 1620SDHI_PFC_PINS(sdhi2_wp_b, RCAR_GP_PIN(3, 28));
1578SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B); 1621SDHI_PFC_WPPN(sdhi2_wp_b, SD2_WP_B);
1579 1622
1623/* - SSI macro -------------------------------------------------------------- */
1624#define SSI_PFC_PINS(name, args...) SH_PFC_PINS(name, args)
1625#define SSI_PFC_CTRL(name, sck, ws) SH_PFC_MUX2(name, sck, ws)
1626#define SSI_PFC_DATA(name, d) SH_PFC_MUX1(name, d)
1627
1628/* - SSI 0/1/2 -------------------------------------------------------------- */
1629SSI_PFC_PINS(ssi012_ctrl, RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7));
1630SSI_PFC_CTRL(ssi012_ctrl, SSI_SCK012, SSI_WS012);
1631SSI_PFC_PINS(ssi0_data, RCAR_GP_PIN(3, 10));
1632SSI_PFC_DATA(ssi0_data, SSI_SDATA0);
1633SSI_PFC_PINS(ssi1_a_ctrl, RCAR_GP_PIN(2, 20), RCAR_GP_PIN(2, 21));
1634SSI_PFC_CTRL(ssi1_a_ctrl, SSI_SCK1_A, SSI_WS1_A);
1635SSI_PFC_PINS(ssi1_b_ctrl, PIN_NUMBER(3, 20), RCAR_GP_PIN(1, 3));
1636SSI_PFC_CTRL(ssi1_b_ctrl, SSI_SCK1_B, SSI_WS1_B);
1637SSI_PFC_PINS(ssi1_data, RCAR_GP_PIN(3, 9));
1638SSI_PFC_DATA(ssi1_data, SSI_SDATA1);
1639SSI_PFC_PINS(ssi2_a_ctrl, RCAR_GP_PIN(2, 26), RCAR_GP_PIN(3, 4));
1640SSI_PFC_CTRL(ssi2_a_ctrl, SSI_SCK2_A, SSI_WS2_A);
1641SSI_PFC_PINS(ssi2_b_ctrl, RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 17));
1642SSI_PFC_CTRL(ssi2_b_ctrl, SSI_SCK2_B, SSI_WS2_B);
1643SSI_PFC_PINS(ssi2_data, RCAR_GP_PIN(3, 8));
1644SSI_PFC_DATA(ssi2_data, SSI_SDATA2);
1645
1646/* - SSI 3/4 ---------------------------------------------------------------- */
1647SSI_PFC_PINS(ssi34_ctrl, RCAR_GP_PIN(3, 2), RCAR_GP_PIN(3, 3));
1648SSI_PFC_CTRL(ssi34_ctrl, SSI_SCK34, SSI_WS34);
1649SSI_PFC_PINS(ssi3_data, RCAR_GP_PIN(3, 5));
1650SSI_PFC_DATA(ssi3_data, SSI_SDATA3);
1651SSI_PFC_PINS(ssi4_ctrl, RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23));
1652SSI_PFC_CTRL(ssi4_ctrl, SSI_SCK4, SSI_WS4);
1653SSI_PFC_PINS(ssi4_data, RCAR_GP_PIN(3, 4));
1654SSI_PFC_DATA(ssi4_data, SSI_SDATA4);
1655
1656/* - SSI 5 ------------------------------------------------------------------ */
1657SSI_PFC_PINS(ssi5_ctrl, RCAR_GP_PIN(2, 31), RCAR_GP_PIN(3, 0));
1658SSI_PFC_CTRL(ssi5_ctrl, SSI_SCK5, SSI_WS5);
1659SSI_PFC_PINS(ssi5_data, RCAR_GP_PIN(3, 1));
1660SSI_PFC_DATA(ssi5_data, SSI_SDATA5);
1661
1662/* - SSI 6 ------------------------------------------------------------------ */
1663SSI_PFC_PINS(ssi6_ctrl, RCAR_GP_PIN(2, 28), RCAR_GP_PIN(2, 29));
1664SSI_PFC_CTRL(ssi6_ctrl, SSI_SCK6, SSI_WS6);
1665SSI_PFC_PINS(ssi6_data, RCAR_GP_PIN(2, 30));
1666SSI_PFC_DATA(ssi6_data, SSI_SDATA6);
1667
1668/* - SSI 7/8 --------------------------------------------------------------- */
1669SSI_PFC_PINS(ssi78_ctrl, RCAR_GP_PIN(2, 24), RCAR_GP_PIN(2, 25));
1670SSI_PFC_CTRL(ssi78_ctrl, SSI_SCK78, SSI_WS78);
1671SSI_PFC_PINS(ssi7_data, RCAR_GP_PIN(2, 27));
1672SSI_PFC_DATA(ssi7_data, SSI_SDATA7);
1673SSI_PFC_PINS(ssi8_data, RCAR_GP_PIN(2, 26));
1674SSI_PFC_DATA(ssi8_data, SSI_SDATA8);
1675
1580/* - USB0 ------------------------------------------------------------------- */ 1676/* - USB0 ------------------------------------------------------------------- */
1581SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1)); 1677SH_PFC_PINS(usb0, RCAR_GP_PIN(0, 1));
1582SH_PFC_MUX1(usb0, PENC0); 1678SH_PFC_MUX1(usb0, PENC0);
@@ -1624,6 +1720,19 @@ VIN_PFC_PINS(vin1_sync, RCAR_GP_PIN(3, 21), RCAR_GP_PIN(3, 22));
1624VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC); 1720VIN_PFC_SYNC(vin1_sync, VI1_HSYNC, VI1_VSYNC);
1625 1721
1626static const struct sh_pfc_pin_group pinmux_groups[] = { 1722static const struct sh_pfc_pin_group pinmux_groups[] = {
1723 SH_PFC_PIN_GROUP(audio_clk_a),
1724 SH_PFC_PIN_GROUP(audio_clk_b),
1725 SH_PFC_PIN_GROUP(audio_clk_c),
1726 SH_PFC_PIN_GROUP(audio_clkout_a),
1727 SH_PFC_PIN_GROUP(audio_clkout_b),
1728 SH_PFC_PIN_GROUP(can0_data_a),
1729 SH_PFC_PIN_GROUP(can0_data_b),
1730 SH_PFC_PIN_GROUP(can1_data_a),
1731 SH_PFC_PIN_GROUP(can1_data_b),
1732 SH_PFC_PIN_GROUP(can_clk_a),
1733 SH_PFC_PIN_GROUP(can_clk_b),
1734 SH_PFC_PIN_GROUP(can_clk_c),
1735 SH_PFC_PIN_GROUP(can_clk_d),
1627 SH_PFC_PIN_GROUP(ether_rmii), 1736 SH_PFC_PIN_GROUP(ether_rmii),
1628 SH_PFC_PIN_GROUP(ether_link), 1737 SH_PFC_PIN_GROUP(ether_link),
1629 SH_PFC_PIN_GROUP(ether_magic), 1738 SH_PFC_PIN_GROUP(ether_magic),
@@ -1713,6 +1822,25 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1713 SH_PFC_PIN_GROUP(sdhi2_data4_b), 1822 SH_PFC_PIN_GROUP(sdhi2_data4_b),
1714 SH_PFC_PIN_GROUP(sdhi2_wp_a), 1823 SH_PFC_PIN_GROUP(sdhi2_wp_a),
1715 SH_PFC_PIN_GROUP(sdhi2_wp_b), 1824 SH_PFC_PIN_GROUP(sdhi2_wp_b),
1825 SH_PFC_PIN_GROUP(ssi012_ctrl),
1826 SH_PFC_PIN_GROUP(ssi0_data),
1827 SH_PFC_PIN_GROUP(ssi1_a_ctrl),
1828 SH_PFC_PIN_GROUP(ssi1_b_ctrl),
1829 SH_PFC_PIN_GROUP(ssi1_data),
1830 SH_PFC_PIN_GROUP(ssi2_a_ctrl),
1831 SH_PFC_PIN_GROUP(ssi2_b_ctrl),
1832 SH_PFC_PIN_GROUP(ssi2_data),
1833 SH_PFC_PIN_GROUP(ssi34_ctrl),
1834 SH_PFC_PIN_GROUP(ssi3_data),
1835 SH_PFC_PIN_GROUP(ssi4_ctrl),
1836 SH_PFC_PIN_GROUP(ssi4_data),
1837 SH_PFC_PIN_GROUP(ssi5_ctrl),
1838 SH_PFC_PIN_GROUP(ssi5_data),
1839 SH_PFC_PIN_GROUP(ssi6_ctrl),
1840 SH_PFC_PIN_GROUP(ssi6_data),
1841 SH_PFC_PIN_GROUP(ssi78_ctrl),
1842 SH_PFC_PIN_GROUP(ssi7_data),
1843 SH_PFC_PIN_GROUP(ssi8_data),
1716 SH_PFC_PIN_GROUP(usb0), 1844 SH_PFC_PIN_GROUP(usb0),
1717 SH_PFC_PIN_GROUP(usb0_ovc), 1845 SH_PFC_PIN_GROUP(usb0_ovc),
1718 SH_PFC_PIN_GROUP(usb1), 1846 SH_PFC_PIN_GROUP(usb1),
@@ -1725,6 +1853,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
1725 SH_PFC_PIN_GROUP(vin1_sync), 1853 SH_PFC_PIN_GROUP(vin1_sync),
1726}; 1854};
1727 1855
1856static const char * const audio_clk_groups[] = {
1857 "audio_clk_a",
1858 "audio_clk_b",
1859 "audio_clk_c",
1860 "audio_clkout_a",
1861 "audio_clkout_b",
1862};
1863
1864static const char * const can0_groups[] = {
1865 "can0_data_a",
1866 "can0_data_b",
1867 "can_clk_a",
1868 "can_clk_b",
1869 "can_clk_c",
1870 "can_clk_d",
1871};
1872
1873static const char * const can1_groups[] = {
1874 "can1_data_a",
1875 "can1_data_b",
1876 "can_clk_a",
1877 "can_clk_b",
1878 "can_clk_c",
1879 "can_clk_d",
1880};
1881
1728static const char * const ether_groups[] = { 1882static const char * const ether_groups[] = {
1729 "ether_rmii", 1883 "ether_rmii",
1730 "ether_link", 1884 "ether_link",
@@ -1875,6 +2029,28 @@ static const char * const sdhi2_groups[] = {
1875 "sdhi2_wp_b", 2029 "sdhi2_wp_b",
1876}; 2030};
1877 2031
2032static const char * const ssi_groups[] = {
2033 "ssi012_ctrl",
2034 "ssi0_data",
2035 "ssi1_a_ctrl",
2036 "ssi1_b_ctrl",
2037 "ssi1_data",
2038 "ssi2_a_ctrl",
2039 "ssi2_b_ctrl",
2040 "ssi2_data",
2041 "ssi34_ctrl",
2042 "ssi3_data",
2043 "ssi4_ctrl",
2044 "ssi4_data",
2045 "ssi5_ctrl",
2046 "ssi5_data",
2047 "ssi6_ctrl",
2048 "ssi6_data",
2049 "ssi78_ctrl",
2050 "ssi7_data",
2051 "ssi8_data",
2052};
2053
1878static const char * const usb0_groups[] = { 2054static const char * const usb0_groups[] = {
1879 "usb0", 2055 "usb0",
1880 "usb0_ovc", 2056 "usb0_ovc",
@@ -1898,6 +2074,9 @@ static const char * const vin1_groups[] = {
1898}; 2074};
1899 2075
1900static const struct sh_pfc_function pinmux_functions[] = { 2076static const struct sh_pfc_function pinmux_functions[] = {
2077 SH_PFC_FUNCTION(audio_clk),
2078 SH_PFC_FUNCTION(can0),
2079 SH_PFC_FUNCTION(can1),
1901 SH_PFC_FUNCTION(ether), 2080 SH_PFC_FUNCTION(ether),
1902 SH_PFC_FUNCTION(hscif0), 2081 SH_PFC_FUNCTION(hscif0),
1903 SH_PFC_FUNCTION(hscif1), 2082 SH_PFC_FUNCTION(hscif1),
@@ -1918,6 +2097,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
1918 SH_PFC_FUNCTION(sdhi0), 2097 SH_PFC_FUNCTION(sdhi0),
1919 SH_PFC_FUNCTION(sdhi1), 2098 SH_PFC_FUNCTION(sdhi1),
1920 SH_PFC_FUNCTION(sdhi2), 2099 SH_PFC_FUNCTION(sdhi2),
2100 SH_PFC_FUNCTION(ssi),
1921 SH_PFC_FUNCTION(usb0), 2101 SH_PFC_FUNCTION(usb0),
1922 SH_PFC_FUNCTION(usb1), 2102 SH_PFC_FUNCTION(usb1),
1923 SH_PFC_FUNCTION(vin0), 2103 SH_PFC_FUNCTION(vin0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 64fcc00693b5..72786fc93958 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -781,6 +781,8 @@ enum {
781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK, 781 ADICS_SAMP_MARK, DU2_CDE_MARK, QPOLB_MARK, SCIFA2_RXD_B_MARK,
782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK, 782 USB1_PWEN_MARK, AUDIO_CLKOUT_D_MARK, USB1_OVC_MARK,
783 TCLK1_B_MARK, 783 TCLK1_B_MARK,
784
785 I2C3_SCL_MARK, I2C3_SDA_MARK,
784 PINMUX_MARK_END, 786 PINMUX_MARK_END,
785}; 787};
786 788
@@ -1719,10 +1721,22 @@ static const u16 pinmux_data[] = {
1719 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D), 1721 PINMUX_IPSR_DATA(IP16_6, AUDIO_CLKOUT_D),
1720 PINMUX_IPSR_DATA(IP16_7, USB1_OVC), 1722 PINMUX_IPSR_DATA(IP16_7, USB1_OVC),
1721 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1), 1723 PINMUX_IPSR_MODSEL_DATA(IP16_7, TCLK1_B, SEL_TMU1_1),
1724
1725 PINMUX_DATA(I2C3_SCL_MARK, FN_SEL_IICDVFS_1),
1726 PINMUX_DATA(I2C3_SDA_MARK, FN_SEL_IICDVFS_1),
1722}; 1727};
1723 1728
1729/* R8A7790 has 6 banks with 32 GPIOs in each = 192 GPIOs */
1730#define ROW_GROUP_A(r) ('Z' - 'A' + 1 + (r))
1731#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1732#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1733
1724static struct sh_pfc_pin pinmux_pins[] = { 1734static struct sh_pfc_pin pinmux_pins[] = {
1725 PINMUX_GPIO_GP_ALL(), 1735 PINMUX_GPIO_GP_ALL(),
1736
1737 /* Pins not associated with a GPIO port */
1738 SH_PFC_PIN_NAMED(ROW_GROUP_A('J'), 15, AJ15),
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1726}; 1740};
1727 1741
1728/* - DU RGB ----------------------------------------------------------------- */ 1742/* - DU RGB ----------------------------------------------------------------- */
@@ -1990,6 +2004,72 @@ static const unsigned int hscif1_ctrl_b_pins[] = {
1990static const unsigned int hscif1_ctrl_b_mux[] = { 2004static const unsigned int hscif1_ctrl_b_mux[] = {
1991 HRTS1_N_B_MARK, HCTS1_N_B_MARK, 2005 HRTS1_N_B_MARK, HCTS1_N_B_MARK,
1992}; 2006};
2007/* - I2C1 ------------------------------------------------------------------- */
2008static const unsigned int i2c1_pins[] = {
2009 /* SCL, SDA */
2010 RCAR_GP_PIN(1, 16), RCAR_GP_PIN(1, 17),
2011};
2012static const unsigned int i2c1_mux[] = {
2013 I2C1_SCL_MARK, I2C1_SDA_MARK,
2014};
2015static const unsigned int i2c1_b_pins[] = {
2016 /* SCL, SDA */
2017 RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 7),
2018};
2019static const unsigned int i2c1_b_mux[] = {
2020 I2C1_SCL_B_MARK, I2C1_SDA_B_MARK,
2021};
2022static const unsigned int i2c1_c_pins[] = {
2023 /* SCL, SDA */
2024 RCAR_GP_PIN(4, 30), RCAR_GP_PIN(4, 27),
2025};
2026static const unsigned int i2c1_c_mux[] = {
2027 I2C1_SCL_C_MARK, I2C1_SDA_C_MARK,
2028};
2029/* - I2C2 ------------------------------------------------------------------- */
2030static const unsigned int i2c2_pins[] = {
2031 /* SCL, SDA */
2032 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2033};
2034static const unsigned int i2c2_mux[] = {
2035 I2C2_SCL_MARK, I2C2_SDA_MARK,
2036};
2037static const unsigned int i2c2_b_pins[] = {
2038 /* SCL, SDA */
2039 RCAR_GP_PIN(4, 0), RCAR_GP_PIN(4, 1),
2040};
2041static const unsigned int i2c2_b_mux[] = {
2042 I2C2_SCL_B_MARK, I2C2_SDA_B_MARK,
2043};
2044static const unsigned int i2c2_c_pins[] = {
2045 /* SCL, SDA */
2046 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
2047};
2048static const unsigned int i2c2_c_mux[] = {
2049 I2C2_SCL_C_MARK, I2C2_SDA_C_MARK,
2050};
2051static const unsigned int i2c2_d_pins[] = {
2052 /* SCL, SDA */
2053 RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 15),
2054};
2055static const unsigned int i2c2_d_mux[] = {
2056 I2C2_SCL_D_MARK, I2C2_SDA_D_MARK,
2057};
2058static const unsigned int i2c2_e_pins[] = {
2059 /* SCL, SDA */
2060 RCAR_GP_PIN(2, 18), RCAR_GP_PIN(2, 19),
2061};
2062static const unsigned int i2c2_e_mux[] = {
2063 I2C2_SCL_E_MARK, I2C2_SDA_E_MARK,
2064};
2065/* - I2C3 ------------------------------------------------------------------- */
2066static const unsigned int i2c3_pins[] = {
2067 /* SCL, SDA */
2068 PIN_A_NUMBER('J', 15), PIN_A_NUMBER('H', 15),
2069};
2070static const unsigned int i2c3_mux[] = {
2071 I2C3_SCL_MARK, I2C3_SDA_MARK,
2072};
1993/* - INTC ------------------------------------------------------------------- */ 2073/* - INTC ------------------------------------------------------------------- */
1994static const unsigned int intc_irq0_pins[] = { 2074static const unsigned int intc_irq0_pins[] = {
1995 /* IRQ */ 2075 /* IRQ */
@@ -3047,6 +3127,15 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3047 SH_PFC_PIN_GROUP(hscif1_data_b), 3127 SH_PFC_PIN_GROUP(hscif1_data_b),
3048 SH_PFC_PIN_GROUP(hscif1_clk_b), 3128 SH_PFC_PIN_GROUP(hscif1_clk_b),
3049 SH_PFC_PIN_GROUP(hscif1_ctrl_b), 3129 SH_PFC_PIN_GROUP(hscif1_ctrl_b),
3130 SH_PFC_PIN_GROUP(i2c1),
3131 SH_PFC_PIN_GROUP(i2c1_b),
3132 SH_PFC_PIN_GROUP(i2c1_c),
3133 SH_PFC_PIN_GROUP(i2c2),
3134 SH_PFC_PIN_GROUP(i2c2_b),
3135 SH_PFC_PIN_GROUP(i2c2_c),
3136 SH_PFC_PIN_GROUP(i2c2_d),
3137 SH_PFC_PIN_GROUP(i2c2_e),
3138 SH_PFC_PIN_GROUP(i2c3),
3050 SH_PFC_PIN_GROUP(intc_irq0), 3139 SH_PFC_PIN_GROUP(intc_irq0),
3051 SH_PFC_PIN_GROUP(intc_irq1), 3140 SH_PFC_PIN_GROUP(intc_irq1),
3052 SH_PFC_PIN_GROUP(intc_irq2), 3141 SH_PFC_PIN_GROUP(intc_irq2),
@@ -3243,6 +3332,24 @@ static const char * const hscif1_groups[] = {
3243 "hscif1_ctrl_b", 3332 "hscif1_ctrl_b",
3244}; 3333};
3245 3334
3335static const char * const i2c1_groups[] = {
3336 "i2c1",
3337 "i2c1_b",
3338 "i2c1_c",
3339};
3340
3341static const char * const i2c2_groups[] = {
3342 "i2c2",
3343 "i2c2_b",
3344 "i2c2_c",
3345 "i2c2_d",
3346 "i2c2_e",
3347};
3348
3349static const char * const i2c3_groups[] = {
3350 "i2c3",
3351};
3352
3246static const char * const intc_groups[] = { 3353static const char * const intc_groups[] = {
3247 "intc_irq0", 3354 "intc_irq0",
3248 "intc_irq1", 3355 "intc_irq1",
@@ -3469,6 +3576,9 @@ static const struct sh_pfc_function pinmux_functions[] = {
3469 SH_PFC_FUNCTION(eth), 3576 SH_PFC_FUNCTION(eth),
3470 SH_PFC_FUNCTION(hscif0), 3577 SH_PFC_FUNCTION(hscif0),
3471 SH_PFC_FUNCTION(hscif1), 3578 SH_PFC_FUNCTION(hscif1),
3579 SH_PFC_FUNCTION(i2c1),
3580 SH_PFC_FUNCTION(i2c2),
3581 SH_PFC_FUNCTION(i2c3),
3472 SH_PFC_FUNCTION(intc), 3582 SH_PFC_FUNCTION(intc),
3473 SH_PFC_FUNCTION(mmc0), 3583 SH_PFC_FUNCTION(mmc0),
3474 SH_PFC_FUNCTION(mmc1), 3584 SH_PFC_FUNCTION(mmc1),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
new file mode 100644
index 000000000000..bf76a654c02f
--- /dev/null
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -0,0 +1,4214 @@
1/*
2 * r8a7791 processor support - PFC hardware block.
3 *
4 * Copyright (C) 2013 Renesas Electronics Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2
8 * as published by the Free Software Foundation.
9 */
10
11#include <linux/kernel.h>
12#include <linux/platform_data/gpio-rcar.h>
13
14#include "core.h"
15#include "sh_pfc.h"
16
17#define CPU_ALL_PORT(fn, sfx) \
18 PORT_GP_32(0, fn, sfx), \
19 PORT_GP_32(1, fn, sfx), \
20 PORT_GP_32(2, fn, sfx), \
21 PORT_GP_32(3, fn, sfx), \
22 PORT_GP_32(4, fn, sfx), \
23 PORT_GP_32(5, fn, sfx), \
24 PORT_GP_32(6, fn, sfx), \
25 PORT_GP_32(7, fn, sfx)
26
27enum {
28 PINMUX_RESERVED = 0,
29
30 PINMUX_DATA_BEGIN,
31 GP_ALL(DATA),
32 PINMUX_DATA_END,
33
34 PINMUX_FUNCTION_BEGIN,
35 GP_ALL(FN),
36
37 /* GPSR0 */
38 FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
39 FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
40 FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
41 FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
42 FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
43 FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
44
45 /* GPSR1 */
46 FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
47 FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
48 FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
49 FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
50 FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
51 FN_IP3_21_20,
52
53 /* GPSR2 */
54 FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
55 FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
56 FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
57 FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
58 FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
59 FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
60 FN_IP6_5_3, FN_IP6_7_6,
61
62 /* GPSR3 */
63 FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
64 FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
65 FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
66 FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
67 FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
68 FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
69 FN_IP9_18_17,
70
71 /* GPSR4 */
72 FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
73 FN_VI0_DATA0_VI0_B0, FN_VI0_DATA1_VI0_B1, FN_VI0_DATA2_VI0_B2,
74 FN_IP9_28_27, FN_VI0_DATA4_VI0_B4, FN_VI0_DATA5_VI0_B5,
75 FN_VI0_DATA6_VI0_B6, FN_VI0_DATA7_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
76 FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
77 FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
78 FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
79 FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
80
81 /* GPSR5 */
82 FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
83 FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
84 FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
85 FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
86 FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
87 FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
88 FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
89
90 /* GPSR6 */
91 FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
92 FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
93 FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
94 FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
95 FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
96 FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
97 FN_USB1_OVC, FN_DU0_DOTCLKIN,
98
99 /* GPSR7 */
100 FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
101 FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
102 FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
103 FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
104 FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
105 FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
106
107 /* IPSR0 */
108 FN_D0, FN_D1, FN_D2, FN_D3, FN_D4, FN_D5, FN_D6, FN_D7, FN_D8,
109 FN_D9, FN_D10, FN_D11, FN_D12, FN_D13, FN_D14, FN_D15,
110 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
111 FN_A1, FN_MSIOF0_SYNC_B, FN_A2, FN_MSIOF0_SS1_B,
112 FN_A3, FN_MSIOF0_SS2_B, FN_A4, FN_MSIOF0_TXD_B,
113 FN_A5, FN_MSIOF0_RXD_B, FN_A6, FN_MSIOF1_SCK,
114
115 /* IPSR1 */
116 FN_A7, FN_MSIOF1_SYNC, FN_A8, FN_MSIOF1_SS1, FN_SCL0,
117 FN_A9, FN_MSIOF1_SS2, FN_SDA0,
118 FN_A10, FN_MSIOF1_TXD, FN_MSIOF1_TXD_D,
119 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
120 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
121 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
122 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
123 FN_A15, FN_BPFCLK_C,
124 FN_A16, FN_DREQ2_B, FN_FMCLK_C, FN_SCIFA1_SCK_B,
125 FN_A17, FN_DACK2_B, FN_SDA0_C,
126 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, FN_SCIFB1_RXD_C,
127
128 /* IPSR2 */
129 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, FN_SCIFB1_TXD_C, FN_SCIFB1_SCK_B,
130 FN_A20, FN_SPCLK,
131 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0,
132 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
133 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
134 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
135 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
136 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1,
137 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1,
138 FN_EX_CS1_N, FN_MSIOF2_SCK,
139 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC,
140 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD, FN_ATAG0_N, FN_EX_WAIT1,
141
142 /* IPSR3 */
143 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, FN_EX_WAIT2,
144 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
145 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1,
146 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
147 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2,
148 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
149 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B,
150 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
151 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B,
152 FN_DREQ0, FN_PWM3, FN_TPU_TO3,
153 FN_DACK0, FN_DRACK0, FN_REMOCON,
154 FN_SPEEDIN, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
155 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
156 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C, FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
157 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C, FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
158
159 /* IPSR4 */
160 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C,
161 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B, FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
162 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
163 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
164 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
165 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
166 FN_GLO_Q1_D, FN_HCTS1_N_E,
167 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
168 FN_SSI_SCK34, FN_SSI_WS34, FN_SSI_SDATA3,
169 FN_SSI_SCK4, FN_GLO_SS_D,
170 FN_SSI_WS4, FN_GLO_RFON_D,
171 FN_SSI_SDATA4, FN_MSIOF2_SCK_D,
172 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
173 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
174
175 /* IPSR5 */
176 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
177 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
178 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
179 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
180 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
181 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
182 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
183 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
184 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS,
185 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
186 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B,
187 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B,
188 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D,
189 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
190 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
191
192 /* IPSR6 */
193 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
194 FN_SCIF_CLK, FN_BPFCLK_E,
195 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
196 FN_SCIFA2_RXD, FN_FMIN_E,
197 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
198 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N,
199 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N,
200 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N,
201 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
202 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
203 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
204 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B, FN_SDA1_E, FN_MSIOF2_SYNC_E,
205 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B, FN_GPS_CLK_C, FN_GPS_CLK_D,
206 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B, FN_GPS_SIGN_C, FN_GPS_SIGN_D,
207
208 /* IPSR7 */
209 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
210 FN_SCIF_CLK_B, FN_GPS_MAG_D,
211 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
212 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
213 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
214 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
215 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B,
216 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B,
217 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B,
218 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B,
219 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B,
220 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B,
221 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
222 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
223 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
224 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
225 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
226 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
227
228 /* IPSR8 */
229 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, FN_SSI_WS78_B,
230 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
231 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
232 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
233 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
234 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
235 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
236 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B, FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
237 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
238 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
239 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
240 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
241 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
242 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
243 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B,
244 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
245 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
246
247 /* IPSR9 */
248 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
249 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C, FN_SCIF3_SCK, FN_SCIFA3_SCK,
250 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
251 FN_DU1_DOTCLKOUT0, FN_QCLK,
252 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
253 FN_TX3_B, FN_SCL2_B, FN_PWM4,
254 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
255 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
256 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
257 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
258 FN_DU1_DISP, FN_QPOLA,
259 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B,
260 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
261 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
262 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
263 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
264 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B,
265 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
266 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N,
267
268 /* IPSR10 */
269 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
270 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N,
271 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
272 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N,
273 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
274 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N,
275 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
276 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
277 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
278 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D,
279 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D,
280 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D,
281 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
282 FN_TS_SDATA0_C, FN_ATACS11_N,
283 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B,
284 FN_TS_SCK0_C, FN_ATAG1_N,
285 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
286 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
287 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
288
289 /* IPSR11 */
290 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
291 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
292 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
293 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
294 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
295 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
296 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
297 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
298 FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
299 FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
300 FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
301 FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
302 FN_VI1_DATA7, FN_AVB_MDC,
303 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
304 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
305
306 /* IPSR12 */
307 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
308 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
309 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
310 FN_SCL2_D, FN_MSIOF1_RXD_E,
311 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
312 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
313 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
314 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
315 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
316 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
317 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
318 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
319 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
320 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
321 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
322 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
323 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
324
325 /* IPSR13 */
326 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
327 FN_ADICLK_B, FN_MSIOF0_SS1_C,
328 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
329 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
330 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
331 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
332 FN_SD0_CLK, FN_SPCLK_B, FN_SD0_CMD, FN_MOSI_IO0_B,
333 FN_SD0_DATA0, FN_MISO_IO1_B, FN_SD0_DATA1, FN_IO2_B,
334 FN_SD0_DATA2, FN_IO3_B, FN_SD0_DATA3, FN_SSL_B,
335 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
336 FN_SCIFA5_TXD_B, FN_TX3_C,
337 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
338 FN_SCIFA5_RXD_B, FN_RX3_C,
339 FN_SD1_CMD, FN_REMOCON_B, FN_SD1_DATA0, FN_SPEEDIN_B,
340 FN_SD1_DATA1, FN_IETX_B, FN_SD1_DATA2, FN_IECLK_B,
341 FN_SD1_DATA3, FN_IERX_B,
342 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
343
344 /* IPSR14 */
345 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C,
346 FN_SD2_CLK, FN_MMC_CLK, FN_SD2_CMD, FN_MMC_CMD,
347 FN_SD2_DATA0, FN_MMC_D0, FN_SD2_DATA1, FN_MMC_D1,
348 FN_SD2_DATA2, FN_MMC_D2, FN_SD2_DATA3, FN_MMC_D3,
349 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
350 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
351 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, FN_VI1_CLK_C, FN_VI1_G0_B,
352 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, FN_VI1_CLKENB_C, FN_VI1_G1_B,
353 FN_MSIOF0_TXD, FN_ADICLK, FN_VI1_FIELD_C, FN_VI1_G2_B,
354 FN_MSIOF0_RXD, FN_ADICHS0, FN_VI1_DATA0_C, FN_VI1_G3_B,
355 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
356 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B,
357 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
358 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B,
359
360 /* IPSR15 */
361 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D,
362 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C,
363 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D,
364 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
365 FN_PWM5_B, FN_SCIFA3_TXD_C,
366 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
367 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
368 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
369 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
370 FN_HCTS0_N, FN_SCIFB0_CTS_N, FN_GLO_I0_C, FN_TCLK1, FN_VI1_DATA1_C,
371 FN_HRTS0_N, FN_SCIFB0_RTS_N, FN_GLO_I1_C, FN_VI1_DATA2_C,
372 FN_HSCK0, FN_SCIFB0_SCK, FN_GLO_Q0_C, FN_CAN_CLK,
373 FN_TCLK2, FN_VI1_DATA3_C,
374 FN_HRX0, FN_SCIFB0_RXD, FN_GLO_Q1_C, FN_CAN0_RX_B, FN_VI1_DATA4_C,
375 FN_HTX0, FN_SCIFB0_TXD, FN_GLO_SCLK_C, FN_CAN0_TX_B, FN_VI1_DATA5_C,
376
377 /* IPSR16 */
378 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B, FN_GLO_SDATA_C, FN_VI1_DATA6_C,
379 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B, FN_GLO_SS_C, FN_VI1_DATA7_C,
380 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
381 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
382 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
383
384 /* MOD_SEL */
385 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
386 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
387 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
388 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
389 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
390 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
391 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
392 FN_SEL_QSP_0, FN_SEL_QSP_1,
393 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
394 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
395 FN_SEL_HSCIF1_4,
396 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
397 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
398 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
399 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
400 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
401
402 /* MOD_SEL2 */
403 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
404 FN_SEL_SCIF0_4,
405 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
406 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
407 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
408 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
409 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
410 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
411 FN_SEL_ADG_0, FN_SEL_ADG_1,
412 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
413 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
414 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
415 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
416 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
417 FN_SEL_SIM_0, FN_SEL_SIM_1,
418 FN_SEL_SSI8_0, FN_SEL_SSI8_1,
419
420 /* MOD_SEL3 */
421 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
422 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
423 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
424 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
425 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
426 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
427 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
428 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
429 FN_SEL_MMC_0, FN_SEL_MMC_1,
430 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
431 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
432 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
433 FN_SEL_IIC1_4,
434 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
435
436 /* MOD_SEL4 */
437 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
438 FN_SEL_SOF1_4,
439 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
440 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
441 FN_SEL_RAD_0, FN_SEL_RAD_1,
442 FN_SEL_RCN_0, FN_SEL_RCN_1,
443 FN_SEL_RSP_0, FN_SEL_RSP_1,
444 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
445 FN_SEL_SCIF2_4,
446 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
447 FN_SEL_SOF2_4,
448 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
449 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
450 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
451 PINMUX_FUNCTION_END,
452
453 PINMUX_MARK_BEGIN,
454
455 EX_CS0_N_MARK, RD_N_MARK,
456
457 AUDIO_CLKA_MARK,
458
459 VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
460 VI0_DATA2_VI0_B2_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
461 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
462
463 SD1_CLK_MARK,
464
465 USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK, USB1_OVC_MARK,
466 DU0_DOTCLKIN_MARK,
467
468 /* IPSR0 */
469 D0_MARK, D1_MARK, D2_MARK, D3_MARK, D4_MARK, D5_MARK,
470 D6_MARK, D7_MARK, D8_MARK,
471 D9_MARK, D10_MARK, D11_MARK, D12_MARK, D13_MARK, D14_MARK, D15_MARK,
472 A0_MARK, ATAWR0_N_C_MARK, MSIOF0_SCK_B_MARK, SCL0_C_MARK, PWM2_B_MARK,
473 A1_MARK, MSIOF0_SYNC_B_MARK, A2_MARK, MSIOF0_SS1_B_MARK,
474 A3_MARK, MSIOF0_SS2_B_MARK, A4_MARK, MSIOF0_TXD_B_MARK,
475 A5_MARK, MSIOF0_RXD_B_MARK, A6_MARK, MSIOF1_SCK_MARK,
476
477 /* IPSR1 */
478 A7_MARK, MSIOF1_SYNC_MARK, A8_MARK, MSIOF1_SS1_MARK, SCL0_MARK,
479 A9_MARK, MSIOF1_SS2_MARK, SDA0_MARK,
480 A10_MARK, MSIOF1_TXD_MARK, MSIOF1_TXD_D_MARK,
481 A11_MARK, MSIOF1_RXD_MARK, SCL3_D_MARK, MSIOF1_RXD_D_MARK,
482 A12_MARK, FMCLK_MARK, SDA3_D_MARK, MSIOF1_SCK_D_MARK,
483 A13_MARK, ATAG0_N_C_MARK, BPFCLK_MARK, MSIOF1_SS1_D_MARK,
484 A14_MARK, ATADIR0_N_C_MARK, FMIN_MARK, FMIN_C_MARK, MSIOF1_SYNC_D_MARK,
485 A15_MARK, BPFCLK_C_MARK,
486 A16_MARK, DREQ2_B_MARK, FMCLK_C_MARK, SCIFA1_SCK_B_MARK,
487 A17_MARK, DACK2_B_MARK, SDA0_C_MARK,
488 A18_MARK, DREQ1_MARK, SCIFA1_RXD_C_MARK, SCIFB1_RXD_C_MARK,
489
490 /* IPSR2 */
491 A19_MARK, DACK1_MARK, SCIFA1_TXD_C_MARK,
492 SCIFB1_TXD_C_MARK, SCIFB1_SCK_B_MARK,
493 A20_MARK, SPCLK_MARK,
494 A21_MARK, ATAWR0_N_B_MARK, MOSI_IO0_MARK,
495 A22_MARK, MISO_IO1_MARK, FMCLK_B_MARK, TX0_MARK, SCIFA0_TXD_MARK,
496 A23_MARK, IO2_MARK, BPFCLK_B_MARK, RX0_MARK, SCIFA0_RXD_MARK,
497 A24_MARK, DREQ2_MARK, IO3_MARK, TX1_MARK, SCIFA1_TXD_MARK,
498 A25_MARK, DACK2_MARK, SSL_MARK, DREQ1_C_MARK,
499 RX1_MARK, SCIFA1_RXD_MARK,
500 CS0_N_MARK, ATAG0_N_B_MARK, SCL1_MARK,
501 CS1_N_A26_MARK, ATADIR0_N_B_MARK, SDA1_MARK,
502 EX_CS1_N_MARK, MSIOF2_SCK_MARK,
503 EX_CS2_N_MARK, ATAWR0_N_MARK, MSIOF2_SYNC_MARK,
504 EX_CS3_N_MARK, ATADIR0_N_MARK, MSIOF2_TXD_MARK,
505 ATAG0_N_MARK, EX_WAIT1_MARK,
506
507 /* IPSR3 */
508 EX_CS4_N_MARK, ATARD0_N_MARK, MSIOF2_RXD_MARK, EX_WAIT2_MARK,
509 EX_CS5_N_MARK, ATACS00_N_MARK, MSIOF2_SS1_MARK, HRX1_B_MARK,
510 SCIFB1_RXD_B_MARK, PWM1_MARK, TPU_TO1_MARK,
511 BS_N_MARK, ATACS10_N_MARK, MSIOF2_SS2_MARK, HTX1_B_MARK,
512 SCIFB1_TXD_B_MARK, PWM2_MARK, TPU_TO2_MARK,
513 RD_WR_N_MARK, HRX2_B_MARK, FMIN_B_MARK,
514 SCIFB0_RXD_B_MARK, DREQ1_D_MARK,
515 WE0_N_MARK, HCTS2_N_B_MARK, SCIFB0_TXD_B_MARK,
516 WE1_N_MARK, ATARD0_N_B_MARK, HTX2_B_MARK, SCIFB0_RTS_N_B_MARK,
517 EX_WAIT0_MARK, HRTS2_N_B_MARK, SCIFB0_CTS_N_B_MARK,
518 DREQ0_MARK, PWM3_MARK, TPU_TO3_MARK,
519 DACK0_MARK, DRACK0_MARK, REMOCON_MARK,
520 SPEEDIN_MARK, HSCK0_C_MARK, HSCK2_C_MARK, SCIFB0_SCK_B_MARK,
521 SCIFB2_SCK_B_MARK, DREQ2_C_MARK, HTX2_D_MARK,
522 SSI_SCK0129_MARK, HRX0_C_MARK, HRX2_C_MARK,
523 SCIFB0_RXD_C_MARK, SCIFB2_RXD_C_MARK,
524 SSI_WS0129_MARK, HTX0_C_MARK, HTX2_C_MARK,
525 SCIFB0_TXD_C_MARK, SCIFB2_TXD_C_MARK,
526
527 /* IPSR4 */
528 SSI_SDATA0_MARK, SCL0_B_MARK, SCL7_B_MARK, MSIOF2_SCK_C_MARK,
529 SSI_SCK1_MARK, SDA0_B_MARK, SDA7_B_MARK,
530 MSIOF2_SYNC_C_MARK, GLO_I0_D_MARK,
531 SSI_WS1_MARK, SCL1_B_MARK, SCL8_B_MARK,
532 MSIOF2_TXD_C_MARK, GLO_I1_D_MARK,
533 SSI_SDATA1_MARK, SDA1_B_MARK, SDA8_B_MARK, MSIOF2_RXD_C_MARK,
534 SSI_SCK2_MARK, SCL2_MARK, GPS_CLK_B_MARK, GLO_Q0_D_MARK, HSCK1_E_MARK,
535 SSI_WS2_MARK, SDA2_MARK, GPS_SIGN_B_MARK, RX2_E_MARK,
536 GLO_Q1_D_MARK, HCTS1_N_E_MARK,
537 SSI_SDATA2_MARK, GPS_MAG_B_MARK, TX2_E_MARK, HRTS1_N_E_MARK,
538 SSI_SCK34_MARK, SSI_WS34_MARK, SSI_SDATA3_MARK,
539 SSI_SCK4_MARK, GLO_SS_D_MARK,
540 SSI_WS4_MARK, GLO_RFON_D_MARK,
541 SSI_SDATA4_MARK, MSIOF2_SCK_D_MARK,
542 SSI_SCK5_MARK, MSIOF1_SCK_C_MARK, TS_SDATA0_MARK, GLO_I0_MARK,
543 MSIOF2_SYNC_D_MARK, VI1_R2_B_MARK,
544
545 /* IPSR5 */
546 SSI_WS5_MARK, MSIOF1_SYNC_C_MARK, TS_SCK0_MARK, GLO_I1_MARK,
547 MSIOF2_TXD_D_MARK, VI1_R3_B_MARK,
548 SSI_SDATA5_MARK, MSIOF1_TXD_C_MARK, TS_SDEN0_MARK, GLO_Q0_MARK,
549 MSIOF2_SS1_D_MARK, VI1_R4_B_MARK,
550 SSI_SCK6_MARK, MSIOF1_RXD_C_MARK, TS_SPSYNC0_MARK, GLO_Q1_MARK,
551 MSIOF2_RXD_D_MARK, VI1_R5_B_MARK,
552 SSI_WS6_MARK, GLO_SCLK_MARK, MSIOF2_SS2_D_MARK, VI1_R6_B_MARK,
553 SSI_SDATA6_MARK, STP_IVCXO27_0_B_MARK, GLO_SDATA_MARK, VI1_R7_B_MARK,
554 SSI_SCK78_MARK, STP_ISCLK_0_B_MARK, GLO_SS_MARK,
555 SSI_WS78_MARK, TX0_D_MARK, STP_ISD_0_B_MARK, GLO_RFON_MARK,
556 SSI_SDATA7_MARK, RX0_D_MARK, STP_ISEN_0_B_MARK,
557 SSI_SDATA8_MARK, TX1_D_MARK, STP_ISSYNC_0_B_MARK,
558 SSI_SCK9_MARK, RX1_D_MARK, GLO_SCLK_D_MARK,
559 SSI_WS9_MARK, TX3_D_MARK, CAN0_TX_D_MARK, GLO_SDATA_D_MARK,
560 SSI_SDATA9_MARK, RX3_D_MARK, CAN0_RX_D_MARK,
561
562 /* IPSR6 */
563 AUDIO_CLKB_MARK, STP_OPWM_0_B_MARK, MSIOF1_SCK_B_MARK,
564 SCIF_CLK_MARK, BPFCLK_E_MARK,
565 AUDIO_CLKC_MARK, SCIFB0_SCK_C_MARK, MSIOF1_SYNC_B_MARK, RX2_MARK,
566 SCIFA2_RXD_MARK, FMIN_E_MARK,
567 AUDIO_CLKOUT_MARK, MSIOF1_SS1_B_MARK, TX2_MARK, SCIFA2_TXD_MARK,
568 IRQ0_MARK, SCIFB1_RXD_D_MARK, INTC_IRQ0_N_MARK,
569 IRQ1_MARK, SCIFB1_SCK_C_MARK, INTC_IRQ1_N_MARK,
570 IRQ2_MARK, SCIFB1_TXD_D_MARK, INTC_IRQ2_N_MARK,
571 IRQ3_MARK, SCL4_C_MARK, MSIOF2_TXD_E_MARK, INTC_IRQ3_N_MARK,
572 IRQ4_MARK, HRX1_C_MARK, SDA4_C_MARK,
573 MSIOF2_RXD_E_MARK, INTC_IRQ4_N_MARK,
574 IRQ5_MARK, HTX1_C_MARK, SCL1_E_MARK, MSIOF2_SCK_E_MARK,
575 IRQ6_MARK, HSCK1_C_MARK, MSIOF1_SS2_B_MARK,
576 SDA1_E_MARK, MSIOF2_SYNC_E_MARK,
577 IRQ7_MARK, HCTS1_N_C_MARK, MSIOF1_TXD_B_MARK,
578 GPS_CLK_C_MARK, GPS_CLK_D_MARK,
579 IRQ8_MARK, HRTS1_N_C_MARK, MSIOF1_RXD_B_MARK,
580 GPS_SIGN_C_MARK, GPS_SIGN_D_MARK,
581
582 /* IPSR7 */
583 IRQ9_MARK, DU1_DOTCLKIN_B_MARK, CAN_CLK_D_MARK, GPS_MAG_C_MARK,
584 SCIF_CLK_B_MARK, GPS_MAG_D_MARK,
585 DU1_DR0_MARK, LCDOUT0_MARK, VI1_DATA0_B_MARK, TX0_B_MARK,
586 SCIFA0_TXD_B_MARK, MSIOF2_SCK_B_MARK,
587 DU1_DR1_MARK, LCDOUT1_MARK, VI1_DATA1_B_MARK, RX0_B_MARK,
588 SCIFA0_RXD_B_MARK, MSIOF2_SYNC_B_MARK,
589 DU1_DR2_MARK, LCDOUT2_MARK, SSI_SCK0129_B_MARK,
590 DU1_DR3_MARK, LCDOUT3_MARK, SSI_WS0129_B_MARK,
591 DU1_DR4_MARK, LCDOUT4_MARK, SSI_SDATA0_B_MARK,
592 DU1_DR5_MARK, LCDOUT5_MARK, SSI_SCK1_B_MARK,
593 DU1_DR6_MARK, LCDOUT6_MARK, SSI_WS1_B_MARK,
594 DU1_DR7_MARK, LCDOUT7_MARK, SSI_SDATA1_B_MARK,
595 DU1_DG0_MARK, LCDOUT8_MARK, VI1_DATA2_B_MARK, TX1_B_MARK,
596 SCIFA1_TXD_B_MARK, MSIOF2_SS1_B_MARK,
597 DU1_DG1_MARK, LCDOUT9_MARK, VI1_DATA3_B_MARK, RX1_B_MARK,
598 SCIFA1_RXD_B_MARK, MSIOF2_SS2_B_MARK,
599 DU1_DG2_MARK, LCDOUT10_MARK, VI1_DATA4_B_MARK, SCIF1_SCK_B_MARK,
600 SCIFA1_SCK_MARK, SSI_SCK78_B_MARK,
601
602 /* IPSR8 */
603 DU1_DG3_MARK, LCDOUT11_MARK, VI1_DATA5_B_MARK, SSI_WS78_B_MARK,
604 DU1_DG4_MARK, LCDOUT12_MARK, VI1_DATA6_B_MARK, HRX0_B_MARK,
605 SCIFB2_RXD_B_MARK, SSI_SDATA7_B_MARK,
606 DU1_DG5_MARK, LCDOUT13_MARK, VI1_DATA7_B_MARK, HCTS0_N_B_MARK,
607 SCIFB2_TXD_B_MARK, SSI_SDATA8_B_MARK,
608 DU1_DG6_MARK, LCDOUT14_MARK, HRTS0_N_B_MARK,
609 SCIFB2_CTS_N_B_MARK, SSI_SCK9_B_MARK,
610 DU1_DG7_MARK, LCDOUT15_MARK, HTX0_B_MARK,
611 SCIFB2_RTS_N_B_MARK, SSI_WS9_B_MARK,
612 DU1_DB0_MARK, LCDOUT16_MARK, VI1_CLK_B_MARK, TX2_B_MARK,
613 SCIFA2_TXD_B_MARK, MSIOF2_TXD_B_MARK,
614 DU1_DB1_MARK, LCDOUT17_MARK, VI1_HSYNC_N_B_MARK, RX2_B_MARK,
615 SCIFA2_RXD_B_MARK, MSIOF2_RXD_B_MARK,
616 DU1_DB2_MARK, LCDOUT18_MARK, VI1_VSYNC_N_B_MARK, SCIF2_SCK_B_MARK,
617 SCIFA2_SCK_MARK, SSI_SDATA9_B_MARK,
618 DU1_DB3_MARK, LCDOUT19_MARK, VI1_CLKENB_B_MARK,
619 DU1_DB4_MARK, LCDOUT20_MARK, VI1_FIELD_B_MARK, CAN1_RX_MARK,
620 DU1_DB5_MARK, LCDOUT21_MARK, TX3_MARK, SCIFA3_TXD_MARK, CAN1_TX_MARK,
621
622 /* IPSR9 */
623 DU1_DB6_MARK, LCDOUT22_MARK, SCL3_C_MARK, RX3_MARK, SCIFA3_RXD_MARK,
624 DU1_DB7_MARK, LCDOUT23_MARK, SDA3_C_MARK,
625 SCIF3_SCK_MARK, SCIFA3_SCK_MARK,
626 DU1_DOTCLKIN_MARK, QSTVA_QVS_MARK,
627 DU1_DOTCLKOUT0_MARK, QCLK_MARK,
628 DU1_DOTCLKOUT1_MARK, QSTVB_QVE_MARK, CAN0_TX_MARK,
629 TX3_B_MARK, SCL2_B_MARK, PWM4_MARK,
630 DU1_EXHSYNC_DU1_HSYNC_MARK, QSTH_QHS_MARK,
631 DU1_EXVSYNC_DU1_VSYNC_MARK, QSTB_QHE_MARK,
632 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, QCPV_QDE_MARK,
633 CAN0_RX_MARK, RX3_B_MARK, SDA2_B_MARK,
634 DU1_DISP_MARK, QPOLA_MARK,
635 DU1_CDE_MARK, QPOLB_MARK, PWM4_B_MARK,
636 VI0_CLKENB_MARK, TX4_MARK, SCIFA4_TXD_MARK, TS_SDATA0_D_MARK,
637 VI0_FIELD_MARK, RX4_MARK, SCIFA4_RXD_MARK, TS_SCK0_D_MARK,
638 VI0_HSYNC_N_MARK, TX5_MARK, SCIFA5_TXD_MARK, TS_SDEN0_D_MARK,
639 VI0_VSYNC_N_MARK, RX5_MARK, SCIFA5_RXD_MARK, TS_SPSYNC0_D_MARK,
640 VI0_DATA3_VI0_B3_MARK, SCIF3_SCK_B_MARK, SCIFA3_SCK_B_MARK,
641 VI0_G0_MARK, SCL8_MARK, STP_IVCXO27_0_C_MARK, SCL4_MARK,
642 HCTS2_N_MARK, SCIFB2_CTS_N_MARK, ATAWR1_N_MARK,
643
644 /* IPSR10 */
645 VI0_G1_MARK, SDA8_MARK, STP_ISCLK_0_C_MARK, SDA4_MARK,
646 HRTS2_N_MARK, SCIFB2_RTS_N_MARK, ATADIR1_N_MARK,
647 VI0_G2_MARK, VI2_HSYNC_N_MARK, STP_ISD_0_C_MARK, SCL3_B_MARK,
648 HSCK2_MARK, SCIFB2_SCK_MARK, ATARD1_N_MARK,
649 VI0_G3_MARK, VI2_VSYNC_N_MARK, STP_ISEN_0_C_MARK, SDA3_B_MARK,
650 HRX2_MARK, SCIFB2_RXD_MARK, ATACS01_N_MARK,
651 VI0_G4_MARK, VI2_CLKENB_MARK, STP_ISSYNC_0_C_MARK,
652 HTX2_MARK, SCIFB2_TXD_MARK, SCIFB0_SCK_D_MARK,
653 VI0_G5_MARK, VI2_FIELD_MARK, STP_OPWM_0_C_MARK, FMCLK_D_MARK,
654 CAN0_TX_E_MARK, HTX1_D_MARK, SCIFB0_TXD_D_MARK,
655 VI0_G6_MARK, VI2_CLK_MARK, BPFCLK_D_MARK,
656 VI0_G7_MARK, VI2_DATA0_MARK, FMIN_D_MARK,
657 VI0_R0_MARK, VI2_DATA1_MARK, GLO_I0_B_MARK,
658 TS_SDATA0_C_MARK, ATACS11_N_MARK,
659 VI0_R1_MARK, VI2_DATA2_MARK, GLO_I1_B_MARK,
660 TS_SCK0_C_MARK, ATAG1_N_MARK,
661 VI0_R2_MARK, VI2_DATA3_MARK, GLO_Q0_B_MARK, TS_SDEN0_C_MARK,
662 VI0_R3_MARK, VI2_DATA4_MARK, GLO_Q1_B_MARK, TS_SPSYNC0_C_MARK,
663 VI0_R4_MARK, VI2_DATA5_MARK, GLO_SCLK_B_MARK, TX0_C_MARK, SCL1_D_MARK,
664
665 /* IPSR11 */
666 VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
667 VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
668 VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
669 SDA4_B_MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
670 VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
671 TX4_B_MARK, SCIFA4_TXD_B_MARK,
672 VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
673 RX4_B_MARK, SCIFA4_RXD_B_MARK,
674 VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
675 VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
676 VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
677 VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
678 VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
679 VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
680 VI1_DATA7_MARK, AVB_MDC_MARK,
681 ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
682 ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
683
684 /* IPSR12 */
685 ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
686 ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
687 ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
688 SCL2_D_MARK, MSIOF1_RXD_E_MARK,
689 ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
690 SDA2_D_MARK, MSIOF1_SCK_E_MARK,
691 ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
692 CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
693 ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
694 CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
695 ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
696 ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
697 ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
698 ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
699 STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
700 ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
701 STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
702 ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
703
704 /* IPSR13 */
705 STP_ISD_0_MARK, AVB_TX_ER_MARK, SCIFB2_SCK_C_MARK,
706 ADICLK_B_MARK, MSIOF0_SS1_C_MARK,
707 STP_ISEN_0_MARK, AVB_TX_CLK_MARK, ADICHS0_B_MARK, MSIOF0_SS2_C_MARK,
708 STP_ISSYNC_0_MARK, AVB_COL_MARK, ADICHS1_B_MARK, MSIOF0_RXD_C_MARK,
709 STP_OPWM_0_MARK, AVB_GTX_CLK_MARK, PWM0_B_MARK,
710 ADICHS2_B_MARK, MSIOF0_TXD_C_MARK,
711 SD0_CLK_MARK, SPCLK_B_MARK, SD0_CMD_MARK, MOSI_IO0_B_MARK,
712 SD0_DATA0_MARK, MISO_IO1_B_MARK, SD0_DATA1_MARK, IO2_B_MARK,
713 SD0_DATA2_MARK, IO3_B_MARK, SD0_DATA3_MARK, SSL_B_MARK,
714 SD0_CD_MARK, MMC_D6_B_MARK, SIM0_RST_B_MARK, CAN0_RX_F_MARK,
715 SCIFA5_TXD_B_MARK, TX3_C_MARK,
716 SD0_WP_MARK, MMC_D7_B_MARK, SIM0_D_B_MARK, CAN0_TX_F_MARK,
717 SCIFA5_RXD_B_MARK, RX3_C_MARK,
718 SD1_CMD_MARK, REMOCON_B_MARK, SD1_DATA0_MARK, SPEEDIN_B_MARK,
719 SD1_DATA1_MARK, IETX_B_MARK, SD1_DATA2_MARK, IECLK_B_MARK,
720 SD1_DATA3_MARK, IERX_B_MARK,
721 SD1_CD_MARK, PWM0_MARK, TPU_TO0_MARK, SCL1_C_MARK,
722
723 /* IPSR14 */
724 SD1_WP_MARK, PWM1_B_MARK, SDA1_C_MARK,
725 SD2_CLK_MARK, MMC_CLK_MARK, SD2_CMD_MARK, MMC_CMD_MARK,
726 SD2_DATA0_MARK, MMC_D0_MARK, SD2_DATA1_MARK, MMC_D1_MARK,
727 SD2_DATA2_MARK, MMC_D2_MARK, SD2_DATA3_MARK, MMC_D3_MARK,
728 SD2_CD_MARK, MMC_D4_MARK, SCL8_C_MARK, TX5_B_MARK, SCIFA5_TXD_C_MARK,
729 SD2_WP_MARK, MMC_D5_MARK, SDA8_C_MARK, RX5_B_MARK, SCIFA5_RXD_C_MARK,
730 MSIOF0_SCK_MARK, RX2_C_MARK, ADIDATA_MARK,
731 VI1_CLK_C_MARK, VI1_G0_B_MARK,
732 MSIOF0_SYNC_MARK, TX2_C_MARK, ADICS_SAMP_MARK,
733 VI1_CLKENB_C_MARK, VI1_G1_B_MARK,
734 MSIOF0_TXD_MARK, ADICLK_MARK, VI1_FIELD_C_MARK, VI1_G2_B_MARK,
735 MSIOF0_RXD_MARK, ADICHS0_MARK, VI1_DATA0_C_MARK, VI1_G3_B_MARK,
736 MSIOF0_SS1_MARK, MMC_D6_MARK, ADICHS1_MARK, TX0_E_MARK,
737 VI1_HSYNC_N_C_MARK, SCL7_C_MARK, VI1_G4_B_MARK,
738 MSIOF0_SS2_MARK, MMC_D7_MARK, ADICHS2_MARK, RX0_E_MARK,
739 VI1_VSYNC_N_C_MARK, SDA7_C_MARK, VI1_G5_B_MARK,
740
741 /* IPSR15 */
742 SIM0_RST_MARK, IETX_MARK, CAN1_TX_D_MARK,
743 SIM0_CLK_MARK, IECLK_MARK, CAN_CLK_C_MARK,
744 SIM0_D_MARK, IERX_MARK, CAN1_RX_D_MARK,
745 GPS_CLK_MARK, DU1_DOTCLKIN_C_MARK, AUDIO_CLKB_B_MARK,
746 PWM5_B_MARK, SCIFA3_TXD_C_MARK,
747 GPS_SIGN_MARK, TX4_C_MARK, SCIFA4_TXD_C_MARK, PWM5_MARK,
748 VI1_G6_B_MARK, SCIFA3_RXD_C_MARK,
749 GPS_MAG_MARK, RX4_C_MARK, SCIFA4_RXD_C_MARK, PWM6_MARK,
750 VI1_G7_B_MARK, SCIFA3_SCK_C_MARK,
751 HCTS0_N_MARK, SCIFB0_CTS_N_MARK, GLO_I0_C_MARK,
752 TCLK1_MARK, VI1_DATA1_C_MARK,
753 HRTS0_N_MARK, SCIFB0_RTS_N_MARK, GLO_I1_C_MARK, VI1_DATA2_C_MARK,
754 HSCK0_MARK, SCIFB0_SCK_MARK, GLO_Q0_C_MARK, CAN_CLK_MARK,
755 TCLK2_MARK, VI1_DATA3_C_MARK,
756 HRX0_MARK, SCIFB0_RXD_MARK, GLO_Q1_C_MARK,
757 CAN0_RX_B_MARK, VI1_DATA4_C_MARK,
758 HTX0_MARK, SCIFB0_TXD_MARK, GLO_SCLK_C_MARK,
759 CAN0_TX_B_MARK, VI1_DATA5_C_MARK,
760
761 /* IPSR16 */
762 HRX1_MARK, SCIFB1_RXD_MARK, VI1_R0_B_MARK,
763 GLO_SDATA_C_MARK, VI1_DATA6_C_MARK,
764 HTX1_MARK, SCIFB1_TXD_MARK, VI1_R1_B_MARK,
765 GLO_SS_C_MARK, VI1_DATA7_C_MARK,
766 HSCK1_MARK, SCIFB1_SCK_MARK, MLB_CK_MARK, GLO_RFON_C_MARK,
767 HCTS1_N_MARK, SCIFB1_CTS_N_MARK, MLB_SIG_MARK, CAN1_TX_B_MARK,
768 HRTS1_N_MARK, SCIFB1_RTS_N_MARK, MLB_DAT_MARK, CAN1_RX_B_MARK,
769 PINMUX_MARK_END,
770};
771
772static const u16 pinmux_data[] = {
773 PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
774
775 PINMUX_DATA(EX_CS0_N_MARK, FN_EX_CS0_N),
776 PINMUX_DATA(RD_N_MARK, FN_RD_N),
777 PINMUX_DATA(AUDIO_CLKA_MARK, FN_AUDIO_CLKA),
778 PINMUX_DATA(VI0_CLK_MARK, FN_VI0_CLK),
779 PINMUX_DATA(VI0_DATA0_VI0_B0_MARK, FN_VI0_DATA0_VI0_B0),
780 PINMUX_DATA(VI0_DATA1_VI0_B1_MARK, FN_VI0_DATA1_VI0_B1),
781 PINMUX_DATA(VI0_DATA2_VI0_B2_MARK, FN_VI0_DATA2_VI0_B2),
782 PINMUX_DATA(VI0_DATA4_VI0_B4_MARK, FN_VI0_DATA4_VI0_B4),
783 PINMUX_DATA(VI0_DATA5_VI0_B5_MARK, FN_VI0_DATA5_VI0_B5),
784 PINMUX_DATA(VI0_DATA6_VI0_B6_MARK, FN_VI0_DATA6_VI0_B6),
785 PINMUX_DATA(VI0_DATA7_VI0_B7_MARK, FN_VI0_DATA7_VI0_B7),
786 PINMUX_DATA(USB0_PWEN_MARK, FN_USB0_PWEN),
787 PINMUX_DATA(USB0_OVC_MARK, FN_USB0_OVC),
788 PINMUX_DATA(USB1_PWEN_MARK, FN_USB1_PWEN),
789 PINMUX_DATA(USB1_OVC_MARK, FN_USB1_OVC),
790 PINMUX_DATA(DU0_DOTCLKIN_MARK, FN_DU0_DOTCLKIN),
791
792 /* IPSR0 */
793 PINMUX_IPSR_DATA(IP0_0, D0),
794 PINMUX_IPSR_DATA(IP0_1, D1),
795 PINMUX_IPSR_DATA(IP0_2, D2),
796 PINMUX_IPSR_DATA(IP0_3, D3),
797 PINMUX_IPSR_DATA(IP0_4, D4),
798 PINMUX_IPSR_DATA(IP0_5, D5),
799 PINMUX_IPSR_DATA(IP0_6, D6),
800 PINMUX_IPSR_DATA(IP0_7, D7),
801 PINMUX_IPSR_DATA(IP0_8, D8),
802 PINMUX_IPSR_DATA(IP0_9, D9),
803 PINMUX_IPSR_DATA(IP0_10, D10),
804 PINMUX_IPSR_DATA(IP0_11, D11),
805 PINMUX_IPSR_DATA(IP0_12, D12),
806 PINMUX_IPSR_DATA(IP0_13, D13),
807 PINMUX_IPSR_DATA(IP0_14, D14),
808 PINMUX_IPSR_DATA(IP0_15, D15),
809 PINMUX_IPSR_DATA(IP0_18_16, A0),
810 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, ATAWR0_N_C, SEL_LBS_2),
811 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, MSIOF0_SCK_B, SEL_SOF0_1),
812 PINMUX_IPSR_MODSEL_DATA(IP0_18_16, SCL0_C, SEL_IIC0_2),
813 PINMUX_IPSR_DATA(IP0_18_16, PWM2_B),
814 PINMUX_IPSR_DATA(IP0_20_19, A1),
815 PINMUX_IPSR_MODSEL_DATA(IP0_20_19, MSIOF0_SYNC_B, SEL_SOF0_1),
816 PINMUX_IPSR_DATA(IP0_22_21, A2),
817 PINMUX_IPSR_MODSEL_DATA(IP0_22_21, MSIOF0_SS1_B, SEL_SOF0_1),
818 PINMUX_IPSR_DATA(IP0_24_23, A3),
819 PINMUX_IPSR_MODSEL_DATA(IP0_24_23, MSIOF0_SS2_B, SEL_SOF0_1),
820 PINMUX_IPSR_DATA(IP0_26_25, A4),
821 PINMUX_IPSR_MODSEL_DATA(IP0_26_25, MSIOF0_TXD_B, SEL_SOF0_1),
822 PINMUX_IPSR_DATA(IP0_28_27, A5),
823 PINMUX_IPSR_MODSEL_DATA(IP0_28_27, MSIOF0_RXD_B, SEL_SOF0_1),
824 PINMUX_IPSR_DATA(IP0_30_29, A6),
825 PINMUX_IPSR_MODSEL_DATA(IP0_30_29, MSIOF1_SCK, SEL_SOF1_0),
826
827 /* IPSR1 */
828 PINMUX_IPSR_DATA(IP1_1_0, A7),
829 PINMUX_IPSR_MODSEL_DATA(IP1_1_0, MSIOF1_SYNC, SEL_SOF1_0),
830 PINMUX_IPSR_DATA(IP1_3_2, A8),
831 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, MSIOF1_SS1, SEL_SOF1_0),
832 PINMUX_IPSR_MODSEL_DATA(IP1_3_2, SCL0, SEL_IIC0_0),
833 PINMUX_IPSR_DATA(IP1_5_4, A9),
834 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, MSIOF1_SS2, SEL_SOF1_0),
835 PINMUX_IPSR_MODSEL_DATA(IP1_5_4, SDA0, SEL_IIC0_0),
836 PINMUX_IPSR_DATA(IP1_7_6, A10),
837 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD, SEL_SOF1_0),
838 PINMUX_IPSR_MODSEL_DATA(IP1_7_6, MSIOF1_TXD_D, SEL_SOF1_3),
839 PINMUX_IPSR_DATA(IP1_10_8, A11),
840 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD, SEL_SOF1_0),
841 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, SCL3_D, SEL_IIC3_3),
842 PINMUX_IPSR_MODSEL_DATA(IP1_10_8, MSIOF1_RXD_D, SEL_SOF1_3),
843 PINMUX_IPSR_DATA(IP1_13_11, A12),
844 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, FMCLK, SEL_FM_0),
845 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, SDA3_D, SEL_IIC3_3),
846 PINMUX_IPSR_MODSEL_DATA(IP1_13_11, MSIOF1_SCK_D, SEL_SOF1_3),
847 PINMUX_IPSR_DATA(IP1_16_14, A13),
848 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, ATAG0_N_C, SEL_LBS_2),
849 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, BPFCLK, SEL_FM_0),
850 PINMUX_IPSR_MODSEL_DATA(IP1_16_14, MSIOF1_SS1_D, SEL_SOF1_3),
851 PINMUX_IPSR_DATA(IP1_19_17, A14),
852 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, ATADIR0_N_C, SEL_LBS_2),
853 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN, SEL_FM_0),
854 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, FMIN_C, SEL_FM_2),
855 PINMUX_IPSR_MODSEL_DATA(IP1_19_17, MSIOF1_SYNC_D, SEL_SOF1_3),
856 PINMUX_IPSR_DATA(IP1_22_20, A15),
857 PINMUX_IPSR_MODSEL_DATA(IP1_22_20, BPFCLK_C, SEL_FM_2),
858 PINMUX_IPSR_DATA(IP1_25_23, A16),
859 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, DREQ2_B, SEL_LBS_1),
860 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, FMCLK_C, SEL_FM_2),
861 PINMUX_IPSR_MODSEL_DATA(IP1_25_23, SCIFA1_SCK_B, SEL_SCIFA1_1),
862 PINMUX_IPSR_DATA(IP1_28_26, A17),
863 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, DACK2_B, SEL_LBS_1),
864 PINMUX_IPSR_MODSEL_DATA(IP1_28_26, SDA0_C, SEL_IIC0_2),
865 PINMUX_IPSR_DATA(IP1_31_29, A18),
866 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, DREQ1, SEL_LBS_0),
867 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFA1_RXD_C, SEL_SCIFA1_2),
868 PINMUX_IPSR_MODSEL_DATA(IP1_31_29, SCIFB1_RXD_C, SEL_SCIFB1_2),
869
870 /* IPSR2 */
871 PINMUX_IPSR_DATA(IP2_2_0, A19),
872 PINMUX_IPSR_DATA(IP2_2_0, DACK1),
873 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFA1_TXD_C, SEL_SCIFA1_2),
874 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_TXD_C, SEL_SCIFB1_2),
875 PINMUX_IPSR_MODSEL_DATA(IP2_2_0, SCIFB1_SCK_B, SEL_SCIFB1_0),
876 PINMUX_IPSR_DATA(IP2_2_0, A20),
877 PINMUX_IPSR_MODSEL_DATA(IP2_4_3, SPCLK, SEL_QSP_0),
878 PINMUX_IPSR_DATA(IP2_6_5, A21),
879 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, ATAWR0_N_B, SEL_LBS_1),
880 PINMUX_IPSR_MODSEL_DATA(IP2_6_5, MOSI_IO0, SEL_QSP_0),
881 PINMUX_IPSR_DATA(IP2_9_7, A22),
882 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, MISO_IO1, SEL_QSP_0),
883 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, FMCLK_B, SEL_FM_1),
884 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, TX0, SEL_SCIF0_0),
885 PINMUX_IPSR_MODSEL_DATA(IP2_9_7, SCIFA0_TXD, SEL_SCFA_0),
886 PINMUX_IPSR_DATA(IP2_12_10, A23),
887 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, IO2, SEL_QSP_0),
888 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, BPFCLK_B, SEL_FM_1),
889 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, RX0, SEL_SCIF0_0),
890 PINMUX_IPSR_MODSEL_DATA(IP2_12_10, SCIFA0_RXD, SEL_SCFA_0),
891 PINMUX_IPSR_DATA(IP2_15_13, A24),
892 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, DREQ2, SEL_LBS_0),
893 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, IO3, SEL_QSP_0),
894 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, TX1, SEL_SCIF1_0),
895 PINMUX_IPSR_MODSEL_DATA(IP2_15_13, SCIFA1_TXD, SEL_SCIFA1_0),
896 PINMUX_IPSR_DATA(IP2_18_16, A25),
897 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DACK2, SEL_LBS_0),
898 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SSL, SEL_QSP_0),
899 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, DREQ1_C, SEL_LBS_2),
900 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, RX1, SEL_SCIF1_0),
901 PINMUX_IPSR_MODSEL_DATA(IP2_18_16, SCIFA1_RXD, SEL_SCIFA1_0),
902 PINMUX_IPSR_DATA(IP2_20_19, CS0_N),
903 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, ATAG0_N_B, SEL_LBS_1),
904 PINMUX_IPSR_MODSEL_DATA(IP2_20_19, SCL1, SEL_IIC1_0),
905 PINMUX_IPSR_DATA(IP2_22_21, CS1_N_A26),
906 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, ATADIR0_N_B, SEL_LBS_1),
907 PINMUX_IPSR_MODSEL_DATA(IP2_22_21, SDA1, SEL_IIC1_0),
908 PINMUX_IPSR_DATA(IP2_24_23, EX_CS1_N),
909 PINMUX_IPSR_MODSEL_DATA(IP2_24_23, MSIOF2_SCK, SEL_SOF2_0),
910 PINMUX_IPSR_DATA(IP2_26_25, EX_CS2_N),
911 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, ATAWR0_N, SEL_LBS_0),
912 PINMUX_IPSR_MODSEL_DATA(IP2_26_25, MSIOF2_SYNC, SEL_SOF2_0),
913 PINMUX_IPSR_DATA(IP2_29_27, EX_CS3_N),
914 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATADIR0_N, SEL_LBS_0),
915 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, MSIOF2_TXD, SEL_SOF2_0),
916 PINMUX_IPSR_MODSEL_DATA(IP2_29_27, ATAG0_N, SEL_LBS_0),
917 PINMUX_IPSR_DATA(IP2_29_27, EX_WAIT1),
918
919 /* IPSR3 */
920 PINMUX_IPSR_DATA(IP3_2_0, EX_CS4_N),
921 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, ATARD0_N, SEL_LBS_0),
922 PINMUX_IPSR_MODSEL_DATA(IP3_2_0, MSIOF2_RXD, SEL_SOF2_0),
923 PINMUX_IPSR_DATA(IP3_2_0, EX_WAIT2),
924 PINMUX_IPSR_DATA(IP3_5_3, EX_CS5_N),
925 PINMUX_IPSR_DATA(IP3_5_3, ATACS00_N),
926 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, MSIOF2_SS1, SEL_SOF2_0),
927 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, HRX1_B, SEL_HSCIF1_1),
928 PINMUX_IPSR_MODSEL_DATA(IP3_5_3, SCIFB1_RXD_B, SEL_SCIFB1_1),
929 PINMUX_IPSR_DATA(IP3_5_3, PWM1),
930 PINMUX_IPSR_DATA(IP3_5_3, TPU_TO1),
931 PINMUX_IPSR_DATA(IP3_8_6, BS_N),
932 PINMUX_IPSR_DATA(IP3_8_6, ATACS10_N),
933 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, MSIOF2_SS2, SEL_SOF2_0),
934 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, HTX1_B, SEL_HSCIF1_1),
935 PINMUX_IPSR_MODSEL_DATA(IP3_8_6, SCIFB1_TXD_B, SEL_SCIFB1_1),
936 PINMUX_IPSR_DATA(IP3_8_6, PWM2),
937 PINMUX_IPSR_DATA(IP3_8_6, TPU_TO2),
938 PINMUX_IPSR_DATA(IP3_11_9, RD_WR_N),
939 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, HRX2_B, SEL_HSCIF2_1),
940 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, FMIN_B, SEL_FM_1),
941 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, SCIFB0_RXD_B, SEL_SCIFB_1),
942 PINMUX_IPSR_MODSEL_DATA(IP3_11_9, DREQ1_D, SEL_LBS_1),
943 PINMUX_IPSR_DATA(IP3_13_12, WE0_N),
944 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, HCTS2_N_B, SEL_HSCIF2_1),
945 PINMUX_IPSR_MODSEL_DATA(IP3_13_12, SCIFB0_TXD_B, SEL_SCIFB_1),
946 PINMUX_IPSR_DATA(IP3_15_14, WE1_N),
947 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, ATARD0_N_B, SEL_LBS_1),
948 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, HTX2_B, SEL_HSCIF2_1),
949 PINMUX_IPSR_MODSEL_DATA(IP3_15_14, SCIFB0_RTS_N_B, SEL_SCIFB_1),
950 PINMUX_IPSR_DATA(IP3_17_16, EX_WAIT0),
951 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, HRTS2_N_B, SEL_HSCIF2_1),
952 PINMUX_IPSR_MODSEL_DATA(IP3_17_16, SCIFB0_CTS_N_B, SEL_SCIFB_1),
953 PINMUX_IPSR_DATA(IP3_19_18, DREQ0),
954 PINMUX_IPSR_DATA(IP3_19_18, PWM3),
955 PINMUX_IPSR_DATA(IP3_19_18, TPU_TO3),
956 PINMUX_IPSR_DATA(IP3_21_20, DACK0),
957 PINMUX_IPSR_DATA(IP3_21_20, DRACK0),
958 PINMUX_IPSR_MODSEL_DATA(IP3_21_20, REMOCON, SEL_RCN_0),
959 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SPEEDIN, SEL_RSP_0),
960 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK0_C, SEL_HSCIF0_2),
961 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, HSCK2_C, SEL_HSCIF2_2),
962 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB0_SCK_B, SEL_SCIFB_1),
963 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, SCIFB2_SCK_B, SEL_SCIFB2_1),
964 PINMUX_IPSR_MODSEL_DATA(IP3_24_22, DREQ2_C, SEL_LBS_2),
965 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
966 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SSI_SCK0129, SEL_SSI0_0),
967 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX0_C, SEL_HSCIF0_2),
968 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, HRX2_C, SEL_HSCIF2_2),
969 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB0_RXD_C, SEL_SCIFB_2),
970 PINMUX_IPSR_MODSEL_DATA(IP3_27_25, SCIFB2_RXD_C, SEL_SCIFB2_2),
971 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SSI_WS0129, SEL_SSI0_0),
972 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX0_C, SEL_HSCIF0_2),
973 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, HTX2_C, SEL_HSCIF2_2),
974 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB0_TXD_C, SEL_SCIFB_2),
975 PINMUX_IPSR_MODSEL_DATA(IP3_30_28, SCIFB2_TXD_C, SEL_SCIFB2_2),
976
977 /* IPSR4 */
978 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SSI_SDATA0, SEL_SSI0_0),
979 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL0_B, SEL_IIC0_1),
980 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, SCL7_B, SEL_IIC7_1),
981 PINMUX_IPSR_MODSEL_DATA(IP4_1_0, MSIOF2_SCK_C, SEL_SOF2_2),
982 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SSI_SCK1, SEL_SSI1_0),
983 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA0_B, SEL_IIC0_1),
984 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, SDA7_B, SEL_IIC7_1),
985 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, MSIOF2_SYNC_C, SEL_SOF2_2),
986 PINMUX_IPSR_MODSEL_DATA(IP4_4_2, GLO_I0_D, SEL_GPS_3),
987 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SSI_WS1, SEL_SSI1_0),
988 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL1_B, SEL_IIC1_1),
989 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, SCL8_B, SEL_IIC8_1),
990 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, MSIOF2_TXD_C, SEL_SOF2_2),
991 PINMUX_IPSR_MODSEL_DATA(IP4_7_5, GLO_I1_D, SEL_GPS_3),
992 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SSI_SDATA1, SEL_SSI1_0),
993 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA1_B, SEL_IIC1_1),
994 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, SDA8_B, SEL_IIC8_1),
995 PINMUX_IPSR_MODSEL_DATA(IP4_9_8, MSIOF2_RXD_C, SEL_SOF2_2),
996 PINMUX_IPSR_DATA(IP4_12_10, SSI_SCK2),
997 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, SCL2, SEL_IIC2_0),
998 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GPS_CLK_B, SEL_GPS_1),
999 PINMUX_IPSR_MODSEL_DATA(IP4_12_10, GLO_Q0_D, SEL_GPS_3),
1000 PINMUX_IPSR_DATA(IP4_15_13, SSI_WS2),
1001 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, SDA2, SEL_IIC2_0),
1002 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GPS_SIGN_B, SEL_GPS_1),
1003 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, RX2_E, SEL_SCIF2_4),
1004 PINMUX_IPSR_MODSEL_DATA(IP4_15_13, GLO_Q1_D, SEL_GPS_3),
1005 PINMUX_IPSR_DATA(IP4_18_16, SSI_SDATA2),
1006 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, GPS_MAG_B, SEL_GPS_1),
1007 PINMUX_IPSR_MODSEL_DATA(IP4_18_16, TX2_E, SEL_SCIF2_4),
1008 PINMUX_IPSR_DATA(IP4_19, SSI_SCK34),
1009 PINMUX_IPSR_DATA(IP4_20, SSI_WS34),
1010 PINMUX_IPSR_DATA(IP4_21, SSI_SDATA3),
1011 PINMUX_IPSR_DATA(IP4_23_22, SSI_SCK4),
1012 PINMUX_IPSR_MODSEL_DATA(IP4_23_22, GLO_SS_D, SEL_GPS_3),
1013 PINMUX_IPSR_DATA(IP4_25_24, SSI_WS4),
1014 PINMUX_IPSR_MODSEL_DATA(IP4_25_24, GLO_RFON_D, SEL_GPS_3),
1015 PINMUX_IPSR_DATA(IP4_27_26, SSI_SDATA4),
1016 PINMUX_IPSR_MODSEL_DATA(IP4_27_26, MSIOF2_SCK_D, SEL_SOF2_3),
1017 PINMUX_IPSR_DATA(IP4_30_28, SSI_SCK5),
1018 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF1_SCK_C, SEL_SOF1_2),
1019 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, TS_SDATA0, SEL_TSIF0_0),
1020 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, GLO_I0, SEL_GPS_0),
1021 PINMUX_IPSR_MODSEL_DATA(IP4_30_28, MSIOF2_SYNC_D, SEL_SOF2_3),
1022 PINMUX_IPSR_DATA(IP4_30_28, VI1_R2_B),
1023
1024 /* IPSR5 */
1025 PINMUX_IPSR_DATA(IP5_2_0, SSI_WS5),
1026 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF1_SYNC_C, SEL_SOF1_2),
1027 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, TS_SCK0, SEL_TSIF0_0),
1028 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, GLO_I1, SEL_GPS_0),
1029 PINMUX_IPSR_MODSEL_DATA(IP5_2_0, MSIOF2_TXD_D, SEL_SOF2_3),
1030 PINMUX_IPSR_DATA(IP5_2_0, VI1_R3_B),
1031 PINMUX_IPSR_DATA(IP5_5_3, SSI_SDATA5),
1032 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF1_TXD_C, SEL_SOF1_2),
1033 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, TS_SDEN0, SEL_TSIF0_0),
1034 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, GLO_Q0, SEL_GPS_0),
1035 PINMUX_IPSR_MODSEL_DATA(IP5_5_3, MSIOF2_SS1_D, SEL_SOF2_3),
1036 PINMUX_IPSR_DATA(IP5_5_3, VI1_R4_B),
1037 PINMUX_IPSR_DATA(IP5_8_6, SSI_SCK6),
1038 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF1_RXD_C, SEL_SOF1_2),
1039 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, TS_SPSYNC0, SEL_TSIF0_0),
1040 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, GLO_Q1, SEL_GPS_0),
1041 PINMUX_IPSR_MODSEL_DATA(IP5_8_6, MSIOF2_RXD_D, SEL_SOF2_3),
1042 PINMUX_IPSR_DATA(IP5_8_6, VI1_R5_B),
1043 PINMUX_IPSR_DATA(IP5_11_9, SSI_WS6),
1044 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, GLO_SCLK, SEL_GPS_0),
1045 PINMUX_IPSR_MODSEL_DATA(IP5_11_9, MSIOF2_SS2_D, SEL_SOF2_3),
1046 PINMUX_IPSR_DATA(IP5_11_9, VI1_R6_B),
1047 PINMUX_IPSR_DATA(IP5_14_12, SSI_SDATA6),
1048 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, STP_IVCXO27_0_B, SEL_SSP_1),
1049 PINMUX_IPSR_MODSEL_DATA(IP5_14_12, GLO_SDATA, SEL_GPS_0),
1050 PINMUX_IPSR_DATA(IP5_14_12, VI1_R7_B),
1051 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, SSI_SCK78, SEL_SSI7_0),
1052 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, STP_ISCLK_0_B, SEL_SSP_1),
1053 PINMUX_IPSR_MODSEL_DATA(IP5_16_15, GLO_SS, SEL_GPS_0),
1054 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, SSI_WS78, SEL_SSI7_0),
1055 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, TX0_D, SEL_SCIF0_3),
1056 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, STP_ISD_0_B, SEL_SSP_1),
1057 PINMUX_IPSR_MODSEL_DATA(IP5_19_17, GLO_RFON, SEL_GPS_0),
1058 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, SSI_SDATA7, SEL_SSI7_0),
1059 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, RX0_D, SEL_SCIF0_3),
1060 PINMUX_IPSR_MODSEL_DATA(IP5_21_20, STP_ISEN_0_B, SEL_SSP_1),
1061 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, SSI_SDATA8, SEL_SSI8_0),
1062 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, TX1_D, SEL_SCIF1_3),
1063 PINMUX_IPSR_MODSEL_DATA(IP5_23_22, STP_ISSYNC_0_B, SEL_SSP_1),
1064 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, SSI_SCK9, SEL_SSI9_0),
1065 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, RX1_D, SEL_SCIF1_3),
1066 PINMUX_IPSR_MODSEL_DATA(IP5_25_24, GLO_SCLK_D, SEL_GPS_3),
1067 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, SSI_WS9, SEL_SSI9_0),
1068 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, TX3_D, SEL_SCIF3_3),
1069 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, CAN0_TX_D, SEL_CAN0_3),
1070 PINMUX_IPSR_MODSEL_DATA(IP5_28_26, GLO_SDATA_D, SEL_GPS_3),
1071 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, SSI_SDATA9, SEL_SSI9_0),
1072 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, RX3_D, SEL_SCIF3_3),
1073 PINMUX_IPSR_MODSEL_DATA(IP5_31_29, CAN0_RX_D, SEL_CAN0_3),
1074
1075 /* IPSR6 */
1076 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, AUDIO_CLKB, SEL_ADG_0),
1077 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, STP_OPWM_0_B, SEL_SSP_1),
1078 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, MSIOF1_SCK_B, SEL_SOF1_1),
1079 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, SCIF_CLK, SEL_SCIF_0),
1080 PINMUX_IPSR_MODSEL_DATA(IP6_2_0, BPFCLK_E, SEL_FM_4),
1081 PINMUX_IPSR_DATA(IP6_5_3, AUDIO_CLKC),
1082 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFB0_SCK_C, SEL_SCIFB_2),
1083 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, MSIOF1_SYNC_B, SEL_SOF1_1),
1084 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, RX2, SEL_SCIF2_0),
1085 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, SCIFA2_RXD, SEL_SCIFA2_0),
1086 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, FMIN_E, SEL_FM_4),
1087 PINMUX_IPSR_DATA(IP6_7_6, AUDIO_CLKOUT),
1088 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, MSIOF1_SS1_B, SEL_SOF1_1),
1089 PINMUX_IPSR_MODSEL_DATA(IP6_5_3, TX2, SEL_SCIF2_0),
1090 PINMUX_IPSR_MODSEL_DATA(IP6_7_6, SCIFA2_TXD, SEL_SCIFA2_0),
1091 PINMUX_IPSR_DATA(IP6_9_8, IRQ0),
1092 PINMUX_IPSR_MODSEL_DATA(IP6_9_8, SCIFB1_RXD_D, SEL_SCIFB1_3),
1093 PINMUX_IPSR_DATA(IP6_9_8, INTC_IRQ0_N),
1094 PINMUX_IPSR_DATA(IP6_11_10, IRQ1),
1095 PINMUX_IPSR_MODSEL_DATA(IP6_11_10, SCIFB1_SCK_C, SEL_SCIFB1_2),
1096 PINMUX_IPSR_DATA(IP6_11_10, INTC_IRQ1_N),
1097 PINMUX_IPSR_DATA(IP6_13_12, IRQ2),
1098 PINMUX_IPSR_MODSEL_DATA(IP6_13_12, SCIFB1_TXD_D, SEL_SCIFB1_3),
1099 PINMUX_IPSR_DATA(IP6_13_12, INTC_IRQ2_N),
1100 PINMUX_IPSR_DATA(IP6_15_14, IRQ3),
1101 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, SCL4_C, SEL_IIC4_2),
1102 PINMUX_IPSR_MODSEL_DATA(IP6_15_14, MSIOF2_TXD_E, SEL_SOF2_4),
1103 PINMUX_IPSR_DATA(IP6_15_14, INTC_IRQ4_N),
1104 PINMUX_IPSR_DATA(IP6_18_16, IRQ4),
1105 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, HRX1_C, SEL_HSCIF1_2),
1106 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, SDA4_C, SEL_IIC4_2),
1107 PINMUX_IPSR_MODSEL_DATA(IP6_18_16, MSIOF2_RXD_E, SEL_SOF2_4),
1108 PINMUX_IPSR_DATA(IP6_18_16, INTC_IRQ4_N),
1109 PINMUX_IPSR_DATA(IP6_20_19, IRQ5),
1110 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, HTX1_C, SEL_HSCIF1_2),
1111 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, SCL1_E, SEL_IIC1_4),
1112 PINMUX_IPSR_MODSEL_DATA(IP6_20_19, MSIOF2_SCK_E, SEL_SOF2_4),
1113 PINMUX_IPSR_DATA(IP6_23_21, IRQ6),
1114 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, HSCK1_C, SEL_HSCIF1_2),
1115 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF1_SS2_B, SEL_SOF1_1),
1116 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, SDA1_E, SEL_IIC1_4),
1117 PINMUX_IPSR_MODSEL_DATA(IP6_23_21, MSIOF2_SYNC_E, SEL_SOF2_4),
1118 PINMUX_IPSR_DATA(IP6_26_24, IRQ7),
1119 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, HCTS1_N_C, SEL_HSCIF1_2),
1120 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, MSIOF1_TXD_B, SEL_SOF1_1),
1121 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_C, SEL_GPS_2),
1122 PINMUX_IPSR_MODSEL_DATA(IP6_26_24, GPS_CLK_D, SEL_GPS_3),
1123 PINMUX_IPSR_DATA(IP6_29_27, IRQ8),
1124 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, HRTS1_N_C, SEL_HSCIF1_2),
1125 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, MSIOF1_RXD_B, SEL_SOF1_1),
1126 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_C, SEL_GPS_2),
1127 PINMUX_IPSR_MODSEL_DATA(IP6_29_27, GPS_SIGN_D, SEL_GPS_3),
1128
1129 /* IPSR7 */
1130 PINMUX_IPSR_DATA(IP7_2_0, IRQ9),
1131 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, DU1_DOTCLKIN_B, SEL_DIS_1),
1132 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, CAN_CLK_D, SEL_CANCLK_3),
1133 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_C, SEL_GPS_2),
1134 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, SCIF_CLK_B, SEL_SCIF_1),
1135 PINMUX_IPSR_MODSEL_DATA(IP7_2_0, GPS_MAG_D, SEL_GPS_3),
1136 PINMUX_IPSR_DATA(IP7_5_3, DU1_DR0),
1137 PINMUX_IPSR_DATA(IP7_5_3, LCDOUT0),
1138 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, VI1_DATA0_B, SEL_VI1_1),
1139 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, TX0_B, SEL_SCIF0_1),
1140 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, SCIFA0_TXD_B, SEL_SCFA_1),
1141 PINMUX_IPSR_MODSEL_DATA(IP7_5_3, MSIOF2_SCK_B, SEL_SOF2_1),
1142 PINMUX_IPSR_DATA(IP7_8_6, DU1_DR1),
1143 PINMUX_IPSR_DATA(IP7_8_6, LCDOUT1),
1144 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, VI1_DATA1_B, SEL_VI1_1),
1145 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, RX0_B, SEL_SCIF0_1),
1146 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, SCIFA0_RXD_B, SEL_SCFA_1),
1147 PINMUX_IPSR_MODSEL_DATA(IP7_8_6, MSIOF2_SYNC_B, SEL_SOF2_1),
1148 PINMUX_IPSR_DATA(IP7_10_9, DU1_DR2),
1149 PINMUX_IPSR_DATA(IP7_10_9, LCDOUT2),
1150 PINMUX_IPSR_MODSEL_DATA(IP7_10_9, SSI_SCK0129_B, SEL_SSI0_1),
1151 PINMUX_IPSR_DATA(IP7_12_11, DU1_DR3),
1152 PINMUX_IPSR_DATA(IP7_12_11, LCDOUT3),
1153 PINMUX_IPSR_MODSEL_DATA(IP7_12_11, SSI_WS0129_B, SEL_SSI0_1),
1154 PINMUX_IPSR_DATA(IP7_14_13, DU1_DR4),
1155 PINMUX_IPSR_DATA(IP7_14_13, LCDOUT4),
1156 PINMUX_IPSR_MODSEL_DATA(IP7_14_13, SSI_SDATA0_B, SEL_SSI0_1),
1157 PINMUX_IPSR_DATA(IP7_16_15, DU1_DR5),
1158 PINMUX_IPSR_DATA(IP7_16_15, LCDOUT5),
1159 PINMUX_IPSR_MODSEL_DATA(IP7_16_15, SSI_SCK1_B, SEL_SSI1_1),
1160 PINMUX_IPSR_DATA(IP7_18_17, DU1_DR6),
1161 PINMUX_IPSR_DATA(IP7_18_17, LCDOUT6),
1162 PINMUX_IPSR_MODSEL_DATA(IP7_18_17, SSI_WS1_B, SEL_SSI1_1),
1163 PINMUX_IPSR_DATA(IP7_20_19, DU1_DR7),
1164 PINMUX_IPSR_DATA(IP7_20_19, LCDOUT7),
1165 PINMUX_IPSR_MODSEL_DATA(IP7_20_19, SSI_SDATA1_B, SEL_SSI1_1),
1166 PINMUX_IPSR_DATA(IP7_23_21, DU1_DG0),
1167 PINMUX_IPSR_DATA(IP7_23_21, LCDOUT8),
1168 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, VI1_DATA2_B, SEL_VI1_1),
1169 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, TX1_B, SEL_SCIF1_1),
1170 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, SCIFA1_TXD_B, SEL_SCIFA1_1),
1171 PINMUX_IPSR_MODSEL_DATA(IP7_23_21, MSIOF2_SS1_B, SEL_SOF2_1),
1172 PINMUX_IPSR_DATA(IP7_26_24, DU1_DG1),
1173 PINMUX_IPSR_DATA(IP7_26_24, LCDOUT9),
1174 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, VI1_DATA3_B, SEL_VI1_1),
1175 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, RX1_B, SEL_SCIF1_1),
1176 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, SCIFA1_RXD_B, SEL_SCIFA1_1),
1177 PINMUX_IPSR_MODSEL_DATA(IP7_26_24, MSIOF2_SS2_B, SEL_SOF2_1),
1178 PINMUX_IPSR_DATA(IP7_29_27, DU1_DG2),
1179 PINMUX_IPSR_DATA(IP7_29_27, LCDOUT10),
1180 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, VI1_DATA4_B, SEL_VI1_1),
1181 PINMUX_IPSR_DATA(IP7_29_27, SCIF1_SCK_B),
1182 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SCIFA1_SCK, SEL_SCIFA1_0),
1183 PINMUX_IPSR_MODSEL_DATA(IP7_29_27, SSI_SCK78_B, SEL_SSI7_1),
1184
1185 /* IPSR8 */
1186 PINMUX_IPSR_DATA(IP8_2_0, DU1_DG3),
1187 PINMUX_IPSR_DATA(IP8_2_0, LCDOUT11),
1188 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, VI1_DATA5_B, SEL_VI1_1),
1189 PINMUX_IPSR_MODSEL_DATA(IP8_2_0, SSI_WS78_B, SEL_SSI7_1),
1190 PINMUX_IPSR_DATA(IP8_5_3, DU1_DG4),
1191 PINMUX_IPSR_DATA(IP8_5_3, LCDOUT12),
1192 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, VI1_DATA6_B, SEL_VI1_1),
1193 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, HRX0_B, SEL_HSCIF0_1),
1194 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SCIFB2_RXD_B, SEL_SCIFB2_1),
1195 PINMUX_IPSR_MODSEL_DATA(IP8_5_3, SSI_SDATA7_B, SEL_SSI7_1),
1196 PINMUX_IPSR_DATA(IP8_8_6, DU1_DG5),
1197 PINMUX_IPSR_DATA(IP8_8_6, LCDOUT13),
1198 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, VI1_DATA7_B, SEL_VI1_1),
1199 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, HCTS0_N_B, SEL_HSCIF0_1),
1200 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SCIFB2_TXD_B, SEL_SCIFB2_1),
1201 PINMUX_IPSR_MODSEL_DATA(IP8_8_6, SSI_SDATA8_B, SEL_SSI8_1),
1202 PINMUX_IPSR_DATA(IP8_11_9, DU1_DG6),
1203 PINMUX_IPSR_DATA(IP8_11_9, LCDOUT14),
1204 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, HRTS0_N_B, SEL_HSCIF0_1),
1205 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SCIFB2_CTS_N_B, SEL_SCIFB2_1),
1206 PINMUX_IPSR_MODSEL_DATA(IP8_11_9, SSI_SCK9_B, SEL_SSI9_1),
1207 PINMUX_IPSR_DATA(IP8_14_12, DU1_DG7),
1208 PINMUX_IPSR_DATA(IP8_14_12, LCDOUT15),
1209 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, HTX0_B, SEL_HSCIF0_1),
1210 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SCIFB2_RTS_N_B, SEL_SCIFB2_1),
1211 PINMUX_IPSR_MODSEL_DATA(IP8_14_12, SSI_WS9_B, SEL_SSI9_1),
1212 PINMUX_IPSR_DATA(IP8_17_15, DU1_DB0),
1213 PINMUX_IPSR_DATA(IP8_17_15, LCDOUT16),
1214 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, VI1_CLK_B, SEL_VI1_1),
1215 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, TX2_B, SEL_SCIF2_1),
1216 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, SCIFA2_TXD_B, SEL_SCIFA2_1),
1217 PINMUX_IPSR_MODSEL_DATA(IP8_17_15, MSIOF2_TXD_B, SEL_SOF2_1),
1218 PINMUX_IPSR_DATA(IP8_20_18, DU1_DB1),
1219 PINMUX_IPSR_DATA(IP8_20_18, LCDOUT17),
1220 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, VI1_HSYNC_N_B, SEL_VI1_1),
1221 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, RX2_B, SEL_SCIF2_1),
1222 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, SCIFA2_RXD_B, SEL_SCIFA2_1),
1223 PINMUX_IPSR_MODSEL_DATA(IP8_20_18, MSIOF2_RXD_B, SEL_SOF2_1),
1224 PINMUX_IPSR_DATA(IP8_23_21, DU1_DB2),
1225 PINMUX_IPSR_DATA(IP8_23_21, LCDOUT18),
1226 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, VI1_VSYNC_N_B, SEL_VI1_1),
1227 PINMUX_IPSR_DATA(IP8_23_21, SCIF2_SCK_B),
1228 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SCIFA2_SCK, SEL_SCIFA2_1),
1229 PINMUX_IPSR_MODSEL_DATA(IP8_23_21, SSI_SDATA9_B, SEL_SSI9_1),
1230 PINMUX_IPSR_DATA(IP8_25_24, DU1_DB3),
1231 PINMUX_IPSR_DATA(IP8_25_24, LCDOUT19),
1232 PINMUX_IPSR_MODSEL_DATA(IP8_25_24, VI1_CLKENB_B, SEL_VI1_1),
1233 PINMUX_IPSR_DATA(IP8_27_26, DU1_DB4),
1234 PINMUX_IPSR_DATA(IP8_27_26, LCDOUT20),
1235 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, VI1_FIELD_B, SEL_VI1_1),
1236 PINMUX_IPSR_MODSEL_DATA(IP8_27_26, CAN1_RX, SEL_CAN1_0),
1237 PINMUX_IPSR_DATA(IP8_30_28, DU1_DB5),
1238 PINMUX_IPSR_DATA(IP8_30_28, LCDOUT21),
1239 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, TX3, SEL_SCIF3_0),
1240 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, SCIFA3_TXD, SEL_SCIFA3_0),
1241 PINMUX_IPSR_MODSEL_DATA(IP8_30_28, CAN1_TX, SEL_CAN1_0),
1242
1243 /* IPSR9 */
1244 PINMUX_IPSR_DATA(IP9_2_0, DU1_DB6),
1245 PINMUX_IPSR_DATA(IP9_2_0, LCDOUT22),
1246 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCL3_C, SEL_IIC3_2),
1247 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, RX3, SEL_SCIF3_0),
1248 PINMUX_IPSR_MODSEL_DATA(IP9_2_0, SCIFA3_RXD, SEL_SCIFA3_0),
1249 PINMUX_IPSR_DATA(IP9_5_3, DU1_DB7),
1250 PINMUX_IPSR_DATA(IP9_5_3, LCDOUT23),
1251 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SDA3_C, SEL_IIC3_2),
1252 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIF3_SCK, SEL_SCIF3_0),
1253 PINMUX_IPSR_MODSEL_DATA(IP9_5_3, SCIFA3_SCK, SEL_SCIFA3_0),
1254 PINMUX_IPSR_MODSEL_DATA(IP9_6, DU1_DOTCLKIN, SEL_DIS_0),
1255 PINMUX_IPSR_DATA(IP9_6, QSTVA_QVS),
1256 PINMUX_IPSR_DATA(IP9_7, DU1_DOTCLKOUT0),
1257 PINMUX_IPSR_DATA(IP9_7, QCLK),
1258 PINMUX_IPSR_DATA(IP9_10_8, DU1_DOTCLKOUT1),
1259 PINMUX_IPSR_DATA(IP9_10_8, QSTVB_QVE),
1260 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, CAN0_TX, SEL_CAN0_0),
1261 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, TX3_B, SEL_SCIF3_1),
1262 PINMUX_IPSR_MODSEL_DATA(IP9_10_8, SCL2_B, SEL_IIC2_1),
1263 PINMUX_IPSR_DATA(IP9_10_8, PWM4),
1264 PINMUX_IPSR_DATA(IP9_11, DU1_EXHSYNC_DU1_HSYNC),
1265 PINMUX_IPSR_DATA(IP9_11, QSTH_QHS),
1266 PINMUX_IPSR_DATA(IP9_12, DU1_EXVSYNC_DU1_VSYNC),
1267 PINMUX_IPSR_DATA(IP9_12, QSTB_QHE),
1268 PINMUX_IPSR_DATA(IP9_15_13, DU1_EXODDF_DU1_ODDF_DISP_CDE),
1269 PINMUX_IPSR_DATA(IP9_15_13, QCPV_QDE),
1270 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, CAN0_RX, SEL_CAN0_0),
1271 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, RX3_B, SEL_SCIF3_1),
1272 PINMUX_IPSR_MODSEL_DATA(IP9_15_13, SDA2_B, SEL_IIC2_1),
1273 PINMUX_IPSR_DATA(IP9_16, DU1_DISP),
1274 PINMUX_IPSR_DATA(IP9_16, QPOLA),
1275 PINMUX_IPSR_DATA(IP9_18_17, DU1_CDE),
1276 PINMUX_IPSR_DATA(IP9_18_17, QPOLB),
1277 PINMUX_IPSR_DATA(IP9_18_17, PWM4_B),
1278 PINMUX_IPSR_DATA(IP9_20_19, VI0_CLKENB),
1279 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TX4, SEL_SCIF4_0),
1280 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, SCIFA4_TXD, SEL_SCIFA4_0),
1281 PINMUX_IPSR_MODSEL_DATA(IP9_20_19, TS_SDATA0_D, SEL_TSIF0_3),
1282 PINMUX_IPSR_DATA(IP9_22_21, VI0_FIELD),
1283 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, RX4, SEL_SCIF4_0),
1284 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, SCIFA4_RXD, SEL_SCIFA4_0),
1285 PINMUX_IPSR_MODSEL_DATA(IP9_22_21, TS_SCK0_D, SEL_TSIF0_3),
1286 PINMUX_IPSR_DATA(IP9_24_23, VI0_HSYNC_N),
1287 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TX5, SEL_SCIF5_0),
1288 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, SCIFA5_TXD, SEL_SCIFA5_0),
1289 PINMUX_IPSR_MODSEL_DATA(IP9_24_23, TS_SDEN0_D, SEL_TSIF0_3),
1290 PINMUX_IPSR_DATA(IP9_26_25, VI0_VSYNC_N),
1291 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, RX5, SEL_SCIF5_0),
1292 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, SCIFA5_RXD, SEL_SCIFA5_0),
1293 PINMUX_IPSR_MODSEL_DATA(IP9_26_25, TS_SPSYNC0_D, SEL_TSIF0_3),
1294 PINMUX_IPSR_DATA(IP9_28_27, VI0_DATA3_VI0_B3),
1295 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIF3_SCK_B, SEL_SCIF3_1),
1296 PINMUX_IPSR_MODSEL_DATA(IP9_28_27, SCIFA3_SCK_B, SEL_SCIFA3_1),
1297 PINMUX_IPSR_DATA(IP9_31_29, VI0_G0),
1298 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL8, SEL_IIC8_0),
1299 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, STP_IVCXO27_0_C, SEL_SSP_2),
1300 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCL4, SEL_IIC4_0),
1301 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, HCTS2_N, SEL_HSCIF2_0),
1302 PINMUX_IPSR_MODSEL_DATA(IP9_31_29, SCIFB2_CTS_N, SEL_SCIFB2_0),
1303 PINMUX_IPSR_DATA(IP9_31_29, ATAWR1_N),
1304
1305 /* IPSR10 */
1306 PINMUX_IPSR_DATA(IP10_2_0, VI0_G1),
1307 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA8, SEL_IIC8_0),
1308 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, STP_ISCLK_0_C, SEL_SSP_2),
1309 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SDA4, SEL_IIC4_0),
1310 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, HRTS2_N, SEL_HSCIF2_0),
1311 PINMUX_IPSR_MODSEL_DATA(IP10_2_0, SCIFB2_RTS_N, SEL_SCIFB2_0),
1312 PINMUX_IPSR_DATA(IP10_2_0, ATADIR1_N),
1313 PINMUX_IPSR_DATA(IP10_5_3, VI0_G2),
1314 PINMUX_IPSR_DATA(IP10_5_3, VI2_HSYNC_N),
1315 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, STP_ISD_0_C, SEL_SSP_2),
1316 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCL3_B, SEL_IIC3_1),
1317 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, HSCK2, SEL_HSCIF2_0),
1318 PINMUX_IPSR_MODSEL_DATA(IP10_5_3, SCIFB2_SCK, SEL_SCIFB2_0),
1319 PINMUX_IPSR_DATA(IP10_5_3, ATARD1_N),
1320 PINMUX_IPSR_DATA(IP10_8_6, VI0_G3),
1321 PINMUX_IPSR_DATA(IP10_8_6, VI2_VSYNC_N),
1322 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, STP_ISEN_0_C, SEL_SSP_2),
1323 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SDA3_B, SEL_IIC3_1),
1324 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, HRX2, SEL_HSCIF2_0),
1325 PINMUX_IPSR_MODSEL_DATA(IP10_8_6, SCIFB2_RXD, SEL_SCIFB2_0),
1326 PINMUX_IPSR_DATA(IP10_8_6, ATACS01_N),
1327 PINMUX_IPSR_DATA(IP10_11_9, VI0_G4),
1328 PINMUX_IPSR_DATA(IP10_11_9, VI2_CLKENB),
1329 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, STP_ISSYNC_0_C, SEL_SSP_2),
1330 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, HTX2, SEL_HSCIF2_0),
1331 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB2_TXD, SEL_SCIFB2_0),
1332 PINMUX_IPSR_MODSEL_DATA(IP10_11_9, SCIFB0_SCK_D, SEL_SCIFB_3),
1333 PINMUX_IPSR_DATA(IP10_14_12, VI0_G5),
1334 PINMUX_IPSR_DATA(IP10_14_12, VI2_FIELD),
1335 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, STP_OPWM_0_C, SEL_SSP_2),
1336 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, FMCLK_D, SEL_FM_3),
1337 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, CAN0_TX_E, SEL_CAN0_4),
1338 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, HTX1_D, SEL_HSCIF1_3),
1339 PINMUX_IPSR_MODSEL_DATA(IP10_14_12, SCIFB0_TXD_D, SEL_SCIFB_3),
1340 PINMUX_IPSR_DATA(IP10_16_15, VI0_G6),
1341 PINMUX_IPSR_DATA(IP10_16_15, VI2_CLK),
1342 PINMUX_IPSR_MODSEL_DATA(IP10_16_15, BPFCLK_D, SEL_FM_3),
1343 PINMUX_IPSR_DATA(IP10_18_17, VI0_G7),
1344 PINMUX_IPSR_DATA(IP10_18_17, VI2_DATA0),
1345 PINMUX_IPSR_MODSEL_DATA(IP10_18_17, FMIN_D, SEL_FM_3),
1346 PINMUX_IPSR_DATA(IP10_21_19, VI0_R0),
1347 PINMUX_IPSR_DATA(IP10_21_19, VI2_DATA1),
1348 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, GLO_I0_B, SEL_GPS_1),
1349 PINMUX_IPSR_MODSEL_DATA(IP10_21_19, TS_SDATA0_C, SEL_TSIF0_2),
1350 PINMUX_IPSR_DATA(IP10_21_19, ATACS11_N),
1351 PINMUX_IPSR_DATA(IP10_24_22, VI0_R1),
1352 PINMUX_IPSR_DATA(IP10_24_22, VI2_DATA2),
1353 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, GLO_I1_B, SEL_GPS_1),
1354 PINMUX_IPSR_MODSEL_DATA(IP10_24_22, TS_SCK0_C, SEL_TSIF0_2),
1355 PINMUX_IPSR_DATA(IP10_24_22, ATAG1_N),
1356 PINMUX_IPSR_DATA(IP10_26_25, VI0_R2),
1357 PINMUX_IPSR_DATA(IP10_26_25, VI2_DATA3),
1358 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, GLO_Q0_B, SEL_GPS_1),
1359 PINMUX_IPSR_MODSEL_DATA(IP10_26_25, TS_SDEN0_C, SEL_TSIF0_2),
1360 PINMUX_IPSR_DATA(IP10_28_27, VI0_R3),
1361 PINMUX_IPSR_DATA(IP10_28_27, VI2_DATA4),
1362 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, GLO_Q1_B, SEL_GPS_1),
1363 PINMUX_IPSR_MODSEL_DATA(IP10_28_27, TS_SPSYNC0_C, SEL_TSIF0_2),
1364 PINMUX_IPSR_DATA(IP10_31_29, VI0_R4),
1365 PINMUX_IPSR_DATA(IP10_31_29, VI2_DATA5),
1366 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, GLO_SCLK_B, SEL_GPS_1),
1367 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, TX0_C, SEL_SCIF0_2),
1368 PINMUX_IPSR_MODSEL_DATA(IP10_31_29, SCL1_D, SEL_IIC1_3),
1369
1370 /* IPSR11 */
1371 PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
1372 PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
1373 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
1374 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
1375 PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
1376 PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
1377 PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
1378 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
1379 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
1380 PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
1381 PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
1382 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
1383 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
1384 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
1385 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
1386 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
1387 PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
1388 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
1389 PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
1390 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
1391 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
1392 PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
1393 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
1394 PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
1395 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
1396 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
1397 PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
1398 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
1399 PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
1400 PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
1401 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
1402 PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
1403 PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
1404 PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
1405 PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
1406 PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
1407 PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
1408 PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
1409 PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
1410 PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
1411 PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
1412 PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
1413 PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
1414 PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
1415 PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
1416 PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
1417 PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
1418 PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
1419 PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
1420 PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
1421 PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
1422 PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
1423 PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
1424 PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
1425 PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
1426 PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
1427 PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
1428
1429 /* IPSR12 */
1430 PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
1431 PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
1432 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
1433 PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
1434 PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
1435 PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
1436 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
1437 PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
1438 PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
1439 PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
1440 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
1441 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
1442 PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
1443 PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
1444 PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
1445 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
1446 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
1447 PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
1448 PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
1449 PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
1450 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
1451 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
1452 PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
1453 PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
1454 PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
1455 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
1456 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
1457 PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
1458 PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
1459 PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
1460 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
1461 PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
1462 PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
1463 PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
1464 PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
1465 PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
1466 PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
1467 PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
1468 PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
1469 PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
1470 PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
1471 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
1472 PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
1473 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
1474 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
1475 PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
1476 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
1477 PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
1478 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
1479 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
1480 PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
1481
1482 /* IPSR13 */
1483 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, STP_ISD_0, SEL_SSP_0),
1484 PINMUX_IPSR_DATA(IP13_2_0, AVB_TX_ER),
1485 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, SCIFB2_SCK_C, SEL_SCIFB2_2),
1486 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, ADICLK_B, SEL_RAD_1),
1487 PINMUX_IPSR_MODSEL_DATA(IP13_2_0, MSIOF0_SS1_C, SEL_SOF0_2),
1488 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, STP_ISEN_0, SEL_SSP_0),
1489 PINMUX_IPSR_DATA(IP13_4_3, AVB_TX_CLK),
1490 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, ADICHS0_B, SEL_RAD_1),
1491 PINMUX_IPSR_MODSEL_DATA(IP13_4_3, MSIOF0_SS2_C, SEL_SOF0_2),
1492 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, STP_ISSYNC_0, SEL_SSP_0),
1493 PINMUX_IPSR_DATA(IP13_6_5, AVB_COL),
1494 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, ADICHS1_B, SEL_RAD_1),
1495 PINMUX_IPSR_MODSEL_DATA(IP13_6_5, MSIOF0_RXD_C, SEL_SOF0_2),
1496 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, STP_OPWM_0, SEL_SSP_0),
1497 PINMUX_IPSR_DATA(IP13_9_7, AVB_GTX_CLK),
1498 PINMUX_IPSR_DATA(IP13_9_7, PWM0_B),
1499 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, ADICHS2_B, SEL_RAD_1),
1500 PINMUX_IPSR_MODSEL_DATA(IP13_9_7, MSIOF0_TXD_C, SEL_SOF0_2),
1501 PINMUX_IPSR_DATA(IP13_10, SD0_CLK),
1502 PINMUX_IPSR_MODSEL_DATA(IP13_10, SPCLK_B, SEL_QSP_1),
1503 PINMUX_IPSR_DATA(IP13_11, SD0_CMD),
1504 PINMUX_IPSR_MODSEL_DATA(IP13_11, MOSI_IO0_B, SEL_QSP_1),
1505 PINMUX_IPSR_DATA(IP13_12, SD0_DATA0),
1506 PINMUX_IPSR_MODSEL_DATA(IP13_12, MISO_IO1_B, SEL_QSP_1),
1507 PINMUX_IPSR_DATA(IP13_13, SD0_DATA1),
1508 PINMUX_IPSR_MODSEL_DATA(IP13_13, IO2_B, SEL_QSP_1),
1509 PINMUX_IPSR_DATA(IP13_14, SD0_DATA2),
1510 PINMUX_IPSR_MODSEL_DATA(IP13_14, IO3_B, SEL_QSP_1),
1511 PINMUX_IPSR_DATA(IP13_15, SD0_DATA3),
1512 PINMUX_IPSR_MODSEL_DATA(IP13_15, SSL_B, SEL_QSP_1),
1513 PINMUX_IPSR_DATA(IP13_18_16, SD0_CD),
1514 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, MMC_D6_B, SEL_MMC_1),
1515 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SIM0_RST_B, SEL_SIM_1),
1516 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, CAN0_RX_F, SEL_CAN0_5),
1517 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, SCIFA5_TXD_B, SEL_SCIFA5_1),
1518 PINMUX_IPSR_MODSEL_DATA(IP13_18_16, TX3_C, SEL_SCIF3_2),
1519 PINMUX_IPSR_DATA(IP13_21_19, SD0_WP),
1520 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, MMC_D7_B, SEL_MMC_1),
1521 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SIM0_D_B, SEL_SIM_1),
1522 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, CAN0_TX_F, SEL_CAN0_5),
1523 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, SCIFA5_RXD_B, SEL_SCIFA5_1),
1524 PINMUX_IPSR_MODSEL_DATA(IP13_21_19, RX3_C, SEL_SCIF3_2),
1525 PINMUX_IPSR_DATA(IP13_22, SD1_CMD),
1526 PINMUX_IPSR_MODSEL_DATA(IP13_22, REMOCON_B, SEL_RCN_1),
1527 PINMUX_IPSR_DATA(IP13_24_23, SD1_DATA0),
1528 PINMUX_IPSR_MODSEL_DATA(IP13_24_23, SPEEDIN_B, SEL_RSP_1),
1529 PINMUX_IPSR_DATA(IP13_25, SD1_DATA1),
1530 PINMUX_IPSR_MODSEL_DATA(IP13_25, IETX_B, SEL_IEB_1),
1531 PINMUX_IPSR_DATA(IP13_26, SD1_DATA2),
1532 PINMUX_IPSR_MODSEL_DATA(IP13_26, IECLK_B, SEL_IEB_1),
1533 PINMUX_IPSR_DATA(IP13_27, SD1_DATA3),
1534 PINMUX_IPSR_MODSEL_DATA(IP13_27, IERX_B, SEL_IEB_1),
1535 PINMUX_IPSR_DATA(IP13_30_28, SD1_CD),
1536 PINMUX_IPSR_DATA(IP13_30_28, PWM0),
1537 PINMUX_IPSR_DATA(IP13_30_28, TPU_TO0),
1538 PINMUX_IPSR_MODSEL_DATA(IP13_30_28, SCL1_C, SEL_IIC1_2),
1539
1540 /* IPSR14 */
1541 PINMUX_IPSR_DATA(IP14_1_0, SD1_WP),
1542 PINMUX_IPSR_DATA(IP14_1_0, PWM1_B),
1543 PINMUX_IPSR_MODSEL_DATA(IP14_1_0, SDA1_C, SEL_IIC1_2),
1544 PINMUX_IPSR_DATA(IP14_2, SD2_CLK),
1545 PINMUX_IPSR_DATA(IP14_2, MMC_CLK),
1546 PINMUX_IPSR_DATA(IP14_3, SD2_CMD),
1547 PINMUX_IPSR_DATA(IP14_3, MMC_CMD),
1548 PINMUX_IPSR_DATA(IP14_4, SD2_DATA0),
1549 PINMUX_IPSR_DATA(IP14_4, MMC_D0),
1550 PINMUX_IPSR_DATA(IP14_5, SD2_DATA1),
1551 PINMUX_IPSR_DATA(IP14_5, MMC_D1),
1552 PINMUX_IPSR_DATA(IP14_6, SD2_DATA2),
1553 PINMUX_IPSR_DATA(IP14_6, MMC_D2),
1554 PINMUX_IPSR_DATA(IP14_7, SD2_DATA3),
1555 PINMUX_IPSR_DATA(IP14_7, MMC_D3),
1556 PINMUX_IPSR_DATA(IP14_10_8, SD2_CD),
1557 PINMUX_IPSR_DATA(IP14_10_8, MMC_D4),
1558 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCL8_C, SEL_IIC8_2),
1559 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, TX5_B, SEL_SCIF5_1),
1560 PINMUX_IPSR_MODSEL_DATA(IP14_10_8, SCIFA5_TXD_C, SEL_SCIFA5_2),
1561 PINMUX_IPSR_DATA(IP14_13_11, SD2_WP),
1562 PINMUX_IPSR_DATA(IP14_13_11, MMC_D5),
1563 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SDA8_C, SEL_IIC8_2),
1564 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, RX5_B, SEL_SCIF5_1),
1565 PINMUX_IPSR_MODSEL_DATA(IP14_13_11, SCIFA5_RXD_C, SEL_SCIFA5_2),
1566 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, MSIOF0_SCK, SEL_SOF0_0),
1567 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, RX2_C, SEL_SCIF2_2),
1568 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, ADIDATA, SEL_RAD_0),
1569 PINMUX_IPSR_MODSEL_DATA(IP14_16_14, VI1_CLK_C, SEL_VI1_2),
1570 PINMUX_IPSR_DATA(IP14_16_14, VI1_G0_B),
1571 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, MSIOF0_SYNC, SEL_SOF0_0),
1572 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, TX2_C, SEL_SCIF2_2),
1573 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, ADICS_SAMP, SEL_RAD_0),
1574 PINMUX_IPSR_MODSEL_DATA(IP14_19_17, VI1_CLKENB_C, SEL_VI1_2),
1575 PINMUX_IPSR_DATA(IP14_19_17, VI1_G1_B),
1576 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, MSIOF0_TXD, SEL_SOF0_0),
1577 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, ADICLK, SEL_RAD_0),
1578 PINMUX_IPSR_MODSEL_DATA(IP14_22_20, VI1_FIELD_C, SEL_VI1_2),
1579 PINMUX_IPSR_DATA(IP14_22_20, VI1_G2_B),
1580 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, MSIOF0_RXD, SEL_SOF0_0),
1581 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, ADICHS0, SEL_RAD_0),
1582 PINMUX_IPSR_MODSEL_DATA(IP14_25_23, VI1_DATA0_C, SEL_VI1_2),
1583 PINMUX_IPSR_DATA(IP14_25_23, VI1_G3_B),
1584 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MSIOF0_SS1, SEL_SOF0_0),
1585 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, MMC_D6, SEL_MMC_0),
1586 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, ADICHS1, SEL_RAD_0),
1587 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, TX0_E, SEL_SCIF0_4),
1588 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, VI1_HSYNC_N_C, SEL_VI1_2),
1589 PINMUX_IPSR_MODSEL_DATA(IP14_28_26, SCL7_C, SEL_IIC7_2),
1590 PINMUX_IPSR_DATA(IP14_28_26, VI1_G4_B),
1591 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MSIOF0_SS2, SEL_SOF0_0),
1592 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, MMC_D7, SEL_MMC_0),
1593 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, ADICHS2, SEL_RAD_0),
1594 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, RX0_E, SEL_SCIF0_4),
1595 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, VI1_VSYNC_N_C, SEL_VI1_2),
1596 PINMUX_IPSR_MODSEL_DATA(IP14_31_29, SDA7_C, SEL_IIC7_2),
1597 PINMUX_IPSR_DATA(IP14_31_29, VI1_G5_B),
1598
1599 /* IPSR15 */
1600 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, SIM0_RST, SEL_SIM_0),
1601 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, IETX, SEL_IEB_0),
1602 PINMUX_IPSR_MODSEL_DATA(IP15_1_0, CAN1_TX_D, SEL_CAN1_3),
1603 PINMUX_IPSR_DATA(IP15_3_2, SIM0_CLK),
1604 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, IECLK, SEL_IEB_0),
1605 PINMUX_IPSR_MODSEL_DATA(IP15_3_2, CAN_CLK_C, SEL_CANCLK_2),
1606 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, SIM0_D, SEL_SIM_0),
1607 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, IERX, SEL_IEB_0),
1608 PINMUX_IPSR_MODSEL_DATA(IP15_5_4, CAN1_RX_D, SEL_CAN1_3),
1609 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, GPS_CLK, SEL_GPS_0),
1610 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, DU1_DOTCLKIN_C, SEL_DIS_2),
1611 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, AUDIO_CLKB_B, SEL_ADG_1),
1612 PINMUX_IPSR_DATA(IP15_8_6, PWM5_B),
1613 PINMUX_IPSR_MODSEL_DATA(IP15_8_6, SCIFA3_TXD_C, SEL_SCIFA3_2),
1614 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, GPS_SIGN, SEL_GPS_0),
1615 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, TX4_C, SEL_SCIF4_2),
1616 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA4_TXD_C, SEL_SCIFA4_2),
1617 PINMUX_IPSR_DATA(IP15_11_9, PWM5),
1618 PINMUX_IPSR_DATA(IP15_11_9, VI1_G6_B),
1619 PINMUX_IPSR_MODSEL_DATA(IP15_11_9, SCIFA3_RXD_C, SEL_SCIFA3_2),
1620 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, GPS_MAG, SEL_GPS_0),
1621 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, RX4_C, SEL_SCIF4_2),
1622 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA4_RXD_C, SEL_SCIFA4_2),
1623 PINMUX_IPSR_DATA(IP15_14_12, PWM6),
1624 PINMUX_IPSR_DATA(IP15_14_12, VI1_G7_B),
1625 PINMUX_IPSR_MODSEL_DATA(IP15_14_12, SCIFA3_SCK_C, SEL_SCIFA3_2),
1626 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, HCTS0_N, SEL_HSCIF0_0),
1627 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, SCIFB0_CTS_N, SEL_SCIFB_0),
1628 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, GLO_I0_C, SEL_GPS_2),
1629 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, TCLK1, SEL_TMU1_0),
1630 PINMUX_IPSR_MODSEL_DATA(IP15_17_15, VI1_DATA1_C, SEL_VI1_2),
1631 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, HRTS0_N, SEL_HSCIF0_0),
1632 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, SCIFB0_RTS_N, SEL_SCIFB_0),
1633 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, GLO_I1_C, SEL_GPS_2),
1634 PINMUX_IPSR_MODSEL_DATA(IP15_20_18, VI1_DATA2_C, SEL_VI1_2),
1635 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, HSCK0, SEL_HSCIF0_0),
1636 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, SCIFB0_SCK, SEL_SCIFB_0),
1637 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, GLO_Q0_C, SEL_GPS_2),
1638 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, CAN_CLK, SEL_CANCLK_0),
1639 PINMUX_IPSR_DATA(IP15_23_21, TCLK2),
1640 PINMUX_IPSR_MODSEL_DATA(IP15_23_21, VI1_DATA3_C, SEL_VI1_2),
1641 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, HRX0, SEL_HSCIF0_0),
1642 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, SCIFB0_RXD, SEL_SCIFB_0),
1643 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, GLO_Q1_C, SEL_GPS_2),
1644 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, CAN0_RX_B, SEL_CAN0_1),
1645 PINMUX_IPSR_MODSEL_DATA(IP15_26_24, VI1_DATA4_C, SEL_VI1_2),
1646 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, HTX0, SEL_HSCIF0_0),
1647 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, SCIFB0_TXD, SEL_SCIFB_0),
1648 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, GLO_SCLK_C, SEL_GPS_2),
1649 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, CAN0_TX_B, SEL_CAN0_1),
1650 PINMUX_IPSR_MODSEL_DATA(IP15_29_27, VI1_DATA5_C, SEL_VI1_2),
1651
1652 /* IPSR16 */
1653 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, HRX1, SEL_HSCIF1_0),
1654 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, SCIFB1_RXD, SEL_SCIFB1_0),
1655 PINMUX_IPSR_DATA(IP16_2_0, VI1_R0_B),
1656 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, GLO_SDATA_C, SEL_GPS_2),
1657 PINMUX_IPSR_MODSEL_DATA(IP16_2_0, VI1_DATA6_C, SEL_VI1_2),
1658 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, HTX1, SEL_HSCIF1_0),
1659 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, SCIFB1_TXD, SEL_SCIFB1_0),
1660 PINMUX_IPSR_DATA(IP16_5_3, VI1_R1_B),
1661 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, GLO_SS_C, SEL_GPS_2),
1662 PINMUX_IPSR_MODSEL_DATA(IP16_5_3, VI1_DATA7_C, SEL_VI1_2),
1663 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, HSCK1, SEL_HSCIF1_0),
1664 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, SCIFB1_SCK, SEL_SCIFB1_0),
1665 PINMUX_IPSR_DATA(IP16_7_6, MLB_CK),
1666 PINMUX_IPSR_MODSEL_DATA(IP16_7_6, GLO_RFON_C, SEL_GPS_2),
1667 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, HCTS1_N, SEL_HSCIF1_0),
1668 PINMUX_IPSR_DATA(IP16_9_8, SCIFB1_CTS_N),
1669 PINMUX_IPSR_DATA(IP16_9_8, MLB_SIG),
1670 PINMUX_IPSR_MODSEL_DATA(IP16_9_8, CAN1_TX_B, SEL_CAN1_1),
1671 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, HRTS1_N, SEL_HSCIF1_0),
1672 PINMUX_IPSR_DATA(IP16_11_10, SCIFB1_RTS_N),
1673 PINMUX_IPSR_DATA(IP16_11_10, MLB_DAT),
1674 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1675};
1676
1677static struct sh_pfc_pin pinmux_pins[] = {
1678 PINMUX_GPIO_GP_ALL(),
1679};
1680
1681/* - DU --------------------------------------------------------------------- */
1682static const unsigned int du_rgb666_pins[] = {
1683 /* R[7:2], G[7:2], B[7:2] */
1684 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1685 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1686 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1687 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1688 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1689 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1690};
1691static const unsigned int du_rgb666_mux[] = {
1692 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1693 DU1_DR3_MARK, DU1_DR2_MARK,
1694 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1695 DU1_DG3_MARK, DU1_DG2_MARK,
1696 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1697 DU1_DB3_MARK, DU1_DB2_MARK,
1698};
1699static const unsigned int du_rgb888_pins[] = {
1700 /* R[7:0], G[7:0], B[7:0] */
1701 RCAR_GP_PIN(3, 7), RCAR_GP_PIN(3, 6), RCAR_GP_PIN(3, 5),
1702 RCAR_GP_PIN(3, 4), RCAR_GP_PIN(3, 3), RCAR_GP_PIN(3, 2),
1703 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1704 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14), RCAR_GP_PIN(3, 13),
1705 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 11), RCAR_GP_PIN(3, 10),
1706 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
1707 RCAR_GP_PIN(3, 23), RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
1708 RCAR_GP_PIN(3, 20), RCAR_GP_PIN(3, 19), RCAR_GP_PIN(3, 18),
1709 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
1710};
1711static const unsigned int du_rgb888_mux[] = {
1712 DU1_DR7_MARK, DU1_DR6_MARK, DU1_DR5_MARK, DU1_DR4_MARK,
1713 DU1_DR3_MARK, DU1_DR2_MARK, DU1_DR1_MARK, DU1_DR0_MARK,
1714 DU1_DG7_MARK, DU1_DG6_MARK, DU1_DG5_MARK, DU1_DG4_MARK,
1715 DU1_DG3_MARK, DU1_DG2_MARK, DU1_DG1_MARK, DU1_DG0_MARK,
1716 DU1_DB7_MARK, DU1_DB6_MARK, DU1_DB5_MARK, DU1_DB4_MARK,
1717 DU1_DB3_MARK, DU1_DB2_MARK, DU1_DB1_MARK, DU1_DB0_MARK,
1718};
1719static const unsigned int du_clk_out_0_pins[] = {
1720 /* CLKOUT */
1721 RCAR_GP_PIN(3, 25),
1722};
1723static const unsigned int du_clk_out_0_mux[] = {
1724 DU1_DOTCLKOUT0_MARK
1725};
1726static const unsigned int du_clk_out_1_pins[] = {
1727 /* CLKOUT */
1728 RCAR_GP_PIN(3, 26),
1729};
1730static const unsigned int du_clk_out_1_mux[] = {
1731 DU1_DOTCLKOUT1_MARK
1732};
1733static const unsigned int du_sync_1_pins[] = {
1734 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */
1735 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1736};
1737static const unsigned int du_sync_1_mux[] = {
1738 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1739 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1740};
1741static const unsigned int du_cde_disp_pins[] = {
1742 /* CDE DISP */
1743 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1744};
1745static const unsigned int du0_clk_in_pins[] = {
1746 /* CLKIN */
1747 RCAR_GP_PIN(6, 31),
1748};
1749static const unsigned int du0_clk_in_mux[] = {
1750 DU0_DOTCLKIN_MARK
1751};
1752static const unsigned int du_cde_disp_mux[] = {
1753 DU1_CDE_MARK, DU1_DISP_MARK
1754};
1755static const unsigned int du1_clk_in_pins[] = {
1756 /* CLKIN */
1757 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), RCAR_GP_PIN(3, 24),
1758};
1759static const unsigned int du1_clk_in_mux[] = {
1760 DU1_DOTCLKIN_C_MARK, DU1_DOTCLKIN_B_MARK, DU1_DOTCLKIN_MARK
1761};
1762/* - ETH -------------------------------------------------------------------- */
1763static const unsigned int eth_link_pins[] = {
1764 /* LINK */
1765 RCAR_GP_PIN(5, 18),
1766};
1767static const unsigned int eth_link_mux[] = {
1768 ETH_LINK_MARK,
1769};
1770static const unsigned int eth_magic_pins[] = {
1771 /* MAGIC */
1772 RCAR_GP_PIN(5, 22),
1773};
1774static const unsigned int eth_magic_mux[] = {
1775 ETH_MAGIC_MARK,
1776};
1777static const unsigned int eth_mdio_pins[] = {
1778 /* MDC, MDIO */
1779 RCAR_GP_PIN(5, 24), RCAR_GP_PIN(5, 13),
1780};
1781static const unsigned int eth_mdio_mux[] = {
1782 ETH_MDC_MARK, ETH_MDIO_MARK,
1783};
1784static const unsigned int eth_rmii_pins[] = {
1785 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK */
1786 RCAR_GP_PIN(5, 16), RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 15),
1787 RCAR_GP_PIN(5, 14), RCAR_GP_PIN(5, 23), RCAR_GP_PIN(5, 20),
1788 RCAR_GP_PIN(5, 21), RCAR_GP_PIN(5, 19),
1789};
1790static const unsigned int eth_rmii_mux[] = {
1791 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1792 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1793};
1794/* - INTC ------------------------------------------------------------------- */
1795static const unsigned int intc_irq0_pins[] = {
1796 /* IRQ */
1797 RCAR_GP_PIN(7, 10),
1798};
1799static const unsigned int intc_irq0_mux[] = {
1800 IRQ0_MARK,
1801};
1802static const unsigned int intc_irq1_pins[] = {
1803 /* IRQ */
1804 RCAR_GP_PIN(7, 11),
1805};
1806static const unsigned int intc_irq1_mux[] = {
1807 IRQ1_MARK,
1808};
1809static const unsigned int intc_irq2_pins[] = {
1810 /* IRQ */
1811 RCAR_GP_PIN(7, 12),
1812};
1813static const unsigned int intc_irq2_mux[] = {
1814 IRQ2_MARK,
1815};
1816static const unsigned int intc_irq3_pins[] = {
1817 /* IRQ */
1818 RCAR_GP_PIN(7, 13),
1819};
1820static const unsigned int intc_irq3_mux[] = {
1821 IRQ3_MARK,
1822};
1823/* - MMCIF ------------------------------------------------------------------ */
1824static const unsigned int mmc_data1_pins[] = {
1825 /* D[0] */
1826 RCAR_GP_PIN(6, 18),
1827};
1828static const unsigned int mmc_data1_mux[] = {
1829 MMC_D0_MARK,
1830};
1831static const unsigned int mmc_data4_pins[] = {
1832 /* D[0:3] */
1833 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1834 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1835};
1836static const unsigned int mmc_data4_mux[] = {
1837 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1838};
1839static const unsigned int mmc_data8_pins[] = {
1840 /* D[0:7] */
1841 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
1842 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
1843 RCAR_GP_PIN(6, 22), RCAR_GP_PIN(6, 23),
1844 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
1845};
1846static const unsigned int mmc_data8_mux[] = {
1847 MMC_D0_MARK, MMC_D1_MARK, MMC_D2_MARK, MMC_D3_MARK,
1848 MMC_D4_MARK, MMC_D5_MARK, MMC_D6_MARK, MMC_D7_MARK,
1849};
1850static const unsigned int mmc_ctrl_pins[] = {
1851 /* CLK, CMD */
1852 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
1853};
1854static const unsigned int mmc_ctrl_mux[] = {
1855 MMC_CLK_MARK, MMC_CMD_MARK,
1856};
1857/* - MSIOF0 ----------------------------------------------------------------- */
1858static const unsigned int msiof0_clk_pins[] = {
1859 /* SCK */
1860 RCAR_GP_PIN(6, 24),
1861};
1862static const unsigned int msiof0_clk_mux[] = {
1863 MSIOF0_SCK_MARK,
1864};
1865static const unsigned int msiof0_sync_pins[] = {
1866 /* SYNC */
1867 RCAR_GP_PIN(6, 25),
1868};
1869static const unsigned int msiof0_sync_mux[] = {
1870 MSIOF0_SYNC_MARK,
1871};
1872static const unsigned int msiof0_ss1_pins[] = {
1873 /* SS1 */
1874 RCAR_GP_PIN(6, 28),
1875};
1876static const unsigned int msiof0_ss1_mux[] = {
1877 MSIOF0_SS1_MARK,
1878};
1879static const unsigned int msiof0_ss2_pins[] = {
1880 /* SS2 */
1881 RCAR_GP_PIN(6, 29),
1882};
1883static const unsigned int msiof0_ss2_mux[] = {
1884 MSIOF0_SS2_MARK,
1885};
1886static const unsigned int msiof0_rx_pins[] = {
1887 /* RXD */
1888 RCAR_GP_PIN(6, 27),
1889};
1890static const unsigned int msiof0_rx_mux[] = {
1891 MSIOF0_RXD_MARK,
1892};
1893static const unsigned int msiof0_tx_pins[] = {
1894 /* TXD */
1895 RCAR_GP_PIN(6, 26),
1896};
1897static const unsigned int msiof0_tx_mux[] = {
1898 MSIOF0_TXD_MARK,
1899};
1900/* - MSIOF1 ----------------------------------------------------------------- */
1901static const unsigned int msiof1_clk_pins[] = {
1902 /* SCK */
1903 RCAR_GP_PIN(0, 22),
1904};
1905static const unsigned int msiof1_clk_mux[] = {
1906 MSIOF1_SCK_MARK,
1907};
1908static const unsigned int msiof1_sync_pins[] = {
1909 /* SYNC */
1910 RCAR_GP_PIN(0, 23),
1911};
1912static const unsigned int msiof1_sync_mux[] = {
1913 MSIOF1_SYNC_MARK,
1914};
1915static const unsigned int msiof1_ss1_pins[] = {
1916 /* SS1 */
1917 RCAR_GP_PIN(0, 24),
1918};
1919static const unsigned int msiof1_ss1_mux[] = {
1920 MSIOF1_SS1_MARK,
1921};
1922static const unsigned int msiof1_ss2_pins[] = {
1923 /* SS2 */
1924 RCAR_GP_PIN(0, 25),
1925};
1926static const unsigned int msiof1_ss2_mux[] = {
1927 MSIOF1_SS2_MARK,
1928};
1929static const unsigned int msiof1_rx_pins[] = {
1930 /* RXD */
1931 RCAR_GP_PIN(0, 27),
1932};
1933static const unsigned int msiof1_rx_mux[] = {
1934 MSIOF1_RXD_MARK,
1935};
1936static const unsigned int msiof1_tx_pins[] = {
1937 /* TXD */
1938 RCAR_GP_PIN(0, 26),
1939};
1940static const unsigned int msiof1_tx_mux[] = {
1941 MSIOF1_TXD_MARK,
1942};
1943/* - MSIOF2 ----------------------------------------------------------------- */
1944static const unsigned int msiof2_clk_pins[] = {
1945 /* SCK */
1946 RCAR_GP_PIN(1, 13),
1947};
1948static const unsigned int msiof2_clk_mux[] = {
1949 MSIOF2_SCK_MARK,
1950};
1951static const unsigned int msiof2_sync_pins[] = {
1952 /* SYNC */
1953 RCAR_GP_PIN(1, 14),
1954};
1955static const unsigned int msiof2_sync_mux[] = {
1956 MSIOF2_SYNC_MARK,
1957};
1958static const unsigned int msiof2_ss1_pins[] = {
1959 /* SS1 */
1960 RCAR_GP_PIN(1, 17),
1961};
1962static const unsigned int msiof2_ss1_mux[] = {
1963 MSIOF2_SS1_MARK,
1964};
1965static const unsigned int msiof2_ss2_pins[] = {
1966 /* SS2 */
1967 RCAR_GP_PIN(1, 18),
1968};
1969static const unsigned int msiof2_ss2_mux[] = {
1970 MSIOF2_SS2_MARK,
1971};
1972static const unsigned int msiof2_rx_pins[] = {
1973 /* RXD */
1974 RCAR_GP_PIN(1, 16),
1975};
1976static const unsigned int msiof2_rx_mux[] = {
1977 MSIOF2_RXD_MARK,
1978};
1979static const unsigned int msiof2_tx_pins[] = {
1980 /* TXD */
1981 RCAR_GP_PIN(1, 15),
1982};
1983static const unsigned int msiof2_tx_mux[] = {
1984 MSIOF2_TXD_MARK,
1985};
1986/* - SCIF0 ------------------------------------------------------------------ */
1987static const unsigned int scif0_data_pins[] = {
1988 /* RX, TX */
1989 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
1990};
1991static const unsigned int scif0_data_mux[] = {
1992 RX0_MARK, TX0_MARK,
1993};
1994static const unsigned int scif0_data_b_pins[] = {
1995 /* RX, TX */
1996 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
1997};
1998static const unsigned int scif0_data_b_mux[] = {
1999 RX0_B_MARK, TX0_B_MARK,
2000};
2001static const unsigned int scif0_data_c_pins[] = {
2002 /* RX, TX */
2003 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 25),
2004};
2005static const unsigned int scif0_data_c_mux[] = {
2006 RX0_C_MARK, TX0_C_MARK,
2007};
2008static const unsigned int scif0_data_d_pins[] = {
2009 /* RX, TX */
2010 RCAR_GP_PIN(2, 23), RCAR_GP_PIN(2, 22),
2011};
2012static const unsigned int scif0_data_d_mux[] = {
2013 RX0_D_MARK, TX0_D_MARK,
2014};
2015static const unsigned int scif0_data_e_pins[] = {
2016 /* RX, TX */
2017 RCAR_GP_PIN(6, 29), RCAR_GP_PIN(6, 28),
2018};
2019static const unsigned int scif0_data_e_mux[] = {
2020 RX0_E_MARK, TX0_E_MARK,
2021};
2022/* - SCIF1 ------------------------------------------------------------------ */
2023static const unsigned int scif1_data_pins[] = {
2024 /* RX, TX */
2025 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2026};
2027static const unsigned int scif1_data_mux[] = {
2028 RX1_MARK, TX1_MARK,
2029};
2030static const unsigned int scif1_data_b_pins[] = {
2031 /* RX, TX */
2032 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2033};
2034static const unsigned int scif1_data_b_mux[] = {
2035 RX1_B_MARK, TX1_B_MARK,
2036};
2037static const unsigned int scif1_clk_b_pins[] = {
2038 /* SCK */
2039 RCAR_GP_PIN(3, 10),
2040};
2041static const unsigned int scif1_clk_b_mux[] = {
2042 SCIF1_SCK_B_MARK,
2043};
2044static const unsigned int scif1_data_c_pins[] = {
2045 /* RX, TX */
2046 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 27),
2047};
2048static const unsigned int scif1_data_c_mux[] = {
2049 RX1_C_MARK, TX1_C_MARK,
2050};
2051static const unsigned int scif1_data_d_pins[] = {
2052 /* RX, TX */
2053 RCAR_GP_PIN(2, 25), RCAR_GP_PIN(2, 24),
2054};
2055static const unsigned int scif1_data_d_mux[] = {
2056 RX1_D_MARK, TX1_D_MARK,
2057};
2058/* - SCIF2 ------------------------------------------------------------------ */
2059static const unsigned int scif2_data_pins[] = {
2060 /* RX, TX */
2061 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2062};
2063static const unsigned int scif2_data_mux[] = {
2064 RX2_MARK, TX2_MARK,
2065};
2066static const unsigned int scif2_data_b_pins[] = {
2067 /* RX, TX */
2068 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2069};
2070static const unsigned int scif2_data_b_mux[] = {
2071 RX2_B_MARK, TX2_B_MARK,
2072};
2073static const unsigned int scif2_clk_b_pins[] = {
2074 /* SCK */
2075 RCAR_GP_PIN(3, 18),
2076};
2077static const unsigned int scif2_clk_b_mux[] = {
2078 SCIF2_SCK_B_MARK,
2079};
2080static const unsigned int scif2_data_c_pins[] = {
2081 /* RX, TX */
2082 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2083};
2084static const unsigned int scif2_data_c_mux[] = {
2085 RX2_C_MARK, TX2_C_MARK,
2086};
2087static const unsigned int scif2_data_e_pins[] = {
2088 /* RX, TX */
2089 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
2090};
2091static const unsigned int scif2_data_e_mux[] = {
2092 RX2_E_MARK, TX2_E_MARK,
2093};
2094/* - SCIF3 ------------------------------------------------------------------ */
2095static const unsigned int scif3_data_pins[] = {
2096 /* RX, TX */
2097 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2098};
2099static const unsigned int scif3_data_mux[] = {
2100 RX3_MARK, TX3_MARK,
2101};
2102static const unsigned int scif3_clk_pins[] = {
2103 /* SCK */
2104 RCAR_GP_PIN(3, 23),
2105};
2106static const unsigned int scif3_clk_mux[] = {
2107 SCIF3_SCK_MARK,
2108};
2109static const unsigned int scif3_data_b_pins[] = {
2110 /* RX, TX */
2111 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 26),
2112};
2113static const unsigned int scif3_data_b_mux[] = {
2114 RX3_B_MARK, TX3_B_MARK,
2115};
2116static const unsigned int scif3_clk_b_pins[] = {
2117 /* SCK */
2118 RCAR_GP_PIN(4, 8),
2119};
2120static const unsigned int scif3_clk_b_mux[] = {
2121 SCIF3_SCK_B_MARK,
2122};
2123static const unsigned int scif3_data_c_pins[] = {
2124 /* RX, TX */
2125 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2126};
2127static const unsigned int scif3_data_c_mux[] = {
2128 RX3_C_MARK, TX3_C_MARK,
2129};
2130static const unsigned int scif3_data_d_pins[] = {
2131 /* RX, TX */
2132 RCAR_GP_PIN(2, 27), RCAR_GP_PIN(2, 26),
2133};
2134static const unsigned int scif3_data_d_mux[] = {
2135 RX3_D_MARK, TX3_D_MARK,
2136};
2137/* - SCIF4 ------------------------------------------------------------------ */
2138static const unsigned int scif4_data_pins[] = {
2139 /* RX, TX */
2140 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2141};
2142static const unsigned int scif4_data_mux[] = {
2143 RX4_MARK, TX4_MARK,
2144};
2145static const unsigned int scif4_data_b_pins[] = {
2146 /* RX, TX */
2147 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2148};
2149static const unsigned int scif4_data_b_mux[] = {
2150 RX4_B_MARK, TX4_B_MARK,
2151};
2152static const unsigned int scif4_data_c_pins[] = {
2153 /* RX, TX */
2154 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2155};
2156static const unsigned int scif4_data_c_mux[] = {
2157 RX4_C_MARK, TX4_C_MARK,
2158};
2159/* - SCIF5 ------------------------------------------------------------------ */
2160static const unsigned int scif5_data_pins[] = {
2161 /* RX, TX */
2162 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2163};
2164static const unsigned int scif5_data_mux[] = {
2165 RX5_MARK, TX5_MARK,
2166};
2167static const unsigned int scif5_data_b_pins[] = {
2168 /* RX, TX */
2169 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2170};
2171static const unsigned int scif5_data_b_mux[] = {
2172 RX5_B_MARK, TX5_B_MARK,
2173};
2174/* - SCIFA0 ----------------------------------------------------------------- */
2175static const unsigned int scifa0_data_pins[] = {
2176 /* RXD, TXD */
2177 RCAR_GP_PIN(1, 7), RCAR_GP_PIN(1, 6),
2178};
2179static const unsigned int scifa0_data_mux[] = {
2180 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2181};
2182static const unsigned int scifa0_data_b_pins[] = {
2183 /* RXD, TXD */
2184 RCAR_GP_PIN(3, 1), RCAR_GP_PIN(3, 0),
2185};
2186static const unsigned int scifa0_data_b_mux[] = {
2187 SCIFA0_RXD_B_MARK, SCIFA0_TXD_B_MARK
2188};
2189/* - SCIFA1 ----------------------------------------------------------------- */
2190static const unsigned int scifa1_data_pins[] = {
2191 /* RXD, TXD */
2192 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 8),
2193};
2194static const unsigned int scifa1_data_mux[] = {
2195 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2196};
2197static const unsigned int scifa1_clk_pins[] = {
2198 /* SCK */
2199 RCAR_GP_PIN(3, 10),
2200};
2201static const unsigned int scifa1_clk_mux[] = {
2202 SCIFA1_SCK_MARK,
2203};
2204static const unsigned int scifa1_data_b_pins[] = {
2205 /* RXD, TXD */
2206 RCAR_GP_PIN(3, 9), RCAR_GP_PIN(3, 8),
2207};
2208static const unsigned int scifa1_data_b_mux[] = {
2209 SCIFA1_RXD_B_MARK, SCIFA1_TXD_B_MARK,
2210};
2211static const unsigned int scifa1_clk_b_pins[] = {
2212 /* SCK */
2213 RCAR_GP_PIN(1, 0),
2214};
2215static const unsigned int scifa1_clk_b_mux[] = {
2216 SCIFA1_SCK_B_MARK,
2217};
2218static const unsigned int scifa1_data_c_pins[] = {
2219 /* RXD, TXD */
2220 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2221};
2222static const unsigned int scifa1_data_c_mux[] = {
2223 SCIFA1_RXD_C_MARK, SCIFA1_TXD_C_MARK,
2224};
2225/* - SCIFA2 ----------------------------------------------------------------- */
2226static const unsigned int scifa2_data_pins[] = {
2227 /* RXD, TXD */
2228 RCAR_GP_PIN(2, 30), RCAR_GP_PIN(2, 31),
2229};
2230static const unsigned int scifa2_data_mux[] = {
2231 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2232};
2233static const unsigned int scifa2_clk_pins[] = {
2234 /* SCK */
2235 RCAR_GP_PIN(3, 18),
2236};
2237static const unsigned int scifa2_clk_mux[] = {
2238 SCIFA2_SCK_MARK,
2239};
2240static const unsigned int scifa2_data_b_pins[] = {
2241 /* RXD, TXD */
2242 RCAR_GP_PIN(3, 17), RCAR_GP_PIN(3, 16),
2243};
2244static const unsigned int scifa2_data_b_mux[] = {
2245 SCIFA2_RXD_B_MARK, SCIFA2_TXD_B_MARK,
2246};
2247/* - SCIFA3 ----------------------------------------------------------------- */
2248static const unsigned int scifa3_data_pins[] = {
2249 /* RXD, TXD */
2250 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 21),
2251};
2252static const unsigned int scifa3_data_mux[] = {
2253 SCIFA3_RXD_MARK, SCIFA3_TXD_MARK,
2254};
2255static const unsigned int scifa3_clk_pins[] = {
2256 /* SCK */
2257 RCAR_GP_PIN(3, 23),
2258};
2259static const unsigned int scifa3_clk_mux[] = {
2260 SCIFA3_SCK_MARK,
2261};
2262static const unsigned int scifa3_data_b_pins[] = {
2263 /* RXD, TXD */
2264 RCAR_GP_PIN(5, 19), RCAR_GP_PIN(5, 20),
2265};
2266static const unsigned int scifa3_data_b_mux[] = {
2267 SCIFA3_RXD_B_MARK, SCIFA3_TXD_B_MARK,
2268};
2269static const unsigned int scifa3_clk_b_pins[] = {
2270 /* SCK */
2271 RCAR_GP_PIN(4, 8),
2272};
2273static const unsigned int scifa3_clk_b_mux[] = {
2274 SCIFA3_SCK_B_MARK,
2275};
2276static const unsigned int scifa3_data_c_pins[] = {
2277 /* RXD, TXD */
2278 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 20),
2279};
2280static const unsigned int scifa3_data_c_mux[] = {
2281 SCIFA3_RXD_C_MARK, SCIFA3_TXD_C_MARK,
2282};
2283static const unsigned int scifa3_clk_c_pins[] = {
2284 /* SCK */
2285 RCAR_GP_PIN(7, 22),
2286};
2287static const unsigned int scifa3_clk_c_mux[] = {
2288 SCIFA3_SCK_C_MARK,
2289};
2290/* - SCIFA4 ----------------------------------------------------------------- */
2291static const unsigned int scifa4_data_pins[] = {
2292 /* RXD, TXD */
2293 RCAR_GP_PIN(4, 2), RCAR_GP_PIN(4, 1),
2294};
2295static const unsigned int scifa4_data_mux[] = {
2296 SCIFA4_RXD_MARK, SCIFA4_TXD_MARK,
2297};
2298static const unsigned int scifa4_data_b_pins[] = {
2299 /* RXD, TXD */
2300 RCAR_GP_PIN(5, 1), RCAR_GP_PIN(5, 0),
2301};
2302static const unsigned int scifa4_data_b_mux[] = {
2303 SCIFA4_RXD_B_MARK, SCIFA4_TXD_B_MARK,
2304};
2305static const unsigned int scifa4_data_c_pins[] = {
2306 /* RXD, TXD */
2307 RCAR_GP_PIN(7, 22), RCAR_GP_PIN(7, 21),
2308};
2309static const unsigned int scifa4_data_c_mux[] = {
2310 SCIFA4_RXD_C_MARK, SCIFA4_TXD_C_MARK,
2311};
2312/* - SCIFA5 ----------------------------------------------------------------- */
2313static const unsigned int scifa5_data_pins[] = {
2314 /* RXD, TXD */
2315 RCAR_GP_PIN(4, 4), RCAR_GP_PIN(4, 3),
2316};
2317static const unsigned int scifa5_data_mux[] = {
2318 SCIFA5_RXD_MARK, SCIFA5_TXD_MARK,
2319};
2320static const unsigned int scifa5_data_b_pins[] = {
2321 /* RXD, TXD */
2322 RCAR_GP_PIN(6, 7), RCAR_GP_PIN(6, 6),
2323};
2324static const unsigned int scifa5_data_b_mux[] = {
2325 SCIFA5_RXD_B_MARK, SCIFA5_TXD_B_MARK,
2326};
2327static const unsigned int scifa5_data_c_pins[] = {
2328 /* RXD, TXD */
2329 RCAR_GP_PIN(6, 23), RCAR_GP_PIN(6, 22),
2330};
2331static const unsigned int scifa5_data_c_mux[] = {
2332 SCIFA5_RXD_C_MARK, SCIFA5_TXD_C_MARK,
2333};
2334/* - SCIFB0 ----------------------------------------------------------------- */
2335static const unsigned int scifb0_data_pins[] = {
2336 /* RXD, TXD */
2337 RCAR_GP_PIN(7, 3), RCAR_GP_PIN(7, 4),
2338};
2339static const unsigned int scifb0_data_mux[] = {
2340 SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
2341};
2342static const unsigned int scifb0_clk_pins[] = {
2343 /* SCK */
2344 RCAR_GP_PIN(7, 2),
2345};
2346static const unsigned int scifb0_clk_mux[] = {
2347 SCIFB0_SCK_MARK,
2348};
2349static const unsigned int scifb0_ctrl_pins[] = {
2350 /* RTS, CTS */
2351 RCAR_GP_PIN(7, 1), RCAR_GP_PIN(7, 0),
2352};
2353static const unsigned int scifb0_ctrl_mux[] = {
2354 SCIFB0_RTS_N_MARK, SCIFB0_CTS_N_MARK,
2355};
2356static const unsigned int scifb0_data_b_pins[] = {
2357 /* RXD, TXD */
2358 RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 21),
2359};
2360static const unsigned int scifb0_data_b_mux[] = {
2361 SCIFB0_RXD_B_MARK, SCIFB0_TXD_B_MARK,
2362};
2363static const unsigned int scifb0_clk_b_pins[] = {
2364 /* SCK */
2365 RCAR_GP_PIN(5, 31),
2366};
2367static const unsigned int scifb0_clk_b_mux[] = {
2368 SCIFB0_SCK_B_MARK,
2369};
2370static const unsigned int scifb0_ctrl_b_pins[] = {
2371 /* RTS, CTS */
2372 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 23),
2373};
2374static const unsigned int scifb0_ctrl_b_mux[] = {
2375 SCIFB0_RTS_N_B_MARK, SCIFB0_CTS_N_B_MARK,
2376};
2377static const unsigned int scifb0_data_c_pins[] = {
2378 /* RXD, TXD */
2379 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2380};
2381static const unsigned int scifb0_data_c_mux[] = {
2382 SCIFB0_RXD_C_MARK, SCIFB0_TXD_C_MARK,
2383};
2384static const unsigned int scifb0_clk_c_pins[] = {
2385 /* SCK */
2386 RCAR_GP_PIN(2, 30),
2387};
2388static const unsigned int scifb0_clk_c_mux[] = {
2389 SCIFB0_SCK_C_MARK,
2390};
2391static const unsigned int scifb0_data_d_pins[] = {
2392 /* RXD, TXD */
2393 RCAR_GP_PIN(4, 28), RCAR_GP_PIN(4, 18),
2394};
2395static const unsigned int scifb0_data_d_mux[] = {
2396 SCIFB0_RXD_D_MARK, SCIFB0_TXD_D_MARK,
2397};
2398static const unsigned int scifb0_clk_d_pins[] = {
2399 /* SCK */
2400 RCAR_GP_PIN(4, 17),
2401};
2402static const unsigned int scifb0_clk_d_mux[] = {
2403 SCIFB0_SCK_D_MARK,
2404};
2405/* - SCIFB1 ----------------------------------------------------------------- */
2406static const unsigned int scifb1_data_pins[] = {
2407 /* RXD, TXD */
2408 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2409};
2410static const unsigned int scifb1_data_mux[] = {
2411 SCIFB1_RXD_MARK, SCIFB1_TXD_MARK,
2412};
2413static const unsigned int scifb1_clk_pins[] = {
2414 /* SCK */
2415 RCAR_GP_PIN(7, 7),
2416};
2417static const unsigned int scifb1_clk_mux[] = {
2418 SCIFB1_SCK_MARK,
2419};
2420static const unsigned int scifb1_ctrl_pins[] = {
2421 /* RTS, CTS */
2422 RCAR_GP_PIN(7, 9), RCAR_GP_PIN(7, 8),
2423};
2424static const unsigned int scifb1_ctrl_mux[] = {
2425 SCIFB1_RTS_N_MARK, SCIFB1_CTS_N_MARK,
2426};
2427static const unsigned int scifb1_data_b_pins[] = {
2428 /* RXD, TXD */
2429 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 18),
2430};
2431static const unsigned int scifb1_data_b_mux[] = {
2432 SCIFB1_RXD_B_MARK, SCIFB1_TXD_B_MARK,
2433};
2434static const unsigned int scifb1_clk_b_pins[] = {
2435 /* SCK */
2436 RCAR_GP_PIN(1, 3),
2437};
2438static const unsigned int scifb1_clk_b_mux[] = {
2439 SCIFB1_SCK_B_MARK,
2440};
2441static const unsigned int scifb1_data_c_pins[] = {
2442 /* RXD, TXD */
2443 RCAR_GP_PIN(1, 2), RCAR_GP_PIN(1, 3),
2444};
2445static const unsigned int scifb1_data_c_mux[] = {
2446 SCIFB1_RXD_C_MARK, SCIFB1_TXD_C_MARK,
2447};
2448static const unsigned int scifb1_clk_c_pins[] = {
2449 /* SCK */
2450 RCAR_GP_PIN(7, 11),
2451};
2452static const unsigned int scifb1_clk_c_mux[] = {
2453 SCIFB1_SCK_C_MARK,
2454};
2455static const unsigned int scifb1_data_d_pins[] = {
2456 /* RXD, TXD */
2457 RCAR_GP_PIN(7, 10), RCAR_GP_PIN(7, 12),
2458};
2459static const unsigned int scifb1_data_d_mux[] = {
2460 SCIFB1_RXD_D_MARK, SCIFB1_TXD_D_MARK,
2461};
2462/* - SCIFB2 ----------------------------------------------------------------- */
2463static const unsigned int scifb2_data_pins[] = {
2464 /* RXD, TXD */
2465 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 17),
2466};
2467static const unsigned int scifb2_data_mux[] = {
2468 SCIFB2_RXD_MARK, SCIFB2_TXD_MARK,
2469};
2470static const unsigned int scifb2_clk_pins[] = {
2471 /* SCK */
2472 RCAR_GP_PIN(4, 15),
2473};
2474static const unsigned int scifb2_clk_mux[] = {
2475 SCIFB2_SCK_MARK,
2476};
2477static const unsigned int scifb2_ctrl_pins[] = {
2478 /* RTS, CTS */
2479 RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 13),
2480};
2481static const unsigned int scifb2_ctrl_mux[] = {
2482 SCIFB2_RTS_N_MARK, SCIFB2_CTS_N_MARK,
2483};
2484static const unsigned int scifb2_data_b_pins[] = {
2485 /* RXD, TXD */
2486 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2487};
2488static const unsigned int scifb2_data_b_mux[] = {
2489 SCIFB2_RXD_B_MARK, SCIFB2_TXD_B_MARK,
2490};
2491static const unsigned int scifb2_clk_b_pins[] = {
2492 /* SCK */
2493 RCAR_GP_PIN(5, 31),
2494};
2495static const unsigned int scifb2_clk_b_mux[] = {
2496 SCIFB2_SCK_B_MARK,
2497};
2498static const unsigned int scifb2_ctrl_b_pins[] = {
2499 /* RTS, CTS */
2500 RCAR_GP_PIN(3, 15), RCAR_GP_PIN(3, 14),
2501};
2502static const unsigned int scifb2_ctrl_b_mux[] = {
2503 SCIFB2_RTS_N_B_MARK, SCIFB2_CTS_N_B_MARK,
2504};
2505static const unsigned int scifb2_data_c_pins[] = {
2506 /* RXD, TXD */
2507 RCAR_GP_PIN(2, 0), RCAR_GP_PIN(2, 1),
2508};
2509static const unsigned int scifb2_data_c_mux[] = {
2510 SCIFB2_RXD_C_MARK, SCIFB2_TXD_C_MARK,
2511};
2512static const unsigned int scifb2_clk_c_pins[] = {
2513 /* SCK */
2514 RCAR_GP_PIN(5, 27),
2515};
2516static const unsigned int scifb2_clk_c_mux[] = {
2517 SCIFB2_SCK_C_MARK,
2518};
2519static const unsigned int scifb2_data_d_pins[] = {
2520 /* RXD, TXD */
2521 RCAR_GP_PIN(5, 26), RCAR_GP_PIN(5, 25),
2522};
2523static const unsigned int scifb2_data_d_mux[] = {
2524 SCIFB2_RXD_D_MARK, SCIFB2_TXD_D_MARK,
2525};
2526/* - SDHI0 ------------------------------------------------------------------ */
2527static const unsigned int sdhi0_data1_pins[] = {
2528 /* D0 */
2529 RCAR_GP_PIN(6, 2),
2530};
2531static const unsigned int sdhi0_data1_mux[] = {
2532 SD0_DATA0_MARK,
2533};
2534static const unsigned int sdhi0_data4_pins[] = {
2535 /* D[0:3] */
2536 RCAR_GP_PIN(6, 2), RCAR_GP_PIN(6, 3),
2537 RCAR_GP_PIN(6, 4), RCAR_GP_PIN(6, 5),
2538};
2539static const unsigned int sdhi0_data4_mux[] = {
2540 SD0_DATA0_MARK, SD0_DATA1_MARK, SD0_DATA2_MARK, SD0_DATA3_MARK,
2541};
2542static const unsigned int sdhi0_ctrl_pins[] = {
2543 /* CLK, CMD */
2544 RCAR_GP_PIN(6, 0), RCAR_GP_PIN(6, 1),
2545};
2546static const unsigned int sdhi0_ctrl_mux[] = {
2547 SD0_CLK_MARK, SD0_CMD_MARK,
2548};
2549static const unsigned int sdhi0_cd_pins[] = {
2550 /* CD */
2551 RCAR_GP_PIN(6, 6),
2552};
2553static const unsigned int sdhi0_cd_mux[] = {
2554 SD0_CD_MARK,
2555};
2556static const unsigned int sdhi0_wp_pins[] = {
2557 /* WP */
2558 RCAR_GP_PIN(6, 7),
2559};
2560static const unsigned int sdhi0_wp_mux[] = {
2561 SD0_WP_MARK,
2562};
2563/* - SDHI1 ------------------------------------------------------------------ */
2564static const unsigned int sdhi1_data1_pins[] = {
2565 /* D0 */
2566 RCAR_GP_PIN(6, 10),
2567};
2568static const unsigned int sdhi1_data1_mux[] = {
2569 SD1_DATA0_MARK,
2570};
2571static const unsigned int sdhi1_data4_pins[] = {
2572 /* D[0:3] */
2573 RCAR_GP_PIN(6, 10), RCAR_GP_PIN(6, 11),
2574 RCAR_GP_PIN(6, 12), RCAR_GP_PIN(6, 13),
2575};
2576static const unsigned int sdhi1_data4_mux[] = {
2577 SD1_DATA0_MARK, SD1_DATA1_MARK, SD1_DATA2_MARK, SD1_DATA3_MARK,
2578};
2579static const unsigned int sdhi1_ctrl_pins[] = {
2580 /* CLK, CMD */
2581 RCAR_GP_PIN(6, 8), RCAR_GP_PIN(6, 9),
2582};
2583static const unsigned int sdhi1_ctrl_mux[] = {
2584 SD1_CLK_MARK, SD1_CMD_MARK,
2585};
2586static const unsigned int sdhi1_cd_pins[] = {
2587 /* CD */
2588 RCAR_GP_PIN(6, 14),
2589};
2590static const unsigned int sdhi1_cd_mux[] = {
2591 SD1_CD_MARK,
2592};
2593static const unsigned int sdhi1_wp_pins[] = {
2594 /* WP */
2595 RCAR_GP_PIN(6, 15),
2596};
2597static const unsigned int sdhi1_wp_mux[] = {
2598 SD1_WP_MARK,
2599};
2600/* - SDHI2 ------------------------------------------------------------------ */
2601static const unsigned int sdhi2_data1_pins[] = {
2602 /* D0 */
2603 RCAR_GP_PIN(6, 18),
2604};
2605static const unsigned int sdhi2_data1_mux[] = {
2606 SD2_DATA0_MARK,
2607};
2608static const unsigned int sdhi2_data4_pins[] = {
2609 /* D[0:3] */
2610 RCAR_GP_PIN(6, 18), RCAR_GP_PIN(6, 19),
2611 RCAR_GP_PIN(6, 20), RCAR_GP_PIN(6, 21),
2612};
2613static const unsigned int sdhi2_data4_mux[] = {
2614 SD2_DATA0_MARK, SD2_DATA1_MARK, SD2_DATA2_MARK, SD2_DATA3_MARK,
2615};
2616static const unsigned int sdhi2_ctrl_pins[] = {
2617 /* CLK, CMD */
2618 RCAR_GP_PIN(6, 16), RCAR_GP_PIN(6, 17),
2619};
2620static const unsigned int sdhi2_ctrl_mux[] = {
2621 SD2_CLK_MARK, SD2_CMD_MARK,
2622};
2623static const unsigned int sdhi2_cd_pins[] = {
2624 /* CD */
2625 RCAR_GP_PIN(6, 22),
2626};
2627static const unsigned int sdhi2_cd_mux[] = {
2628 SD2_CD_MARK,
2629};
2630static const unsigned int sdhi2_wp_pins[] = {
2631 /* WP */
2632 RCAR_GP_PIN(6, 23),
2633};
2634static const unsigned int sdhi2_wp_mux[] = {
2635 SD2_WP_MARK,
2636};
2637/* - USB0 ------------------------------------------------------------------- */
2638static const unsigned int usb0_pwen_pins[] = {
2639 /* PWEN */
2640 RCAR_GP_PIN(7, 23),
2641};
2642static const unsigned int usb0_pwen_mux[] = {
2643 USB0_PWEN_MARK,
2644};
2645static const unsigned int usb0_ovc_pins[] = {
2646 /* OVC */
2647 RCAR_GP_PIN(7, 24),
2648};
2649static const unsigned int usb0_ovc_mux[] = {
2650 USB0_OVC_MARK,
2651};
2652/* - USB1 ------------------------------------------------------------------- */
2653static const unsigned int usb1_pwen_pins[] = {
2654 /* PWEN */
2655 RCAR_GP_PIN(7, 25),
2656};
2657static const unsigned int usb1_pwen_mux[] = {
2658 USB1_PWEN_MARK,
2659};
2660static const unsigned int usb1_ovc_pins[] = {
2661 /* OVC */
2662 RCAR_GP_PIN(6, 30),
2663};
2664static const unsigned int usb1_ovc_mux[] = {
2665 USB1_OVC_MARK,
2666};
2667
2668static const struct sh_pfc_pin_group pinmux_groups[] = {
2669 SH_PFC_PIN_GROUP(du_rgb666),
2670 SH_PFC_PIN_GROUP(du_rgb888),
2671 SH_PFC_PIN_GROUP(du_clk_out_0),
2672 SH_PFC_PIN_GROUP(du_clk_out_1),
2673 SH_PFC_PIN_GROUP(du_sync_1),
2674 SH_PFC_PIN_GROUP(du_cde_disp),
2675 SH_PFC_PIN_GROUP(du0_clk_in),
2676 SH_PFC_PIN_GROUP(du1_clk_in),
2677 SH_PFC_PIN_GROUP(eth_link),
2678 SH_PFC_PIN_GROUP(eth_magic),
2679 SH_PFC_PIN_GROUP(eth_mdio),
2680 SH_PFC_PIN_GROUP(eth_rmii),
2681 SH_PFC_PIN_GROUP(intc_irq0),
2682 SH_PFC_PIN_GROUP(intc_irq1),
2683 SH_PFC_PIN_GROUP(intc_irq2),
2684 SH_PFC_PIN_GROUP(intc_irq3),
2685 SH_PFC_PIN_GROUP(mmc_data1),
2686 SH_PFC_PIN_GROUP(mmc_data4),
2687 SH_PFC_PIN_GROUP(mmc_data8),
2688 SH_PFC_PIN_GROUP(mmc_ctrl),
2689 SH_PFC_PIN_GROUP(msiof0_clk),
2690 SH_PFC_PIN_GROUP(msiof0_sync),
2691 SH_PFC_PIN_GROUP(msiof0_ss1),
2692 SH_PFC_PIN_GROUP(msiof0_ss2),
2693 SH_PFC_PIN_GROUP(msiof0_rx),
2694 SH_PFC_PIN_GROUP(msiof0_tx),
2695 SH_PFC_PIN_GROUP(msiof1_clk),
2696 SH_PFC_PIN_GROUP(msiof1_sync),
2697 SH_PFC_PIN_GROUP(msiof1_ss1),
2698 SH_PFC_PIN_GROUP(msiof1_ss2),
2699 SH_PFC_PIN_GROUP(msiof1_rx),
2700 SH_PFC_PIN_GROUP(msiof1_tx),
2701 SH_PFC_PIN_GROUP(msiof2_clk),
2702 SH_PFC_PIN_GROUP(msiof2_sync),
2703 SH_PFC_PIN_GROUP(msiof2_ss1),
2704 SH_PFC_PIN_GROUP(msiof2_ss2),
2705 SH_PFC_PIN_GROUP(msiof2_rx),
2706 SH_PFC_PIN_GROUP(msiof2_tx),
2707 SH_PFC_PIN_GROUP(scif0_data),
2708 SH_PFC_PIN_GROUP(scif0_data_b),
2709 SH_PFC_PIN_GROUP(scif0_data_c),
2710 SH_PFC_PIN_GROUP(scif0_data_d),
2711 SH_PFC_PIN_GROUP(scif0_data_e),
2712 SH_PFC_PIN_GROUP(scif1_data),
2713 SH_PFC_PIN_GROUP(scif1_data_b),
2714 SH_PFC_PIN_GROUP(scif1_clk_b),
2715 SH_PFC_PIN_GROUP(scif1_data_c),
2716 SH_PFC_PIN_GROUP(scif1_data_d),
2717 SH_PFC_PIN_GROUP(scif2_data),
2718 SH_PFC_PIN_GROUP(scif2_data_b),
2719 SH_PFC_PIN_GROUP(scif2_clk_b),
2720 SH_PFC_PIN_GROUP(scif2_data_c),
2721 SH_PFC_PIN_GROUP(scif2_data_e),
2722 SH_PFC_PIN_GROUP(scif3_data),
2723 SH_PFC_PIN_GROUP(scif3_clk),
2724 SH_PFC_PIN_GROUP(scif3_data_b),
2725 SH_PFC_PIN_GROUP(scif3_clk_b),
2726 SH_PFC_PIN_GROUP(scif3_data_c),
2727 SH_PFC_PIN_GROUP(scif3_data_d),
2728 SH_PFC_PIN_GROUP(scif4_data),
2729 SH_PFC_PIN_GROUP(scif4_data_b),
2730 SH_PFC_PIN_GROUP(scif4_data_c),
2731 SH_PFC_PIN_GROUP(scif5_data),
2732 SH_PFC_PIN_GROUP(scif5_data_b),
2733 SH_PFC_PIN_GROUP(scifa0_data),
2734 SH_PFC_PIN_GROUP(scifa0_data_b),
2735 SH_PFC_PIN_GROUP(scifa1_data),
2736 SH_PFC_PIN_GROUP(scifa1_clk),
2737 SH_PFC_PIN_GROUP(scifa1_data_b),
2738 SH_PFC_PIN_GROUP(scifa1_clk_b),
2739 SH_PFC_PIN_GROUP(scifa1_data_c),
2740 SH_PFC_PIN_GROUP(scifa2_data),
2741 SH_PFC_PIN_GROUP(scifa2_clk),
2742 SH_PFC_PIN_GROUP(scifa2_data_b),
2743 SH_PFC_PIN_GROUP(scifa3_data),
2744 SH_PFC_PIN_GROUP(scifa3_clk),
2745 SH_PFC_PIN_GROUP(scifa3_data_b),
2746 SH_PFC_PIN_GROUP(scifa3_clk_b),
2747 SH_PFC_PIN_GROUP(scifa3_data_c),
2748 SH_PFC_PIN_GROUP(scifa3_clk_c),
2749 SH_PFC_PIN_GROUP(scifa4_data),
2750 SH_PFC_PIN_GROUP(scifa4_data_b),
2751 SH_PFC_PIN_GROUP(scifa4_data_c),
2752 SH_PFC_PIN_GROUP(scifa5_data),
2753 SH_PFC_PIN_GROUP(scifa5_data_b),
2754 SH_PFC_PIN_GROUP(scifa5_data_c),
2755 SH_PFC_PIN_GROUP(scifb0_data),
2756 SH_PFC_PIN_GROUP(scifb0_clk),
2757 SH_PFC_PIN_GROUP(scifb0_ctrl),
2758 SH_PFC_PIN_GROUP(scifb0_data_b),
2759 SH_PFC_PIN_GROUP(scifb0_clk_b),
2760 SH_PFC_PIN_GROUP(scifb0_ctrl_b),
2761 SH_PFC_PIN_GROUP(scifb0_data_c),
2762 SH_PFC_PIN_GROUP(scifb0_clk_c),
2763 SH_PFC_PIN_GROUP(scifb0_data_d),
2764 SH_PFC_PIN_GROUP(scifb0_clk_d),
2765 SH_PFC_PIN_GROUP(scifb1_data),
2766 SH_PFC_PIN_GROUP(scifb1_clk),
2767 SH_PFC_PIN_GROUP(scifb1_ctrl),
2768 SH_PFC_PIN_GROUP(scifb1_data_b),
2769 SH_PFC_PIN_GROUP(scifb1_clk_b),
2770 SH_PFC_PIN_GROUP(scifb1_data_c),
2771 SH_PFC_PIN_GROUP(scifb1_clk_c),
2772 SH_PFC_PIN_GROUP(scifb1_data_d),
2773 SH_PFC_PIN_GROUP(scifb2_data),
2774 SH_PFC_PIN_GROUP(scifb2_clk),
2775 SH_PFC_PIN_GROUP(scifb2_ctrl),
2776 SH_PFC_PIN_GROUP(scifb2_data_b),
2777 SH_PFC_PIN_GROUP(scifb2_clk_b),
2778 SH_PFC_PIN_GROUP(scifb2_ctrl_b),
2779 SH_PFC_PIN_GROUP(scifb2_data_c),
2780 SH_PFC_PIN_GROUP(scifb2_clk_c),
2781 SH_PFC_PIN_GROUP(scifb2_data_d),
2782 SH_PFC_PIN_GROUP(sdhi0_data1),
2783 SH_PFC_PIN_GROUP(sdhi0_data4),
2784 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2785 SH_PFC_PIN_GROUP(sdhi0_cd),
2786 SH_PFC_PIN_GROUP(sdhi0_wp),
2787 SH_PFC_PIN_GROUP(sdhi1_data1),
2788 SH_PFC_PIN_GROUP(sdhi1_data4),
2789 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2790 SH_PFC_PIN_GROUP(sdhi1_cd),
2791 SH_PFC_PIN_GROUP(sdhi1_wp),
2792 SH_PFC_PIN_GROUP(sdhi2_data1),
2793 SH_PFC_PIN_GROUP(sdhi2_data4),
2794 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2795 SH_PFC_PIN_GROUP(sdhi2_cd),
2796 SH_PFC_PIN_GROUP(sdhi2_wp),
2797 SH_PFC_PIN_GROUP(usb0_pwen),
2798 SH_PFC_PIN_GROUP(usb0_ovc),
2799 SH_PFC_PIN_GROUP(usb1_pwen),
2800 SH_PFC_PIN_GROUP(usb1_ovc),
2801};
2802
2803static const char * const du_groups[] = {
2804 "du_rgb666",
2805 "du_rgb888",
2806 "du_clk_out_0",
2807 "du_clk_out_1",
2808 "du_sync_1",
2809 "du_cde_disp",
2810};
2811
2812static const char * const du0_groups[] = {
2813 "du0_clk_in",
2814};
2815
2816static const char * const du1_groups[] = {
2817 "du1_clk_in",
2818};
2819
2820static const char * const eth_groups[] = {
2821 "eth_link",
2822 "eth_magic",
2823 "eth_mdio",
2824 "eth_rmii",
2825};
2826
2827static const char * const intc_groups[] = {
2828 "intc_irq0",
2829 "intc_irq1",
2830 "intc_irq2",
2831 "intc_irq3",
2832};
2833
2834static const char * const mmc_groups[] = {
2835 "mmc_data1",
2836 "mmc_data4",
2837 "mmc_data8",
2838 "mmc_ctrl",
2839};
2840
2841static const char * const msiof0_groups[] = {
2842 "msiof0_clk",
2843 "msiof0_ctrl",
2844 "msiof0_data",
2845};
2846
2847static const char * const msiof1_groups[] = {
2848 "msiof1_clk",
2849 "msiof1_ctrl",
2850 "msiof1_data",
2851};
2852
2853static const char * const msiof2_groups[] = {
2854 "msiof2_clk",
2855 "msiof2_ctrl",
2856 "msiof2_data",
2857};
2858
2859static const char * const scif0_groups[] = {
2860 "scif0_data",
2861 "scif0_data_b",
2862 "scif0_data_c",
2863 "scif0_data_d",
2864 "scif0_data_e",
2865};
2866
2867static const char * const scif1_groups[] = {
2868 "scif1_data",
2869 "scif1_data_b",
2870 "scif1_clk_b",
2871 "scif1_data_c",
2872 "scif1_data_d",
2873};
2874
2875static const char * const scif2_groups[] = {
2876 "scif2_data",
2877 "scif2_data_b",
2878 "scif2_clk_b",
2879 "scif2_data_c",
2880 "scif2_data_e",
2881};
2882static const char * const scif3_groups[] = {
2883 "scif3_data",
2884 "scif3_clk",
2885 "scif3_data_b",
2886 "scif3_clk_b",
2887 "scif3_data_c",
2888 "scif3_data_d",
2889};
2890static const char * const scif4_groups[] = {
2891 "scif4_data",
2892 "scif4_data_b",
2893 "scif4_data_c",
2894};
2895static const char * const scif5_groups[] = {
2896 "scif5_data",
2897 "scif5_data_b",
2898};
2899static const char * const scifa0_groups[] = {
2900 "scifa0_data",
2901 "scifa0_data_b",
2902};
2903static const char * const scifa1_groups[] = {
2904 "scifa1_data",
2905 "scifa1_clk",
2906 "scifa1_data_b",
2907 "scifa1_clk_b",
2908 "scifa1_data_c",
2909};
2910static const char * const scifa2_groups[] = {
2911 "scifa2_data",
2912 "scifa2_clk",
2913 "scifa2_data_b",
2914};
2915static const char * const scifa3_groups[] = {
2916 "scifa3_data",
2917 "scifa3_clk",
2918 "scifa3_data_b",
2919 "scifa3_clk_b",
2920 "scifa3_data_c",
2921 "scifa3_clk_c",
2922};
2923static const char * const scifa4_groups[] = {
2924 "scifa4_data",
2925 "scifa4_data_b",
2926 "scifa4_data_c",
2927};
2928static const char * const scifa5_groups[] = {
2929 "scifa5_data",
2930 "scifa5_data_b",
2931 "scifa5_data_c",
2932};
2933static const char * const scifb0_groups[] = {
2934 "scifb0_data",
2935 "scifb0_clk",
2936 "scifb0_ctrl",
2937 "scifb0_data_b",
2938 "scifb0_clk_b",
2939 "scifb0_ctrl_b",
2940 "scifb0_data_c",
2941 "scifb0_clk_c",
2942 "scifb0_data_d",
2943 "scifb0_clk_d",
2944};
2945static const char * const scifb1_groups[] = {
2946 "scifb1_data",
2947 "scifb1_clk",
2948 "scifb1_ctrl",
2949 "scifb1_data_b",
2950 "scifb1_clk_b",
2951 "scifb1_data_c",
2952 "scifb1_clk_c",
2953 "scifb1_data_d",
2954};
2955static const char * const scifb2_groups[] = {
2956 "scifb2_data",
2957 "scifb2_clk",
2958 "scifb2_ctrl",
2959 "scifb2_data_b",
2960 "scifb2_clk_b",
2961 "scifb2_ctrl_b",
2962 "scifb0_data_c",
2963 "scifb2_clk_c",
2964 "scifb2_data_d",
2965};
2966
2967static const char * const sdhi0_groups[] = {
2968 "sdhi0_data1",
2969 "sdhi0_data4",
2970 "sdhi0_ctrl",
2971 "sdhi0_cd",
2972 "sdhi0_wp",
2973};
2974
2975static const char * const sdhi1_groups[] = {
2976 "sdhi1_data1",
2977 "sdhi1_data4",
2978 "sdhi1_ctrl",
2979 "sdhi1_cd",
2980 "sdhi1_wp",
2981};
2982
2983static const char * const sdhi2_groups[] = {
2984 "sdhi2_data1",
2985 "sdhi2_data4",
2986 "sdhi2_ctrl",
2987 "sdhi2_cd",
2988 "sdhi2_wp",
2989};
2990
2991static const char * const usb0_groups[] = {
2992 "usb0_pwen",
2993 "usb0_ovc",
2994};
2995static const char * const usb1_groups[] = {
2996 "usb1_pwen",
2997 "usb1_ovc",
2998};
2999
3000static const struct sh_pfc_function pinmux_functions[] = {
3001 SH_PFC_FUNCTION(du),
3002 SH_PFC_FUNCTION(du0),
3003 SH_PFC_FUNCTION(du1),
3004 SH_PFC_FUNCTION(eth),
3005 SH_PFC_FUNCTION(intc),
3006 SH_PFC_FUNCTION(mmc),
3007 SH_PFC_FUNCTION(msiof0),
3008 SH_PFC_FUNCTION(msiof1),
3009 SH_PFC_FUNCTION(msiof2),
3010 SH_PFC_FUNCTION(scif0),
3011 SH_PFC_FUNCTION(scif1),
3012 SH_PFC_FUNCTION(scif2),
3013 SH_PFC_FUNCTION(scif3),
3014 SH_PFC_FUNCTION(scif4),
3015 SH_PFC_FUNCTION(scif5),
3016 SH_PFC_FUNCTION(scifa0),
3017 SH_PFC_FUNCTION(scifa1),
3018 SH_PFC_FUNCTION(scifa2),
3019 SH_PFC_FUNCTION(scifa3),
3020 SH_PFC_FUNCTION(scifa4),
3021 SH_PFC_FUNCTION(scifa5),
3022 SH_PFC_FUNCTION(scifb0),
3023 SH_PFC_FUNCTION(scifb1),
3024 SH_PFC_FUNCTION(scifb2),
3025 SH_PFC_FUNCTION(sdhi0),
3026 SH_PFC_FUNCTION(sdhi1),
3027 SH_PFC_FUNCTION(sdhi2),
3028 SH_PFC_FUNCTION(usb0),
3029 SH_PFC_FUNCTION(usb1),
3030};
3031
3032static struct pinmux_cfg_reg pinmux_config_regs[] = {
3033 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3034 GP_0_31_FN, FN_IP1_22_20,
3035 GP_0_30_FN, FN_IP1_19_17,
3036 GP_0_29_FN, FN_IP1_16_14,
3037 GP_0_28_FN, FN_IP1_13_11,
3038 GP_0_27_FN, FN_IP1_10_8,
3039 GP_0_26_FN, FN_IP1_7_6,
3040 GP_0_25_FN, FN_IP1_5_4,
3041 GP_0_24_FN, FN_IP1_3_2,
3042 GP_0_23_FN, FN_IP1_1_0,
3043 GP_0_22_FN, FN_IP0_30_29,
3044 GP_0_21_FN, FN_IP0_28_27,
3045 GP_0_20_FN, FN_IP0_26_25,
3046 GP_0_19_FN, FN_IP0_24_23,
3047 GP_0_18_FN, FN_IP0_22_21,
3048 GP_0_17_FN, FN_IP0_20_19,
3049 GP_0_16_FN, FN_IP0_18_16,
3050 GP_0_15_FN, FN_IP0_15,
3051 GP_0_14_FN, FN_IP0_14,
3052 GP_0_13_FN, FN_IP0_13,
3053 GP_0_12_FN, FN_IP0_12,
3054 GP_0_11_FN, FN_IP0_11,
3055 GP_0_10_FN, FN_IP0_10,
3056 GP_0_9_FN, FN_IP0_9,
3057 GP_0_8_FN, FN_IP0_8,
3058 GP_0_7_FN, FN_IP0_7,
3059 GP_0_6_FN, FN_IP0_6,
3060 GP_0_5_FN, FN_IP0_5,
3061 GP_0_4_FN, FN_IP0_4,
3062 GP_0_3_FN, FN_IP0_3,
3063 GP_0_2_FN, FN_IP0_2,
3064 GP_0_1_FN, FN_IP0_1,
3065 GP_0_0_FN, FN_IP0_0, }
3066 },
3067 { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
3068 0, 0,
3069 0, 0,
3070 0, 0,
3071 0, 0,
3072 0, 0,
3073 0, 0,
3074 GP_1_25_FN, FN_IP3_21_20,
3075 GP_1_24_FN, FN_IP3_19_18,
3076 GP_1_23_FN, FN_IP3_17_16,
3077 GP_1_22_FN, FN_IP3_15_14,
3078 GP_1_21_FN, FN_IP3_13_12,
3079 GP_1_20_FN, FN_IP3_11_9,
3080 GP_1_19_FN, FN_RD_N,
3081 GP_1_18_FN, FN_IP3_8_6,
3082 GP_1_17_FN, FN_IP3_5_3,
3083 GP_1_16_FN, FN_IP3_2_0,
3084 GP_1_15_FN, FN_IP2_29_27,
3085 GP_1_14_FN, FN_IP2_26_25,
3086 GP_1_13_FN, FN_IP2_24_23,
3087 GP_1_12_FN, FN_EX_CS0_N,
3088 GP_1_11_FN, FN_IP2_22_21,
3089 GP_1_10_FN, FN_IP2_20_19,
3090 GP_1_9_FN, FN_IP2_18_16,
3091 GP_1_8_FN, FN_IP2_15_13,
3092 GP_1_7_FN, FN_IP2_12_10,
3093 GP_1_6_FN, FN_IP2_9_7,
3094 GP_1_5_FN, FN_IP2_6_5,
3095 GP_1_4_FN, FN_IP2_4_3,
3096 GP_1_3_FN, FN_IP2_2_0,
3097 GP_1_2_FN, FN_IP1_31_29,
3098 GP_1_1_FN, FN_IP1_28_26,
3099 GP_1_0_FN, FN_IP1_25_23, }
3100 },
3101 { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
3102 GP_2_31_FN, FN_IP6_7_6,
3103 GP_2_30_FN, FN_IP6_5_3,
3104 GP_2_29_FN, FN_IP6_2_0,
3105 GP_2_28_FN, FN_AUDIO_CLKA,
3106 GP_2_27_FN, FN_IP5_31_29,
3107 GP_2_26_FN, FN_IP5_28_26,
3108 GP_2_25_FN, FN_IP5_25_24,
3109 GP_2_24_FN, FN_IP5_23_22,
3110 GP_2_23_FN, FN_IP5_21_20,
3111 GP_2_22_FN, FN_IP5_19_17,
3112 GP_2_21_FN, FN_IP5_16_15,
3113 GP_2_20_FN, FN_IP5_14_12,
3114 GP_2_19_FN, FN_IP5_11_9,
3115 GP_2_18_FN, FN_IP5_8_6,
3116 GP_2_17_FN, FN_IP5_5_3,
3117 GP_2_16_FN, FN_IP5_2_0,
3118 GP_2_15_FN, FN_IP4_30_28,
3119 GP_2_14_FN, FN_IP4_27_26,
3120 GP_2_13_FN, FN_IP4_25_24,
3121 GP_2_12_FN, FN_IP4_23_22,
3122 GP_2_11_FN, FN_IP4_21,
3123 GP_2_10_FN, FN_IP4_20,
3124 GP_2_9_FN, FN_IP4_19,
3125 GP_2_8_FN, FN_IP4_18_16,
3126 GP_2_7_FN, FN_IP4_15_13,
3127 GP_2_6_FN, FN_IP4_12_10,
3128 GP_2_5_FN, FN_IP4_9_8,
3129 GP_2_4_FN, FN_IP4_7_5,
3130 GP_2_3_FN, FN_IP4_4_2,
3131 GP_2_2_FN, FN_IP4_1_0,
3132 GP_2_1_FN, FN_IP3_30_28,
3133 GP_2_0_FN, FN_IP3_27_25 }
3134 },
3135 { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
3136 GP_3_31_FN, FN_IP9_18_17,
3137 GP_3_30_FN, FN_IP9_16,
3138 GP_3_29_FN, FN_IP9_15_13,
3139 GP_3_28_FN, FN_IP9_12,
3140 GP_3_27_FN, FN_IP9_11,
3141 GP_3_26_FN, FN_IP9_10_8,
3142 GP_3_25_FN, FN_IP9_7,
3143 GP_3_24_FN, FN_IP9_6,
3144 GP_3_23_FN, FN_IP9_5_3,
3145 GP_3_22_FN, FN_IP9_2_0,
3146 GP_3_21_FN, FN_IP8_30_28,
3147 GP_3_20_FN, FN_IP8_27_26,
3148 GP_3_19_FN, FN_IP8_25_24,
3149 GP_3_18_FN, FN_IP8_23_21,
3150 GP_3_17_FN, FN_IP8_20_18,
3151 GP_3_16_FN, FN_IP8_17_15,
3152 GP_3_15_FN, FN_IP8_14_12,
3153 GP_3_14_FN, FN_IP8_11_9,
3154 GP_3_13_FN, FN_IP8_8_6,
3155 GP_3_12_FN, FN_IP8_5_3,
3156 GP_3_11_FN, FN_IP8_2_0,
3157 GP_3_10_FN, FN_IP7_29_27,
3158 GP_3_9_FN, FN_IP7_26_24,
3159 GP_3_8_FN, FN_IP7_23_21,
3160 GP_3_7_FN, FN_IP7_20_19,
3161 GP_3_6_FN, FN_IP7_18_17,
3162 GP_3_5_FN, FN_IP7_16_15,
3163 GP_3_4_FN, FN_IP7_14_13,
3164 GP_3_3_FN, FN_IP7_12_11,
3165 GP_3_2_FN, FN_IP7_10_9,
3166 GP_3_1_FN, FN_IP7_8_6,
3167 GP_3_0_FN, FN_IP7_5_3 }
3168 },
3169 { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
3170 GP_4_31_FN, FN_IP15_5_4,
3171 GP_4_30_FN, FN_IP15_3_2,
3172 GP_4_29_FN, FN_IP15_1_0,
3173 GP_4_28_FN, FN_IP11_8_6,
3174 GP_4_27_FN, FN_IP11_5_3,
3175 GP_4_26_FN, FN_IP11_2_0,
3176 GP_4_25_FN, FN_IP10_31_29,
3177 GP_4_24_FN, FN_IP10_28_27,
3178 GP_4_23_FN, FN_IP10_26_25,
3179 GP_4_22_FN, FN_IP10_24_22,
3180 GP_4_21_FN, FN_IP10_21_19,
3181 GP_4_20_FN, FN_IP10_18_17,
3182 GP_4_19_FN, FN_IP10_16_15,
3183 GP_4_18_FN, FN_IP10_14_12,
3184 GP_4_17_FN, FN_IP10_11_9,
3185 GP_4_16_FN, FN_IP10_8_6,
3186 GP_4_15_FN, FN_IP10_5_3,
3187 GP_4_14_FN, FN_IP10_2_0,
3188 GP_4_13_FN, FN_IP9_31_29,
3189 GP_4_12_FN, FN_VI0_DATA7_VI0_B7,
3190 GP_4_11_FN, FN_VI0_DATA6_VI0_B6,
3191 GP_4_10_FN, FN_VI0_DATA5_VI0_B5,
3192 GP_4_9_FN, FN_VI0_DATA4_VI0_B4,
3193 GP_4_8_FN, FN_IP9_28_27,
3194 GP_4_7_FN, FN_VI0_DATA2_VI0_B2,
3195 GP_4_6_FN, FN_VI0_DATA1_VI0_B1,
3196 GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
3197 GP_4_4_FN, FN_IP9_26_25,
3198 GP_4_3_FN, FN_IP9_24_23,
3199 GP_4_2_FN, FN_IP9_22_21,
3200 GP_4_1_FN, FN_IP9_20_19,
3201 GP_4_0_FN, FN_VI0_CLK }
3202 },
3203 { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
3204 GP_5_31_FN, FN_IP3_24_22,
3205 GP_5_30_FN, FN_IP13_9_7,
3206 GP_5_29_FN, FN_IP13_6_5,
3207 GP_5_28_FN, FN_IP13_4_3,
3208 GP_5_27_FN, FN_IP13_2_0,
3209 GP_5_26_FN, FN_IP12_29_27,
3210 GP_5_25_FN, FN_IP12_26_24,
3211 GP_5_24_FN, FN_IP12_23_22,
3212 GP_5_23_FN, FN_IP12_21_20,
3213 GP_5_22_FN, FN_IP12_19_18,
3214 GP_5_21_FN, FN_IP12_17_16,
3215 GP_5_20_FN, FN_IP12_15_13,
3216 GP_5_19_FN, FN_IP12_12_10,
3217 GP_5_18_FN, FN_IP12_9_7,
3218 GP_5_17_FN, FN_IP12_6_4,
3219 GP_5_16_FN, FN_IP12_3_2,
3220 GP_5_15_FN, FN_IP12_1_0,
3221 GP_5_14_FN, FN_IP11_31_30,
3222 GP_5_13_FN, FN_IP11_29_28,
3223 GP_5_12_FN, FN_IP11_27,
3224 GP_5_11_FN, FN_IP11_26,
3225 GP_5_10_FN, FN_IP11_25,
3226 GP_5_9_FN, FN_IP11_24,
3227 GP_5_8_FN, FN_IP11_23,
3228 GP_5_7_FN, FN_IP11_22,
3229 GP_5_6_FN, FN_IP11_21,
3230 GP_5_5_FN, FN_IP11_20,
3231 GP_5_4_FN, FN_IP11_19,
3232 GP_5_3_FN, FN_IP11_18_17,
3233 GP_5_2_FN, FN_IP11_16_15,
3234 GP_5_1_FN, FN_IP11_14_12,
3235 GP_5_0_FN, FN_IP11_11_9 }
3236 },
3237 { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
3238 GP_6_31_FN, FN_DU0_DOTCLKIN,
3239 GP_6_30_FN, FN_USB1_OVC,
3240 GP_6_29_FN, FN_IP14_31_29,
3241 GP_6_28_FN, FN_IP14_28_26,
3242 GP_6_27_FN, FN_IP14_25_23,
3243 GP_6_26_FN, FN_IP14_22_20,
3244 GP_6_25_FN, FN_IP14_19_17,
3245 GP_6_24_FN, FN_IP14_16_14,
3246 GP_6_23_FN, FN_IP14_13_11,
3247 GP_6_22_FN, FN_IP14_10_8,
3248 GP_6_21_FN, FN_IP14_7,
3249 GP_6_20_FN, FN_IP14_6,
3250 GP_6_19_FN, FN_IP14_5,
3251 GP_6_18_FN, FN_IP14_4,
3252 GP_6_17_FN, FN_IP14_3,
3253 GP_6_16_FN, FN_IP14_2,
3254 GP_6_15_FN, FN_IP14_1_0,
3255 GP_6_14_FN, FN_IP13_30_28,
3256 GP_6_13_FN, FN_IP13_27,
3257 GP_6_12_FN, FN_IP13_26,
3258 GP_6_11_FN, FN_IP13_25,
3259 GP_6_10_FN, FN_IP13_24_23,
3260 GP_6_9_FN, FN_IP13_22,
3261 0, 0,
3262 GP_6_7_FN, FN_IP13_21_19,
3263 GP_6_6_FN, FN_IP13_18_16,
3264 GP_6_5_FN, FN_IP13_15,
3265 GP_6_4_FN, FN_IP13_14,
3266 GP_6_3_FN, FN_IP13_13,
3267 GP_6_2_FN, FN_IP13_12,
3268 GP_6_1_FN, FN_IP13_11,
3269 GP_6_0_FN, FN_IP13_10 }
3270 },
3271 { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
3272 0, 0,
3273 0, 0,
3274 0, 0,
3275 0, 0,
3276 0, 0,
3277 0, 0,
3278 GP_7_25_FN, FN_USB1_PWEN,
3279 GP_7_24_FN, FN_USB0_OVC,
3280 GP_7_23_FN, FN_USB0_PWEN,
3281 GP_7_22_FN, FN_IP15_14_12,
3282 GP_7_21_FN, FN_IP15_11_9,
3283 GP_7_20_FN, FN_IP15_8_6,
3284 GP_7_19_FN, FN_IP7_2_0,
3285 GP_7_18_FN, FN_IP6_29_27,
3286 GP_7_17_FN, FN_IP6_26_24,
3287 GP_7_16_FN, FN_IP6_23_21,
3288 GP_7_15_FN, FN_IP6_20_19,
3289 GP_7_14_FN, FN_IP6_18_16,
3290 GP_7_13_FN, FN_IP6_15_14,
3291 GP_7_12_FN, FN_IP6_13_12,
3292 GP_7_11_FN, FN_IP6_11_10,
3293 GP_7_10_FN, FN_IP6_9_8,
3294 GP_7_9_FN, FN_IP16_11_10,
3295 GP_7_8_FN, FN_IP16_9_8,
3296 GP_7_7_FN, FN_IP16_7_6,
3297 GP_7_6_FN, FN_IP16_5_3,
3298 GP_7_5_FN, FN_IP16_2_0,
3299 GP_7_4_FN, FN_IP15_29_27,
3300 GP_7_3_FN, FN_IP15_26_24,
3301 GP_7_2_FN, FN_IP15_23_21,
3302 GP_7_1_FN, FN_IP15_20_18,
3303 GP_7_0_FN, FN_IP15_17_15 }
3304 },
3305 { PINMUX_CFG_REG_VAR("IPSR0", 0xE6060020, 32,
3306 1, 2, 2, 2, 2, 2, 2, 3, 1, 1, 1, 1, 1, 1, 1, 1,
3307 1, 1, 1, 1, 1, 1, 1, 1) {
3308 /* IP0_31 [1] */
3309 0, 0,
3310 /* IP0_30_29 [2] */
3311 FN_A6, FN_MSIOF1_SCK,
3312 0, 0,
3313 /* IP0_28_27 [2] */
3314 FN_A5, FN_MSIOF0_RXD_B,
3315 0, 0,
3316 /* IP0_26_25 [2] */
3317 FN_A4, FN_MSIOF0_TXD_B,
3318 0, 0,
3319 /* IP0_24_23 [2] */
3320 FN_A3, FN_MSIOF0_SS2_B,
3321 0, 0,
3322 /* IP0_22_21 [2] */
3323 FN_A2, FN_MSIOF0_SS1_B,
3324 0, 0,
3325 /* IP0_20_19 [2] */
3326 FN_A1, FN_MSIOF0_SYNC_B,
3327 0, 0,
3328 /* IP0_18_16 [3] */
3329 FN_A0, FN_ATAWR0_N_C, FN_MSIOF0_SCK_B, FN_SCL0_C, FN_PWM2_B,
3330 0, 0, 0,
3331 /* IP0_15 [1] */
3332 FN_D15, 0,
3333 /* IP0_14 [1] */
3334 FN_D14, 0,
3335 /* IP0_13 [1] */
3336 FN_D13, 0,
3337 /* IP0_12 [1] */
3338 FN_D12, 0,
3339 /* IP0_11 [1] */
3340 FN_D11, 0,
3341 /* IP0_10 [1] */
3342 FN_D10, 0,
3343 /* IP0_9 [1] */
3344 FN_D9, 0,
3345 /* IP0_8 [1] */
3346 FN_D8, 0,
3347 /* IP0_7 [1] */
3348 FN_D7, 0,
3349 /* IP0_6 [1] */
3350 FN_D6, 0,
3351 /* IP0_5 [1] */
3352 FN_D5, 0,
3353 /* IP0_4 [1] */
3354 FN_D4, 0,
3355 /* IP0_3 [1] */
3356 FN_D3, 0,
3357 /* IP0_2 [1] */
3358 FN_D2, 0,
3359 /* IP0_1 [1] */
3360 FN_D1, 0,
3361 /* IP0_0 [1] */
3362 FN_D0, 0, }
3363 },
3364 { PINMUX_CFG_REG_VAR("IPSR1", 0xE6060024, 32,
3365 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2, 2) {
3366 /* IP1_31_29 [3] */
3367 FN_A18, FN_DREQ1, FN_SCIFA1_RXD_C, 0, FN_SCIFB1_RXD_C,
3368 0, 0, 0,
3369 /* IP1_28_26 [3] */
3370 FN_A17, FN_DACK2_B, 0, FN_SDA0_C,
3371 0, 0, 0, 0,
3372 /* IP1_25_23 [3] */
3373 FN_A16, FN_DREQ2_B, FN_FMCLK_C, 0, FN_SCIFA1_SCK_B,
3374 0, 0, 0,
3375 /* IP1_22_20 [3] */
3376 FN_A15, FN_BPFCLK_C,
3377 0, 0, 0, 0, 0, 0,
3378 /* IP1_19_17 [3] */
3379 FN_A14, FN_ATADIR0_N_C, FN_FMIN, FN_FMIN_C, FN_MSIOF1_SYNC_D,
3380 0, 0, 0,
3381 /* IP1_16_14 [3] */
3382 FN_A13, FN_ATAG0_N_C, FN_BPFCLK, FN_MSIOF1_SS1_D,
3383 0, 0, 0, 0,
3384 /* IP1_13_11 [3] */
3385 FN_A12, FN_FMCLK, FN_SDA3_D, FN_MSIOF1_SCK_D,
3386 0, 0, 0, 0,
3387 /* IP1_10_8 [3] */
3388 FN_A11, FN_MSIOF1_RXD, FN_SCL3_D, FN_MSIOF1_RXD_D,
3389 0, 0, 0, 0,
3390 /* IP1_7_6 [2] */
3391 FN_A10, FN_MSIOF1_TXD, 0, FN_MSIOF1_TXD_D,
3392 /* IP1_5_4 [2] */
3393 FN_A9, FN_MSIOF1_SS2, FN_SDA0, 0,
3394 /* IP1_3_2 [2] */
3395 FN_A8, FN_MSIOF1_SS1, FN_SCL0, 0,
3396 /* IP1_1_0 [2] */
3397 FN_A7, FN_MSIOF1_SYNC,
3398 0, 0, }
3399 },
3400 { PINMUX_CFG_REG_VAR("IPSR2", 0xE6060028, 32,
3401 2, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2, 3) {
3402 /* IP2_31_20 [2] */
3403 0, 0, 0, 0,
3404 /* IP2_29_27 [3] */
3405 FN_EX_CS3_N, FN_ATADIR0_N, FN_MSIOF2_TXD,
3406 FN_ATAG0_N, 0, FN_EX_WAIT1,
3407 0, 0,
3408 /* IP2_26_25 [2] */
3409 FN_EX_CS2_N, FN_ATAWR0_N, FN_MSIOF2_SYNC, 0,
3410 /* IP2_24_23 [2] */
3411 FN_EX_CS1_N, FN_MSIOF2_SCK, 0, 0,
3412 /* IP2_22_21 [2] */
3413 FN_CS1_N_A26, FN_ATADIR0_N_B, FN_SDA1, 0,
3414 /* IP2_20_19 [2] */
3415 FN_CS0_N, FN_ATAG0_N_B, FN_SCL1, 0,
3416 /* IP2_18_16 [3] */
3417 FN_A25, FN_DACK2, FN_SSL, FN_DREQ1_C, FN_RX1, FN_SCIFA1_RXD,
3418 0, 0,
3419 /* IP2_15_13 [3] */
3420 FN_A24, FN_DREQ2, FN_IO3, FN_TX1, FN_SCIFA1_TXD,
3421 0, 0, 0,
3422 /* IP2_12_0 [3] */
3423 FN_A23, FN_IO2, FN_BPFCLK_B, FN_RX0, FN_SCIFA0_RXD,
3424 0, 0, 0,
3425 /* IP2_9_7 [3] */
3426 FN_A22, FN_MISO_IO1, FN_FMCLK_B, FN_TX0, FN_SCIFA0_TXD,
3427 0, 0, 0,
3428 /* IP2_6_5 [2] */
3429 FN_A21, FN_ATAWR0_N_B, FN_MOSI_IO0, 0,
3430 /* IP2_4_3 [2] */
3431 FN_A20, FN_SPCLK, 0, 0,
3432 /* IP2_2_0 [3] */
3433 FN_A19, FN_DACK1, FN_SCIFA1_TXD_C, 0,
3434 FN_SCIFB1_TXD_C, 0, FN_SCIFB1_SCK_B, 0, }
3435 },
3436 { PINMUX_CFG_REG_VAR("IPSR3", 0xE606002C, 32,
3437 1, 3, 3, 3, 2, 2, 2, 2, 2, 3, 3, 3, 3) {
3438 /* IP3_31 [1] */
3439 0, 0,
3440 /* IP3_30_28 [3] */
3441 FN_SSI_WS0129, FN_HTX0_C, FN_HTX2_C,
3442 FN_SCIFB0_TXD_C, FN_SCIFB2_TXD_C,
3443 0, 0, 0,
3444 /* IP3_27_25 [3] */
3445 FN_SSI_SCK0129, FN_HRX0_C, FN_HRX2_C,
3446 FN_SCIFB0_RXD_C, FN_SCIFB2_RXD_C,
3447 0, 0, 0,
3448 /* IP3_24_22 [3] */
3449 FN_SPEEDIN, 0, FN_HSCK0_C, FN_HSCK2_C, FN_SCIFB0_SCK_B,
3450 FN_SCIFB2_SCK_B, FN_DREQ2_C, FN_HTX2_D,
3451 /* IP3_21_20 [2] */
3452 FN_DACK0, FN_DRACK0, FN_REMOCON, 0,
3453 /* IP3_19_18 [2] */
3454 FN_DREQ0, FN_PWM3, FN_TPU_TO3, 0,
3455 /* IP3_17_16 [2] */
3456 FN_EX_WAIT0, FN_HRTS2_N_B, FN_SCIFB0_CTS_N_B, 0,
3457 /* IP3_15_14 [2] */
3458 FN_WE1_N, FN_ATARD0_N_B, FN_HTX2_B, FN_SCIFB0_RTS_N_B,
3459 /* IP3_13_12 [2] */
3460 FN_WE0_N, FN_HCTS2_N_B, FN_SCIFB0_TXD_B, 0,
3461 /* IP3_11_9 [3] */
3462 FN_RD_WR_N, FN_HRX2_B, FN_FMIN_B, FN_SCIFB0_RXD_B, FN_DREQ1_D,
3463 0, 0, 0,
3464 /* IP3_8_6 [3] */
3465 FN_BS_N, FN_ATACS10_N, FN_MSIOF2_SS2, FN_HTX1_B,
3466 FN_SCIFB1_TXD_B, FN_PWM2, FN_TPU_TO2, 0,
3467 /* IP3_5_3 [3] */
3468 FN_EX_CS5_N, FN_ATACS00_N, FN_MSIOF2_SS1, FN_HRX1_B,
3469 FN_SCIFB1_RXD_B, FN_PWM1, FN_TPU_TO1, 0,
3470 /* IP3_2_0 [3] */
3471 FN_EX_CS4_N, FN_ATARD0_N, FN_MSIOF2_RXD, 0, FN_EX_WAIT2,
3472 0, 0, 0, }
3473 },
3474 { PINMUX_CFG_REG_VAR("IPSR4", 0xE6060030, 32,
3475 1, 3, 2, 2, 2, 1, 1, 1, 3, 3, 3, 2, 3, 3, 2) {
3476 /* IP4_31 [1] */
3477 0, 0,
3478 /* IP4_30_28 [3] */
3479 FN_SSI_SCK5, FN_MSIOF1_SCK_C, FN_TS_SDATA0, FN_GLO_I0,
3480 FN_MSIOF2_SYNC_D, FN_VI1_R2_B,
3481 0, 0,
3482 /* IP4_27_26 [2] */
3483 FN_SSI_SDATA4, FN_MSIOF2_SCK_D, 0, 0,
3484 /* IP4_25_24 [2] */
3485 FN_SSI_WS4, FN_GLO_RFON_D, 0, 0,
3486 /* IP4_23_22 [2] */
3487 FN_SSI_SCK4, FN_GLO_SS_D, 0, 0,
3488 /* IP4_21 [1] */
3489 FN_SSI_SDATA3, 0,
3490 /* IP4_20 [1] */
3491 FN_SSI_WS34, 0,
3492 /* IP4_19 [1] */
3493 FN_SSI_SCK34, 0,
3494 /* IP4_18_16 [3] */
3495 FN_SSI_SDATA2, FN_GPS_MAG_B, FN_TX2_E, FN_HRTS1_N_E,
3496 0, 0, 0, 0,
3497 /* IP4_15_13 [3] */
3498 FN_SSI_WS2, FN_SDA2, FN_GPS_SIGN_B, FN_RX2_E,
3499 FN_GLO_Q1_D, FN_HCTS1_N_E,
3500 0, 0,
3501 /* IP4_12_10 [3] */
3502 FN_SSI_SCK2, FN_SCL2, FN_GPS_CLK_B, FN_GLO_Q0_D, FN_HSCK1_E,
3503 0, 0, 0,
3504 /* IP4_9_8 [2] */
3505 FN_SSI_SDATA1, FN_SDA1_B, FN_SDA8_B, FN_MSIOF2_RXD_C,
3506 /* IP4_7_5 [3] */
3507 FN_SSI_WS1, FN_SCL1_B, FN_SCL8_B, FN_MSIOF2_TXD_C, FN_GLO_I1_D,
3508 0, 0, 0,
3509 /* IP4_4_2 [3] */
3510 FN_SSI_SCK1, FN_SDA0_B, FN_SDA7_B,
3511 FN_MSIOF2_SYNC_C, FN_GLO_I0_D,
3512 0, 0, 0,
3513 /* IP4_1_0 [2] */
3514 FN_SSI_SDATA0, FN_SCL0_B, FN_SCL7_B, FN_MSIOF2_SCK_C, }
3515 },
3516 { PINMUX_CFG_REG_VAR("IPSR5", 0xE6060034, 32,
3517 3, 3, 2, 2, 2, 3, 2, 3, 3, 3, 3, 3) {
3518 /* IP5_31_29 [3] */
3519 FN_SSI_SDATA9, FN_RX3_D, FN_CAN0_RX_D,
3520 0, 0, 0, 0, 0,
3521 /* IP5_28_26 [3] */
3522 FN_SSI_WS9, FN_TX3_D, FN_CAN0_TX_D, FN_GLO_SDATA_D,
3523 0, 0, 0, 0,
3524 /* IP5_25_24 [2] */
3525 FN_SSI_SCK9, FN_RX1_D, FN_GLO_SCLK_D, 0,
3526 /* IP5_23_22 [2] */
3527 FN_SSI_SDATA8, FN_TX1_D, FN_STP_ISSYNC_0_B, 0,
3528 /* IP5_21_20 [2] */
3529 FN_SSI_SDATA7, FN_RX0_D, FN_STP_ISEN_0_B, 0,
3530 /* IP5_19_17 [3] */
3531 FN_SSI_WS78, FN_TX0_D, FN_STP_ISD_0_B, FN_GLO_RFON,
3532 0, 0, 0, 0,
3533 /* IP5_16_15 [2] */
3534 FN_SSI_SCK78, FN_STP_ISCLK_0_B, FN_GLO_SS, 0,
3535 /* IP5_14_12 [3] */
3536 FN_SSI_SDATA6, FN_STP_IVCXO27_0_B, FN_GLO_SDATA, FN_VI1_R7_B,
3537 0, 0, 0, 0,
3538 /* IP5_11_9 [3] */
3539 FN_SSI_WS6, FN_GLO_SCLK, FN_MSIOF2_SS2_D, FN_VI1_R6_B,
3540 0, 0, 0, 0,
3541 /* IP5_8_6 [3] */
3542 FN_SSI_SCK6, FN_MSIOF1_RXD_C, FN_TS_SPSYNC0, FN_GLO_Q1,
3543 FN_MSIOF2_RXD_D, FN_VI1_R5_B,
3544 0, 0,
3545 /* IP5_5_3 [3] */
3546 FN_SSI_SDATA5, FN_MSIOF1_TXD_C, FN_TS_SDEN0, FN_GLO_Q0,
3547 FN_MSIOF2_SS1_D, FN_VI1_R4_B,
3548 0, 0,
3549 /* IP5_2_0 [3] */
3550 FN_SSI_WS5, FN_MSIOF1_SYNC_C, FN_TS_SCK0, FN_GLO_I1,
3551 FN_MSIOF2_TXD_D, FN_VI1_R3_B,
3552 0, 0, }
3553 },
3554 { PINMUX_CFG_REG_VAR("IPSR6", 0xE6060038, 32,
3555 2, 3, 3, 3, 2, 3, 2, 2, 2, 2, 2, 3, 3) {
3556 /* IP6_31_30 [2] */
3557 0, 0, 0, 0,
3558 /* IP6_29_27 [3] */
3559 FN_IRQ8, FN_HRTS1_N_C, FN_MSIOF1_RXD_B,
3560 FN_GPS_SIGN_C, FN_GPS_SIGN_D,
3561 0, 0, 0,
3562 /* IP6_26_24 [3] */
3563 FN_IRQ7, FN_HCTS1_N_C, FN_MSIOF1_TXD_B,
3564 FN_GPS_CLK_C, FN_GPS_CLK_D,
3565 0, 0, 0,
3566 /* IP6_23_21 [3] */
3567 FN_IRQ6, FN_HSCK1_C, FN_MSIOF1_SS2_B,
3568 FN_SDA1_E, FN_MSIOF2_SYNC_E,
3569 0, 0, 0,
3570 /* IP6_20_19 [2] */
3571 FN_IRQ5, FN_HTX1_C, FN_SCL1_E, FN_MSIOF2_SCK_E,
3572 /* IP6_18_16 [3] */
3573 FN_IRQ4, FN_HRX1_C, FN_SDA4_C, FN_MSIOF2_RXD_E, FN_INTC_IRQ4_N,
3574 0, 0, 0,
3575 /* IP6_15_14 [2] */
3576 FN_IRQ3, FN_SCL4_C, FN_MSIOF2_TXD_E, FN_INTC_IRQ3_N,
3577 /* IP6_13_12 [2] */
3578 FN_IRQ2, FN_SCIFB1_TXD_D, FN_INTC_IRQ2_N, 0,
3579 /* IP6_11_10 [2] */
3580 FN_IRQ1, FN_SCIFB1_SCK_C, FN_INTC_IRQ1_N, 0,
3581 /* IP6_9_8 [2] */
3582 FN_IRQ0, FN_SCIFB1_RXD_D, FN_INTC_IRQ0_N, 0,
3583 /* IP6_7_6 [2] */
3584 FN_AUDIO_CLKOUT, FN_MSIOF1_SS1_B, FN_TX2, FN_SCIFA2_TXD,
3585 /* IP6_5_3 [3] */
3586 FN_AUDIO_CLKC, FN_SCIFB0_SCK_C, FN_MSIOF1_SYNC_B, FN_RX2,
3587 FN_SCIFA2_RXD, FN_FMIN_E,
3588 0, 0,
3589 /* IP6_2_0 [3] */
3590 FN_AUDIO_CLKB, FN_STP_OPWM_0_B, FN_MSIOF1_SCK_B,
3591 FN_SCIF_CLK, 0, FN_BPFCLK_E,
3592 0, 0, }
3593 },
3594 { PINMUX_CFG_REG_VAR("IPSR7", 0xE606003C, 32,
3595 2, 3, 3, 3, 2, 2, 2, 2, 2, 2, 3, 3, 3) {
3596 /* IP7_31_30 [2] */
3597 0, 0, 0, 0,
3598 /* IP7_29_27 [3] */
3599 FN_DU1_DG2, FN_LCDOUT10, FN_VI1_DATA4_B, FN_SCIF1_SCK_B,
3600 FN_SCIFA1_SCK, FN_SSI_SCK78_B,
3601 0, 0,
3602 /* IP7_26_24 [3] */
3603 FN_DU1_DG1, FN_LCDOUT9, FN_VI1_DATA3_B, FN_RX1_B,
3604 FN_SCIFA1_RXD_B, FN_MSIOF2_SS2_B,
3605 0, 0,
3606 /* IP7_23_21 [3] */
3607 FN_DU1_DG0, FN_LCDOUT8, FN_VI1_DATA2_B, FN_TX1_B,
3608 FN_SCIFA1_TXD_B, FN_MSIOF2_SS1_B,
3609 0, 0,
3610 /* IP7_20_19 [2] */
3611 FN_DU1_DR7, FN_LCDOUT7, FN_SSI_SDATA1_B, 0,
3612 /* IP7_18_17 [2] */
3613 FN_DU1_DR6, FN_LCDOUT6, FN_SSI_WS1_B, 0,
3614 /* IP7_16_15 [2] */
3615 FN_DU1_DR5, FN_LCDOUT5, FN_SSI_SCK1_B, 0,
3616 /* IP7_14_13 [2] */
3617 FN_DU1_DR4, FN_LCDOUT4, FN_SSI_SDATA0_B, 0,
3618 /* IP7_12_11 [2] */
3619 FN_DU1_DR3, FN_LCDOUT3, FN_SSI_WS0129_B, 0,
3620 /* IP7_10_9 [2] */
3621 FN_DU1_DR2, FN_LCDOUT2, FN_SSI_SCK0129_B, 0,
3622 /* IP7_8_6 [3] */
3623 FN_DU1_DR1, FN_LCDOUT1, FN_VI1_DATA1_B, FN_RX0_B,
3624 FN_SCIFA0_RXD_B, FN_MSIOF2_SYNC_B,
3625 0, 0,
3626 /* IP7_5_3 [3] */
3627 FN_DU1_DR0, FN_LCDOUT0, FN_VI1_DATA0_B, FN_TX0_B,
3628 FN_SCIFA0_TXD_B, FN_MSIOF2_SCK_B,
3629 0, 0,
3630 /* IP7_2_0 [3] */
3631 FN_IRQ9, FN_DU1_DOTCLKIN_B, FN_CAN_CLK_D, FN_GPS_MAG_C,
3632 FN_SCIF_CLK_B, FN_GPS_MAG_D,
3633 0, 0, }
3634 },
3635 { PINMUX_CFG_REG_VAR("IPSR8", 0xE6060040, 32,
3636 1, 3, 2, 2, 3, 3, 3, 3, 3, 3, 3, 3) {
3637 /* IP8_31 [1] */
3638 0, 0,
3639 /* IP8_30_28 [3] */
3640 FN_DU1_DB5, FN_LCDOUT21, FN_TX3, FN_SCIFA3_TXD, FN_CAN1_TX,
3641 0, 0, 0,
3642 /* IP8_27_26 [2] */
3643 FN_DU1_DB4, FN_LCDOUT20, FN_VI1_FIELD_B, FN_CAN1_RX,
3644 /* IP8_25_24 [2] */
3645 FN_DU1_DB3, FN_LCDOUT19, FN_VI1_CLKENB_B, 0,
3646 /* IP8_23_21 [3] */
3647 FN_DU1_DB2, FN_LCDOUT18, FN_VI1_VSYNC_N_B, FN_SCIF2_SCK_B,
3648 FN_SCIFA2_SCK, FN_SSI_SDATA9_B,
3649 0, 0,
3650 /* IP8_20_18 [3] */
3651 FN_DU1_DB1, FN_LCDOUT17, FN_VI1_HSYNC_N_B, FN_RX2_B,
3652 FN_SCIFA2_RXD_B, FN_MSIOF2_RXD_B,
3653 0, 0,
3654 /* IP8_17_15 [3] */
3655 FN_DU1_DB0, FN_LCDOUT16, FN_VI1_CLK_B, FN_TX2_B,
3656 FN_SCIFA2_TXD_B, FN_MSIOF2_TXD_B,
3657 0, 0,
3658 /* IP8_14_12 [3] */
3659 FN_DU1_DG7, FN_LCDOUT15, FN_HTX0_B,
3660 FN_SCIFB2_RTS_N_B, FN_SSI_WS9_B,
3661 0, 0, 0,
3662 /* IP8_11_9 [3] */
3663 FN_DU1_DG6, FN_LCDOUT14, FN_HRTS0_N_B,
3664 FN_SCIFB2_CTS_N_B, FN_SSI_SCK9_B,
3665 0, 0, 0,
3666 /* IP8_8_6 [3] */
3667 FN_DU1_DG5, FN_LCDOUT13, FN_VI1_DATA7_B, FN_HCTS0_N_B,
3668 FN_SCIFB2_TXD_B, FN_SSI_SDATA8_B,
3669 0, 0,
3670 /* IP8_5_3 [3] */
3671 FN_DU1_DG4, FN_LCDOUT12, FN_VI1_DATA6_B, FN_HRX0_B,
3672 FN_SCIFB2_RXD_B, FN_SSI_SDATA7_B,
3673 0, 0,
3674 /* IP8_2_0 [3] */
3675 FN_DU1_DG3, FN_LCDOUT11, FN_VI1_DATA5_B, 0, FN_SSI_WS78_B,
3676 0, 0, 0, }
3677 },
3678 { PINMUX_CFG_REG_VAR("IPSR9", 0xE6060044, 32,
3679 3, 2, 2, 2, 2, 2, 2, 1, 3, 1, 1, 3, 1, 1, 3, 3) {
3680 /* IP9_31_29 [3] */
3681 FN_VI0_G0, FN_SCL8, FN_STP_IVCXO27_0_C, FN_SCL4,
3682 FN_HCTS2_N, FN_SCIFB2_CTS_N, FN_ATAWR1_N, 0,
3683 /* IP9_28_27 [2] */
3684 FN_VI0_DATA3_VI0_B3, FN_SCIF3_SCK_B, FN_SCIFA3_SCK_B, 0,
3685 /* IP9_26_25 [2] */
3686 FN_VI0_VSYNC_N, FN_RX5, FN_SCIFA5_RXD, FN_TS_SPSYNC0_D,
3687 /* IP9_24_23 [2] */
3688 FN_VI0_HSYNC_N, FN_TX5, FN_SCIFA5_TXD, FN_TS_SDEN0_D,
3689 /* IP9_22_21 [2] */
3690 FN_VI0_FIELD, FN_RX4, FN_SCIFA4_RXD, FN_TS_SCK0_D,
3691 /* IP9_20_19 [2] */
3692 FN_VI0_CLKENB, FN_TX4, FN_SCIFA4_TXD, FN_TS_SDATA0_D,
3693 /* IP9_18_17 [2] */
3694 FN_DU1_CDE, FN_QPOLB, FN_PWM4_B, 0,
3695 /* IP9_16 [1] */
3696 FN_DU1_DISP, FN_QPOLA,
3697 /* IP9_15_13 [3] */
3698 FN_DU1_EXODDF_DU1_ODDF_DISP_CDE, FN_QCPV_QDE,
3699 FN_CAN0_RX, FN_RX3_B, FN_SDA2_B,
3700 0, 0, 0,
3701 /* IP9_12 [1] */
3702 FN_DU1_EXVSYNC_DU1_VSYNC, FN_QSTB_QHE,
3703 /* IP9_11 [1] */
3704 FN_DU1_EXHSYNC_DU1_HSYNC, FN_QSTH_QHS,
3705 /* IP9_10_8 [3] */
3706 FN_DU1_DOTCLKOUT1, FN_QSTVB_QVE, FN_CAN0_TX,
3707 FN_TX3_B, FN_SCL2_B, FN_PWM4,
3708 0, 0,
3709 /* IP9_7 [1] */
3710 FN_DU1_DOTCLKOUT0, FN_QCLK,
3711 /* IP9_6 [1] */
3712 FN_DU1_DOTCLKIN, FN_QSTVA_QVS,
3713 /* IP9_5_3 [3] */
3714 FN_DU1_DB7, FN_LCDOUT23, FN_SDA3_C,
3715 FN_SCIF3_SCK, FN_SCIFA3_SCK,
3716 0, 0, 0,
3717 /* IP9_2_0 [3] */
3718 FN_DU1_DB6, FN_LCDOUT22, FN_SCL3_C, FN_RX3, FN_SCIFA3_RXD,
3719 0, 0, 0, }
3720 },
3721 { PINMUX_CFG_REG_VAR("IPSR10", 0xE6060048, 32,
3722 3, 2, 2, 3, 3, 2, 2, 3, 3, 3, 3, 3) {
3723 /* IP10_31_29 [3] */
3724 FN_VI0_R4, FN_VI2_DATA5, FN_GLO_SCLK_B, FN_TX0_C, FN_SCL1_D,
3725 0, 0, 0,
3726 /* IP10_28_27 [2] */
3727 FN_VI0_R3, FN_VI2_DATA4, FN_GLO_Q1_B, FN_TS_SPSYNC0_C,
3728 /* IP10_26_25 [2] */
3729 FN_VI0_R2, FN_VI2_DATA3, FN_GLO_Q0_B, FN_TS_SDEN0_C,
3730 /* IP10_24_22 [3] */
3731 FN_VI0_R1, FN_VI2_DATA2, FN_GLO_I1_B, FN_TS_SCK0_C, FN_ATAG1_N,
3732 0, 0, 0,
3733 /* IP10_21_29 [3] */
3734 FN_VI0_R0, FN_VI2_DATA1, FN_GLO_I0_B,
3735 FN_TS_SDATA0_C, FN_ATACS11_N,
3736 0, 0, 0,
3737 /* IP10_18_17 [2] */
3738 FN_VI0_G7, FN_VI2_DATA0, FN_FMIN_D, 0,
3739 /* IP10_16_15 [2] */
3740 FN_VI0_G6, FN_VI2_CLK, FN_BPFCLK_D, 0,
3741 /* IP10_14_12 [3] */
3742 FN_VI0_G5, FN_VI2_FIELD, FN_STP_OPWM_0_C, FN_FMCLK_D,
3743 FN_CAN0_TX_E, FN_HTX1_D, FN_SCIFB0_TXD_D, 0,
3744 /* IP10_11_9 [3] */
3745 FN_VI0_G4, FN_VI2_CLKENB, FN_STP_ISSYNC_0_C,
3746 FN_HTX2, FN_SCIFB2_TXD, FN_SCIFB0_SCK_D,
3747 0, 0,
3748 /* IP10_8_6 [3] */
3749 FN_VI0_G3, FN_VI2_VSYNC_N, FN_STP_ISEN_0_C, FN_SDA3_B,
3750 FN_HRX2, FN_SCIFB2_RXD, FN_ATACS01_N, 0,
3751 /* IP10_5_3 [3] */
3752 FN_VI0_G2, FN_VI2_HSYNC_N, FN_STP_ISD_0_C, FN_SCL3_B,
3753 FN_HSCK2, FN_SCIFB2_SCK, FN_ATARD1_N, 0,
3754 /* IP10_2_0 [3] */
3755 FN_VI0_G1, FN_SDA8, FN_STP_ISCLK_0_C, FN_SDA4,
3756 FN_HRTS2_N, FN_SCIFB2_RTS_N, FN_ATADIR1_N, 0, }
3757 },
3758 { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
3759 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
3760 3, 3, 3, 3, 3) {
3761 /* IP11_31_30 [2] */
3762 FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
3763 /* IP11_29_28 [2] */
3764 FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
3765 /* IP11_27 [1] */
3766 FN_VI1_DATA7, FN_AVB_MDC,
3767 /* IP11_26 [1] */
3768 FN_VI1_DATA6, FN_AVB_MAGIC,
3769 /* IP11_25 [1] */
3770 FN_VI1_DATA5, FN_AVB_RX_DV,
3771 /* IP11_24 [1] */
3772 FN_VI1_DATA4, FN_AVB_MDIO,
3773 /* IP11_23 [1] */
3774 FN_VI1_DATA3, FN_AVB_RX_ER,
3775 /* IP11_22 [1] */
3776 FN_VI1_DATA2, FN_AVB_RXD7,
3777 /* IP11_21 [1] */
3778 FN_VI1_DATA1, FN_AVB_RXD6,
3779 /* IP11_20 [1] */
3780 FN_VI1_DATA0, FN_AVB_RXD5,
3781 /* IP11_19 [1] */
3782 FN_VI1_CLK, FN_AVB_RXD4,
3783 /* IP11_18_17 [2] */
3784 FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
3785 /* IP11_16_15 [2] */
3786 FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
3787 /* IP11_14_12 [3] */
3788 FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
3789 FN_RX4_B, FN_SCIFA4_RXD_B,
3790 0, 0, 0,
3791 /* IP11_11_9 [3] */
3792 FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
3793 FN_TX4_B, FN_SCIFA4_TXD_B,
3794 0, 0, 0,
3795 /* IP11_8_6 [3] */
3796 FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
3797 FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
3798 /* IP11_5_3 [3] */
3799 FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
3800 0, 0, 0,
3801 /* IP11_2_0 [3] */
3802 FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
3803 0, 0, 0, }
3804 },
3805 { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
3806 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
3807 /* IP12_31_30 [2] */
3808 0, 0, 0, 0,
3809 /* IP12_29_27 [3] */
3810 FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
3811 FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
3812 0, 0, 0,
3813 /* IP12_26_24 [3] */
3814 FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
3815 FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
3816 0, 0, 0,
3817 /* IP12_23_22 [2] */
3818 FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
3819 /* IP12_21_20 [2] */
3820 FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
3821 /* IP12_19_18 [2] */
3822 FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
3823 /* IP12_17_16 [2] */
3824 FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
3825 /* IP12_15_13 [3] */
3826 FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
3827 FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
3828 0, 0, 0,
3829 /* IP12_12_10 [3] */
3830 FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
3831 FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
3832 0, 0, 0,
3833 /* IP12_9_7 [3] */
3834 FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
3835 FN_SDA2_D, FN_MSIOF1_SCK_E,
3836 0, 0, 0,
3837 /* IP12_6_4 [3] */
3838 FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
3839 FN_SCL2_D, FN_MSIOF1_RXD_E,
3840 0, 0, 0,
3841 /* IP12_3_2 [2] */
3842 FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
3843 /* IP12_1_0 [2] */
3844 FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
3845 },
3846 { PINMUX_CFG_REG_VAR("IPSR13", 0xE6060054, 32,
3847 1, 3, 1, 1, 1, 2, 1, 3, 3, 1, 1, 1, 1, 1, 1,
3848 3, 2, 2, 3) {
3849 /* IP13_31 [1] */
3850 0, 0,
3851 /* IP13_30_28 [3] */
3852 FN_SD1_CD, FN_PWM0, FN_TPU_TO0, FN_SCL1_C,
3853 0, 0, 0, 0,
3854 /* IP13_27 [1] */
3855 FN_SD1_DATA3, FN_IERX_B,
3856 /* IP13_26 [1] */
3857 FN_SD1_DATA2, FN_IECLK_B,
3858 /* IP13_25 [1] */
3859 FN_SD1_DATA1, FN_IETX_B,
3860 /* IP13_24_23 [2] */
3861 FN_SD1_DATA0, FN_SPEEDIN_B, 0, 0,
3862 /* IP13_22 [1] */
3863 FN_SD1_CMD, FN_REMOCON_B,
3864 /* IP13_21_19 [3] */
3865 FN_SD0_WP, FN_MMC_D7_B, FN_SIM0_D_B, FN_CAN0_TX_F,
3866 FN_SCIFA5_RXD_B, FN_RX3_C,
3867 0, 0,
3868 /* IP13_18_16 [3] */
3869 FN_SD0_CD, FN_MMC_D6_B, FN_SIM0_RST_B, FN_CAN0_RX_F,
3870 FN_SCIFA5_TXD_B, FN_TX3_C,
3871 0, 0,
3872 /* IP13_15 [1] */
3873 FN_SD0_DATA3, FN_SSL_B,
3874 /* IP13_14 [1] */
3875 FN_SD0_DATA2, FN_IO3_B,
3876 /* IP13_13 [1] */
3877 FN_SD0_DATA1, FN_IO2_B,
3878 /* IP13_12 [1] */
3879 FN_SD0_DATA0, FN_MISO_IO1_B,
3880 /* IP13_11 [1] */
3881 FN_SD0_CMD, FN_MOSI_IO0_B,
3882 /* IP13_10 [1] */
3883 FN_SD0_CLK, FN_SPCLK_B,
3884 /* IP13_9_7 [3] */
3885 FN_STP_OPWM_0, FN_AVB_GTX_CLK, FN_PWM0_B,
3886 FN_ADICHS2_B, FN_MSIOF0_TXD_C,
3887 0, 0, 0,
3888 /* IP13_6_5 [2] */
3889 FN_STP_ISSYNC_0, FN_AVB_COL, FN_ADICHS1_B, FN_MSIOF0_RXD_C,
3890 /* IP13_4_3 [2] */
3891 FN_STP_ISEN_0, FN_AVB_TX_CLK, FN_ADICHS0_B, FN_MSIOF0_SS2_C,
3892 /* IP13_2_0 [3] */
3893 FN_STP_ISD_0, FN_AVB_TX_ER, FN_SCIFB2_SCK_C,
3894 FN_ADICLK_B, FN_MSIOF0_SS1_C,
3895 0, 0, 0, }
3896 },
3897 { PINMUX_CFG_REG_VAR("IPSR14", 0xE6060058, 32,
3898 3, 3, 3, 3, 3, 3, 3, 3, 1, 1, 1, 1, 1, 1, 2) {
3899 /* IP14_31_29 [3] */
3900 FN_MSIOF0_SS2, FN_MMC_D7, FN_ADICHS2, FN_RX0_E,
3901 FN_VI1_VSYNC_N_C, FN_SDA7_C, FN_VI1_G5_B, 0,
3902 /* IP14_28_26 [3] */
3903 FN_MSIOF0_SS1, FN_MMC_D6, FN_ADICHS1, FN_TX0_E,
3904 FN_VI1_HSYNC_N_C, FN_SCL7_C, FN_VI1_G4_B, 0,
3905 /* IP14_25_23 [3] */
3906 FN_MSIOF0_RXD, FN_ADICHS0, 0, FN_VI1_DATA0_C, FN_VI1_G3_B,
3907 0, 0, 0,
3908 /* IP14_22_20 [3] */
3909 FN_MSIOF0_TXD, FN_ADICLK, 0, FN_VI1_FIELD_C, FN_VI1_G2_B,
3910 0, 0, 0,
3911 /* IP14_19_17 [3] */
3912 FN_MSIOF0_SYNC, FN_TX2_C, FN_ADICS_SAMP, 0,
3913 FN_VI1_CLKENB_C, FN_VI1_G1_B,
3914 0, 0,
3915 /* IP14_16_14 [3] */
3916 FN_MSIOF0_SCK, FN_RX2_C, FN_ADIDATA, 0,
3917 FN_VI1_CLK_C, FN_VI1_G0_B,
3918 0, 0,
3919 /* IP14_13_11 [3] */
3920 FN_SD2_WP, FN_MMC_D5, FN_SDA8_C, FN_RX5_B, FN_SCIFA5_RXD_C,
3921 0, 0, 0,
3922 /* IP14_10_8 [3] */
3923 FN_SD2_CD, FN_MMC_D4, FN_SCL8_C, FN_TX5_B, FN_SCIFA5_TXD_C,
3924 0, 0, 0,
3925 /* IP14_7 [1] */
3926 FN_SD2_DATA3, FN_MMC_D3,
3927 /* IP14_6 [1] */
3928 FN_SD2_DATA2, FN_MMC_D2,
3929 /* IP14_5 [1] */
3930 FN_SD2_DATA1, FN_MMC_D1,
3931 /* IP14_4 [1] */
3932 FN_SD2_DATA0, FN_MMC_D0,
3933 /* IP14_3 [1] */
3934 FN_SD2_CMD, FN_MMC_CMD,
3935 /* IP14_2 [1] */
3936 FN_SD2_CLK, FN_MMC_CLK,
3937 /* IP14_1_0 [2] */
3938 FN_SD1_WP, FN_PWM1_B, FN_SDA1_C, 0, }
3939 },
3940 { PINMUX_CFG_REG_VAR("IPSR15", 0xE606005C, 32,
3941 2, 3, 3, 3, 3, 3, 3, 3, 3, 2, 2, 2) {
3942 /* IP15_31_30 [2] */
3943 0, 0, 0, 0,
3944 /* IP15_29_27 [3] */
3945 FN_HTX0, FN_SCIFB0_TXD, 0, FN_GLO_SCLK_C,
3946 FN_CAN0_TX_B, FN_VI1_DATA5_C,
3947 0, 0,
3948 /* IP15_26_24 [3] */
3949 FN_HRX0, FN_SCIFB0_RXD, 0, FN_GLO_Q1_C,
3950 FN_CAN0_RX_B, FN_VI1_DATA4_C,
3951 0, 0,
3952 /* IP15_23_21 [3] */
3953 FN_HSCK0, FN_SCIFB0_SCK, 0, FN_GLO_Q0_C, FN_CAN_CLK,
3954 FN_TCLK2, FN_VI1_DATA3_C, 0,
3955 /* IP15_20_18 [3] */
3956 FN_HRTS0_N, FN_SCIFB0_RTS_N, 0, FN_GLO_I1_C, FN_VI1_DATA2_C,
3957 0, 0, 0,
3958 /* IP15_17_15 [3] */
3959 FN_HCTS0_N, FN_SCIFB0_CTS_N, 0, FN_GLO_I0_C,
3960 FN_TCLK1, FN_VI1_DATA1_C,
3961 0, 0,
3962 /* IP15_14_12 [3] */
3963 FN_GPS_MAG, FN_RX4_C, FN_SCIFA4_RXD_C, FN_PWM6,
3964 FN_VI1_G7_B, FN_SCIFA3_SCK_C,
3965 0, 0,
3966 /* IP15_11_9 [3] */
3967 FN_GPS_SIGN, FN_TX4_C, FN_SCIFA4_TXD_C, FN_PWM5,
3968 FN_VI1_G6_B, FN_SCIFA3_RXD_C,
3969 0, 0,
3970 /* IP15_8_6 [3] */
3971 FN_GPS_CLK, FN_DU1_DOTCLKIN_C, FN_AUDIO_CLKB_B,
3972 FN_PWM5_B, FN_SCIFA3_TXD_C,
3973 0, 0, 0,
3974 /* IP15_5_4 [2] */
3975 FN_SIM0_D, FN_IERX, FN_CAN1_RX_D, 0,
3976 /* IP15_3_2 [2] */
3977 FN_SIM0_CLK, FN_IECLK, FN_CAN_CLK_C, 0,
3978 /* IP15_1_0 [2] */
3979 FN_SIM0_RST, FN_IETX, FN_CAN1_TX_D, 0, }
3980 },
3981 { PINMUX_CFG_REG_VAR("IPSR16", 0xE6060160, 32,
3982 4, 4, 4, 4, 4, 2, 2, 2, 3, 3) {
3983 /* IP16_31_28 [4] */
3984 0, 0, 0, 0, 0, 0, 0, 0,
3985 0, 0, 0, 0, 0, 0, 0, 0,
3986 /* IP16_27_24 [4] */
3987 0, 0, 0, 0, 0, 0, 0, 0,
3988 0, 0, 0, 0, 0, 0, 0, 0,
3989 /* IP16_23_20 [4] */
3990 0, 0, 0, 0, 0, 0, 0, 0,
3991 0, 0, 0, 0, 0, 0, 0, 0,
3992 /* IP16_19_16 [4] */
3993 0, 0, 0, 0, 0, 0, 0, 0,
3994 0, 0, 0, 0, 0, 0, 0, 0,
3995 /* IP16_15_12 [4] */
3996 0, 0, 0, 0, 0, 0, 0, 0,
3997 0, 0, 0, 0, 0, 0, 0, 0,
3998 /* IP16_11_10 [2] */
3999 FN_HRTS1_N, FN_SCIFB1_RTS_N, FN_MLB_DAT, FN_CAN1_RX_B,
4000 /* IP16_9_8 [2] */
4001 FN_HCTS1_N, FN_SCIFB1_CTS_N, FN_MLB_SIG, FN_CAN1_TX_B,
4002 /* IP16_7_6 [2] */
4003 FN_HSCK1, FN_SCIFB1_SCK, FN_MLB_CK, FN_GLO_RFON_C,
4004 /* IP16_5_3 [3] */
4005 FN_HTX1, FN_SCIFB1_TXD, FN_VI1_R1_B,
4006 FN_GLO_SS_C, FN_VI1_DATA7_C,
4007 0, 0, 0,
4008 /* IP16_2_0 [3] */
4009 FN_HRX1, FN_SCIFB1_RXD, FN_VI1_R0_B,
4010 FN_GLO_SDATA_C, FN_VI1_DATA6_C,
4011 0, 0, 0, }
4012 },
4013 { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
4014 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
4015 3, 2, 2, 2, 1, 2, 2, 2) {
4016 /* RESEVED [1] */
4017 0, 0,
4018 /* SEL_SCIF1 [2] */
4019 FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
4020 /* SEL_SCIFB [2] */
4021 FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
4022 /* SEL_SCIFB2 [2] */
4023 FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
4024 FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
4025 /* SEL_SCIFB1 [3] */
4026 FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
4027 FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
4028 0, 0, 0, 0,
4029 /* SEL_SCIFA1 [2] */
4030 FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
4031 /* SEL_SSI9 [1] */
4032 FN_SEL_SSI9_0, FN_SEL_SSI9_1,
4033 /* SEL_SCFA [1] */
4034 FN_SEL_SCFA_0, FN_SEL_SCFA_1,
4035 /* SEL_QSP [1] */
4036 FN_SEL_QSP_0, FN_SEL_QSP_1,
4037 /* SEL_SSI7 [1] */
4038 FN_SEL_SSI7_0, FN_SEL_SSI7_1,
4039 /* SEL_HSCIF1 [3] */
4040 FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
4041 FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
4042 0, 0, 0,
4043 /* RESEVED [2] */
4044 0, 0, 0, 0,
4045 /* SEL_VI1 [2] */
4046 FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
4047 /* RESEVED [2] */
4048 0, 0, 0, 0,
4049 /* SEL_TMU [1] */
4050 FN_SEL_TMU1_0, FN_SEL_TMU1_1,
4051 /* SEL_LBS [2] */
4052 FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
4053 /* SEL_TSIF0 [2] */
4054 FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
4055 /* SEL_SOF0 [2] */
4056 FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
4057 },
4058 { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
4059 3, 1, 1, 3, 2, 1, 1, 2, 2,
4060 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
4061 /* SEL_SCIF0 [3] */
4062 FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
4063 FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
4064 0, 0, 0,
4065 /* RESEVED [1] */
4066 0, 0,
4067 /* SEL_SCIF [1] */
4068 FN_SEL_SCIF_0, FN_SEL_SCIF_1,
4069 /* SEL_CAN0 [3] */
4070 FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
4071 FN_SEL_CAN0_4, FN_SEL_CAN0_5,
4072 0, 0,
4073 /* SEL_CAN1 [2] */
4074 FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
4075 /* RESEVED [1] */
4076 0, 0,
4077 /* SEL_SCIFA2 [1] */
4078 FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
4079 /* SEL_SCIF4 [2] */
4080 FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
4081 /* RESEVED [2] */
4082 0, 0, 0, 0,
4083 /* SEL_ADG [1] */
4084 FN_SEL_ADG_0, FN_SEL_ADG_1,
4085 /* SEL_FM [3] */
4086 FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
4087 FN_SEL_FM_3, FN_SEL_FM_4,
4088 0, 0, 0,
4089 /* SEL_SCIFA5 [2] */
4090 FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
4091 /* RESEVED [1] */
4092 0, 0,
4093 /* SEL_GPS [2] */
4094 FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
4095 /* SEL_SCIFA4 [2] */
4096 FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
4097 /* SEL_SCIFA3 [2] */
4098 FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
4099 /* SEL_SIM [1] */
4100 FN_SEL_SIM_0, FN_SEL_SIM_1,
4101 /* RESEVED [1] */
4102 0, 0,
4103 /* SEL_SSI8 [1] */
4104 FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
4105 },
4106 { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
4107 2, 2, 2, 2, 2, 2, 2, 2,
4108 1, 1, 2, 2, 3, 2, 2, 2, 1) {
4109 /* SEL_HSCIF2 [2] */
4110 FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
4111 FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
4112 /* SEL_CANCLK [2] */
4113 FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
4114 FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
4115 /* SEL_IIC8 [2] */
4116 FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
4117 /* SEL_IIC7 [2] */
4118 FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
4119 /* SEL_IIC4 [2] */
4120 FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
4121 /* SEL_IIC3 [2] */
4122 FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
4123 /* SEL_SCIF3 [2] */
4124 FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
4125 /* SEL_IEB [2] */
4126 FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
4127 /* SEL_MMC [1] */
4128 FN_SEL_MMC_0, FN_SEL_MMC_1,
4129 /* SEL_SCIF5 [1] */
4130 FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
4131 /* RESEVED [2] */
4132 0, 0, 0, 0,
4133 /* SEL_IIC2 [2] */
4134 FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
4135 /* SEL_IIC1 [3] */
4136 FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
4137 FN_SEL_IIC1_4,
4138 0, 0, 0,
4139 /* SEL_IIC0 [2] */
4140 FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
4141 /* RESEVED [2] */
4142 0, 0, 0, 0,
4143 /* RESEVED [2] */
4144 0, 0, 0, 0,
4145 /* RESEVED [1] */
4146 0, 0, }
4147 },
4148 { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
4149 3, 2, 2, 1, 1, 1, 1, 3, 2,
4150 2, 3, 1, 1, 1, 2, 2, 2, 2) {
4151 /* SEL_SOF1 [3] */
4152 FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
4153 FN_SEL_SOF1_4,
4154 0, 0, 0,
4155 /* SEL_HSCIF0 [2] */
4156 FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
4157 /* SEL_DIS [2] */
4158 FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
4159 /* RESEVED [1] */
4160 0, 0,
4161 /* SEL_RAD [1] */
4162 FN_SEL_RAD_0, FN_SEL_RAD_1,
4163 /* SEL_RCN [1] */
4164 FN_SEL_RCN_0, FN_SEL_RCN_1,
4165 /* SEL_RSP [1] */
4166 FN_SEL_RSP_0, FN_SEL_RSP_1,
4167 /* SEL_SCIF2 [3] */
4168 FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
4169 FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
4170 0, 0, 0,
4171 /* RESEVED [2] */
4172 0, 0, 0, 0,
4173 /* RESEVED [2] */
4174 0, 0, 0, 0,
4175 /* SEL_SOF2 [3] */
4176 FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
4177 FN_SEL_SOF2_3, FN_SEL_SOF2_4,
4178 0, 0, 0,
4179 /* RESEVED [1] */
4180 0, 0,
4181 /* SEL_SSI1 [1] */
4182 FN_SEL_SSI1_0, FN_SEL_SSI1_1,
4183 /* SEL_SSI0 [1] */
4184 FN_SEL_SSI0_0, FN_SEL_SSI0_1,
4185 /* SEL_SSP [2] */
4186 FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
4187 /* RESEVED [2] */
4188 0, 0, 0, 0,
4189 /* RESEVED [2] */
4190 0, 0, 0, 0,
4191 /* RESEVED [2] */
4192 0, 0, 0, 0, }
4193 },
4194 { },
4195};
4196
4197const struct sh_pfc_soc_info r8a7791_pinmux_info = {
4198 .name = "r8a77910_pfc",
4199 .unlock_reg = 0xe6060000, /* PMMR */
4200
4201 .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
4202
4203 .pins = pinmux_pins,
4204 .nr_pins = ARRAY_SIZE(pinmux_pins),
4205 .groups = pinmux_groups,
4206 .nr_groups = ARRAY_SIZE(pinmux_groups),
4207 .functions = pinmux_functions,
4208 .nr_functions = ARRAY_SIZE(pinmux_functions),
4209
4210 .cfg_regs = pinmux_config_regs,
4211
4212 .gpio_data = pinmux_data,
4213 .gpio_data_size = ARRAY_SIZE(pinmux_data),
4214};
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index edf45a6940ca..8ab7898d21be 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -122,6 +122,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
122 PINCTRL_PIN(100, "ac97_dout"), 122 PINCTRL_PIN(100, "ac97_dout"),
123 PINCTRL_PIN(101, "ac97_din"), 123 PINCTRL_PIN(101, "ac97_din"),
124 PINCTRL_PIN(102, "x_rtc_io"), 124 PINCTRL_PIN(102, "x_rtc_io"),
125
126 PINCTRL_PIN(103, "x_usb1_dp"),
127 PINCTRL_PIN(104, "x_usb1_dn"),
125}; 128};
126 129
127static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 130static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
@@ -139,6 +142,7 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
139static const struct sirfsoc_padmux lcd_16bits_padmux = { 142static const struct sirfsoc_padmux lcd_16bits_padmux = {
140 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), 143 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
141 .muxmask = lcd_16bits_sirfsoc_muxmask, 144 .muxmask = lcd_16bits_sirfsoc_muxmask,
145 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
142 .funcmask = BIT(4), 146 .funcmask = BIT(4),
143 .funcval = 0, 147 .funcval = 0,
144}; 148};
@@ -164,6 +168,7 @@ static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
164static const struct sirfsoc_padmux lcd_18bits_padmux = { 168static const struct sirfsoc_padmux lcd_18bits_padmux = {
165 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), 169 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
166 .muxmask = lcd_18bits_muxmask, 170 .muxmask = lcd_18bits_muxmask,
171 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
167 .funcmask = BIT(4) | BIT(15), 172 .funcmask = BIT(4) | BIT(15),
168 .funcval = 0, 173 .funcval = 0,
169}; 174};
@@ -189,6 +194,7 @@ static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
189static const struct sirfsoc_padmux lcd_24bits_padmux = { 194static const struct sirfsoc_padmux lcd_24bits_padmux = {
190 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), 195 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
191 .muxmask = lcd_24bits_muxmask, 196 .muxmask = lcd_24bits_muxmask,
197 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
192 .funcmask = BIT(4) | BIT(15), 198 .funcmask = BIT(4) | BIT(15),
193 .funcval = 0, 199 .funcval = 0,
194}; 200};
@@ -214,6 +220,7 @@ static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
214static const struct sirfsoc_padmux lcdrom_padmux = { 220static const struct sirfsoc_padmux lcdrom_padmux = {
215 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), 221 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
216 .muxmask = lcdrom_muxmask, 222 .muxmask = lcdrom_muxmask,
223 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
217 .funcmask = BIT(4), 224 .funcmask = BIT(4),
218 .funcval = BIT(4), 225 .funcval = BIT(4),
219}; 226};
@@ -237,6 +244,7 @@ static const struct sirfsoc_muxmask uart0_muxmask[] = {
237static const struct sirfsoc_padmux uart0_padmux = { 244static const struct sirfsoc_padmux uart0_padmux = {
238 .muxmask_counts = ARRAY_SIZE(uart0_muxmask), 245 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
239 .muxmask = uart0_muxmask, 246 .muxmask = uart0_muxmask,
247 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
240 .funcmask = BIT(9), 248 .funcmask = BIT(9),
241 .funcval = BIT(9), 249 .funcval = BIT(9),
242}; 250};
@@ -284,6 +292,7 @@ static const struct sirfsoc_muxmask uart2_muxmask[] = {
284static const struct sirfsoc_padmux uart2_padmux = { 292static const struct sirfsoc_padmux uart2_padmux = {
285 .muxmask_counts = ARRAY_SIZE(uart2_muxmask), 293 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
286 .muxmask = uart2_muxmask, 294 .muxmask = uart2_muxmask,
295 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
287 .funcmask = BIT(10), 296 .funcmask = BIT(10),
288 .funcval = BIT(10), 297 .funcval = BIT(10),
289}; 298};
@@ -317,6 +326,7 @@ static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
317static const struct sirfsoc_padmux sdmmc3_padmux = { 326static const struct sirfsoc_padmux sdmmc3_padmux = {
318 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), 327 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
319 .muxmask = sdmmc3_muxmask, 328 .muxmask = sdmmc3_muxmask,
329 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
320 .funcmask = BIT(7), 330 .funcmask = BIT(7),
321 .funcval = 0, 331 .funcval = 0,
322}; 332};
@@ -336,6 +346,7 @@ static const struct sirfsoc_muxmask spi0_muxmask[] = {
336static const struct sirfsoc_padmux spi0_padmux = { 346static const struct sirfsoc_padmux spi0_padmux = {
337 .muxmask_counts = ARRAY_SIZE(spi0_muxmask), 347 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
338 .muxmask = spi0_muxmask, 348 .muxmask = spi0_muxmask,
349 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
339 .funcmask = BIT(7), 350 .funcmask = BIT(7),
340 .funcval = BIT(7), 351 .funcval = BIT(7),
341}; 352};
@@ -352,6 +363,7 @@ static const struct sirfsoc_muxmask cko1_muxmask[] = {
352static const struct sirfsoc_padmux cko1_padmux = { 363static const struct sirfsoc_padmux cko1_padmux = {
353 .muxmask_counts = ARRAY_SIZE(cko1_muxmask), 364 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
354 .muxmask = cko1_muxmask, 365 .muxmask = cko1_muxmask,
366 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
355 .funcmask = BIT(3), 367 .funcmask = BIT(3),
356 .funcval = 0, 368 .funcval = 0,
357}; 369};
@@ -371,6 +383,7 @@ static const struct sirfsoc_muxmask i2s_muxmask[] = {
371static const struct sirfsoc_padmux i2s_padmux = { 383static const struct sirfsoc_padmux i2s_padmux = {
372 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 384 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
373 .muxmask = i2s_muxmask, 385 .muxmask = i2s_muxmask,
386 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
374 .funcmask = BIT(3), 387 .funcmask = BIT(3),
375 .funcval = BIT(3), 388 .funcval = BIT(3),
376}; 389};
@@ -390,6 +403,7 @@ static const struct sirfsoc_muxmask i2s_no_din_muxmask[] = {
390static const struct sirfsoc_padmux i2s_no_din_padmux = { 403static const struct sirfsoc_padmux i2s_no_din_padmux = {
391 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask), 404 .muxmask_counts = ARRAY_SIZE(i2s_no_din_muxmask),
392 .muxmask = i2s_no_din_muxmask, 405 .muxmask = i2s_no_din_muxmask,
406 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
393 .funcmask = BIT(3), 407 .funcmask = BIT(3),
394 .funcval = BIT(3), 408 .funcval = BIT(3),
395}; 409};
@@ -409,6 +423,7 @@ static const struct sirfsoc_muxmask i2s_6chn_muxmask[] = {
409static const struct sirfsoc_padmux i2s_6chn_padmux = { 423static const struct sirfsoc_padmux i2s_6chn_padmux = {
410 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask), 424 .muxmask_counts = ARRAY_SIZE(i2s_6chn_muxmask),
411 .muxmask = i2s_6chn_muxmask, 425 .muxmask = i2s_6chn_muxmask,
426 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
412 .funcmask = BIT(1) | BIT(3) | BIT(9), 427 .funcmask = BIT(1) | BIT(3) | BIT(9),
413 .funcval = BIT(1) | BIT(3) | BIT(9), 428 .funcval = BIT(1) | BIT(3) | BIT(9),
414}; 429};
@@ -439,6 +454,7 @@ static const struct sirfsoc_muxmask spi1_muxmask[] = {
439static const struct sirfsoc_padmux spi1_padmux = { 454static const struct sirfsoc_padmux spi1_padmux = {
440 .muxmask_counts = ARRAY_SIZE(spi1_muxmask), 455 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
441 .muxmask = spi1_muxmask, 456 .muxmask = spi1_muxmask,
457 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
442 .funcmask = BIT(16), 458 .funcmask = BIT(16),
443 .funcval = 0, 459 .funcval = 0,
444}; 460};
@@ -455,6 +471,7 @@ static const struct sirfsoc_muxmask sdmmc1_muxmask[] = {
455static const struct sirfsoc_padmux sdmmc1_padmux = { 471static const struct sirfsoc_padmux sdmmc1_padmux = {
456 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask), 472 .muxmask_counts = ARRAY_SIZE(sdmmc1_muxmask),
457 .muxmask = sdmmc1_muxmask, 473 .muxmask = sdmmc1_muxmask,
474 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
458 .funcmask = BIT(5), 475 .funcmask = BIT(5),
459 .funcval = BIT(5), 476 .funcval = BIT(5),
460}; 477};
@@ -471,6 +488,7 @@ static const struct sirfsoc_muxmask gps_muxmask[] = {
471static const struct sirfsoc_padmux gps_padmux = { 488static const struct sirfsoc_padmux gps_padmux = {
472 .muxmask_counts = ARRAY_SIZE(gps_muxmask), 489 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
473 .muxmask = gps_muxmask, 490 .muxmask = gps_muxmask,
491 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
474 .funcmask = BIT(13), 492 .funcmask = BIT(13),
475 .funcval = 0, 493 .funcval = 0,
476}; 494};
@@ -487,6 +505,7 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
487static const struct sirfsoc_padmux sdmmc5_padmux = { 505static const struct sirfsoc_padmux sdmmc5_padmux = {
488 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), 506 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
489 .muxmask = sdmmc5_muxmask, 507 .muxmask = sdmmc5_muxmask,
508 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
490 .funcmask = BIT(13), 509 .funcmask = BIT(13),
491 .funcval = BIT(13), 510 .funcval = BIT(13),
492}; 511};
@@ -503,6 +522,7 @@ static const struct sirfsoc_muxmask usp0_muxmask[] = {
503static const struct sirfsoc_padmux usp0_padmux = { 522static const struct sirfsoc_padmux usp0_padmux = {
504 .muxmask_counts = ARRAY_SIZE(usp0_muxmask), 523 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
505 .muxmask = usp0_muxmask, 524 .muxmask = usp0_muxmask,
525 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
506 .funcmask = BIT(1) | BIT(2) | BIT(9), 526 .funcmask = BIT(1) | BIT(2) | BIT(9),
507 .funcval = 0, 527 .funcval = 0,
508}; 528};
@@ -535,6 +555,7 @@ static const struct sirfsoc_muxmask usp1_muxmask[] = {
535static const struct sirfsoc_padmux usp1_padmux = { 555static const struct sirfsoc_padmux usp1_padmux = {
536 .muxmask_counts = ARRAY_SIZE(usp1_muxmask), 556 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
537 .muxmask = usp1_muxmask, 557 .muxmask = usp1_muxmask,
558 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
538 .funcmask = BIT(16), 559 .funcmask = BIT(16),
539 .funcval = BIT(16), 560 .funcval = BIT(16),
540}; 561};
@@ -554,6 +575,7 @@ static const struct sirfsoc_muxmask nand_muxmask[] = {
554static const struct sirfsoc_padmux nand_padmux = { 575static const struct sirfsoc_padmux nand_padmux = {
555 .muxmask_counts = ARRAY_SIZE(nand_muxmask), 576 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
556 .muxmask = nand_muxmask, 577 .muxmask = nand_muxmask,
578 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
557 .funcmask = BIT(5) | BIT(19), 579 .funcmask = BIT(5) | BIT(19),
558 .funcval = 0, 580 .funcval = 0,
559}; 581};
@@ -570,6 +592,7 @@ static const struct sirfsoc_muxmask sdmmc0_muxmask[] = {
570static const struct sirfsoc_padmux sdmmc0_padmux = { 592static const struct sirfsoc_padmux sdmmc0_padmux = {
571 .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask), 593 .muxmask_counts = ARRAY_SIZE(sdmmc0_muxmask),
572 .muxmask = sdmmc0_muxmask, 594 .muxmask = sdmmc0_muxmask,
595 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
573 .funcmask = BIT(5) | BIT(19), 596 .funcmask = BIT(5) | BIT(19),
574 .funcval = BIT(19), 597 .funcval = BIT(19),
575}; 598};
@@ -586,6 +609,7 @@ static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
586static const struct sirfsoc_padmux sdmmc2_padmux = { 609static const struct sirfsoc_padmux sdmmc2_padmux = {
587 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), 610 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
588 .muxmask = sdmmc2_muxmask, 611 .muxmask = sdmmc2_muxmask,
612 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
589 .funcmask = BIT(11), 613 .funcmask = BIT(11),
590 .funcval = 0, 614 .funcval = 0,
591}; 615};
@@ -602,6 +626,7 @@ static const struct sirfsoc_muxmask sdmmc2_nowp_muxmask[] = {
602static const struct sirfsoc_padmux sdmmc2_nowp_padmux = { 626static const struct sirfsoc_padmux sdmmc2_nowp_padmux = {
603 .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask), 627 .muxmask_counts = ARRAY_SIZE(sdmmc2_nowp_muxmask),
604 .muxmask = sdmmc2_nowp_muxmask, 628 .muxmask = sdmmc2_nowp_muxmask,
629 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
605 .funcmask = BIT(11), 630 .funcmask = BIT(11),
606 .funcval = 0, 631 .funcval = 0,
607}; 632};
@@ -634,6 +659,7 @@ static const struct sirfsoc_muxmask vip_muxmask[] = {
634static const struct sirfsoc_padmux vip_padmux = { 659static const struct sirfsoc_padmux vip_padmux = {
635 .muxmask_counts = ARRAY_SIZE(vip_muxmask), 660 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
636 .muxmask = vip_muxmask, 661 .muxmask = vip_muxmask,
662 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
637 .funcmask = BIT(18), 663 .funcmask = BIT(18),
638 .funcval = BIT(18), 664 .funcval = BIT(18),
639}; 665};
@@ -654,6 +680,7 @@ static const struct sirfsoc_muxmask vip_noupli_muxmask[] = {
654static const struct sirfsoc_padmux vip_noupli_padmux = { 680static const struct sirfsoc_padmux vip_noupli_padmux = {
655 .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask), 681 .muxmask_counts = ARRAY_SIZE(vip_noupli_muxmask),
656 .muxmask = vip_noupli_muxmask, 682 .muxmask = vip_noupli_muxmask,
683 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
657 .funcmask = BIT(15), 684 .funcmask = BIT(15),
658 .funcval = BIT(15), 685 .funcval = BIT(15),
659}; 686};
@@ -684,6 +711,7 @@ static const struct sirfsoc_muxmask i2c1_muxmask[] = {
684static const struct sirfsoc_padmux i2c1_padmux = { 711static const struct sirfsoc_padmux i2c1_padmux = {
685 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask), 712 .muxmask_counts = ARRAY_SIZE(i2c1_muxmask),
686 .muxmask = i2c1_muxmask, 713 .muxmask = i2c1_muxmask,
714 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
687 .funcmask = BIT(16), 715 .funcmask = BIT(16),
688 .funcval = 0, 716 .funcval = 0,
689}; 717};
@@ -700,6 +728,7 @@ static const struct sirfsoc_muxmask pwm0_muxmask[] = {
700static const struct sirfsoc_padmux pwm0_padmux = { 728static const struct sirfsoc_padmux pwm0_padmux = {
701 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), 729 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
702 .muxmask = pwm0_muxmask, 730 .muxmask = pwm0_muxmask,
731 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
703 .funcmask = BIT(12), 732 .funcmask = BIT(12),
704 .funcval = 0, 733 .funcval = 0,
705}; 734};
@@ -772,6 +801,7 @@ static const struct sirfsoc_muxmask warm_rst_muxmask[] = {
772static const struct sirfsoc_padmux warm_rst_padmux = { 801static const struct sirfsoc_padmux warm_rst_padmux = {
773 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask), 802 .muxmask_counts = ARRAY_SIZE(warm_rst_muxmask),
774 .muxmask = warm_rst_muxmask, 803 .muxmask = warm_rst_muxmask,
804 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
775 .funcmask = BIT(4), 805 .funcmask = BIT(4),
776 .funcval = 0, 806 .funcval = 0,
777}; 807};
@@ -789,6 +819,7 @@ static const struct sirfsoc_muxmask usb0_upli_drvbus_muxmask[] = {
789static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = { 819static const struct sirfsoc_padmux usb0_upli_drvbus_padmux = {
790 .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask), 820 .muxmask_counts = ARRAY_SIZE(usb0_upli_drvbus_muxmask),
791 .muxmask = usb0_upli_drvbus_muxmask, 821 .muxmask = usb0_upli_drvbus_muxmask,
822 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
792 .funcmask = BIT(18), 823 .funcmask = BIT(18),
793 .funcval = 0, 824 .funcval = 0,
794}; 825};
@@ -805,12 +836,31 @@ static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
805static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { 836static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
806 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), 837 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
807 .muxmask = usb1_utmi_drvbus_muxmask, 838 .muxmask = usb1_utmi_drvbus_muxmask,
839 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
808 .funcmask = BIT(11), 840 .funcmask = BIT(11),
809 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ 841 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
810}; 842};
811 843
812static const unsigned usb1_utmi_drvbus_pins[] = { 28 }; 844static const unsigned usb1_utmi_drvbus_pins[] = { 28 };
813 845
846static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
847 .muxmask_counts = 0,
848 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
849 .funcmask = BIT(2),
850 .funcval = BIT(2),
851};
852
853static const unsigned usb1_dp_dn_pins[] = { 103, 104 };
854
855static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
856 .muxmask_counts = 0,
857 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
858 .funcmask = BIT(2),
859 .funcval = 0,
860};
861
862static const unsigned uart1_route_io_usb1_pins[] = { 103, 104 };
863
814static const struct sirfsoc_muxmask pulse_count_muxmask[] = { 864static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
815 { 865 {
816 .group = 0, 866 .group = 0,
@@ -859,6 +909,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
859 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), 909 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
860 SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins), 910 SIRFSOC_PIN_GROUP("usb0_upli_drvbusgrp", usb0_upli_drvbus_pins),
861 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), 911 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
912 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
913 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
862 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 914 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
863 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 915 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
864 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins), 916 SIRFSOC_PIN_GROUP("i2s_no_dingrp", i2s_no_din_pins),
@@ -903,6 +955,8 @@ static const char * const sdmmc5grp[] = { "sdmmc5grp" };
903static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" }; 955static const char * const sdmmc2_nowpgrp[] = { "sdmmc2_nowpgrp" };
904static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" }; 956static const char * const usb0_upli_drvbusgrp[] = { "usb0_upli_drvbusgrp" };
905static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 957static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
958static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
959static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
906static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 960static const char * const pulse_countgrp[] = { "pulse_countgrp" };
907static const char * const i2sgrp[] = { "i2sgrp" }; 961static const char * const i2sgrp[] = { "i2sgrp" };
908static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" }; 962static const char * const i2s_no_dingrp[] = { "i2s_no_dingrp" };
@@ -949,6 +1003,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
949 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux), 1003 SIRFSOC_PMX_FUNCTION("sdmmc2_nowp", sdmmc2_nowpgrp, sdmmc2_nowp_padmux),
950 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux), 1004 SIRFSOC_PMX_FUNCTION("usb0_upli_drvbus", usb0_upli_drvbusgrp, usb0_upli_drvbus_padmux),
951 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 1005 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
1006 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
1007 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
952 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 1008 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
953 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 1009 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
954 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux), 1010 SIRFSOC_PMX_FUNCTION("i2s_no_din", i2s_no_dingrp, i2s_no_din_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index 1f0ad1ef5a3a..050777be0f1e 100644
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -126,6 +126,9 @@ static const struct pinctrl_pin_desc sirfsoc_pads[] = {
126 PINCTRL_PIN(112, "x_ldd[13]"), 126 PINCTRL_PIN(112, "x_ldd[13]"),
127 PINCTRL_PIN(113, "x_ldd[14]"), 127 PINCTRL_PIN(113, "x_ldd[14]"),
128 PINCTRL_PIN(114, "x_ldd[15]"), 128 PINCTRL_PIN(114, "x_ldd[15]"),
129
130 PINCTRL_PIN(115, "x_usb1_dp"),
131 PINCTRL_PIN(116, "x_usb1_dn"),
129}; 132};
130 133
131static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = { 134static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
@@ -143,6 +146,7 @@ static const struct sirfsoc_muxmask lcd_16bits_sirfsoc_muxmask[] = {
143static const struct sirfsoc_padmux lcd_16bits_padmux = { 146static const struct sirfsoc_padmux lcd_16bits_padmux = {
144 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask), 147 .muxmask_counts = ARRAY_SIZE(lcd_16bits_sirfsoc_muxmask),
145 .muxmask = lcd_16bits_sirfsoc_muxmask, 148 .muxmask = lcd_16bits_sirfsoc_muxmask,
149 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
146 .funcmask = BIT(4), 150 .funcmask = BIT(4),
147 .funcval = 0, 151 .funcval = 0,
148}; 152};
@@ -168,6 +172,7 @@ static const struct sirfsoc_muxmask lcd_18bits_muxmask[] = {
168static const struct sirfsoc_padmux lcd_18bits_padmux = { 172static const struct sirfsoc_padmux lcd_18bits_padmux = {
169 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask), 173 .muxmask_counts = ARRAY_SIZE(lcd_18bits_muxmask),
170 .muxmask = lcd_18bits_muxmask, 174 .muxmask = lcd_18bits_muxmask,
175 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
171 .funcmask = BIT(4), 176 .funcmask = BIT(4),
172 .funcval = 0, 177 .funcval = 0,
173}; 178};
@@ -193,6 +198,7 @@ static const struct sirfsoc_muxmask lcd_24bits_muxmask[] = {
193static const struct sirfsoc_padmux lcd_24bits_padmux = { 198static const struct sirfsoc_padmux lcd_24bits_padmux = {
194 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask), 199 .muxmask_counts = ARRAY_SIZE(lcd_24bits_muxmask),
195 .muxmask = lcd_24bits_muxmask, 200 .muxmask = lcd_24bits_muxmask,
201 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
196 .funcmask = BIT(4), 202 .funcmask = BIT(4),
197 .funcval = 0, 203 .funcval = 0,
198}; 204};
@@ -218,6 +224,7 @@ static const struct sirfsoc_muxmask lcdrom_muxmask[] = {
218static const struct sirfsoc_padmux lcdrom_padmux = { 224static const struct sirfsoc_padmux lcdrom_padmux = {
219 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask), 225 .muxmask_counts = ARRAY_SIZE(lcdrom_muxmask),
220 .muxmask = lcdrom_muxmask, 226 .muxmask = lcdrom_muxmask,
227 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
221 .funcmask = BIT(4), 228 .funcmask = BIT(4),
222 .funcval = BIT(4), 229 .funcval = BIT(4),
223}; 230};
@@ -238,6 +245,7 @@ static const struct sirfsoc_muxmask uart0_muxmask[] = {
238static const struct sirfsoc_padmux uart0_padmux = { 245static const struct sirfsoc_padmux uart0_padmux = {
239 .muxmask_counts = ARRAY_SIZE(uart0_muxmask), 246 .muxmask_counts = ARRAY_SIZE(uart0_muxmask),
240 .muxmask = uart0_muxmask, 247 .muxmask = uart0_muxmask,
248 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
241 .funcmask = BIT(9), 249 .funcmask = BIT(9),
242 .funcval = BIT(9), 250 .funcval = BIT(9),
243}; 251};
@@ -282,6 +290,7 @@ static const struct sirfsoc_muxmask uart2_muxmask[] = {
282static const struct sirfsoc_padmux uart2_padmux = { 290static const struct sirfsoc_padmux uart2_padmux = {
283 .muxmask_counts = ARRAY_SIZE(uart2_muxmask), 291 .muxmask_counts = ARRAY_SIZE(uart2_muxmask),
284 .muxmask = uart2_muxmask, 292 .muxmask = uart2_muxmask,
293 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
285 .funcmask = BIT(10), 294 .funcmask = BIT(10),
286 .funcval = BIT(10), 295 .funcval = BIT(10),
287}; 296};
@@ -315,6 +324,7 @@ static const struct sirfsoc_muxmask sdmmc3_muxmask[] = {
315static const struct sirfsoc_padmux sdmmc3_padmux = { 324static const struct sirfsoc_padmux sdmmc3_padmux = {
316 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask), 325 .muxmask_counts = ARRAY_SIZE(sdmmc3_muxmask),
317 .muxmask = sdmmc3_muxmask, 326 .muxmask = sdmmc3_muxmask,
327 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
318 .funcmask = BIT(7), 328 .funcmask = BIT(7),
319 .funcval = 0, 329 .funcval = 0,
320}; 330};
@@ -331,6 +341,7 @@ static const struct sirfsoc_muxmask spi0_muxmask[] = {
331static const struct sirfsoc_padmux spi0_padmux = { 341static const struct sirfsoc_padmux spi0_padmux = {
332 .muxmask_counts = ARRAY_SIZE(spi0_muxmask), 342 .muxmask_counts = ARRAY_SIZE(spi0_muxmask),
333 .muxmask = spi0_muxmask, 343 .muxmask = spi0_muxmask,
344 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
334 .funcmask = BIT(7), 345 .funcmask = BIT(7),
335 .funcval = BIT(7), 346 .funcval = BIT(7),
336}; 347};
@@ -361,6 +372,7 @@ static const struct sirfsoc_muxmask cko1_muxmask[] = {
361static const struct sirfsoc_padmux cko1_padmux = { 372static const struct sirfsoc_padmux cko1_padmux = {
362 .muxmask_counts = ARRAY_SIZE(cko1_muxmask), 373 .muxmask_counts = ARRAY_SIZE(cko1_muxmask),
363 .muxmask = cko1_muxmask, 374 .muxmask = cko1_muxmask,
375 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
364 .funcmask = BIT(3), 376 .funcmask = BIT(3),
365 .funcval = 0, 377 .funcval = 0,
366}; 378};
@@ -379,6 +391,7 @@ static const struct sirfsoc_muxmask i2s_muxmask[] = {
379static const struct sirfsoc_padmux i2s_padmux = { 391static const struct sirfsoc_padmux i2s_padmux = {
380 .muxmask_counts = ARRAY_SIZE(i2s_muxmask), 392 .muxmask_counts = ARRAY_SIZE(i2s_muxmask),
381 .muxmask = i2s_muxmask, 393 .muxmask = i2s_muxmask,
394 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
382 .funcmask = BIT(3) | BIT(9), 395 .funcmask = BIT(3) | BIT(9),
383 .funcval = BIT(3), 396 .funcval = BIT(3),
384}; 397};
@@ -395,6 +408,7 @@ static const struct sirfsoc_muxmask ac97_muxmask[] = {
395static const struct sirfsoc_padmux ac97_padmux = { 408static const struct sirfsoc_padmux ac97_padmux = {
396 .muxmask_counts = ARRAY_SIZE(ac97_muxmask), 409 .muxmask_counts = ARRAY_SIZE(ac97_muxmask),
397 .muxmask = ac97_muxmask, 410 .muxmask = ac97_muxmask,
411 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
398 .funcmask = BIT(8), 412 .funcmask = BIT(8),
399 .funcval = 0, 413 .funcval = 0,
400}; 414};
@@ -411,6 +425,7 @@ static const struct sirfsoc_muxmask spi1_muxmask[] = {
411static const struct sirfsoc_padmux spi1_padmux = { 425static const struct sirfsoc_padmux spi1_padmux = {
412 .muxmask_counts = ARRAY_SIZE(spi1_muxmask), 426 .muxmask_counts = ARRAY_SIZE(spi1_muxmask),
413 .muxmask = spi1_muxmask, 427 .muxmask = spi1_muxmask,
428 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
414 .funcmask = BIT(8), 429 .funcmask = BIT(8),
415 .funcval = BIT(8), 430 .funcval = BIT(8),
416}; 431};
@@ -441,6 +456,7 @@ static const struct sirfsoc_muxmask gps_muxmask[] = {
441static const struct sirfsoc_padmux gps_padmux = { 456static const struct sirfsoc_padmux gps_padmux = {
442 .muxmask_counts = ARRAY_SIZE(gps_muxmask), 457 .muxmask_counts = ARRAY_SIZE(gps_muxmask),
443 .muxmask = gps_muxmask, 458 .muxmask = gps_muxmask,
459 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
444 .funcmask = BIT(12) | BIT(13) | BIT(14), 460 .funcmask = BIT(12) | BIT(13) | BIT(14),
445 .funcval = BIT(12), 461 .funcval = BIT(12),
446}; 462};
@@ -463,6 +479,7 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
463static const struct sirfsoc_padmux sdmmc5_padmux = { 479static const struct sirfsoc_padmux sdmmc5_padmux = {
464 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask), 480 .muxmask_counts = ARRAY_SIZE(sdmmc5_muxmask),
465 .muxmask = sdmmc5_muxmask, 481 .muxmask = sdmmc5_muxmask,
482 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
466 .funcmask = BIT(13) | BIT(14), 483 .funcmask = BIT(13) | BIT(14),
467 .funcval = BIT(13) | BIT(14), 484 .funcval = BIT(13) | BIT(14),
468}; 485};
@@ -479,12 +496,27 @@ static const struct sirfsoc_muxmask usp0_muxmask[] = {
479static const struct sirfsoc_padmux usp0_padmux = { 496static const struct sirfsoc_padmux usp0_padmux = {
480 .muxmask_counts = ARRAY_SIZE(usp0_muxmask), 497 .muxmask_counts = ARRAY_SIZE(usp0_muxmask),
481 .muxmask = usp0_muxmask, 498 .muxmask = usp0_muxmask,
499 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
482 .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9), 500 .funcmask = BIT(1) | BIT(2) | BIT(6) | BIT(9),
483 .funcval = 0, 501 .funcval = 0,
484}; 502};
485 503
486static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; 504static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
487 505
506static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
507 {
508 .group = 1,
509 .mask = BIT(20) | BIT(21),
510 },
511};
512
513static const struct sirfsoc_padmux usp0_uart_nostreamctrl_padmux = {
514 .muxmask_counts = ARRAY_SIZE(usp0_uart_nostreamctrl_muxmask),
515 .muxmask = usp0_uart_nostreamctrl_muxmask,
516};
517
518static const unsigned usp0_uart_nostreamctrl_pins[] = { 52, 53 };
519
488static const struct sirfsoc_muxmask usp1_muxmask[] = { 520static const struct sirfsoc_muxmask usp1_muxmask[] = {
489 { 521 {
490 .group = 1, 522 .group = 1,
@@ -495,12 +527,27 @@ static const struct sirfsoc_muxmask usp1_muxmask[] = {
495static const struct sirfsoc_padmux usp1_padmux = { 527static const struct sirfsoc_padmux usp1_padmux = {
496 .muxmask_counts = ARRAY_SIZE(usp1_muxmask), 528 .muxmask_counts = ARRAY_SIZE(usp1_muxmask),
497 .muxmask = usp1_muxmask, 529 .muxmask = usp1_muxmask,
530 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
498 .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11), 531 .funcmask = BIT(1) | BIT(9) | BIT(10) | BIT(11),
499 .funcval = 0, 532 .funcval = 0,
500}; 533};
501 534
502static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 }; 535static const unsigned usp1_pins[] = { 56, 57, 58, 59, 60 };
503 536
537static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
538 {
539 .group = 1,
540 .mask = BIT(25) | BIT(26),
541 },
542};
543
544static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
545 .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
546 .muxmask = usp1_uart_nostreamctrl_muxmask,
547};
548
549static const unsigned usp1_uart_nostreamctrl_pins[] = { 57, 58 };
550
504static const struct sirfsoc_muxmask usp2_muxmask[] = { 551static const struct sirfsoc_muxmask usp2_muxmask[] = {
505 { 552 {
506 .group = 1, 553 .group = 1,
@@ -514,12 +561,27 @@ static const struct sirfsoc_muxmask usp2_muxmask[] = {
514static const struct sirfsoc_padmux usp2_padmux = { 561static const struct sirfsoc_padmux usp2_padmux = {
515 .muxmask_counts = ARRAY_SIZE(usp2_muxmask), 562 .muxmask_counts = ARRAY_SIZE(usp2_muxmask),
516 .muxmask = usp2_muxmask, 563 .muxmask = usp2_muxmask,
564 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
517 .funcmask = BIT(13) | BIT(14), 565 .funcmask = BIT(13) | BIT(14),
518 .funcval = 0, 566 .funcval = 0,
519}; 567};
520 568
521static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 }; 569static const unsigned usp2_pins[] = { 61, 62, 63, 64, 65 };
522 570
571static const struct sirfsoc_muxmask usp2_uart_nostreamctrl_muxmask[] = {
572 {
573 .group = 1,
574 .mask = BIT(30) | BIT(31),
575 },
576};
577
578static const struct sirfsoc_padmux usp2_uart_nostreamctrl_padmux = {
579 .muxmask_counts = ARRAY_SIZE(usp2_uart_nostreamctrl_muxmask),
580 .muxmask = usp2_uart_nostreamctrl_muxmask,
581};
582
583static const unsigned usp2_uart_nostreamctrl_pins[] = { 62, 63 };
584
523static const struct sirfsoc_muxmask nand_muxmask[] = { 585static const struct sirfsoc_muxmask nand_muxmask[] = {
524 { 586 {
525 .group = 2, 587 .group = 2,
@@ -530,6 +592,7 @@ static const struct sirfsoc_muxmask nand_muxmask[] = {
530static const struct sirfsoc_padmux nand_padmux = { 592static const struct sirfsoc_padmux nand_padmux = {
531 .muxmask_counts = ARRAY_SIZE(nand_muxmask), 593 .muxmask_counts = ARRAY_SIZE(nand_muxmask),
532 .muxmask = nand_muxmask, 594 .muxmask = nand_muxmask,
595 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
533 .funcmask = BIT(5), 596 .funcmask = BIT(5),
534 .funcval = 0, 597 .funcval = 0,
535}; 598};
@@ -538,6 +601,7 @@ static const unsigned nand_pins[] = { 64, 65, 92, 93, 94 };
538 601
539static const struct sirfsoc_padmux sdmmc0_padmux = { 602static const struct sirfsoc_padmux sdmmc0_padmux = {
540 .muxmask_counts = 0, 603 .muxmask_counts = 0,
604 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
541 .funcmask = BIT(5), 605 .funcmask = BIT(5),
542 .funcval = 0, 606 .funcval = 0,
543}; 607};
@@ -554,6 +618,7 @@ static const struct sirfsoc_muxmask sdmmc2_muxmask[] = {
554static const struct sirfsoc_padmux sdmmc2_padmux = { 618static const struct sirfsoc_padmux sdmmc2_padmux = {
555 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask), 619 .muxmask_counts = ARRAY_SIZE(sdmmc2_muxmask),
556 .muxmask = sdmmc2_muxmask, 620 .muxmask = sdmmc2_muxmask,
621 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
557 .funcmask = BIT(5), 622 .funcmask = BIT(5),
558 .funcval = BIT(5), 623 .funcval = BIT(5),
559}; 624};
@@ -586,6 +651,7 @@ static const struct sirfsoc_muxmask vip_muxmask[] = {
586static const struct sirfsoc_padmux vip_padmux = { 651static const struct sirfsoc_padmux vip_padmux = {
587 .muxmask_counts = ARRAY_SIZE(vip_muxmask), 652 .muxmask_counts = ARRAY_SIZE(vip_muxmask),
588 .muxmask = vip_muxmask, 653 .muxmask = vip_muxmask,
654 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
589 .funcmask = BIT(0), 655 .funcmask = BIT(0),
590 .funcval = 0, 656 .funcval = 0,
591}; 657};
@@ -635,6 +701,7 @@ static const struct sirfsoc_muxmask viprom_muxmask[] = {
635static const struct sirfsoc_padmux viprom_padmux = { 701static const struct sirfsoc_padmux viprom_padmux = {
636 .muxmask_counts = ARRAY_SIZE(viprom_muxmask), 702 .muxmask_counts = ARRAY_SIZE(viprom_muxmask),
637 .muxmask = viprom_muxmask, 703 .muxmask = viprom_muxmask,
704 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
638 .funcmask = BIT(0), 705 .funcmask = BIT(0),
639 .funcval = BIT(0), 706 .funcval = BIT(0),
640}; 707};
@@ -651,6 +718,7 @@ static const struct sirfsoc_muxmask pwm0_muxmask[] = {
651static const struct sirfsoc_padmux pwm0_padmux = { 718static const struct sirfsoc_padmux pwm0_padmux = {
652 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask), 719 .muxmask_counts = ARRAY_SIZE(pwm0_muxmask),
653 .muxmask = pwm0_muxmask, 720 .muxmask = pwm0_muxmask,
721 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
654 .funcmask = BIT(12), 722 .funcmask = BIT(12),
655 .funcval = 0, 723 .funcval = 0,
656}; 724};
@@ -722,6 +790,7 @@ static const struct sirfsoc_muxmask usb0_utmi_drvbus_muxmask[] = {
722static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = { 790static const struct sirfsoc_padmux usb0_utmi_drvbus_padmux = {
723 .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask), 791 .muxmask_counts = ARRAY_SIZE(usb0_utmi_drvbus_muxmask),
724 .muxmask = usb0_utmi_drvbus_muxmask, 792 .muxmask = usb0_utmi_drvbus_muxmask,
793 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
725 .funcmask = BIT(6), 794 .funcmask = BIT(6),
726 .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */ 795 .funcval = BIT(6), /* refer to PAD_UTMI_DRVVBUS0_ENABLE */
727}; 796};
@@ -738,12 +807,31 @@ static const struct sirfsoc_muxmask usb1_utmi_drvbus_muxmask[] = {
738static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = { 807static const struct sirfsoc_padmux usb1_utmi_drvbus_padmux = {
739 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask), 808 .muxmask_counts = ARRAY_SIZE(usb1_utmi_drvbus_muxmask),
740 .muxmask = usb1_utmi_drvbus_muxmask, 809 .muxmask = usb1_utmi_drvbus_muxmask,
810 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
741 .funcmask = BIT(11), 811 .funcmask = BIT(11),
742 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */ 812 .funcval = BIT(11), /* refer to PAD_UTMI_DRVVBUS1_ENABLE */
743}; 813};
744 814
745static const unsigned usb1_utmi_drvbus_pins[] = { 59 }; 815static const unsigned usb1_utmi_drvbus_pins[] = { 59 };
746 816
817static const struct sirfsoc_padmux usb1_dp_dn_padmux = {
818 .muxmask_counts = 0,
819 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
820 .funcmask = BIT(2),
821 .funcval = BIT(2),
822};
823
824static const unsigned usb1_dp_dn_pins[] = { 115, 116 };
825
826static const struct sirfsoc_padmux uart1_route_io_usb1_padmux = {
827 .muxmask_counts = 0,
828 .ctrlreg = SIRFSOC_RSC_USB_UART_SHARE,
829 .funcmask = BIT(2),
830 .funcval = 0,
831};
832
833static const unsigned uart1_route_io_usb1_pins[] = { 115, 116 };
834
747static const struct sirfsoc_muxmask pulse_count_muxmask[] = { 835static const struct sirfsoc_muxmask pulse_count_muxmask[] = {
748 { 836 {
749 .group = 0, 837 .group = 0,
@@ -764,12 +852,19 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
764 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins), 852 SIRFSOC_PIN_GROUP("lcd_24bitsgrp", lcd_24bits_pins),
765 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins), 853 SIRFSOC_PIN_GROUP("lcdrom_grp", lcdrom_pins),
766 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins), 854 SIRFSOC_PIN_GROUP("uart0grp", uart0_pins),
855 SIRFSOC_PIN_GROUP("uart0_nostreamctrlgrp", uart0_nostreamctrl_pins),
767 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins), 856 SIRFSOC_PIN_GROUP("uart1grp", uart1_pins),
768 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins), 857 SIRFSOC_PIN_GROUP("uart2grp", uart2_pins),
769 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins), 858 SIRFSOC_PIN_GROUP("uart2_nostreamctrlgrp", uart2_nostreamctrl_pins),
770 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), 859 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
860 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
861 usp0_uart_nostreamctrl_pins),
771 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), 862 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
863 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
864 usp1_uart_nostreamctrl_pins),
772 SIRFSOC_PIN_GROUP("usp2grp", usp2_pins), 865 SIRFSOC_PIN_GROUP("usp2grp", usp2_pins),
866 SIRFSOC_PIN_GROUP("usp2_uart_nostreamctrl_grp",
867 usp2_uart_nostreamctrl_pins),
773 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), 868 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
774 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), 869 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
775 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), 870 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
@@ -789,6 +884,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
789 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins), 884 SIRFSOC_PIN_GROUP("sdmmc5grp", sdmmc5_pins),
790 SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins), 885 SIRFSOC_PIN_GROUP("usb0_utmi_drvbusgrp", usb0_utmi_drvbus_pins),
791 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins), 886 SIRFSOC_PIN_GROUP("usb1_utmi_drvbusgrp", usb1_utmi_drvbus_pins),
887 SIRFSOC_PIN_GROUP("usb1_dp_dngrp", usb1_dp_dn_pins),
888 SIRFSOC_PIN_GROUP("uart1_route_io_usb1grp", uart1_route_io_usb1_pins),
792 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins), 889 SIRFSOC_PIN_GROUP("pulse_countgrp", pulse_count_pins),
793 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins), 890 SIRFSOC_PIN_GROUP("i2sgrp", i2s_pins),
794 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins), 891 SIRFSOC_PIN_GROUP("ac97grp", ac97_pins),
@@ -803,12 +900,19 @@ static const char * const lcd_18bitsgrp[] = { "lcd_18bitsgrp" };
803static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" }; 900static const char * const lcd_24bitsgrp[] = { "lcd_24bitsgrp" };
804static const char * const lcdromgrp[] = { "lcdromgrp" }; 901static const char * const lcdromgrp[] = { "lcdromgrp" };
805static const char * const uart0grp[] = { "uart0grp" }; 902static const char * const uart0grp[] = { "uart0grp" };
903static const char * const uart0_nostreamctrlgrp[] = { "uart0_nostreamctrlgrp" };
806static const char * const uart1grp[] = { "uart1grp" }; 904static const char * const uart1grp[] = { "uart1grp" };
807static const char * const uart2grp[] = { "uart2grp" }; 905static const char * const uart2grp[] = { "uart2grp" };
808static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" }; 906static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
809static const char * const usp0grp[] = { "usp0grp" }; 907static const char * const usp0grp[] = { "usp0grp" };
908static const char * const usp0_uart_nostreamctrl_grp[] =
909 { "usp0_uart_nostreamctrl_grp" };
810static const char * const usp1grp[] = { "usp1grp" }; 910static const char * const usp1grp[] = { "usp1grp" };
911static const char * const usp1_uart_nostreamctrl_grp[] =
912 { "usp1_uart_nostreamctrl_grp" };
811static const char * const usp2grp[] = { "usp2grp" }; 913static const char * const usp2grp[] = { "usp2grp" };
914static const char * const usp2_uart_nostreamctrl_grp[] =
915 { "usp2_uart_nostreamctrl_grp" };
812static const char * const i2c0grp[] = { "i2c0grp" }; 916static const char * const i2c0grp[] = { "i2c0grp" };
813static const char * const i2c1grp[] = { "i2c1grp" }; 917static const char * const i2c1grp[] = { "i2c1grp" };
814static const char * const pwm0grp[] = { "pwm0grp" }; 918static const char * const pwm0grp[] = { "pwm0grp" };
@@ -828,6 +932,8 @@ static const char * const sdmmc4grp[] = { "sdmmc4grp" };
828static const char * const sdmmc5grp[] = { "sdmmc5grp" }; 932static const char * const sdmmc5grp[] = { "sdmmc5grp" };
829static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" }; 933static const char * const usb0_utmi_drvbusgrp[] = { "usb0_utmi_drvbusgrp" };
830static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" }; 934static const char * const usb1_utmi_drvbusgrp[] = { "usb1_utmi_drvbusgrp" };
935static const char * const usb1_dp_dngrp[] = { "usb1_dp_dngrp" };
936static const char * const uart1_route_io_usb1grp[] = { "uart1_route_io_usb1grp" };
831static const char * const pulse_countgrp[] = { "pulse_countgrp" }; 937static const char * const pulse_countgrp[] = { "pulse_countgrp" };
832static const char * const i2sgrp[] = { "i2sgrp" }; 938static const char * const i2sgrp[] = { "i2sgrp" };
833static const char * const ac97grp[] = { "ac97grp" }; 939static const char * const ac97grp[] = { "ac97grp" };
@@ -842,12 +948,19 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
842 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux), 948 SIRFSOC_PMX_FUNCTION("lcd_24bits", lcd_24bitsgrp, lcd_24bits_padmux),
843 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux), 949 SIRFSOC_PMX_FUNCTION("lcdrom", lcdromgrp, lcdrom_padmux),
844 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux), 950 SIRFSOC_PMX_FUNCTION("uart0", uart0grp, uart0_padmux),
951 SIRFSOC_PMX_FUNCTION("uart0_nostreamctrl", uart0_nostreamctrlgrp, uart0_nostreamctrl_padmux),
845 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux), 952 SIRFSOC_PMX_FUNCTION("uart1", uart1grp, uart1_padmux),
846 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux), 953 SIRFSOC_PMX_FUNCTION("uart2", uart2grp, uart2_padmux),
847 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux), 954 SIRFSOC_PMX_FUNCTION("uart2_nostreamctrl", uart2_nostreamctrlgrp, uart2_nostreamctrl_padmux),
848 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), 955 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
956 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
957 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
849 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), 958 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
959 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
960 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
850 SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux), 961 SIRFSOC_PMX_FUNCTION("usp2", usp2grp, usp2_padmux),
962 SIRFSOC_PMX_FUNCTION("usp2_uart_nostreamctrl",
963 usp2_uart_nostreamctrl_grp, usp2_uart_nostreamctrl_padmux),
851 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), 964 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
852 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), 965 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
853 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), 966 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
@@ -867,6 +980,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
867 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux), 980 SIRFSOC_PMX_FUNCTION("sdmmc5", sdmmc5grp, sdmmc5_padmux),
868 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux), 981 SIRFSOC_PMX_FUNCTION("usb0_utmi_drvbus", usb0_utmi_drvbusgrp, usb0_utmi_drvbus_padmux),
869 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux), 982 SIRFSOC_PMX_FUNCTION("usb1_utmi_drvbus", usb1_utmi_drvbusgrp, usb1_utmi_drvbus_padmux),
983 SIRFSOC_PMX_FUNCTION("usb1_dp_dn", usb1_dp_dngrp, usb1_dp_dn_padmux),
984 SIRFSOC_PMX_FUNCTION("uart1_route_io_usb1", uart1_route_io_usb1grp, uart1_route_io_usb1_padmux),
870 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux), 985 SIRFSOC_PMX_FUNCTION("pulse_count", pulse_countgrp, pulse_count_padmux),
871 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux), 986 SIRFSOC_PMX_FUNCTION("i2s", i2sgrp, i2s_padmux),
872 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux), 987 SIRFSOC_PMX_FUNCTION("ac97", ac97grp, ac97_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index 26f946af7933..b81e388c50de 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -166,12 +166,12 @@ static void sirfsoc_pinmux_endisable(struct sirfsoc_pmx *spmx, unsigned selector
166 166
167 if (mux->funcmask && enable) { 167 if (mux->funcmask && enable) {
168 u32 func_en_val; 168 u32 func_en_val;
169
169 func_en_val = 170 func_en_val =
170 readl(spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX); 171 readl(spmx->rsc_virtbase + mux->ctrlreg);
171 func_en_val = 172 func_en_val =
172 (func_en_val & ~mux->funcmask) | (mux-> 173 (func_en_val & ~mux->funcmask) | (mux->funcval);
173 funcval); 174 writel(func_en_val, spmx->rsc_virtbase + mux->ctrlreg);
174 writel(func_en_val, spmx->rsc_virtbase + SIRFSOC_RSC_PIN_MUX);
175 } 175 }
176} 176}
177 177
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.h b/drivers/pinctrl/sirf/pinctrl-sirf.h
index 17cc108510ba..d7f16b499ad9 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.h
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.h
@@ -9,8 +9,9 @@
9#ifndef __PINMUX_SIRF_H__ 9#ifndef __PINMUX_SIRF_H__
10#define __PINMUX_SIRF_H__ 10#define __PINMUX_SIRF_H__
11 11
12#define SIRFSOC_NUM_PADS 622 12#define SIRFSOC_NUM_PADS 622
13#define SIRFSOC_RSC_PIN_MUX 0x4 13#define SIRFSOC_RSC_USB_UART_SHARE 0
14#define SIRFSOC_RSC_PIN_MUX 0x4
14 15
15#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84) 16#define SIRFSOC_GPIO_PAD_EN(g) ((g)*0x100 + 0x84)
16#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90) 17#define SIRFSOC_GPIO_PAD_EN_CLR(g) ((g)*0x100 + 0x90)
@@ -61,6 +62,7 @@ struct sirfsoc_padmux {
61 unsigned long muxmask_counts; 62 unsigned long muxmask_counts;
62 const struct sirfsoc_muxmask *muxmask; 63 const struct sirfsoc_muxmask *muxmask;
63 /* RSC_PIN_MUX set */ 64 /* RSC_PIN_MUX set */
65 unsigned long ctrlreg;
64 unsigned long funcmask; 66 unsigned long funcmask;
65 unsigned long funcval; 67 unsigned long funcval;
66}; 68};
diff --git a/drivers/pinctrl/spear/pinctrl-plgpio.c b/drivers/pinctrl/spear/pinctrl-plgpio.c
index 0a7f0bdbaa7d..ff2940e9f2a7 100644
--- a/drivers/pinctrl/spear/pinctrl-plgpio.c
+++ b/drivers/pinctrl/spear/pinctrl-plgpio.c
@@ -735,7 +735,7 @@ static struct platform_driver plgpio_driver = {
735 .owner = THIS_MODULE, 735 .owner = THIS_MODULE,
736 .name = "spear-plgpio", 736 .name = "spear-plgpio",
737 .pm = &plgpio_dev_pm_ops, 737 .pm = &plgpio_dev_pm_ops,
738 .of_match_table = of_match_ptr(plgpio_of_match), 738 .of_match_table = plgpio_of_match,
739 }, 739 },
740}; 740};
741 741
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-27 07:57:05 -0500