diff options
Diffstat (limited to 'drivers')
34 files changed, 7841 insertions, 302 deletions
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile index 3f1f829260bb..708ffb2165ea 100644 --- a/drivers/gpio/Makefile +++ b/drivers/gpio/Makefile | |||
@@ -37,7 +37,6 @@ obj-$(CONFIG_GPIO_MSM_V1) += gpio-msm-v1.o | |||
37 | obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o | 37 | obj-$(CONFIG_GPIO_MSM_V2) += gpio-msm-v2.o |
38 | obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o | 38 | obj-$(CONFIG_GPIO_MXC) += gpio-mxc.o |
39 | obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o | 39 | obj-$(CONFIG_GPIO_MXS) += gpio-mxs.o |
40 | obj-$(CONFIG_PLAT_NOMADIK) += gpio-nomadik.o | ||
41 | obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o | 40 | obj-$(CONFIG_ARCH_OMAP) += gpio-omap.o |
42 | obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o | 41 | obj-$(CONFIG_GPIO_PCA953X) += gpio-pca953x.o |
43 | obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o | 42 | obj-$(CONFIG_GPIO_PCF857X) += gpio-pcf857x.o |
diff --git a/drivers/gpio/gpio-tegra.c b/drivers/gpio/gpio-tegra.c index 12f349b3830d..dc5184d57892 100644 --- a/drivers/gpio/gpio-tegra.c +++ b/drivers/gpio/gpio-tegra.c | |||
@@ -26,10 +26,10 @@ | |||
26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
27 | #include <linux/module.h> | 27 | #include <linux/module.h> |
28 | #include <linux/irqdomain.h> | 28 | #include <linux/irqdomain.h> |
29 | #include <linux/pinctrl/consumer.h> | ||
29 | 30 | ||
30 | #include <asm/mach/irq.h> | 31 | #include <asm/mach/irq.h> |
31 | 32 | ||
32 | #include <mach/gpio-tegra.h> | ||
33 | #include <mach/iomap.h> | 33 | #include <mach/iomap.h> |
34 | #include <mach/suspend.h> | 34 | #include <mach/suspend.h> |
35 | 35 | ||
@@ -108,18 +108,29 @@ static void tegra_gpio_mask_write(u32 reg, int gpio, int value) | |||
108 | tegra_gpio_writel(val, reg); | 108 | tegra_gpio_writel(val, reg); |
109 | } | 109 | } |
110 | 110 | ||
111 | void tegra_gpio_enable(int gpio) | 111 | static void tegra_gpio_enable(int gpio) |
112 | { | 112 | { |
113 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); | 113 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); |
114 | } | 114 | } |
115 | EXPORT_SYMBOL_GPL(tegra_gpio_enable); | 115 | EXPORT_SYMBOL_GPL(tegra_gpio_enable); |
116 | 116 | ||
117 | void tegra_gpio_disable(int gpio) | 117 | static void tegra_gpio_disable(int gpio) |
118 | { | 118 | { |
119 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); | 119 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); |
120 | } | 120 | } |
121 | EXPORT_SYMBOL_GPL(tegra_gpio_disable); | 121 | EXPORT_SYMBOL_GPL(tegra_gpio_disable); |
122 | 122 | ||
123 | int tegra_gpio_request(struct gpio_chip *chip, unsigned offset) | ||
124 | { | ||
125 | return pinctrl_request_gpio(offset); | ||
126 | } | ||
127 | |||
128 | void tegra_gpio_free(struct gpio_chip *chip, unsigned offset) | ||
129 | { | ||
130 | pinctrl_free_gpio(offset); | ||
131 | tegra_gpio_disable(offset); | ||
132 | } | ||
133 | |||
123 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | 134 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) |
124 | { | 135 | { |
125 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); | 136 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); |
@@ -133,6 +144,7 @@ static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) | |||
133 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | 144 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
134 | { | 145 | { |
135 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); | 146 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); |
147 | tegra_gpio_enable(offset); | ||
136 | return 0; | 148 | return 0; |
137 | } | 149 | } |
138 | 150 | ||
@@ -141,6 +153,7 @@ static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |||
141 | { | 153 | { |
142 | tegra_gpio_set(chip, offset, value); | 154 | tegra_gpio_set(chip, offset, value); |
143 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); | 155 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); |
156 | tegra_gpio_enable(offset); | ||
144 | return 0; | 157 | return 0; |
145 | } | 158 | } |
146 | 159 | ||
@@ -151,13 +164,14 @@ static int tegra_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |||
151 | 164 | ||
152 | static struct gpio_chip tegra_gpio_chip = { | 165 | static struct gpio_chip tegra_gpio_chip = { |
153 | .label = "tegra-gpio", | 166 | .label = "tegra-gpio", |
167 | .request = tegra_gpio_request, | ||
168 | .free = tegra_gpio_free, | ||
154 | .direction_input = tegra_gpio_direction_input, | 169 | .direction_input = tegra_gpio_direction_input, |
155 | .get = tegra_gpio_get, | 170 | .get = tegra_gpio_get, |
156 | .direction_output = tegra_gpio_direction_output, | 171 | .direction_output = tegra_gpio_direction_output, |
157 | .set = tegra_gpio_set, | 172 | .set = tegra_gpio_set, |
158 | .to_irq = tegra_gpio_to_irq, | 173 | .to_irq = tegra_gpio_to_irq, |
159 | .base = 0, | 174 | .base = 0, |
160 | .ngpio = TEGRA_NR_GPIOS, | ||
161 | }; | 175 | }; |
162 | 176 | ||
163 | static void tegra_gpio_irq_ack(struct irq_data *d) | 177 | static void tegra_gpio_irq_ack(struct irq_data *d) |
@@ -224,6 +238,9 @@ static int tegra_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |||
224 | 238 | ||
225 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | 239 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); |
226 | 240 | ||
241 | tegra_gpio_mask_write(GPIO_MSK_OE(gpio), gpio, 0); | ||
242 | tegra_gpio_enable(gpio); | ||
243 | |||
227 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | 244 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) |
228 | __irq_set_handler_locked(d->irq, handle_level_irq); | 245 | __irq_set_handler_locked(d->irq, handle_level_irq); |
229 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | 246 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) |
@@ -490,20 +507,6 @@ static int __init tegra_gpio_init(void) | |||
490 | } | 507 | } |
491 | postcore_initcall(tegra_gpio_init); | 508 | postcore_initcall(tegra_gpio_init); |
492 | 509 | ||
493 | void tegra_gpio_config(struct tegra_gpio_table *table, int num) | ||
494 | { | ||
495 | int i; | ||
496 | |||
497 | for (i = 0; i < num; i++) { | ||
498 | int gpio = table[i].gpio; | ||
499 | |||
500 | if (table[i].enable) | ||
501 | tegra_gpio_enable(gpio); | ||
502 | else | ||
503 | tegra_gpio_disable(gpio); | ||
504 | } | ||
505 | } | ||
506 | |||
507 | #ifdef CONFIG_DEBUG_FS | 510 | #ifdef CONFIG_DEBUG_FS |
508 | 511 | ||
509 | #include <linux/debugfs.h> | 512 | #include <linux/debugfs.h> |
diff --git a/drivers/i2c/busses/i2c-imx.c b/drivers/i2c/busses/i2c-imx.c index dfb84b7ee550..56bce9a8bcbb 100644 --- a/drivers/i2c/busses/i2c-imx.c +++ b/drivers/i2c/busses/i2c-imx.c | |||
@@ -51,6 +51,7 @@ | |||
51 | #include <linux/of.h> | 51 | #include <linux/of.h> |
52 | #include <linux/of_device.h> | 52 | #include <linux/of_device.h> |
53 | #include <linux/of_i2c.h> | 53 | #include <linux/of_i2c.h> |
54 | #include <linux/pinctrl/consumer.h> | ||
54 | 55 | ||
55 | #include <mach/irqs.h> | 56 | #include <mach/irqs.h> |
56 | #include <mach/hardware.h> | 57 | #include <mach/hardware.h> |
@@ -470,6 +471,7 @@ static int __init i2c_imx_probe(struct platform_device *pdev) | |||
470 | struct imx_i2c_struct *i2c_imx; | 471 | struct imx_i2c_struct *i2c_imx; |
471 | struct resource *res; | 472 | struct resource *res; |
472 | struct imxi2c_platform_data *pdata = pdev->dev.platform_data; | 473 | struct imxi2c_platform_data *pdata = pdev->dev.platform_data; |
474 | struct pinctrl *pinctrl; | ||
473 | void __iomem *base; | 475 | void __iomem *base; |
474 | resource_size_t res_size; | 476 | resource_size_t res_size; |
475 | int irq, bitrate; | 477 | int irq, bitrate; |
@@ -520,6 +522,12 @@ static int __init i2c_imx_probe(struct platform_device *pdev) | |||
520 | i2c_imx->base = base; | 522 | i2c_imx->base = base; |
521 | i2c_imx->res = res; | 523 | i2c_imx->res = res; |
522 | 524 | ||
525 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
526 | if (IS_ERR(pinctrl)) { | ||
527 | ret = PTR_ERR(pinctrl); | ||
528 | goto fail3; | ||
529 | } | ||
530 | |||
523 | /* Get I2C clock */ | 531 | /* Get I2C clock */ |
524 | i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk"); | 532 | i2c_imx->clk = clk_get(&pdev->dev, "i2c_clk"); |
525 | if (IS_ERR(i2c_imx->clk)) { | 533 | if (IS_ERR(i2c_imx->clk)) { |
diff --git a/drivers/i2c/busses/i2c-mxs.c b/drivers/i2c/busses/i2c-mxs.c index 76b8af44f634..7fa73eed84a7 100644 --- a/drivers/i2c/busses/i2c-mxs.c +++ b/drivers/i2c/busses/i2c-mxs.c | |||
@@ -26,6 +26,7 @@ | |||
26 | #include <linux/platform_device.h> | 26 | #include <linux/platform_device.h> |
27 | #include <linux/jiffies.h> | 27 | #include <linux/jiffies.h> |
28 | #include <linux/io.h> | 28 | #include <linux/io.h> |
29 | #include <linux/pinctrl/consumer.h> | ||
29 | 30 | ||
30 | #include <mach/common.h> | 31 | #include <mach/common.h> |
31 | 32 | ||
@@ -325,10 +326,15 @@ static int __devinit mxs_i2c_probe(struct platform_device *pdev) | |||
325 | struct device *dev = &pdev->dev; | 326 | struct device *dev = &pdev->dev; |
326 | struct mxs_i2c_dev *i2c; | 327 | struct mxs_i2c_dev *i2c; |
327 | struct i2c_adapter *adap; | 328 | struct i2c_adapter *adap; |
329 | struct pinctrl *pinctrl; | ||
328 | struct resource *res; | 330 | struct resource *res; |
329 | resource_size_t res_size; | 331 | resource_size_t res_size; |
330 | int err, irq; | 332 | int err, irq; |
331 | 333 | ||
334 | pinctrl = devm_pinctrl_get_select_default(dev); | ||
335 | if (IS_ERR(pinctrl)) | ||
336 | return PTR_ERR(pinctrl); | ||
337 | |||
332 | i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); | 338 | i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL); |
333 | if (!i2c) | 339 | if (!i2c) |
334 | return -ENOMEM; | 340 | return -ENOMEM; |
diff --git a/drivers/mmc/host/mxs-mmc.c b/drivers/mmc/host/mxs-mmc.c index e3f5af96ab87..bb03ddda481d 100644 --- a/drivers/mmc/host/mxs-mmc.c +++ b/drivers/mmc/host/mxs-mmc.c | |||
@@ -39,6 +39,7 @@ | |||
39 | #include <linux/regulator/consumer.h> | 39 | #include <linux/regulator/consumer.h> |
40 | #include <linux/module.h> | 40 | #include <linux/module.h> |
41 | #include <linux/fsl/mxs-dma.h> | 41 | #include <linux/fsl/mxs-dma.h> |
42 | #include <linux/pinctrl/consumer.h> | ||
42 | 43 | ||
43 | #include <mach/mxs.h> | 44 | #include <mach/mxs.h> |
44 | #include <mach/common.h> | 45 | #include <mach/common.h> |
@@ -682,6 +683,7 @@ static int mxs_mmc_probe(struct platform_device *pdev) | |||
682 | struct mmc_host *mmc; | 683 | struct mmc_host *mmc; |
683 | struct resource *iores, *dmares, *r; | 684 | struct resource *iores, *dmares, *r; |
684 | struct mxs_mmc_platform_data *pdata; | 685 | struct mxs_mmc_platform_data *pdata; |
686 | struct pinctrl *pinctrl; | ||
685 | int ret = 0, irq_err, irq_dma; | 687 | int ret = 0, irq_err, irq_dma; |
686 | dma_cap_mask_t mask; | 688 | dma_cap_mask_t mask; |
687 | 689 | ||
@@ -719,6 +721,12 @@ static int mxs_mmc_probe(struct platform_device *pdev) | |||
719 | host->irq = irq_err; | 721 | host->irq = irq_err; |
720 | host->sdio_irq_en = 0; | 722 | host->sdio_irq_en = 0; |
721 | 723 | ||
724 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
725 | if (IS_ERR(pinctrl)) { | ||
726 | ret = PTR_ERR(pinctrl); | ||
727 | goto out_iounmap; | ||
728 | } | ||
729 | |||
722 | host->clk = clk_get(&pdev->dev, NULL); | 730 | host->clk = clk_get(&pdev->dev, NULL); |
723 | if (IS_ERR(host->clk)) { | 731 | if (IS_ERR(host->clk)) { |
724 | ret = PTR_ERR(host->clk); | 732 | ret = PTR_ERR(host->clk); |
diff --git a/drivers/mmc/host/sdhci-esdhc-imx.c b/drivers/mmc/host/sdhci-esdhc-imx.c index 8abdaf6697a8..d190d04636a7 100644 --- a/drivers/mmc/host/sdhci-esdhc-imx.c +++ b/drivers/mmc/host/sdhci-esdhc-imx.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/of.h> | 24 | #include <linux/of.h> |
25 | #include <linux/of_device.h> | 25 | #include <linux/of_device.h> |
26 | #include <linux/of_gpio.h> | 26 | #include <linux/of_gpio.h> |
27 | #include <linux/pinctrl/consumer.h> | ||
27 | #include <mach/esdhc.h> | 28 | #include <mach/esdhc.h> |
28 | #include "sdhci-pltfm.h" | 29 | #include "sdhci-pltfm.h" |
29 | #include "sdhci-esdhc.h" | 30 | #include "sdhci-esdhc.h" |
@@ -68,6 +69,7 @@ struct pltfm_imx_data { | |||
68 | int flags; | 69 | int flags; |
69 | u32 scratchpad; | 70 | u32 scratchpad; |
70 | enum imx_esdhc_type devtype; | 71 | enum imx_esdhc_type devtype; |
72 | struct pinctrl *pinctrl; | ||
71 | struct esdhc_platform_data boarddata; | 73 | struct esdhc_platform_data boarddata; |
72 | }; | 74 | }; |
73 | 75 | ||
@@ -467,6 +469,12 @@ static int __devinit sdhci_esdhc_imx_probe(struct platform_device *pdev) | |||
467 | clk_prepare_enable(clk); | 469 | clk_prepare_enable(clk); |
468 | pltfm_host->clk = clk; | 470 | pltfm_host->clk = clk; |
469 | 471 | ||
472 | imx_data->pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
473 | if (IS_ERR(imx_data->pinctrl)) { | ||
474 | err = PTR_ERR(imx_data->pinctrl); | ||
475 | goto pin_err; | ||
476 | } | ||
477 | |||
470 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; | 478 | host->quirks |= SDHCI_QUIRK_BROKEN_TIMEOUT_VAL; |
471 | 479 | ||
472 | if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) | 480 | if (is_imx25_esdhc(imx_data) || is_imx35_esdhc(imx_data)) |
@@ -558,6 +566,7 @@ no_card_detect_irq: | |||
558 | gpio_free(boarddata->wp_gpio); | 566 | gpio_free(boarddata->wp_gpio); |
559 | no_card_detect_pin: | 567 | no_card_detect_pin: |
560 | no_board_data: | 568 | no_board_data: |
569 | pin_err: | ||
561 | clk_disable_unprepare(pltfm_host->clk); | 570 | clk_disable_unprepare(pltfm_host->clk); |
562 | clk_put(pltfm_host->clk); | 571 | clk_put(pltfm_host->clk); |
563 | err_clk_get: | 572 | err_clk_get: |
diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 53b26502f6e2..ff5a16991939 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c | |||
@@ -269,7 +269,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) | |||
269 | "failed to allocate power gpio\n"); | 269 | "failed to allocate power gpio\n"); |
270 | goto err_power_req; | 270 | goto err_power_req; |
271 | } | 271 | } |
272 | tegra_gpio_enable(plat->power_gpio); | ||
273 | gpio_direction_output(plat->power_gpio, 1); | 272 | gpio_direction_output(plat->power_gpio, 1); |
274 | } | 273 | } |
275 | 274 | ||
@@ -280,7 +279,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) | |||
280 | "failed to allocate cd gpio\n"); | 279 | "failed to allocate cd gpio\n"); |
281 | goto err_cd_req; | 280 | goto err_cd_req; |
282 | } | 281 | } |
283 | tegra_gpio_enable(plat->cd_gpio); | ||
284 | gpio_direction_input(plat->cd_gpio); | 282 | gpio_direction_input(plat->cd_gpio); |
285 | 283 | ||
286 | rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq, | 284 | rc = request_irq(gpio_to_irq(plat->cd_gpio), carddetect_irq, |
@@ -301,7 +299,6 @@ static int __devinit sdhci_tegra_probe(struct platform_device *pdev) | |||
301 | "failed to allocate wp gpio\n"); | 299 | "failed to allocate wp gpio\n"); |
302 | goto err_wp_req; | 300 | goto err_wp_req; |
303 | } | 301 | } |
304 | tegra_gpio_enable(plat->wp_gpio); | ||
305 | gpio_direction_input(plat->wp_gpio); | 302 | gpio_direction_input(plat->wp_gpio); |
306 | } | 303 | } |
307 | 304 | ||
@@ -329,23 +326,17 @@ err_add_host: | |||
329 | clk_disable(pltfm_host->clk); | 326 | clk_disable(pltfm_host->clk); |
330 | clk_put(pltfm_host->clk); | 327 | clk_put(pltfm_host->clk); |
331 | err_clk_get: | 328 | err_clk_get: |
332 | if (gpio_is_valid(plat->wp_gpio)) { | 329 | if (gpio_is_valid(plat->wp_gpio)) |
333 | tegra_gpio_disable(plat->wp_gpio); | ||
334 | gpio_free(plat->wp_gpio); | 330 | gpio_free(plat->wp_gpio); |
335 | } | ||
336 | err_wp_req: | 331 | err_wp_req: |
337 | if (gpio_is_valid(plat->cd_gpio)) | 332 | if (gpio_is_valid(plat->cd_gpio)) |
338 | free_irq(gpio_to_irq(plat->cd_gpio), host); | 333 | free_irq(gpio_to_irq(plat->cd_gpio), host); |
339 | err_cd_irq_req: | 334 | err_cd_irq_req: |
340 | if (gpio_is_valid(plat->cd_gpio)) { | 335 | if (gpio_is_valid(plat->cd_gpio)) |
341 | tegra_gpio_disable(plat->cd_gpio); | ||
342 | gpio_free(plat->cd_gpio); | 336 | gpio_free(plat->cd_gpio); |
343 | } | ||
344 | err_cd_req: | 337 | err_cd_req: |
345 | if (gpio_is_valid(plat->power_gpio)) { | 338 | if (gpio_is_valid(plat->power_gpio)) |
346 | tegra_gpio_disable(plat->power_gpio); | ||
347 | gpio_free(plat->power_gpio); | 339 | gpio_free(plat->power_gpio); |
348 | } | ||
349 | err_power_req: | 340 | err_power_req: |
350 | err_no_plat: | 341 | err_no_plat: |
351 | sdhci_pltfm_free(pdev); | 342 | sdhci_pltfm_free(pdev); |
@@ -362,21 +353,16 @@ static int __devexit sdhci_tegra_remove(struct platform_device *pdev) | |||
362 | 353 | ||
363 | sdhci_remove_host(host, dead); | 354 | sdhci_remove_host(host, dead); |
364 | 355 | ||
365 | if (gpio_is_valid(plat->wp_gpio)) { | 356 | if (gpio_is_valid(plat->wp_gpio)) |
366 | tegra_gpio_disable(plat->wp_gpio); | ||
367 | gpio_free(plat->wp_gpio); | 357 | gpio_free(plat->wp_gpio); |
368 | } | ||
369 | 358 | ||
370 | if (gpio_is_valid(plat->cd_gpio)) { | 359 | if (gpio_is_valid(plat->cd_gpio)) { |
371 | free_irq(gpio_to_irq(plat->cd_gpio), host); | 360 | free_irq(gpio_to_irq(plat->cd_gpio), host); |
372 | tegra_gpio_disable(plat->cd_gpio); | ||
373 | gpio_free(plat->cd_gpio); | 361 | gpio_free(plat->cd_gpio); |
374 | } | 362 | } |
375 | 363 | ||
376 | if (gpio_is_valid(plat->power_gpio)) { | 364 | if (gpio_is_valid(plat->power_gpio)) |
377 | tegra_gpio_disable(plat->power_gpio); | ||
378 | gpio_free(plat->power_gpio); | 365 | gpio_free(plat->power_gpio); |
379 | } | ||
380 | 366 | ||
381 | clk_disable(pltfm_host->clk); | 367 | clk_disable(pltfm_host->clk); |
382 | clk_put(pltfm_host->clk); | 368 | clk_put(pltfm_host->clk); |
diff --git a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c index 9ec51cec2e14..b68e04310bd8 100644 --- a/drivers/mtd/nand/gpmi-nand/gpmi-nand.c +++ b/drivers/mtd/nand/gpmi-nand/gpmi-nand.c | |||
@@ -24,6 +24,7 @@ | |||
24 | #include <linux/module.h> | 24 | #include <linux/module.h> |
25 | #include <linux/mtd/gpmi-nand.h> | 25 | #include <linux/mtd/gpmi-nand.h> |
26 | #include <linux/mtd/partitions.h> | 26 | #include <linux/mtd/partitions.h> |
27 | #include <linux/pinctrl/consumer.h> | ||
27 | #include "gpmi-nand.h" | 28 | #include "gpmi-nand.h" |
28 | 29 | ||
29 | /* add our owner bbt descriptor */ | 30 | /* add our owner bbt descriptor */ |
@@ -476,6 +477,7 @@ acquire_err: | |||
476 | static int __devinit acquire_resources(struct gpmi_nand_data *this) | 477 | static int __devinit acquire_resources(struct gpmi_nand_data *this) |
477 | { | 478 | { |
478 | struct resources *res = &this->resources; | 479 | struct resources *res = &this->resources; |
480 | struct pinctrl *pinctrl; | ||
479 | int ret; | 481 | int ret; |
480 | 482 | ||
481 | ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME); | 483 | ret = acquire_register_block(this, GPMI_NAND_GPMI_REGS_ADDR_RES_NAME); |
@@ -494,6 +496,12 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this) | |||
494 | if (ret) | 496 | if (ret) |
495 | goto exit_dma_channels; | 497 | goto exit_dma_channels; |
496 | 498 | ||
499 | pinctrl = devm_pinctrl_get_select_default(&this->pdev->dev); | ||
500 | if (IS_ERR(pinctrl)) { | ||
501 | ret = PTR_ERR(pinctrl); | ||
502 | goto exit_pin; | ||
503 | } | ||
504 | |||
497 | res->clock = clk_get(&this->pdev->dev, NULL); | 505 | res->clock = clk_get(&this->pdev->dev, NULL); |
498 | if (IS_ERR(res->clock)) { | 506 | if (IS_ERR(res->clock)) { |
499 | pr_err("can not get the clock\n"); | 507 | pr_err("can not get the clock\n"); |
@@ -503,6 +511,7 @@ static int __devinit acquire_resources(struct gpmi_nand_data *this) | |||
503 | return 0; | 511 | return 0; |
504 | 512 | ||
505 | exit_clock: | 513 | exit_clock: |
514 | exit_pin: | ||
506 | release_dma_channels(this); | 515 | release_dma_channels(this); |
507 | exit_dma_channels: | 516 | exit_dma_channels: |
508 | release_bch_irq(this); | 517 | release_bch_irq(this); |
diff --git a/drivers/net/can/flexcan.c b/drivers/net/can/flexcan.c index 1efb08386c61..38c0690df5c8 100644 --- a/drivers/net/can/flexcan.c +++ b/drivers/net/can/flexcan.c | |||
@@ -35,6 +35,7 @@ | |||
35 | #include <linux/module.h> | 35 | #include <linux/module.h> |
36 | #include <linux/of.h> | 36 | #include <linux/of.h> |
37 | #include <linux/platform_device.h> | 37 | #include <linux/platform_device.h> |
38 | #include <linux/pinctrl/consumer.h> | ||
38 | 39 | ||
39 | #define DRV_NAME "flexcan" | 40 | #define DRV_NAME "flexcan" |
40 | 41 | ||
@@ -927,11 +928,16 @@ static int __devinit flexcan_probe(struct platform_device *pdev) | |||
927 | struct flexcan_priv *priv; | 928 | struct flexcan_priv *priv; |
928 | struct resource *mem; | 929 | struct resource *mem; |
929 | struct clk *clk = NULL; | 930 | struct clk *clk = NULL; |
931 | struct pinctrl *pinctrl; | ||
930 | void __iomem *base; | 932 | void __iomem *base; |
931 | resource_size_t mem_size; | 933 | resource_size_t mem_size; |
932 | int err, irq; | 934 | int err, irq; |
933 | u32 clock_freq = 0; | 935 | u32 clock_freq = 0; |
934 | 936 | ||
937 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
938 | if (IS_ERR(pinctrl)) | ||
939 | return PTR_ERR(pinctrl); | ||
940 | |||
935 | if (pdev->dev.of_node) { | 941 | if (pdev->dev.of_node) { |
936 | const u32 *clock_freq_p; | 942 | const u32 *clock_freq_p; |
937 | 943 | ||
diff --git a/drivers/net/ethernet/freescale/fec.c b/drivers/net/ethernet/freescale/fec.c index 7fa0227c9c02..8f2cf8c09e2d 100644 --- a/drivers/net/ethernet/freescale/fec.c +++ b/drivers/net/ethernet/freescale/fec.c | |||
@@ -48,6 +48,7 @@ | |||
48 | #include <linux/of_device.h> | 48 | #include <linux/of_device.h> |
49 | #include <linux/of_gpio.h> | 49 | #include <linux/of_gpio.h> |
50 | #include <linux/of_net.h> | 50 | #include <linux/of_net.h> |
51 | #include <linux/pinctrl/consumer.h> | ||
51 | 52 | ||
52 | #include <asm/cacheflush.h> | 53 | #include <asm/cacheflush.h> |
53 | 54 | ||
@@ -1543,6 +1544,7 @@ fec_probe(struct platform_device *pdev) | |||
1543 | struct resource *r; | 1544 | struct resource *r; |
1544 | const struct of_device_id *of_id; | 1545 | const struct of_device_id *of_id; |
1545 | static int dev_id; | 1546 | static int dev_id; |
1547 | struct pinctrl *pinctrl; | ||
1546 | 1548 | ||
1547 | of_id = of_match_device(fec_dt_ids, &pdev->dev); | 1549 | of_id = of_match_device(fec_dt_ids, &pdev->dev); |
1548 | if (of_id) | 1550 | if (of_id) |
@@ -1610,6 +1612,12 @@ fec_probe(struct platform_device *pdev) | |||
1610 | } | 1612 | } |
1611 | } | 1613 | } |
1612 | 1614 | ||
1615 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
1616 | if (IS_ERR(pinctrl)) { | ||
1617 | ret = PTR_ERR(pinctrl); | ||
1618 | goto failed_pin; | ||
1619 | } | ||
1620 | |||
1613 | fep->clk = clk_get(&pdev->dev, NULL); | 1621 | fep->clk = clk_get(&pdev->dev, NULL); |
1614 | if (IS_ERR(fep->clk)) { | 1622 | if (IS_ERR(fep->clk)) { |
1615 | ret = PTR_ERR(fep->clk); | 1623 | ret = PTR_ERR(fep->clk); |
@@ -1640,6 +1648,7 @@ failed_mii_init: | |||
1640 | failed_init: | 1648 | failed_init: |
1641 | clk_disable_unprepare(fep->clk); | 1649 | clk_disable_unprepare(fep->clk); |
1642 | clk_put(fep->clk); | 1650 | clk_put(fep->clk); |
1651 | failed_pin: | ||
1643 | failed_clk: | 1652 | failed_clk: |
1644 | for (i = 0; i < FEC_IRQ_NUM; i++) { | 1653 | for (i = 0; i < FEC_IRQ_NUM; i++) { |
1645 | irq = platform_get_irq(pdev, i); | 1654 | irq = platform_get_irq(pdev, i); |
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 91c1f64102f0..c6e6ae0aa3b1 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig | |||
@@ -80,6 +80,16 @@ config PINCTRL_IMX28 | |||
80 | select PINCONF | 80 | select PINCONF |
81 | select PINCTRL_MXS | 81 | select PINCTRL_MXS |
82 | 82 | ||
83 | config PINCTRL_NOMADIK | ||
84 | bool "Nomadik pin controller driver" | ||
85 | depends on ARCH_U8500 || ARCH_NOMADIK | ||
86 | select PINMUX | ||
87 | select PINCONF | ||
88 | |||
89 | config PINCTRL_DB8500 | ||
90 | bool "DB8500 pin controller driver" | ||
91 | depends on PINCTRL_NOMADIK && ARCH_U8500 | ||
92 | |||
83 | config PINCTRL_PXA168 | 93 | config PINCTRL_PXA168 |
84 | bool "PXA168 pin controller driver" | 94 | bool "PXA168 pin controller driver" |
85 | depends on ARCH_MMP | 95 | depends on ARCH_MMP |
@@ -127,6 +137,8 @@ config PINCTRL_COH901 | |||
127 | COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 | 137 | COH 901 335 and COH 901 571/3. They contain 3, 5 or 7 |
128 | ports of 8 GPIO pins each. | 138 | ports of 8 GPIO pins each. |
129 | 139 | ||
140 | source "drivers/pinctrl/spear/Kconfig" | ||
141 | |||
130 | endmenu | 142 | endmenu |
131 | 143 | ||
132 | endif | 144 | endif |
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 515e32ff1597..8c074376cdea 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile | |||
@@ -18,6 +18,8 @@ obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o | |||
18 | obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o | 18 | obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o |
19 | obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o | 19 | obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o |
20 | obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o | 20 | obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o |
21 | obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o | ||
22 | obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o | ||
21 | obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o | 23 | obj-$(CONFIG_PINCTRL_PXA168) += pinctrl-pxa168.o |
22 | obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o | 24 | obj-$(CONFIG_PINCTRL_PXA910) += pinctrl-pxa910.o |
23 | obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o | 25 | obj-$(CONFIG_PINCTRL_SIRF) += pinctrl-sirf.o |
@@ -26,3 +28,5 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o | |||
26 | obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o | 28 | obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o |
27 | obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o | 29 | obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o |
28 | obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o | 30 | obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o |
31 | |||
32 | obj-$(CONFIG_PLAT_SPEAR) += spear/ | ||
diff --git a/drivers/pinctrl/pinctrl-nomadik-db8500.c b/drivers/pinctrl/pinctrl-nomadik-db8500.c new file mode 100644 index 000000000000..8b2022276f71 --- /dev/null +++ b/drivers/pinctrl/pinctrl-nomadik-db8500.c | |||
@@ -0,0 +1,857 @@ | |||
1 | #include <linux/kernel.h> | ||
2 | #include <linux/pinctrl/pinctrl.h> | ||
3 | #include "pinctrl-nomadik.h" | ||
4 | |||
5 | /* All the pins that can be used for GPIO and some other functions */ | ||
6 | #define _GPIO(offset) (offset) | ||
7 | |||
8 | #define DB8500_PIN_AJ5 _GPIO(0) | ||
9 | #define DB8500_PIN_AJ3 _GPIO(1) | ||
10 | #define DB8500_PIN_AH4 _GPIO(2) | ||
11 | #define DB8500_PIN_AH3 _GPIO(3) | ||
12 | #define DB8500_PIN_AH6 _GPIO(4) | ||
13 | #define DB8500_PIN_AG6 _GPIO(5) | ||
14 | #define DB8500_PIN_AF6 _GPIO(6) | ||
15 | #define DB8500_PIN_AG5 _GPIO(7) | ||
16 | #define DB8500_PIN_AD5 _GPIO(8) | ||
17 | #define DB8500_PIN_AE4 _GPIO(9) | ||
18 | #define DB8500_PIN_AF5 _GPIO(10) | ||
19 | #define DB8500_PIN_AG4 _GPIO(11) | ||
20 | #define DB8500_PIN_AC4 _GPIO(12) | ||
21 | #define DB8500_PIN_AF3 _GPIO(13) | ||
22 | #define DB8500_PIN_AE3 _GPIO(14) | ||
23 | #define DB8500_PIN_AC3 _GPIO(15) | ||
24 | #define DB8500_PIN_AD3 _GPIO(16) | ||
25 | #define DB8500_PIN_AD4 _GPIO(17) | ||
26 | #define DB8500_PIN_AC2 _GPIO(18) | ||
27 | #define DB8500_PIN_AC1 _GPIO(19) | ||
28 | #define DB8500_PIN_AB4 _GPIO(20) | ||
29 | #define DB8500_PIN_AB3 _GPIO(21) | ||
30 | #define DB8500_PIN_AA3 _GPIO(22) | ||
31 | #define DB8500_PIN_AA4 _GPIO(23) | ||
32 | #define DB8500_PIN_AB2 _GPIO(24) | ||
33 | #define DB8500_PIN_Y4 _GPIO(25) | ||
34 | #define DB8500_PIN_Y2 _GPIO(26) | ||
35 | #define DB8500_PIN_AA2 _GPIO(27) | ||
36 | #define DB8500_PIN_AA1 _GPIO(28) | ||
37 | #define DB8500_PIN_W2 _GPIO(29) | ||
38 | #define DB8500_PIN_W3 _GPIO(30) | ||
39 | #define DB8500_PIN_V3 _GPIO(31) | ||
40 | #define DB8500_PIN_V2 _GPIO(32) | ||
41 | #define DB8500_PIN_AF2 _GPIO(33) | ||
42 | #define DB8500_PIN_AE1 _GPIO(34) | ||
43 | #define DB8500_PIN_AE2 _GPIO(35) | ||
44 | #define DB8500_PIN_AG2 _GPIO(36) | ||
45 | /* Hole */ | ||
46 | #define DB8500_PIN_F3 _GPIO(64) | ||
47 | #define DB8500_PIN_F1 _GPIO(65) | ||
48 | #define DB8500_PIN_G3 _GPIO(66) | ||
49 | #define DB8500_PIN_G2 _GPIO(67) | ||
50 | #define DB8500_PIN_E1 _GPIO(68) | ||
51 | #define DB8500_PIN_E2 _GPIO(69) | ||
52 | #define DB8500_PIN_G5 _GPIO(70) | ||
53 | #define DB8500_PIN_G4 _GPIO(71) | ||
54 | #define DB8500_PIN_H4 _GPIO(72) | ||
55 | #define DB8500_PIN_H3 _GPIO(73) | ||
56 | #define DB8500_PIN_J3 _GPIO(74) | ||
57 | #define DB8500_PIN_H2 _GPIO(75) | ||
58 | #define DB8500_PIN_J2 _GPIO(76) | ||
59 | #define DB8500_PIN_H1 _GPIO(77) | ||
60 | #define DB8500_PIN_F4 _GPIO(78) | ||
61 | #define DB8500_PIN_E3 _GPIO(79) | ||
62 | #define DB8500_PIN_E4 _GPIO(80) | ||
63 | #define DB8500_PIN_D2 _GPIO(81) | ||
64 | #define DB8500_PIN_C1 _GPIO(82) | ||
65 | #define DB8500_PIN_D3 _GPIO(83) | ||
66 | #define DB8500_PIN_C2 _GPIO(84) | ||
67 | #define DB8500_PIN_D5 _GPIO(85) | ||
68 | #define DB8500_PIN_C6 _GPIO(86) | ||
69 | #define DB8500_PIN_B3 _GPIO(87) | ||
70 | #define DB8500_PIN_C4 _GPIO(88) | ||
71 | #define DB8500_PIN_E6 _GPIO(89) | ||
72 | #define DB8500_PIN_A3 _GPIO(90) | ||
73 | #define DB8500_PIN_B6 _GPIO(91) | ||
74 | #define DB8500_PIN_D6 _GPIO(92) | ||
75 | #define DB8500_PIN_B7 _GPIO(93) | ||
76 | #define DB8500_PIN_D7 _GPIO(94) | ||
77 | #define DB8500_PIN_E8 _GPIO(95) | ||
78 | #define DB8500_PIN_D8 _GPIO(96) | ||
79 | #define DB8500_PIN_D9 _GPIO(97) | ||
80 | /* Hole */ | ||
81 | #define DB8500_PIN_A5 _GPIO(128) | ||
82 | #define DB8500_PIN_B4 _GPIO(129) | ||
83 | #define DB8500_PIN_C8 _GPIO(130) | ||
84 | #define DB8500_PIN_A12 _GPIO(131) | ||
85 | #define DB8500_PIN_C10 _GPIO(132) | ||
86 | #define DB8500_PIN_B10 _GPIO(133) | ||
87 | #define DB8500_PIN_B9 _GPIO(134) | ||
88 | #define DB8500_PIN_A9 _GPIO(135) | ||
89 | #define DB8500_PIN_C7 _GPIO(136) | ||
90 | #define DB8500_PIN_A7 _GPIO(137) | ||
91 | #define DB8500_PIN_C5 _GPIO(138) | ||
92 | #define DB8500_PIN_C9 _GPIO(139) | ||
93 | #define DB8500_PIN_B11 _GPIO(140) | ||
94 | #define DB8500_PIN_C12 _GPIO(141) | ||
95 | #define DB8500_PIN_C11 _GPIO(142) | ||
96 | #define DB8500_PIN_D12 _GPIO(143) | ||
97 | #define DB8500_PIN_B13 _GPIO(144) | ||
98 | #define DB8500_PIN_C13 _GPIO(145) | ||
99 | #define DB8500_PIN_D13 _GPIO(146) | ||
100 | #define DB8500_PIN_C15 _GPIO(147) | ||
101 | #define DB8500_PIN_B16 _GPIO(148) | ||
102 | #define DB8500_PIN_B14 _GPIO(149) | ||
103 | #define DB8500_PIN_C14 _GPIO(150) | ||
104 | #define DB8500_PIN_D17 _GPIO(151) | ||
105 | #define DB8500_PIN_D16 _GPIO(152) | ||
106 | #define DB8500_PIN_B17 _GPIO(153) | ||
107 | #define DB8500_PIN_C16 _GPIO(154) | ||
108 | #define DB8500_PIN_C19 _GPIO(155) | ||
109 | #define DB8500_PIN_C17 _GPIO(156) | ||
110 | #define DB8500_PIN_A18 _GPIO(157) | ||
111 | #define DB8500_PIN_C18 _GPIO(158) | ||
112 | #define DB8500_PIN_B19 _GPIO(159) | ||
113 | #define DB8500_PIN_B20 _GPIO(160) | ||
114 | #define DB8500_PIN_D21 _GPIO(161) | ||
115 | #define DB8500_PIN_D20 _GPIO(162) | ||
116 | #define DB8500_PIN_C20 _GPIO(163) | ||
117 | #define DB8500_PIN_B21 _GPIO(164) | ||
118 | #define DB8500_PIN_C21 _GPIO(165) | ||
119 | #define DB8500_PIN_A22 _GPIO(166) | ||
120 | #define DB8500_PIN_B24 _GPIO(167) | ||
121 | #define DB8500_PIN_C22 _GPIO(168) | ||
122 | #define DB8500_PIN_D22 _GPIO(169) | ||
123 | #define DB8500_PIN_C23 _GPIO(170) | ||
124 | #define DB8500_PIN_D23 _GPIO(171) | ||
125 | /* Hole */ | ||
126 | #define DB8500_PIN_AJ27 _GPIO(192) | ||
127 | #define DB8500_PIN_AH27 _GPIO(193) | ||
128 | #define DB8500_PIN_AF27 _GPIO(194) | ||
129 | #define DB8500_PIN_AG28 _GPIO(195) | ||
130 | #define DB8500_PIN_AG26 _GPIO(196) | ||
131 | #define DB8500_PIN_AH24 _GPIO(197) | ||
132 | #define DB8500_PIN_AG25 _GPIO(198) | ||
133 | #define DB8500_PIN_AH23 _GPIO(199) | ||
134 | #define DB8500_PIN_AH26 _GPIO(200) | ||
135 | #define DB8500_PIN_AF24 _GPIO(201) | ||
136 | #define DB8500_PIN_AF25 _GPIO(202) | ||
137 | #define DB8500_PIN_AE23 _GPIO(203) | ||
138 | #define DB8500_PIN_AF23 _GPIO(204) | ||
139 | #define DB8500_PIN_AG23 _GPIO(205) | ||
140 | #define DB8500_PIN_AG24 _GPIO(206) | ||
141 | #define DB8500_PIN_AJ23 _GPIO(207) | ||
142 | #define DB8500_PIN_AH16 _GPIO(208) | ||
143 | #define DB8500_PIN_AG15 _GPIO(209) | ||
144 | #define DB8500_PIN_AJ15 _GPIO(210) | ||
145 | #define DB8500_PIN_AG14 _GPIO(211) | ||
146 | #define DB8500_PIN_AF13 _GPIO(212) | ||
147 | #define DB8500_PIN_AG13 _GPIO(213) | ||
148 | #define DB8500_PIN_AH15 _GPIO(214) | ||
149 | #define DB8500_PIN_AH13 _GPIO(215) | ||
150 | #define DB8500_PIN_AG12 _GPIO(216) | ||
151 | #define DB8500_PIN_AH12 _GPIO(217) | ||
152 | #define DB8500_PIN_AH11 _GPIO(218) | ||
153 | #define DB8500_PIN_AG10 _GPIO(219) | ||
154 | #define DB8500_PIN_AH10 _GPIO(220) | ||
155 | #define DB8500_PIN_AJ11 _GPIO(221) | ||
156 | #define DB8500_PIN_AJ9 _GPIO(222) | ||
157 | #define DB8500_PIN_AH9 _GPIO(223) | ||
158 | #define DB8500_PIN_AG9 _GPIO(224) | ||
159 | #define DB8500_PIN_AG8 _GPIO(225) | ||
160 | #define DB8500_PIN_AF8 _GPIO(226) | ||
161 | #define DB8500_PIN_AH7 _GPIO(227) | ||
162 | #define DB8500_PIN_AJ6 _GPIO(228) | ||
163 | #define DB8500_PIN_AG7 _GPIO(229) | ||
164 | #define DB8500_PIN_AF7 _GPIO(230) | ||
165 | /* Hole */ | ||
166 | #define DB8500_PIN_AF28 _GPIO(256) | ||
167 | #define DB8500_PIN_AE29 _GPIO(257) | ||
168 | #define DB8500_PIN_AD29 _GPIO(258) | ||
169 | #define DB8500_PIN_AC29 _GPIO(259) | ||
170 | #define DB8500_PIN_AD28 _GPIO(260) | ||
171 | #define DB8500_PIN_AD26 _GPIO(261) | ||
172 | #define DB8500_PIN_AE26 _GPIO(262) | ||
173 | #define DB8500_PIN_AG29 _GPIO(263) | ||
174 | #define DB8500_PIN_AE27 _GPIO(264) | ||
175 | #define DB8500_PIN_AD27 _GPIO(265) | ||
176 | #define DB8500_PIN_AC28 _GPIO(266) | ||
177 | #define DB8500_PIN_AC27 _GPIO(267) | ||
178 | |||
179 | /* | ||
180 | * The names of the pins are denoted by GPIO number and ball name, even | ||
181 | * though they can be used for other things than GPIO, this is the first | ||
182 | * column in the table of the data sheet and often used on schematics and | ||
183 | * such. | ||
184 | */ | ||
185 | static const struct pinctrl_pin_desc nmk_db8500_pins[] = { | ||
186 | PINCTRL_PIN(DB8500_PIN_AJ5, "GPIO0_AJ5"), | ||
187 | PINCTRL_PIN(DB8500_PIN_AJ3, "GPIO1_AJ3"), | ||
188 | PINCTRL_PIN(DB8500_PIN_AH4, "GPIO2_AH4"), | ||
189 | PINCTRL_PIN(DB8500_PIN_AH3, "GPIO3_AH3"), | ||
190 | PINCTRL_PIN(DB8500_PIN_AH6, "GPIO4_AH6"), | ||
191 | PINCTRL_PIN(DB8500_PIN_AG6, "GPIO5_AG6"), | ||
192 | PINCTRL_PIN(DB8500_PIN_AF6, "GPIO6_AF6"), | ||
193 | PINCTRL_PIN(DB8500_PIN_AG5, "GPIO7_AG5"), | ||
194 | PINCTRL_PIN(DB8500_PIN_AD5, "GPIO8_AD5"), | ||
195 | PINCTRL_PIN(DB8500_PIN_AE4, "GPIO9_AE4"), | ||
196 | PINCTRL_PIN(DB8500_PIN_AF5, "GPIO10_AF5"), | ||
197 | PINCTRL_PIN(DB8500_PIN_AG4, "GPIO11_AG4"), | ||
198 | PINCTRL_PIN(DB8500_PIN_AC4, "GPIO12_AC4"), | ||
199 | PINCTRL_PIN(DB8500_PIN_AF3, "GPIO13_AF3"), | ||
200 | PINCTRL_PIN(DB8500_PIN_AE3, "GPIO14_AE3"), | ||
201 | PINCTRL_PIN(DB8500_PIN_AC3, "GPIO15_AC3"), | ||
202 | PINCTRL_PIN(DB8500_PIN_AD3, "GPIO16_AD3"), | ||
203 | PINCTRL_PIN(DB8500_PIN_AD4, "GPIO17_AD4"), | ||
204 | PINCTRL_PIN(DB8500_PIN_AC2, "GPIO18_AC2"), | ||
205 | PINCTRL_PIN(DB8500_PIN_AC1, "GPIO19_AC1"), | ||
206 | PINCTRL_PIN(DB8500_PIN_AB4, "GPIO20_AB4"), | ||
207 | PINCTRL_PIN(DB8500_PIN_AB3, "GPIO21_AB3"), | ||
208 | PINCTRL_PIN(DB8500_PIN_AA3, "GPIO22_AA3"), | ||
209 | PINCTRL_PIN(DB8500_PIN_AA4, "GPIO23_AA4"), | ||
210 | PINCTRL_PIN(DB8500_PIN_AB2, "GPIO24_AB2"), | ||
211 | PINCTRL_PIN(DB8500_PIN_Y4, "GPIO25_Y4"), | ||
212 | PINCTRL_PIN(DB8500_PIN_Y2, "GPIO26_Y2"), | ||
213 | PINCTRL_PIN(DB8500_PIN_AA2, "GPIO27_AA2"), | ||
214 | PINCTRL_PIN(DB8500_PIN_AA1, "GPIO28_AA1"), | ||
215 | PINCTRL_PIN(DB8500_PIN_W2, "GPIO29_W2"), | ||
216 | PINCTRL_PIN(DB8500_PIN_W3, "GPIO30_W3"), | ||
217 | PINCTRL_PIN(DB8500_PIN_V3, "GPIO31_V3"), | ||
218 | PINCTRL_PIN(DB8500_PIN_V2, "GPIO32_V2"), | ||
219 | PINCTRL_PIN(DB8500_PIN_AF2, "GPIO33_AF2"), | ||
220 | PINCTRL_PIN(DB8500_PIN_AE1, "GPIO34_AE1"), | ||
221 | PINCTRL_PIN(DB8500_PIN_AE2, "GPIO35_AE2"), | ||
222 | PINCTRL_PIN(DB8500_PIN_AG2, "GPIO36_AG2"), | ||
223 | /* Hole */ | ||
224 | PINCTRL_PIN(DB8500_PIN_F3, "GPIO64_F3"), | ||
225 | PINCTRL_PIN(DB8500_PIN_F1, "GPIO65_F1"), | ||
226 | PINCTRL_PIN(DB8500_PIN_G3, "GPIO66_G3"), | ||
227 | PINCTRL_PIN(DB8500_PIN_G2, "GPIO67_G2"), | ||
228 | PINCTRL_PIN(DB8500_PIN_E1, "GPIO68_E1"), | ||
229 | PINCTRL_PIN(DB8500_PIN_E2, "GPIO69_E2"), | ||
230 | PINCTRL_PIN(DB8500_PIN_G5, "GPIO70_G5"), | ||
231 | PINCTRL_PIN(DB8500_PIN_G4, "GPIO71_G4"), | ||
232 | PINCTRL_PIN(DB8500_PIN_H4, "GPIO72_H4"), | ||
233 | PINCTRL_PIN(DB8500_PIN_H3, "GPIO73_H3"), | ||
234 | PINCTRL_PIN(DB8500_PIN_J3, "GPIO74_J3"), | ||
235 | PINCTRL_PIN(DB8500_PIN_H2, "GPIO75_H2"), | ||
236 | PINCTRL_PIN(DB8500_PIN_J2, "GPIO76_J2"), | ||
237 | PINCTRL_PIN(DB8500_PIN_H1, "GPIO77_H1"), | ||
238 | PINCTRL_PIN(DB8500_PIN_F4, "GPIO78_F4"), | ||
239 | PINCTRL_PIN(DB8500_PIN_E3, "GPIO79_E3"), | ||
240 | PINCTRL_PIN(DB8500_PIN_E4, "GPIO80_E4"), | ||
241 | PINCTRL_PIN(DB8500_PIN_D2, "GPIO81_D2"), | ||
242 | PINCTRL_PIN(DB8500_PIN_C1, "GPIO82_C1"), | ||
243 | PINCTRL_PIN(DB8500_PIN_D3, "GPIO83_D3"), | ||
244 | PINCTRL_PIN(DB8500_PIN_C2, "GPIO84_C2"), | ||
245 | PINCTRL_PIN(DB8500_PIN_D5, "GPIO85_D5"), | ||
246 | PINCTRL_PIN(DB8500_PIN_C6, "GPIO86_C6"), | ||
247 | PINCTRL_PIN(DB8500_PIN_B3, "GPIO87_B3"), | ||
248 | PINCTRL_PIN(DB8500_PIN_C4, "GPIO88_C4"), | ||
249 | PINCTRL_PIN(DB8500_PIN_E6, "GPIO89_E6"), | ||
250 | PINCTRL_PIN(DB8500_PIN_A3, "GPIO90_A3"), | ||
251 | PINCTRL_PIN(DB8500_PIN_B6, "GPIO91_B6"), | ||
252 | PINCTRL_PIN(DB8500_PIN_D6, "GPIO92_D6"), | ||
253 | PINCTRL_PIN(DB8500_PIN_B7, "GPIO93_B7"), | ||
254 | PINCTRL_PIN(DB8500_PIN_D7, "GPIO94_D7"), | ||
255 | PINCTRL_PIN(DB8500_PIN_E8, "GPIO95_E8"), | ||
256 | PINCTRL_PIN(DB8500_PIN_D8, "GPIO96_D8"), | ||
257 | PINCTRL_PIN(DB8500_PIN_D9, "GPIO97_D9"), | ||
258 | /* Hole */ | ||
259 | PINCTRL_PIN(DB8500_PIN_A5, "GPIO128_A5"), | ||
260 | PINCTRL_PIN(DB8500_PIN_B4, "GPIO129_B4"), | ||
261 | PINCTRL_PIN(DB8500_PIN_C8, "GPIO130_C8"), | ||
262 | PINCTRL_PIN(DB8500_PIN_A12, "GPIO131_A12"), | ||
263 | PINCTRL_PIN(DB8500_PIN_C10, "GPIO132_C10"), | ||
264 | PINCTRL_PIN(DB8500_PIN_B10, "GPIO133_B10"), | ||
265 | PINCTRL_PIN(DB8500_PIN_B9, "GPIO134_B9"), | ||
266 | PINCTRL_PIN(DB8500_PIN_A9, "GPIO135_A9"), | ||
267 | PINCTRL_PIN(DB8500_PIN_C7, "GPIO136_C7"), | ||
268 | PINCTRL_PIN(DB8500_PIN_A7, "GPIO137_A7"), | ||
269 | PINCTRL_PIN(DB8500_PIN_C5, "GPIO138_C5"), | ||
270 | PINCTRL_PIN(DB8500_PIN_C9, "GPIO139_C9"), | ||
271 | PINCTRL_PIN(DB8500_PIN_B11, "GPIO140_B11"), | ||
272 | PINCTRL_PIN(DB8500_PIN_C12, "GPIO141_C12"), | ||
273 | PINCTRL_PIN(DB8500_PIN_C11, "GPIO142_C11"), | ||
274 | PINCTRL_PIN(DB8500_PIN_D12, "GPIO143_D12"), | ||
275 | PINCTRL_PIN(DB8500_PIN_B13, "GPIO144_B13"), | ||
276 | PINCTRL_PIN(DB8500_PIN_C13, "GPIO145_C13"), | ||
277 | PINCTRL_PIN(DB8500_PIN_D13, "GPIO146_D13"), | ||
278 | PINCTRL_PIN(DB8500_PIN_C15, "GPIO147_C15"), | ||
279 | PINCTRL_PIN(DB8500_PIN_B16, "GPIO148_B16"), | ||
280 | PINCTRL_PIN(DB8500_PIN_B14, "GPIO149_B14"), | ||
281 | PINCTRL_PIN(DB8500_PIN_C14, "GPIO150_C14"), | ||
282 | PINCTRL_PIN(DB8500_PIN_D17, "GPIO151_D17"), | ||
283 | PINCTRL_PIN(DB8500_PIN_D16, "GPIO152_D16"), | ||
284 | PINCTRL_PIN(DB8500_PIN_B17, "GPIO153_B17"), | ||
285 | PINCTRL_PIN(DB8500_PIN_C16, "GPIO154_C16"), | ||
286 | PINCTRL_PIN(DB8500_PIN_C19, "GPIO155_C19"), | ||
287 | PINCTRL_PIN(DB8500_PIN_C17, "GPIO156_C17"), | ||
288 | PINCTRL_PIN(DB8500_PIN_A18, "GPIO157_A18"), | ||
289 | PINCTRL_PIN(DB8500_PIN_C18, "GPIO158_C18"), | ||
290 | PINCTRL_PIN(DB8500_PIN_B19, "GPIO159_B19"), | ||
291 | PINCTRL_PIN(DB8500_PIN_B20, "GPIO160_B20"), | ||
292 | PINCTRL_PIN(DB8500_PIN_D21, "GPIO161_D21"), | ||
293 | PINCTRL_PIN(DB8500_PIN_D20, "GPIO162_D20"), | ||
294 | PINCTRL_PIN(DB8500_PIN_C20, "GPIO163_C20"), | ||
295 | PINCTRL_PIN(DB8500_PIN_B21, "GPIO164_B21"), | ||
296 | PINCTRL_PIN(DB8500_PIN_C21, "GPIO165_C21"), | ||
297 | PINCTRL_PIN(DB8500_PIN_A22, "GPIO166_A22"), | ||
298 | PINCTRL_PIN(DB8500_PIN_B24, "GPIO167_B24"), | ||
299 | PINCTRL_PIN(DB8500_PIN_C22, "GPIO168_C22"), | ||
300 | PINCTRL_PIN(DB8500_PIN_D22, "GPIO169_D22"), | ||
301 | PINCTRL_PIN(DB8500_PIN_C23, "GPIO170_C23"), | ||
302 | PINCTRL_PIN(DB8500_PIN_D23, "GPIO171_D23"), | ||
303 | /* Hole */ | ||
304 | PINCTRL_PIN(DB8500_PIN_AJ27, "GPIO192_AJ27"), | ||
305 | PINCTRL_PIN(DB8500_PIN_AH27, "GPIO193_AH27"), | ||
306 | PINCTRL_PIN(DB8500_PIN_AF27, "GPIO194_AF27"), | ||
307 | PINCTRL_PIN(DB8500_PIN_AG28, "GPIO195_AG28"), | ||
308 | PINCTRL_PIN(DB8500_PIN_AG26, "GPIO196_AG26"), | ||
309 | PINCTRL_PIN(DB8500_PIN_AH24, "GPIO197_AH24"), | ||
310 | PINCTRL_PIN(DB8500_PIN_AG25, "GPIO198_AG25"), | ||
311 | PINCTRL_PIN(DB8500_PIN_AH23, "GPIO199_AH23"), | ||
312 | PINCTRL_PIN(DB8500_PIN_AH26, "GPIO200_AH26"), | ||
313 | PINCTRL_PIN(DB8500_PIN_AF24, "GPIO201_AF24"), | ||
314 | PINCTRL_PIN(DB8500_PIN_AF25, "GPIO202_AF25"), | ||
315 | PINCTRL_PIN(DB8500_PIN_AE23, "GPIO203_AE23"), | ||
316 | PINCTRL_PIN(DB8500_PIN_AF23, "GPIO204_AF23"), | ||
317 | PINCTRL_PIN(DB8500_PIN_AG23, "GPIO205_AG23"), | ||
318 | PINCTRL_PIN(DB8500_PIN_AG24, "GPIO206_AG24"), | ||
319 | PINCTRL_PIN(DB8500_PIN_AJ23, "GPIO207_AJ23"), | ||
320 | PINCTRL_PIN(DB8500_PIN_AH16, "GPIO208_AH16"), | ||
321 | PINCTRL_PIN(DB8500_PIN_AG15, "GPIO209_AG15"), | ||
322 | PINCTRL_PIN(DB8500_PIN_AJ15, "GPIO210_AJ15"), | ||
323 | PINCTRL_PIN(DB8500_PIN_AG14, "GPIO211_AG14"), | ||
324 | PINCTRL_PIN(DB8500_PIN_AF13, "GPIO212_AF13"), | ||
325 | PINCTRL_PIN(DB8500_PIN_AG13, "GPIO213_AG13"), | ||
326 | PINCTRL_PIN(DB8500_PIN_AH15, "GPIO214_AH15"), | ||
327 | PINCTRL_PIN(DB8500_PIN_AH13, "GPIO215_AH13"), | ||
328 | PINCTRL_PIN(DB8500_PIN_AG12, "GPIO216_AG12"), | ||
329 | PINCTRL_PIN(DB8500_PIN_AH12, "GPIO217_AH12"), | ||
330 | PINCTRL_PIN(DB8500_PIN_AH11, "GPIO218_AH11"), | ||
331 | PINCTRL_PIN(DB8500_PIN_AG10, "GPIO219_AG10"), | ||
332 | PINCTRL_PIN(DB8500_PIN_AH10, "GPIO220_AH10"), | ||
333 | PINCTRL_PIN(DB8500_PIN_AJ11, "GPIO221_AJ11"), | ||
334 | PINCTRL_PIN(DB8500_PIN_AJ9, "GPIO222_AJ9"), | ||
335 | PINCTRL_PIN(DB8500_PIN_AH9, "GPIO223_AH9"), | ||
336 | PINCTRL_PIN(DB8500_PIN_AG9, "GPIO224_AG9"), | ||
337 | PINCTRL_PIN(DB8500_PIN_AG8, "GPIO225_AG8"), | ||
338 | PINCTRL_PIN(DB8500_PIN_AF8, "GPIO226_AF8"), | ||
339 | PINCTRL_PIN(DB8500_PIN_AH7, "GPIO227_AH7"), | ||
340 | PINCTRL_PIN(DB8500_PIN_AJ6, "GPIO228_AJ6"), | ||
341 | PINCTRL_PIN(DB8500_PIN_AG7, "GPIO229_AG7"), | ||
342 | PINCTRL_PIN(DB8500_PIN_AF7, "GPIO230_AF7"), | ||
343 | /* Hole */ | ||
344 | PINCTRL_PIN(DB8500_PIN_AF28, "GPIO256_AF28"), | ||
345 | PINCTRL_PIN(DB8500_PIN_AE29, "GPIO257_AE29"), | ||
346 | PINCTRL_PIN(DB8500_PIN_AD29, "GPIO258_AD29"), | ||
347 | PINCTRL_PIN(DB8500_PIN_AC29, "GPIO259_AC29"), | ||
348 | PINCTRL_PIN(DB8500_PIN_AD28, "GPIO260_AD28"), | ||
349 | PINCTRL_PIN(DB8500_PIN_AD26, "GPIO261_AD26"), | ||
350 | PINCTRL_PIN(DB8500_PIN_AE26, "GPIO262_AE26"), | ||
351 | PINCTRL_PIN(DB8500_PIN_AG29, "GPIO263_AG29"), | ||
352 | PINCTRL_PIN(DB8500_PIN_AE27, "GPIO264_AE27"), | ||
353 | PINCTRL_PIN(DB8500_PIN_AD27, "GPIO265_AD27"), | ||
354 | PINCTRL_PIN(DB8500_PIN_AC28, "GPIO266_AC28"), | ||
355 | PINCTRL_PIN(DB8500_PIN_AC27, "GPIO267_AC27"), | ||
356 | }; | ||
357 | |||
358 | #define DB8500_GPIO_RANGE(a, b, c) { .name = "DB8500", .id = a, .base = b, \ | ||
359 | .pin_base = b, .npins = c } | ||
360 | |||
361 | /* | ||
362 | * This matches the 32-pin gpio chips registered by the GPIO portion. This | ||
363 | * cannot be const since we assign the struct gpio_chip * pointer at runtime. | ||
364 | */ | ||
365 | static struct pinctrl_gpio_range nmk_db8500_ranges[] = { | ||
366 | DB8500_GPIO_RANGE(0, 0, 32), | ||
367 | DB8500_GPIO_RANGE(1, 32, 5), | ||
368 | DB8500_GPIO_RANGE(2, 64, 32), | ||
369 | DB8500_GPIO_RANGE(3, 96, 2), | ||
370 | DB8500_GPIO_RANGE(4, 128, 32), | ||
371 | DB8500_GPIO_RANGE(5, 160, 12), | ||
372 | DB8500_GPIO_RANGE(6, 192, 32), | ||
373 | DB8500_GPIO_RANGE(7, 224, 7), | ||
374 | DB8500_GPIO_RANGE(8, 256, 12), | ||
375 | }; | ||
376 | |||
377 | /* | ||
378 | * Read the pin group names like this: | ||
379 | * u0_a_1 = first groups of pins for uart0 on alt function a | ||
380 | * i2c2_b_2 = second group of pins for i2c2 on alt function b | ||
381 | * | ||
382 | * The groups are arranged as sets per altfunction column, so we can | ||
383 | * mux in one group at a time by selecting the same altfunction for them | ||
384 | * all. When functions require pins on different altfunctions, you need | ||
385 | * to combine several groups. | ||
386 | */ | ||
387 | |||
388 | /* Altfunction A column */ | ||
389 | static const unsigned u0_a_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, | ||
390 | DB8500_PIN_AH4, DB8500_PIN_AH3 }; | ||
391 | static const unsigned u1rxtx_a_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; | ||
392 | static const unsigned u1ctsrts_a_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; | ||
393 | /* Image processor I2C line, this is driven by image processor firmware */ | ||
394 | static const unsigned ipi2c_a_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; | ||
395 | static const unsigned ipi2c_a_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; | ||
396 | /* MSP0 can only be on these pins, but TXD and RXD can be flipped */ | ||
397 | static const unsigned msp0txrx_a_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; | ||
398 | static const unsigned msp0tfstck_a_1_pins[] = { DB8500_PIN_AF3, DB8500_PIN_AE3 }; | ||
399 | static const unsigned msp0rfsrck_a_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; | ||
400 | /* Basic pins of the MMC/SD card 0 interface */ | ||
401 | static const unsigned mc0_a_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, | ||
402 | DB8500_PIN_AB4, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, | ||
403 | DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; | ||
404 | /* Often only 4 bits are used, then these are not needed (only used for MMC) */ | ||
405 | static const unsigned mc0_dat47_a_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, | ||
406 | DB8500_PIN_V3, DB8500_PIN_V2}; | ||
407 | static const unsigned mc0dat31dir_a_1_pins[] = { DB8500_PIN_AB3 }; | ||
408 | /* MSP1 can only be on these pins, but TXD and RXD can be flipped */ | ||
409 | static const unsigned msp1txrx_a_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; | ||
410 | static const unsigned msp1_a_1_pins[] = { DB8500_PIN_AE1, DB8500_PIN_AE2 }; | ||
411 | /* LCD interface */ | ||
412 | static const unsigned lcdb_a_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, | ||
413 | DB8500_PIN_G3, DB8500_PIN_G2 }; | ||
414 | static const unsigned lcdvsi0_a_1_pins[] = { DB8500_PIN_E1 }; | ||
415 | static const unsigned lcdvsi1_a_1_pins[] = { DB8500_PIN_E2 }; | ||
416 | static const unsigned lcd_d0_d7_a_1_pins[] = { | ||
417 | DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, | ||
418 | DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1 }; | ||
419 | /* D8 thru D11 often used as TVOUT lines */ | ||
420 | static const unsigned lcd_d8_d11_a_1_pins[] = { DB8500_PIN_F4, | ||
421 | DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2 }; | ||
422 | static const unsigned lcd_d12_d23_a_1_pins[] = { | ||
423 | DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5, | ||
424 | DB8500_PIN_C6, DB8500_PIN_B3, DB8500_PIN_C4, DB8500_PIN_E6, | ||
425 | DB8500_PIN_A3, DB8500_PIN_B6, DB8500_PIN_D6, DB8500_PIN_B7 }; | ||
426 | static const unsigned kp_a_1_pins[] = { DB8500_PIN_D7, DB8500_PIN_E8, | ||
427 | DB8500_PIN_D8, DB8500_PIN_D9 }; | ||
428 | static const unsigned kpskaskb_a_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16 }; | ||
429 | static const unsigned kp_a_2_pins[] = { | ||
430 | DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, | ||
431 | DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, | ||
432 | DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, | ||
433 | DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; | ||
434 | /* MC2 has 8 data lines and no direction control, so only for (e)MMC */ | ||
435 | static const unsigned mc2_a_1_pins[] = { DB8500_PIN_A5, DB8500_PIN_B4, | ||
436 | DB8500_PIN_C8, DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, | ||
437 | DB8500_PIN_B9, DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, | ||
438 | DB8500_PIN_C5 }; | ||
439 | static const unsigned ssp1_a_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, | ||
440 | DB8500_PIN_C12, DB8500_PIN_C11 }; | ||
441 | static const unsigned ssp0_a_1_pins[] = { DB8500_PIN_D12, DB8500_PIN_B13, | ||
442 | DB8500_PIN_C13, DB8500_PIN_D13 }; | ||
443 | static const unsigned i2c0_a_1_pins[] = { DB8500_PIN_C15, DB8500_PIN_B16 }; | ||
444 | /* | ||
445 | * Image processor GPIO pins are named "ipgpio" and have their own | ||
446 | * numberspace | ||
447 | */ | ||
448 | static const unsigned ipgpio0_a_1_pins[] = { DB8500_PIN_B14 }; | ||
449 | static const unsigned ipgpio1_a_1_pins[] = { DB8500_PIN_C14 }; | ||
450 | /* Three modem pins named RF_PURn, MODEM_STATE and MODEM_PWREN */ | ||
451 | static const unsigned modem_a_1_pins[] = { DB8500_PIN_D22, DB8500_PIN_C23, | ||
452 | DB8500_PIN_D23 }; | ||
453 | /* | ||
454 | * This MSP cannot switch RX and TX, SCK in a separate group since this | ||
455 | * seems to be optional. | ||
456 | */ | ||
457 | static const unsigned msp2sck_a_1_pins[] = { DB8500_PIN_AJ27 }; | ||
458 | static const unsigned msp2_a_1_pins[] = { DB8500_PIN_AH27, DB8500_PIN_AF27, | ||
459 | DB8500_PIN_AG28, DB8500_PIN_AG26 }; | ||
460 | static const unsigned mc4_a_1_pins[] = { DB8500_PIN_AH24, DB8500_PIN_AG25, | ||
461 | DB8500_PIN_AH23, DB8500_PIN_AH26, DB8500_PIN_AF24, DB8500_PIN_AF25, | ||
462 | DB8500_PIN_AE23, DB8500_PIN_AF23, DB8500_PIN_AG23, DB8500_PIN_AG24, | ||
463 | DB8500_PIN_AJ23 }; | ||
464 | /* MC1 has only 4 data pins, designed for SD or SDIO exclusively */ | ||
465 | static const unsigned mc1_a_1_pins[] = { DB8500_PIN_AH16, DB8500_PIN_AG15, | ||
466 | DB8500_PIN_AJ15, DB8500_PIN_AG14, DB8500_PIN_AF13, DB8500_PIN_AG13, | ||
467 | DB8500_PIN_AH15 }; | ||
468 | static const unsigned mc1dir_a_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, | ||
469 | DB8500_PIN_AH12, DB8500_PIN_AH11 }; | ||
470 | static const unsigned hsir_a_1_pins[] = { DB8500_PIN_AG10, DB8500_PIN_AH10 }; | ||
471 | static const unsigned hsit_a_1_pins[] = { DB8500_PIN_AJ11, DB8500_PIN_AJ9, | ||
472 | DB8500_PIN_AH9, DB8500_PIN_AG9, DB8500_PIN_AG8, DB8500_PIN_AF8 }; | ||
473 | static const unsigned clkout_a_1_pins[] = { DB8500_PIN_AH7, DB8500_PIN_AJ6 }; | ||
474 | static const unsigned clkout_a_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; | ||
475 | static const unsigned usb_a_1_pins[] = { DB8500_PIN_AF28, DB8500_PIN_AE29, | ||
476 | DB8500_PIN_AD29, DB8500_PIN_AC29, DB8500_PIN_AD28, DB8500_PIN_AD26, | ||
477 | DB8500_PIN_AE26, DB8500_PIN_AG29, DB8500_PIN_AE27, DB8500_PIN_AD27, | ||
478 | DB8500_PIN_AC28, DB8500_PIN_AC27 }; | ||
479 | |||
480 | /* Altfunction B column */ | ||
481 | static const unsigned trig_b_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3 }; | ||
482 | static const unsigned i2c4_b_1_pins[] = { DB8500_PIN_AH6, DB8500_PIN_AG6 }; | ||
483 | static const unsigned i2c1_b_1_pins[] = { DB8500_PIN_AF6, DB8500_PIN_AG5 }; | ||
484 | static const unsigned i2c2_b_1_pins[] = { DB8500_PIN_AD5, DB8500_PIN_AE4 }; | ||
485 | static const unsigned i2c2_b_2_pins[] = { DB8500_PIN_AF5, DB8500_PIN_AG4 }; | ||
486 | static const unsigned msp0txrx_b_1_pins[] = { DB8500_PIN_AC4, DB8500_PIN_AC3 }; | ||
487 | static const unsigned i2c1_b_2_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; | ||
488 | /* Just RX and TX for UART2 */ | ||
489 | static const unsigned u2rxtx_b_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1 }; | ||
490 | static const unsigned uartmodtx_b_1_pins[] = { DB8500_PIN_AB4 }; | ||
491 | static const unsigned msp0sck_b_1_pins[] = { DB8500_PIN_AB3 }; | ||
492 | static const unsigned uartmodrx_b_1_pins[] = { DB8500_PIN_AA3 }; | ||
493 | static const unsigned stmmod_b_1_pins[] = { DB8500_PIN_AA4, DB8500_PIN_Y4, | ||
494 | DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; | ||
495 | static const unsigned uartmodrx_b_2_pins[] = { DB8500_PIN_AB2 }; | ||
496 | static const unsigned spi3_b_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3, | ||
497 | DB8500_PIN_V3, DB8500_PIN_V2 }; | ||
498 | static const unsigned msp1txrx_b_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AG2 }; | ||
499 | static const unsigned kp_b_1_pins[] = { DB8500_PIN_F3, DB8500_PIN_F1, | ||
500 | DB8500_PIN_G3, DB8500_PIN_G2, DB8500_PIN_E1, DB8500_PIN_E2, | ||
501 | DB8500_PIN_G5, DB8500_PIN_G4, DB8500_PIN_H4, DB8500_PIN_H3, | ||
502 | DB8500_PIN_J3, DB8500_PIN_H2, DB8500_PIN_J2, DB8500_PIN_H1, | ||
503 | DB8500_PIN_F4, DB8500_PIN_E3, DB8500_PIN_E4, DB8500_PIN_D2, | ||
504 | DB8500_PIN_C1, DB8500_PIN_D3, DB8500_PIN_C2, DB8500_PIN_D5 }; | ||
505 | static const unsigned sm_b_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, | ||
506 | DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, | ||
507 | DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, | ||
508 | DB8500_PIN_D9, DB8500_PIN_A5, DB8500_PIN_B4, DB8500_PIN_C8, | ||
509 | DB8500_PIN_A12, DB8500_PIN_C10, DB8500_PIN_B10, DB8500_PIN_B9, | ||
510 | DB8500_PIN_A9, DB8500_PIN_C7, DB8500_PIN_A7, DB8500_PIN_C5, | ||
511 | DB8500_PIN_C9, DB8500_PIN_B14 }; | ||
512 | /* This chip select pin can be "ps0" in alt B so have it separately */ | ||
513 | static const unsigned smcs0_b_1_pins[] = { DB8500_PIN_E8 }; | ||
514 | static const unsigned ipgpio7_b_1_pins[] = { DB8500_PIN_B11 }; | ||
515 | static const unsigned ipgpio2_b_1_pins[] = { DB8500_PIN_C12 }; | ||
516 | static const unsigned ipgpio3_b_1_pins[] = { DB8500_PIN_C11 }; | ||
517 | static const unsigned lcdaclk_b_1_pins[] = { DB8500_PIN_C14 }; | ||
518 | static const unsigned lcda_b_1_pins[] = { DB8500_PIN_D22, | ||
519 | DB8500_PIN_C23, DB8500_PIN_D23 }; | ||
520 | static const unsigned lcd_b_1_pins[] = { DB8500_PIN_D17, DB8500_PIN_D16, | ||
521 | DB8500_PIN_B17, DB8500_PIN_C16, DB8500_PIN_C19, DB8500_PIN_C17, | ||
522 | DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19, DB8500_PIN_B20, | ||
523 | DB8500_PIN_D21, DB8500_PIN_D20, DB8500_PIN_C20, DB8500_PIN_B21, | ||
524 | DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24, DB8500_PIN_C22 }; | ||
525 | static const unsigned ddrtrig_b_1_pins[] = { DB8500_PIN_AJ27 }; | ||
526 | static const unsigned pwl_b_1_pins[] = { DB8500_PIN_AF25 }; | ||
527 | static const unsigned spi1_b_1_pins[] = { DB8500_PIN_AG15, DB8500_PIN_AF13, | ||
528 | DB8500_PIN_AG13, DB8500_PIN_AH15 }; | ||
529 | static const unsigned mc3_b_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, | ||
530 | DB8500_PIN_AH12, DB8500_PIN_AH11, DB8500_PIN_AG10, DB8500_PIN_AH10, | ||
531 | DB8500_PIN_AJ11, DB8500_PIN_AJ9, DB8500_PIN_AH9, DB8500_PIN_AG9, | ||
532 | DB8500_PIN_AG8 }; | ||
533 | static const unsigned pwl_b_2_pins[] = { DB8500_PIN_AF8 }; | ||
534 | static const unsigned pwl_b_3_pins[] = { DB8500_PIN_AG7 }; | ||
535 | static const unsigned pwl_b_4_pins[] = { DB8500_PIN_AF7 }; | ||
536 | |||
537 | /* Altfunction C column */ | ||
538 | static const unsigned ipjtag_c_1_pins[] = { DB8500_PIN_AJ5, DB8500_PIN_AJ3, | ||
539 | DB8500_PIN_AH4, DB8500_PIN_AH3, DB8500_PIN_AH6 }; | ||
540 | static const unsigned ipgpio6_c_1_pins[] = { DB8500_PIN_AG6 }; | ||
541 | static const unsigned ipgpio0_c_1_pins[] = { DB8500_PIN_AF6 }; | ||
542 | static const unsigned ipgpio1_c_1_pins[] = { DB8500_PIN_AG5 }; | ||
543 | static const unsigned ipgpio3_c_1_pins[] = { DB8500_PIN_AF5 }; | ||
544 | static const unsigned ipgpio2_c_1_pins[] = { DB8500_PIN_AG4 }; | ||
545 | static const unsigned slim0_c_1_pins[] = { DB8500_PIN_AD3, DB8500_PIN_AD4 }; | ||
546 | /* Optional 4-bit Memory Stick interface */ | ||
547 | static const unsigned ms_c_1_pins[] = { DB8500_PIN_AC2, DB8500_PIN_AC1, | ||
548 | DB8500_PIN_AB3, DB8500_PIN_AA3, DB8500_PIN_AA4, DB8500_PIN_AB2, | ||
549 | DB8500_PIN_Y4, DB8500_PIN_Y2, DB8500_PIN_AA2, DB8500_PIN_AA1 }; | ||
550 | static const unsigned iptrigout_c_1_pins[] = { DB8500_PIN_AB4 }; | ||
551 | static const unsigned u2rxtx_c_1_pins[] = { DB8500_PIN_W2, DB8500_PIN_W3 }; | ||
552 | static const unsigned u2ctsrts_c_1_pins[] = { DB8500_PIN_V3, DB8500_PIN_V2 }; | ||
553 | static const unsigned u0_c_1_pins[] = { DB8500_PIN_AF2, DB8500_PIN_AE1, | ||
554 | DB8500_PIN_AE2, DB8500_PIN_AG2 }; | ||
555 | static const unsigned ipgpio4_c_1_pins[] = { DB8500_PIN_F3 }; | ||
556 | static const unsigned ipgpio5_c_1_pins[] = { DB8500_PIN_F1 }; | ||
557 | static const unsigned ipgpio6_c_2_pins[] = { DB8500_PIN_G3 }; | ||
558 | static const unsigned ipgpio7_c_1_pins[] = { DB8500_PIN_G2 }; | ||
559 | static const unsigned smcleale_c_1_pins[] = { DB8500_PIN_E1, DB8500_PIN_E2 }; | ||
560 | static const unsigned stmape_c_1_pins[] = { DB8500_PIN_G5, DB8500_PIN_G4, | ||
561 | DB8500_PIN_H4, DB8500_PIN_H3, DB8500_PIN_J3 }; | ||
562 | static const unsigned u2rxtx_c_2_pins[] = { DB8500_PIN_H2, DB8500_PIN_J2 }; | ||
563 | static const unsigned ipgpio2_c_2_pins[] = { DB8500_PIN_F4 }; | ||
564 | static const unsigned ipgpio3_c_2_pins[] = { DB8500_PIN_E3 }; | ||
565 | static const unsigned ipgpio4_c_2_pins[] = { DB8500_PIN_E4 }; | ||
566 | static const unsigned ipgpio5_c_2_pins[] = { DB8500_PIN_D2 }; | ||
567 | static const unsigned mc5_c_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, | ||
568 | DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, | ||
569 | DB8500_PIN_D6, DB8500_PIN_B7, DB8500_PIN_D7, DB8500_PIN_D8, | ||
570 | DB8500_PIN_D9 }; | ||
571 | static const unsigned mc2rstn_c_1_pins[] = { DB8500_PIN_C8 }; | ||
572 | static const unsigned kp_c_1_pins[] = { DB8500_PIN_C9, DB8500_PIN_B11, | ||
573 | DB8500_PIN_C12, DB8500_PIN_C11, DB8500_PIN_D17, DB8500_PIN_D16, | ||
574 | DB8500_PIN_C23, DB8500_PIN_D23 }; | ||
575 | static const unsigned smps1_c_1_pins[] = { DB8500_PIN_B14 }; | ||
576 | static const unsigned u2rxtx_c_3_pins[] = { DB8500_PIN_B17, DB8500_PIN_C16 }; | ||
577 | static const unsigned stmape_c_2_pins[] = { DB8500_PIN_C19, DB8500_PIN_C17, | ||
578 | DB8500_PIN_A18, DB8500_PIN_C18, DB8500_PIN_B19 }; | ||
579 | static const unsigned uartmodrx_c_1_pins[] = { DB8500_PIN_D21 }; | ||
580 | static const unsigned uartmodtx_c_1_pins[] = { DB8500_PIN_D20 }; | ||
581 | static const unsigned stmmod_c_1_pins[] = { DB8500_PIN_C20, DB8500_PIN_B21, | ||
582 | DB8500_PIN_C21, DB8500_PIN_A22, DB8500_PIN_B24 }; | ||
583 | static const unsigned usbsim_c_1_pins[] = { DB8500_PIN_D22 }; | ||
584 | static const unsigned mc4rstn_c_1_pins[] = { DB8500_PIN_AF25 }; | ||
585 | static const unsigned clkout_c_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AH12 }; | ||
586 | static const unsigned i2c3_c_1_pins[] = { DB8500_PIN_AG12, DB8500_PIN_AH11 }; | ||
587 | static const unsigned spi0_c_1_pins[] = { DB8500_PIN_AH10, DB8500_PIN_AH9, | ||
588 | DB8500_PIN_AG9, DB8500_PIN_AG8 }; | ||
589 | static const unsigned usbsim_c_2_pins[] = { DB8500_PIN_AF8 }; | ||
590 | static const unsigned i2c3_c_2_pins[] = { DB8500_PIN_AG7, DB8500_PIN_AF7 }; | ||
591 | |||
592 | /* Other C1 column */ | ||
593 | static const unsigned kp_oc1_1_pins[] = { DB8500_PIN_C6, DB8500_PIN_B3, | ||
594 | DB8500_PIN_C4, DB8500_PIN_E6, DB8500_PIN_A3, DB8500_PIN_B6, | ||
595 | DB8500_PIN_D6, DB8500_PIN_B7 }; | ||
596 | static const unsigned spi2_oc1_1_pins[] = { DB8500_PIN_AH13, DB8500_PIN_AG12, | ||
597 | DB8500_PIN_AH12, DB8500_PIN_AH11 }; | ||
598 | |||
599 | #define DB8500_PIN_GROUP(a,b) { .name = #a, .pins = a##_pins, \ | ||
600 | .npins = ARRAY_SIZE(a##_pins), .altsetting = b } | ||
601 | |||
602 | static const struct nmk_pingroup nmk_db8500_groups[] = { | ||
603 | /* Altfunction A column */ | ||
604 | DB8500_PIN_GROUP(u0_a_1, NMK_GPIO_ALT_A), | ||
605 | DB8500_PIN_GROUP(u1rxtx_a_1, NMK_GPIO_ALT_A), | ||
606 | DB8500_PIN_GROUP(u1ctsrts_a_1, NMK_GPIO_ALT_A), | ||
607 | DB8500_PIN_GROUP(ipi2c_a_1, NMK_GPIO_ALT_A), | ||
608 | DB8500_PIN_GROUP(ipi2c_a_2, NMK_GPIO_ALT_A), | ||
609 | DB8500_PIN_GROUP(msp0txrx_a_1, NMK_GPIO_ALT_A), | ||
610 | DB8500_PIN_GROUP(msp0tfstck_a_1, NMK_GPIO_ALT_A), | ||
611 | DB8500_PIN_GROUP(msp0rfsrck_a_1, NMK_GPIO_ALT_A), | ||
612 | DB8500_PIN_GROUP(mc0_a_1, NMK_GPIO_ALT_A), | ||
613 | DB8500_PIN_GROUP(msp1txrx_a_1, NMK_GPIO_ALT_A), | ||
614 | DB8500_PIN_GROUP(msp1_a_1, NMK_GPIO_ALT_A), | ||
615 | DB8500_PIN_GROUP(lcdb_a_1, NMK_GPIO_ALT_A), | ||
616 | DB8500_PIN_GROUP(lcdvsi0_a_1, NMK_GPIO_ALT_A), | ||
617 | DB8500_PIN_GROUP(lcdvsi1_a_1, NMK_GPIO_ALT_A), | ||
618 | DB8500_PIN_GROUP(lcd_d0_d7_a_1, NMK_GPIO_ALT_A), | ||
619 | DB8500_PIN_GROUP(lcd_d8_d11_a_1, NMK_GPIO_ALT_A), | ||
620 | DB8500_PIN_GROUP(lcd_d12_d23_a_1, NMK_GPIO_ALT_A), | ||
621 | DB8500_PIN_GROUP(kp_a_1, NMK_GPIO_ALT_A), | ||
622 | DB8500_PIN_GROUP(mc2_a_1, NMK_GPIO_ALT_A), | ||
623 | DB8500_PIN_GROUP(ssp1_a_1, NMK_GPIO_ALT_A), | ||
624 | DB8500_PIN_GROUP(ssp0_a_1, NMK_GPIO_ALT_A), | ||
625 | DB8500_PIN_GROUP(i2c0_a_1, NMK_GPIO_ALT_A), | ||
626 | DB8500_PIN_GROUP(ipgpio0_a_1, NMK_GPIO_ALT_A), | ||
627 | DB8500_PIN_GROUP(ipgpio1_a_1, NMK_GPIO_ALT_A), | ||
628 | DB8500_PIN_GROUP(msp2sck_a_1, NMK_GPIO_ALT_A), | ||
629 | DB8500_PIN_GROUP(msp2_a_1, NMK_GPIO_ALT_A), | ||
630 | DB8500_PIN_GROUP(mc4_a_1, NMK_GPIO_ALT_A), | ||
631 | DB8500_PIN_GROUP(mc1_a_1, NMK_GPIO_ALT_A), | ||
632 | DB8500_PIN_GROUP(hsir_a_1, NMK_GPIO_ALT_A), | ||
633 | DB8500_PIN_GROUP(hsit_a_1, NMK_GPIO_ALT_A), | ||
634 | DB8500_PIN_GROUP(clkout_a_1, NMK_GPIO_ALT_A), | ||
635 | DB8500_PIN_GROUP(clkout_a_2, NMK_GPIO_ALT_A), | ||
636 | DB8500_PIN_GROUP(usb_a_1, NMK_GPIO_ALT_A), | ||
637 | /* Altfunction B column */ | ||
638 | DB8500_PIN_GROUP(trig_b_1, NMK_GPIO_ALT_B), | ||
639 | DB8500_PIN_GROUP(i2c4_b_1, NMK_GPIO_ALT_B), | ||
640 | DB8500_PIN_GROUP(i2c1_b_1, NMK_GPIO_ALT_B), | ||
641 | DB8500_PIN_GROUP(i2c2_b_1, NMK_GPIO_ALT_B), | ||
642 | DB8500_PIN_GROUP(i2c2_b_2, NMK_GPIO_ALT_B), | ||
643 | DB8500_PIN_GROUP(msp0txrx_b_1, NMK_GPIO_ALT_B), | ||
644 | DB8500_PIN_GROUP(i2c1_b_2, NMK_GPIO_ALT_B), | ||
645 | DB8500_PIN_GROUP(u2rxtx_b_1, NMK_GPIO_ALT_B), | ||
646 | DB8500_PIN_GROUP(uartmodtx_b_1, NMK_GPIO_ALT_B), | ||
647 | DB8500_PIN_GROUP(msp0sck_b_1, NMK_GPIO_ALT_B), | ||
648 | DB8500_PIN_GROUP(uartmodrx_b_1, NMK_GPIO_ALT_B), | ||
649 | DB8500_PIN_GROUP(stmmod_b_1, NMK_GPIO_ALT_B), | ||
650 | DB8500_PIN_GROUP(uartmodrx_b_2, NMK_GPIO_ALT_B), | ||
651 | DB8500_PIN_GROUP(spi3_b_1, NMK_GPIO_ALT_B), | ||
652 | DB8500_PIN_GROUP(msp1txrx_b_1, NMK_GPIO_ALT_B), | ||
653 | DB8500_PIN_GROUP(kp_b_1, NMK_GPIO_ALT_B), | ||
654 | DB8500_PIN_GROUP(sm_b_1, NMK_GPIO_ALT_B), | ||
655 | DB8500_PIN_GROUP(smcs0_b_1, NMK_GPIO_ALT_B), | ||
656 | DB8500_PIN_GROUP(ipgpio7_b_1, NMK_GPIO_ALT_B), | ||
657 | DB8500_PIN_GROUP(ipgpio2_b_1, NMK_GPIO_ALT_B), | ||
658 | DB8500_PIN_GROUP(ipgpio3_b_1, NMK_GPIO_ALT_B), | ||
659 | DB8500_PIN_GROUP(lcdaclk_b_1, NMK_GPIO_ALT_B), | ||
660 | DB8500_PIN_GROUP(lcda_b_1, NMK_GPIO_ALT_B), | ||
661 | DB8500_PIN_GROUP(lcd_b_1, NMK_GPIO_ALT_B), | ||
662 | DB8500_PIN_GROUP(ddrtrig_b_1, NMK_GPIO_ALT_B), | ||
663 | DB8500_PIN_GROUP(pwl_b_1, NMK_GPIO_ALT_B), | ||
664 | DB8500_PIN_GROUP(spi1_b_1, NMK_GPIO_ALT_B), | ||
665 | DB8500_PIN_GROUP(mc3_b_1, NMK_GPIO_ALT_B), | ||
666 | DB8500_PIN_GROUP(pwl_b_2, NMK_GPIO_ALT_B), | ||
667 | DB8500_PIN_GROUP(pwl_b_3, NMK_GPIO_ALT_B), | ||
668 | DB8500_PIN_GROUP(pwl_b_4, NMK_GPIO_ALT_B), | ||
669 | /* Altfunction C column */ | ||
670 | DB8500_PIN_GROUP(ipjtag_c_1, NMK_GPIO_ALT_C), | ||
671 | DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), | ||
672 | DB8500_PIN_GROUP(ipgpio0_c_1, NMK_GPIO_ALT_C), | ||
673 | DB8500_PIN_GROUP(ipgpio1_c_1, NMK_GPIO_ALT_C), | ||
674 | DB8500_PIN_GROUP(ipgpio3_c_1, NMK_GPIO_ALT_C), | ||
675 | DB8500_PIN_GROUP(ipgpio2_c_1, NMK_GPIO_ALT_C), | ||
676 | DB8500_PIN_GROUP(slim0_c_1, NMK_GPIO_ALT_C), | ||
677 | DB8500_PIN_GROUP(ms_c_1, NMK_GPIO_ALT_C), | ||
678 | DB8500_PIN_GROUP(iptrigout_c_1, NMK_GPIO_ALT_C), | ||
679 | DB8500_PIN_GROUP(u2rxtx_c_1, NMK_GPIO_ALT_C), | ||
680 | DB8500_PIN_GROUP(u2ctsrts_c_1, NMK_GPIO_ALT_C), | ||
681 | DB8500_PIN_GROUP(u0_c_1, NMK_GPIO_ALT_C), | ||
682 | DB8500_PIN_GROUP(ipgpio4_c_1, NMK_GPIO_ALT_C), | ||
683 | DB8500_PIN_GROUP(ipgpio5_c_1, NMK_GPIO_ALT_C), | ||
684 | DB8500_PIN_GROUP(ipgpio6_c_1, NMK_GPIO_ALT_C), | ||
685 | DB8500_PIN_GROUP(ipgpio7_c_1, NMK_GPIO_ALT_C), | ||
686 | DB8500_PIN_GROUP(smcleale_c_1, NMK_GPIO_ALT_C), | ||
687 | DB8500_PIN_GROUP(stmape_c_1, NMK_GPIO_ALT_C), | ||
688 | DB8500_PIN_GROUP(u2rxtx_c_2, NMK_GPIO_ALT_C), | ||
689 | DB8500_PIN_GROUP(ipgpio2_c_2, NMK_GPIO_ALT_C), | ||
690 | DB8500_PIN_GROUP(ipgpio3_c_2, NMK_GPIO_ALT_C), | ||
691 | DB8500_PIN_GROUP(ipgpio4_c_2, NMK_GPIO_ALT_C), | ||
692 | DB8500_PIN_GROUP(ipgpio5_c_2, NMK_GPIO_ALT_C), | ||
693 | DB8500_PIN_GROUP(mc5_c_1, NMK_GPIO_ALT_C), | ||
694 | DB8500_PIN_GROUP(mc2rstn_c_1, NMK_GPIO_ALT_C), | ||
695 | DB8500_PIN_GROUP(kp_c_1, NMK_GPIO_ALT_C), | ||
696 | DB8500_PIN_GROUP(smps1_c_1, NMK_GPIO_ALT_C), | ||
697 | DB8500_PIN_GROUP(u2rxtx_c_3, NMK_GPIO_ALT_C), | ||
698 | DB8500_PIN_GROUP(stmape_c_2, NMK_GPIO_ALT_C), | ||
699 | DB8500_PIN_GROUP(uartmodrx_c_1, NMK_GPIO_ALT_C), | ||
700 | DB8500_PIN_GROUP(uartmodtx_c_1, NMK_GPIO_ALT_C), | ||
701 | DB8500_PIN_GROUP(stmmod_c_1, NMK_GPIO_ALT_C), | ||
702 | DB8500_PIN_GROUP(usbsim_c_1, NMK_GPIO_ALT_C), | ||
703 | DB8500_PIN_GROUP(mc4rstn_c_1, NMK_GPIO_ALT_C), | ||
704 | DB8500_PIN_GROUP(clkout_c_1, NMK_GPIO_ALT_C), | ||
705 | DB8500_PIN_GROUP(i2c3_c_1, NMK_GPIO_ALT_C), | ||
706 | DB8500_PIN_GROUP(spi0_c_1, NMK_GPIO_ALT_C), | ||
707 | DB8500_PIN_GROUP(usbsim_c_2, NMK_GPIO_ALT_C), | ||
708 | DB8500_PIN_GROUP(i2c3_c_2, NMK_GPIO_ALT_C), | ||
709 | /* Other alt C1 column, these are still configured as alt C */ | ||
710 | DB8500_PIN_GROUP(kp_oc1_1, NMK_GPIO_ALT_C), | ||
711 | DB8500_PIN_GROUP(spi2_oc1_1, NMK_GPIO_ALT_C), | ||
712 | }; | ||
713 | |||
714 | /* We use this macro to define the groups applicable to a function */ | ||
715 | #define DB8500_FUNC_GROUPS(a, b...) \ | ||
716 | static const char * const a##_groups[] = { b }; | ||
717 | |||
718 | DB8500_FUNC_GROUPS(u0, "u0_a_1", "u0_c_1"); | ||
719 | DB8500_FUNC_GROUPS(u1, "u1rxtx_a_1", "u1ctsrts_a_1"); | ||
720 | /* | ||
721 | * UART2 can be muxed out with just RX/TX in four places, CTS+RTS is however | ||
722 | * only available on two pins in alternative function C | ||
723 | */ | ||
724 | DB8500_FUNC_GROUPS(u2, "u2rxtx_b_1", "u2rxtx_c_1", "u2ctsrts_c_1", | ||
725 | "u2rxtx_c_2", "u2rxtx_c_3"); | ||
726 | DB8500_FUNC_GROUPS(ipi2c, "ipi2c_a_1", "ipi2c_a_2"); | ||
727 | /* | ||
728 | * MSP0 can only be on a certain set of pins, but the TX/RX pins can be | ||
729 | * switched around by selecting the altfunction A or B. The SCK pin is | ||
730 | * only available on the altfunction B. | ||
731 | */ | ||
732 | DB8500_FUNC_GROUPS(msp0, "msp0txrx_a_1", "msp0tfstck_a_1", "msp0rfstck_a_1", | ||
733 | "msp0txrx_b_1", "msp0sck_b_1"); | ||
734 | DB8500_FUNC_GROUPS(mc0, "mc0_a_1"); | ||
735 | /* MSP0 can swap RX/TX like MSP0 but has no SCK pin available */ | ||
736 | DB8500_FUNC_GROUPS(msp1, "msp1txrx_a_1", "msp1_a_1", "msp1txrx_b_1"); | ||
737 | DB8500_FUNC_GROUPS(lcdb, "lcdb_a_1"); | ||
738 | DB8500_FUNC_GROUPS(lcd, "lcdvsi0_a_1", "lcdvsi1_a_1", "lcd_d0_d7_a_1", | ||
739 | "lcd_d8_d11_a_1", "lcd_d12_d23_a_1", "lcd_b_1"); | ||
740 | DB8500_FUNC_GROUPS(kp, "kp_a_1", "kp_b_1", "kp_c_1", "kp_oc1_1"); | ||
741 | DB8500_FUNC_GROUPS(mc2, "mc2_a_1", "mc2rstn_c_1"); | ||
742 | DB8500_FUNC_GROUPS(ssp1, "ssp1_a_1"); | ||
743 | DB8500_FUNC_GROUPS(ssp0, "ssp0_a_1"); | ||
744 | DB8500_FUNC_GROUPS(i2c0, "i2c0_a_1"); | ||
745 | /* The image processor has 8 GPIO pins that can be muxed out */ | ||
746 | DB8500_FUNC_GROUPS(ipgpio, "ipgpio0_a_1", "ipgpio1_a_1", "ipgpio7_b_1", | ||
747 | "ipgpio2_b_1", "ipgpio3_b_1", "ipgpio6_c_1", "ipgpio0_c_1", | ||
748 | "ipgpio1_c_1", "ipgpio3_c_1", "ipgpio2_c_1", "ipgpio4_c_1", | ||
749 | "ipgpio5_c_1", "ipgpio6_c_2", "ipgpio7_c_1", "ipgpio2_c_2", | ||
750 | "ipgpio3_c_2", "ipgpio4_c_2", "ipgpio5_c_2"); | ||
751 | /* MSP2 can not invert the RX/TX pins but has the optional SCK pin */ | ||
752 | DB8500_FUNC_GROUPS(msp2, "msp2sck_a_1", "msp2_a_1"); | ||
753 | DB8500_FUNC_GROUPS(mc4, "mc4_a_1", "mc4rstn_c_1"); | ||
754 | DB8500_FUNC_GROUPS(mc1, "mc1_a_1", "mc1dir_a_1"); | ||
755 | DB8500_FUNC_GROUPS(hsi, "hsir1_a_1", "hsit1_a_1"); | ||
756 | DB8500_FUNC_GROUPS(clkout, "clkout_a_1", "clkout_a_2", "clkout_c_1"); | ||
757 | DB8500_FUNC_GROUPS(usb, "usb_a_1"); | ||
758 | DB8500_FUNC_GROUPS(trig, "trig_b_1"); | ||
759 | DB8500_FUNC_GROUPS(i2c4, "i2c4_b_1"); | ||
760 | DB8500_FUNC_GROUPS(i2c1, "i2c1_b_1", "i2c1_b_2"); | ||
761 | DB8500_FUNC_GROUPS(i2c2, "i2c2_b_1", "i2c2_b_2"); | ||
762 | /* | ||
763 | * The modem UART can output its RX and TX pins in some different places, | ||
764 | * so select one of each. | ||
765 | */ | ||
766 | DB8500_FUNC_GROUPS(uartmod, "uartmodtx_b_1", "uartmodrx_b_1", "uartmodrx_b_2", | ||
767 | "uartmodrx_c_1", "uartmod_tx_c_1"); | ||
768 | DB8500_FUNC_GROUPS(stmmod, "stmmod_b_1", "stmmod_c_1"); | ||
769 | DB8500_FUNC_GROUPS(spi3, "spi3_b_1"); | ||
770 | /* Select between CS0 on alt B or PS1 on alt C */ | ||
771 | DB8500_FUNC_GROUPS(sm, "sm_b_1", "smcs0_b_1", "smcleale_c_1", "smps1_c_1"); | ||
772 | DB8500_FUNC_GROUPS(lcda, "lcdaclk_b_1", "lcda_b_1"); | ||
773 | DB8500_FUNC_GROUPS(ddrtrig, "ddrtrig_b_1"); | ||
774 | DB8500_FUNC_GROUPS(pwl, "pwl_b_1", "pwl_b_2", "pwl_b_3", "pwl_b_4"); | ||
775 | DB8500_FUNC_GROUPS(spi1, "spi1_b_1"); | ||
776 | DB8500_FUNC_GROUPS(mc3, "mc3_b_1"); | ||
777 | DB8500_FUNC_GROUPS(ipjtag, "ipjtag_c_1"); | ||
778 | DB8500_FUNC_GROUPS(slim0, "slim0_c_1"); | ||
779 | DB8500_FUNC_GROUPS(ms, "ms_c_1"); | ||
780 | DB8500_FUNC_GROUPS(iptrigout, "iptrigout_c_1"); | ||
781 | DB8500_FUNC_GROUPS(stmape, "stmape_c_1", "stmape_c_2"); | ||
782 | DB8500_FUNC_GROUPS(mc5, "mc5_c_1"); | ||
783 | DB8500_FUNC_GROUPS(usbsim, "usbsim_c_1", "usbsim_c_2"); | ||
784 | DB8500_FUNC_GROUPS(i2c3, "i2c3_c_1", "i2c3_c_2"); | ||
785 | DB8500_FUNC_GROUPS(spi0, "spi0_c_1"); | ||
786 | DB8500_FUNC_GROUPS(spi2, "spi2_oc1_1"); | ||
787 | |||
788 | #define FUNCTION(fname) \ | ||
789 | { \ | ||
790 | .name = #fname, \ | ||
791 | .groups = fname##_groups, \ | ||
792 | .ngroups = ARRAY_SIZE(fname##_groups), \ | ||
793 | } | ||
794 | |||
795 | static const struct nmk_function nmk_db8500_functions[] = { | ||
796 | FUNCTION(u0), | ||
797 | FUNCTION(u1), | ||
798 | FUNCTION(u2), | ||
799 | FUNCTION(ipi2c), | ||
800 | FUNCTION(msp0), | ||
801 | FUNCTION(mc0), | ||
802 | FUNCTION(msp1), | ||
803 | FUNCTION(lcdb), | ||
804 | FUNCTION(lcd), | ||
805 | FUNCTION(kp), | ||
806 | FUNCTION(mc2), | ||
807 | FUNCTION(ssp1), | ||
808 | FUNCTION(ssp0), | ||
809 | FUNCTION(i2c0), | ||
810 | FUNCTION(ipgpio), | ||
811 | FUNCTION(msp2), | ||
812 | FUNCTION(mc4), | ||
813 | FUNCTION(mc1), | ||
814 | FUNCTION(hsi), | ||
815 | FUNCTION(clkout), | ||
816 | FUNCTION(usb), | ||
817 | FUNCTION(trig), | ||
818 | FUNCTION(i2c4), | ||
819 | FUNCTION(i2c1), | ||
820 | FUNCTION(i2c2), | ||
821 | FUNCTION(uartmod), | ||
822 | FUNCTION(stmmod), | ||
823 | FUNCTION(spi3), | ||
824 | FUNCTION(sm), | ||
825 | FUNCTION(lcda), | ||
826 | FUNCTION(ddrtrig), | ||
827 | FUNCTION(pwl), | ||
828 | FUNCTION(spi1), | ||
829 | FUNCTION(mc3), | ||
830 | FUNCTION(ipjtag), | ||
831 | FUNCTION(slim0), | ||
832 | FUNCTION(ms), | ||
833 | FUNCTION(iptrigout), | ||
834 | FUNCTION(stmape), | ||
835 | FUNCTION(mc5), | ||
836 | FUNCTION(usbsim), | ||
837 | FUNCTION(i2c3), | ||
838 | FUNCTION(spi0), | ||
839 | FUNCTION(spi2), | ||
840 | }; | ||
841 | |||
842 | static const struct nmk_pinctrl_soc_data nmk_db8500_soc = { | ||
843 | .gpio_ranges = nmk_db8500_ranges, | ||
844 | .gpio_num_ranges = ARRAY_SIZE(nmk_db8500_ranges), | ||
845 | .pins = nmk_db8500_pins, | ||
846 | .npins = ARRAY_SIZE(nmk_db8500_pins), | ||
847 | .functions = nmk_db8500_functions, | ||
848 | .nfunctions = ARRAY_SIZE(nmk_db8500_functions), | ||
849 | .groups = nmk_db8500_groups, | ||
850 | .ngroups = ARRAY_SIZE(nmk_db8500_groups), | ||
851 | }; | ||
852 | |||
853 | void __devinit | ||
854 | nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) | ||
855 | { | ||
856 | *soc = &nmk_db8500_soc; | ||
857 | } | ||
diff --git a/drivers/gpio/gpio-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c index 839624f9fe6a..b8e01c3eaa95 100644 --- a/drivers/gpio/gpio-nomadik.c +++ b/drivers/pinctrl/pinctrl-nomadik.c | |||
@@ -22,14 +22,20 @@ | |||
22 | #include <linux/spinlock.h> | 22 | #include <linux/spinlock.h> |
23 | #include <linux/interrupt.h> | 23 | #include <linux/interrupt.h> |
24 | #include <linux/irq.h> | 24 | #include <linux/irq.h> |
25 | #include <linux/irqdomain.h> | ||
25 | #include <linux/slab.h> | 26 | #include <linux/slab.h> |
27 | #include <linux/pinctrl/pinctrl.h> | ||
28 | #include <linux/pinctrl/pinmux.h> | ||
29 | #include <linux/pinctrl/pinconf.h> | ||
30 | /* Since we request GPIOs from ourself */ | ||
31 | #include <linux/pinctrl/consumer.h> | ||
26 | 32 | ||
27 | #include <asm/mach/irq.h> | 33 | #include <asm/mach/irq.h> |
28 | 34 | ||
29 | #include <plat/pincfg.h> | 35 | #include <plat/pincfg.h> |
30 | #include <plat/gpio-nomadik.h> | 36 | #include <plat/gpio-nomadik.h> |
31 | #include <mach/hardware.h> | 37 | |
32 | #include <asm/gpio.h> | 38 | #include "pinctrl-nomadik.h" |
33 | 39 | ||
34 | /* | 40 | /* |
35 | * The GPIO module in the Nomadik family of Systems-on-Chip is an | 41 | * The GPIO module in the Nomadik family of Systems-on-Chip is an |
@@ -43,6 +49,7 @@ | |||
43 | 49 | ||
44 | struct nmk_gpio_chip { | 50 | struct nmk_gpio_chip { |
45 | struct gpio_chip chip; | 51 | struct gpio_chip chip; |
52 | struct irq_domain *domain; | ||
46 | void __iomem *addr; | 53 | void __iomem *addr; |
47 | struct clk *clk; | 54 | struct clk *clk; |
48 | unsigned int bank; | 55 | unsigned int bank; |
@@ -58,8 +65,16 @@ struct nmk_gpio_chip { | |||
58 | u32 real_wake; | 65 | u32 real_wake; |
59 | u32 rwimsc; | 66 | u32 rwimsc; |
60 | u32 fwimsc; | 67 | u32 fwimsc; |
61 | u32 slpm; | 68 | u32 rimsc; |
69 | u32 fimsc; | ||
62 | u32 pull_up; | 70 | u32 pull_up; |
71 | u32 lowemi; | ||
72 | }; | ||
73 | |||
74 | struct nmk_pinctrl { | ||
75 | struct device *dev; | ||
76 | struct pinctrl_dev *pctl; | ||
77 | const struct nmk_pinctrl_soc_data *soc; | ||
63 | }; | 78 | }; |
64 | 79 | ||
65 | static struct nmk_gpio_chip * | 80 | static struct nmk_gpio_chip * |
@@ -124,6 +139,24 @@ static void __nmk_gpio_set_pull(struct nmk_gpio_chip *nmk_chip, | |||
124 | } | 139 | } |
125 | } | 140 | } |
126 | 141 | ||
142 | static void __nmk_gpio_set_lowemi(struct nmk_gpio_chip *nmk_chip, | ||
143 | unsigned offset, bool lowemi) | ||
144 | { | ||
145 | u32 bit = BIT(offset); | ||
146 | bool enabled = nmk_chip->lowemi & bit; | ||
147 | |||
148 | if (lowemi == enabled) | ||
149 | return; | ||
150 | |||
151 | if (lowemi) | ||
152 | nmk_chip->lowemi |= bit; | ||
153 | else | ||
154 | nmk_chip->lowemi &= ~bit; | ||
155 | |||
156 | writel_relaxed(nmk_chip->lowemi, | ||
157 | nmk_chip->addr + NMK_GPIO_LOWEMI); | ||
158 | } | ||
159 | |||
127 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, | 160 | static void __nmk_gpio_make_input(struct nmk_gpio_chip *nmk_chip, |
128 | unsigned offset) | 161 | unsigned offset) |
129 | { | 162 | { |
@@ -150,8 +183,8 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, | |||
150 | unsigned offset, int gpio_mode, | 183 | unsigned offset, int gpio_mode, |
151 | bool glitch) | 184 | bool glitch) |
152 | { | 185 | { |
153 | u32 rwimsc = readl(nmk_chip->addr + NMK_GPIO_RWIMSC); | 186 | u32 rwimsc = nmk_chip->rwimsc; |
154 | u32 fwimsc = readl(nmk_chip->addr + NMK_GPIO_FWIMSC); | 187 | u32 fwimsc = nmk_chip->fwimsc; |
155 | 188 | ||
156 | if (glitch && nmk_chip->set_ioforce) { | 189 | if (glitch && nmk_chip->set_ioforce) { |
157 | u32 bit = BIT(offset); | 190 | u32 bit = BIT(offset); |
@@ -173,6 +206,36 @@ static void __nmk_gpio_set_mode_safe(struct nmk_gpio_chip *nmk_chip, | |||
173 | } | 206 | } |
174 | } | 207 | } |
175 | 208 | ||
209 | static void | ||
210 | nmk_gpio_disable_lazy_irq(struct nmk_gpio_chip *nmk_chip, unsigned offset) | ||
211 | { | ||
212 | u32 falling = nmk_chip->fimsc & BIT(offset); | ||
213 | u32 rising = nmk_chip->rimsc & BIT(offset); | ||
214 | int gpio = nmk_chip->chip.base + offset; | ||
215 | int irq = NOMADIK_GPIO_TO_IRQ(gpio); | ||
216 | struct irq_data *d = irq_get_irq_data(irq); | ||
217 | |||
218 | if (!rising && !falling) | ||
219 | return; | ||
220 | |||
221 | if (!d || !irqd_irq_disabled(d)) | ||
222 | return; | ||
223 | |||
224 | if (rising) { | ||
225 | nmk_chip->rimsc &= ~BIT(offset); | ||
226 | writel_relaxed(nmk_chip->rimsc, | ||
227 | nmk_chip->addr + NMK_GPIO_RIMSC); | ||
228 | } | ||
229 | |||
230 | if (falling) { | ||
231 | nmk_chip->fimsc &= ~BIT(offset); | ||
232 | writel_relaxed(nmk_chip->fimsc, | ||
233 | nmk_chip->addr + NMK_GPIO_FIMSC); | ||
234 | } | ||
235 | |||
236 | dev_dbg(nmk_chip->chip.dev, "%d: clearing interrupt mask\n", gpio); | ||
237 | } | ||
238 | |||
176 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, | 239 | static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, |
177 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) | 240 | pin_cfg_t cfg, bool sleep, unsigned int *slpmregs) |
178 | { | 241 | { |
@@ -238,6 +301,17 @@ static void __nmk_config_pin(struct nmk_gpio_chip *nmk_chip, unsigned offset, | |||
238 | __nmk_gpio_set_pull(nmk_chip, offset, pull); | 301 | __nmk_gpio_set_pull(nmk_chip, offset, pull); |
239 | } | 302 | } |
240 | 303 | ||
304 | __nmk_gpio_set_lowemi(nmk_chip, offset, PIN_LOWEMI(cfg)); | ||
305 | |||
306 | /* | ||
307 | * If the pin is switching to altfunc, and there was an interrupt | ||
308 | * installed on it which has been lazy disabled, actually mask the | ||
309 | * interrupt to prevent spurious interrupts that would occur while the | ||
310 | * pin is under control of the peripheral. Only SKE does this. | ||
311 | */ | ||
312 | if (af != NMK_GPIO_ALT_GPIO) | ||
313 | nmk_gpio_disable_lazy_irq(nmk_chip, offset); | ||
314 | |||
241 | /* | 315 | /* |
242 | * If we've backed up the SLPM registers (glitch workaround), modify | 316 | * If we've backed up the SLPM registers (glitch workaround), modify |
243 | * the backups since they will be restored. | 317 | * the backups since they will be restored. |
@@ -334,7 +408,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |||
334 | struct nmk_gpio_chip *nmk_chip; | 408 | struct nmk_gpio_chip *nmk_chip; |
335 | int pin = PIN_NUM(cfgs[i]); | 409 | int pin = PIN_NUM(cfgs[i]); |
336 | 410 | ||
337 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(pin)); | 411 | nmk_chip = nmk_gpio_chips[pin / NMK_GPIO_PER_CHIP]; |
338 | if (!nmk_chip) { | 412 | if (!nmk_chip) { |
339 | ret = -EINVAL; | 413 | ret = -EINVAL; |
340 | break; | 414 | break; |
@@ -342,7 +416,7 @@ static int __nmk_config_pins(pin_cfg_t *cfgs, int num, bool sleep) | |||
342 | 416 | ||
343 | clk_enable(nmk_chip->clk); | 417 | clk_enable(nmk_chip->clk); |
344 | spin_lock(&nmk_chip->lock); | 418 | spin_lock(&nmk_chip->lock); |
345 | __nmk_config_pin(nmk_chip, pin - nmk_chip->chip.base, | 419 | __nmk_config_pin(nmk_chip, pin % NMK_GPIO_PER_CHIP, |
346 | cfgs[i], sleep, glitch ? slpm : NULL); | 420 | cfgs[i], sleep, glitch ? slpm : NULL); |
347 | spin_unlock(&nmk_chip->lock); | 421 | spin_unlock(&nmk_chip->lock); |
348 | clk_disable(nmk_chip->clk); | 422 | clk_disable(nmk_chip->clk); |
@@ -426,7 +500,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |||
426 | struct nmk_gpio_chip *nmk_chip; | 500 | struct nmk_gpio_chip *nmk_chip; |
427 | unsigned long flags; | 501 | unsigned long flags; |
428 | 502 | ||
429 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 503 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
430 | if (!nmk_chip) | 504 | if (!nmk_chip) |
431 | return -EINVAL; | 505 | return -EINVAL; |
432 | 506 | ||
@@ -434,7 +508,7 @@ int nmk_gpio_set_slpm(int gpio, enum nmk_gpio_slpm mode) | |||
434 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | 508 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
435 | spin_lock(&nmk_chip->lock); | 509 | spin_lock(&nmk_chip->lock); |
436 | 510 | ||
437 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, mode); | 511 | __nmk_gpio_set_slpm(nmk_chip, gpio % NMK_GPIO_PER_CHIP, mode); |
438 | 512 | ||
439 | spin_unlock(&nmk_chip->lock); | 513 | spin_unlock(&nmk_chip->lock); |
440 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | 514 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); |
@@ -461,13 +535,13 @@ int nmk_gpio_set_pull(int gpio, enum nmk_gpio_pull pull) | |||
461 | struct nmk_gpio_chip *nmk_chip; | 535 | struct nmk_gpio_chip *nmk_chip; |
462 | unsigned long flags; | 536 | unsigned long flags; |
463 | 537 | ||
464 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 538 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
465 | if (!nmk_chip) | 539 | if (!nmk_chip) |
466 | return -EINVAL; | 540 | return -EINVAL; |
467 | 541 | ||
468 | clk_enable(nmk_chip->clk); | 542 | clk_enable(nmk_chip->clk); |
469 | spin_lock_irqsave(&nmk_chip->lock, flags); | 543 | spin_lock_irqsave(&nmk_chip->lock, flags); |
470 | __nmk_gpio_set_pull(nmk_chip, gpio - nmk_chip->chip.base, pull); | 544 | __nmk_gpio_set_pull(nmk_chip, gpio % NMK_GPIO_PER_CHIP, pull); |
471 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | 545 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
472 | clk_disable(nmk_chip->clk); | 546 | clk_disable(nmk_chip->clk); |
473 | 547 | ||
@@ -489,13 +563,13 @@ int nmk_gpio_set_mode(int gpio, int gpio_mode) | |||
489 | struct nmk_gpio_chip *nmk_chip; | 563 | struct nmk_gpio_chip *nmk_chip; |
490 | unsigned long flags; | 564 | unsigned long flags; |
491 | 565 | ||
492 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 566 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
493 | if (!nmk_chip) | 567 | if (!nmk_chip) |
494 | return -EINVAL; | 568 | return -EINVAL; |
495 | 569 | ||
496 | clk_enable(nmk_chip->clk); | 570 | clk_enable(nmk_chip->clk); |
497 | spin_lock_irqsave(&nmk_chip->lock, flags); | 571 | spin_lock_irqsave(&nmk_chip->lock, flags); |
498 | __nmk_gpio_set_mode(nmk_chip, gpio - nmk_chip->chip.base, gpio_mode); | 572 | __nmk_gpio_set_mode(nmk_chip, gpio % NMK_GPIO_PER_CHIP, gpio_mode); |
499 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | 573 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
500 | clk_disable(nmk_chip->clk); | 574 | clk_disable(nmk_chip->clk); |
501 | 575 | ||
@@ -508,11 +582,11 @@ int nmk_gpio_get_mode(int gpio) | |||
508 | struct nmk_gpio_chip *nmk_chip; | 582 | struct nmk_gpio_chip *nmk_chip; |
509 | u32 afunc, bfunc, bit; | 583 | u32 afunc, bfunc, bit; |
510 | 584 | ||
511 | nmk_chip = irq_get_chip_data(NOMADIK_GPIO_TO_IRQ(gpio)); | 585 | nmk_chip = nmk_gpio_chips[gpio / NMK_GPIO_PER_CHIP]; |
512 | if (!nmk_chip) | 586 | if (!nmk_chip) |
513 | return -EINVAL; | 587 | return -EINVAL; |
514 | 588 | ||
515 | bit = 1 << (gpio - nmk_chip->chip.base); | 589 | bit = 1 << (gpio % NMK_GPIO_PER_CHIP); |
516 | 590 | ||
517 | clk_enable(nmk_chip->clk); | 591 | clk_enable(nmk_chip->clk); |
518 | 592 | ||
@@ -529,21 +603,19 @@ EXPORT_SYMBOL(nmk_gpio_get_mode); | |||
529 | /* IRQ functions */ | 603 | /* IRQ functions */ |
530 | static inline int nmk_gpio_get_bitmask(int gpio) | 604 | static inline int nmk_gpio_get_bitmask(int gpio) |
531 | { | 605 | { |
532 | return 1 << (gpio % 32); | 606 | return 1 << (gpio % NMK_GPIO_PER_CHIP); |
533 | } | 607 | } |
534 | 608 | ||
535 | static void nmk_gpio_irq_ack(struct irq_data *d) | 609 | static void nmk_gpio_irq_ack(struct irq_data *d) |
536 | { | 610 | { |
537 | int gpio; | ||
538 | struct nmk_gpio_chip *nmk_chip; | 611 | struct nmk_gpio_chip *nmk_chip; |
539 | 612 | ||
540 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); | ||
541 | nmk_chip = irq_data_get_irq_chip_data(d); | 613 | nmk_chip = irq_data_get_irq_chip_data(d); |
542 | if (!nmk_chip) | 614 | if (!nmk_chip) |
543 | return; | 615 | return; |
544 | 616 | ||
545 | clk_enable(nmk_chip->clk); | 617 | clk_enable(nmk_chip->clk); |
546 | writel(nmk_gpio_get_bitmask(gpio), nmk_chip->addr + NMK_GPIO_IC); | 618 | writel(nmk_gpio_get_bitmask(d->hwirq), nmk_chip->addr + NMK_GPIO_IC); |
547 | clk_disable(nmk_chip->clk); | 619 | clk_disable(nmk_chip->clk); |
548 | } | 620 | } |
549 | 621 | ||
@@ -556,37 +628,52 @@ static void __nmk_gpio_irq_modify(struct nmk_gpio_chip *nmk_chip, | |||
556 | int gpio, enum nmk_gpio_irq_type which, | 628 | int gpio, enum nmk_gpio_irq_type which, |
557 | bool enable) | 629 | bool enable) |
558 | { | 630 | { |
559 | u32 rimsc = which == WAKE ? NMK_GPIO_RWIMSC : NMK_GPIO_RIMSC; | ||
560 | u32 fimsc = which == WAKE ? NMK_GPIO_FWIMSC : NMK_GPIO_FIMSC; | ||
561 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | 631 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
562 | u32 reg; | 632 | u32 *rimscval; |
633 | u32 *fimscval; | ||
634 | u32 rimscreg; | ||
635 | u32 fimscreg; | ||
636 | |||
637 | if (which == NORMAL) { | ||
638 | rimscreg = NMK_GPIO_RIMSC; | ||
639 | fimscreg = NMK_GPIO_FIMSC; | ||
640 | rimscval = &nmk_chip->rimsc; | ||
641 | fimscval = &nmk_chip->fimsc; | ||
642 | } else { | ||
643 | rimscreg = NMK_GPIO_RWIMSC; | ||
644 | fimscreg = NMK_GPIO_FWIMSC; | ||
645 | rimscval = &nmk_chip->rwimsc; | ||
646 | fimscval = &nmk_chip->fwimsc; | ||
647 | } | ||
563 | 648 | ||
564 | /* we must individually set/clear the two edges */ | 649 | /* we must individually set/clear the two edges */ |
565 | if (nmk_chip->edge_rising & bitmask) { | 650 | if (nmk_chip->edge_rising & bitmask) { |
566 | reg = readl(nmk_chip->addr + rimsc); | ||
567 | if (enable) | 651 | if (enable) |
568 | reg |= bitmask; | 652 | *rimscval |= bitmask; |
569 | else | 653 | else |
570 | reg &= ~bitmask; | 654 | *rimscval &= ~bitmask; |
571 | writel(reg, nmk_chip->addr + rimsc); | 655 | writel(*rimscval, nmk_chip->addr + rimscreg); |
572 | } | 656 | } |
573 | if (nmk_chip->edge_falling & bitmask) { | 657 | if (nmk_chip->edge_falling & bitmask) { |
574 | reg = readl(nmk_chip->addr + fimsc); | ||
575 | if (enable) | 658 | if (enable) |
576 | reg |= bitmask; | 659 | *fimscval |= bitmask; |
577 | else | 660 | else |
578 | reg &= ~bitmask; | 661 | *fimscval &= ~bitmask; |
579 | writel(reg, nmk_chip->addr + fimsc); | 662 | writel(*fimscval, nmk_chip->addr + fimscreg); |
580 | } | 663 | } |
581 | } | 664 | } |
582 | 665 | ||
583 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, | 666 | static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, |
584 | int gpio, bool on) | 667 | int gpio, bool on) |
585 | { | 668 | { |
586 | if (nmk_chip->sleepmode) { | 669 | /* |
587 | __nmk_gpio_set_slpm(nmk_chip, gpio - nmk_chip->chip.base, | 670 | * Ensure WAKEUP_ENABLE is on. No need to disable it if wakeup is |
588 | on ? NMK_GPIO_SLPM_WAKEUP_ENABLE | 671 | * disabled, since setting SLPM to 1 increases power consumption, and |
589 | : NMK_GPIO_SLPM_WAKEUP_DISABLE); | 672 | * wakeup is anyhow controlled by the RIMSC and FIMSC registers. |
673 | */ | ||
674 | if (nmk_chip->sleepmode && on) { | ||
675 | __nmk_gpio_set_slpm(nmk_chip, gpio % nmk_chip->chip.base, | ||
676 | NMK_GPIO_SLPM_WAKEUP_ENABLE); | ||
590 | } | 677 | } |
591 | 678 | ||
592 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); | 679 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, on); |
@@ -594,14 +681,12 @@ static void __nmk_gpio_set_wake(struct nmk_gpio_chip *nmk_chip, | |||
594 | 681 | ||
595 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | 682 | static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) |
596 | { | 683 | { |
597 | int gpio; | ||
598 | struct nmk_gpio_chip *nmk_chip; | 684 | struct nmk_gpio_chip *nmk_chip; |
599 | unsigned long flags; | 685 | unsigned long flags; |
600 | u32 bitmask; | 686 | u32 bitmask; |
601 | 687 | ||
602 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); | ||
603 | nmk_chip = irq_data_get_irq_chip_data(d); | 688 | nmk_chip = irq_data_get_irq_chip_data(d); |
604 | bitmask = nmk_gpio_get_bitmask(gpio); | 689 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
605 | if (!nmk_chip) | 690 | if (!nmk_chip) |
606 | return -EINVAL; | 691 | return -EINVAL; |
607 | 692 | ||
@@ -609,10 +694,10 @@ static int nmk_gpio_irq_maskunmask(struct irq_data *d, bool enable) | |||
609 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | 694 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
610 | spin_lock(&nmk_chip->lock); | 695 | spin_lock(&nmk_chip->lock); |
611 | 696 | ||
612 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, enable); | 697 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, enable); |
613 | 698 | ||
614 | if (!(nmk_chip->real_wake & bitmask)) | 699 | if (!(nmk_chip->real_wake & bitmask)) |
615 | __nmk_gpio_set_wake(nmk_chip, gpio, enable); | 700 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, enable); |
616 | 701 | ||
617 | spin_unlock(&nmk_chip->lock); | 702 | spin_unlock(&nmk_chip->lock); |
618 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | 703 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); |
@@ -636,20 +721,18 @@ static int nmk_gpio_irq_set_wake(struct irq_data *d, unsigned int on) | |||
636 | struct nmk_gpio_chip *nmk_chip; | 721 | struct nmk_gpio_chip *nmk_chip; |
637 | unsigned long flags; | 722 | unsigned long flags; |
638 | u32 bitmask; | 723 | u32 bitmask; |
639 | int gpio; | ||
640 | 724 | ||
641 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); | ||
642 | nmk_chip = irq_data_get_irq_chip_data(d); | 725 | nmk_chip = irq_data_get_irq_chip_data(d); |
643 | if (!nmk_chip) | 726 | if (!nmk_chip) |
644 | return -EINVAL; | 727 | return -EINVAL; |
645 | bitmask = nmk_gpio_get_bitmask(gpio); | 728 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
646 | 729 | ||
647 | clk_enable(nmk_chip->clk); | 730 | clk_enable(nmk_chip->clk); |
648 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | 731 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); |
649 | spin_lock(&nmk_chip->lock); | 732 | spin_lock(&nmk_chip->lock); |
650 | 733 | ||
651 | if (irqd_irq_disabled(d)) | 734 | if (irqd_irq_disabled(d)) |
652 | __nmk_gpio_set_wake(nmk_chip, gpio, on); | 735 | __nmk_gpio_set_wake(nmk_chip, d->hwirq, on); |
653 | 736 | ||
654 | if (on) | 737 | if (on) |
655 | nmk_chip->real_wake |= bitmask; | 738 | nmk_chip->real_wake |= bitmask; |
@@ -667,17 +750,14 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |||
667 | { | 750 | { |
668 | bool enabled = !irqd_irq_disabled(d); | 751 | bool enabled = !irqd_irq_disabled(d); |
669 | bool wake = irqd_is_wakeup_set(d); | 752 | bool wake = irqd_is_wakeup_set(d); |
670 | int gpio; | ||
671 | struct nmk_gpio_chip *nmk_chip; | 753 | struct nmk_gpio_chip *nmk_chip; |
672 | unsigned long flags; | 754 | unsigned long flags; |
673 | u32 bitmask; | 755 | u32 bitmask; |
674 | 756 | ||
675 | gpio = NOMADIK_IRQ_TO_GPIO(d->irq); | ||
676 | nmk_chip = irq_data_get_irq_chip_data(d); | 757 | nmk_chip = irq_data_get_irq_chip_data(d); |
677 | bitmask = nmk_gpio_get_bitmask(gpio); | 758 | bitmask = nmk_gpio_get_bitmask(d->hwirq); |
678 | if (!nmk_chip) | 759 | if (!nmk_chip) |
679 | return -EINVAL; | 760 | return -EINVAL; |
680 | |||
681 | if (type & IRQ_TYPE_LEVEL_HIGH) | 761 | if (type & IRQ_TYPE_LEVEL_HIGH) |
682 | return -EINVAL; | 762 | return -EINVAL; |
683 | if (type & IRQ_TYPE_LEVEL_LOW) | 763 | if (type & IRQ_TYPE_LEVEL_LOW) |
@@ -687,10 +767,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |||
687 | spin_lock_irqsave(&nmk_chip->lock, flags); | 767 | spin_lock_irqsave(&nmk_chip->lock, flags); |
688 | 768 | ||
689 | if (enabled) | 769 | if (enabled) |
690 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, false); | 770 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, false); |
691 | 771 | ||
692 | if (enabled || wake) | 772 | if (enabled || wake) |
693 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, false); | 773 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, false); |
694 | 774 | ||
695 | nmk_chip->edge_rising &= ~bitmask; | 775 | nmk_chip->edge_rising &= ~bitmask; |
696 | if (type & IRQ_TYPE_EDGE_RISING) | 776 | if (type & IRQ_TYPE_EDGE_RISING) |
@@ -701,10 +781,10 @@ static int nmk_gpio_irq_set_type(struct irq_data *d, unsigned int type) | |||
701 | nmk_chip->edge_falling |= bitmask; | 781 | nmk_chip->edge_falling |= bitmask; |
702 | 782 | ||
703 | if (enabled) | 783 | if (enabled) |
704 | __nmk_gpio_irq_modify(nmk_chip, gpio, NORMAL, true); | 784 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, NORMAL, true); |
705 | 785 | ||
706 | if (enabled || wake) | 786 | if (enabled || wake) |
707 | __nmk_gpio_irq_modify(nmk_chip, gpio, WAKE, true); | 787 | __nmk_gpio_irq_modify(nmk_chip, d->hwirq, WAKE, true); |
708 | 788 | ||
709 | spin_unlock_irqrestore(&nmk_chip->lock, flags); | 789 | spin_unlock_irqrestore(&nmk_chip->lock, flags); |
710 | clk_disable(nmk_chip->clk); | 790 | clk_disable(nmk_chip->clk); |
@@ -750,7 +830,7 @@ static void __nmk_gpio_irq_handler(unsigned int irq, struct irq_desc *desc, | |||
750 | chained_irq_enter(host_chip, desc); | 830 | chained_irq_enter(host_chip, desc); |
751 | 831 | ||
752 | nmk_chip = irq_get_handler_data(irq); | 832 | nmk_chip = irq_get_handler_data(irq); |
753 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | 833 | first_irq = nmk_chip->domain->revmap_data.legacy.first_irq; |
754 | while (status) { | 834 | while (status) { |
755 | int bit = __ffs(status); | 835 | int bit = __ffs(status); |
756 | 836 | ||
@@ -784,18 +864,6 @@ static void nmk_gpio_secondary_irq_handler(unsigned int irq, | |||
784 | 864 | ||
785 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) | 865 | static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) |
786 | { | 866 | { |
787 | unsigned int first_irq; | ||
788 | int i; | ||
789 | |||
790 | first_irq = NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base); | ||
791 | for (i = first_irq; i < first_irq + nmk_chip->chip.ngpio; i++) { | ||
792 | irq_set_chip_and_handler(i, &nmk_gpio_irq_chip, | ||
793 | handle_edge_irq); | ||
794 | set_irq_flags(i, IRQF_VALID); | ||
795 | irq_set_chip_data(i, nmk_chip); | ||
796 | irq_set_irq_type(i, IRQ_TYPE_EDGE_FALLING); | ||
797 | } | ||
798 | |||
799 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); | 867 | irq_set_chained_handler(nmk_chip->parent_irq, nmk_gpio_irq_handler); |
800 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); | 868 | irq_set_handler_data(nmk_chip->parent_irq, nmk_chip); |
801 | 869 | ||
@@ -809,6 +877,25 @@ static int nmk_gpio_init_irq(struct nmk_gpio_chip *nmk_chip) | |||
809 | } | 877 | } |
810 | 878 | ||
811 | /* I/O Functions */ | 879 | /* I/O Functions */ |
880 | |||
881 | static int nmk_gpio_request(struct gpio_chip *chip, unsigned offset) | ||
882 | { | ||
883 | /* | ||
884 | * Map back to global GPIO space and request muxing, the direction | ||
885 | * parameter does not matter for this controller. | ||
886 | */ | ||
887 | int gpio = chip->base + offset; | ||
888 | |||
889 | return pinctrl_request_gpio(gpio); | ||
890 | } | ||
891 | |||
892 | static void nmk_gpio_free(struct gpio_chip *chip, unsigned offset) | ||
893 | { | ||
894 | int gpio = chip->base + offset; | ||
895 | |||
896 | pinctrl_free_gpio(gpio); | ||
897 | } | ||
898 | |||
812 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) | 899 | static int nmk_gpio_make_input(struct gpio_chip *chip, unsigned offset) |
813 | { | 900 | { |
814 | struct nmk_gpio_chip *nmk_chip = | 901 | struct nmk_gpio_chip *nmk_chip = |
@@ -872,21 +959,23 @@ static int nmk_gpio_to_irq(struct gpio_chip *chip, unsigned offset) | |||
872 | struct nmk_gpio_chip *nmk_chip = | 959 | struct nmk_gpio_chip *nmk_chip = |
873 | container_of(chip, struct nmk_gpio_chip, chip); | 960 | container_of(chip, struct nmk_gpio_chip, chip); |
874 | 961 | ||
875 | return NOMADIK_GPIO_TO_IRQ(nmk_chip->chip.base) + offset; | 962 | return irq_find_mapping(nmk_chip->domain, offset); |
876 | } | 963 | } |
877 | 964 | ||
878 | #ifdef CONFIG_DEBUG_FS | 965 | #ifdef CONFIG_DEBUG_FS |
879 | 966 | ||
880 | #include <linux/seq_file.h> | 967 | #include <linux/seq_file.h> |
881 | 968 | ||
882 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | 969 | static void nmk_gpio_dbg_show_one(struct seq_file *s, struct gpio_chip *chip, |
970 | unsigned offset, unsigned gpio) | ||
883 | { | 971 | { |
884 | int mode; | 972 | const char *label = gpiochip_is_requested(chip, offset); |
885 | unsigned i; | ||
886 | unsigned gpio = chip->base; | ||
887 | int is_out; | ||
888 | struct nmk_gpio_chip *nmk_chip = | 973 | struct nmk_gpio_chip *nmk_chip = |
889 | container_of(chip, struct nmk_gpio_chip, chip); | 974 | container_of(chip, struct nmk_gpio_chip, chip); |
975 | int mode; | ||
976 | bool is_out; | ||
977 | bool pull; | ||
978 | u32 bit = 1 << offset; | ||
890 | const char *modes[] = { | 979 | const char *modes[] = { |
891 | [NMK_GPIO_ALT_GPIO] = "gpio", | 980 | [NMK_GPIO_ALT_GPIO] = "gpio", |
892 | [NMK_GPIO_ALT_A] = "altA", | 981 | [NMK_GPIO_ALT_A] = "altA", |
@@ -895,61 +984,70 @@ static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | |||
895 | }; | 984 | }; |
896 | 985 | ||
897 | clk_enable(nmk_chip->clk); | 986 | clk_enable(nmk_chip->clk); |
898 | 987 | is_out = !!(readl(nmk_chip->addr + NMK_GPIO_DIR) & bit); | |
899 | for (i = 0; i < chip->ngpio; i++, gpio++) { | 988 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); |
900 | const char *label = gpiochip_is_requested(chip, i); | 989 | mode = nmk_gpio_get_mode(gpio); |
901 | bool pull; | 990 | |
902 | u32 bit = 1 << i; | 991 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", |
903 | 992 | gpio, label ?: "(none)", | |
904 | is_out = readl(nmk_chip->addr + NMK_GPIO_DIR) & bit; | 993 | is_out ? "out" : "in ", |
905 | pull = !(readl(nmk_chip->addr + NMK_GPIO_PDIS) & bit); | 994 | chip->get |
906 | mode = nmk_gpio_get_mode(gpio); | 995 | ? (chip->get(chip, offset) ? "hi" : "lo") |
907 | seq_printf(s, " gpio-%-3d (%-20.20s) %s %s %s %s", | 996 | : "? ", |
908 | gpio, label ?: "(none)", | 997 | (mode < 0) ? "unknown" : modes[mode], |
909 | is_out ? "out" : "in ", | 998 | pull ? "pull" : "none"); |
910 | chip->get | 999 | |
911 | ? (chip->get(chip, i) ? "hi" : "lo") | 1000 | if (label && !is_out) { |
912 | : "? ", | 1001 | int irq = gpio_to_irq(gpio); |
913 | (mode < 0) ? "unknown" : modes[mode], | 1002 | struct irq_desc *desc = irq_to_desc(irq); |
914 | pull ? "pull" : "none"); | 1003 | |
915 | 1004 | /* This races with request_irq(), set_irq_type(), | |
916 | if (label && !is_out) { | 1005 | * and set_irq_wake() ... but those are "rare". |
917 | int irq = gpio_to_irq(gpio); | 1006 | */ |
918 | struct irq_desc *desc = irq_to_desc(irq); | 1007 | if (irq >= 0 && desc->action) { |
919 | 1008 | char *trigger; | |
920 | /* This races with request_irq(), set_irq_type(), | 1009 | u32 bitmask = nmk_gpio_get_bitmask(gpio); |
921 | * and set_irq_wake() ... but those are "rare". | 1010 | |
922 | */ | 1011 | if (nmk_chip->edge_rising & bitmask) |
923 | if (irq >= 0 && desc->action) { | 1012 | trigger = "edge-rising"; |
924 | char *trigger; | 1013 | else if (nmk_chip->edge_falling & bitmask) |
925 | u32 bitmask = nmk_gpio_get_bitmask(gpio); | 1014 | trigger = "edge-falling"; |
926 | 1015 | else | |
927 | if (nmk_chip->edge_rising & bitmask) | 1016 | trigger = "edge-undefined"; |
928 | trigger = "edge-rising"; | 1017 | |
929 | else if (nmk_chip->edge_falling & bitmask) | 1018 | seq_printf(s, " irq-%d %s%s", |
930 | trigger = "edge-falling"; | 1019 | irq, trigger, |
931 | else | 1020 | irqd_is_wakeup_set(&desc->irq_data) |
932 | trigger = "edge-undefined"; | 1021 | ? " wakeup" : ""); |
933 | |||
934 | seq_printf(s, " irq-%d %s%s", | ||
935 | irq, trigger, | ||
936 | irqd_is_wakeup_set(&desc->irq_data) | ||
937 | ? " wakeup" : ""); | ||
938 | } | ||
939 | } | 1022 | } |
1023 | } | ||
1024 | clk_disable(nmk_chip->clk); | ||
1025 | } | ||
940 | 1026 | ||
1027 | static void nmk_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip) | ||
1028 | { | ||
1029 | unsigned i; | ||
1030 | unsigned gpio = chip->base; | ||
1031 | |||
1032 | for (i = 0; i < chip->ngpio; i++, gpio++) { | ||
1033 | nmk_gpio_dbg_show_one(s, chip, i, gpio); | ||
941 | seq_printf(s, "\n"); | 1034 | seq_printf(s, "\n"); |
942 | } | 1035 | } |
943 | |||
944 | clk_disable(nmk_chip->clk); | ||
945 | } | 1036 | } |
946 | 1037 | ||
947 | #else | 1038 | #else |
1039 | static inline void nmk_gpio_dbg_show_one(struct seq_file *s, | ||
1040 | struct gpio_chip *chip, | ||
1041 | unsigned offset, unsigned gpio) | ||
1042 | { | ||
1043 | } | ||
948 | #define nmk_gpio_dbg_show NULL | 1044 | #define nmk_gpio_dbg_show NULL |
949 | #endif | 1045 | #endif |
950 | 1046 | ||
951 | /* This structure is replicated for each GPIO block allocated at probe time */ | 1047 | /* This structure is replicated for each GPIO block allocated at probe time */ |
952 | static struct gpio_chip nmk_gpio_template = { | 1048 | static struct gpio_chip nmk_gpio_template = { |
1049 | .request = nmk_gpio_request, | ||
1050 | .free = nmk_gpio_free, | ||
953 | .direction_input = nmk_gpio_make_input, | 1051 | .direction_input = nmk_gpio_make_input, |
954 | .get = nmk_gpio_get_input, | 1052 | .get = nmk_gpio_get_input, |
955 | .direction_output = nmk_gpio_make_output, | 1053 | .direction_output = nmk_gpio_make_output, |
@@ -1008,21 +1106,11 @@ void nmk_gpio_wakeups_suspend(void) | |||
1008 | 1106 | ||
1009 | clk_enable(chip->clk); | 1107 | clk_enable(chip->clk); |
1010 | 1108 | ||
1011 | chip->rwimsc = readl(chip->addr + NMK_GPIO_RWIMSC); | ||
1012 | chip->fwimsc = readl(chip->addr + NMK_GPIO_FWIMSC); | ||
1013 | |||
1014 | writel(chip->rwimsc & chip->real_wake, | 1109 | writel(chip->rwimsc & chip->real_wake, |
1015 | chip->addr + NMK_GPIO_RWIMSC); | 1110 | chip->addr + NMK_GPIO_RWIMSC); |
1016 | writel(chip->fwimsc & chip->real_wake, | 1111 | writel(chip->fwimsc & chip->real_wake, |
1017 | chip->addr + NMK_GPIO_FWIMSC); | 1112 | chip->addr + NMK_GPIO_FWIMSC); |
1018 | 1113 | ||
1019 | if (chip->sleepmode) { | ||
1020 | chip->slpm = readl(chip->addr + NMK_GPIO_SLPC); | ||
1021 | |||
1022 | /* 0 -> wakeup enable */ | ||
1023 | writel(~chip->real_wake, chip->addr + NMK_GPIO_SLPC); | ||
1024 | } | ||
1025 | |||
1026 | clk_disable(chip->clk); | 1114 | clk_disable(chip->clk); |
1027 | } | 1115 | } |
1028 | } | 1116 | } |
@@ -1042,9 +1130,6 @@ void nmk_gpio_wakeups_resume(void) | |||
1042 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); | 1130 | writel(chip->rwimsc, chip->addr + NMK_GPIO_RWIMSC); |
1043 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); | 1131 | writel(chip->fwimsc, chip->addr + NMK_GPIO_FWIMSC); |
1044 | 1132 | ||
1045 | if (chip->sleepmode) | ||
1046 | writel(chip->slpm, chip->addr + NMK_GPIO_SLPC); | ||
1047 | |||
1048 | clk_disable(chip->clk); | 1133 | clk_disable(chip->clk); |
1049 | } | 1134 | } |
1050 | } | 1135 | } |
@@ -1068,19 +1153,62 @@ void nmk_gpio_read_pull(int gpio_bank, u32 *pull_up) | |||
1068 | } | 1153 | } |
1069 | } | 1154 | } |
1070 | 1155 | ||
1156 | int nmk_gpio_irq_map(struct irq_domain *d, unsigned int irq, | ||
1157 | irq_hw_number_t hwirq) | ||
1158 | { | ||
1159 | struct nmk_gpio_chip *nmk_chip = d->host_data; | ||
1160 | |||
1161 | if (!nmk_chip) | ||
1162 | return -EINVAL; | ||
1163 | |||
1164 | irq_set_chip_and_handler(irq, &nmk_gpio_irq_chip, handle_edge_irq); | ||
1165 | set_irq_flags(irq, IRQF_VALID); | ||
1166 | irq_set_chip_data(irq, nmk_chip); | ||
1167 | irq_set_irq_type(irq, IRQ_TYPE_EDGE_FALLING); | ||
1168 | |||
1169 | return 0; | ||
1170 | } | ||
1171 | |||
1172 | const struct irq_domain_ops nmk_gpio_irq_simple_ops = { | ||
1173 | .map = nmk_gpio_irq_map, | ||
1174 | .xlate = irq_domain_xlate_twocell, | ||
1175 | }; | ||
1176 | |||
1071 | static int __devinit nmk_gpio_probe(struct platform_device *dev) | 1177 | static int __devinit nmk_gpio_probe(struct platform_device *dev) |
1072 | { | 1178 | { |
1073 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; | 1179 | struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; |
1180 | struct device_node *np = dev->dev.of_node; | ||
1074 | struct nmk_gpio_chip *nmk_chip; | 1181 | struct nmk_gpio_chip *nmk_chip; |
1075 | struct gpio_chip *chip; | 1182 | struct gpio_chip *chip; |
1076 | struct resource *res; | 1183 | struct resource *res; |
1077 | struct clk *clk; | 1184 | struct clk *clk; |
1078 | int secondary_irq; | 1185 | int secondary_irq; |
1186 | void __iomem *base; | ||
1079 | int irq; | 1187 | int irq; |
1080 | int ret; | 1188 | int ret; |
1081 | 1189 | ||
1082 | if (!pdata) | 1190 | if (!pdata && !np) { |
1191 | dev_err(&dev->dev, "No platform data or device tree found\n"); | ||
1083 | return -ENODEV; | 1192 | return -ENODEV; |
1193 | } | ||
1194 | |||
1195 | if (np) { | ||
1196 | pdata = kzalloc(sizeof(*pdata), GFP_KERNEL); | ||
1197 | if (!pdata) | ||
1198 | return -ENOMEM; | ||
1199 | |||
1200 | if (of_get_property(np, "supports-sleepmode", NULL)) | ||
1201 | pdata->supports_sleepmode = true; | ||
1202 | |||
1203 | if (of_property_read_u32(np, "gpio-bank", &dev->id)) { | ||
1204 | dev_err(&dev->dev, "gpio-bank property not found\n"); | ||
1205 | ret = -EINVAL; | ||
1206 | goto out; | ||
1207 | } | ||
1208 | |||
1209 | pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; | ||
1210 | pdata->num_gpio = NMK_GPIO_PER_CHIP; | ||
1211 | } | ||
1084 | 1212 | ||
1085 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); | 1213 | res = platform_get_resource(dev, IORESOURCE_MEM, 0); |
1086 | if (!res) { | 1214 | if (!res) { |
@@ -1106,10 +1234,16 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) | |||
1106 | goto out; | 1234 | goto out; |
1107 | } | 1235 | } |
1108 | 1236 | ||
1237 | base = ioremap(res->start, resource_size(res)); | ||
1238 | if (!base) { | ||
1239 | ret = -ENOMEM; | ||
1240 | goto out_release; | ||
1241 | } | ||
1242 | |||
1109 | clk = clk_get(&dev->dev, NULL); | 1243 | clk = clk_get(&dev->dev, NULL); |
1110 | if (IS_ERR(clk)) { | 1244 | if (IS_ERR(clk)) { |
1111 | ret = PTR_ERR(clk); | 1245 | ret = PTR_ERR(clk); |
1112 | goto out_release; | 1246 | goto out_unmap; |
1113 | } | 1247 | } |
1114 | 1248 | ||
1115 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); | 1249 | nmk_chip = kzalloc(sizeof(*nmk_chip), GFP_KERNEL); |
@@ -1117,13 +1251,14 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) | |||
1117 | ret = -ENOMEM; | 1251 | ret = -ENOMEM; |
1118 | goto out_clk; | 1252 | goto out_clk; |
1119 | } | 1253 | } |
1254 | |||
1120 | /* | 1255 | /* |
1121 | * The virt address in nmk_chip->addr is in the nomadik register space, | 1256 | * The virt address in nmk_chip->addr is in the nomadik register space, |
1122 | * so we can simply convert the resource address, without remapping | 1257 | * so we can simply convert the resource address, without remapping |
1123 | */ | 1258 | */ |
1124 | nmk_chip->bank = dev->id; | 1259 | nmk_chip->bank = dev->id; |
1125 | nmk_chip->clk = clk; | 1260 | nmk_chip->clk = clk; |
1126 | nmk_chip->addr = io_p2v(res->start); | 1261 | nmk_chip->addr = base; |
1127 | nmk_chip->chip = nmk_gpio_template; | 1262 | nmk_chip->chip = nmk_gpio_template; |
1128 | nmk_chip->parent_irq = irq; | 1263 | nmk_chip->parent_irq = irq; |
1129 | nmk_chip->secondary_parent_irq = secondary_irq; | 1264 | nmk_chip->secondary_parent_irq = secondary_irq; |
@@ -1139,6 +1274,14 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) | |||
1139 | chip->dev = &dev->dev; | 1274 | chip->dev = &dev->dev; |
1140 | chip->owner = THIS_MODULE; | 1275 | chip->owner = THIS_MODULE; |
1141 | 1276 | ||
1277 | clk_enable(nmk_chip->clk); | ||
1278 | nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); | ||
1279 | clk_disable(nmk_chip->clk); | ||
1280 | |||
1281 | #ifdef CONFIG_OF_GPIO | ||
1282 | chip->of_node = np; | ||
1283 | #endif | ||
1284 | |||
1142 | ret = gpiochip_add(&nmk_chip->chip); | 1285 | ret = gpiochip_add(&nmk_chip->chip); |
1143 | if (ret) | 1286 | if (ret) |
1144 | goto out_free; | 1287 | goto out_free; |
@@ -1146,12 +1289,22 @@ static int __devinit nmk_gpio_probe(struct platform_device *dev) | |||
1146 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); | 1289 | BUG_ON(nmk_chip->bank >= ARRAY_SIZE(nmk_gpio_chips)); |
1147 | 1290 | ||
1148 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; | 1291 | nmk_gpio_chips[nmk_chip->bank] = nmk_chip; |
1292 | |||
1149 | platform_set_drvdata(dev, nmk_chip); | 1293 | platform_set_drvdata(dev, nmk_chip); |
1150 | 1294 | ||
1295 | nmk_chip->domain = irq_domain_add_legacy(np, NMK_GPIO_PER_CHIP, | ||
1296 | NOMADIK_GPIO_TO_IRQ(pdata->first_gpio), | ||
1297 | 0, &nmk_gpio_irq_simple_ops, nmk_chip); | ||
1298 | if (!nmk_chip->domain) { | ||
1299 | pr_err("%s: Failed to create irqdomain\n", np->full_name); | ||
1300 | ret = -ENOSYS; | ||
1301 | goto out_free; | ||
1302 | } | ||
1303 | |||
1151 | nmk_gpio_init_irq(nmk_chip); | 1304 | nmk_gpio_init_irq(nmk_chip); |
1152 | 1305 | ||
1153 | dev_info(&dev->dev, "at address %p\n", | 1306 | dev_info(&dev->dev, "at address %p\n", nmk_chip->addr); |
1154 | nmk_chip->addr); | 1307 | |
1155 | return 0; | 1308 | return 0; |
1156 | 1309 | ||
1157 | out_free: | 1310 | out_free: |
@@ -1159,25 +1312,465 @@ out_free: | |||
1159 | out_clk: | 1312 | out_clk: |
1160 | clk_disable(clk); | 1313 | clk_disable(clk); |
1161 | clk_put(clk); | 1314 | clk_put(clk); |
1315 | out_unmap: | ||
1316 | iounmap(base); | ||
1162 | out_release: | 1317 | out_release: |
1163 | release_mem_region(res->start, resource_size(res)); | 1318 | release_mem_region(res->start, resource_size(res)); |
1164 | out: | 1319 | out: |
1165 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, | 1320 | dev_err(&dev->dev, "Failure %i for GPIO %i-%i\n", ret, |
1166 | pdata->first_gpio, pdata->first_gpio+31); | 1321 | pdata->first_gpio, pdata->first_gpio+31); |
1322 | if (np) | ||
1323 | kfree(pdata); | ||
1324 | |||
1167 | return ret; | 1325 | return ret; |
1168 | } | 1326 | } |
1169 | 1327 | ||
1328 | static int nmk_get_groups_cnt(struct pinctrl_dev *pctldev) | ||
1329 | { | ||
1330 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1331 | |||
1332 | return npct->soc->ngroups; | ||
1333 | } | ||
1334 | |||
1335 | static const char *nmk_get_group_name(struct pinctrl_dev *pctldev, | ||
1336 | unsigned selector) | ||
1337 | { | ||
1338 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1339 | |||
1340 | return npct->soc->groups[selector].name; | ||
1341 | } | ||
1342 | |||
1343 | static int nmk_get_group_pins(struct pinctrl_dev *pctldev, unsigned selector, | ||
1344 | const unsigned **pins, | ||
1345 | unsigned *num_pins) | ||
1346 | { | ||
1347 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1348 | |||
1349 | *pins = npct->soc->groups[selector].pins; | ||
1350 | *num_pins = npct->soc->groups[selector].npins; | ||
1351 | return 0; | ||
1352 | } | ||
1353 | |||
1354 | static struct pinctrl_gpio_range * | ||
1355 | nmk_match_gpio_range(struct pinctrl_dev *pctldev, unsigned offset) | ||
1356 | { | ||
1357 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1358 | int i; | ||
1359 | |||
1360 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | ||
1361 | struct pinctrl_gpio_range *range; | ||
1362 | |||
1363 | range = &npct->soc->gpio_ranges[i]; | ||
1364 | if (offset >= range->pin_base && | ||
1365 | offset <= (range->pin_base + range->npins - 1)) | ||
1366 | return range; | ||
1367 | } | ||
1368 | return NULL; | ||
1369 | } | ||
1370 | |||
1371 | static void nmk_pin_dbg_show(struct pinctrl_dev *pctldev, struct seq_file *s, | ||
1372 | unsigned offset) | ||
1373 | { | ||
1374 | struct pinctrl_gpio_range *range; | ||
1375 | struct gpio_chip *chip; | ||
1376 | |||
1377 | range = nmk_match_gpio_range(pctldev, offset); | ||
1378 | if (!range || !range->gc) { | ||
1379 | seq_printf(s, "invalid pin offset"); | ||
1380 | return; | ||
1381 | } | ||
1382 | chip = range->gc; | ||
1383 | nmk_gpio_dbg_show_one(s, chip, offset - chip->base, offset); | ||
1384 | } | ||
1385 | |||
1386 | static struct pinctrl_ops nmk_pinctrl_ops = { | ||
1387 | .get_groups_count = nmk_get_groups_cnt, | ||
1388 | .get_group_name = nmk_get_group_name, | ||
1389 | .get_group_pins = nmk_get_group_pins, | ||
1390 | .pin_dbg_show = nmk_pin_dbg_show, | ||
1391 | }; | ||
1392 | |||
1393 | static int nmk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev) | ||
1394 | { | ||
1395 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1396 | |||
1397 | return npct->soc->nfunctions; | ||
1398 | } | ||
1399 | |||
1400 | static const char *nmk_pmx_get_func_name(struct pinctrl_dev *pctldev, | ||
1401 | unsigned function) | ||
1402 | { | ||
1403 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1404 | |||
1405 | return npct->soc->functions[function].name; | ||
1406 | } | ||
1407 | |||
1408 | static int nmk_pmx_get_func_groups(struct pinctrl_dev *pctldev, | ||
1409 | unsigned function, | ||
1410 | const char * const **groups, | ||
1411 | unsigned * const num_groups) | ||
1412 | { | ||
1413 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1414 | |||
1415 | *groups = npct->soc->functions[function].groups; | ||
1416 | *num_groups = npct->soc->functions[function].ngroups; | ||
1417 | |||
1418 | return 0; | ||
1419 | } | ||
1420 | |||
1421 | static int nmk_pmx_enable(struct pinctrl_dev *pctldev, unsigned function, | ||
1422 | unsigned group) | ||
1423 | { | ||
1424 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1425 | const struct nmk_pingroup *g; | ||
1426 | static unsigned int slpm[NUM_BANKS]; | ||
1427 | unsigned long flags; | ||
1428 | bool glitch; | ||
1429 | int ret = -EINVAL; | ||
1430 | int i; | ||
1431 | |||
1432 | g = &npct->soc->groups[group]; | ||
1433 | |||
1434 | if (g->altsetting < 0) | ||
1435 | return -EINVAL; | ||
1436 | |||
1437 | dev_dbg(npct->dev, "enable group %s, %u pins\n", g->name, g->npins); | ||
1438 | |||
1439 | /* Handle this special glitch on altfunction C */ | ||
1440 | glitch = (g->altsetting == NMK_GPIO_ALT_C); | ||
1441 | |||
1442 | if (glitch) { | ||
1443 | spin_lock_irqsave(&nmk_gpio_slpm_lock, flags); | ||
1444 | |||
1445 | /* Initially don't put any pins to sleep when switching */ | ||
1446 | memset(slpm, 0xff, sizeof(slpm)); | ||
1447 | |||
1448 | /* | ||
1449 | * Then mask the pins that need to be sleeping now when we're | ||
1450 | * switching to the ALT C function. | ||
1451 | */ | ||
1452 | for (i = 0; i < g->npins; i++) | ||
1453 | slpm[g->pins[i] / NMK_GPIO_PER_CHIP] &= ~BIT(g->pins[i]); | ||
1454 | nmk_gpio_glitch_slpm_init(slpm); | ||
1455 | } | ||
1456 | |||
1457 | for (i = 0; i < g->npins; i++) { | ||
1458 | struct pinctrl_gpio_range *range; | ||
1459 | struct nmk_gpio_chip *nmk_chip; | ||
1460 | struct gpio_chip *chip; | ||
1461 | unsigned bit; | ||
1462 | |||
1463 | range = nmk_match_gpio_range(pctldev, g->pins[i]); | ||
1464 | if (!range) { | ||
1465 | dev_err(npct->dev, | ||
1466 | "invalid pin offset %d in group %s at index %d\n", | ||
1467 | g->pins[i], g->name, i); | ||
1468 | goto out_glitch; | ||
1469 | } | ||
1470 | if (!range->gc) { | ||
1471 | dev_err(npct->dev, "GPIO chip missing in range for pin offset %d in group %s at index %d\n", | ||
1472 | g->pins[i], g->name, i); | ||
1473 | goto out_glitch; | ||
1474 | } | ||
1475 | chip = range->gc; | ||
1476 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | ||
1477 | dev_dbg(npct->dev, "setting pin %d to altsetting %d\n", g->pins[i], g->altsetting); | ||
1478 | |||
1479 | clk_enable(nmk_chip->clk); | ||
1480 | bit = g->pins[i] % NMK_GPIO_PER_CHIP; | ||
1481 | /* | ||
1482 | * If the pin is switching to altfunc, and there was an | ||
1483 | * interrupt installed on it which has been lazy disabled, | ||
1484 | * actually mask the interrupt to prevent spurious interrupts | ||
1485 | * that would occur while the pin is under control of the | ||
1486 | * peripheral. Only SKE does this. | ||
1487 | */ | ||
1488 | nmk_gpio_disable_lazy_irq(nmk_chip, bit); | ||
1489 | |||
1490 | __nmk_gpio_set_mode_safe(nmk_chip, bit, g->altsetting, glitch); | ||
1491 | clk_disable(nmk_chip->clk); | ||
1492 | } | ||
1493 | |||
1494 | /* When all pins are successfully reconfigured we get here */ | ||
1495 | ret = 0; | ||
1496 | |||
1497 | out_glitch: | ||
1498 | if (glitch) { | ||
1499 | nmk_gpio_glitch_slpm_restore(slpm); | ||
1500 | spin_unlock_irqrestore(&nmk_gpio_slpm_lock, flags); | ||
1501 | } | ||
1502 | |||
1503 | return ret; | ||
1504 | } | ||
1505 | |||
1506 | static void nmk_pmx_disable(struct pinctrl_dev *pctldev, | ||
1507 | unsigned function, unsigned group) | ||
1508 | { | ||
1509 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1510 | const struct nmk_pingroup *g; | ||
1511 | |||
1512 | g = &npct->soc->groups[group]; | ||
1513 | |||
1514 | if (g->altsetting < 0) | ||
1515 | return; | ||
1516 | |||
1517 | /* Poke out the mux, set the pin to some default state? */ | ||
1518 | dev_dbg(npct->dev, "disable group %s, %u pins\n", g->name, g->npins); | ||
1519 | } | ||
1520 | |||
1521 | int nmk_gpio_request_enable(struct pinctrl_dev *pctldev, | ||
1522 | struct pinctrl_gpio_range *range, | ||
1523 | unsigned offset) | ||
1524 | { | ||
1525 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1526 | struct nmk_gpio_chip *nmk_chip; | ||
1527 | struct gpio_chip *chip; | ||
1528 | unsigned bit; | ||
1529 | |||
1530 | if (!range) { | ||
1531 | dev_err(npct->dev, "invalid range\n"); | ||
1532 | return -EINVAL; | ||
1533 | } | ||
1534 | if (!range->gc) { | ||
1535 | dev_err(npct->dev, "missing GPIO chip in range\n"); | ||
1536 | return -EINVAL; | ||
1537 | } | ||
1538 | chip = range->gc; | ||
1539 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | ||
1540 | |||
1541 | dev_dbg(npct->dev, "enable pin %u as GPIO\n", offset); | ||
1542 | |||
1543 | clk_enable(nmk_chip->clk); | ||
1544 | bit = offset % NMK_GPIO_PER_CHIP; | ||
1545 | /* There is no glitch when converting any pin to GPIO */ | ||
1546 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | ||
1547 | clk_disable(nmk_chip->clk); | ||
1548 | |||
1549 | return 0; | ||
1550 | } | ||
1551 | |||
1552 | void nmk_gpio_disable_free(struct pinctrl_dev *pctldev, | ||
1553 | struct pinctrl_gpio_range *range, | ||
1554 | unsigned offset) | ||
1555 | { | ||
1556 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1557 | |||
1558 | dev_dbg(npct->dev, "disable pin %u as GPIO\n", offset); | ||
1559 | /* Set the pin to some default state, GPIO is usually default */ | ||
1560 | } | ||
1561 | |||
1562 | static struct pinmux_ops nmk_pinmux_ops = { | ||
1563 | .get_functions_count = nmk_pmx_get_funcs_cnt, | ||
1564 | .get_function_name = nmk_pmx_get_func_name, | ||
1565 | .get_function_groups = nmk_pmx_get_func_groups, | ||
1566 | .enable = nmk_pmx_enable, | ||
1567 | .disable = nmk_pmx_disable, | ||
1568 | .gpio_request_enable = nmk_gpio_request_enable, | ||
1569 | .gpio_disable_free = nmk_gpio_disable_free, | ||
1570 | }; | ||
1571 | |||
1572 | int nmk_pin_config_get(struct pinctrl_dev *pctldev, | ||
1573 | unsigned pin, | ||
1574 | unsigned long *config) | ||
1575 | { | ||
1576 | /* Not implemented */ | ||
1577 | return -EINVAL; | ||
1578 | } | ||
1579 | |||
1580 | int nmk_pin_config_set(struct pinctrl_dev *pctldev, | ||
1581 | unsigned pin, | ||
1582 | unsigned long config) | ||
1583 | { | ||
1584 | static const char *pullnames[] = { | ||
1585 | [NMK_GPIO_PULL_NONE] = "none", | ||
1586 | [NMK_GPIO_PULL_UP] = "up", | ||
1587 | [NMK_GPIO_PULL_DOWN] = "down", | ||
1588 | [3] /* illegal */ = "??" | ||
1589 | }; | ||
1590 | static const char *slpmnames[] = { | ||
1591 | [NMK_GPIO_SLPM_INPUT] = "input/wakeup", | ||
1592 | [NMK_GPIO_SLPM_NOCHANGE] = "no-change/no-wakeup", | ||
1593 | }; | ||
1594 | struct nmk_pinctrl *npct = pinctrl_dev_get_drvdata(pctldev); | ||
1595 | struct nmk_gpio_chip *nmk_chip; | ||
1596 | struct pinctrl_gpio_range *range; | ||
1597 | struct gpio_chip *chip; | ||
1598 | unsigned bit; | ||
1599 | |||
1600 | /* | ||
1601 | * The pin config contains pin number and altfunction fields, here | ||
1602 | * we just ignore that part. It's being handled by the framework and | ||
1603 | * pinmux callback respectively. | ||
1604 | */ | ||
1605 | pin_cfg_t cfg = (pin_cfg_t) config; | ||
1606 | int pull = PIN_PULL(cfg); | ||
1607 | int slpm = PIN_SLPM(cfg); | ||
1608 | int output = PIN_DIR(cfg); | ||
1609 | int val = PIN_VAL(cfg); | ||
1610 | bool lowemi = PIN_LOWEMI(cfg); | ||
1611 | bool gpiomode = PIN_GPIOMODE(cfg); | ||
1612 | bool sleep = PIN_SLEEPMODE(cfg); | ||
1613 | |||
1614 | range = nmk_match_gpio_range(pctldev, pin); | ||
1615 | if (!range) { | ||
1616 | dev_err(npct->dev, "invalid pin offset %d\n", pin); | ||
1617 | return -EINVAL; | ||
1618 | } | ||
1619 | if (!range->gc) { | ||
1620 | dev_err(npct->dev, "GPIO chip missing in range for pin %d\n", | ||
1621 | pin); | ||
1622 | return -EINVAL; | ||
1623 | } | ||
1624 | chip = range->gc; | ||
1625 | nmk_chip = container_of(chip, struct nmk_gpio_chip, chip); | ||
1626 | |||
1627 | if (sleep) { | ||
1628 | int slpm_pull = PIN_SLPM_PULL(cfg); | ||
1629 | int slpm_output = PIN_SLPM_DIR(cfg); | ||
1630 | int slpm_val = PIN_SLPM_VAL(cfg); | ||
1631 | |||
1632 | /* All pins go into GPIO mode at sleep */ | ||
1633 | gpiomode = true; | ||
1634 | |||
1635 | /* | ||
1636 | * The SLPM_* values are normal values + 1 to allow zero to | ||
1637 | * mean "same as normal". | ||
1638 | */ | ||
1639 | if (slpm_pull) | ||
1640 | pull = slpm_pull - 1; | ||
1641 | if (slpm_output) | ||
1642 | output = slpm_output - 1; | ||
1643 | if (slpm_val) | ||
1644 | val = slpm_val - 1; | ||
1645 | |||
1646 | dev_dbg(nmk_chip->chip.dev, "pin %d: sleep pull %s, dir %s, val %s\n", | ||
1647 | pin, | ||
1648 | slpm_pull ? pullnames[pull] : "same", | ||
1649 | slpm_output ? (output ? "output" : "input") : "same", | ||
1650 | slpm_val ? (val ? "high" : "low") : "same"); | ||
1651 | } | ||
1652 | |||
1653 | dev_dbg(nmk_chip->chip.dev, "pin %d [%#lx]: pull %s, slpm %s (%s%s), lowemi %s\n", | ||
1654 | pin, cfg, pullnames[pull], slpmnames[slpm], | ||
1655 | output ? "output " : "input", | ||
1656 | output ? (val ? "high" : "low") : "", | ||
1657 | lowemi ? "on" : "off" ); | ||
1658 | |||
1659 | clk_enable(nmk_chip->clk); | ||
1660 | bit = pin % NMK_GPIO_PER_CHIP; | ||
1661 | if (gpiomode) | ||
1662 | /* No glitch when going to GPIO mode */ | ||
1663 | __nmk_gpio_set_mode(nmk_chip, bit, NMK_GPIO_ALT_GPIO); | ||
1664 | if (output) | ||
1665 | __nmk_gpio_make_output(nmk_chip, bit, val); | ||
1666 | else { | ||
1667 | __nmk_gpio_make_input(nmk_chip, bit); | ||
1668 | __nmk_gpio_set_pull(nmk_chip, bit, pull); | ||
1669 | } | ||
1670 | /* TODO: isn't this only applicable on output pins? */ | ||
1671 | __nmk_gpio_set_lowemi(nmk_chip, bit, lowemi); | ||
1672 | |||
1673 | __nmk_gpio_set_slpm(nmk_chip, bit, slpm); | ||
1674 | clk_disable(nmk_chip->clk); | ||
1675 | return 0; | ||
1676 | } | ||
1677 | |||
1678 | static struct pinconf_ops nmk_pinconf_ops = { | ||
1679 | .pin_config_get = nmk_pin_config_get, | ||
1680 | .pin_config_set = nmk_pin_config_set, | ||
1681 | }; | ||
1682 | |||
1683 | static struct pinctrl_desc nmk_pinctrl_desc = { | ||
1684 | .name = "pinctrl-nomadik", | ||
1685 | .pctlops = &nmk_pinctrl_ops, | ||
1686 | .pmxops = &nmk_pinmux_ops, | ||
1687 | .confops = &nmk_pinconf_ops, | ||
1688 | .owner = THIS_MODULE, | ||
1689 | }; | ||
1690 | |||
1691 | static int __devinit nmk_pinctrl_probe(struct platform_device *pdev) | ||
1692 | { | ||
1693 | const struct platform_device_id *platid = platform_get_device_id(pdev); | ||
1694 | struct nmk_pinctrl *npct; | ||
1695 | int i; | ||
1696 | |||
1697 | npct = devm_kzalloc(&pdev->dev, sizeof(*npct), GFP_KERNEL); | ||
1698 | if (!npct) | ||
1699 | return -ENOMEM; | ||
1700 | |||
1701 | /* Poke in other ASIC variants here */ | ||
1702 | if (platid->driver_data == PINCTRL_NMK_DB8500) | ||
1703 | nmk_pinctrl_db8500_init(&npct->soc); | ||
1704 | |||
1705 | /* | ||
1706 | * We need all the GPIO drivers to probe FIRST, or we will not be able | ||
1707 | * to obtain references to the struct gpio_chip * for them, and we | ||
1708 | * need this to proceed. | ||
1709 | */ | ||
1710 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) { | ||
1711 | if (!nmk_gpio_chips[i]) { | ||
1712 | dev_warn(&pdev->dev, "GPIO chip %d not registered yet\n", i); | ||
1713 | devm_kfree(&pdev->dev, npct); | ||
1714 | return -EPROBE_DEFER; | ||
1715 | } | ||
1716 | npct->soc->gpio_ranges[i].gc = &nmk_gpio_chips[i]->chip; | ||
1717 | } | ||
1718 | |||
1719 | nmk_pinctrl_desc.pins = npct->soc->pins; | ||
1720 | nmk_pinctrl_desc.npins = npct->soc->npins; | ||
1721 | npct->dev = &pdev->dev; | ||
1722 | npct->pctl = pinctrl_register(&nmk_pinctrl_desc, &pdev->dev, npct); | ||
1723 | if (!npct->pctl) { | ||
1724 | dev_err(&pdev->dev, "could not register Nomadik pinctrl driver\n"); | ||
1725 | return -EINVAL; | ||
1726 | } | ||
1727 | |||
1728 | /* We will handle a range of GPIO pins */ | ||
1729 | for (i = 0; i < npct->soc->gpio_num_ranges; i++) | ||
1730 | pinctrl_add_gpio_range(npct->pctl, &npct->soc->gpio_ranges[i]); | ||
1731 | |||
1732 | platform_set_drvdata(pdev, npct); | ||
1733 | dev_info(&pdev->dev, "initialized Nomadik pin control driver\n"); | ||
1734 | |||
1735 | return 0; | ||
1736 | } | ||
1737 | |||
1738 | static const struct of_device_id nmk_gpio_match[] = { | ||
1739 | { .compatible = "st,nomadik-gpio", }, | ||
1740 | {} | ||
1741 | }; | ||
1742 | |||
1170 | static struct platform_driver nmk_gpio_driver = { | 1743 | static struct platform_driver nmk_gpio_driver = { |
1171 | .driver = { | 1744 | .driver = { |
1172 | .owner = THIS_MODULE, | 1745 | .owner = THIS_MODULE, |
1173 | .name = "gpio", | 1746 | .name = "gpio", |
1747 | .of_match_table = nmk_gpio_match, | ||
1174 | }, | 1748 | }, |
1175 | .probe = nmk_gpio_probe, | 1749 | .probe = nmk_gpio_probe, |
1176 | }; | 1750 | }; |
1177 | 1751 | ||
1752 | static const struct platform_device_id nmk_pinctrl_id[] = { | ||
1753 | { "pinctrl-stn8815", PINCTRL_NMK_STN8815 }, | ||
1754 | { "pinctrl-db8500", PINCTRL_NMK_DB8500 }, | ||
1755 | }; | ||
1756 | |||
1757 | static struct platform_driver nmk_pinctrl_driver = { | ||
1758 | .driver = { | ||
1759 | .owner = THIS_MODULE, | ||
1760 | .name = "pinctrl-nomadik", | ||
1761 | }, | ||
1762 | .probe = nmk_pinctrl_probe, | ||
1763 | .id_table = nmk_pinctrl_id, | ||
1764 | }; | ||
1765 | |||
1178 | static int __init nmk_gpio_init(void) | 1766 | static int __init nmk_gpio_init(void) |
1179 | { | 1767 | { |
1180 | return platform_driver_register(&nmk_gpio_driver); | 1768 | int ret; |
1769 | |||
1770 | ret = platform_driver_register(&nmk_gpio_driver); | ||
1771 | if (ret) | ||
1772 | return ret; | ||
1773 | return platform_driver_register(&nmk_pinctrl_driver); | ||
1181 | } | 1774 | } |
1182 | 1775 | ||
1183 | core_initcall(nmk_gpio_init); | 1776 | core_initcall(nmk_gpio_init); |
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h new file mode 100644 index 000000000000..bc91aed7185d --- /dev/null +++ b/drivers/pinctrl/pinctrl-nomadik.h | |||
@@ -0,0 +1,77 @@ | |||
1 | #ifndef PINCTRL_PINCTRL_NOMADIK_H | ||
2 | #define PINCTRL_PINCTRL_NOMADIK_H | ||
3 | |||
4 | #include <plat/gpio-nomadik.h> | ||
5 | |||
6 | /* Package definitions */ | ||
7 | #define PINCTRL_NMK_STN8815 0 | ||
8 | #define PINCTRL_NMK_DB8500 1 | ||
9 | |||
10 | /** | ||
11 | * struct nmk_function - Nomadik pinctrl mux function | ||
12 | * @name: The name of the function, exported to pinctrl core. | ||
13 | * @groups: An array of pin groups that may select this function. | ||
14 | * @ngroups: The number of entries in @groups. | ||
15 | */ | ||
16 | struct nmk_function { | ||
17 | const char *name; | ||
18 | const char * const *groups; | ||
19 | unsigned ngroups; | ||
20 | }; | ||
21 | |||
22 | /** | ||
23 | * struct nmk_pingroup - describes a Nomadik pin group | ||
24 | * @name: the name of this specific pin group | ||
25 | * @pins: an array of discrete physical pins used in this group, taken | ||
26 | * from the driver-local pin enumeration space | ||
27 | * @num_pins: the number of pins in this group array, i.e. the number of | ||
28 | * elements in .pins so we can iterate over that array | ||
29 | * @altsetting: the altsetting to apply to all pins in this group to | ||
30 | * configure them to be used by a function | ||
31 | */ | ||
32 | struct nmk_pingroup { | ||
33 | const char *name; | ||
34 | const unsigned int *pins; | ||
35 | const unsigned npins; | ||
36 | int altsetting; | ||
37 | }; | ||
38 | |||
39 | /** | ||
40 | * struct nmk_pinctrl_soc_data - Nomadik pin controller per-SoC configuration | ||
41 | * @gpio_ranges: An array of GPIO ranges for this SoC | ||
42 | * @gpio_num_ranges: The number of GPIO ranges for this SoC | ||
43 | * @pins: An array describing all pins the pin controller affects. | ||
44 | * All pins which are also GPIOs must be listed first within the | ||
45 | * array, and be numbered identically to the GPIO controller's | ||
46 | * numbering. | ||
47 | * @npins: The number of entries in @pins. | ||
48 | * @functions: The functions supported on this SoC. | ||
49 | * @nfunction: The number of entries in @functions. | ||
50 | * @groups: An array describing all pin groups the pin SoC supports. | ||
51 | * @ngroups: The number of entries in @groups. | ||
52 | */ | ||
53 | struct nmk_pinctrl_soc_data { | ||
54 | struct pinctrl_gpio_range *gpio_ranges; | ||
55 | unsigned gpio_num_ranges; | ||
56 | const struct pinctrl_pin_desc *pins; | ||
57 | unsigned npins; | ||
58 | const struct nmk_function *functions; | ||
59 | unsigned nfunctions; | ||
60 | const struct nmk_pingroup *groups; | ||
61 | unsigned ngroups; | ||
62 | }; | ||
63 | |||
64 | #ifdef CONFIG_PINCTRL_DB8500 | ||
65 | |||
66 | void nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc); | ||
67 | |||
68 | #else | ||
69 | |||
70 | static inline void | ||
71 | nmk_pinctrl_db8500_init(const struct nmk_pinctrl_soc_data **soc) | ||
72 | { | ||
73 | } | ||
74 | |||
75 | #endif | ||
76 | |||
77 | #endif /* PINCTRL_PINCTRL_NOMADIK_H */ | ||
diff --git a/drivers/pinctrl/pinctrl-tegra.c b/drivers/pinctrl/pinctrl-tegra.c index 2c98fba01ca5..b6934867d8d3 100644 --- a/drivers/pinctrl/pinctrl-tegra.c +++ b/drivers/pinctrl/pinctrl-tegra.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Driver for the NVIDIA Tegra pinmux | 2 | * Driver for the NVIDIA Tegra pinmux |
3 | * | 3 | * |
4 | * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Derived from code: | 6 | * Derived from code: |
7 | * Copyright (C) 2010 Google, Inc. | 7 | * Copyright (C) 2010 Google, Inc. |
@@ -22,7 +22,8 @@ | |||
22 | #include <linux/init.h> | 22 | #include <linux/init.h> |
23 | #include <linux/io.h> | 23 | #include <linux/io.h> |
24 | #include <linux/module.h> | 24 | #include <linux/module.h> |
25 | #include <linux/of_device.h> | 25 | #include <linux/of.h> |
26 | #include <linux/platform_device.h> | ||
26 | #include <linux/pinctrl/machine.h> | 27 | #include <linux/pinctrl/machine.h> |
27 | #include <linux/pinctrl/pinctrl.h> | 28 | #include <linux/pinctrl/pinctrl.h> |
28 | #include <linux/pinctrl/pinmux.h> | 29 | #include <linux/pinctrl/pinmux.h> |
@@ -31,10 +32,9 @@ | |||
31 | 32 | ||
32 | #include <mach/pinconf-tegra.h> | 33 | #include <mach/pinconf-tegra.h> |
33 | 34 | ||
35 | #include "core.h" | ||
34 | #include "pinctrl-tegra.h" | 36 | #include "pinctrl-tegra.h" |
35 | 37 | ||
36 | #define DRIVER_NAME "tegra-pinmux-disabled" | ||
37 | |||
38 | struct tegra_pmx { | 38 | struct tegra_pmx { |
39 | struct device *dev; | 39 | struct device *dev; |
40 | struct pinctrl_dev *pctl; | 40 | struct pinctrl_dev *pctl; |
@@ -83,15 +83,18 @@ static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | |||
83 | return 0; | 83 | return 0; |
84 | } | 84 | } |
85 | 85 | ||
86 | #ifdef CONFIG_DEBUG_FS | ||
86 | static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, | 87 | static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, |
87 | struct seq_file *s, | 88 | struct seq_file *s, |
88 | unsigned offset) | 89 | unsigned offset) |
89 | { | 90 | { |
90 | seq_printf(s, " " DRIVER_NAME); | 91 | seq_printf(s, " %s", dev_name(pctldev->dev)); |
91 | } | 92 | } |
93 | #endif | ||
92 | 94 | ||
93 | static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, | 95 | static int reserve_map(struct device *dev, struct pinctrl_map **map, |
94 | unsigned *num_maps, unsigned reserve) | 96 | unsigned *reserved_maps, unsigned *num_maps, |
97 | unsigned reserve) | ||
95 | { | 98 | { |
96 | unsigned old_num = *reserved_maps; | 99 | unsigned old_num = *reserved_maps; |
97 | unsigned new_num = *num_maps + reserve; | 100 | unsigned new_num = *num_maps + reserve; |
@@ -101,8 +104,10 @@ static int reserve_map(struct pinctrl_map **map, unsigned *reserved_maps, | |||
101 | return 0; | 104 | return 0; |
102 | 105 | ||
103 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); | 106 | new_map = krealloc(*map, sizeof(*new_map) * new_num, GFP_KERNEL); |
104 | if (!new_map) | 107 | if (!new_map) { |
108 | dev_err(dev, "krealloc(map) failed\n"); | ||
105 | return -ENOMEM; | 109 | return -ENOMEM; |
110 | } | ||
106 | 111 | ||
107 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); | 112 | memset(new_map + old_num, 0, (new_num - old_num) * sizeof(*new_map)); |
108 | 113 | ||
@@ -116,7 +121,7 @@ static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, | |||
116 | unsigned *num_maps, const char *group, | 121 | unsigned *num_maps, const char *group, |
117 | const char *function) | 122 | const char *function) |
118 | { | 123 | { |
119 | if (*num_maps == *reserved_maps) | 124 | if (WARN_ON(*num_maps == *reserved_maps)) |
120 | return -ENOSPC; | 125 | return -ENOSPC; |
121 | 126 | ||
122 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; | 127 | (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP; |
@@ -127,19 +132,22 @@ static int add_map_mux(struct pinctrl_map **map, unsigned *reserved_maps, | |||
127 | return 0; | 132 | return 0; |
128 | } | 133 | } |
129 | 134 | ||
130 | static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps, | 135 | static int add_map_configs(struct device *dev, struct pinctrl_map **map, |
131 | unsigned *num_maps, const char *group, | 136 | unsigned *reserved_maps, unsigned *num_maps, |
132 | unsigned long *configs, unsigned num_configs) | 137 | const char *group, unsigned long *configs, |
138 | unsigned num_configs) | ||
133 | { | 139 | { |
134 | unsigned long *dup_configs; | 140 | unsigned long *dup_configs; |
135 | 141 | ||
136 | if (*num_maps == *reserved_maps) | 142 | if (WARN_ON(*num_maps == *reserved_maps)) |
137 | return -ENOSPC; | 143 | return -ENOSPC; |
138 | 144 | ||
139 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), | 145 | dup_configs = kmemdup(configs, num_configs * sizeof(*dup_configs), |
140 | GFP_KERNEL); | 146 | GFP_KERNEL); |
141 | if (!dup_configs) | 147 | if (!dup_configs) { |
148 | dev_err(dev, "kmemdup(configs) failed\n"); | ||
142 | return -ENOMEM; | 149 | return -ENOMEM; |
150 | } | ||
143 | 151 | ||
144 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; | 152 | (*map)[*num_maps].type = PIN_MAP_TYPE_CONFIGS_GROUP; |
145 | (*map)[*num_maps].data.configs.group_or_pin = group; | 153 | (*map)[*num_maps].data.configs.group_or_pin = group; |
@@ -150,8 +158,8 @@ static int add_map_configs(struct pinctrl_map **map, unsigned *reserved_maps, | |||
150 | return 0; | 158 | return 0; |
151 | } | 159 | } |
152 | 160 | ||
153 | static int add_config(unsigned long **configs, unsigned *num_configs, | 161 | static int add_config(struct device *dev, unsigned long **configs, |
154 | unsigned long config) | 162 | unsigned *num_configs, unsigned long config) |
155 | { | 163 | { |
156 | unsigned old_num = *num_configs; | 164 | unsigned old_num = *num_configs; |
157 | unsigned new_num = old_num + 1; | 165 | unsigned new_num = old_num + 1; |
@@ -159,8 +167,10 @@ static int add_config(unsigned long **configs, unsigned *num_configs, | |||
159 | 167 | ||
160 | new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, | 168 | new_configs = krealloc(*configs, sizeof(*new_configs) * new_num, |
161 | GFP_KERNEL); | 169 | GFP_KERNEL); |
162 | if (!new_configs) | 170 | if (!new_configs) { |
171 | dev_err(dev, "krealloc(configs) failed\n"); | ||
163 | return -ENOMEM; | 172 | return -ENOMEM; |
173 | } | ||
164 | 174 | ||
165 | new_configs[old_num] = config; | 175 | new_configs[old_num] = config; |
166 | 176 | ||
@@ -201,7 +211,8 @@ static const struct cfg_param { | |||
201 | {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, | 211 | {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING}, |
202 | }; | 212 | }; |
203 | 213 | ||
204 | int tegra_pinctrl_dt_subnode_to_map(struct device_node *np, | 214 | int tegra_pinctrl_dt_subnode_to_map(struct device *dev, |
215 | struct device_node *np, | ||
205 | struct pinctrl_map **map, | 216 | struct pinctrl_map **map, |
206 | unsigned *reserved_maps, | 217 | unsigned *reserved_maps, |
207 | unsigned *num_maps) | 218 | unsigned *num_maps) |
@@ -217,16 +228,25 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np, | |||
217 | const char *group; | 228 | const char *group; |
218 | 229 | ||
219 | ret = of_property_read_string(np, "nvidia,function", &function); | 230 | ret = of_property_read_string(np, "nvidia,function", &function); |
220 | if (ret < 0) | 231 | if (ret < 0) { |
232 | /* EINVAL=missing, which is fine since it's optional */ | ||
233 | if (ret != -EINVAL) | ||
234 | dev_err(dev, | ||
235 | "could not parse property nvidia,function\n"); | ||
221 | function = NULL; | 236 | function = NULL; |
237 | } | ||
222 | 238 | ||
223 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | 239 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { |
224 | ret = of_property_read_u32(np, cfg_params[i].property, &val); | 240 | ret = of_property_read_u32(np, cfg_params[i].property, &val); |
225 | if (!ret) { | 241 | if (!ret) { |
226 | config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); | 242 | config = TEGRA_PINCONF_PACK(cfg_params[i].param, val); |
227 | ret = add_config(&configs, &num_configs, config); | 243 | ret = add_config(dev, &configs, &num_configs, config); |
228 | if (ret < 0) | 244 | if (ret < 0) |
229 | goto exit; | 245 | goto exit; |
246 | /* EINVAL=missing, which is fine since it's optional */ | ||
247 | } else if (ret != -EINVAL) { | ||
248 | dev_err(dev, "could not parse property %s\n", | ||
249 | cfg_params[i].property); | ||
230 | } | 250 | } |
231 | } | 251 | } |
232 | 252 | ||
@@ -236,11 +256,13 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np, | |||
236 | if (num_configs) | 256 | if (num_configs) |
237 | reserve++; | 257 | reserve++; |
238 | ret = of_property_count_strings(np, "nvidia,pins"); | 258 | ret = of_property_count_strings(np, "nvidia,pins"); |
239 | if (ret < 0) | 259 | if (ret < 0) { |
260 | dev_err(dev, "could not parse property nvidia,pins\n"); | ||
240 | goto exit; | 261 | goto exit; |
262 | } | ||
241 | reserve *= ret; | 263 | reserve *= ret; |
242 | 264 | ||
243 | ret = reserve_map(map, reserved_maps, num_maps, reserve); | 265 | ret = reserve_map(dev, map, reserved_maps, num_maps, reserve); |
244 | if (ret < 0) | 266 | if (ret < 0) |
245 | goto exit; | 267 | goto exit; |
246 | 268 | ||
@@ -253,8 +275,9 @@ int tegra_pinctrl_dt_subnode_to_map(struct device_node *np, | |||
253 | } | 275 | } |
254 | 276 | ||
255 | if (num_configs) { | 277 | if (num_configs) { |
256 | ret = add_map_configs(map, reserved_maps, num_maps, | 278 | ret = add_map_configs(dev, map, reserved_maps, |
257 | group, configs, num_configs); | 279 | num_maps, group, configs, |
280 | num_configs); | ||
258 | if (ret < 0) | 281 | if (ret < 0) |
259 | goto exit; | 282 | goto exit; |
260 | } | 283 | } |
@@ -280,8 +303,8 @@ int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | |||
280 | *num_maps = 0; | 303 | *num_maps = 0; |
281 | 304 | ||
282 | for_each_child_of_node(np_config, np) { | 305 | for_each_child_of_node(np_config, np) { |
283 | ret = tegra_pinctrl_dt_subnode_to_map(np, map, &reserved_maps, | 306 | ret = tegra_pinctrl_dt_subnode_to_map(pctldev->dev, np, map, |
284 | num_maps); | 307 | &reserved_maps, num_maps); |
285 | if (ret < 0) { | 308 | if (ret < 0) { |
286 | tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps); | 309 | tegra_pinctrl_dt_free_map(pctldev, *map, *num_maps); |
287 | return ret; | 310 | return ret; |
@@ -295,7 +318,9 @@ static struct pinctrl_ops tegra_pinctrl_ops = { | |||
295 | .get_groups_count = tegra_pinctrl_get_groups_count, | 318 | .get_groups_count = tegra_pinctrl_get_groups_count, |
296 | .get_group_name = tegra_pinctrl_get_group_name, | 319 | .get_group_name = tegra_pinctrl_get_group_name, |
297 | .get_group_pins = tegra_pinctrl_get_group_pins, | 320 | .get_group_pins = tegra_pinctrl_get_group_pins, |
321 | #ifdef CONFIG_DEBUG_FS | ||
298 | .pin_dbg_show = tegra_pinctrl_pin_dbg_show, | 322 | .pin_dbg_show = tegra_pinctrl_pin_dbg_show, |
323 | #endif | ||
299 | .dt_node_to_map = tegra_pinctrl_dt_node_to_map, | 324 | .dt_node_to_map = tegra_pinctrl_dt_node_to_map, |
300 | .dt_free_map = tegra_pinctrl_dt_free_map, | 325 | .dt_free_map = tegra_pinctrl_dt_free_map, |
301 | }; | 326 | }; |
@@ -338,14 +363,14 @@ static int tegra_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, | |||
338 | 363 | ||
339 | g = &pmx->soc->groups[group]; | 364 | g = &pmx->soc->groups[group]; |
340 | 365 | ||
341 | if (g->mux_reg < 0) | 366 | if (WARN_ON(g->mux_reg < 0)) |
342 | return -EINVAL; | 367 | return -EINVAL; |
343 | 368 | ||
344 | for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { | 369 | for (i = 0; i < ARRAY_SIZE(g->funcs); i++) { |
345 | if (g->funcs[i] == function) | 370 | if (g->funcs[i] == function) |
346 | break; | 371 | break; |
347 | } | 372 | } |
348 | if (i == ARRAY_SIZE(g->funcs)) | 373 | if (WARN_ON(i == ARRAY_SIZE(g->funcs))) |
349 | return -EINVAL; | 374 | return -EINVAL; |
350 | 375 | ||
351 | val = pmx_readl(pmx, g->mux_bank, g->mux_reg); | 376 | val = pmx_readl(pmx, g->mux_bank, g->mux_reg); |
@@ -365,7 +390,7 @@ static void tegra_pinctrl_disable(struct pinctrl_dev *pctldev, | |||
365 | 390 | ||
366 | g = &pmx->soc->groups[group]; | 391 | g = &pmx->soc->groups[group]; |
367 | 392 | ||
368 | if (g->mux_reg < 0) | 393 | if (WARN_ON(g->mux_reg < 0)) |
369 | return; | 394 | return; |
370 | 395 | ||
371 | val = pmx_readl(pmx, g->mux_bank, g->mux_reg); | 396 | val = pmx_readl(pmx, g->mux_bank, g->mux_reg); |
@@ -385,6 +410,7 @@ static struct pinmux_ops tegra_pinmux_ops = { | |||
385 | static int tegra_pinconf_reg(struct tegra_pmx *pmx, | 410 | static int tegra_pinconf_reg(struct tegra_pmx *pmx, |
386 | const struct tegra_pingroup *g, | 411 | const struct tegra_pingroup *g, |
387 | enum tegra_pinconf_param param, | 412 | enum tegra_pinconf_param param, |
413 | bool report_err, | ||
388 | s8 *bank, s16 *reg, s8 *bit, s8 *width) | 414 | s8 *bank, s16 *reg, s8 *bit, s8 *width) |
389 | { | 415 | { |
390 | switch (param) { | 416 | switch (param) { |
@@ -472,9 +498,10 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, | |||
472 | } | 498 | } |
473 | 499 | ||
474 | if (*reg < 0) { | 500 | if (*reg < 0) { |
475 | dev_err(pmx->dev, | 501 | if (report_err) |
476 | "Config param %04x not supported on group %s\n", | 502 | dev_err(pmx->dev, |
477 | param, g->name); | 503 | "Config param %04x not supported on group %s\n", |
504 | param, g->name); | ||
478 | return -ENOTSUPP; | 505 | return -ENOTSUPP; |
479 | } | 506 | } |
480 | 507 | ||
@@ -484,12 +511,14 @@ static int tegra_pinconf_reg(struct tegra_pmx *pmx, | |||
484 | static int tegra_pinconf_get(struct pinctrl_dev *pctldev, | 511 | static int tegra_pinconf_get(struct pinctrl_dev *pctldev, |
485 | unsigned pin, unsigned long *config) | 512 | unsigned pin, unsigned long *config) |
486 | { | 513 | { |
514 | dev_err(pctldev->dev, "pin_config_get op not supported\n"); | ||
487 | return -ENOTSUPP; | 515 | return -ENOTSUPP; |
488 | } | 516 | } |
489 | 517 | ||
490 | static int tegra_pinconf_set(struct pinctrl_dev *pctldev, | 518 | static int tegra_pinconf_set(struct pinctrl_dev *pctldev, |
491 | unsigned pin, unsigned long config) | 519 | unsigned pin, unsigned long config) |
492 | { | 520 | { |
521 | dev_err(pctldev->dev, "pin_config_set op not supported\n"); | ||
493 | return -ENOTSUPP; | 522 | return -ENOTSUPP; |
494 | } | 523 | } |
495 | 524 | ||
@@ -507,7 +536,8 @@ static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev, | |||
507 | 536 | ||
508 | g = &pmx->soc->groups[group]; | 537 | g = &pmx->soc->groups[group]; |
509 | 538 | ||
510 | ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width); | 539 | ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, |
540 | &width); | ||
511 | if (ret < 0) | 541 | if (ret < 0) |
512 | return ret; | 542 | return ret; |
513 | 543 | ||
@@ -534,7 +564,8 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, | |||
534 | 564 | ||
535 | g = &pmx->soc->groups[group]; | 565 | g = &pmx->soc->groups[group]; |
536 | 566 | ||
537 | ret = tegra_pinconf_reg(pmx, g, param, &bank, ®, &bit, &width); | 567 | ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit, |
568 | &width); | ||
538 | if (ret < 0) | 569 | if (ret < 0) |
539 | return ret; | 570 | return ret; |
540 | 571 | ||
@@ -542,8 +573,10 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, | |||
542 | 573 | ||
543 | /* LOCK can't be cleared */ | 574 | /* LOCK can't be cleared */ |
544 | if (param == TEGRA_PINCONF_PARAM_LOCK) { | 575 | if (param == TEGRA_PINCONF_PARAM_LOCK) { |
545 | if ((val & BIT(bit)) && !arg) | 576 | if ((val & BIT(bit)) && !arg) { |
577 | dev_err(pctldev->dev, "LOCK bit cannot be cleared\n"); | ||
546 | return -EINVAL; | 578 | return -EINVAL; |
579 | } | ||
547 | } | 580 | } |
548 | 581 | ||
549 | /* Special-case Boolean values; allow any non-zero as true */ | 582 | /* Special-case Boolean values; allow any non-zero as true */ |
@@ -552,8 +585,12 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, | |||
552 | 585 | ||
553 | /* Range-check user-supplied value */ | 586 | /* Range-check user-supplied value */ |
554 | mask = (1 << width) - 1; | 587 | mask = (1 << width) - 1; |
555 | if (arg & ~mask) | 588 | if (arg & ~mask) { |
589 | dev_err(pctldev->dev, | ||
590 | "config %lx: %x too big for %d bit register\n", | ||
591 | config, arg, width); | ||
556 | return -EINVAL; | 592 | return -EINVAL; |
593 | } | ||
557 | 594 | ||
558 | /* Update register */ | 595 | /* Update register */ |
559 | val &= ~(mask << bit); | 596 | val &= ~(mask << bit); |
@@ -563,23 +600,78 @@ static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev, | |||
563 | return 0; | 600 | return 0; |
564 | } | 601 | } |
565 | 602 | ||
603 | #ifdef CONFIG_DEBUG_FS | ||
566 | static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, | 604 | static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev, |
567 | struct seq_file *s, unsigned offset) | 605 | struct seq_file *s, unsigned offset) |
568 | { | 606 | { |
569 | } | 607 | } |
570 | 608 | ||
609 | static const char *strip_prefix(const char *s) | ||
610 | { | ||
611 | const char *comma = strchr(s, ','); | ||
612 | if (!comma) | ||
613 | return s; | ||
614 | |||
615 | return comma + 1; | ||
616 | } | ||
617 | |||
571 | static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, | 618 | static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, |
572 | struct seq_file *s, unsigned selector) | 619 | struct seq_file *s, unsigned group) |
620 | { | ||
621 | struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
622 | const struct tegra_pingroup *g; | ||
623 | int i, ret; | ||
624 | s8 bank, bit, width; | ||
625 | s16 reg; | ||
626 | u32 val; | ||
627 | |||
628 | g = &pmx->soc->groups[group]; | ||
629 | |||
630 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | ||
631 | ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false, | ||
632 | &bank, ®, &bit, &width); | ||
633 | if (ret < 0) | ||
634 | continue; | ||
635 | |||
636 | val = pmx_readl(pmx, bank, reg); | ||
637 | val >>= bit; | ||
638 | val &= (1 << width) - 1; | ||
639 | |||
640 | seq_printf(s, "\n\t%s=%u", | ||
641 | strip_prefix(cfg_params[i].property), val); | ||
642 | } | ||
643 | } | ||
644 | |||
645 | static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev, | ||
646 | struct seq_file *s, | ||
647 | unsigned long config) | ||
573 | { | 648 | { |
649 | enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config); | ||
650 | u16 arg = TEGRA_PINCONF_UNPACK_ARG(config); | ||
651 | const char *pname = "unknown"; | ||
652 | int i; | ||
653 | |||
654 | for (i = 0; i < ARRAY_SIZE(cfg_params); i++) { | ||
655 | if (cfg_params[i].param == param) { | ||
656 | pname = cfg_params[i].property; | ||
657 | break; | ||
658 | } | ||
659 | } | ||
660 | |||
661 | seq_printf(s, "%s=%d", strip_prefix(pname), arg); | ||
574 | } | 662 | } |
663 | #endif | ||
575 | 664 | ||
576 | struct pinconf_ops tegra_pinconf_ops = { | 665 | struct pinconf_ops tegra_pinconf_ops = { |
577 | .pin_config_get = tegra_pinconf_get, | 666 | .pin_config_get = tegra_pinconf_get, |
578 | .pin_config_set = tegra_pinconf_set, | 667 | .pin_config_set = tegra_pinconf_set, |
579 | .pin_config_group_get = tegra_pinconf_group_get, | 668 | .pin_config_group_get = tegra_pinconf_group_get, |
580 | .pin_config_group_set = tegra_pinconf_group_set, | 669 | .pin_config_group_set = tegra_pinconf_group_set, |
670 | #ifdef CONFIG_DEBUG_FS | ||
581 | .pin_config_dbg_show = tegra_pinconf_dbg_show, | 671 | .pin_config_dbg_show = tegra_pinconf_dbg_show, |
582 | .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, | 672 | .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show, |
673 | .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show, | ||
674 | #endif | ||
583 | }; | 675 | }; |
584 | 676 | ||
585 | static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { | 677 | static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { |
@@ -589,60 +681,29 @@ static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = { | |||
589 | }; | 681 | }; |
590 | 682 | ||
591 | static struct pinctrl_desc tegra_pinctrl_desc = { | 683 | static struct pinctrl_desc tegra_pinctrl_desc = { |
592 | .name = DRIVER_NAME, | ||
593 | .pctlops = &tegra_pinctrl_ops, | 684 | .pctlops = &tegra_pinctrl_ops, |
594 | .pmxops = &tegra_pinmux_ops, | 685 | .pmxops = &tegra_pinmux_ops, |
595 | .confops = &tegra_pinconf_ops, | 686 | .confops = &tegra_pinconf_ops, |
596 | .owner = THIS_MODULE, | 687 | .owner = THIS_MODULE, |
597 | }; | 688 | }; |
598 | 689 | ||
599 | static struct of_device_id tegra_pinctrl_of_match[] __devinitdata = { | 690 | int __devinit tegra_pinctrl_probe(struct platform_device *pdev, |
600 | #ifdef CONFIG_PINCTRL_TEGRA20 | 691 | const struct tegra_pinctrl_soc_data *soc_data) |
601 | { | ||
602 | .compatible = "nvidia,tegra20-pinmux-disabled", | ||
603 | .data = tegra20_pinctrl_init, | ||
604 | }, | ||
605 | #endif | ||
606 | #ifdef CONFIG_PINCTRL_TEGRA30 | ||
607 | { | ||
608 | .compatible = "nvidia,tegra30-pinmux-disabled", | ||
609 | .data = tegra30_pinctrl_init, | ||
610 | }, | ||
611 | #endif | ||
612 | {}, | ||
613 | }; | ||
614 | |||
615 | static int __devinit tegra_pinctrl_probe(struct platform_device *pdev) | ||
616 | { | 692 | { |
617 | const struct of_device_id *match; | ||
618 | tegra_pinctrl_soc_initf initf = NULL; | ||
619 | struct tegra_pmx *pmx; | 693 | struct tegra_pmx *pmx; |
620 | struct resource *res; | 694 | struct resource *res; |
621 | int i; | 695 | int i; |
622 | 696 | ||
623 | match = of_match_device(tegra_pinctrl_of_match, &pdev->dev); | ||
624 | if (match) | ||
625 | initf = (tegra_pinctrl_soc_initf)match->data; | ||
626 | #ifdef CONFIG_PINCTRL_TEGRA20 | ||
627 | if (!initf) | ||
628 | initf = tegra20_pinctrl_init; | ||
629 | #endif | ||
630 | if (!initf) { | ||
631 | dev_err(&pdev->dev, | ||
632 | "Could not determine SoC-specific init func\n"); | ||
633 | return -EINVAL; | ||
634 | } | ||
635 | |||
636 | pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); | 697 | pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); |
637 | if (!pmx) { | 698 | if (!pmx) { |
638 | dev_err(&pdev->dev, "Can't alloc tegra_pmx\n"); | 699 | dev_err(&pdev->dev, "Can't alloc tegra_pmx\n"); |
639 | return -ENOMEM; | 700 | return -ENOMEM; |
640 | } | 701 | } |
641 | pmx->dev = &pdev->dev; | 702 | pmx->dev = &pdev->dev; |
642 | 703 | pmx->soc = soc_data; | |
643 | (*initf)(&pmx->soc); | ||
644 | 704 | ||
645 | tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; | 705 | tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios; |
706 | tegra_pinctrl_desc.name = dev_name(&pdev->dev); | ||
646 | tegra_pinctrl_desc.pins = pmx->soc->pins; | 707 | tegra_pinctrl_desc.pins = pmx->soc->pins; |
647 | tegra_pinctrl_desc.npins = pmx->soc->npins; | 708 | tegra_pinctrl_desc.npins = pmx->soc->npins; |
648 | 709 | ||
@@ -697,8 +758,9 @@ static int __devinit tegra_pinctrl_probe(struct platform_device *pdev) | |||
697 | 758 | ||
698 | return 0; | 759 | return 0; |
699 | } | 760 | } |
761 | EXPORT_SYMBOL_GPL(tegra_pinctrl_probe); | ||
700 | 762 | ||
701 | static int __devexit tegra_pinctrl_remove(struct platform_device *pdev) | 763 | int __devexit tegra_pinctrl_remove(struct platform_device *pdev) |
702 | { | 764 | { |
703 | struct tegra_pmx *pmx = platform_get_drvdata(pdev); | 765 | struct tegra_pmx *pmx = platform_get_drvdata(pdev); |
704 | 766 | ||
@@ -707,30 +769,4 @@ static int __devexit tegra_pinctrl_remove(struct platform_device *pdev) | |||
707 | 769 | ||
708 | return 0; | 770 | return 0; |
709 | } | 771 | } |
710 | 772 | EXPORT_SYMBOL_GPL(tegra_pinctrl_remove); | |
711 | static struct platform_driver tegra_pinctrl_driver = { | ||
712 | .driver = { | ||
713 | .name = DRIVER_NAME, | ||
714 | .owner = THIS_MODULE, | ||
715 | .of_match_table = tegra_pinctrl_of_match, | ||
716 | }, | ||
717 | .probe = tegra_pinctrl_probe, | ||
718 | .remove = __devexit_p(tegra_pinctrl_remove), | ||
719 | }; | ||
720 | |||
721 | static int __init tegra_pinctrl_init(void) | ||
722 | { | ||
723 | return platform_driver_register(&tegra_pinctrl_driver); | ||
724 | } | ||
725 | arch_initcall(tegra_pinctrl_init); | ||
726 | |||
727 | static void __exit tegra_pinctrl_exit(void) | ||
728 | { | ||
729 | platform_driver_unregister(&tegra_pinctrl_driver); | ||
730 | } | ||
731 | module_exit(tegra_pinctrl_exit); | ||
732 | |||
733 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | ||
734 | MODULE_DESCRIPTION("NVIDIA Tegra pinctrl driver"); | ||
735 | MODULE_LICENSE("GPL v2"); | ||
736 | MODULE_DEVICE_TABLE(of, tegra_pinctrl_of_match); | ||
diff --git a/drivers/pinctrl/pinctrl-tegra.h b/drivers/pinctrl/pinctrl-tegra.h index 782c795326ef..705c007a38cc 100644 --- a/drivers/pinctrl/pinctrl-tegra.h +++ b/drivers/pinctrl/pinctrl-tegra.h | |||
@@ -139,25 +139,8 @@ struct tegra_pinctrl_soc_data { | |||
139 | unsigned ngroups; | 139 | unsigned ngroups; |
140 | }; | 140 | }; |
141 | 141 | ||
142 | /** | 142 | int tegra_pinctrl_probe(struct platform_device *pdev, |
143 | * tegra_pinctrl_soc_initf() - Retrieve pin controller details for a SoC. | 143 | const struct tegra_pinctrl_soc_data *soc_data); |
144 | * @soc_data: This pointer must be updated to point at a struct containing | 144 | int tegra_pinctrl_remove(struct platform_device *pdev); |
145 | * details of the SoC. | ||
146 | */ | ||
147 | typedef void (*tegra_pinctrl_soc_initf)( | ||
148 | const struct tegra_pinctrl_soc_data **soc_data); | ||
149 | |||
150 | /** | ||
151 | * tegra20_pinctrl_init() - Retrieve pin controller details for Tegra20 | ||
152 | * @soc_data: This pointer will be updated to point at a struct containing | ||
153 | * details of Tegra20's pin controller. | ||
154 | */ | ||
155 | void tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data); | ||
156 | /** | ||
157 | * tegra30_pinctrl_init() - Retrieve pin controller details for Tegra20 | ||
158 | * @soc_data: This pointer will be updated to point at a struct containing | ||
159 | * details of Tegra30's pin controller. | ||
160 | */ | ||
161 | void tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc_data); | ||
162 | 145 | ||
163 | #endif | 146 | #endif |
diff --git a/drivers/pinctrl/pinctrl-tegra20.c b/drivers/pinctrl/pinctrl-tegra20.c index f69ff96aa292..a74f9a568536 100644 --- a/drivers/pinctrl/pinctrl-tegra20.c +++ b/drivers/pinctrl/pinctrl-tegra20.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Pinctrl data for the NVIDIA Tegra20 pinmux | 2 | * Pinctrl data for the NVIDIA Tegra20 pinmux |
3 | * | 3 | * |
4 | * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Derived from code: | 6 | * Derived from code: |
7 | * Copyright (C) 2010 Google, Inc. | 7 | * Copyright (C) 2010 Google, Inc. |
@@ -17,6 +17,8 @@ | |||
17 | * more details. | 17 | * more details. |
18 | */ | 18 | */ |
19 | 19 | ||
20 | #include <linux/module.h> | ||
21 | #include <linux/of.h> | ||
20 | #include <linux/platform_device.h> | 22 | #include <linux/platform_device.h> |
21 | #include <linux/pinctrl/pinctrl.h> | 23 | #include <linux/pinctrl/pinctrl.h> |
22 | #include <linux/pinctrl/pinmux.h> | 24 | #include <linux/pinctrl/pinmux.h> |
@@ -2854,7 +2856,39 @@ static const struct tegra_pinctrl_soc_data tegra20_pinctrl = { | |||
2854 | .ngroups = ARRAY_SIZE(tegra20_groups), | 2856 | .ngroups = ARRAY_SIZE(tegra20_groups), |
2855 | }; | 2857 | }; |
2856 | 2858 | ||
2857 | void __devinit tegra20_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) | 2859 | static int __devinit tegra20_pinctrl_probe(struct platform_device *pdev) |
2858 | { | 2860 | { |
2859 | *soc = &tegra20_pinctrl; | 2861 | return tegra_pinctrl_probe(pdev, &tegra20_pinctrl); |
2860 | } | 2862 | } |
2863 | |||
2864 | static struct of_device_id tegra20_pinctrl_of_match[] __devinitdata = { | ||
2865 | { .compatible = "nvidia,tegra20-pinmux", }, | ||
2866 | { }, | ||
2867 | }; | ||
2868 | |||
2869 | static struct platform_driver tegra20_pinctrl_driver = { | ||
2870 | .driver = { | ||
2871 | .name = "tegra20-pinctrl", | ||
2872 | .owner = THIS_MODULE, | ||
2873 | .of_match_table = tegra20_pinctrl_of_match, | ||
2874 | }, | ||
2875 | .probe = tegra20_pinctrl_probe, | ||
2876 | .remove = __devexit_p(tegra_pinctrl_remove), | ||
2877 | }; | ||
2878 | |||
2879 | static int __init tegra20_pinctrl_init(void) | ||
2880 | { | ||
2881 | return platform_driver_register(&tegra20_pinctrl_driver); | ||
2882 | } | ||
2883 | arch_initcall(tegra20_pinctrl_init); | ||
2884 | |||
2885 | static void __exit tegra20_pinctrl_exit(void) | ||
2886 | { | ||
2887 | platform_driver_unregister(&tegra20_pinctrl_driver); | ||
2888 | } | ||
2889 | module_exit(tegra20_pinctrl_exit); | ||
2890 | |||
2891 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | ||
2892 | MODULE_DESCRIPTION("NVIDIA Tegra20 pinctrl driver"); | ||
2893 | MODULE_LICENSE("GPL v2"); | ||
2894 | MODULE_DEVICE_TABLE(of, tegra20_pinctrl_of_match); | ||
diff --git a/drivers/pinctrl/pinctrl-tegra30.c b/drivers/pinctrl/pinctrl-tegra30.c index 4d7571d4a431..0386fdf0da16 100644 --- a/drivers/pinctrl/pinctrl-tegra30.c +++ b/drivers/pinctrl/pinctrl-tegra30.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Pinctrl data for the NVIDIA Tegra30 pinmux | 2 | * Pinctrl data for the NVIDIA Tegra30 pinmux |
3 | * | 3 | * |
4 | * Copyright (c) 2011, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2011-2012, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * This program is free software; you can redistribute it and/or modify it | 6 | * This program is free software; you can redistribute it and/or modify it |
7 | * under the terms and conditions of the GNU General Public License, | 7 | * under the terms and conditions of the GNU General Public License, |
@@ -13,6 +13,8 @@ | |||
13 | * more details. | 13 | * more details. |
14 | */ | 14 | */ |
15 | 15 | ||
16 | #include <linux/module.h> | ||
17 | #include <linux/of.h> | ||
16 | #include <linux/platform_device.h> | 18 | #include <linux/platform_device.h> |
17 | #include <linux/pinctrl/pinctrl.h> | 19 | #include <linux/pinctrl/pinctrl.h> |
18 | #include <linux/pinctrl/pinmux.h> | 20 | #include <linux/pinctrl/pinmux.h> |
@@ -3720,7 +3722,39 @@ static const struct tegra_pinctrl_soc_data tegra30_pinctrl = { | |||
3720 | .ngroups = ARRAY_SIZE(tegra30_groups), | 3722 | .ngroups = ARRAY_SIZE(tegra30_groups), |
3721 | }; | 3723 | }; |
3722 | 3724 | ||
3723 | void __devinit tegra30_pinctrl_init(const struct tegra_pinctrl_soc_data **soc) | 3725 | static int __devinit tegra30_pinctrl_probe(struct platform_device *pdev) |
3724 | { | 3726 | { |
3725 | *soc = &tegra30_pinctrl; | 3727 | return tegra_pinctrl_probe(pdev, &tegra30_pinctrl); |
3726 | } | 3728 | } |
3729 | |||
3730 | static struct of_device_id tegra30_pinctrl_of_match[] __devinitdata = { | ||
3731 | { .compatible = "nvidia,tegra30-pinmux", }, | ||
3732 | { }, | ||
3733 | }; | ||
3734 | |||
3735 | static struct platform_driver tegra30_pinctrl_driver = { | ||
3736 | .driver = { | ||
3737 | .name = "tegra30-pinctrl", | ||
3738 | .owner = THIS_MODULE, | ||
3739 | .of_match_table = tegra30_pinctrl_of_match, | ||
3740 | }, | ||
3741 | .probe = tegra30_pinctrl_probe, | ||
3742 | .remove = __devexit_p(tegra_pinctrl_remove), | ||
3743 | }; | ||
3744 | |||
3745 | static int __init tegra30_pinctrl_init(void) | ||
3746 | { | ||
3747 | return platform_driver_register(&tegra30_pinctrl_driver); | ||
3748 | } | ||
3749 | arch_initcall(tegra30_pinctrl_init); | ||
3750 | |||
3751 | static void __exit tegra30_pinctrl_exit(void) | ||
3752 | { | ||
3753 | platform_driver_unregister(&tegra30_pinctrl_driver); | ||
3754 | } | ||
3755 | module_exit(tegra30_pinctrl_exit); | ||
3756 | |||
3757 | MODULE_AUTHOR("Stephen Warren <swarren@nvidia.com>"); | ||
3758 | MODULE_DESCRIPTION("NVIDIA Tegra30 pinctrl driver"); | ||
3759 | MODULE_LICENSE("GPL v2"); | ||
3760 | MODULE_DEVICE_TABLE(of, tegra30_pinctrl_of_match); | ||
diff --git a/drivers/pinctrl/spear/Kconfig b/drivers/pinctrl/spear/Kconfig new file mode 100644 index 000000000000..6a2596b4f359 --- /dev/null +++ b/drivers/pinctrl/spear/Kconfig | |||
@@ -0,0 +1,34 @@ | |||
1 | # | ||
2 | # ST Microelectronics SPEAr PINCTRL drivers | ||
3 | # | ||
4 | |||
5 | if PLAT_SPEAR | ||
6 | |||
7 | config PINCTRL_SPEAR | ||
8 | bool | ||
9 | depends on OF | ||
10 | select PINMUX | ||
11 | help | ||
12 | This enables pin control drivers for SPEAr Platform | ||
13 | |||
14 | config PINCTRL_SPEAR3XX | ||
15 | bool | ||
16 | depends on ARCH_SPEAR3XX | ||
17 | select PINCTRL_SPEAR | ||
18 | |||
19 | config PINCTRL_SPEAR300 | ||
20 | bool "ST Microelectronics SPEAr300 SoC pin controller driver" | ||
21 | depends on MACH_SPEAR300 | ||
22 | select PINCTRL_SPEAR3XX | ||
23 | |||
24 | config PINCTRL_SPEAR310 | ||
25 | bool "ST Microelectronics SPEAr310 SoC pin controller driver" | ||
26 | depends on MACH_SPEAR310 | ||
27 | select PINCTRL_SPEAR3XX | ||
28 | |||
29 | config PINCTRL_SPEAR320 | ||
30 | bool "ST Microelectronics SPEAr320 SoC pin controller driver" | ||
31 | depends on MACH_SPEAR320 | ||
32 | select PINCTRL_SPEAR3XX | ||
33 | |||
34 | endif | ||
diff --git a/drivers/pinctrl/spear/Makefile b/drivers/pinctrl/spear/Makefile new file mode 100644 index 000000000000..15dcb85da22d --- /dev/null +++ b/drivers/pinctrl/spear/Makefile | |||
@@ -0,0 +1,7 @@ | |||
1 | # SPEAr pinmux support | ||
2 | |||
3 | obj-$(CONFIG_PINCTRL_SPEAR) += pinctrl-spear.o | ||
4 | obj-$(CONFIG_PINCTRL_SPEAR3XX) += pinctrl-spear3xx.o | ||
5 | obj-$(CONFIG_PINCTRL_SPEAR300) += pinctrl-spear300.o | ||
6 | obj-$(CONFIG_PINCTRL_SPEAR310) += pinctrl-spear310.o | ||
7 | obj-$(CONFIG_PINCTRL_SPEAR320) += pinctrl-spear320.o | ||
diff --git a/drivers/pinctrl/spear/pinctrl-spear.c b/drivers/pinctrl/spear/pinctrl-spear.c new file mode 100644 index 000000000000..5ae50aadf885 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear.c | |||
@@ -0,0 +1,354 @@ | |||
1 | /* | ||
2 | * Driver for the ST Microelectronics SPEAr pinmux | ||
3 | * | ||
4 | * Copyright (C) 2012 ST Microelectronics | ||
5 | * Viresh Kumar <viresh.kumar@st.com> | ||
6 | * | ||
7 | * Inspired from: | ||
8 | * - U300 Pinctl drivers | ||
9 | * - Tegra Pinctl drivers | ||
10 | * | ||
11 | * This file is licensed under the terms of the GNU General Public | ||
12 | * License version 2. This program is licensed "as is" without any | ||
13 | * warranty of any kind, whether express or implied. | ||
14 | */ | ||
15 | |||
16 | #include <linux/err.h> | ||
17 | #include <linux/io.h> | ||
18 | #include <linux/module.h> | ||
19 | #include <linux/of.h> | ||
20 | #include <linux/of_address.h> | ||
21 | #include <linux/pinctrl/machine.h> | ||
22 | #include <linux/pinctrl/pinctrl.h> | ||
23 | #include <linux/pinctrl/pinmux.h> | ||
24 | #include <linux/platform_device.h> | ||
25 | #include <linux/slab.h> | ||
26 | |||
27 | #include "pinctrl-spear.h" | ||
28 | |||
29 | #define DRIVER_NAME "spear-pinmux" | ||
30 | |||
31 | static inline u32 pmx_readl(struct spear_pmx *pmx, u32 reg) | ||
32 | { | ||
33 | return readl_relaxed(pmx->vbase + reg); | ||
34 | } | ||
35 | |||
36 | static inline void pmx_writel(struct spear_pmx *pmx, u32 val, u32 reg) | ||
37 | { | ||
38 | writel_relaxed(val, pmx->vbase + reg); | ||
39 | } | ||
40 | |||
41 | static int set_mode(struct spear_pmx *pmx, int mode) | ||
42 | { | ||
43 | struct spear_pmx_mode *pmx_mode = NULL; | ||
44 | int i; | ||
45 | u32 val; | ||
46 | |||
47 | if (!pmx->machdata->pmx_modes || !pmx->machdata->npmx_modes) | ||
48 | return -EINVAL; | ||
49 | |||
50 | for (i = 0; i < pmx->machdata->npmx_modes; i++) { | ||
51 | if (pmx->machdata->pmx_modes[i]->mode == (1 << mode)) { | ||
52 | pmx_mode = pmx->machdata->pmx_modes[i]; | ||
53 | break; | ||
54 | } | ||
55 | } | ||
56 | |||
57 | if (!pmx_mode) | ||
58 | return -EINVAL; | ||
59 | |||
60 | val = pmx_readl(pmx, pmx_mode->reg); | ||
61 | val &= ~pmx_mode->mask; | ||
62 | val |= pmx_mode->val; | ||
63 | pmx_writel(pmx, val, pmx_mode->reg); | ||
64 | |||
65 | pmx->machdata->mode = pmx_mode->mode; | ||
66 | dev_info(pmx->dev, "Configured Mode: %s with id: %x\n\n", | ||
67 | pmx_mode->name ? pmx_mode->name : "no_name", | ||
68 | pmx_mode->reg); | ||
69 | |||
70 | return 0; | ||
71 | } | ||
72 | |||
73 | void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg) | ||
74 | { | ||
75 | struct spear_pingroup *pgroup; | ||
76 | struct spear_modemux *modemux; | ||
77 | int i, j, group; | ||
78 | |||
79 | for (group = 0; group < machdata->ngroups; group++) { | ||
80 | pgroup = machdata->groups[group]; | ||
81 | |||
82 | for (i = 0; i < pgroup->nmodemuxs; i++) { | ||
83 | modemux = &pgroup->modemuxs[i]; | ||
84 | |||
85 | for (j = 0; j < modemux->nmuxregs; j++) | ||
86 | if (modemux->muxregs[j].reg == 0xFFFF) | ||
87 | modemux->muxregs[j].reg = reg; | ||
88 | } | ||
89 | } | ||
90 | } | ||
91 | |||
92 | static int spear_pinctrl_get_groups_cnt(struct pinctrl_dev *pctldev) | ||
93 | { | ||
94 | struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
95 | |||
96 | return pmx->machdata->ngroups; | ||
97 | } | ||
98 | |||
99 | static const char *spear_pinctrl_get_group_name(struct pinctrl_dev *pctldev, | ||
100 | unsigned group) | ||
101 | { | ||
102 | struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
103 | |||
104 | return pmx->machdata->groups[group]->name; | ||
105 | } | ||
106 | |||
107 | static int spear_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, | ||
108 | unsigned group, const unsigned **pins, unsigned *num_pins) | ||
109 | { | ||
110 | struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
111 | |||
112 | *pins = pmx->machdata->groups[group]->pins; | ||
113 | *num_pins = pmx->machdata->groups[group]->npins; | ||
114 | |||
115 | return 0; | ||
116 | } | ||
117 | |||
118 | static void spear_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, | ||
119 | struct seq_file *s, unsigned offset) | ||
120 | { | ||
121 | seq_printf(s, " " DRIVER_NAME); | ||
122 | } | ||
123 | |||
124 | int spear_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev, | ||
125 | struct device_node *np_config, | ||
126 | struct pinctrl_map **map, unsigned *num_maps) | ||
127 | { | ||
128 | struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
129 | struct device_node *np; | ||
130 | struct property *prop; | ||
131 | const char *function, *group; | ||
132 | int ret, index = 0, count = 0; | ||
133 | |||
134 | /* calculate number of maps required */ | ||
135 | for_each_child_of_node(np_config, np) { | ||
136 | ret = of_property_read_string(np, "st,function", &function); | ||
137 | if (ret < 0) | ||
138 | return ret; | ||
139 | |||
140 | ret = of_property_count_strings(np, "st,pins"); | ||
141 | if (ret < 0) | ||
142 | return ret; | ||
143 | |||
144 | count += ret; | ||
145 | } | ||
146 | |||
147 | if (!count) { | ||
148 | dev_err(pmx->dev, "No child nodes passed via DT\n"); | ||
149 | return -ENODEV; | ||
150 | } | ||
151 | |||
152 | *map = kzalloc(sizeof(**map) * count, GFP_KERNEL); | ||
153 | if (!*map) | ||
154 | return -ENOMEM; | ||
155 | |||
156 | for_each_child_of_node(np_config, np) { | ||
157 | of_property_read_string(np, "st,function", &function); | ||
158 | of_property_for_each_string(np, "st,pins", prop, group) { | ||
159 | (*map)[index].type = PIN_MAP_TYPE_MUX_GROUP; | ||
160 | (*map)[index].data.mux.group = group; | ||
161 | (*map)[index].data.mux.function = function; | ||
162 | index++; | ||
163 | } | ||
164 | } | ||
165 | |||
166 | *num_maps = count; | ||
167 | |||
168 | return 0; | ||
169 | } | ||
170 | |||
171 | void spear_pinctrl_dt_free_map(struct pinctrl_dev *pctldev, | ||
172 | struct pinctrl_map *map, unsigned num_maps) | ||
173 | { | ||
174 | kfree(map); | ||
175 | } | ||
176 | |||
177 | static struct pinctrl_ops spear_pinctrl_ops = { | ||
178 | .get_groups_count = spear_pinctrl_get_groups_cnt, | ||
179 | .get_group_name = spear_pinctrl_get_group_name, | ||
180 | .get_group_pins = spear_pinctrl_get_group_pins, | ||
181 | .pin_dbg_show = spear_pinctrl_pin_dbg_show, | ||
182 | .dt_node_to_map = spear_pinctrl_dt_node_to_map, | ||
183 | .dt_free_map = spear_pinctrl_dt_free_map, | ||
184 | }; | ||
185 | |||
186 | static int spear_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev) | ||
187 | { | ||
188 | struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
189 | |||
190 | return pmx->machdata->nfunctions; | ||
191 | } | ||
192 | |||
193 | static const char *spear_pinctrl_get_func_name(struct pinctrl_dev *pctldev, | ||
194 | unsigned function) | ||
195 | { | ||
196 | struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
197 | |||
198 | return pmx->machdata->functions[function]->name; | ||
199 | } | ||
200 | |||
201 | static int spear_pinctrl_get_func_groups(struct pinctrl_dev *pctldev, | ||
202 | unsigned function, const char *const **groups, | ||
203 | unsigned * const ngroups) | ||
204 | { | ||
205 | struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
206 | |||
207 | *groups = pmx->machdata->functions[function]->groups; | ||
208 | *ngroups = pmx->machdata->functions[function]->ngroups; | ||
209 | |||
210 | return 0; | ||
211 | } | ||
212 | |||
213 | static int spear_pinctrl_endisable(struct pinctrl_dev *pctldev, | ||
214 | unsigned function, unsigned group, bool enable) | ||
215 | { | ||
216 | struct spear_pmx *pmx = pinctrl_dev_get_drvdata(pctldev); | ||
217 | const struct spear_pingroup *pgroup; | ||
218 | const struct spear_modemux *modemux; | ||
219 | struct spear_muxreg *muxreg; | ||
220 | u32 val, temp; | ||
221 | int i, j; | ||
222 | bool found = false; | ||
223 | |||
224 | pgroup = pmx->machdata->groups[group]; | ||
225 | |||
226 | for (i = 0; i < pgroup->nmodemuxs; i++) { | ||
227 | modemux = &pgroup->modemuxs[i]; | ||
228 | |||
229 | /* SoC have any modes */ | ||
230 | if (pmx->machdata->modes_supported) { | ||
231 | if (!(pmx->machdata->mode & modemux->modes)) | ||
232 | continue; | ||
233 | } | ||
234 | |||
235 | found = true; | ||
236 | for (j = 0; j < modemux->nmuxregs; j++) { | ||
237 | muxreg = &modemux->muxregs[j]; | ||
238 | |||
239 | val = pmx_readl(pmx, muxreg->reg); | ||
240 | val &= ~muxreg->mask; | ||
241 | |||
242 | if (enable) | ||
243 | temp = muxreg->val; | ||
244 | else | ||
245 | temp = ~muxreg->val; | ||
246 | |||
247 | val |= temp; | ||
248 | pmx_writel(pmx, val, muxreg->reg); | ||
249 | } | ||
250 | } | ||
251 | |||
252 | if (!found) { | ||
253 | dev_err(pmx->dev, "pinmux group: %s not supported\n", | ||
254 | pgroup->name); | ||
255 | return -ENODEV; | ||
256 | } | ||
257 | |||
258 | return 0; | ||
259 | } | ||
260 | |||
261 | static int spear_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function, | ||
262 | unsigned group) | ||
263 | { | ||
264 | return spear_pinctrl_endisable(pctldev, function, group, true); | ||
265 | } | ||
266 | |||
267 | static void spear_pinctrl_disable(struct pinctrl_dev *pctldev, | ||
268 | unsigned function, unsigned group) | ||
269 | { | ||
270 | spear_pinctrl_endisable(pctldev, function, group, false); | ||
271 | } | ||
272 | |||
273 | static struct pinmux_ops spear_pinmux_ops = { | ||
274 | .get_functions_count = spear_pinctrl_get_funcs_count, | ||
275 | .get_function_name = spear_pinctrl_get_func_name, | ||
276 | .get_function_groups = spear_pinctrl_get_func_groups, | ||
277 | .enable = spear_pinctrl_enable, | ||
278 | .disable = spear_pinctrl_disable, | ||
279 | }; | ||
280 | |||
281 | static struct pinctrl_desc spear_pinctrl_desc = { | ||
282 | .name = DRIVER_NAME, | ||
283 | .pctlops = &spear_pinctrl_ops, | ||
284 | .pmxops = &spear_pinmux_ops, | ||
285 | .owner = THIS_MODULE, | ||
286 | }; | ||
287 | |||
288 | int __devinit spear_pinctrl_probe(struct platform_device *pdev, | ||
289 | struct spear_pinctrl_machdata *machdata) | ||
290 | { | ||
291 | struct device_node *np = pdev->dev.of_node; | ||
292 | struct resource *res; | ||
293 | struct spear_pmx *pmx; | ||
294 | |||
295 | if (!machdata) | ||
296 | return -ENODEV; | ||
297 | |||
298 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | ||
299 | if (!res) | ||
300 | return -EINVAL; | ||
301 | |||
302 | pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL); | ||
303 | if (!pmx) { | ||
304 | dev_err(&pdev->dev, "Can't alloc spear_pmx\n"); | ||
305 | return -ENOMEM; | ||
306 | } | ||
307 | |||
308 | pmx->vbase = devm_ioremap(&pdev->dev, res->start, resource_size(res)); | ||
309 | if (!pmx->vbase) { | ||
310 | dev_err(&pdev->dev, "Couldn't ioremap at index 0\n"); | ||
311 | return -ENODEV; | ||
312 | } | ||
313 | |||
314 | pmx->dev = &pdev->dev; | ||
315 | pmx->machdata = machdata; | ||
316 | |||
317 | /* configure mode, if supported by SoC */ | ||
318 | if (machdata->modes_supported) { | ||
319 | int mode = 0; | ||
320 | |||
321 | if (of_property_read_u32(np, "st,pinmux-mode", &mode)) { | ||
322 | dev_err(&pdev->dev, "OF: pinmux mode not passed\n"); | ||
323 | return -EINVAL; | ||
324 | } | ||
325 | |||
326 | if (set_mode(pmx, mode)) { | ||
327 | dev_err(&pdev->dev, "OF: Couldn't configure mode: %x\n", | ||
328 | mode); | ||
329 | return -EINVAL; | ||
330 | } | ||
331 | } | ||
332 | |||
333 | platform_set_drvdata(pdev, pmx); | ||
334 | |||
335 | spear_pinctrl_desc.pins = machdata->pins; | ||
336 | spear_pinctrl_desc.npins = machdata->npins; | ||
337 | |||
338 | pmx->pctl = pinctrl_register(&spear_pinctrl_desc, &pdev->dev, pmx); | ||
339 | if (IS_ERR(pmx->pctl)) { | ||
340 | dev_err(&pdev->dev, "Couldn't register pinctrl driver\n"); | ||
341 | return PTR_ERR(pmx->pctl); | ||
342 | } | ||
343 | |||
344 | return 0; | ||
345 | } | ||
346 | |||
347 | int __devexit spear_pinctrl_remove(struct platform_device *pdev) | ||
348 | { | ||
349 | struct spear_pmx *pmx = platform_get_drvdata(pdev); | ||
350 | |||
351 | pinctrl_unregister(pmx->pctl); | ||
352 | |||
353 | return 0; | ||
354 | } | ||
diff --git a/drivers/pinctrl/spear/pinctrl-spear.h b/drivers/pinctrl/spear/pinctrl-spear.h new file mode 100644 index 000000000000..47a6b5b72f90 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear.h | |||
@@ -0,0 +1,142 @@ | |||
1 | /* | ||
2 | * Driver header file for the ST Microelectronics SPEAr pinmux | ||
3 | * | ||
4 | * Copyright (C) 2012 ST Microelectronics | ||
5 | * Viresh Kumar <viresh.kumar@st.com> | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public | ||
8 | * License version 2. This program is licensed "as is" without any | ||
9 | * warranty of any kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | #ifndef __PINMUX_SPEAR_H__ | ||
13 | #define __PINMUX_SPEAR_H__ | ||
14 | |||
15 | #include <linux/pinctrl/pinctrl.h> | ||
16 | #include <linux/types.h> | ||
17 | |||
18 | struct platform_device; | ||
19 | struct device; | ||
20 | |||
21 | /** | ||
22 | * struct spear_pmx_mode - SPEAr pmx mode | ||
23 | * @name: name of pmx mode | ||
24 | * @mode: mode id | ||
25 | * @reg: register for configuring this mode | ||
26 | * @mask: mask of this mode in reg | ||
27 | * @val: val to be configured at reg after doing (val & mask) | ||
28 | */ | ||
29 | struct spear_pmx_mode { | ||
30 | const char *const name; | ||
31 | u16 mode; | ||
32 | u16 reg; | ||
33 | u16 mask; | ||
34 | u32 val; | ||
35 | }; | ||
36 | |||
37 | /** | ||
38 | * struct spear_muxreg - SPEAr mux reg configuration | ||
39 | * @reg: register offset | ||
40 | * @mask: mask bits | ||
41 | * @val: val to be written on mask bits | ||
42 | */ | ||
43 | struct spear_muxreg { | ||
44 | u16 reg; | ||
45 | u32 mask; | ||
46 | u32 val; | ||
47 | }; | ||
48 | |||
49 | /** | ||
50 | * struct spear_modemux - SPEAr mode mux configuration | ||
51 | * @modes: mode ids supported by this group of muxregs | ||
52 | * @nmuxregs: number of muxreg configurations to be done for modes | ||
53 | * @muxregs: array of muxreg configurations to be done for modes | ||
54 | */ | ||
55 | struct spear_modemux { | ||
56 | u16 modes; | ||
57 | u8 nmuxregs; | ||
58 | struct spear_muxreg *muxregs; | ||
59 | }; | ||
60 | |||
61 | /** | ||
62 | * struct spear_pingroup - SPEAr pin group configurations | ||
63 | * @name: name of pin group | ||
64 | * @pins: array containing pin numbers | ||
65 | * @npins: size of pins array | ||
66 | * @modemuxs: array of modemux configurations for this pin group | ||
67 | * @nmodemuxs: size of array modemuxs | ||
68 | * | ||
69 | * A representation of a group of pins in the SPEAr pin controller. Each group | ||
70 | * allows some parameter or parameters to be configured. | ||
71 | */ | ||
72 | struct spear_pingroup { | ||
73 | const char *name; | ||
74 | const unsigned *pins; | ||
75 | unsigned npins; | ||
76 | struct spear_modemux *modemuxs; | ||
77 | unsigned nmodemuxs; | ||
78 | }; | ||
79 | |||
80 | /** | ||
81 | * struct spear_function - SPEAr pinctrl mux function | ||
82 | * @name: The name of the function, exported to pinctrl core. | ||
83 | * @groups: An array of pin groups that may select this function. | ||
84 | * @ngroups: The number of entries in @groups. | ||
85 | */ | ||
86 | struct spear_function { | ||
87 | const char *name; | ||
88 | const char *const *groups; | ||
89 | unsigned ngroups; | ||
90 | }; | ||
91 | |||
92 | /** | ||
93 | * struct spear_pinctrl_machdata - SPEAr pin controller machine driver | ||
94 | * configuration | ||
95 | * @pins: An array describing all pins the pin controller affects. | ||
96 | * All pins which are also GPIOs must be listed first within the *array, | ||
97 | * and be numbered identically to the GPIO controller's *numbering. | ||
98 | * @npins: The numbmer of entries in @pins. | ||
99 | * @functions: An array describing all mux functions the SoC supports. | ||
100 | * @nfunctions: The numbmer of entries in @functions. | ||
101 | * @groups: An array describing all pin groups the pin SoC supports. | ||
102 | * @ngroups: The numbmer of entries in @groups. | ||
103 | * | ||
104 | * @modes_supported: Does SoC support modes | ||
105 | * @mode: mode configured from probe | ||
106 | * @pmx_modes: array of modes supported by SoC | ||
107 | * @npmx_modes: number of entries in pmx_modes. | ||
108 | */ | ||
109 | struct spear_pinctrl_machdata { | ||
110 | const struct pinctrl_pin_desc *pins; | ||
111 | unsigned npins; | ||
112 | struct spear_function **functions; | ||
113 | unsigned nfunctions; | ||
114 | struct spear_pingroup **groups; | ||
115 | unsigned ngroups; | ||
116 | |||
117 | bool modes_supported; | ||
118 | u16 mode; | ||
119 | struct spear_pmx_mode **pmx_modes; | ||
120 | unsigned npmx_modes; | ||
121 | }; | ||
122 | |||
123 | /** | ||
124 | * struct spear_pmx - SPEAr pinctrl mux | ||
125 | * @dev: pointer to struct dev of platform_device registered | ||
126 | * @pctl: pointer to struct pinctrl_dev | ||
127 | * @machdata: pointer to SoC or machine specific structure | ||
128 | * @vbase: virtual base address of pinmux controller | ||
129 | */ | ||
130 | struct spear_pmx { | ||
131 | struct device *dev; | ||
132 | struct pinctrl_dev *pctl; | ||
133 | struct spear_pinctrl_machdata *machdata; | ||
134 | void __iomem *vbase; | ||
135 | }; | ||
136 | |||
137 | /* exported routines */ | ||
138 | void __devinit pmx_init_addr(struct spear_pinctrl_machdata *machdata, u16 reg); | ||
139 | int __devinit spear_pinctrl_probe(struct platform_device *pdev, | ||
140 | struct spear_pinctrl_machdata *machdata); | ||
141 | int __devexit spear_pinctrl_remove(struct platform_device *pdev); | ||
142 | #endif /* __PINMUX_SPEAR_H__ */ | ||
diff --git a/drivers/pinctrl/spear/pinctrl-spear300.c b/drivers/pinctrl/spear/pinctrl-spear300.c new file mode 100644 index 000000000000..9c82a35e4e78 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear300.c | |||
@@ -0,0 +1,708 @@ | |||
1 | /* | ||
2 | * Driver for the ST Microelectronics SPEAr300 pinmux | ||
3 | * | ||
4 | * Copyright (C) 2012 ST Microelectronics | ||
5 | * Viresh Kumar <viresh.kumar@st.com> | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public | ||
8 | * License version 2. This program is licensed "as is" without any | ||
9 | * warranty of any kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | #include <linux/err.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/of_device.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include "pinctrl-spear3xx.h" | ||
18 | |||
19 | #define DRIVER_NAME "spear300-pinmux" | ||
20 | |||
21 | /* addresses */ | ||
22 | #define PMX_CONFIG_REG 0x00 | ||
23 | #define MODE_CONFIG_REG 0x04 | ||
24 | |||
25 | /* modes */ | ||
26 | #define NAND_MODE (1 << 0) | ||
27 | #define NOR_MODE (1 << 1) | ||
28 | #define PHOTO_FRAME_MODE (1 << 2) | ||
29 | #define LEND_IP_PHONE_MODE (1 << 3) | ||
30 | #define HEND_IP_PHONE_MODE (1 << 4) | ||
31 | #define LEND_WIFI_PHONE_MODE (1 << 5) | ||
32 | #define HEND_WIFI_PHONE_MODE (1 << 6) | ||
33 | #define ATA_PABX_WI2S_MODE (1 << 7) | ||
34 | #define ATA_PABX_I2S_MODE (1 << 8) | ||
35 | #define CAML_LCDW_MODE (1 << 9) | ||
36 | #define CAMU_LCD_MODE (1 << 10) | ||
37 | #define CAMU_WLCD_MODE (1 << 11) | ||
38 | #define CAML_LCD_MODE (1 << 12) | ||
39 | |||
40 | static struct spear_pmx_mode pmx_mode_nand = { | ||
41 | .name = "nand", | ||
42 | .mode = NAND_MODE, | ||
43 | .reg = MODE_CONFIG_REG, | ||
44 | .mask = 0x0000000F, | ||
45 | .val = 0x00, | ||
46 | }; | ||
47 | |||
48 | static struct spear_pmx_mode pmx_mode_nor = { | ||
49 | .name = "nor", | ||
50 | .mode = NOR_MODE, | ||
51 | .reg = MODE_CONFIG_REG, | ||
52 | .mask = 0x0000000F, | ||
53 | .val = 0x01, | ||
54 | }; | ||
55 | |||
56 | static struct spear_pmx_mode pmx_mode_photo_frame = { | ||
57 | .name = "photo frame mode", | ||
58 | .mode = PHOTO_FRAME_MODE, | ||
59 | .reg = MODE_CONFIG_REG, | ||
60 | .mask = 0x0000000F, | ||
61 | .val = 0x02, | ||
62 | }; | ||
63 | |||
64 | static struct spear_pmx_mode pmx_mode_lend_ip_phone = { | ||
65 | .name = "lend ip phone mode", | ||
66 | .mode = LEND_IP_PHONE_MODE, | ||
67 | .reg = MODE_CONFIG_REG, | ||
68 | .mask = 0x0000000F, | ||
69 | .val = 0x03, | ||
70 | }; | ||
71 | |||
72 | static struct spear_pmx_mode pmx_mode_hend_ip_phone = { | ||
73 | .name = "hend ip phone mode", | ||
74 | .mode = HEND_IP_PHONE_MODE, | ||
75 | .reg = MODE_CONFIG_REG, | ||
76 | .mask = 0x0000000F, | ||
77 | .val = 0x04, | ||
78 | }; | ||
79 | |||
80 | static struct spear_pmx_mode pmx_mode_lend_wifi_phone = { | ||
81 | .name = "lend wifi phone mode", | ||
82 | .mode = LEND_WIFI_PHONE_MODE, | ||
83 | .reg = MODE_CONFIG_REG, | ||
84 | .mask = 0x0000000F, | ||
85 | .val = 0x05, | ||
86 | }; | ||
87 | |||
88 | static struct spear_pmx_mode pmx_mode_hend_wifi_phone = { | ||
89 | .name = "hend wifi phone mode", | ||
90 | .mode = HEND_WIFI_PHONE_MODE, | ||
91 | .reg = MODE_CONFIG_REG, | ||
92 | .mask = 0x0000000F, | ||
93 | .val = 0x06, | ||
94 | }; | ||
95 | |||
96 | static struct spear_pmx_mode pmx_mode_ata_pabx_wi2s = { | ||
97 | .name = "ata pabx wi2s mode", | ||
98 | .mode = ATA_PABX_WI2S_MODE, | ||
99 | .reg = MODE_CONFIG_REG, | ||
100 | .mask = 0x0000000F, | ||
101 | .val = 0x07, | ||
102 | }; | ||
103 | |||
104 | static struct spear_pmx_mode pmx_mode_ata_pabx_i2s = { | ||
105 | .name = "ata pabx i2s mode", | ||
106 | .mode = ATA_PABX_I2S_MODE, | ||
107 | .reg = MODE_CONFIG_REG, | ||
108 | .mask = 0x0000000F, | ||
109 | .val = 0x08, | ||
110 | }; | ||
111 | |||
112 | static struct spear_pmx_mode pmx_mode_caml_lcdw = { | ||
113 | .name = "caml lcdw mode", | ||
114 | .mode = CAML_LCDW_MODE, | ||
115 | .reg = MODE_CONFIG_REG, | ||
116 | .mask = 0x0000000F, | ||
117 | .val = 0x0C, | ||
118 | }; | ||
119 | |||
120 | static struct spear_pmx_mode pmx_mode_camu_lcd = { | ||
121 | .name = "camu lcd mode", | ||
122 | .mode = CAMU_LCD_MODE, | ||
123 | .reg = MODE_CONFIG_REG, | ||
124 | .mask = 0x0000000F, | ||
125 | .val = 0x0D, | ||
126 | }; | ||
127 | |||
128 | static struct spear_pmx_mode pmx_mode_camu_wlcd = { | ||
129 | .name = "camu wlcd mode", | ||
130 | .mode = CAMU_WLCD_MODE, | ||
131 | .reg = MODE_CONFIG_REG, | ||
132 | .mask = 0x0000000F, | ||
133 | .val = 0xE, | ||
134 | }; | ||
135 | |||
136 | static struct spear_pmx_mode pmx_mode_caml_lcd = { | ||
137 | .name = "caml lcd mode", | ||
138 | .mode = CAML_LCD_MODE, | ||
139 | .reg = MODE_CONFIG_REG, | ||
140 | .mask = 0x0000000F, | ||
141 | .val = 0x0F, | ||
142 | }; | ||
143 | |||
144 | static struct spear_pmx_mode *spear300_pmx_modes[] = { | ||
145 | &pmx_mode_nand, | ||
146 | &pmx_mode_nor, | ||
147 | &pmx_mode_photo_frame, | ||
148 | &pmx_mode_lend_ip_phone, | ||
149 | &pmx_mode_hend_ip_phone, | ||
150 | &pmx_mode_lend_wifi_phone, | ||
151 | &pmx_mode_hend_wifi_phone, | ||
152 | &pmx_mode_ata_pabx_wi2s, | ||
153 | &pmx_mode_ata_pabx_i2s, | ||
154 | &pmx_mode_caml_lcdw, | ||
155 | &pmx_mode_camu_lcd, | ||
156 | &pmx_mode_camu_wlcd, | ||
157 | &pmx_mode_caml_lcd, | ||
158 | }; | ||
159 | |||
160 | /* fsmc_2chips_pins */ | ||
161 | static const unsigned fsmc_2chips_pins[] = { 1, 97 }; | ||
162 | static struct spear_muxreg fsmc_2chips_muxreg[] = { | ||
163 | { | ||
164 | .reg = PMX_CONFIG_REG, | ||
165 | .mask = PMX_FIRDA_MASK, | ||
166 | .val = 0, | ||
167 | }, | ||
168 | }; | ||
169 | |||
170 | static struct spear_modemux fsmc_2chips_modemux[] = { | ||
171 | { | ||
172 | .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | | ||
173 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, | ||
174 | .muxregs = fsmc_2chips_muxreg, | ||
175 | .nmuxregs = ARRAY_SIZE(fsmc_2chips_muxreg), | ||
176 | }, | ||
177 | }; | ||
178 | |||
179 | static struct spear_pingroup fsmc_2chips_pingroup = { | ||
180 | .name = "fsmc_2chips_grp", | ||
181 | .pins = fsmc_2chips_pins, | ||
182 | .npins = ARRAY_SIZE(fsmc_2chips_pins), | ||
183 | .modemuxs = fsmc_2chips_modemux, | ||
184 | .nmodemuxs = ARRAY_SIZE(fsmc_2chips_modemux), | ||
185 | }; | ||
186 | |||
187 | /* fsmc_4chips_pins */ | ||
188 | static const unsigned fsmc_4chips_pins[] = { 1, 2, 3, 97 }; | ||
189 | static struct spear_muxreg fsmc_4chips_muxreg[] = { | ||
190 | { | ||
191 | .reg = PMX_CONFIG_REG, | ||
192 | .mask = PMX_FIRDA_MASK | PMX_UART0_MASK, | ||
193 | .val = 0, | ||
194 | }, | ||
195 | }; | ||
196 | |||
197 | static struct spear_modemux fsmc_4chips_modemux[] = { | ||
198 | { | ||
199 | .modes = NAND_MODE | NOR_MODE | PHOTO_FRAME_MODE | | ||
200 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE, | ||
201 | .muxregs = fsmc_4chips_muxreg, | ||
202 | .nmuxregs = ARRAY_SIZE(fsmc_4chips_muxreg), | ||
203 | }, | ||
204 | }; | ||
205 | |||
206 | static struct spear_pingroup fsmc_4chips_pingroup = { | ||
207 | .name = "fsmc_4chips_grp", | ||
208 | .pins = fsmc_4chips_pins, | ||
209 | .npins = ARRAY_SIZE(fsmc_4chips_pins), | ||
210 | .modemuxs = fsmc_4chips_modemux, | ||
211 | .nmodemuxs = ARRAY_SIZE(fsmc_4chips_modemux), | ||
212 | }; | ||
213 | |||
214 | static const char *const fsmc_grps[] = { "fsmc_2chips_grp", "fsmc_4chips_grp" | ||
215 | }; | ||
216 | static struct spear_function fsmc_function = { | ||
217 | .name = "fsmc", | ||
218 | .groups = fsmc_grps, | ||
219 | .ngroups = ARRAY_SIZE(fsmc_grps), | ||
220 | }; | ||
221 | |||
222 | /* clcd_lcdmode_pins */ | ||
223 | static const unsigned clcd_lcdmode_pins[] = { 49, 50 }; | ||
224 | static struct spear_muxreg clcd_lcdmode_muxreg[] = { | ||
225 | { | ||
226 | .reg = PMX_CONFIG_REG, | ||
227 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
228 | .val = 0, | ||
229 | }, | ||
230 | }; | ||
231 | |||
232 | static struct spear_modemux clcd_lcdmode_modemux[] = { | ||
233 | { | ||
234 | .modes = HEND_IP_PHONE_MODE | HEND_WIFI_PHONE_MODE | | ||
235 | CAMU_LCD_MODE | CAML_LCD_MODE, | ||
236 | .muxregs = clcd_lcdmode_muxreg, | ||
237 | .nmuxregs = ARRAY_SIZE(clcd_lcdmode_muxreg), | ||
238 | }, | ||
239 | }; | ||
240 | |||
241 | static struct spear_pingroup clcd_lcdmode_pingroup = { | ||
242 | .name = "clcd_lcdmode_grp", | ||
243 | .pins = clcd_lcdmode_pins, | ||
244 | .npins = ARRAY_SIZE(clcd_lcdmode_pins), | ||
245 | .modemuxs = clcd_lcdmode_modemux, | ||
246 | .nmodemuxs = ARRAY_SIZE(clcd_lcdmode_modemux), | ||
247 | }; | ||
248 | |||
249 | /* clcd_pfmode_pins */ | ||
250 | static const unsigned clcd_pfmode_pins[] = { 47, 48, 49, 50 }; | ||
251 | static struct spear_muxreg clcd_pfmode_muxreg[] = { | ||
252 | { | ||
253 | .reg = PMX_CONFIG_REG, | ||
254 | .mask = PMX_TIMER_2_3_MASK, | ||
255 | .val = 0, | ||
256 | }, | ||
257 | }; | ||
258 | |||
259 | static struct spear_modemux clcd_pfmode_modemux[] = { | ||
260 | { | ||
261 | .modes = PHOTO_FRAME_MODE, | ||
262 | .muxregs = clcd_pfmode_muxreg, | ||
263 | .nmuxregs = ARRAY_SIZE(clcd_pfmode_muxreg), | ||
264 | }, | ||
265 | }; | ||
266 | |||
267 | static struct spear_pingroup clcd_pfmode_pingroup = { | ||
268 | .name = "clcd_pfmode_grp", | ||
269 | .pins = clcd_pfmode_pins, | ||
270 | .npins = ARRAY_SIZE(clcd_pfmode_pins), | ||
271 | .modemuxs = clcd_pfmode_modemux, | ||
272 | .nmodemuxs = ARRAY_SIZE(clcd_pfmode_modemux), | ||
273 | }; | ||
274 | |||
275 | static const char *const clcd_grps[] = { "clcd_lcdmode_grp", "clcd_pfmode_grp" | ||
276 | }; | ||
277 | static struct spear_function clcd_function = { | ||
278 | .name = "clcd", | ||
279 | .groups = clcd_grps, | ||
280 | .ngroups = ARRAY_SIZE(clcd_grps), | ||
281 | }; | ||
282 | |||
283 | /* tdm_pins */ | ||
284 | static const unsigned tdm_pins[] = { 34, 35, 36, 37, 38 }; | ||
285 | static struct spear_muxreg tdm_muxreg[] = { | ||
286 | { | ||
287 | .reg = PMX_CONFIG_REG, | ||
288 | .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, | ||
289 | .val = 0, | ||
290 | }, | ||
291 | }; | ||
292 | |||
293 | static struct spear_modemux tdm_modemux[] = { | ||
294 | { | ||
295 | .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | | ||
296 | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | ||
297 | | HEND_WIFI_PHONE_MODE | ATA_PABX_WI2S_MODE | ||
298 | | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | ||
299 | | CAMU_WLCD_MODE | CAML_LCD_MODE, | ||
300 | .muxregs = tdm_muxreg, | ||
301 | .nmuxregs = ARRAY_SIZE(tdm_muxreg), | ||
302 | }, | ||
303 | }; | ||
304 | |||
305 | static struct spear_pingroup tdm_pingroup = { | ||
306 | .name = "tdm_grp", | ||
307 | .pins = tdm_pins, | ||
308 | .npins = ARRAY_SIZE(tdm_pins), | ||
309 | .modemuxs = tdm_modemux, | ||
310 | .nmodemuxs = ARRAY_SIZE(tdm_modemux), | ||
311 | }; | ||
312 | |||
313 | static const char *const tdm_grps[] = { "tdm_grp" }; | ||
314 | static struct spear_function tdm_function = { | ||
315 | .name = "tdm", | ||
316 | .groups = tdm_grps, | ||
317 | .ngroups = ARRAY_SIZE(tdm_grps), | ||
318 | }; | ||
319 | |||
320 | /* i2c_clk_pins */ | ||
321 | static const unsigned i2c_clk_pins[] = { 45, 46, 47, 48 }; | ||
322 | static struct spear_muxreg i2c_clk_muxreg[] = { | ||
323 | { | ||
324 | .reg = PMX_CONFIG_REG, | ||
325 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
326 | .val = 0, | ||
327 | }, | ||
328 | }; | ||
329 | |||
330 | static struct spear_modemux i2c_clk_modemux[] = { | ||
331 | { | ||
332 | .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | | ||
333 | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | | ||
334 | ATA_PABX_WI2S_MODE | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | ||
335 | | CAML_LCD_MODE, | ||
336 | .muxregs = i2c_clk_muxreg, | ||
337 | .nmuxregs = ARRAY_SIZE(i2c_clk_muxreg), | ||
338 | }, | ||
339 | }; | ||
340 | |||
341 | static struct spear_pingroup i2c_clk_pingroup = { | ||
342 | .name = "i2c_clk_grp_grp", | ||
343 | .pins = i2c_clk_pins, | ||
344 | .npins = ARRAY_SIZE(i2c_clk_pins), | ||
345 | .modemuxs = i2c_clk_modemux, | ||
346 | .nmodemuxs = ARRAY_SIZE(i2c_clk_modemux), | ||
347 | }; | ||
348 | |||
349 | static const char *const i2c_grps[] = { "i2c_clk_grp" }; | ||
350 | static struct spear_function i2c_function = { | ||
351 | .name = "i2c1", | ||
352 | .groups = i2c_grps, | ||
353 | .ngroups = ARRAY_SIZE(i2c_grps), | ||
354 | }; | ||
355 | |||
356 | /* caml_pins */ | ||
357 | static const unsigned caml_pins[] = { 12, 13, 14, 15, 16, 17, 18, 19, 20, 21 }; | ||
358 | static struct spear_muxreg caml_muxreg[] = { | ||
359 | { | ||
360 | .reg = PMX_CONFIG_REG, | ||
361 | .mask = PMX_MII_MASK, | ||
362 | .val = 0, | ||
363 | }, | ||
364 | }; | ||
365 | |||
366 | static struct spear_modemux caml_modemux[] = { | ||
367 | { | ||
368 | .modes = CAML_LCDW_MODE | CAML_LCD_MODE, | ||
369 | .muxregs = caml_muxreg, | ||
370 | .nmuxregs = ARRAY_SIZE(caml_muxreg), | ||
371 | }, | ||
372 | }; | ||
373 | |||
374 | static struct spear_pingroup caml_pingroup = { | ||
375 | .name = "caml_grp", | ||
376 | .pins = caml_pins, | ||
377 | .npins = ARRAY_SIZE(caml_pins), | ||
378 | .modemuxs = caml_modemux, | ||
379 | .nmodemuxs = ARRAY_SIZE(caml_modemux), | ||
380 | }; | ||
381 | |||
382 | /* camu_pins */ | ||
383 | static const unsigned camu_pins[] = { 16, 17, 18, 19, 20, 21, 45, 46, 47, 48 }; | ||
384 | static struct spear_muxreg camu_muxreg[] = { | ||
385 | { | ||
386 | .reg = PMX_CONFIG_REG, | ||
387 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | PMX_MII_MASK, | ||
388 | .val = 0, | ||
389 | }, | ||
390 | }; | ||
391 | |||
392 | static struct spear_modemux camu_modemux[] = { | ||
393 | { | ||
394 | .modes = CAMU_LCD_MODE | CAMU_WLCD_MODE, | ||
395 | .muxregs = camu_muxreg, | ||
396 | .nmuxregs = ARRAY_SIZE(camu_muxreg), | ||
397 | }, | ||
398 | }; | ||
399 | |||
400 | static struct spear_pingroup camu_pingroup = { | ||
401 | .name = "camu_grp", | ||
402 | .pins = camu_pins, | ||
403 | .npins = ARRAY_SIZE(camu_pins), | ||
404 | .modemuxs = camu_modemux, | ||
405 | .nmodemuxs = ARRAY_SIZE(camu_modemux), | ||
406 | }; | ||
407 | |||
408 | static const char *const cam_grps[] = { "caml_grp", "camu_grp" }; | ||
409 | static struct spear_function cam_function = { | ||
410 | .name = "cam", | ||
411 | .groups = cam_grps, | ||
412 | .ngroups = ARRAY_SIZE(cam_grps), | ||
413 | }; | ||
414 | |||
415 | /* dac_pins */ | ||
416 | static const unsigned dac_pins[] = { 43, 44 }; | ||
417 | static struct spear_muxreg dac_muxreg[] = { | ||
418 | { | ||
419 | .reg = PMX_CONFIG_REG, | ||
420 | .mask = PMX_TIMER_0_1_MASK, | ||
421 | .val = 0, | ||
422 | }, | ||
423 | }; | ||
424 | |||
425 | static struct spear_modemux dac_modemux[] = { | ||
426 | { | ||
427 | .modes = ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | ||
428 | | CAMU_WLCD_MODE | CAML_LCD_MODE, | ||
429 | .muxregs = dac_muxreg, | ||
430 | .nmuxregs = ARRAY_SIZE(dac_muxreg), | ||
431 | }, | ||
432 | }; | ||
433 | |||
434 | static struct spear_pingroup dac_pingroup = { | ||
435 | .name = "dac_grp", | ||
436 | .pins = dac_pins, | ||
437 | .npins = ARRAY_SIZE(dac_pins), | ||
438 | .modemuxs = dac_modemux, | ||
439 | .nmodemuxs = ARRAY_SIZE(dac_modemux), | ||
440 | }; | ||
441 | |||
442 | static const char *const dac_grps[] = { "dac_grp" }; | ||
443 | static struct spear_function dac_function = { | ||
444 | .name = "dac", | ||
445 | .groups = dac_grps, | ||
446 | .ngroups = ARRAY_SIZE(dac_grps), | ||
447 | }; | ||
448 | |||
449 | /* i2s_pins */ | ||
450 | static const unsigned i2s_pins[] = { 39, 40, 41, 42 }; | ||
451 | static struct spear_muxreg i2s_muxreg[] = { | ||
452 | { | ||
453 | .reg = PMX_CONFIG_REG, | ||
454 | .mask = PMX_UART0_MODEM_MASK, | ||
455 | .val = 0, | ||
456 | }, | ||
457 | }; | ||
458 | |||
459 | static struct spear_modemux i2s_modemux[] = { | ||
460 | { | ||
461 | .modes = LEND_IP_PHONE_MODE | HEND_IP_PHONE_MODE | ||
462 | | LEND_WIFI_PHONE_MODE | HEND_WIFI_PHONE_MODE | | ||
463 | ATA_PABX_I2S_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | ||
464 | | CAMU_WLCD_MODE | CAML_LCD_MODE, | ||
465 | .muxregs = i2s_muxreg, | ||
466 | .nmuxregs = ARRAY_SIZE(i2s_muxreg), | ||
467 | }, | ||
468 | }; | ||
469 | |||
470 | static struct spear_pingroup i2s_pingroup = { | ||
471 | .name = "i2s_grp", | ||
472 | .pins = i2s_pins, | ||
473 | .npins = ARRAY_SIZE(i2s_pins), | ||
474 | .modemuxs = i2s_modemux, | ||
475 | .nmodemuxs = ARRAY_SIZE(i2s_modemux), | ||
476 | }; | ||
477 | |||
478 | static const char *const i2s_grps[] = { "i2s_grp" }; | ||
479 | static struct spear_function i2s_function = { | ||
480 | .name = "i2s", | ||
481 | .groups = i2s_grps, | ||
482 | .ngroups = ARRAY_SIZE(i2s_grps), | ||
483 | }; | ||
484 | |||
485 | /* sdhci_4bit_pins */ | ||
486 | static const unsigned sdhci_4bit_pins[] = { 28, 29, 30, 31, 32, 33 }; | ||
487 | static struct spear_muxreg sdhci_4bit_muxreg[] = { | ||
488 | { | ||
489 | .reg = PMX_CONFIG_REG, | ||
490 | .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | | ||
491 | PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | | ||
492 | PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, | ||
493 | .val = 0, | ||
494 | }, | ||
495 | }; | ||
496 | |||
497 | static struct spear_modemux sdhci_4bit_modemux[] = { | ||
498 | { | ||
499 | .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | | ||
500 | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | | ||
501 | HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | | ||
502 | CAMU_WLCD_MODE | CAML_LCD_MODE | ATA_PABX_WI2S_MODE, | ||
503 | .muxregs = sdhci_4bit_muxreg, | ||
504 | .nmuxregs = ARRAY_SIZE(sdhci_4bit_muxreg), | ||
505 | }, | ||
506 | }; | ||
507 | |||
508 | static struct spear_pingroup sdhci_4bit_pingroup = { | ||
509 | .name = "sdhci_4bit_grp", | ||
510 | .pins = sdhci_4bit_pins, | ||
511 | .npins = ARRAY_SIZE(sdhci_4bit_pins), | ||
512 | .modemuxs = sdhci_4bit_modemux, | ||
513 | .nmodemuxs = ARRAY_SIZE(sdhci_4bit_modemux), | ||
514 | }; | ||
515 | |||
516 | /* sdhci_8bit_pins */ | ||
517 | static const unsigned sdhci_8bit_pins[] = { 24, 25, 26, 27, 28, 29, 30, 31, 32, | ||
518 | 33 }; | ||
519 | static struct spear_muxreg sdhci_8bit_muxreg[] = { | ||
520 | { | ||
521 | .reg = PMX_CONFIG_REG, | ||
522 | .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK | | ||
523 | PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK | | ||
524 | PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK | PMX_MII_MASK, | ||
525 | .val = 0, | ||
526 | }, | ||
527 | }; | ||
528 | |||
529 | static struct spear_modemux sdhci_8bit_modemux[] = { | ||
530 | { | ||
531 | .modes = PHOTO_FRAME_MODE | LEND_IP_PHONE_MODE | | ||
532 | HEND_IP_PHONE_MODE | LEND_WIFI_PHONE_MODE | | ||
533 | HEND_WIFI_PHONE_MODE | CAML_LCDW_MODE | CAMU_LCD_MODE | | ||
534 | CAMU_WLCD_MODE | CAML_LCD_MODE, | ||
535 | .muxregs = sdhci_8bit_muxreg, | ||
536 | .nmuxregs = ARRAY_SIZE(sdhci_8bit_muxreg), | ||
537 | }, | ||
538 | }; | ||
539 | |||
540 | static struct spear_pingroup sdhci_8bit_pingroup = { | ||
541 | .name = "sdhci_8bit_grp", | ||
542 | .pins = sdhci_8bit_pins, | ||
543 | .npins = ARRAY_SIZE(sdhci_8bit_pins), | ||
544 | .modemuxs = sdhci_8bit_modemux, | ||
545 | .nmodemuxs = ARRAY_SIZE(sdhci_8bit_modemux), | ||
546 | }; | ||
547 | |||
548 | static const char *const sdhci_grps[] = { "sdhci_4bit_grp", "sdhci_8bit_grp" }; | ||
549 | static struct spear_function sdhci_function = { | ||
550 | .name = "sdhci", | ||
551 | .groups = sdhci_grps, | ||
552 | .ngroups = ARRAY_SIZE(sdhci_grps), | ||
553 | }; | ||
554 | |||
555 | /* gpio1_0_to_3_pins */ | ||
556 | static const unsigned gpio1_0_to_3_pins[] = { 39, 40, 41, 42 }; | ||
557 | static struct spear_muxreg gpio1_0_to_3_muxreg[] = { | ||
558 | { | ||
559 | .reg = PMX_CONFIG_REG, | ||
560 | .mask = PMX_UART0_MODEM_MASK, | ||
561 | .val = 0, | ||
562 | }, | ||
563 | }; | ||
564 | |||
565 | static struct spear_modemux gpio1_0_to_3_modemux[] = { | ||
566 | { | ||
567 | .modes = PHOTO_FRAME_MODE, | ||
568 | .muxregs = gpio1_0_to_3_muxreg, | ||
569 | .nmuxregs = ARRAY_SIZE(gpio1_0_to_3_muxreg), | ||
570 | }, | ||
571 | }; | ||
572 | |||
573 | static struct spear_pingroup gpio1_0_to_3_pingroup = { | ||
574 | .name = "gpio1_0_to_3_grp", | ||
575 | .pins = gpio1_0_to_3_pins, | ||
576 | .npins = ARRAY_SIZE(gpio1_0_to_3_pins), | ||
577 | .modemuxs = gpio1_0_to_3_modemux, | ||
578 | .nmodemuxs = ARRAY_SIZE(gpio1_0_to_3_modemux), | ||
579 | }; | ||
580 | |||
581 | /* gpio1_4_to_7_pins */ | ||
582 | static const unsigned gpio1_4_to_7_pins[] = { 43, 44, 45, 46 }; | ||
583 | |||
584 | static struct spear_muxreg gpio1_4_to_7_muxreg[] = { | ||
585 | { | ||
586 | .reg = PMX_CONFIG_REG, | ||
587 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
588 | .val = 0, | ||
589 | }, | ||
590 | }; | ||
591 | |||
592 | static struct spear_modemux gpio1_4_to_7_modemux[] = { | ||
593 | { | ||
594 | .modes = PHOTO_FRAME_MODE, | ||
595 | .muxregs = gpio1_4_to_7_muxreg, | ||
596 | .nmuxregs = ARRAY_SIZE(gpio1_4_to_7_muxreg), | ||
597 | }, | ||
598 | }; | ||
599 | |||
600 | static struct spear_pingroup gpio1_4_to_7_pingroup = { | ||
601 | .name = "gpio1_4_to_7_grp", | ||
602 | .pins = gpio1_4_to_7_pins, | ||
603 | .npins = ARRAY_SIZE(gpio1_4_to_7_pins), | ||
604 | .modemuxs = gpio1_4_to_7_modemux, | ||
605 | .nmodemuxs = ARRAY_SIZE(gpio1_4_to_7_modemux), | ||
606 | }; | ||
607 | |||
608 | static const char *const gpio1_grps[] = { "gpio1_0_to_3_grp", "gpio1_4_to_7_grp" | ||
609 | }; | ||
610 | static struct spear_function gpio1_function = { | ||
611 | .name = "gpio1", | ||
612 | .groups = gpio1_grps, | ||
613 | .ngroups = ARRAY_SIZE(gpio1_grps), | ||
614 | }; | ||
615 | |||
616 | /* pingroups */ | ||
617 | static struct spear_pingroup *spear300_pingroups[] = { | ||
618 | SPEAR3XX_COMMON_PINGROUPS, | ||
619 | &fsmc_2chips_pingroup, | ||
620 | &fsmc_4chips_pingroup, | ||
621 | &clcd_lcdmode_pingroup, | ||
622 | &clcd_pfmode_pingroup, | ||
623 | &tdm_pingroup, | ||
624 | &i2c_clk_pingroup, | ||
625 | &caml_pingroup, | ||
626 | &camu_pingroup, | ||
627 | &dac_pingroup, | ||
628 | &i2s_pingroup, | ||
629 | &sdhci_4bit_pingroup, | ||
630 | &sdhci_8bit_pingroup, | ||
631 | &gpio1_0_to_3_pingroup, | ||
632 | &gpio1_4_to_7_pingroup, | ||
633 | }; | ||
634 | |||
635 | /* functions */ | ||
636 | static struct spear_function *spear300_functions[] = { | ||
637 | SPEAR3XX_COMMON_FUNCTIONS, | ||
638 | &fsmc_function, | ||
639 | &clcd_function, | ||
640 | &tdm_function, | ||
641 | &i2c_function, | ||
642 | &cam_function, | ||
643 | &dac_function, | ||
644 | &i2s_function, | ||
645 | &sdhci_function, | ||
646 | &gpio1_function, | ||
647 | }; | ||
648 | |||
649 | static struct of_device_id spear300_pinctrl_of_match[] __devinitdata = { | ||
650 | { | ||
651 | .compatible = "st,spear300-pinmux", | ||
652 | }, | ||
653 | {}, | ||
654 | }; | ||
655 | |||
656 | static int __devinit spear300_pinctrl_probe(struct platform_device *pdev) | ||
657 | { | ||
658 | int ret; | ||
659 | |||
660 | spear3xx_machdata.groups = spear300_pingroups; | ||
661 | spear3xx_machdata.ngroups = ARRAY_SIZE(spear300_pingroups); | ||
662 | spear3xx_machdata.functions = spear300_functions; | ||
663 | spear3xx_machdata.nfunctions = ARRAY_SIZE(spear300_functions); | ||
664 | |||
665 | spear3xx_machdata.modes_supported = true; | ||
666 | spear3xx_machdata.pmx_modes = spear300_pmx_modes; | ||
667 | spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear300_pmx_modes); | ||
668 | |||
669 | pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); | ||
670 | |||
671 | ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); | ||
672 | if (ret) | ||
673 | return ret; | ||
674 | |||
675 | return 0; | ||
676 | } | ||
677 | |||
678 | static int __devexit spear300_pinctrl_remove(struct platform_device *pdev) | ||
679 | { | ||
680 | return spear_pinctrl_remove(pdev); | ||
681 | } | ||
682 | |||
683 | static struct platform_driver spear300_pinctrl_driver = { | ||
684 | .driver = { | ||
685 | .name = DRIVER_NAME, | ||
686 | .owner = THIS_MODULE, | ||
687 | .of_match_table = spear300_pinctrl_of_match, | ||
688 | }, | ||
689 | .probe = spear300_pinctrl_probe, | ||
690 | .remove = __devexit_p(spear300_pinctrl_remove), | ||
691 | }; | ||
692 | |||
693 | static int __init spear300_pinctrl_init(void) | ||
694 | { | ||
695 | return platform_driver_register(&spear300_pinctrl_driver); | ||
696 | } | ||
697 | arch_initcall(spear300_pinctrl_init); | ||
698 | |||
699 | static void __exit spear300_pinctrl_exit(void) | ||
700 | { | ||
701 | platform_driver_unregister(&spear300_pinctrl_driver); | ||
702 | } | ||
703 | module_exit(spear300_pinctrl_exit); | ||
704 | |||
705 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>"); | ||
706 | MODULE_DESCRIPTION("ST Microelectronics SPEAr300 pinctrl driver"); | ||
707 | MODULE_LICENSE("GPL v2"); | ||
708 | MODULE_DEVICE_TABLE(of, spear300_pinctrl_of_match); | ||
diff --git a/drivers/pinctrl/spear/pinctrl-spear310.c b/drivers/pinctrl/spear/pinctrl-spear310.c new file mode 100644 index 000000000000..1a9707605125 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear310.c | |||
@@ -0,0 +1,431 @@ | |||
1 | /* | ||
2 | * Driver for the ST Microelectronics SPEAr310 pinmux | ||
3 | * | ||
4 | * Copyright (C) 2012 ST Microelectronics | ||
5 | * Viresh Kumar <viresh.kumar@st.com> | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public | ||
8 | * License version 2. This program is licensed "as is" without any | ||
9 | * warranty of any kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | #include <linux/err.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/of_device.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include "pinctrl-spear3xx.h" | ||
18 | |||
19 | #define DRIVER_NAME "spear310-pinmux" | ||
20 | |||
21 | /* addresses */ | ||
22 | #define PMX_CONFIG_REG 0x08 | ||
23 | |||
24 | /* emi_cs_0_to_5_pins */ | ||
25 | static const unsigned emi_cs_0_to_5_pins[] = { 45, 46, 47, 48, 49, 50 }; | ||
26 | static struct spear_muxreg emi_cs_0_to_5_muxreg[] = { | ||
27 | { | ||
28 | .reg = PMX_CONFIG_REG, | ||
29 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
30 | .val = 0, | ||
31 | }, | ||
32 | }; | ||
33 | |||
34 | static struct spear_modemux emi_cs_0_to_5_modemux[] = { | ||
35 | { | ||
36 | .muxregs = emi_cs_0_to_5_muxreg, | ||
37 | .nmuxregs = ARRAY_SIZE(emi_cs_0_to_5_muxreg), | ||
38 | }, | ||
39 | }; | ||
40 | |||
41 | static struct spear_pingroup emi_cs_0_to_5_pingroup = { | ||
42 | .name = "emi_cs_0_to_5_grp", | ||
43 | .pins = emi_cs_0_to_5_pins, | ||
44 | .npins = ARRAY_SIZE(emi_cs_0_to_5_pins), | ||
45 | .modemuxs = emi_cs_0_to_5_modemux, | ||
46 | .nmodemuxs = ARRAY_SIZE(emi_cs_0_to_5_modemux), | ||
47 | }; | ||
48 | |||
49 | static const char *const emi_cs_0_to_5_grps[] = { "emi_cs_0_to_5_grp" }; | ||
50 | static struct spear_function emi_cs_0_to_5_function = { | ||
51 | .name = "emi", | ||
52 | .groups = emi_cs_0_to_5_grps, | ||
53 | .ngroups = ARRAY_SIZE(emi_cs_0_to_5_grps), | ||
54 | }; | ||
55 | |||
56 | /* uart1_pins */ | ||
57 | static const unsigned uart1_pins[] = { 0, 1 }; | ||
58 | static struct spear_muxreg uart1_muxreg[] = { | ||
59 | { | ||
60 | .reg = PMX_CONFIG_REG, | ||
61 | .mask = PMX_FIRDA_MASK, | ||
62 | .val = 0, | ||
63 | }, | ||
64 | }; | ||
65 | |||
66 | static struct spear_modemux uart1_modemux[] = { | ||
67 | { | ||
68 | .muxregs = uart1_muxreg, | ||
69 | .nmuxregs = ARRAY_SIZE(uart1_muxreg), | ||
70 | }, | ||
71 | }; | ||
72 | |||
73 | static struct spear_pingroup uart1_pingroup = { | ||
74 | .name = "uart1_grp", | ||
75 | .pins = uart1_pins, | ||
76 | .npins = ARRAY_SIZE(uart1_pins), | ||
77 | .modemuxs = uart1_modemux, | ||
78 | .nmodemuxs = ARRAY_SIZE(uart1_modemux), | ||
79 | }; | ||
80 | |||
81 | static const char *const uart1_grps[] = { "uart1_grp" }; | ||
82 | static struct spear_function uart1_function = { | ||
83 | .name = "uart1", | ||
84 | .groups = uart1_grps, | ||
85 | .ngroups = ARRAY_SIZE(uart1_grps), | ||
86 | }; | ||
87 | |||
88 | /* uart2_pins */ | ||
89 | static const unsigned uart2_pins[] = { 43, 44 }; | ||
90 | static struct spear_muxreg uart2_muxreg[] = { | ||
91 | { | ||
92 | .reg = PMX_CONFIG_REG, | ||
93 | .mask = PMX_TIMER_0_1_MASK, | ||
94 | .val = 0, | ||
95 | }, | ||
96 | }; | ||
97 | |||
98 | static struct spear_modemux uart2_modemux[] = { | ||
99 | { | ||
100 | .muxregs = uart2_muxreg, | ||
101 | .nmuxregs = ARRAY_SIZE(uart2_muxreg), | ||
102 | }, | ||
103 | }; | ||
104 | |||
105 | static struct spear_pingroup uart2_pingroup = { | ||
106 | .name = "uart2_grp", | ||
107 | .pins = uart2_pins, | ||
108 | .npins = ARRAY_SIZE(uart2_pins), | ||
109 | .modemuxs = uart2_modemux, | ||
110 | .nmodemuxs = ARRAY_SIZE(uart2_modemux), | ||
111 | }; | ||
112 | |||
113 | static const char *const uart2_grps[] = { "uart2_grp" }; | ||
114 | static struct spear_function uart2_function = { | ||
115 | .name = "uart2", | ||
116 | .groups = uart2_grps, | ||
117 | .ngroups = ARRAY_SIZE(uart2_grps), | ||
118 | }; | ||
119 | |||
120 | /* uart3_pins */ | ||
121 | static const unsigned uart3_pins[] = { 37, 38 }; | ||
122 | static struct spear_muxreg uart3_muxreg[] = { | ||
123 | { | ||
124 | .reg = PMX_CONFIG_REG, | ||
125 | .mask = PMX_UART0_MODEM_MASK, | ||
126 | .val = 0, | ||
127 | }, | ||
128 | }; | ||
129 | |||
130 | static struct spear_modemux uart3_modemux[] = { | ||
131 | { | ||
132 | .muxregs = uart3_muxreg, | ||
133 | .nmuxregs = ARRAY_SIZE(uart3_muxreg), | ||
134 | }, | ||
135 | }; | ||
136 | |||
137 | static struct spear_pingroup uart3_pingroup = { | ||
138 | .name = "uart3_grp", | ||
139 | .pins = uart3_pins, | ||
140 | .npins = ARRAY_SIZE(uart3_pins), | ||
141 | .modemuxs = uart3_modemux, | ||
142 | .nmodemuxs = ARRAY_SIZE(uart3_modemux), | ||
143 | }; | ||
144 | |||
145 | static const char *const uart3_grps[] = { "uart3_grp" }; | ||
146 | static struct spear_function uart3_function = { | ||
147 | .name = "uart3", | ||
148 | .groups = uart3_grps, | ||
149 | .ngroups = ARRAY_SIZE(uart3_grps), | ||
150 | }; | ||
151 | |||
152 | /* uart4_pins */ | ||
153 | static const unsigned uart4_pins[] = { 39, 40 }; | ||
154 | static struct spear_muxreg uart4_muxreg[] = { | ||
155 | { | ||
156 | .reg = PMX_CONFIG_REG, | ||
157 | .mask = PMX_UART0_MODEM_MASK, | ||
158 | .val = 0, | ||
159 | }, | ||
160 | }; | ||
161 | |||
162 | static struct spear_modemux uart4_modemux[] = { | ||
163 | { | ||
164 | .muxregs = uart4_muxreg, | ||
165 | .nmuxregs = ARRAY_SIZE(uart4_muxreg), | ||
166 | }, | ||
167 | }; | ||
168 | |||
169 | static struct spear_pingroup uart4_pingroup = { | ||
170 | .name = "uart4_grp", | ||
171 | .pins = uart4_pins, | ||
172 | .npins = ARRAY_SIZE(uart4_pins), | ||
173 | .modemuxs = uart4_modemux, | ||
174 | .nmodemuxs = ARRAY_SIZE(uart4_modemux), | ||
175 | }; | ||
176 | |||
177 | static const char *const uart4_grps[] = { "uart4_grp" }; | ||
178 | static struct spear_function uart4_function = { | ||
179 | .name = "uart4", | ||
180 | .groups = uart4_grps, | ||
181 | .ngroups = ARRAY_SIZE(uart4_grps), | ||
182 | }; | ||
183 | |||
184 | /* uart5_pins */ | ||
185 | static const unsigned uart5_pins[] = { 41, 42 }; | ||
186 | static struct spear_muxreg uart5_muxreg[] = { | ||
187 | { | ||
188 | .reg = PMX_CONFIG_REG, | ||
189 | .mask = PMX_UART0_MODEM_MASK, | ||
190 | .val = 0, | ||
191 | }, | ||
192 | }; | ||
193 | |||
194 | static struct spear_modemux uart5_modemux[] = { | ||
195 | { | ||
196 | .muxregs = uart5_muxreg, | ||
197 | .nmuxregs = ARRAY_SIZE(uart5_muxreg), | ||
198 | }, | ||
199 | }; | ||
200 | |||
201 | static struct spear_pingroup uart5_pingroup = { | ||
202 | .name = "uart5_grp", | ||
203 | .pins = uart5_pins, | ||
204 | .npins = ARRAY_SIZE(uart5_pins), | ||
205 | .modemuxs = uart5_modemux, | ||
206 | .nmodemuxs = ARRAY_SIZE(uart5_modemux), | ||
207 | }; | ||
208 | |||
209 | static const char *const uart5_grps[] = { "uart5_grp" }; | ||
210 | static struct spear_function uart5_function = { | ||
211 | .name = "uart5", | ||
212 | .groups = uart5_grps, | ||
213 | .ngroups = ARRAY_SIZE(uart5_grps), | ||
214 | }; | ||
215 | |||
216 | /* fsmc_pins */ | ||
217 | static const unsigned fsmc_pins[] = { 34, 35, 36 }; | ||
218 | static struct spear_muxreg fsmc_muxreg[] = { | ||
219 | { | ||
220 | .reg = PMX_CONFIG_REG, | ||
221 | .mask = PMX_SSP_CS_MASK, | ||
222 | .val = 0, | ||
223 | }, | ||
224 | }; | ||
225 | |||
226 | static struct spear_modemux fsmc_modemux[] = { | ||
227 | { | ||
228 | .muxregs = fsmc_muxreg, | ||
229 | .nmuxregs = ARRAY_SIZE(fsmc_muxreg), | ||
230 | }, | ||
231 | }; | ||
232 | |||
233 | static struct spear_pingroup fsmc_pingroup = { | ||
234 | .name = "fsmc_grp", | ||
235 | .pins = fsmc_pins, | ||
236 | .npins = ARRAY_SIZE(fsmc_pins), | ||
237 | .modemuxs = fsmc_modemux, | ||
238 | .nmodemuxs = ARRAY_SIZE(fsmc_modemux), | ||
239 | }; | ||
240 | |||
241 | static const char *const fsmc_grps[] = { "fsmc_grp" }; | ||
242 | static struct spear_function fsmc_function = { | ||
243 | .name = "fsmc", | ||
244 | .groups = fsmc_grps, | ||
245 | .ngroups = ARRAY_SIZE(fsmc_grps), | ||
246 | }; | ||
247 | |||
248 | /* rs485_0_pins */ | ||
249 | static const unsigned rs485_0_pins[] = { 19, 20, 21, 22, 23 }; | ||
250 | static struct spear_muxreg rs485_0_muxreg[] = { | ||
251 | { | ||
252 | .reg = PMX_CONFIG_REG, | ||
253 | .mask = PMX_MII_MASK, | ||
254 | .val = 0, | ||
255 | }, | ||
256 | }; | ||
257 | |||
258 | static struct spear_modemux rs485_0_modemux[] = { | ||
259 | { | ||
260 | .muxregs = rs485_0_muxreg, | ||
261 | .nmuxregs = ARRAY_SIZE(rs485_0_muxreg), | ||
262 | }, | ||
263 | }; | ||
264 | |||
265 | static struct spear_pingroup rs485_0_pingroup = { | ||
266 | .name = "rs485_0_grp", | ||
267 | .pins = rs485_0_pins, | ||
268 | .npins = ARRAY_SIZE(rs485_0_pins), | ||
269 | .modemuxs = rs485_0_modemux, | ||
270 | .nmodemuxs = ARRAY_SIZE(rs485_0_modemux), | ||
271 | }; | ||
272 | |||
273 | static const char *const rs485_0_grps[] = { "rs485_0" }; | ||
274 | static struct spear_function rs485_0_function = { | ||
275 | .name = "rs485_0", | ||
276 | .groups = rs485_0_grps, | ||
277 | .ngroups = ARRAY_SIZE(rs485_0_grps), | ||
278 | }; | ||
279 | |||
280 | /* rs485_1_pins */ | ||
281 | static const unsigned rs485_1_pins[] = { 14, 15, 16, 17, 18 }; | ||
282 | static struct spear_muxreg rs485_1_muxreg[] = { | ||
283 | { | ||
284 | .reg = PMX_CONFIG_REG, | ||
285 | .mask = PMX_MII_MASK, | ||
286 | .val = 0, | ||
287 | }, | ||
288 | }; | ||
289 | |||
290 | static struct spear_modemux rs485_1_modemux[] = { | ||
291 | { | ||
292 | .muxregs = rs485_1_muxreg, | ||
293 | .nmuxregs = ARRAY_SIZE(rs485_1_muxreg), | ||
294 | }, | ||
295 | }; | ||
296 | |||
297 | static struct spear_pingroup rs485_1_pingroup = { | ||
298 | .name = "rs485_1_grp", | ||
299 | .pins = rs485_1_pins, | ||
300 | .npins = ARRAY_SIZE(rs485_1_pins), | ||
301 | .modemuxs = rs485_1_modemux, | ||
302 | .nmodemuxs = ARRAY_SIZE(rs485_1_modemux), | ||
303 | }; | ||
304 | |||
305 | static const char *const rs485_1_grps[] = { "rs485_1" }; | ||
306 | static struct spear_function rs485_1_function = { | ||
307 | .name = "rs485_1", | ||
308 | .groups = rs485_1_grps, | ||
309 | .ngroups = ARRAY_SIZE(rs485_1_grps), | ||
310 | }; | ||
311 | |||
312 | /* tdm_pins */ | ||
313 | static const unsigned tdm_pins[] = { 10, 11, 12, 13 }; | ||
314 | static struct spear_muxreg tdm_muxreg[] = { | ||
315 | { | ||
316 | .reg = PMX_CONFIG_REG, | ||
317 | .mask = PMX_MII_MASK, | ||
318 | .val = 0, | ||
319 | }, | ||
320 | }; | ||
321 | |||
322 | static struct spear_modemux tdm_modemux[] = { | ||
323 | { | ||
324 | .muxregs = tdm_muxreg, | ||
325 | .nmuxregs = ARRAY_SIZE(tdm_muxreg), | ||
326 | }, | ||
327 | }; | ||
328 | |||
329 | static struct spear_pingroup tdm_pingroup = { | ||
330 | .name = "tdm_grp", | ||
331 | .pins = tdm_pins, | ||
332 | .npins = ARRAY_SIZE(tdm_pins), | ||
333 | .modemuxs = tdm_modemux, | ||
334 | .nmodemuxs = ARRAY_SIZE(tdm_modemux), | ||
335 | }; | ||
336 | |||
337 | static const char *const tdm_grps[] = { "tdm_grp" }; | ||
338 | static struct spear_function tdm_function = { | ||
339 | .name = "tdm", | ||
340 | .groups = tdm_grps, | ||
341 | .ngroups = ARRAY_SIZE(tdm_grps), | ||
342 | }; | ||
343 | |||
344 | /* pingroups */ | ||
345 | static struct spear_pingroup *spear310_pingroups[] = { | ||
346 | SPEAR3XX_COMMON_PINGROUPS, | ||
347 | &emi_cs_0_to_5_pingroup, | ||
348 | &uart1_pingroup, | ||
349 | &uart2_pingroup, | ||
350 | &uart3_pingroup, | ||
351 | &uart4_pingroup, | ||
352 | &uart5_pingroup, | ||
353 | &fsmc_pingroup, | ||
354 | &rs485_0_pingroup, | ||
355 | &rs485_1_pingroup, | ||
356 | &tdm_pingroup, | ||
357 | }; | ||
358 | |||
359 | /* functions */ | ||
360 | static struct spear_function *spear310_functions[] = { | ||
361 | SPEAR3XX_COMMON_FUNCTIONS, | ||
362 | &emi_cs_0_to_5_function, | ||
363 | &uart1_function, | ||
364 | &uart2_function, | ||
365 | &uart3_function, | ||
366 | &uart4_function, | ||
367 | &uart5_function, | ||
368 | &fsmc_function, | ||
369 | &rs485_0_function, | ||
370 | &rs485_1_function, | ||
371 | &tdm_function, | ||
372 | }; | ||
373 | |||
374 | static struct of_device_id spear310_pinctrl_of_match[] __devinitdata = { | ||
375 | { | ||
376 | .compatible = "st,spear310-pinmux", | ||
377 | }, | ||
378 | {}, | ||
379 | }; | ||
380 | |||
381 | static int __devinit spear310_pinctrl_probe(struct platform_device *pdev) | ||
382 | { | ||
383 | int ret; | ||
384 | |||
385 | spear3xx_machdata.groups = spear310_pingroups; | ||
386 | spear3xx_machdata.ngroups = ARRAY_SIZE(spear310_pingroups); | ||
387 | spear3xx_machdata.functions = spear310_functions; | ||
388 | spear3xx_machdata.nfunctions = ARRAY_SIZE(spear310_functions); | ||
389 | |||
390 | pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); | ||
391 | |||
392 | spear3xx_machdata.modes_supported = false; | ||
393 | |||
394 | ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); | ||
395 | if (ret) | ||
396 | return ret; | ||
397 | |||
398 | return 0; | ||
399 | } | ||
400 | |||
401 | static int __devexit spear310_pinctrl_remove(struct platform_device *pdev) | ||
402 | { | ||
403 | return spear_pinctrl_remove(pdev); | ||
404 | } | ||
405 | |||
406 | static struct platform_driver spear310_pinctrl_driver = { | ||
407 | .driver = { | ||
408 | .name = DRIVER_NAME, | ||
409 | .owner = THIS_MODULE, | ||
410 | .of_match_table = spear310_pinctrl_of_match, | ||
411 | }, | ||
412 | .probe = spear310_pinctrl_probe, | ||
413 | .remove = __devexit_p(spear310_pinctrl_remove), | ||
414 | }; | ||
415 | |||
416 | static int __init spear310_pinctrl_init(void) | ||
417 | { | ||
418 | return platform_driver_register(&spear310_pinctrl_driver); | ||
419 | } | ||
420 | arch_initcall(spear310_pinctrl_init); | ||
421 | |||
422 | static void __exit spear310_pinctrl_exit(void) | ||
423 | { | ||
424 | platform_driver_unregister(&spear310_pinctrl_driver); | ||
425 | } | ||
426 | module_exit(spear310_pinctrl_exit); | ||
427 | |||
428 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>"); | ||
429 | MODULE_DESCRIPTION("ST Microelectronics SPEAr310 pinctrl driver"); | ||
430 | MODULE_LICENSE("GPL v2"); | ||
431 | MODULE_DEVICE_TABLE(of, SPEAr310_pinctrl_of_match); | ||
diff --git a/drivers/pinctrl/spear/pinctrl-spear320.c b/drivers/pinctrl/spear/pinctrl-spear320.c new file mode 100644 index 000000000000..de726e6c283a --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear320.c | |||
@@ -0,0 +1,3468 @@ | |||
1 | /* | ||
2 | * Driver for the ST Microelectronics SPEAr320 pinmux | ||
3 | * | ||
4 | * Copyright (C) 2012 ST Microelectronics | ||
5 | * Viresh Kumar <viresh.kumar@st.com> | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public | ||
8 | * License version 2. This program is licensed "as is" without any | ||
9 | * warranty of any kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | #include <linux/err.h> | ||
13 | #include <linux/init.h> | ||
14 | #include <linux/module.h> | ||
15 | #include <linux/of_device.h> | ||
16 | #include <linux/platform_device.h> | ||
17 | #include "pinctrl-spear3xx.h" | ||
18 | |||
19 | #define DRIVER_NAME "spear320-pinmux" | ||
20 | |||
21 | /* addresses */ | ||
22 | #define PMX_CONFIG_REG 0x0C | ||
23 | #define MODE_CONFIG_REG 0x10 | ||
24 | #define MODE_EXT_CONFIG_REG 0x18 | ||
25 | |||
26 | /* modes */ | ||
27 | #define AUTO_NET_SMII_MODE (1 << 0) | ||
28 | #define AUTO_NET_MII_MODE (1 << 1) | ||
29 | #define AUTO_EXP_MODE (1 << 2) | ||
30 | #define SMALL_PRINTERS_MODE (1 << 3) | ||
31 | #define EXTENDED_MODE (1 << 4) | ||
32 | |||
33 | static struct spear_pmx_mode pmx_mode_auto_net_smii = { | ||
34 | .name = "Automation Networking SMII mode", | ||
35 | .mode = AUTO_NET_SMII_MODE, | ||
36 | .reg = MODE_CONFIG_REG, | ||
37 | .mask = 0x00000007, | ||
38 | .val = 0x0, | ||
39 | }; | ||
40 | |||
41 | static struct spear_pmx_mode pmx_mode_auto_net_mii = { | ||
42 | .name = "Automation Networking MII mode", | ||
43 | .mode = AUTO_NET_MII_MODE, | ||
44 | .reg = MODE_CONFIG_REG, | ||
45 | .mask = 0x00000007, | ||
46 | .val = 0x1, | ||
47 | }; | ||
48 | |||
49 | static struct spear_pmx_mode pmx_mode_auto_exp = { | ||
50 | .name = "Automation Expanded mode", | ||
51 | .mode = AUTO_EXP_MODE, | ||
52 | .reg = MODE_CONFIG_REG, | ||
53 | .mask = 0x00000007, | ||
54 | .val = 0x2, | ||
55 | }; | ||
56 | |||
57 | static struct spear_pmx_mode pmx_mode_small_printers = { | ||
58 | .name = "Small Printers mode", | ||
59 | .mode = SMALL_PRINTERS_MODE, | ||
60 | .reg = MODE_CONFIG_REG, | ||
61 | .mask = 0x00000007, | ||
62 | .val = 0x3, | ||
63 | }; | ||
64 | |||
65 | static struct spear_pmx_mode pmx_mode_extended = { | ||
66 | .name = "extended mode", | ||
67 | .mode = EXTENDED_MODE, | ||
68 | .reg = MODE_EXT_CONFIG_REG, | ||
69 | .mask = 0x00000001, | ||
70 | .val = 0x1, | ||
71 | }; | ||
72 | |||
73 | static struct spear_pmx_mode *spear320_pmx_modes[] = { | ||
74 | &pmx_mode_auto_net_smii, | ||
75 | &pmx_mode_auto_net_mii, | ||
76 | &pmx_mode_auto_exp, | ||
77 | &pmx_mode_small_printers, | ||
78 | &pmx_mode_extended, | ||
79 | }; | ||
80 | |||
81 | /* Extended mode registers and their offsets */ | ||
82 | #define EXT_CTRL_REG 0x0018 | ||
83 | #define MII_MDIO_MASK (1 << 4) | ||
84 | #define MII_MDIO_10_11_VAL 0 | ||
85 | #define MII_MDIO_81_VAL (1 << 4) | ||
86 | #define EMI_FSMC_DYNAMIC_MUX_MASK (1 << 5) | ||
87 | #define MAC_MODE_MII 0 | ||
88 | #define MAC_MODE_RMII 1 | ||
89 | #define MAC_MODE_SMII 2 | ||
90 | #define MAC_MODE_SS_SMII 3 | ||
91 | #define MAC_MODE_MASK 0x3 | ||
92 | #define MAC1_MODE_SHIFT 16 | ||
93 | #define MAC2_MODE_SHIFT 18 | ||
94 | |||
95 | #define IP_SEL_PAD_0_9_REG 0x00A4 | ||
96 | #define PMX_PL_0_1_MASK (0x3F << 0) | ||
97 | #define PMX_UART2_PL_0_1_VAL 0x0 | ||
98 | #define PMX_I2C2_PL_0_1_VAL (0x4 | (0x4 << 3)) | ||
99 | |||
100 | #define PMX_PL_2_3_MASK (0x3F << 6) | ||
101 | #define PMX_I2C2_PL_2_3_VAL 0x0 | ||
102 | #define PMX_UART6_PL_2_3_VAL ((0x1 << 6) | (0x1 << 9)) | ||
103 | #define PMX_UART1_ENH_PL_2_3_VAL ((0x4 << 6) | (0x4 << 9)) | ||
104 | |||
105 | #define PMX_PL_4_5_MASK (0x3F << 12) | ||
106 | #define PMX_UART5_PL_4_5_VAL ((0x1 << 12) | (0x1 << 15)) | ||
107 | #define PMX_UART1_ENH_PL_4_5_VAL ((0x4 << 12) | (0x4 << 15)) | ||
108 | #define PMX_PL_5_MASK (0x7 << 15) | ||
109 | #define PMX_TOUCH_Y_PL_5_VAL 0x0 | ||
110 | |||
111 | #define PMX_PL_6_7_MASK (0x3F << 18) | ||
112 | #define PMX_PL_6_MASK (0x7 << 18) | ||
113 | #define PMX_PL_7_MASK (0x7 << 21) | ||
114 | #define PMX_UART4_PL_6_7_VAL ((0x1 << 18) | (0x1 << 21)) | ||
115 | #define PMX_PWM_3_PL_6_VAL (0x2 << 18) | ||
116 | #define PMX_PWM_2_PL_7_VAL (0x2 << 21) | ||
117 | #define PMX_UART1_ENH_PL_6_7_VAL ((0x4 << 18) | (0x4 << 21)) | ||
118 | |||
119 | #define PMX_PL_8_9_MASK (0x3F << 24) | ||
120 | #define PMX_UART3_PL_8_9_VAL ((0x1 << 24) | (0x1 << 27)) | ||
121 | #define PMX_PWM_0_1_PL_8_9_VAL ((0x2 << 24) | (0x2 << 27)) | ||
122 | #define PMX_I2C1_PL_8_9_VAL ((0x4 << 24) | (0x4 << 27)) | ||
123 | |||
124 | #define IP_SEL_PAD_10_19_REG 0x00A8 | ||
125 | #define PMX_PL_10_11_MASK (0x3F << 0) | ||
126 | #define PMX_SMII_PL_10_11_VAL 0 | ||
127 | #define PMX_RMII_PL_10_11_VAL ((0x4 << 0) | (0x4 << 3)) | ||
128 | |||
129 | #define PMX_PL_12_MASK (0x7 << 6) | ||
130 | #define PMX_PWM3_PL_12_VAL 0 | ||
131 | #define PMX_SDHCI_CD_PL_12_VAL (0x4 << 6) | ||
132 | |||
133 | #define PMX_PL_13_14_MASK (0x3F << 9) | ||
134 | #define PMX_PL_13_MASK (0x7 << 9) | ||
135 | #define PMX_PL_14_MASK (0x7 << 12) | ||
136 | #define PMX_SSP2_PL_13_14_15_16_VAL 0 | ||
137 | #define PMX_UART4_PL_13_14_VAL ((0x1 << 9) | (0x1 << 12)) | ||
138 | #define PMX_RMII_PL_13_14_VAL ((0x4 << 9) | (0x4 << 12)) | ||
139 | #define PMX_PWM2_PL_13_VAL (0x2 << 9) | ||
140 | #define PMX_PWM1_PL_14_VAL (0x2 << 12) | ||
141 | |||
142 | #define PMX_PL_15_MASK (0x7 << 15) | ||
143 | #define PMX_PWM0_PL_15_VAL (0x2 << 15) | ||
144 | #define PMX_PL_15_16_MASK (0x3F << 15) | ||
145 | #define PMX_UART3_PL_15_16_VAL ((0x1 << 15) | (0x1 << 18)) | ||
146 | #define PMX_RMII_PL_15_16_VAL ((0x4 << 15) | (0x4 << 18)) | ||
147 | |||
148 | #define PMX_PL_17_18_MASK (0x3F << 21) | ||
149 | #define PMX_SSP1_PL_17_18_19_20_VAL 0 | ||
150 | #define PMX_RMII_PL_17_18_VAL ((0x4 << 21) | (0x4 << 24)) | ||
151 | |||
152 | #define PMX_PL_19_MASK (0x7 << 27) | ||
153 | #define PMX_I2C2_PL_19_VAL (0x1 << 27) | ||
154 | #define PMX_RMII_PL_19_VAL (0x4 << 27) | ||
155 | |||
156 | #define IP_SEL_PAD_20_29_REG 0x00AC | ||
157 | #define PMX_PL_20_MASK (0x7 << 0) | ||
158 | #define PMX_I2C2_PL_20_VAL (0x1 << 0) | ||
159 | #define PMX_RMII_PL_20_VAL (0x4 << 0) | ||
160 | |||
161 | #define PMX_PL_21_TO_27_MASK (0x1FFFFF << 3) | ||
162 | #define PMX_SMII_PL_21_TO_27_VAL 0 | ||
163 | #define PMX_RMII_PL_21_TO_27_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15) | (0x4 << 18) | (0x4 << 21)) | ||
164 | |||
165 | #define PMX_PL_28_29_MASK (0x3F << 24) | ||
166 | #define PMX_PL_28_MASK (0x7 << 24) | ||
167 | #define PMX_PL_29_MASK (0x7 << 27) | ||
168 | #define PMX_UART1_PL_28_29_VAL 0 | ||
169 | #define PMX_PWM_3_PL_28_VAL (0x4 << 24) | ||
170 | #define PMX_PWM_2_PL_29_VAL (0x4 << 27) | ||
171 | |||
172 | #define IP_SEL_PAD_30_39_REG 0x00B0 | ||
173 | #define PMX_PL_30_31_MASK (0x3F << 0) | ||
174 | #define PMX_CAN1_PL_30_31_VAL (0) | ||
175 | #define PMX_PL_30_MASK (0x7 << 0) | ||
176 | #define PMX_PL_31_MASK (0x7 << 3) | ||
177 | #define PMX_PWM1_EXT_PL_30_VAL (0x4 << 0) | ||
178 | #define PMX_PWM0_EXT_PL_31_VAL (0x4 << 3) | ||
179 | #define PMX_UART1_ENH_PL_31_VAL (0x3 << 3) | ||
180 | |||
181 | #define PMX_PL_32_33_MASK (0x3F << 6) | ||
182 | #define PMX_CAN0_PL_32_33_VAL 0 | ||
183 | #define PMX_UART1_ENH_PL_32_33_VAL ((0x3 << 6) | (0x3 << 9)) | ||
184 | #define PMX_SSP2_PL_32_33_VAL ((0x4 << 6) | (0x4 << 9)) | ||
185 | |||
186 | #define PMX_PL_34_MASK (0x7 << 12) | ||
187 | #define PMX_PWM2_PL_34_VAL 0 | ||
188 | #define PMX_UART1_ENH_PL_34_VAL (0x2 << 12) | ||
189 | #define PMX_SSP2_PL_34_VAL (0x4 << 12) | ||
190 | |||
191 | #define PMX_PL_35_MASK (0x7 << 15) | ||
192 | #define PMX_I2S_REF_CLK_PL_35_VAL 0 | ||
193 | #define PMX_UART1_ENH_PL_35_VAL (0x2 << 15) | ||
194 | #define PMX_SSP2_PL_35_VAL (0x4 << 15) | ||
195 | |||
196 | #define PMX_PL_36_MASK (0x7 << 18) | ||
197 | #define PMX_TOUCH_X_PL_36_VAL 0 | ||
198 | #define PMX_UART1_ENH_PL_36_VAL (0x2 << 18) | ||
199 | #define PMX_SSP1_PL_36_VAL (0x4 << 18) | ||
200 | |||
201 | #define PMX_PL_37_38_MASK (0x3F << 21) | ||
202 | #define PMX_PWM0_1_PL_37_38_VAL 0 | ||
203 | #define PMX_UART5_PL_37_38_VAL ((0x2 << 21) | (0x2 << 24)) | ||
204 | #define PMX_SSP1_PL_37_38_VAL ((0x4 << 21) | (0x4 << 24)) | ||
205 | |||
206 | #define PMX_PL_39_MASK (0x7 << 27) | ||
207 | #define PMX_I2S_PL_39_VAL 0 | ||
208 | #define PMX_UART4_PL_39_VAL (0x2 << 27) | ||
209 | #define PMX_SSP1_PL_39_VAL (0x4 << 27) | ||
210 | |||
211 | #define IP_SEL_PAD_40_49_REG 0x00B4 | ||
212 | #define PMX_PL_40_MASK (0x7 << 0) | ||
213 | #define PMX_I2S_PL_40_VAL 0 | ||
214 | #define PMX_UART4_PL_40_VAL (0x2 << 0) | ||
215 | #define PMX_PWM3_PL_40_VAL (0x4 << 0) | ||
216 | |||
217 | #define PMX_PL_41_42_MASK (0x3F << 3) | ||
218 | #define PMX_PL_41_MASK (0x7 << 3) | ||
219 | #define PMX_PL_42_MASK (0x7 << 6) | ||
220 | #define PMX_I2S_PL_41_42_VAL 0 | ||
221 | #define PMX_UART3_PL_41_42_VAL ((0x2 << 3) | (0x2 << 6)) | ||
222 | #define PMX_PWM2_PL_41_VAL (0x4 << 3) | ||
223 | #define PMX_PWM1_PL_42_VAL (0x4 << 6) | ||
224 | |||
225 | #define PMX_PL_43_MASK (0x7 << 9) | ||
226 | #define PMX_SDHCI_PL_43_VAL 0 | ||
227 | #define PMX_UART1_ENH_PL_43_VAL (0x2 << 9) | ||
228 | #define PMX_PWM0_PL_43_VAL (0x4 << 9) | ||
229 | |||
230 | #define PMX_PL_44_45_MASK (0x3F << 12) | ||
231 | #define PMX_SDHCI_PL_44_45_VAL 0 | ||
232 | #define PMX_UART1_ENH_PL_44_45_VAL ((0x2 << 12) | (0x2 << 15)) | ||
233 | #define PMX_SSP2_PL_44_45_VAL ((0x4 << 12) | (0x4 << 15)) | ||
234 | |||
235 | #define PMX_PL_46_47_MASK (0x3F << 18) | ||
236 | #define PMX_SDHCI_PL_46_47_VAL 0 | ||
237 | #define PMX_FSMC_EMI_PL_46_47_VAL ((0x2 << 18) | (0x2 << 21)) | ||
238 | #define PMX_SSP2_PL_46_47_VAL ((0x4 << 18) | (0x4 << 21)) | ||
239 | |||
240 | #define PMX_PL_48_49_MASK (0x3F << 24) | ||
241 | #define PMX_SDHCI_PL_48_49_VAL 0 | ||
242 | #define PMX_FSMC_EMI_PL_48_49_VAL ((0x2 << 24) | (0x2 << 27)) | ||
243 | #define PMX_SSP1_PL_48_49_VAL ((0x4 << 24) | (0x4 << 27)) | ||
244 | |||
245 | #define IP_SEL_PAD_50_59_REG 0x00B8 | ||
246 | #define PMX_PL_50_51_MASK (0x3F << 0) | ||
247 | #define PMX_EMI_PL_50_51_VAL ((0x2 << 0) | (0x2 << 3)) | ||
248 | #define PMX_SSP1_PL_50_51_VAL ((0x4 << 0) | (0x4 << 3)) | ||
249 | #define PMX_PL_50_MASK (0x7 << 0) | ||
250 | #define PMX_PL_51_MASK (0x7 << 3) | ||
251 | #define PMX_SDHCI_PL_50_VAL 0 | ||
252 | #define PMX_SDHCI_CD_PL_51_VAL 0 | ||
253 | |||
254 | #define PMX_PL_52_53_MASK (0x3F << 6) | ||
255 | #define PMX_FSMC_PL_52_53_VAL 0 | ||
256 | #define PMX_EMI_PL_52_53_VAL ((0x2 << 6) | (0x2 << 9)) | ||
257 | #define PMX_UART3_PL_52_53_VAL ((0x4 << 6) | (0x4 << 9)) | ||
258 | |||
259 | #define PMX_PL_54_55_56_MASK (0x1FF << 12) | ||
260 | #define PMX_FSMC_EMI_PL_54_55_56_VAL ((0x2 << 12) | (0x2 << 15) | (0x2 << 18)) | ||
261 | |||
262 | #define PMX_PL_57_MASK (0x7 << 21) | ||
263 | #define PMX_FSMC_PL_57_VAL 0 | ||
264 | #define PMX_PWM3_PL_57_VAL (0x4 << 21) | ||
265 | |||
266 | #define PMX_PL_58_59_MASK (0x3F << 24) | ||
267 | #define PMX_PL_58_MASK (0x7 << 24) | ||
268 | #define PMX_PL_59_MASK (0x7 << 27) | ||
269 | #define PMX_FSMC_EMI_PL_58_59_VAL ((0x2 << 24) | (0x2 << 27)) | ||
270 | #define PMX_PWM2_PL_58_VAL (0x4 << 24) | ||
271 | #define PMX_PWM1_PL_59_VAL (0x4 << 27) | ||
272 | |||
273 | #define IP_SEL_PAD_60_69_REG 0x00BC | ||
274 | #define PMX_PL_60_MASK (0x7 << 0) | ||
275 | #define PMX_FSMC_PL_60_VAL 0 | ||
276 | #define PMX_PWM0_PL_60_VAL (0x4 << 0) | ||
277 | |||
278 | #define PMX_PL_61_TO_64_MASK (0xFFF << 3) | ||
279 | #define PMX_FSMC_PL_61_TO_64_VAL ((0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12)) | ||
280 | #define PMX_SSP2_PL_61_TO_64_VAL ((0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12)) | ||
281 | |||
282 | #define PMX_PL_65_TO_68_MASK (0xFFF << 15) | ||
283 | #define PMX_FSMC_PL_65_TO_68_VAL ((0x2 << 15) | (0x2 << 18) | (0x2 << 21) | (0x2 << 24)) | ||
284 | #define PMX_SSP1_PL_65_TO_68_VAL ((0x4 << 15) | (0x4 << 18) | (0x4 << 21) | (0x4 << 24)) | ||
285 | |||
286 | #define PMX_PL_69_MASK (0x7 << 27) | ||
287 | #define PMX_CLCD_PL_69_VAL (0) | ||
288 | #define PMX_EMI_PL_69_VAL (0x2 << 27) | ||
289 | #define PMX_SPP_PL_69_VAL (0x3 << 27) | ||
290 | #define PMX_UART5_PL_69_VAL (0x4 << 27) | ||
291 | |||
292 | #define IP_SEL_PAD_70_79_REG 0x00C0 | ||
293 | #define PMX_PL_70_MASK (0x7 << 0) | ||
294 | #define PMX_CLCD_PL_70_VAL (0) | ||
295 | #define PMX_FSMC_EMI_PL_70_VAL (0x2 << 0) | ||
296 | #define PMX_SPP_PL_70_VAL (0x3 << 0) | ||
297 | #define PMX_UART5_PL_70_VAL (0x4 << 0) | ||
298 | |||
299 | #define PMX_PL_71_72_MASK (0x3F << 3) | ||
300 | #define PMX_CLCD_PL_71_72_VAL (0) | ||
301 | #define PMX_FSMC_EMI_PL_71_72_VAL ((0x2 << 3) | (0x2 << 6)) | ||
302 | #define PMX_SPP_PL_71_72_VAL ((0x3 << 3) | (0x3 << 6)) | ||
303 | #define PMX_UART4_PL_71_72_VAL ((0x4 << 3) | (0x4 << 6)) | ||
304 | |||
305 | #define PMX_PL_73_MASK (0x7 << 9) | ||
306 | #define PMX_CLCD_PL_73_VAL (0) | ||
307 | #define PMX_FSMC_EMI_PL_73_VAL (0x2 << 9) | ||
308 | #define PMX_SPP_PL_73_VAL (0x3 << 9) | ||
309 | #define PMX_UART3_PL_73_VAL (0x4 << 9) | ||
310 | |||
311 | #define PMX_PL_74_MASK (0x7 << 12) | ||
312 | #define PMX_CLCD_PL_74_VAL (0) | ||
313 | #define PMX_EMI_PL_74_VAL (0x2 << 12) | ||
314 | #define PMX_SPP_PL_74_VAL (0x3 << 12) | ||
315 | #define PMX_UART3_PL_74_VAL (0x4 << 12) | ||
316 | |||
317 | #define PMX_PL_75_76_MASK (0x3F << 15) | ||
318 | #define PMX_CLCD_PL_75_76_VAL (0) | ||
319 | #define PMX_EMI_PL_75_76_VAL ((0x2 << 15) | (0x2 << 18)) | ||
320 | #define PMX_SPP_PL_75_76_VAL ((0x3 << 15) | (0x3 << 18)) | ||
321 | #define PMX_I2C2_PL_75_76_VAL ((0x4 << 15) | (0x4 << 18)) | ||
322 | |||
323 | #define PMX_PL_77_78_79_MASK (0x1FF << 21) | ||
324 | #define PMX_CLCD_PL_77_78_79_VAL (0) | ||
325 | #define PMX_EMI_PL_77_78_79_VAL ((0x2 << 21) | (0x2 << 24) | (0x2 << 27)) | ||
326 | #define PMX_SPP_PL_77_78_79_VAL ((0x3 << 21) | (0x3 << 24) | (0x3 << 27)) | ||
327 | #define PMX_RS485_PL_77_78_79_VAL ((0x4 << 21) | (0x4 << 24) | (0x4 << 27)) | ||
328 | |||
329 | #define IP_SEL_PAD_80_89_REG 0x00C4 | ||
330 | #define PMX_PL_80_TO_85_MASK (0x3FFFF << 0) | ||
331 | #define PMX_CLCD_PL_80_TO_85_VAL 0 | ||
332 | #define PMX_MII2_PL_80_TO_85_VAL ((0x1 << 0) | (0x1 << 3) | (0x1 << 6) | (0x1 << 9) | (0x1 << 12) | (0x1 << 15)) | ||
333 | #define PMX_EMI_PL_80_TO_85_VAL ((0x2 << 0) | (0x2 << 3) | (0x2 << 6) | (0x2 << 9) | (0x2 << 12) | (0x2 << 15)) | ||
334 | #define PMX_SPP_PL_80_TO_85_VAL ((0x3 << 0) | (0x3 << 3) | (0x3 << 6) | (0x3 << 9) | (0x3 << 12) | (0x3 << 15)) | ||
335 | #define PMX_UART1_ENH_PL_80_TO_85_VAL ((0x4 << 0) | (0x4 << 3) | (0x4 << 6) | (0x4 << 9) | (0x4 << 12) | (0x4 << 15)) | ||
336 | |||
337 | #define PMX_PL_86_87_MASK (0x3F << 18) | ||
338 | #define PMX_PL_86_MASK (0x7 << 18) | ||
339 | #define PMX_PL_87_MASK (0x7 << 21) | ||
340 | #define PMX_CLCD_PL_86_87_VAL 0 | ||
341 | #define PMX_MII2_PL_86_87_VAL ((0x1 << 18) | (0x1 << 21)) | ||
342 | #define PMX_EMI_PL_86_87_VAL ((0x2 << 18) | (0x2 << 21)) | ||
343 | #define PMX_PWM3_PL_86_VAL (0x4 << 18) | ||
344 | #define PMX_PWM2_PL_87_VAL (0x4 << 21) | ||
345 | |||
346 | #define PMX_PL_88_89_MASK (0x3F << 24) | ||
347 | #define PMX_CLCD_PL_88_89_VAL 0 | ||
348 | #define PMX_MII2_PL_88_89_VAL ((0x1 << 24) | (0x1 << 27)) | ||
349 | #define PMX_EMI_PL_88_89_VAL ((0x2 << 24) | (0x2 << 27)) | ||
350 | #define PMX_UART6_PL_88_89_VAL ((0x3 << 24) | (0x3 << 27)) | ||
351 | #define PMX_PWM0_1_PL_88_89_VAL ((0x4 << 24) | (0x4 << 27)) | ||
352 | |||
353 | #define IP_SEL_PAD_90_99_REG 0x00C8 | ||
354 | #define PMX_PL_90_91_MASK (0x3F << 0) | ||
355 | #define PMX_CLCD_PL_90_91_VAL 0 | ||
356 | #define PMX_MII2_PL_90_91_VAL ((0x1 << 0) | (0x1 << 3)) | ||
357 | #define PMX_EMI1_PL_90_91_VAL ((0x2 << 0) | (0x2 << 3)) | ||
358 | #define PMX_UART5_PL_90_91_VAL ((0x3 << 0) | (0x3 << 3)) | ||
359 | #define PMX_SSP2_PL_90_91_VAL ((0x4 << 0) | (0x4 << 3)) | ||
360 | |||
361 | #define PMX_PL_92_93_MASK (0x3F << 6) | ||
362 | #define PMX_CLCD_PL_92_93_VAL 0 | ||
363 | #define PMX_MII2_PL_92_93_VAL ((0x1 << 6) | (0x1 << 9)) | ||
364 | #define PMX_EMI1_PL_92_93_VAL ((0x2 << 6) | (0x2 << 9)) | ||
365 | #define PMX_UART4_PL_92_93_VAL ((0x3 << 6) | (0x3 << 9)) | ||
366 | #define PMX_SSP2_PL_92_93_VAL ((0x4 << 6) | (0x4 << 9)) | ||
367 | |||
368 | #define PMX_PL_94_95_MASK (0x3F << 12) | ||
369 | #define PMX_CLCD_PL_94_95_VAL 0 | ||
370 | #define PMX_MII2_PL_94_95_VAL ((0x1 << 12) | (0x1 << 15)) | ||
371 | #define PMX_EMI1_PL_94_95_VAL ((0x2 << 12) | (0x2 << 15)) | ||
372 | #define PMX_UART3_PL_94_95_VAL ((0x3 << 12) | (0x3 << 15)) | ||
373 | #define PMX_SSP1_PL_94_95_VAL ((0x4 << 12) | (0x4 << 15)) | ||
374 | |||
375 | #define PMX_PL_96_97_MASK (0x3F << 18) | ||
376 | #define PMX_CLCD_PL_96_97_VAL 0 | ||
377 | #define PMX_MII2_PL_96_97_VAL ((0x1 << 18) | (0x1 << 21)) | ||
378 | #define PMX_EMI1_PL_96_97_VAL ((0x2 << 18) | (0x2 << 21)) | ||
379 | #define PMX_I2C2_PL_96_97_VAL ((0x3 << 18) | (0x3 << 21)) | ||
380 | #define PMX_SSP1_PL_96_97_VAL ((0x4 << 18) | (0x4 << 21)) | ||
381 | |||
382 | #define PMX_PL_98_MASK (0x7 << 24) | ||
383 | #define PMX_CLCD_PL_98_VAL 0 | ||
384 | #define PMX_I2C1_PL_98_VAL (0x2 << 24) | ||
385 | #define PMX_UART3_PL_98_VAL (0x4 << 24) | ||
386 | |||
387 | #define PMX_PL_99_MASK (0x7 << 27) | ||
388 | #define PMX_SDHCI_PL_99_VAL 0 | ||
389 | #define PMX_I2C1_PL_99_VAL (0x2 << 27) | ||
390 | #define PMX_UART3_PL_99_VAL (0x4 << 27) | ||
391 | |||
392 | #define IP_SEL_MIX_PAD_REG 0x00CC | ||
393 | #define PMX_PL_100_101_MASK (0x3F << 0) | ||
394 | #define PMX_SDHCI_PL_100_101_VAL 0 | ||
395 | #define PMX_UART4_PL_100_101_VAL ((0x4 << 0) | (0x4 << 3)) | ||
396 | |||
397 | #define PMX_SSP1_PORT_SEL_MASK (0x7 << 8) | ||
398 | #define PMX_SSP1_PORT_94_TO_97_VAL 0 | ||
399 | #define PMX_SSP1_PORT_65_TO_68_VAL (0x1 << 8) | ||
400 | #define PMX_SSP1_PORT_48_TO_51_VAL (0x2 << 8) | ||
401 | #define PMX_SSP1_PORT_36_TO_39_VAL (0x3 << 8) | ||
402 | #define PMX_SSP1_PORT_17_TO_20_VAL (0x4 << 8) | ||
403 | |||
404 | #define PMX_SSP2_PORT_SEL_MASK (0x7 << 11) | ||
405 | #define PMX_SSP2_PORT_90_TO_93_VAL 0 | ||
406 | #define PMX_SSP2_PORT_61_TO_64_VAL (0x1 << 11) | ||
407 | #define PMX_SSP2_PORT_44_TO_47_VAL (0x2 << 11) | ||
408 | #define PMX_SSP2_PORT_32_TO_35_VAL (0x3 << 11) | ||
409 | #define PMX_SSP2_PORT_13_TO_16_VAL (0x4 << 11) | ||
410 | |||
411 | #define PMX_UART1_ENH_PORT_SEL_MASK (0x3 << 14) | ||
412 | #define PMX_UART1_ENH_PORT_81_TO_85_VAL 0 | ||
413 | #define PMX_UART1_ENH_PORT_44_45_34_36_VAL (0x1 << 14) | ||
414 | #define PMX_UART1_ENH_PORT_32_TO_34_36_VAL (0x2 << 14) | ||
415 | #define PMX_UART1_ENH_PORT_3_TO_5_7_VAL (0x3 << 14) | ||
416 | |||
417 | #define PMX_UART3_PORT_SEL_MASK (0x7 << 16) | ||
418 | #define PMX_UART3_PORT_94_VAL 0 | ||
419 | #define PMX_UART3_PORT_73_VAL (0x1 << 16) | ||
420 | #define PMX_UART3_PORT_52_VAL (0x2 << 16) | ||
421 | #define PMX_UART3_PORT_41_VAL (0x3 << 16) | ||
422 | #define PMX_UART3_PORT_15_VAL (0x4 << 16) | ||
423 | #define PMX_UART3_PORT_8_VAL (0x5 << 16) | ||
424 | #define PMX_UART3_PORT_99_VAL (0x6 << 16) | ||
425 | |||
426 | #define PMX_UART4_PORT_SEL_MASK (0x7 << 19) | ||
427 | #define PMX_UART4_PORT_92_VAL 0 | ||
428 | #define PMX_UART4_PORT_71_VAL (0x1 << 19) | ||
429 | #define PMX_UART4_PORT_39_VAL (0x2 << 19) | ||
430 | #define PMX_UART4_PORT_13_VAL (0x3 << 19) | ||
431 | #define PMX_UART4_PORT_6_VAL (0x4 << 19) | ||
432 | #define PMX_UART4_PORT_101_VAL (0x5 << 19) | ||
433 | |||
434 | #define PMX_UART5_PORT_SEL_MASK (0x3 << 22) | ||
435 | #define PMX_UART5_PORT_90_VAL 0 | ||
436 | #define PMX_UART5_PORT_69_VAL (0x1 << 22) | ||
437 | #define PMX_UART5_PORT_37_VAL (0x2 << 22) | ||
438 | #define PMX_UART5_PORT_4_VAL (0x3 << 22) | ||
439 | |||
440 | #define PMX_UART6_PORT_SEL_MASK (0x1 << 24) | ||
441 | #define PMX_UART6_PORT_88_VAL 0 | ||
442 | #define PMX_UART6_PORT_2_VAL (0x1 << 24) | ||
443 | |||
444 | #define PMX_I2C1_PORT_SEL_MASK (0x1 << 25) | ||
445 | #define PMX_I2C1_PORT_8_9_VAL 0 | ||
446 | #define PMX_I2C1_PORT_98_99_VAL (0x1 << 25) | ||
447 | |||
448 | #define PMX_I2C2_PORT_SEL_MASK (0x3 << 26) | ||
449 | #define PMX_I2C2_PORT_96_97_VAL 0 | ||
450 | #define PMX_I2C2_PORT_75_76_VAL (0x1 << 26) | ||
451 | #define PMX_I2C2_PORT_19_20_VAL (0x2 << 26) | ||
452 | #define PMX_I2C2_PORT_2_3_VAL (0x3 << 26) | ||
453 | #define PMX_I2C2_PORT_0_1_VAL (0x4 << 26) | ||
454 | |||
455 | #define PMX_SDHCI_CD_PORT_SEL_MASK (0x1 << 29) | ||
456 | #define PMX_SDHCI_CD_PORT_12_VAL 0 | ||
457 | #define PMX_SDHCI_CD_PORT_51_VAL (0x1 << 29) | ||
458 | |||
459 | /* Pad multiplexing for CLCD device */ | ||
460 | static const unsigned clcd_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, | ||
461 | 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, | ||
462 | 97 }; | ||
463 | static struct spear_muxreg clcd_muxreg[] = { | ||
464 | { | ||
465 | .reg = IP_SEL_PAD_60_69_REG, | ||
466 | .mask = PMX_PL_69_MASK, | ||
467 | .val = PMX_CLCD_PL_69_VAL, | ||
468 | }, { | ||
469 | .reg = IP_SEL_PAD_70_79_REG, | ||
470 | .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | | ||
471 | PMX_PL_74_MASK | PMX_PL_75_76_MASK | | ||
472 | PMX_PL_77_78_79_MASK, | ||
473 | .val = PMX_CLCD_PL_70_VAL | PMX_CLCD_PL_71_72_VAL | | ||
474 | PMX_CLCD_PL_73_VAL | PMX_CLCD_PL_74_VAL | | ||
475 | PMX_CLCD_PL_75_76_VAL | PMX_CLCD_PL_77_78_79_VAL, | ||
476 | }, { | ||
477 | .reg = IP_SEL_PAD_80_89_REG, | ||
478 | .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | | ||
479 | PMX_PL_88_89_MASK, | ||
480 | .val = PMX_CLCD_PL_80_TO_85_VAL | PMX_CLCD_PL_86_87_VAL | | ||
481 | PMX_CLCD_PL_88_89_VAL, | ||
482 | }, { | ||
483 | .reg = IP_SEL_PAD_90_99_REG, | ||
484 | .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | | ||
485 | PMX_PL_94_95_MASK | PMX_PL_96_97_MASK | PMX_PL_98_MASK, | ||
486 | .val = PMX_CLCD_PL_90_91_VAL | PMX_CLCD_PL_92_93_VAL | | ||
487 | PMX_CLCD_PL_94_95_VAL | PMX_CLCD_PL_96_97_VAL | | ||
488 | PMX_CLCD_PL_98_VAL, | ||
489 | }, | ||
490 | }; | ||
491 | |||
492 | static struct spear_modemux clcd_modemux[] = { | ||
493 | { | ||
494 | .modes = EXTENDED_MODE, | ||
495 | .muxregs = clcd_muxreg, | ||
496 | .nmuxregs = ARRAY_SIZE(clcd_muxreg), | ||
497 | }, | ||
498 | }; | ||
499 | |||
500 | static struct spear_pingroup clcd_pingroup = { | ||
501 | .name = "clcd_grp", | ||
502 | .pins = clcd_pins, | ||
503 | .npins = ARRAY_SIZE(clcd_pins), | ||
504 | .modemuxs = clcd_modemux, | ||
505 | .nmodemuxs = ARRAY_SIZE(clcd_modemux), | ||
506 | }; | ||
507 | |||
508 | static const char *const clcd_grps[] = { "clcd_grp" }; | ||
509 | static struct spear_function clcd_function = { | ||
510 | .name = "clcd", | ||
511 | .groups = clcd_grps, | ||
512 | .ngroups = ARRAY_SIZE(clcd_grps), | ||
513 | }; | ||
514 | |||
515 | /* Pad multiplexing for EMI (Parallel NOR flash) device */ | ||
516 | static const unsigned emi_pins[] = { 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, | ||
517 | 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, | ||
518 | 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, | ||
519 | 93, 94, 95, 96, 97 }; | ||
520 | static struct spear_muxreg emi_muxreg[] = { | ||
521 | { | ||
522 | .reg = PMX_CONFIG_REG, | ||
523 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
524 | .val = 0, | ||
525 | }, | ||
526 | }; | ||
527 | |||
528 | static struct spear_muxreg emi_ext_muxreg[] = { | ||
529 | { | ||
530 | .reg = IP_SEL_PAD_40_49_REG, | ||
531 | .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, | ||
532 | .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, | ||
533 | }, { | ||
534 | .reg = IP_SEL_PAD_50_59_REG, | ||
535 | .mask = PMX_PL_50_51_MASK | PMX_PL_52_53_MASK | | ||
536 | PMX_PL_54_55_56_MASK | PMX_PL_58_59_MASK, | ||
537 | .val = PMX_EMI_PL_50_51_VAL | PMX_EMI_PL_52_53_VAL | | ||
538 | PMX_FSMC_EMI_PL_54_55_56_VAL | | ||
539 | PMX_FSMC_EMI_PL_58_59_VAL, | ||
540 | }, { | ||
541 | .reg = IP_SEL_PAD_60_69_REG, | ||
542 | .mask = PMX_PL_69_MASK, | ||
543 | .val = PMX_EMI_PL_69_VAL, | ||
544 | }, { | ||
545 | .reg = IP_SEL_PAD_70_79_REG, | ||
546 | .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | | ||
547 | PMX_PL_74_MASK | PMX_PL_75_76_MASK | | ||
548 | PMX_PL_77_78_79_MASK, | ||
549 | .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | | ||
550 | PMX_FSMC_EMI_PL_73_VAL | PMX_EMI_PL_74_VAL | | ||
551 | PMX_EMI_PL_75_76_VAL | PMX_EMI_PL_77_78_79_VAL, | ||
552 | }, { | ||
553 | .reg = IP_SEL_PAD_80_89_REG, | ||
554 | .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | | ||
555 | PMX_PL_88_89_MASK, | ||
556 | .val = PMX_EMI_PL_80_TO_85_VAL | PMX_EMI_PL_86_87_VAL | | ||
557 | PMX_EMI_PL_88_89_VAL, | ||
558 | }, { | ||
559 | .reg = IP_SEL_PAD_90_99_REG, | ||
560 | .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | | ||
561 | PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, | ||
562 | .val = PMX_EMI1_PL_90_91_VAL | PMX_EMI1_PL_92_93_VAL | | ||
563 | PMX_EMI1_PL_94_95_VAL | PMX_EMI1_PL_96_97_VAL, | ||
564 | }, { | ||
565 | .reg = EXT_CTRL_REG, | ||
566 | .mask = EMI_FSMC_DYNAMIC_MUX_MASK, | ||
567 | .val = EMI_FSMC_DYNAMIC_MUX_MASK, | ||
568 | }, | ||
569 | }; | ||
570 | |||
571 | static struct spear_modemux emi_modemux[] = { | ||
572 | { | ||
573 | .modes = AUTO_EXP_MODE | EXTENDED_MODE, | ||
574 | .muxregs = emi_muxreg, | ||
575 | .nmuxregs = ARRAY_SIZE(emi_muxreg), | ||
576 | }, { | ||
577 | .modes = EXTENDED_MODE, | ||
578 | .muxregs = emi_ext_muxreg, | ||
579 | .nmuxregs = ARRAY_SIZE(emi_ext_muxreg), | ||
580 | }, | ||
581 | }; | ||
582 | |||
583 | static struct spear_pingroup emi_pingroup = { | ||
584 | .name = "emi_grp", | ||
585 | .pins = emi_pins, | ||
586 | .npins = ARRAY_SIZE(emi_pins), | ||
587 | .modemuxs = emi_modemux, | ||
588 | .nmodemuxs = ARRAY_SIZE(emi_modemux), | ||
589 | }; | ||
590 | |||
591 | static const char *const emi_grps[] = { "emi_grp" }; | ||
592 | static struct spear_function emi_function = { | ||
593 | .name = "emi", | ||
594 | .groups = emi_grps, | ||
595 | .ngroups = ARRAY_SIZE(emi_grps), | ||
596 | }; | ||
597 | |||
598 | /* Pad multiplexing for FSMC (NAND flash) device */ | ||
599 | static const unsigned fsmc_8bit_pins[] = { 52, 53, 54, 55, 56, 57, 58, 59, 60, | ||
600 | 61, 62, 63, 64, 65, 66, 67, 68 }; | ||
601 | static struct spear_muxreg fsmc_8bit_muxreg[] = { | ||
602 | { | ||
603 | .reg = IP_SEL_PAD_50_59_REG, | ||
604 | .mask = PMX_PL_52_53_MASK | PMX_PL_54_55_56_MASK | | ||
605 | PMX_PL_57_MASK | PMX_PL_58_59_MASK, | ||
606 | .val = PMX_FSMC_PL_52_53_VAL | PMX_FSMC_EMI_PL_54_55_56_VAL | | ||
607 | PMX_FSMC_PL_57_VAL | PMX_FSMC_EMI_PL_58_59_VAL, | ||
608 | }, { | ||
609 | .reg = IP_SEL_PAD_60_69_REG, | ||
610 | .mask = PMX_PL_60_MASK | PMX_PL_61_TO_64_MASK | | ||
611 | PMX_PL_65_TO_68_MASK, | ||
612 | .val = PMX_FSMC_PL_60_VAL | PMX_FSMC_PL_61_TO_64_VAL | | ||
613 | PMX_FSMC_PL_65_TO_68_VAL, | ||
614 | }, { | ||
615 | .reg = EXT_CTRL_REG, | ||
616 | .mask = EMI_FSMC_DYNAMIC_MUX_MASK, | ||
617 | .val = EMI_FSMC_DYNAMIC_MUX_MASK, | ||
618 | }, | ||
619 | }; | ||
620 | |||
621 | static struct spear_modemux fsmc_8bit_modemux[] = { | ||
622 | { | ||
623 | .modes = EXTENDED_MODE, | ||
624 | .muxregs = fsmc_8bit_muxreg, | ||
625 | .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), | ||
626 | }, | ||
627 | }; | ||
628 | |||
629 | static struct spear_pingroup fsmc_8bit_pingroup = { | ||
630 | .name = "fsmc_8bit_grp", | ||
631 | .pins = fsmc_8bit_pins, | ||
632 | .npins = ARRAY_SIZE(fsmc_8bit_pins), | ||
633 | .modemuxs = fsmc_8bit_modemux, | ||
634 | .nmodemuxs = ARRAY_SIZE(fsmc_8bit_modemux), | ||
635 | }; | ||
636 | |||
637 | static const unsigned fsmc_16bit_pins[] = { 46, 47, 48, 49, 52, 53, 54, 55, 56, | ||
638 | 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 70, 71, 72, 73 }; | ||
639 | static struct spear_muxreg fsmc_16bit_autoexp_muxreg[] = { | ||
640 | { | ||
641 | .reg = PMX_CONFIG_REG, | ||
642 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
643 | .val = 0, | ||
644 | }, | ||
645 | }; | ||
646 | |||
647 | static struct spear_muxreg fsmc_16bit_muxreg[] = { | ||
648 | { | ||
649 | .reg = IP_SEL_PAD_40_49_REG, | ||
650 | .mask = PMX_PL_46_47_MASK | PMX_PL_48_49_MASK, | ||
651 | .val = PMX_FSMC_EMI_PL_46_47_VAL | PMX_FSMC_EMI_PL_48_49_VAL, | ||
652 | }, { | ||
653 | .reg = IP_SEL_PAD_70_79_REG, | ||
654 | .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK, | ||
655 | .val = PMX_FSMC_EMI_PL_70_VAL | PMX_FSMC_EMI_PL_71_72_VAL | | ||
656 | PMX_FSMC_EMI_PL_73_VAL, | ||
657 | } | ||
658 | }; | ||
659 | |||
660 | static struct spear_modemux fsmc_16bit_modemux[] = { | ||
661 | { | ||
662 | .modes = EXTENDED_MODE, | ||
663 | .muxregs = fsmc_8bit_muxreg, | ||
664 | .nmuxregs = ARRAY_SIZE(fsmc_8bit_muxreg), | ||
665 | }, { | ||
666 | .modes = AUTO_EXP_MODE | EXTENDED_MODE, | ||
667 | .muxregs = fsmc_16bit_autoexp_muxreg, | ||
668 | .nmuxregs = ARRAY_SIZE(fsmc_16bit_autoexp_muxreg), | ||
669 | }, { | ||
670 | .modes = EXTENDED_MODE, | ||
671 | .muxregs = fsmc_16bit_muxreg, | ||
672 | .nmuxregs = ARRAY_SIZE(fsmc_16bit_muxreg), | ||
673 | }, | ||
674 | }; | ||
675 | |||
676 | static struct spear_pingroup fsmc_16bit_pingroup = { | ||
677 | .name = "fsmc_16bit_grp", | ||
678 | .pins = fsmc_16bit_pins, | ||
679 | .npins = ARRAY_SIZE(fsmc_16bit_pins), | ||
680 | .modemuxs = fsmc_16bit_modemux, | ||
681 | .nmodemuxs = ARRAY_SIZE(fsmc_16bit_modemux), | ||
682 | }; | ||
683 | |||
684 | static const char *const fsmc_grps[] = { "fsmc_8bit_grp", "fsmc_16bit_grp" }; | ||
685 | static struct spear_function fsmc_function = { | ||
686 | .name = "fsmc", | ||
687 | .groups = fsmc_grps, | ||
688 | .ngroups = ARRAY_SIZE(fsmc_grps), | ||
689 | }; | ||
690 | |||
691 | /* Pad multiplexing for SPP device */ | ||
692 | static const unsigned spp_pins[] = { 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, | ||
693 | 80, 81, 82, 83, 84, 85 }; | ||
694 | static struct spear_muxreg spp_muxreg[] = { | ||
695 | { | ||
696 | .reg = IP_SEL_PAD_60_69_REG, | ||
697 | .mask = PMX_PL_69_MASK, | ||
698 | .val = PMX_SPP_PL_69_VAL, | ||
699 | }, { | ||
700 | .reg = IP_SEL_PAD_70_79_REG, | ||
701 | .mask = PMX_PL_70_MASK | PMX_PL_71_72_MASK | PMX_PL_73_MASK | | ||
702 | PMX_PL_74_MASK | PMX_PL_75_76_MASK | | ||
703 | PMX_PL_77_78_79_MASK, | ||
704 | .val = PMX_SPP_PL_70_VAL | PMX_SPP_PL_71_72_VAL | | ||
705 | PMX_SPP_PL_73_VAL | PMX_SPP_PL_74_VAL | | ||
706 | PMX_SPP_PL_75_76_VAL | PMX_SPP_PL_77_78_79_VAL, | ||
707 | }, { | ||
708 | .reg = IP_SEL_PAD_80_89_REG, | ||
709 | .mask = PMX_PL_80_TO_85_MASK, | ||
710 | .val = PMX_SPP_PL_80_TO_85_VAL, | ||
711 | }, | ||
712 | }; | ||
713 | |||
714 | static struct spear_modemux spp_modemux[] = { | ||
715 | { | ||
716 | .modes = EXTENDED_MODE, | ||
717 | .muxregs = spp_muxreg, | ||
718 | .nmuxregs = ARRAY_SIZE(spp_muxreg), | ||
719 | }, | ||
720 | }; | ||
721 | |||
722 | static struct spear_pingroup spp_pingroup = { | ||
723 | .name = "spp_grp", | ||
724 | .pins = spp_pins, | ||
725 | .npins = ARRAY_SIZE(spp_pins), | ||
726 | .modemuxs = spp_modemux, | ||
727 | .nmodemuxs = ARRAY_SIZE(spp_modemux), | ||
728 | }; | ||
729 | |||
730 | static const char *const spp_grps[] = { "spp_grp" }; | ||
731 | static struct spear_function spp_function = { | ||
732 | .name = "spp", | ||
733 | .groups = spp_grps, | ||
734 | .ngroups = ARRAY_SIZE(spp_grps), | ||
735 | }; | ||
736 | |||
737 | /* Pad multiplexing for SDHCI device */ | ||
738 | static const unsigned sdhci_led_pins[] = { 34 }; | ||
739 | static struct spear_muxreg sdhci_led_muxreg[] = { | ||
740 | { | ||
741 | .reg = PMX_CONFIG_REG, | ||
742 | .mask = PMX_SSP_CS_MASK, | ||
743 | .val = 0, | ||
744 | }, | ||
745 | }; | ||
746 | |||
747 | static struct spear_muxreg sdhci_led_ext_muxreg[] = { | ||
748 | { | ||
749 | .reg = IP_SEL_PAD_30_39_REG, | ||
750 | .mask = PMX_PL_34_MASK, | ||
751 | .val = PMX_PWM2_PL_34_VAL, | ||
752 | }, | ||
753 | }; | ||
754 | |||
755 | static struct spear_modemux sdhci_led_modemux[] = { | ||
756 | { | ||
757 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, | ||
758 | .muxregs = sdhci_led_muxreg, | ||
759 | .nmuxregs = ARRAY_SIZE(sdhci_led_muxreg), | ||
760 | }, { | ||
761 | .modes = EXTENDED_MODE, | ||
762 | .muxregs = sdhci_led_ext_muxreg, | ||
763 | .nmuxregs = ARRAY_SIZE(sdhci_led_ext_muxreg), | ||
764 | }, | ||
765 | }; | ||
766 | |||
767 | static struct spear_pingroup sdhci_led_pingroup = { | ||
768 | .name = "sdhci_led_grp", | ||
769 | .pins = sdhci_led_pins, | ||
770 | .npins = ARRAY_SIZE(sdhci_led_pins), | ||
771 | .modemuxs = sdhci_led_modemux, | ||
772 | .nmodemuxs = ARRAY_SIZE(sdhci_led_modemux), | ||
773 | }; | ||
774 | |||
775 | static const unsigned sdhci_cd_12_pins[] = { 12, 43, 44, 45, 46, 47, 48, 49, | ||
776 | 50}; | ||
777 | static const unsigned sdhci_cd_51_pins[] = { 43, 44, 45, 46, 47, 48, 49, 50, 51 | ||
778 | }; | ||
779 | static struct spear_muxreg sdhci_muxreg[] = { | ||
780 | { | ||
781 | .reg = PMX_CONFIG_REG, | ||
782 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
783 | .val = 0, | ||
784 | }, | ||
785 | }; | ||
786 | |||
787 | static struct spear_muxreg sdhci_ext_muxreg[] = { | ||
788 | { | ||
789 | .reg = IP_SEL_PAD_40_49_REG, | ||
790 | .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK | PMX_PL_46_47_MASK | | ||
791 | PMX_PL_48_49_MASK, | ||
792 | .val = PMX_SDHCI_PL_43_VAL | PMX_SDHCI_PL_44_45_VAL | | ||
793 | PMX_SDHCI_PL_46_47_VAL | PMX_SDHCI_PL_48_49_VAL, | ||
794 | }, { | ||
795 | .reg = IP_SEL_PAD_50_59_REG, | ||
796 | .mask = PMX_PL_50_MASK, | ||
797 | .val = PMX_SDHCI_PL_50_VAL, | ||
798 | }, { | ||
799 | .reg = IP_SEL_PAD_90_99_REG, | ||
800 | .mask = PMX_PL_99_MASK, | ||
801 | .val = PMX_SDHCI_PL_99_VAL, | ||
802 | }, { | ||
803 | .reg = IP_SEL_MIX_PAD_REG, | ||
804 | .mask = PMX_PL_100_101_MASK, | ||
805 | .val = PMX_SDHCI_PL_100_101_VAL, | ||
806 | }, | ||
807 | }; | ||
808 | |||
809 | static struct spear_muxreg sdhci_cd_12_muxreg[] = { | ||
810 | { | ||
811 | .reg = PMX_CONFIG_REG, | ||
812 | .mask = PMX_MII_MASK, | ||
813 | .val = 0, | ||
814 | }, { | ||
815 | .reg = IP_SEL_PAD_10_19_REG, | ||
816 | .mask = PMX_PL_12_MASK, | ||
817 | .val = PMX_SDHCI_CD_PL_12_VAL, | ||
818 | }, { | ||
819 | .reg = IP_SEL_MIX_PAD_REG, | ||
820 | .mask = PMX_SDHCI_CD_PORT_SEL_MASK, | ||
821 | .val = PMX_SDHCI_CD_PORT_12_VAL, | ||
822 | }, | ||
823 | }; | ||
824 | |||
825 | static struct spear_muxreg sdhci_cd_51_muxreg[] = { | ||
826 | { | ||
827 | .reg = IP_SEL_PAD_50_59_REG, | ||
828 | .mask = PMX_PL_51_MASK, | ||
829 | .val = PMX_SDHCI_CD_PL_51_VAL, | ||
830 | }, { | ||
831 | .reg = IP_SEL_MIX_PAD_REG, | ||
832 | .mask = PMX_SDHCI_CD_PORT_SEL_MASK, | ||
833 | .val = PMX_SDHCI_CD_PORT_51_VAL, | ||
834 | }, | ||
835 | }; | ||
836 | |||
837 | #define pmx_sdhci_common_modemux \ | ||
838 | { \ | ||
839 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | \ | ||
840 | SMALL_PRINTERS_MODE | EXTENDED_MODE, \ | ||
841 | .muxregs = sdhci_muxreg, \ | ||
842 | .nmuxregs = ARRAY_SIZE(sdhci_muxreg), \ | ||
843 | }, { \ | ||
844 | .modes = EXTENDED_MODE, \ | ||
845 | .muxregs = sdhci_ext_muxreg, \ | ||
846 | .nmuxregs = ARRAY_SIZE(sdhci_ext_muxreg), \ | ||
847 | } | ||
848 | |||
849 | static struct spear_modemux sdhci_modemux[][3] = { | ||
850 | { | ||
851 | /* select pin 12 for cd */ | ||
852 | pmx_sdhci_common_modemux, | ||
853 | { | ||
854 | .modes = EXTENDED_MODE, | ||
855 | .muxregs = sdhci_cd_12_muxreg, | ||
856 | .nmuxregs = ARRAY_SIZE(sdhci_cd_12_muxreg), | ||
857 | }, | ||
858 | }, { | ||
859 | /* select pin 51 for cd */ | ||
860 | pmx_sdhci_common_modemux, | ||
861 | { | ||
862 | .modes = EXTENDED_MODE, | ||
863 | .muxregs = sdhci_cd_51_muxreg, | ||
864 | .nmuxregs = ARRAY_SIZE(sdhci_cd_51_muxreg), | ||
865 | }, | ||
866 | } | ||
867 | }; | ||
868 | |||
869 | static struct spear_pingroup sdhci_pingroup[] = { | ||
870 | { | ||
871 | .name = "sdhci_cd_12_grp", | ||
872 | .pins = sdhci_cd_12_pins, | ||
873 | .npins = ARRAY_SIZE(sdhci_cd_12_pins), | ||
874 | .modemuxs = sdhci_modemux[0], | ||
875 | .nmodemuxs = ARRAY_SIZE(sdhci_modemux[0]), | ||
876 | }, { | ||
877 | .name = "sdhci_cd_51_grp", | ||
878 | .pins = sdhci_cd_51_pins, | ||
879 | .npins = ARRAY_SIZE(sdhci_cd_51_pins), | ||
880 | .modemuxs = sdhci_modemux[1], | ||
881 | .nmodemuxs = ARRAY_SIZE(sdhci_modemux[1]), | ||
882 | }, | ||
883 | }; | ||
884 | |||
885 | static const char *const sdhci_grps[] = { "sdhci_cd_12_grp", "sdhci_cd_51_grp", | ||
886 | "sdhci_led_grp" }; | ||
887 | |||
888 | static struct spear_function sdhci_function = { | ||
889 | .name = "sdhci", | ||
890 | .groups = sdhci_grps, | ||
891 | .ngroups = ARRAY_SIZE(sdhci_grps), | ||
892 | }; | ||
893 | |||
894 | /* Pad multiplexing for I2S device */ | ||
895 | static const unsigned i2s_pins[] = { 35, 39, 40, 41, 42 }; | ||
896 | static struct spear_muxreg i2s_muxreg[] = { | ||
897 | { | ||
898 | .reg = PMX_CONFIG_REG, | ||
899 | .mask = PMX_SSP_CS_MASK, | ||
900 | .val = 0, | ||
901 | }, { | ||
902 | .reg = PMX_CONFIG_REG, | ||
903 | .mask = PMX_UART0_MODEM_MASK, | ||
904 | .val = 0, | ||
905 | }, | ||
906 | }; | ||
907 | |||
908 | static struct spear_muxreg i2s_ext_muxreg[] = { | ||
909 | { | ||
910 | .reg = IP_SEL_PAD_30_39_REG, | ||
911 | .mask = PMX_PL_35_MASK | PMX_PL_39_MASK, | ||
912 | .val = PMX_I2S_REF_CLK_PL_35_VAL | PMX_I2S_PL_39_VAL, | ||
913 | }, { | ||
914 | .reg = IP_SEL_PAD_40_49_REG, | ||
915 | .mask = PMX_PL_40_MASK | PMX_PL_41_42_MASK, | ||
916 | .val = PMX_I2S_PL_40_VAL | PMX_I2S_PL_41_42_VAL, | ||
917 | }, | ||
918 | }; | ||
919 | |||
920 | static struct spear_modemux i2s_modemux[] = { | ||
921 | { | ||
922 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, | ||
923 | .muxregs = i2s_muxreg, | ||
924 | .nmuxregs = ARRAY_SIZE(i2s_muxreg), | ||
925 | }, { | ||
926 | .modes = EXTENDED_MODE, | ||
927 | .muxregs = i2s_ext_muxreg, | ||
928 | .nmuxregs = ARRAY_SIZE(i2s_ext_muxreg), | ||
929 | }, | ||
930 | }; | ||
931 | |||
932 | static struct spear_pingroup i2s_pingroup = { | ||
933 | .name = "i2s_grp", | ||
934 | .pins = i2s_pins, | ||
935 | .npins = ARRAY_SIZE(i2s_pins), | ||
936 | .modemuxs = i2s_modemux, | ||
937 | .nmodemuxs = ARRAY_SIZE(i2s_modemux), | ||
938 | }; | ||
939 | |||
940 | static const char *const i2s_grps[] = { "i2s_grp" }; | ||
941 | static struct spear_function i2s_function = { | ||
942 | .name = "i2s", | ||
943 | .groups = i2s_grps, | ||
944 | .ngroups = ARRAY_SIZE(i2s_grps), | ||
945 | }; | ||
946 | |||
947 | /* Pad multiplexing for UART1 device */ | ||
948 | static const unsigned uart1_pins[] = { 28, 29 }; | ||
949 | static struct spear_muxreg uart1_muxreg[] = { | ||
950 | { | ||
951 | .reg = PMX_CONFIG_REG, | ||
952 | .mask = PMX_GPIO_PIN0_MASK | PMX_GPIO_PIN1_MASK, | ||
953 | .val = 0, | ||
954 | }, | ||
955 | }; | ||
956 | |||
957 | static struct spear_muxreg uart1_ext_muxreg[] = { | ||
958 | { | ||
959 | .reg = IP_SEL_PAD_20_29_REG, | ||
960 | .mask = PMX_PL_28_29_MASK, | ||
961 | .val = PMX_UART1_PL_28_29_VAL, | ||
962 | }, | ||
963 | }; | ||
964 | |||
965 | static struct spear_modemux uart1_modemux[] = { | ||
966 | { | ||
967 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE | ||
968 | | SMALL_PRINTERS_MODE | EXTENDED_MODE, | ||
969 | .muxregs = uart1_muxreg, | ||
970 | .nmuxregs = ARRAY_SIZE(uart1_muxreg), | ||
971 | }, { | ||
972 | .modes = EXTENDED_MODE, | ||
973 | .muxregs = uart1_ext_muxreg, | ||
974 | .nmuxregs = ARRAY_SIZE(uart1_ext_muxreg), | ||
975 | }, | ||
976 | }; | ||
977 | |||
978 | static struct spear_pingroup uart1_pingroup = { | ||
979 | .name = "uart1_grp", | ||
980 | .pins = uart1_pins, | ||
981 | .npins = ARRAY_SIZE(uart1_pins), | ||
982 | .modemuxs = uart1_modemux, | ||
983 | .nmodemuxs = ARRAY_SIZE(uart1_modemux), | ||
984 | }; | ||
985 | |||
986 | static const char *const uart1_grps[] = { "uart1_grp" }; | ||
987 | static struct spear_function uart1_function = { | ||
988 | .name = "uart1", | ||
989 | .groups = uart1_grps, | ||
990 | .ngroups = ARRAY_SIZE(uart1_grps), | ||
991 | }; | ||
992 | |||
993 | /* Pad multiplexing for UART1 Modem device */ | ||
994 | static const unsigned uart1_modem_2_to_7_pins[] = { 2, 3, 4, 5, 6, 7 }; | ||
995 | static const unsigned uart1_modem_31_to_36_pins[] = { 31, 32, 33, 34, 35, 36 }; | ||
996 | static const unsigned uart1_modem_34_to_45_pins[] = { 34, 35, 36, 43, 44, 45 }; | ||
997 | static const unsigned uart1_modem_80_to_85_pins[] = { 80, 81, 82, 83, 84, 85 }; | ||
998 | |||
999 | static struct spear_muxreg uart1_modem_ext_2_to_7_muxreg[] = { | ||
1000 | { | ||
1001 | .reg = PMX_CONFIG_REG, | ||
1002 | .mask = PMX_UART0_MASK | PMX_I2C_MASK | PMX_SSP_MASK, | ||
1003 | .val = 0, | ||
1004 | }, { | ||
1005 | .reg = IP_SEL_PAD_0_9_REG, | ||
1006 | .mask = PMX_PL_2_3_MASK | PMX_PL_6_7_MASK, | ||
1007 | .val = PMX_UART1_ENH_PL_2_3_VAL | PMX_UART1_ENH_PL_4_5_VAL | | ||
1008 | PMX_UART1_ENH_PL_6_7_VAL, | ||
1009 | }, { | ||
1010 | .reg = IP_SEL_MIX_PAD_REG, | ||
1011 | .mask = PMX_UART1_ENH_PORT_SEL_MASK, | ||
1012 | .val = PMX_UART1_ENH_PORT_3_TO_5_7_VAL, | ||
1013 | }, | ||
1014 | }; | ||
1015 | |||
1016 | static struct spear_muxreg uart1_modem_31_to_36_muxreg[] = { | ||
1017 | { | ||
1018 | .reg = PMX_CONFIG_REG, | ||
1019 | .mask = PMX_GPIO_PIN3_MASK | PMX_GPIO_PIN4_MASK | | ||
1020 | PMX_GPIO_PIN5_MASK | PMX_SSP_CS_MASK, | ||
1021 | .val = 0, | ||
1022 | }, | ||
1023 | }; | ||
1024 | |||
1025 | static struct spear_muxreg uart1_modem_ext_31_to_36_muxreg[] = { | ||
1026 | { | ||
1027 | .reg = IP_SEL_PAD_30_39_REG, | ||
1028 | .mask = PMX_PL_31_MASK | PMX_PL_32_33_MASK | PMX_PL_34_MASK | | ||
1029 | PMX_PL_35_MASK | PMX_PL_36_MASK, | ||
1030 | .val = PMX_UART1_ENH_PL_31_VAL | PMX_UART1_ENH_PL_32_33_VAL | | ||
1031 | PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | | ||
1032 | PMX_UART1_ENH_PL_36_VAL, | ||
1033 | }, { | ||
1034 | .reg = IP_SEL_MIX_PAD_REG, | ||
1035 | .mask = PMX_UART1_ENH_PORT_SEL_MASK, | ||
1036 | .val = PMX_UART1_ENH_PORT_32_TO_34_36_VAL, | ||
1037 | }, | ||
1038 | }; | ||
1039 | |||
1040 | static struct spear_muxreg uart1_modem_34_to_45_muxreg[] = { | ||
1041 | { | ||
1042 | .reg = PMX_CONFIG_REG, | ||
1043 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK | | ||
1044 | PMX_SSP_CS_MASK, | ||
1045 | .val = 0, | ||
1046 | }, | ||
1047 | }; | ||
1048 | |||
1049 | static struct spear_muxreg uart1_modem_ext_34_to_45_muxreg[] = { | ||
1050 | { | ||
1051 | .reg = IP_SEL_PAD_30_39_REG, | ||
1052 | .mask = PMX_PL_34_MASK | PMX_PL_35_MASK | PMX_PL_36_MASK, | ||
1053 | .val = PMX_UART1_ENH_PL_34_VAL | PMX_UART1_ENH_PL_35_VAL | | ||
1054 | PMX_UART1_ENH_PL_36_VAL, | ||
1055 | }, { | ||
1056 | .reg = IP_SEL_PAD_40_49_REG, | ||
1057 | .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, | ||
1058 | .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, | ||
1059 | }, { | ||
1060 | .reg = IP_SEL_MIX_PAD_REG, | ||
1061 | .mask = PMX_UART1_ENH_PORT_SEL_MASK, | ||
1062 | .val = PMX_UART1_ENH_PORT_44_45_34_36_VAL, | ||
1063 | }, | ||
1064 | }; | ||
1065 | |||
1066 | static struct spear_muxreg uart1_modem_ext_80_to_85_muxreg[] = { | ||
1067 | { | ||
1068 | .reg = IP_SEL_PAD_80_89_REG, | ||
1069 | .mask = PMX_PL_80_TO_85_MASK, | ||
1070 | .val = PMX_UART1_ENH_PL_80_TO_85_VAL, | ||
1071 | }, { | ||
1072 | .reg = IP_SEL_PAD_40_49_REG, | ||
1073 | .mask = PMX_PL_43_MASK | PMX_PL_44_45_MASK, | ||
1074 | .val = PMX_UART1_ENH_PL_43_VAL | PMX_UART1_ENH_PL_44_45_VAL, | ||
1075 | }, { | ||
1076 | .reg = IP_SEL_MIX_PAD_REG, | ||
1077 | .mask = PMX_UART1_ENH_PORT_SEL_MASK, | ||
1078 | .val = PMX_UART1_ENH_PORT_81_TO_85_VAL, | ||
1079 | }, | ||
1080 | }; | ||
1081 | |||
1082 | static struct spear_modemux uart1_modem_2_to_7_modemux[] = { | ||
1083 | { | ||
1084 | .modes = EXTENDED_MODE, | ||
1085 | .muxregs = uart1_modem_ext_2_to_7_muxreg, | ||
1086 | .nmuxregs = ARRAY_SIZE(uart1_modem_ext_2_to_7_muxreg), | ||
1087 | }, | ||
1088 | }; | ||
1089 | |||
1090 | static struct spear_modemux uart1_modem_31_to_36_modemux[] = { | ||
1091 | { | ||
1092 | .modes = SMALL_PRINTERS_MODE | EXTENDED_MODE, | ||
1093 | .muxregs = uart1_modem_31_to_36_muxreg, | ||
1094 | .nmuxregs = ARRAY_SIZE(uart1_modem_31_to_36_muxreg), | ||
1095 | }, { | ||
1096 | .modes = EXTENDED_MODE, | ||
1097 | .muxregs = uart1_modem_ext_31_to_36_muxreg, | ||
1098 | .nmuxregs = ARRAY_SIZE(uart1_modem_ext_31_to_36_muxreg), | ||
1099 | }, | ||
1100 | }; | ||
1101 | |||
1102 | static struct spear_modemux uart1_modem_34_to_45_modemux[] = { | ||
1103 | { | ||
1104 | .modes = AUTO_EXP_MODE | EXTENDED_MODE, | ||
1105 | .muxregs = uart1_modem_34_to_45_muxreg, | ||
1106 | .nmuxregs = ARRAY_SIZE(uart1_modem_34_to_45_muxreg), | ||
1107 | }, { | ||
1108 | .modes = EXTENDED_MODE, | ||
1109 | .muxregs = uart1_modem_ext_34_to_45_muxreg, | ||
1110 | .nmuxregs = ARRAY_SIZE(uart1_modem_ext_34_to_45_muxreg), | ||
1111 | }, | ||
1112 | }; | ||
1113 | |||
1114 | static struct spear_modemux uart1_modem_80_to_85_modemux[] = { | ||
1115 | { | ||
1116 | .modes = EXTENDED_MODE, | ||
1117 | .muxregs = uart1_modem_ext_80_to_85_muxreg, | ||
1118 | .nmuxregs = ARRAY_SIZE(uart1_modem_ext_80_to_85_muxreg), | ||
1119 | }, | ||
1120 | }; | ||
1121 | |||
1122 | static struct spear_pingroup uart1_modem_pingroup[] = { | ||
1123 | { | ||
1124 | .name = "uart1_modem_2_to_7_grp", | ||
1125 | .pins = uart1_modem_2_to_7_pins, | ||
1126 | .npins = ARRAY_SIZE(uart1_modem_2_to_7_pins), | ||
1127 | .modemuxs = uart1_modem_2_to_7_modemux, | ||
1128 | .nmodemuxs = ARRAY_SIZE(uart1_modem_2_to_7_modemux), | ||
1129 | }, { | ||
1130 | .name = "uart1_modem_31_to_36_grp", | ||
1131 | .pins = uart1_modem_31_to_36_pins, | ||
1132 | .npins = ARRAY_SIZE(uart1_modem_31_to_36_pins), | ||
1133 | .modemuxs = uart1_modem_31_to_36_modemux, | ||
1134 | .nmodemuxs = ARRAY_SIZE(uart1_modem_31_to_36_modemux), | ||
1135 | }, { | ||
1136 | .name = "uart1_modem_34_to_45_grp", | ||
1137 | .pins = uart1_modem_34_to_45_pins, | ||
1138 | .npins = ARRAY_SIZE(uart1_modem_34_to_45_pins), | ||
1139 | .modemuxs = uart1_modem_34_to_45_modemux, | ||
1140 | .nmodemuxs = ARRAY_SIZE(uart1_modem_34_to_45_modemux), | ||
1141 | }, { | ||
1142 | .name = "uart1_modem_80_to_85_grp", | ||
1143 | .pins = uart1_modem_80_to_85_pins, | ||
1144 | .npins = ARRAY_SIZE(uart1_modem_80_to_85_pins), | ||
1145 | .modemuxs = uart1_modem_80_to_85_modemux, | ||
1146 | .nmodemuxs = ARRAY_SIZE(uart1_modem_80_to_85_modemux), | ||
1147 | }, | ||
1148 | }; | ||
1149 | |||
1150 | static const char *const uart1_modem_grps[] = { "uart1_modem_2_to_7_grp", | ||
1151 | "uart1_modem_31_to_36_grp", "uart1_modem_34_to_45_grp", | ||
1152 | "uart1_modem_80_to_85_grp" }; | ||
1153 | static struct spear_function uart1_modem_function = { | ||
1154 | .name = "uart1_modem", | ||
1155 | .groups = uart1_modem_grps, | ||
1156 | .ngroups = ARRAY_SIZE(uart1_modem_grps), | ||
1157 | }; | ||
1158 | |||
1159 | /* Pad multiplexing for UART2 device */ | ||
1160 | static const unsigned uart2_pins[] = { 0, 1 }; | ||
1161 | static struct spear_muxreg uart2_muxreg[] = { | ||
1162 | { | ||
1163 | .reg = PMX_CONFIG_REG, | ||
1164 | .mask = PMX_FIRDA_MASK, | ||
1165 | .val = 0, | ||
1166 | }, | ||
1167 | }; | ||
1168 | |||
1169 | static struct spear_muxreg uart2_ext_muxreg[] = { | ||
1170 | { | ||
1171 | .reg = IP_SEL_PAD_0_9_REG, | ||
1172 | .mask = PMX_PL_0_1_MASK, | ||
1173 | .val = PMX_UART2_PL_0_1_VAL, | ||
1174 | }, | ||
1175 | }; | ||
1176 | |||
1177 | static struct spear_modemux uart2_modemux[] = { | ||
1178 | { | ||
1179 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE | ||
1180 | | SMALL_PRINTERS_MODE | EXTENDED_MODE, | ||
1181 | .muxregs = uart2_muxreg, | ||
1182 | .nmuxregs = ARRAY_SIZE(uart2_muxreg), | ||
1183 | }, { | ||
1184 | .modes = EXTENDED_MODE, | ||
1185 | .muxregs = uart2_ext_muxreg, | ||
1186 | .nmuxregs = ARRAY_SIZE(uart2_ext_muxreg), | ||
1187 | }, | ||
1188 | }; | ||
1189 | |||
1190 | static struct spear_pingroup uart2_pingroup = { | ||
1191 | .name = "uart2_grp", | ||
1192 | .pins = uart2_pins, | ||
1193 | .npins = ARRAY_SIZE(uart2_pins), | ||
1194 | .modemuxs = uart2_modemux, | ||
1195 | .nmodemuxs = ARRAY_SIZE(uart2_modemux), | ||
1196 | }; | ||
1197 | |||
1198 | static const char *const uart2_grps[] = { "uart2_grp" }; | ||
1199 | static struct spear_function uart2_function = { | ||
1200 | .name = "uart2", | ||
1201 | .groups = uart2_grps, | ||
1202 | .ngroups = ARRAY_SIZE(uart2_grps), | ||
1203 | }; | ||
1204 | |||
1205 | /* Pad multiplexing for uart3 device */ | ||
1206 | static const unsigned uart3_pins[][2] = { { 8, 9 }, { 15, 16 }, { 41, 42 }, | ||
1207 | { 52, 53 }, { 73, 74 }, { 94, 95 }, { 98, 99 } }; | ||
1208 | |||
1209 | static struct spear_muxreg uart3_ext_8_9_muxreg[] = { | ||
1210 | { | ||
1211 | .reg = PMX_CONFIG_REG, | ||
1212 | .mask = PMX_SSP_MASK, | ||
1213 | .val = 0, | ||
1214 | }, { | ||
1215 | .reg = IP_SEL_PAD_0_9_REG, | ||
1216 | .mask = PMX_PL_8_9_MASK, | ||
1217 | .val = PMX_UART3_PL_8_9_VAL, | ||
1218 | }, { | ||
1219 | .reg = IP_SEL_MIX_PAD_REG, | ||
1220 | .mask = PMX_UART3_PORT_SEL_MASK, | ||
1221 | .val = PMX_UART3_PORT_8_VAL, | ||
1222 | }, | ||
1223 | }; | ||
1224 | |||
1225 | static struct spear_muxreg uart3_ext_15_16_muxreg[] = { | ||
1226 | { | ||
1227 | .reg = PMX_CONFIG_REG, | ||
1228 | .mask = PMX_MII_MASK, | ||
1229 | .val = 0, | ||
1230 | }, { | ||
1231 | .reg = IP_SEL_PAD_10_19_REG, | ||
1232 | .mask = PMX_PL_15_16_MASK, | ||
1233 | .val = PMX_UART3_PL_15_16_VAL, | ||
1234 | }, { | ||
1235 | .reg = IP_SEL_MIX_PAD_REG, | ||
1236 | .mask = PMX_UART3_PORT_SEL_MASK, | ||
1237 | .val = PMX_UART3_PORT_15_VAL, | ||
1238 | }, | ||
1239 | }; | ||
1240 | |||
1241 | static struct spear_muxreg uart3_ext_41_42_muxreg[] = { | ||
1242 | { | ||
1243 | .reg = PMX_CONFIG_REG, | ||
1244 | .mask = PMX_UART0_MODEM_MASK, | ||
1245 | .val = 0, | ||
1246 | }, { | ||
1247 | .reg = IP_SEL_PAD_40_49_REG, | ||
1248 | .mask = PMX_PL_41_42_MASK, | ||
1249 | .val = PMX_UART3_PL_41_42_VAL, | ||
1250 | }, { | ||
1251 | .reg = IP_SEL_MIX_PAD_REG, | ||
1252 | .mask = PMX_UART3_PORT_SEL_MASK, | ||
1253 | .val = PMX_UART3_PORT_41_VAL, | ||
1254 | }, | ||
1255 | }; | ||
1256 | |||
1257 | static struct spear_muxreg uart3_ext_52_53_muxreg[] = { | ||
1258 | { | ||
1259 | .reg = IP_SEL_PAD_50_59_REG, | ||
1260 | .mask = PMX_PL_52_53_MASK, | ||
1261 | .val = PMX_UART3_PL_52_53_VAL, | ||
1262 | }, { | ||
1263 | .reg = IP_SEL_MIX_PAD_REG, | ||
1264 | .mask = PMX_UART3_PORT_SEL_MASK, | ||
1265 | .val = PMX_UART3_PORT_52_VAL, | ||
1266 | }, | ||
1267 | }; | ||
1268 | |||
1269 | static struct spear_muxreg uart3_ext_73_74_muxreg[] = { | ||
1270 | { | ||
1271 | .reg = IP_SEL_PAD_70_79_REG, | ||
1272 | .mask = PMX_PL_73_MASK | PMX_PL_74_MASK, | ||
1273 | .val = PMX_UART3_PL_73_VAL | PMX_UART3_PL_74_VAL, | ||
1274 | }, { | ||
1275 | .reg = IP_SEL_MIX_PAD_REG, | ||
1276 | .mask = PMX_UART3_PORT_SEL_MASK, | ||
1277 | .val = PMX_UART3_PORT_73_VAL, | ||
1278 | }, | ||
1279 | }; | ||
1280 | |||
1281 | static struct spear_muxreg uart3_ext_94_95_muxreg[] = { | ||
1282 | { | ||
1283 | .reg = IP_SEL_PAD_90_99_REG, | ||
1284 | .mask = PMX_PL_94_95_MASK, | ||
1285 | .val = PMX_UART3_PL_94_95_VAL, | ||
1286 | }, { | ||
1287 | .reg = IP_SEL_MIX_PAD_REG, | ||
1288 | .mask = PMX_UART3_PORT_SEL_MASK, | ||
1289 | .val = PMX_UART3_PORT_94_VAL, | ||
1290 | }, | ||
1291 | }; | ||
1292 | |||
1293 | static struct spear_muxreg uart3_ext_98_99_muxreg[] = { | ||
1294 | { | ||
1295 | .reg = IP_SEL_PAD_90_99_REG, | ||
1296 | .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, | ||
1297 | .val = PMX_UART3_PL_98_VAL | PMX_UART3_PL_99_VAL, | ||
1298 | }, { | ||
1299 | .reg = IP_SEL_MIX_PAD_REG, | ||
1300 | .mask = PMX_UART3_PORT_SEL_MASK, | ||
1301 | .val = PMX_UART3_PORT_99_VAL, | ||
1302 | }, | ||
1303 | }; | ||
1304 | |||
1305 | static struct spear_modemux uart3_modemux[][1] = { | ||
1306 | { | ||
1307 | /* Select signals on pins 8_9 */ | ||
1308 | { | ||
1309 | .modes = EXTENDED_MODE, | ||
1310 | .muxregs = uart3_ext_8_9_muxreg, | ||
1311 | .nmuxregs = ARRAY_SIZE(uart3_ext_8_9_muxreg), | ||
1312 | }, | ||
1313 | }, { | ||
1314 | /* Select signals on pins 15_16 */ | ||
1315 | { | ||
1316 | .modes = EXTENDED_MODE, | ||
1317 | .muxregs = uart3_ext_15_16_muxreg, | ||
1318 | .nmuxregs = ARRAY_SIZE(uart3_ext_15_16_muxreg), | ||
1319 | }, | ||
1320 | }, { | ||
1321 | /* Select signals on pins 41_42 */ | ||
1322 | { | ||
1323 | .modes = EXTENDED_MODE, | ||
1324 | .muxregs = uart3_ext_41_42_muxreg, | ||
1325 | .nmuxregs = ARRAY_SIZE(uart3_ext_41_42_muxreg), | ||
1326 | }, | ||
1327 | }, { | ||
1328 | /* Select signals on pins 52_53 */ | ||
1329 | { | ||
1330 | .modes = EXTENDED_MODE, | ||
1331 | .muxregs = uart3_ext_52_53_muxreg, | ||
1332 | .nmuxregs = ARRAY_SIZE(uart3_ext_52_53_muxreg), | ||
1333 | }, | ||
1334 | }, { | ||
1335 | /* Select signals on pins 73_74 */ | ||
1336 | { | ||
1337 | .modes = EXTENDED_MODE, | ||
1338 | .muxregs = uart3_ext_73_74_muxreg, | ||
1339 | .nmuxregs = ARRAY_SIZE(uart3_ext_73_74_muxreg), | ||
1340 | }, | ||
1341 | }, { | ||
1342 | /* Select signals on pins 94_95 */ | ||
1343 | { | ||
1344 | .modes = EXTENDED_MODE, | ||
1345 | .muxregs = uart3_ext_94_95_muxreg, | ||
1346 | .nmuxregs = ARRAY_SIZE(uart3_ext_94_95_muxreg), | ||
1347 | }, | ||
1348 | }, { | ||
1349 | /* Select signals on pins 98_99 */ | ||
1350 | { | ||
1351 | .modes = EXTENDED_MODE, | ||
1352 | .muxregs = uart3_ext_98_99_muxreg, | ||
1353 | .nmuxregs = ARRAY_SIZE(uart3_ext_98_99_muxreg), | ||
1354 | }, | ||
1355 | }, | ||
1356 | }; | ||
1357 | |||
1358 | static struct spear_pingroup uart3_pingroup[] = { | ||
1359 | { | ||
1360 | .name = "uart3_8_9_grp", | ||
1361 | .pins = uart3_pins[0], | ||
1362 | .npins = ARRAY_SIZE(uart3_pins[0]), | ||
1363 | .modemuxs = uart3_modemux[0], | ||
1364 | .nmodemuxs = ARRAY_SIZE(uart3_modemux[0]), | ||
1365 | }, { | ||
1366 | .name = "uart3_15_16_grp", | ||
1367 | .pins = uart3_pins[1], | ||
1368 | .npins = ARRAY_SIZE(uart3_pins[1]), | ||
1369 | .modemuxs = uart3_modemux[1], | ||
1370 | .nmodemuxs = ARRAY_SIZE(uart3_modemux[1]), | ||
1371 | }, { | ||
1372 | .name = "uart3_41_42_grp", | ||
1373 | .pins = uart3_pins[2], | ||
1374 | .npins = ARRAY_SIZE(uart3_pins[2]), | ||
1375 | .modemuxs = uart3_modemux[2], | ||
1376 | .nmodemuxs = ARRAY_SIZE(uart3_modemux[2]), | ||
1377 | }, { | ||
1378 | .name = "uart3_52_53_grp", | ||
1379 | .pins = uart3_pins[3], | ||
1380 | .npins = ARRAY_SIZE(uart3_pins[3]), | ||
1381 | .modemuxs = uart3_modemux[3], | ||
1382 | .nmodemuxs = ARRAY_SIZE(uart3_modemux[3]), | ||
1383 | }, { | ||
1384 | .name = "uart3_73_74_grp", | ||
1385 | .pins = uart3_pins[4], | ||
1386 | .npins = ARRAY_SIZE(uart3_pins[4]), | ||
1387 | .modemuxs = uart3_modemux[4], | ||
1388 | .nmodemuxs = ARRAY_SIZE(uart3_modemux[4]), | ||
1389 | }, { | ||
1390 | .name = "uart3_94_95_grp", | ||
1391 | .pins = uart3_pins[5], | ||
1392 | .npins = ARRAY_SIZE(uart3_pins[5]), | ||
1393 | .modemuxs = uart3_modemux[5], | ||
1394 | .nmodemuxs = ARRAY_SIZE(uart3_modemux[5]), | ||
1395 | }, { | ||
1396 | .name = "uart3_98_99_grp", | ||
1397 | .pins = uart3_pins[6], | ||
1398 | .npins = ARRAY_SIZE(uart3_pins[6]), | ||
1399 | .modemuxs = uart3_modemux[6], | ||
1400 | .nmodemuxs = ARRAY_SIZE(uart3_modemux[6]), | ||
1401 | }, | ||
1402 | }; | ||
1403 | |||
1404 | static const char *const uart3_grps[] = { "uart3_8_9_grp", "uart3_15_16_grp", | ||
1405 | "uart3_41_42_grp", "uart3_52_53_grp", "uart3_73_74_grp", | ||
1406 | "uart3_94_95_grp", "uart3_98_99_grp" }; | ||
1407 | |||
1408 | static struct spear_function uart3_function = { | ||
1409 | .name = "uart3", | ||
1410 | .groups = uart3_grps, | ||
1411 | .ngroups = ARRAY_SIZE(uart3_grps), | ||
1412 | }; | ||
1413 | |||
1414 | /* Pad multiplexing for uart4 device */ | ||
1415 | static const unsigned uart4_pins[][2] = { { 6, 7 }, { 13, 14 }, { 39, 40 }, | ||
1416 | { 71, 72 }, { 92, 93 }, { 100, 101 } }; | ||
1417 | |||
1418 | static struct spear_muxreg uart4_ext_6_7_muxreg[] = { | ||
1419 | { | ||
1420 | .reg = PMX_CONFIG_REG, | ||
1421 | .mask = PMX_SSP_MASK, | ||
1422 | .val = 0, | ||
1423 | }, { | ||
1424 | .reg = IP_SEL_PAD_0_9_REG, | ||
1425 | .mask = PMX_PL_6_7_MASK, | ||
1426 | .val = PMX_UART4_PL_6_7_VAL, | ||
1427 | }, { | ||
1428 | .reg = IP_SEL_MIX_PAD_REG, | ||
1429 | .mask = PMX_UART4_PORT_SEL_MASK, | ||
1430 | .val = PMX_UART4_PORT_6_VAL, | ||
1431 | }, | ||
1432 | }; | ||
1433 | |||
1434 | static struct spear_muxreg uart4_ext_13_14_muxreg[] = { | ||
1435 | { | ||
1436 | .reg = PMX_CONFIG_REG, | ||
1437 | .mask = PMX_MII_MASK, | ||
1438 | .val = 0, | ||
1439 | }, { | ||
1440 | .reg = IP_SEL_PAD_10_19_REG, | ||
1441 | .mask = PMX_PL_13_14_MASK, | ||
1442 | .val = PMX_UART4_PL_13_14_VAL, | ||
1443 | }, { | ||
1444 | .reg = IP_SEL_MIX_PAD_REG, | ||
1445 | .mask = PMX_UART4_PORT_SEL_MASK, | ||
1446 | .val = PMX_UART4_PORT_13_VAL, | ||
1447 | }, | ||
1448 | }; | ||
1449 | |||
1450 | static struct spear_muxreg uart4_ext_39_40_muxreg[] = { | ||
1451 | { | ||
1452 | .reg = PMX_CONFIG_REG, | ||
1453 | .mask = PMX_UART0_MODEM_MASK, | ||
1454 | .val = 0, | ||
1455 | }, { | ||
1456 | .reg = IP_SEL_PAD_30_39_REG, | ||
1457 | .mask = PMX_PL_39_MASK, | ||
1458 | .val = PMX_UART4_PL_39_VAL, | ||
1459 | }, { | ||
1460 | .reg = IP_SEL_PAD_40_49_REG, | ||
1461 | .mask = PMX_PL_40_MASK, | ||
1462 | .val = PMX_UART4_PL_40_VAL, | ||
1463 | }, { | ||
1464 | .reg = IP_SEL_MIX_PAD_REG, | ||
1465 | .mask = PMX_UART4_PORT_SEL_MASK, | ||
1466 | .val = PMX_UART4_PORT_39_VAL, | ||
1467 | }, | ||
1468 | }; | ||
1469 | |||
1470 | static struct spear_muxreg uart4_ext_71_72_muxreg[] = { | ||
1471 | { | ||
1472 | .reg = IP_SEL_PAD_70_79_REG, | ||
1473 | .mask = PMX_PL_71_72_MASK, | ||
1474 | .val = PMX_UART4_PL_71_72_VAL, | ||
1475 | }, { | ||
1476 | .reg = IP_SEL_MIX_PAD_REG, | ||
1477 | .mask = PMX_UART4_PORT_SEL_MASK, | ||
1478 | .val = PMX_UART4_PORT_71_VAL, | ||
1479 | }, | ||
1480 | }; | ||
1481 | |||
1482 | static struct spear_muxreg uart4_ext_92_93_muxreg[] = { | ||
1483 | { | ||
1484 | .reg = IP_SEL_PAD_90_99_REG, | ||
1485 | .mask = PMX_PL_92_93_MASK, | ||
1486 | .val = PMX_UART4_PL_92_93_VAL, | ||
1487 | }, { | ||
1488 | .reg = IP_SEL_MIX_PAD_REG, | ||
1489 | .mask = PMX_UART4_PORT_SEL_MASK, | ||
1490 | .val = PMX_UART4_PORT_92_VAL, | ||
1491 | }, | ||
1492 | }; | ||
1493 | |||
1494 | static struct spear_muxreg uart4_ext_100_101_muxreg[] = { | ||
1495 | { | ||
1496 | .reg = IP_SEL_MIX_PAD_REG, | ||
1497 | .mask = PMX_PL_100_101_MASK | | ||
1498 | PMX_UART4_PORT_SEL_MASK, | ||
1499 | .val = PMX_UART4_PL_100_101_VAL | | ||
1500 | PMX_UART4_PORT_101_VAL, | ||
1501 | }, | ||
1502 | }; | ||
1503 | |||
1504 | static struct spear_modemux uart4_modemux[][1] = { | ||
1505 | { | ||
1506 | /* Select signals on pins 6_7 */ | ||
1507 | { | ||
1508 | .modes = EXTENDED_MODE, | ||
1509 | .muxregs = uart4_ext_6_7_muxreg, | ||
1510 | .nmuxregs = ARRAY_SIZE(uart4_ext_6_7_muxreg), | ||
1511 | }, | ||
1512 | }, { | ||
1513 | /* Select signals on pins 13_14 */ | ||
1514 | { | ||
1515 | .modes = EXTENDED_MODE, | ||
1516 | .muxregs = uart4_ext_13_14_muxreg, | ||
1517 | .nmuxregs = ARRAY_SIZE(uart4_ext_13_14_muxreg), | ||
1518 | }, | ||
1519 | }, { | ||
1520 | /* Select signals on pins 39_40 */ | ||
1521 | { | ||
1522 | .modes = EXTENDED_MODE, | ||
1523 | .muxregs = uart4_ext_39_40_muxreg, | ||
1524 | .nmuxregs = ARRAY_SIZE(uart4_ext_39_40_muxreg), | ||
1525 | }, | ||
1526 | }, { | ||
1527 | /* Select signals on pins 71_72 */ | ||
1528 | { | ||
1529 | .modes = EXTENDED_MODE, | ||
1530 | .muxregs = uart4_ext_71_72_muxreg, | ||
1531 | .nmuxregs = ARRAY_SIZE(uart4_ext_71_72_muxreg), | ||
1532 | }, | ||
1533 | }, { | ||
1534 | /* Select signals on pins 92_93 */ | ||
1535 | { | ||
1536 | .modes = EXTENDED_MODE, | ||
1537 | .muxregs = uart4_ext_92_93_muxreg, | ||
1538 | .nmuxregs = ARRAY_SIZE(uart4_ext_92_93_muxreg), | ||
1539 | }, | ||
1540 | }, { | ||
1541 | /* Select signals on pins 100_101_ */ | ||
1542 | { | ||
1543 | .modes = EXTENDED_MODE, | ||
1544 | .muxregs = uart4_ext_100_101_muxreg, | ||
1545 | .nmuxregs = ARRAY_SIZE(uart4_ext_100_101_muxreg), | ||
1546 | }, | ||
1547 | }, | ||
1548 | }; | ||
1549 | |||
1550 | static struct spear_pingroup uart4_pingroup[] = { | ||
1551 | { | ||
1552 | .name = "uart4_6_7_grp", | ||
1553 | .pins = uart4_pins[0], | ||
1554 | .npins = ARRAY_SIZE(uart4_pins[0]), | ||
1555 | .modemuxs = uart4_modemux[0], | ||
1556 | .nmodemuxs = ARRAY_SIZE(uart4_modemux[0]), | ||
1557 | }, { | ||
1558 | .name = "uart4_13_14_grp", | ||
1559 | .pins = uart4_pins[1], | ||
1560 | .npins = ARRAY_SIZE(uart4_pins[1]), | ||
1561 | .modemuxs = uart4_modemux[1], | ||
1562 | .nmodemuxs = ARRAY_SIZE(uart4_modemux[1]), | ||
1563 | }, { | ||
1564 | .name = "uart4_39_40_grp", | ||
1565 | .pins = uart4_pins[2], | ||
1566 | .npins = ARRAY_SIZE(uart4_pins[2]), | ||
1567 | .modemuxs = uart4_modemux[2], | ||
1568 | .nmodemuxs = ARRAY_SIZE(uart4_modemux[2]), | ||
1569 | }, { | ||
1570 | .name = "uart4_71_72_grp", | ||
1571 | .pins = uart4_pins[3], | ||
1572 | .npins = ARRAY_SIZE(uart4_pins[3]), | ||
1573 | .modemuxs = uart4_modemux[3], | ||
1574 | .nmodemuxs = ARRAY_SIZE(uart4_modemux[3]), | ||
1575 | }, { | ||
1576 | .name = "uart4_92_93_grp", | ||
1577 | .pins = uart4_pins[4], | ||
1578 | .npins = ARRAY_SIZE(uart4_pins[4]), | ||
1579 | .modemuxs = uart4_modemux[4], | ||
1580 | .nmodemuxs = ARRAY_SIZE(uart4_modemux[4]), | ||
1581 | }, { | ||
1582 | .name = "uart4_100_101_grp", | ||
1583 | .pins = uart4_pins[5], | ||
1584 | .npins = ARRAY_SIZE(uart4_pins[5]), | ||
1585 | .modemuxs = uart4_modemux[5], | ||
1586 | .nmodemuxs = ARRAY_SIZE(uart4_modemux[5]), | ||
1587 | }, | ||
1588 | }; | ||
1589 | |||
1590 | static const char *const uart4_grps[] = { "uart4_6_7_grp", "uart4_13_14_grp", | ||
1591 | "uart4_39_40_grp", "uart4_71_72_grp", "uart4_92_93_grp", | ||
1592 | "uart4_100_101_grp" }; | ||
1593 | |||
1594 | static struct spear_function uart4_function = { | ||
1595 | .name = "uart4", | ||
1596 | .groups = uart4_grps, | ||
1597 | .ngroups = ARRAY_SIZE(uart4_grps), | ||
1598 | }; | ||
1599 | |||
1600 | /* Pad multiplexing for uart5 device */ | ||
1601 | static const unsigned uart5_pins[][2] = { { 4, 5 }, { 37, 38 }, { 69, 70 }, | ||
1602 | { 90, 91 } }; | ||
1603 | |||
1604 | static struct spear_muxreg uart5_ext_4_5_muxreg[] = { | ||
1605 | { | ||
1606 | .reg = PMX_CONFIG_REG, | ||
1607 | .mask = PMX_I2C_MASK, | ||
1608 | .val = 0, | ||
1609 | }, { | ||
1610 | .reg = IP_SEL_PAD_0_9_REG, | ||
1611 | .mask = PMX_PL_4_5_MASK, | ||
1612 | .val = PMX_UART5_PL_4_5_VAL, | ||
1613 | }, { | ||
1614 | .reg = IP_SEL_MIX_PAD_REG, | ||
1615 | .mask = PMX_UART5_PORT_SEL_MASK, | ||
1616 | .val = PMX_UART5_PORT_4_VAL, | ||
1617 | }, | ||
1618 | }; | ||
1619 | |||
1620 | static struct spear_muxreg uart5_ext_37_38_muxreg[] = { | ||
1621 | { | ||
1622 | .reg = PMX_CONFIG_REG, | ||
1623 | .mask = PMX_UART0_MODEM_MASK, | ||
1624 | .val = 0, | ||
1625 | }, { | ||
1626 | .reg = IP_SEL_PAD_30_39_REG, | ||
1627 | .mask = PMX_PL_37_38_MASK, | ||
1628 | .val = PMX_UART5_PL_37_38_VAL, | ||
1629 | }, { | ||
1630 | .reg = IP_SEL_MIX_PAD_REG, | ||
1631 | .mask = PMX_UART5_PORT_SEL_MASK, | ||
1632 | .val = PMX_UART5_PORT_37_VAL, | ||
1633 | }, | ||
1634 | }; | ||
1635 | |||
1636 | static struct spear_muxreg uart5_ext_69_70_muxreg[] = { | ||
1637 | { | ||
1638 | .reg = IP_SEL_PAD_60_69_REG, | ||
1639 | .mask = PMX_PL_69_MASK, | ||
1640 | .val = PMX_UART5_PL_69_VAL, | ||
1641 | }, { | ||
1642 | .reg = IP_SEL_PAD_70_79_REG, | ||
1643 | .mask = PMX_PL_70_MASK, | ||
1644 | .val = PMX_UART5_PL_70_VAL, | ||
1645 | }, { | ||
1646 | .reg = IP_SEL_MIX_PAD_REG, | ||
1647 | .mask = PMX_UART5_PORT_SEL_MASK, | ||
1648 | .val = PMX_UART5_PORT_69_VAL, | ||
1649 | }, | ||
1650 | }; | ||
1651 | |||
1652 | static struct spear_muxreg uart5_ext_90_91_muxreg[] = { | ||
1653 | { | ||
1654 | .reg = IP_SEL_PAD_90_99_REG, | ||
1655 | .mask = PMX_PL_90_91_MASK, | ||
1656 | .val = PMX_UART5_PL_90_91_VAL, | ||
1657 | }, { | ||
1658 | .reg = IP_SEL_MIX_PAD_REG, | ||
1659 | .mask = PMX_UART5_PORT_SEL_MASK, | ||
1660 | .val = PMX_UART5_PORT_90_VAL, | ||
1661 | }, | ||
1662 | }; | ||
1663 | |||
1664 | static struct spear_modemux uart5_modemux[][1] = { | ||
1665 | { | ||
1666 | /* Select signals on pins 4_5 */ | ||
1667 | { | ||
1668 | .modes = EXTENDED_MODE, | ||
1669 | .muxregs = uart5_ext_4_5_muxreg, | ||
1670 | .nmuxregs = ARRAY_SIZE(uart5_ext_4_5_muxreg), | ||
1671 | }, | ||
1672 | }, { | ||
1673 | /* Select signals on pins 37_38 */ | ||
1674 | { | ||
1675 | .modes = EXTENDED_MODE, | ||
1676 | .muxregs = uart5_ext_37_38_muxreg, | ||
1677 | .nmuxregs = ARRAY_SIZE(uart5_ext_37_38_muxreg), | ||
1678 | }, | ||
1679 | }, { | ||
1680 | /* Select signals on pins 69_70 */ | ||
1681 | { | ||
1682 | .modes = EXTENDED_MODE, | ||
1683 | .muxregs = uart5_ext_69_70_muxreg, | ||
1684 | .nmuxregs = ARRAY_SIZE(uart5_ext_69_70_muxreg), | ||
1685 | }, | ||
1686 | }, { | ||
1687 | /* Select signals on pins 90_91 */ | ||
1688 | { | ||
1689 | .modes = EXTENDED_MODE, | ||
1690 | .muxregs = uart5_ext_90_91_muxreg, | ||
1691 | .nmuxregs = ARRAY_SIZE(uart5_ext_90_91_muxreg), | ||
1692 | }, | ||
1693 | }, | ||
1694 | }; | ||
1695 | |||
1696 | static struct spear_pingroup uart5_pingroup[] = { | ||
1697 | { | ||
1698 | .name = "uart5_4_5_grp", | ||
1699 | .pins = uart5_pins[0], | ||
1700 | .npins = ARRAY_SIZE(uart5_pins[0]), | ||
1701 | .modemuxs = uart5_modemux[0], | ||
1702 | .nmodemuxs = ARRAY_SIZE(uart5_modemux[0]), | ||
1703 | }, { | ||
1704 | .name = "uart5_37_38_grp", | ||
1705 | .pins = uart5_pins[1], | ||
1706 | .npins = ARRAY_SIZE(uart5_pins[1]), | ||
1707 | .modemuxs = uart5_modemux[1], | ||
1708 | .nmodemuxs = ARRAY_SIZE(uart5_modemux[1]), | ||
1709 | }, { | ||
1710 | .name = "uart5_69_70_grp", | ||
1711 | .pins = uart5_pins[2], | ||
1712 | .npins = ARRAY_SIZE(uart5_pins[2]), | ||
1713 | .modemuxs = uart5_modemux[2], | ||
1714 | .nmodemuxs = ARRAY_SIZE(uart5_modemux[2]), | ||
1715 | }, { | ||
1716 | .name = "uart5_90_91_grp", | ||
1717 | .pins = uart5_pins[3], | ||
1718 | .npins = ARRAY_SIZE(uart5_pins[3]), | ||
1719 | .modemuxs = uart5_modemux[3], | ||
1720 | .nmodemuxs = ARRAY_SIZE(uart5_modemux[3]), | ||
1721 | }, | ||
1722 | }; | ||
1723 | |||
1724 | static const char *const uart5_grps[] = { "uart5_4_5_grp", "uart5_37_38_grp", | ||
1725 | "uart5_69_70_grp", "uart5_90_91_grp" }; | ||
1726 | static struct spear_function uart5_function = { | ||
1727 | .name = "uart5", | ||
1728 | .groups = uart5_grps, | ||
1729 | .ngroups = ARRAY_SIZE(uart5_grps), | ||
1730 | }; | ||
1731 | |||
1732 | /* Pad multiplexing for uart6 device */ | ||
1733 | static const unsigned uart6_pins[][2] = { { 2, 3 }, { 88, 89 } }; | ||
1734 | static struct spear_muxreg uart6_ext_2_3_muxreg[] = { | ||
1735 | { | ||
1736 | .reg = PMX_CONFIG_REG, | ||
1737 | .mask = PMX_UART0_MASK, | ||
1738 | .val = 0, | ||
1739 | }, { | ||
1740 | .reg = IP_SEL_PAD_0_9_REG, | ||
1741 | .mask = PMX_PL_2_3_MASK, | ||
1742 | .val = PMX_UART6_PL_2_3_VAL, | ||
1743 | }, { | ||
1744 | .reg = IP_SEL_MIX_PAD_REG, | ||
1745 | .mask = PMX_UART6_PORT_SEL_MASK, | ||
1746 | .val = PMX_UART6_PORT_2_VAL, | ||
1747 | }, | ||
1748 | }; | ||
1749 | |||
1750 | static struct spear_muxreg uart6_ext_88_89_muxreg[] = { | ||
1751 | { | ||
1752 | .reg = IP_SEL_PAD_80_89_REG, | ||
1753 | .mask = PMX_PL_88_89_MASK, | ||
1754 | .val = PMX_UART6_PL_88_89_VAL, | ||
1755 | }, { | ||
1756 | .reg = IP_SEL_MIX_PAD_REG, | ||
1757 | .mask = PMX_UART6_PORT_SEL_MASK, | ||
1758 | .val = PMX_UART6_PORT_88_VAL, | ||
1759 | }, | ||
1760 | }; | ||
1761 | |||
1762 | static struct spear_modemux uart6_modemux[][1] = { | ||
1763 | { | ||
1764 | /* Select signals on pins 2_3 */ | ||
1765 | { | ||
1766 | .modes = EXTENDED_MODE, | ||
1767 | .muxregs = uart6_ext_2_3_muxreg, | ||
1768 | .nmuxregs = ARRAY_SIZE(uart6_ext_2_3_muxreg), | ||
1769 | }, | ||
1770 | }, { | ||
1771 | /* Select signals on pins 88_89 */ | ||
1772 | { | ||
1773 | .modes = EXTENDED_MODE, | ||
1774 | .muxregs = uart6_ext_88_89_muxreg, | ||
1775 | .nmuxregs = ARRAY_SIZE(uart6_ext_88_89_muxreg), | ||
1776 | }, | ||
1777 | }, | ||
1778 | }; | ||
1779 | |||
1780 | static struct spear_pingroup uart6_pingroup[] = { | ||
1781 | { | ||
1782 | .name = "uart6_2_3_grp", | ||
1783 | .pins = uart6_pins[0], | ||
1784 | .npins = ARRAY_SIZE(uart6_pins[0]), | ||
1785 | .modemuxs = uart6_modemux[0], | ||
1786 | .nmodemuxs = ARRAY_SIZE(uart6_modemux[0]), | ||
1787 | }, { | ||
1788 | .name = "uart6_88_89_grp", | ||
1789 | .pins = uart6_pins[1], | ||
1790 | .npins = ARRAY_SIZE(uart6_pins[1]), | ||
1791 | .modemuxs = uart6_modemux[1], | ||
1792 | .nmodemuxs = ARRAY_SIZE(uart6_modemux[1]), | ||
1793 | }, | ||
1794 | }; | ||
1795 | |||
1796 | static const char *const uart6_grps[] = { "uart6_2_3_grp", "uart6_88_89_grp" }; | ||
1797 | static struct spear_function uart6_function = { | ||
1798 | .name = "uart6", | ||
1799 | .groups = uart6_grps, | ||
1800 | .ngroups = ARRAY_SIZE(uart6_grps), | ||
1801 | }; | ||
1802 | |||
1803 | /* UART - RS485 pmx */ | ||
1804 | static const unsigned rs485_pins[] = { 77, 78, 79 }; | ||
1805 | static struct spear_muxreg rs485_muxreg[] = { | ||
1806 | { | ||
1807 | .reg = IP_SEL_PAD_70_79_REG, | ||
1808 | .mask = PMX_PL_77_78_79_MASK, | ||
1809 | .val = PMX_RS485_PL_77_78_79_VAL, | ||
1810 | }, | ||
1811 | }; | ||
1812 | |||
1813 | static struct spear_modemux rs485_modemux[] = { | ||
1814 | { | ||
1815 | .modes = EXTENDED_MODE, | ||
1816 | .muxregs = rs485_muxreg, | ||
1817 | .nmuxregs = ARRAY_SIZE(rs485_muxreg), | ||
1818 | }, | ||
1819 | }; | ||
1820 | |||
1821 | static struct spear_pingroup rs485_pingroup = { | ||
1822 | .name = "rs485_grp", | ||
1823 | .pins = rs485_pins, | ||
1824 | .npins = ARRAY_SIZE(rs485_pins), | ||
1825 | .modemuxs = rs485_modemux, | ||
1826 | .nmodemuxs = ARRAY_SIZE(rs485_modemux), | ||
1827 | }; | ||
1828 | |||
1829 | static const char *const rs485_grps[] = { "rs485_grp" }; | ||
1830 | static struct spear_function rs485_function = { | ||
1831 | .name = "rs485", | ||
1832 | .groups = rs485_grps, | ||
1833 | .ngroups = ARRAY_SIZE(rs485_grps), | ||
1834 | }; | ||
1835 | |||
1836 | /* Pad multiplexing for Touchscreen device */ | ||
1837 | static const unsigned touchscreen_pins[] = { 5, 36 }; | ||
1838 | static struct spear_muxreg touchscreen_muxreg[] = { | ||
1839 | { | ||
1840 | .reg = PMX_CONFIG_REG, | ||
1841 | .mask = PMX_I2C_MASK | PMX_SSP_CS_MASK, | ||
1842 | .val = 0, | ||
1843 | }, | ||
1844 | }; | ||
1845 | |||
1846 | static struct spear_muxreg touchscreen_ext_muxreg[] = { | ||
1847 | { | ||
1848 | .reg = IP_SEL_PAD_0_9_REG, | ||
1849 | .mask = PMX_PL_5_MASK, | ||
1850 | .val = PMX_TOUCH_Y_PL_5_VAL, | ||
1851 | }, { | ||
1852 | .reg = IP_SEL_PAD_30_39_REG, | ||
1853 | .mask = PMX_PL_36_MASK, | ||
1854 | .val = PMX_TOUCH_X_PL_36_VAL, | ||
1855 | }, | ||
1856 | }; | ||
1857 | |||
1858 | static struct spear_modemux touchscreen_modemux[] = { | ||
1859 | { | ||
1860 | .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, | ||
1861 | .muxregs = touchscreen_muxreg, | ||
1862 | .nmuxregs = ARRAY_SIZE(touchscreen_muxreg), | ||
1863 | }, { | ||
1864 | .modes = EXTENDED_MODE, | ||
1865 | .muxregs = touchscreen_ext_muxreg, | ||
1866 | .nmuxregs = ARRAY_SIZE(touchscreen_ext_muxreg), | ||
1867 | }, | ||
1868 | }; | ||
1869 | |||
1870 | static struct spear_pingroup touchscreen_pingroup = { | ||
1871 | .name = "touchscreen_grp", | ||
1872 | .pins = touchscreen_pins, | ||
1873 | .npins = ARRAY_SIZE(touchscreen_pins), | ||
1874 | .modemuxs = touchscreen_modemux, | ||
1875 | .nmodemuxs = ARRAY_SIZE(touchscreen_modemux), | ||
1876 | }; | ||
1877 | |||
1878 | static const char *const touchscreen_grps[] = { "touchscreen_grp" }; | ||
1879 | static struct spear_function touchscreen_function = { | ||
1880 | .name = "touchscreen", | ||
1881 | .groups = touchscreen_grps, | ||
1882 | .ngroups = ARRAY_SIZE(touchscreen_grps), | ||
1883 | }; | ||
1884 | |||
1885 | /* Pad multiplexing for CAN device */ | ||
1886 | static const unsigned can0_pins[] = { 32, 33 }; | ||
1887 | static struct spear_muxreg can0_muxreg[] = { | ||
1888 | { | ||
1889 | .reg = PMX_CONFIG_REG, | ||
1890 | .mask = PMX_GPIO_PIN4_MASK | PMX_GPIO_PIN5_MASK, | ||
1891 | .val = 0, | ||
1892 | }, | ||
1893 | }; | ||
1894 | |||
1895 | static struct spear_muxreg can0_ext_muxreg[] = { | ||
1896 | { | ||
1897 | .reg = IP_SEL_PAD_30_39_REG, | ||
1898 | .mask = PMX_PL_32_33_MASK, | ||
1899 | .val = PMX_CAN0_PL_32_33_VAL, | ||
1900 | }, | ||
1901 | }; | ||
1902 | |||
1903 | static struct spear_modemux can0_modemux[] = { | ||
1904 | { | ||
1905 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE | ||
1906 | | EXTENDED_MODE, | ||
1907 | .muxregs = can0_muxreg, | ||
1908 | .nmuxregs = ARRAY_SIZE(can0_muxreg), | ||
1909 | }, { | ||
1910 | .modes = EXTENDED_MODE, | ||
1911 | .muxregs = can0_ext_muxreg, | ||
1912 | .nmuxregs = ARRAY_SIZE(can0_ext_muxreg), | ||
1913 | }, | ||
1914 | }; | ||
1915 | |||
1916 | static struct spear_pingroup can0_pingroup = { | ||
1917 | .name = "can0_grp", | ||
1918 | .pins = can0_pins, | ||
1919 | .npins = ARRAY_SIZE(can0_pins), | ||
1920 | .modemuxs = can0_modemux, | ||
1921 | .nmodemuxs = ARRAY_SIZE(can0_modemux), | ||
1922 | }; | ||
1923 | |||
1924 | static const char *const can0_grps[] = { "can0_grp" }; | ||
1925 | static struct spear_function can0_function = { | ||
1926 | .name = "can0", | ||
1927 | .groups = can0_grps, | ||
1928 | .ngroups = ARRAY_SIZE(can0_grps), | ||
1929 | }; | ||
1930 | |||
1931 | static const unsigned can1_pins[] = { 30, 31 }; | ||
1932 | static struct spear_muxreg can1_muxreg[] = { | ||
1933 | { | ||
1934 | .reg = PMX_CONFIG_REG, | ||
1935 | .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, | ||
1936 | .val = 0, | ||
1937 | }, | ||
1938 | }; | ||
1939 | |||
1940 | static struct spear_muxreg can1_ext_muxreg[] = { | ||
1941 | { | ||
1942 | .reg = IP_SEL_PAD_30_39_REG, | ||
1943 | .mask = PMX_PL_30_31_MASK, | ||
1944 | .val = PMX_CAN1_PL_30_31_VAL, | ||
1945 | }, | ||
1946 | }; | ||
1947 | |||
1948 | static struct spear_modemux can1_modemux[] = { | ||
1949 | { | ||
1950 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | AUTO_EXP_MODE | ||
1951 | | EXTENDED_MODE, | ||
1952 | .muxregs = can1_muxreg, | ||
1953 | .nmuxregs = ARRAY_SIZE(can1_muxreg), | ||
1954 | }, { | ||
1955 | .modes = EXTENDED_MODE, | ||
1956 | .muxregs = can1_ext_muxreg, | ||
1957 | .nmuxregs = ARRAY_SIZE(can1_ext_muxreg), | ||
1958 | }, | ||
1959 | }; | ||
1960 | |||
1961 | static struct spear_pingroup can1_pingroup = { | ||
1962 | .name = "can1_grp", | ||
1963 | .pins = can1_pins, | ||
1964 | .npins = ARRAY_SIZE(can1_pins), | ||
1965 | .modemuxs = can1_modemux, | ||
1966 | .nmodemuxs = ARRAY_SIZE(can1_modemux), | ||
1967 | }; | ||
1968 | |||
1969 | static const char *const can1_grps[] = { "can1_grp" }; | ||
1970 | static struct spear_function can1_function = { | ||
1971 | .name = "can1", | ||
1972 | .groups = can1_grps, | ||
1973 | .ngroups = ARRAY_SIZE(can1_grps), | ||
1974 | }; | ||
1975 | |||
1976 | /* Pad multiplexing for PWM0_1 device */ | ||
1977 | static const unsigned pwm0_1_pins[][2] = { { 37, 38 }, { 14, 15 }, { 8, 9 }, | ||
1978 | { 30, 31 }, { 42, 43 }, { 59, 60 }, { 88, 89 } }; | ||
1979 | |||
1980 | static struct spear_muxreg pwm0_1_pin_8_9_muxreg[] = { | ||
1981 | { | ||
1982 | .reg = PMX_CONFIG_REG, | ||
1983 | .mask = PMX_SSP_MASK, | ||
1984 | .val = 0, | ||
1985 | }, { | ||
1986 | .reg = IP_SEL_PAD_0_9_REG, | ||
1987 | .mask = PMX_PL_8_9_MASK, | ||
1988 | .val = PMX_PWM_0_1_PL_8_9_VAL, | ||
1989 | }, | ||
1990 | }; | ||
1991 | |||
1992 | static struct spear_muxreg pwm0_1_autoexpsmallpri_muxreg[] = { | ||
1993 | { | ||
1994 | .reg = PMX_CONFIG_REG, | ||
1995 | .mask = PMX_MII_MASK, | ||
1996 | .val = 0, | ||
1997 | }, | ||
1998 | }; | ||
1999 | |||
2000 | static struct spear_muxreg pwm0_1_pin_14_15_muxreg[] = { | ||
2001 | { | ||
2002 | .reg = IP_SEL_PAD_10_19_REG, | ||
2003 | .mask = PMX_PL_14_MASK | PMX_PL_15_MASK, | ||
2004 | .val = PMX_PWM1_PL_14_VAL | PMX_PWM0_PL_15_VAL, | ||
2005 | }, | ||
2006 | }; | ||
2007 | |||
2008 | static struct spear_muxreg pwm0_1_pin_30_31_muxreg[] = { | ||
2009 | { | ||
2010 | .reg = PMX_CONFIG_REG, | ||
2011 | .mask = PMX_GPIO_PIN2_MASK | PMX_GPIO_PIN3_MASK, | ||
2012 | .val = 0, | ||
2013 | }, { | ||
2014 | .reg = IP_SEL_PAD_30_39_REG, | ||
2015 | .mask = PMX_PL_30_MASK | PMX_PL_31_MASK, | ||
2016 | .val = PMX_PWM1_EXT_PL_30_VAL | PMX_PWM0_EXT_PL_31_VAL, | ||
2017 | }, | ||
2018 | }; | ||
2019 | |||
2020 | static struct spear_muxreg pwm0_1_net_muxreg[] = { | ||
2021 | { | ||
2022 | .reg = PMX_CONFIG_REG, | ||
2023 | .mask = PMX_UART0_MODEM_MASK, | ||
2024 | .val = 0, | ||
2025 | }, | ||
2026 | }; | ||
2027 | |||
2028 | static struct spear_muxreg pwm0_1_pin_37_38_muxreg[] = { | ||
2029 | { | ||
2030 | .reg = IP_SEL_PAD_30_39_REG, | ||
2031 | .mask = PMX_PL_37_38_MASK, | ||
2032 | .val = PMX_PWM0_1_PL_37_38_VAL, | ||
2033 | }, | ||
2034 | }; | ||
2035 | |||
2036 | static struct spear_muxreg pwm0_1_pin_42_43_muxreg[] = { | ||
2037 | { | ||
2038 | .reg = PMX_CONFIG_REG, | ||
2039 | .mask = PMX_UART0_MODEM_MASK | PMX_TIMER_0_1_MASK , | ||
2040 | .val = 0, | ||
2041 | }, { | ||
2042 | .reg = IP_SEL_PAD_40_49_REG, | ||
2043 | .mask = PMX_PL_42_MASK | PMX_PL_43_MASK, | ||
2044 | .val = PMX_PWM1_PL_42_VAL | | ||
2045 | PMX_PWM0_PL_43_VAL, | ||
2046 | }, | ||
2047 | }; | ||
2048 | |||
2049 | static struct spear_muxreg pwm0_1_pin_59_60_muxreg[] = { | ||
2050 | { | ||
2051 | .reg = IP_SEL_PAD_50_59_REG, | ||
2052 | .mask = PMX_PL_59_MASK, | ||
2053 | .val = PMX_PWM1_PL_59_VAL, | ||
2054 | }, { | ||
2055 | .reg = IP_SEL_PAD_60_69_REG, | ||
2056 | .mask = PMX_PL_60_MASK, | ||
2057 | .val = PMX_PWM0_PL_60_VAL, | ||
2058 | }, | ||
2059 | }; | ||
2060 | |||
2061 | static struct spear_muxreg pwm0_1_pin_88_89_muxreg[] = { | ||
2062 | { | ||
2063 | .reg = IP_SEL_PAD_80_89_REG, | ||
2064 | .mask = PMX_PL_88_89_MASK, | ||
2065 | .val = PMX_PWM0_1_PL_88_89_VAL, | ||
2066 | }, | ||
2067 | }; | ||
2068 | |||
2069 | static struct spear_modemux pwm0_1_pin_8_9_modemux[] = { | ||
2070 | { | ||
2071 | .modes = EXTENDED_MODE, | ||
2072 | .muxregs = pwm0_1_pin_8_9_muxreg, | ||
2073 | .nmuxregs = ARRAY_SIZE(pwm0_1_pin_8_9_muxreg), | ||
2074 | }, | ||
2075 | }; | ||
2076 | |||
2077 | static struct spear_modemux pwm0_1_pin_14_15_modemux[] = { | ||
2078 | { | ||
2079 | .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, | ||
2080 | .muxregs = pwm0_1_autoexpsmallpri_muxreg, | ||
2081 | .nmuxregs = ARRAY_SIZE(pwm0_1_autoexpsmallpri_muxreg), | ||
2082 | }, { | ||
2083 | .modes = EXTENDED_MODE, | ||
2084 | .muxregs = pwm0_1_pin_14_15_muxreg, | ||
2085 | .nmuxregs = ARRAY_SIZE(pwm0_1_pin_14_15_muxreg), | ||
2086 | }, | ||
2087 | }; | ||
2088 | |||
2089 | static struct spear_modemux pwm0_1_pin_30_31_modemux[] = { | ||
2090 | { | ||
2091 | .modes = EXTENDED_MODE, | ||
2092 | .muxregs = pwm0_1_pin_30_31_muxreg, | ||
2093 | .nmuxregs = ARRAY_SIZE(pwm0_1_pin_30_31_muxreg), | ||
2094 | }, | ||
2095 | }; | ||
2096 | |||
2097 | static struct spear_modemux pwm0_1_pin_37_38_modemux[] = { | ||
2098 | { | ||
2099 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, | ||
2100 | .muxregs = pwm0_1_net_muxreg, | ||
2101 | .nmuxregs = ARRAY_SIZE(pwm0_1_net_muxreg), | ||
2102 | }, { | ||
2103 | .modes = EXTENDED_MODE, | ||
2104 | .muxregs = pwm0_1_pin_37_38_muxreg, | ||
2105 | .nmuxregs = ARRAY_SIZE(pwm0_1_pin_37_38_muxreg), | ||
2106 | }, | ||
2107 | }; | ||
2108 | |||
2109 | static struct spear_modemux pwm0_1_pin_42_43_modemux[] = { | ||
2110 | { | ||
2111 | .modes = EXTENDED_MODE, | ||
2112 | .muxregs = pwm0_1_pin_42_43_muxreg, | ||
2113 | .nmuxregs = ARRAY_SIZE(pwm0_1_pin_42_43_muxreg), | ||
2114 | }, | ||
2115 | }; | ||
2116 | |||
2117 | static struct spear_modemux pwm0_1_pin_59_60_modemux[] = { | ||
2118 | { | ||
2119 | .modes = EXTENDED_MODE, | ||
2120 | .muxregs = pwm0_1_pin_59_60_muxreg, | ||
2121 | .nmuxregs = ARRAY_SIZE(pwm0_1_pin_59_60_muxreg), | ||
2122 | }, | ||
2123 | }; | ||
2124 | |||
2125 | static struct spear_modemux pwm0_1_pin_88_89_modemux[] = { | ||
2126 | { | ||
2127 | .modes = EXTENDED_MODE, | ||
2128 | .muxregs = pwm0_1_pin_88_89_muxreg, | ||
2129 | .nmuxregs = ARRAY_SIZE(pwm0_1_pin_88_89_muxreg), | ||
2130 | }, | ||
2131 | }; | ||
2132 | |||
2133 | static struct spear_pingroup pwm0_1_pingroup[] = { | ||
2134 | { | ||
2135 | .name = "pwm0_1_pin_8_9_grp", | ||
2136 | .pins = pwm0_1_pins[0], | ||
2137 | .npins = ARRAY_SIZE(pwm0_1_pins[0]), | ||
2138 | .modemuxs = pwm0_1_pin_8_9_modemux, | ||
2139 | .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_8_9_modemux), | ||
2140 | }, { | ||
2141 | .name = "pwm0_1_pin_14_15_grp", | ||
2142 | .pins = pwm0_1_pins[1], | ||
2143 | .npins = ARRAY_SIZE(pwm0_1_pins[1]), | ||
2144 | .modemuxs = pwm0_1_pin_14_15_modemux, | ||
2145 | .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_14_15_modemux), | ||
2146 | }, { | ||
2147 | .name = "pwm0_1_pin_30_31_grp", | ||
2148 | .pins = pwm0_1_pins[2], | ||
2149 | .npins = ARRAY_SIZE(pwm0_1_pins[2]), | ||
2150 | .modemuxs = pwm0_1_pin_30_31_modemux, | ||
2151 | .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_30_31_modemux), | ||
2152 | }, { | ||
2153 | .name = "pwm0_1_pin_37_38_grp", | ||
2154 | .pins = pwm0_1_pins[3], | ||
2155 | .npins = ARRAY_SIZE(pwm0_1_pins[3]), | ||
2156 | .modemuxs = pwm0_1_pin_37_38_modemux, | ||
2157 | .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_37_38_modemux), | ||
2158 | }, { | ||
2159 | .name = "pwm0_1_pin_42_43_grp", | ||
2160 | .pins = pwm0_1_pins[4], | ||
2161 | .npins = ARRAY_SIZE(pwm0_1_pins[4]), | ||
2162 | .modemuxs = pwm0_1_pin_42_43_modemux, | ||
2163 | .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_42_43_modemux), | ||
2164 | }, { | ||
2165 | .name = "pwm0_1_pin_59_60_grp", | ||
2166 | .pins = pwm0_1_pins[5], | ||
2167 | .npins = ARRAY_SIZE(pwm0_1_pins[5]), | ||
2168 | .modemuxs = pwm0_1_pin_59_60_modemux, | ||
2169 | .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_59_60_modemux), | ||
2170 | }, { | ||
2171 | .name = "pwm0_1_pin_88_89_grp", | ||
2172 | .pins = pwm0_1_pins[6], | ||
2173 | .npins = ARRAY_SIZE(pwm0_1_pins[6]), | ||
2174 | .modemuxs = pwm0_1_pin_88_89_modemux, | ||
2175 | .nmodemuxs = ARRAY_SIZE(pwm0_1_pin_88_89_modemux), | ||
2176 | }, | ||
2177 | }; | ||
2178 | |||
2179 | static const char *const pwm0_1_grps[] = { "pwm0_1_pin_8_9_grp", | ||
2180 | "pwm0_1_pin_14_15_grp", "pwm0_1_pin_30_31_grp", "pwm0_1_pin_37_38_grp", | ||
2181 | "pwm0_1_pin_42_43_grp", "pwm0_1_pin_59_60_grp", "pwm0_1_pin_88_89_grp" | ||
2182 | }; | ||
2183 | |||
2184 | static struct spear_function pwm0_1_function = { | ||
2185 | .name = "pwm0_1", | ||
2186 | .groups = pwm0_1_grps, | ||
2187 | .ngroups = ARRAY_SIZE(pwm0_1_grps), | ||
2188 | }; | ||
2189 | |||
2190 | /* Pad multiplexing for PWM2 device */ | ||
2191 | static const unsigned pwm2_pins[][1] = { { 7 }, { 13 }, { 29 }, { 34 }, { 41 }, | ||
2192 | { 58 }, { 87 } }; | ||
2193 | static struct spear_muxreg pwm2_net_muxreg[] = { | ||
2194 | { | ||
2195 | .reg = PMX_CONFIG_REG, | ||
2196 | .mask = PMX_SSP_CS_MASK, | ||
2197 | .val = 0, | ||
2198 | }, | ||
2199 | }; | ||
2200 | |||
2201 | static struct spear_muxreg pwm2_pin_7_muxreg[] = { | ||
2202 | { | ||
2203 | .reg = IP_SEL_PAD_0_9_REG, | ||
2204 | .mask = PMX_PL_7_MASK, | ||
2205 | .val = PMX_PWM_2_PL_7_VAL, | ||
2206 | }, | ||
2207 | }; | ||
2208 | |||
2209 | static struct spear_muxreg pwm2_autoexpsmallpri_muxreg[] = { | ||
2210 | { | ||
2211 | .reg = PMX_CONFIG_REG, | ||
2212 | .mask = PMX_MII_MASK, | ||
2213 | .val = 0, | ||
2214 | }, | ||
2215 | }; | ||
2216 | |||
2217 | static struct spear_muxreg pwm2_pin_13_muxreg[] = { | ||
2218 | { | ||
2219 | .reg = IP_SEL_PAD_10_19_REG, | ||
2220 | .mask = PMX_PL_13_MASK, | ||
2221 | .val = PMX_PWM2_PL_13_VAL, | ||
2222 | }, | ||
2223 | }; | ||
2224 | |||
2225 | static struct spear_muxreg pwm2_pin_29_muxreg[] = { | ||
2226 | { | ||
2227 | .reg = PMX_CONFIG_REG, | ||
2228 | .mask = PMX_GPIO_PIN1_MASK, | ||
2229 | .val = 0, | ||
2230 | }, { | ||
2231 | .reg = IP_SEL_PAD_20_29_REG, | ||
2232 | .mask = PMX_PL_29_MASK, | ||
2233 | .val = PMX_PWM_2_PL_29_VAL, | ||
2234 | }, | ||
2235 | }; | ||
2236 | |||
2237 | static struct spear_muxreg pwm2_pin_34_muxreg[] = { | ||
2238 | { | ||
2239 | .reg = PMX_CONFIG_REG, | ||
2240 | .mask = PMX_SSP_CS_MASK, | ||
2241 | .val = 0, | ||
2242 | }, { | ||
2243 | .reg = IP_SEL_PAD_30_39_REG, | ||
2244 | .mask = PMX_PL_34_MASK, | ||
2245 | .val = PMX_PWM2_PL_34_VAL, | ||
2246 | }, | ||
2247 | }; | ||
2248 | |||
2249 | static struct spear_muxreg pwm2_pin_41_muxreg[] = { | ||
2250 | { | ||
2251 | .reg = PMX_CONFIG_REG, | ||
2252 | .mask = PMX_UART0_MODEM_MASK, | ||
2253 | .val = 0, | ||
2254 | }, { | ||
2255 | .reg = IP_SEL_PAD_40_49_REG, | ||
2256 | .mask = PMX_PL_41_MASK, | ||
2257 | .val = PMX_PWM2_PL_41_VAL, | ||
2258 | }, | ||
2259 | }; | ||
2260 | |||
2261 | static struct spear_muxreg pwm2_pin_58_muxreg[] = { | ||
2262 | { | ||
2263 | .reg = IP_SEL_PAD_50_59_REG, | ||
2264 | .mask = PMX_PL_58_MASK, | ||
2265 | .val = PMX_PWM2_PL_58_VAL, | ||
2266 | }, | ||
2267 | }; | ||
2268 | |||
2269 | static struct spear_muxreg pwm2_pin_87_muxreg[] = { | ||
2270 | { | ||
2271 | .reg = IP_SEL_PAD_80_89_REG, | ||
2272 | .mask = PMX_PL_87_MASK, | ||
2273 | .val = PMX_PWM2_PL_87_VAL, | ||
2274 | }, | ||
2275 | }; | ||
2276 | |||
2277 | static struct spear_modemux pwm2_pin_7_modemux[] = { | ||
2278 | { | ||
2279 | .modes = AUTO_NET_SMII_MODE | AUTO_NET_MII_MODE | EXTENDED_MODE, | ||
2280 | .muxregs = pwm2_net_muxreg, | ||
2281 | .nmuxregs = ARRAY_SIZE(pwm2_net_muxreg), | ||
2282 | }, { | ||
2283 | .modes = EXTENDED_MODE, | ||
2284 | .muxregs = pwm2_pin_7_muxreg, | ||
2285 | .nmuxregs = ARRAY_SIZE(pwm2_pin_7_muxreg), | ||
2286 | }, | ||
2287 | }; | ||
2288 | static struct spear_modemux pwm2_pin_13_modemux[] = { | ||
2289 | { | ||
2290 | .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | EXTENDED_MODE, | ||
2291 | .muxregs = pwm2_autoexpsmallpri_muxreg, | ||
2292 | .nmuxregs = ARRAY_SIZE(pwm2_autoexpsmallpri_muxreg), | ||
2293 | }, { | ||
2294 | .modes = EXTENDED_MODE, | ||
2295 | .muxregs = pwm2_pin_13_muxreg, | ||
2296 | .nmuxregs = ARRAY_SIZE(pwm2_pin_13_muxreg), | ||
2297 | }, | ||
2298 | }; | ||
2299 | static struct spear_modemux pwm2_pin_29_modemux[] = { | ||
2300 | { | ||
2301 | .modes = EXTENDED_MODE, | ||
2302 | .muxregs = pwm2_pin_29_muxreg, | ||
2303 | .nmuxregs = ARRAY_SIZE(pwm2_pin_29_muxreg), | ||
2304 | }, | ||
2305 | }; | ||
2306 | static struct spear_modemux pwm2_pin_34_modemux[] = { | ||
2307 | { | ||
2308 | .modes = EXTENDED_MODE, | ||
2309 | .muxregs = pwm2_pin_34_muxreg, | ||
2310 | .nmuxregs = ARRAY_SIZE(pwm2_pin_34_muxreg), | ||
2311 | }, | ||
2312 | }; | ||
2313 | |||
2314 | static struct spear_modemux pwm2_pin_41_modemux[] = { | ||
2315 | { | ||
2316 | .modes = EXTENDED_MODE, | ||
2317 | .muxregs = pwm2_pin_41_muxreg, | ||
2318 | .nmuxregs = ARRAY_SIZE(pwm2_pin_41_muxreg), | ||
2319 | }, | ||
2320 | }; | ||
2321 | |||
2322 | static struct spear_modemux pwm2_pin_58_modemux[] = { | ||
2323 | { | ||
2324 | .modes = EXTENDED_MODE, | ||
2325 | .muxregs = pwm2_pin_58_muxreg, | ||
2326 | .nmuxregs = ARRAY_SIZE(pwm2_pin_58_muxreg), | ||
2327 | }, | ||
2328 | }; | ||
2329 | |||
2330 | static struct spear_modemux pwm2_pin_87_modemux[] = { | ||
2331 | { | ||
2332 | .modes = EXTENDED_MODE, | ||
2333 | .muxregs = pwm2_pin_87_muxreg, | ||
2334 | .nmuxregs = ARRAY_SIZE(pwm2_pin_87_muxreg), | ||
2335 | }, | ||
2336 | }; | ||
2337 | |||
2338 | static struct spear_pingroup pwm2_pingroup[] = { | ||
2339 | { | ||
2340 | .name = "pwm2_pin_7_grp", | ||
2341 | .pins = pwm2_pins[0], | ||
2342 | .npins = ARRAY_SIZE(pwm2_pins[0]), | ||
2343 | .modemuxs = pwm2_pin_7_modemux, | ||
2344 | .nmodemuxs = ARRAY_SIZE(pwm2_pin_7_modemux), | ||
2345 | }, { | ||
2346 | .name = "pwm2_pin_13_grp", | ||
2347 | .pins = pwm2_pins[1], | ||
2348 | .npins = ARRAY_SIZE(pwm2_pins[1]), | ||
2349 | .modemuxs = pwm2_pin_13_modemux, | ||
2350 | .nmodemuxs = ARRAY_SIZE(pwm2_pin_13_modemux), | ||
2351 | }, { | ||
2352 | .name = "pwm2_pin_29_grp", | ||
2353 | .pins = pwm2_pins[2], | ||
2354 | .npins = ARRAY_SIZE(pwm2_pins[2]), | ||
2355 | .modemuxs = pwm2_pin_29_modemux, | ||
2356 | .nmodemuxs = ARRAY_SIZE(pwm2_pin_29_modemux), | ||
2357 | }, { | ||
2358 | .name = "pwm2_pin_34_grp", | ||
2359 | .pins = pwm2_pins[3], | ||
2360 | .npins = ARRAY_SIZE(pwm2_pins[3]), | ||
2361 | .modemuxs = pwm2_pin_34_modemux, | ||
2362 | .nmodemuxs = ARRAY_SIZE(pwm2_pin_34_modemux), | ||
2363 | }, { | ||
2364 | .name = "pwm2_pin_41_grp", | ||
2365 | .pins = pwm2_pins[4], | ||
2366 | .npins = ARRAY_SIZE(pwm2_pins[4]), | ||
2367 | .modemuxs = pwm2_pin_41_modemux, | ||
2368 | .nmodemuxs = ARRAY_SIZE(pwm2_pin_41_modemux), | ||
2369 | }, { | ||
2370 | .name = "pwm2_pin_58_grp", | ||
2371 | .pins = pwm2_pins[5], | ||
2372 | .npins = ARRAY_SIZE(pwm2_pins[5]), | ||
2373 | .modemuxs = pwm2_pin_58_modemux, | ||
2374 | .nmodemuxs = ARRAY_SIZE(pwm2_pin_58_modemux), | ||
2375 | }, { | ||
2376 | .name = "pwm2_pin_87_grp", | ||
2377 | .pins = pwm2_pins[6], | ||
2378 | .npins = ARRAY_SIZE(pwm2_pins[6]), | ||
2379 | .modemuxs = pwm2_pin_87_modemux, | ||
2380 | .nmodemuxs = ARRAY_SIZE(pwm2_pin_87_modemux), | ||
2381 | }, | ||
2382 | }; | ||
2383 | |||
2384 | static const char *const pwm2_grps[] = { "pwm2_pin_7_grp", "pwm2_pin_13_grp", | ||
2385 | "pwm2_pin_29_grp", "pwm2_pin_34_grp", "pwm2_pin_41_grp", | ||
2386 | "pwm2_pin_58_grp", "pwm2_pin_87_grp" }; | ||
2387 | static struct spear_function pwm2_function = { | ||
2388 | .name = "pwm2", | ||
2389 | .groups = pwm2_grps, | ||
2390 | .ngroups = ARRAY_SIZE(pwm2_grps), | ||
2391 | }; | ||
2392 | |||
2393 | /* Pad multiplexing for PWM3 device */ | ||
2394 | static const unsigned pwm3_pins[][1] = { { 6 }, { 12 }, { 28 }, { 40 }, { 57 }, | ||
2395 | { 86 } }; | ||
2396 | static struct spear_muxreg pwm3_pin_6_muxreg[] = { | ||
2397 | { | ||
2398 | .reg = PMX_CONFIG_REG, | ||
2399 | .mask = PMX_SSP_MASK, | ||
2400 | .val = 0, | ||
2401 | }, { | ||
2402 | .reg = IP_SEL_PAD_0_9_REG, | ||
2403 | .mask = PMX_PL_6_MASK, | ||
2404 | .val = PMX_PWM_3_PL_6_VAL, | ||
2405 | }, | ||
2406 | }; | ||
2407 | |||
2408 | static struct spear_muxreg pwm3_muxreg[] = { | ||
2409 | { | ||
2410 | .reg = PMX_CONFIG_REG, | ||
2411 | .mask = PMX_MII_MASK, | ||
2412 | .val = 0, | ||
2413 | }, | ||
2414 | }; | ||
2415 | |||
2416 | static struct spear_muxreg pwm3_pin_12_muxreg[] = { | ||
2417 | { | ||
2418 | .reg = IP_SEL_PAD_10_19_REG, | ||
2419 | .mask = PMX_PL_12_MASK, | ||
2420 | .val = PMX_PWM3_PL_12_VAL, | ||
2421 | }, | ||
2422 | }; | ||
2423 | |||
2424 | static struct spear_muxreg pwm3_pin_28_muxreg[] = { | ||
2425 | { | ||
2426 | .reg = PMX_CONFIG_REG, | ||
2427 | .mask = PMX_GPIO_PIN0_MASK, | ||
2428 | .val = 0, | ||
2429 | }, { | ||
2430 | .reg = IP_SEL_PAD_20_29_REG, | ||
2431 | .mask = PMX_PL_28_MASK, | ||
2432 | .val = PMX_PWM_3_PL_28_VAL, | ||
2433 | }, | ||
2434 | }; | ||
2435 | |||
2436 | static struct spear_muxreg pwm3_pin_40_muxreg[] = { | ||
2437 | { | ||
2438 | .reg = PMX_CONFIG_REG, | ||
2439 | .mask = PMX_UART0_MODEM_MASK, | ||
2440 | .val = 0, | ||
2441 | }, { | ||
2442 | .reg = IP_SEL_PAD_40_49_REG, | ||
2443 | .mask = PMX_PL_40_MASK, | ||
2444 | .val = PMX_PWM3_PL_40_VAL, | ||
2445 | }, | ||
2446 | }; | ||
2447 | |||
2448 | static struct spear_muxreg pwm3_pin_57_muxreg[] = { | ||
2449 | { | ||
2450 | .reg = IP_SEL_PAD_50_59_REG, | ||
2451 | .mask = PMX_PL_57_MASK, | ||
2452 | .val = PMX_PWM3_PL_57_VAL, | ||
2453 | }, | ||
2454 | }; | ||
2455 | |||
2456 | static struct spear_muxreg pwm3_pin_86_muxreg[] = { | ||
2457 | { | ||
2458 | .reg = IP_SEL_PAD_80_89_REG, | ||
2459 | .mask = PMX_PL_86_MASK, | ||
2460 | .val = PMX_PWM3_PL_86_VAL, | ||
2461 | }, | ||
2462 | }; | ||
2463 | |||
2464 | static struct spear_modemux pwm3_pin_6_modemux[] = { | ||
2465 | { | ||
2466 | .modes = EXTENDED_MODE, | ||
2467 | .muxregs = pwm3_pin_6_muxreg, | ||
2468 | .nmuxregs = ARRAY_SIZE(pwm3_pin_6_muxreg), | ||
2469 | }, | ||
2470 | }; | ||
2471 | |||
2472 | static struct spear_modemux pwm3_pin_12_modemux[] = { | ||
2473 | { | ||
2474 | .modes = AUTO_EXP_MODE | SMALL_PRINTERS_MODE | | ||
2475 | AUTO_NET_SMII_MODE | EXTENDED_MODE, | ||
2476 | .muxregs = pwm3_muxreg, | ||
2477 | .nmuxregs = ARRAY_SIZE(pwm3_muxreg), | ||
2478 | }, { | ||
2479 | .modes = EXTENDED_MODE, | ||
2480 | .muxregs = pwm3_pin_12_muxreg, | ||
2481 | .nmuxregs = ARRAY_SIZE(pwm3_pin_12_muxreg), | ||
2482 | }, | ||
2483 | }; | ||
2484 | |||
2485 | static struct spear_modemux pwm3_pin_28_modemux[] = { | ||
2486 | { | ||
2487 | .modes = EXTENDED_MODE, | ||
2488 | .muxregs = pwm3_pin_28_muxreg, | ||
2489 | .nmuxregs = ARRAY_SIZE(pwm3_pin_28_muxreg), | ||
2490 | }, | ||
2491 | }; | ||
2492 | |||
2493 | static struct spear_modemux pwm3_pin_40_modemux[] = { | ||
2494 | { | ||
2495 | .modes = EXTENDED_MODE, | ||
2496 | .muxregs = pwm3_pin_40_muxreg, | ||
2497 | .nmuxregs = ARRAY_SIZE(pwm3_pin_40_muxreg), | ||
2498 | }, | ||
2499 | }; | ||
2500 | |||
2501 | static struct spear_modemux pwm3_pin_57_modemux[] = { | ||
2502 | { | ||
2503 | .modes = EXTENDED_MODE, | ||
2504 | .muxregs = pwm3_pin_57_muxreg, | ||
2505 | .nmuxregs = ARRAY_SIZE(pwm3_pin_57_muxreg), | ||
2506 | }, | ||
2507 | }; | ||
2508 | |||
2509 | static struct spear_modemux pwm3_pin_86_modemux[] = { | ||
2510 | { | ||
2511 | .modes = EXTENDED_MODE, | ||
2512 | .muxregs = pwm3_pin_86_muxreg, | ||
2513 | .nmuxregs = ARRAY_SIZE(pwm3_pin_86_muxreg), | ||
2514 | }, | ||
2515 | }; | ||
2516 | |||
2517 | static struct spear_pingroup pwm3_pingroup[] = { | ||
2518 | { | ||
2519 | .name = "pwm3_pin_6_grp", | ||
2520 | .pins = pwm3_pins[0], | ||
2521 | .npins = ARRAY_SIZE(pwm3_pins[0]), | ||
2522 | .modemuxs = pwm3_pin_6_modemux, | ||
2523 | .nmodemuxs = ARRAY_SIZE(pwm3_pin_6_modemux), | ||
2524 | }, { | ||
2525 | .name = "pwm3_pin_12_grp", | ||
2526 | .pins = pwm3_pins[1], | ||
2527 | .npins = ARRAY_SIZE(pwm3_pins[1]), | ||
2528 | .modemuxs = pwm3_pin_12_modemux, | ||
2529 | .nmodemuxs = ARRAY_SIZE(pwm3_pin_12_modemux), | ||
2530 | }, { | ||
2531 | .name = "pwm3_pin_28_grp", | ||
2532 | .pins = pwm3_pins[2], | ||
2533 | .npins = ARRAY_SIZE(pwm3_pins[2]), | ||
2534 | .modemuxs = pwm3_pin_28_modemux, | ||
2535 | .nmodemuxs = ARRAY_SIZE(pwm3_pin_28_modemux), | ||
2536 | }, { | ||
2537 | .name = "pwm3_pin_40_grp", | ||
2538 | .pins = pwm3_pins[3], | ||
2539 | .npins = ARRAY_SIZE(pwm3_pins[3]), | ||
2540 | .modemuxs = pwm3_pin_40_modemux, | ||
2541 | .nmodemuxs = ARRAY_SIZE(pwm3_pin_40_modemux), | ||
2542 | }, { | ||
2543 | .name = "pwm3_pin_57_grp", | ||
2544 | .pins = pwm3_pins[4], | ||
2545 | .npins = ARRAY_SIZE(pwm3_pins[4]), | ||
2546 | .modemuxs = pwm3_pin_57_modemux, | ||
2547 | .nmodemuxs = ARRAY_SIZE(pwm3_pin_57_modemux), | ||
2548 | }, { | ||
2549 | .name = "pwm3_pin_86_grp", | ||
2550 | .pins = pwm3_pins[5], | ||
2551 | .npins = ARRAY_SIZE(pwm3_pins[5]), | ||
2552 | .modemuxs = pwm3_pin_86_modemux, | ||
2553 | .nmodemuxs = ARRAY_SIZE(pwm3_pin_86_modemux), | ||
2554 | }, | ||
2555 | }; | ||
2556 | |||
2557 | static const char *const pwm3_grps[] = { "pwm3_pin_6_grp", "pwm3_pin_12_grp", | ||
2558 | "pwm3_pin_28_grp", "pwm3_pin_40_grp", "pwm3_pin_57_grp", | ||
2559 | "pwm3_pin_86_grp" }; | ||
2560 | static struct spear_function pwm3_function = { | ||
2561 | .name = "pwm3", | ||
2562 | .groups = pwm3_grps, | ||
2563 | .ngroups = ARRAY_SIZE(pwm3_grps), | ||
2564 | }; | ||
2565 | |||
2566 | /* Pad multiplexing for SSP1 device */ | ||
2567 | static const unsigned ssp1_pins[][2] = { { 17, 20 }, { 36, 39 }, { 48, 51 }, | ||
2568 | { 65, 68 }, { 94, 97 } }; | ||
2569 | static struct spear_muxreg ssp1_muxreg[] = { | ||
2570 | { | ||
2571 | .reg = PMX_CONFIG_REG, | ||
2572 | .mask = PMX_MII_MASK, | ||
2573 | .val = 0, | ||
2574 | }, | ||
2575 | }; | ||
2576 | |||
2577 | static struct spear_muxreg ssp1_ext_17_20_muxreg[] = { | ||
2578 | { | ||
2579 | .reg = IP_SEL_PAD_10_19_REG, | ||
2580 | .mask = PMX_PL_17_18_MASK | PMX_PL_19_MASK, | ||
2581 | .val = PMX_SSP1_PL_17_18_19_20_VAL, | ||
2582 | }, { | ||
2583 | .reg = IP_SEL_PAD_20_29_REG, | ||
2584 | .mask = PMX_PL_20_MASK, | ||
2585 | .val = PMX_SSP1_PL_17_18_19_20_VAL, | ||
2586 | }, { | ||
2587 | .reg = IP_SEL_MIX_PAD_REG, | ||
2588 | .mask = PMX_SSP1_PORT_SEL_MASK, | ||
2589 | .val = PMX_SSP1_PORT_17_TO_20_VAL, | ||
2590 | }, | ||
2591 | }; | ||
2592 | |||
2593 | static struct spear_muxreg ssp1_ext_36_39_muxreg[] = { | ||
2594 | { | ||
2595 | .reg = PMX_CONFIG_REG, | ||
2596 | .mask = PMX_UART0_MODEM_MASK | PMX_SSP_CS_MASK, | ||
2597 | .val = 0, | ||
2598 | }, { | ||
2599 | .reg = IP_SEL_PAD_30_39_REG, | ||
2600 | .mask = PMX_PL_36_MASK | PMX_PL_37_38_MASK | PMX_PL_39_MASK, | ||
2601 | .val = PMX_SSP1_PL_36_VAL | PMX_SSP1_PL_37_38_VAL | | ||
2602 | PMX_SSP1_PL_39_VAL, | ||
2603 | }, { | ||
2604 | .reg = IP_SEL_MIX_PAD_REG, | ||
2605 | .mask = PMX_SSP1_PORT_SEL_MASK, | ||
2606 | .val = PMX_SSP1_PORT_36_TO_39_VAL, | ||
2607 | }, | ||
2608 | }; | ||
2609 | |||
2610 | static struct spear_muxreg ssp1_ext_48_51_muxreg[] = { | ||
2611 | { | ||
2612 | .reg = PMX_CONFIG_REG, | ||
2613 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
2614 | .val = 0, | ||
2615 | }, { | ||
2616 | .reg = IP_SEL_PAD_40_49_REG, | ||
2617 | .mask = PMX_PL_48_49_MASK, | ||
2618 | .val = PMX_SSP1_PL_48_49_VAL, | ||
2619 | }, { | ||
2620 | .reg = IP_SEL_PAD_50_59_REG, | ||
2621 | .mask = PMX_PL_50_51_MASK, | ||
2622 | .val = PMX_SSP1_PL_50_51_VAL, | ||
2623 | }, { | ||
2624 | .reg = IP_SEL_MIX_PAD_REG, | ||
2625 | .mask = PMX_SSP1_PORT_SEL_MASK, | ||
2626 | .val = PMX_SSP1_PORT_48_TO_51_VAL, | ||
2627 | }, | ||
2628 | }; | ||
2629 | |||
2630 | static struct spear_muxreg ssp1_ext_65_68_muxreg[] = { | ||
2631 | { | ||
2632 | .reg = IP_SEL_PAD_60_69_REG, | ||
2633 | .mask = PMX_PL_65_TO_68_MASK, | ||
2634 | .val = PMX_SSP1_PL_65_TO_68_VAL, | ||
2635 | }, { | ||
2636 | .reg = IP_SEL_MIX_PAD_REG, | ||
2637 | .mask = PMX_SSP1_PORT_SEL_MASK, | ||
2638 | .val = PMX_SSP1_PORT_65_TO_68_VAL, | ||
2639 | }, | ||
2640 | }; | ||
2641 | |||
2642 | static struct spear_muxreg ssp1_ext_94_97_muxreg[] = { | ||
2643 | { | ||
2644 | .reg = IP_SEL_PAD_90_99_REG, | ||
2645 | .mask = PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, | ||
2646 | .val = PMX_SSP1_PL_94_95_VAL | PMX_SSP1_PL_96_97_VAL, | ||
2647 | }, { | ||
2648 | .reg = IP_SEL_MIX_PAD_REG, | ||
2649 | .mask = PMX_SSP1_PORT_SEL_MASK, | ||
2650 | .val = PMX_SSP1_PORT_94_TO_97_VAL, | ||
2651 | }, | ||
2652 | }; | ||
2653 | |||
2654 | static struct spear_modemux ssp1_17_20_modemux[] = { | ||
2655 | { | ||
2656 | .modes = SMALL_PRINTERS_MODE | AUTO_NET_SMII_MODE | | ||
2657 | EXTENDED_MODE, | ||
2658 | .muxregs = ssp1_muxreg, | ||
2659 | .nmuxregs = ARRAY_SIZE(ssp1_muxreg), | ||
2660 | }, { | ||
2661 | .modes = EXTENDED_MODE, | ||
2662 | .muxregs = ssp1_ext_17_20_muxreg, | ||
2663 | .nmuxregs = ARRAY_SIZE(ssp1_ext_17_20_muxreg), | ||
2664 | }, | ||
2665 | }; | ||
2666 | |||
2667 | static struct spear_modemux ssp1_36_39_modemux[] = { | ||
2668 | { | ||
2669 | .modes = EXTENDED_MODE, | ||
2670 | .muxregs = ssp1_ext_36_39_muxreg, | ||
2671 | .nmuxregs = ARRAY_SIZE(ssp1_ext_36_39_muxreg), | ||
2672 | }, | ||
2673 | }; | ||
2674 | |||
2675 | static struct spear_modemux ssp1_48_51_modemux[] = { | ||
2676 | { | ||
2677 | .modes = EXTENDED_MODE, | ||
2678 | .muxregs = ssp1_ext_48_51_muxreg, | ||
2679 | .nmuxregs = ARRAY_SIZE(ssp1_ext_48_51_muxreg), | ||
2680 | }, | ||
2681 | }; | ||
2682 | static struct spear_modemux ssp1_65_68_modemux[] = { | ||
2683 | { | ||
2684 | .modes = EXTENDED_MODE, | ||
2685 | .muxregs = ssp1_ext_65_68_muxreg, | ||
2686 | .nmuxregs = ARRAY_SIZE(ssp1_ext_65_68_muxreg), | ||
2687 | }, | ||
2688 | }; | ||
2689 | |||
2690 | static struct spear_modemux ssp1_94_97_modemux[] = { | ||
2691 | { | ||
2692 | .modes = EXTENDED_MODE, | ||
2693 | .muxregs = ssp1_ext_94_97_muxreg, | ||
2694 | .nmuxregs = ARRAY_SIZE(ssp1_ext_94_97_muxreg), | ||
2695 | }, | ||
2696 | }; | ||
2697 | |||
2698 | static struct spear_pingroup ssp1_pingroup[] = { | ||
2699 | { | ||
2700 | .name = "ssp1_17_20_grp", | ||
2701 | .pins = ssp1_pins[0], | ||
2702 | .npins = ARRAY_SIZE(ssp1_pins[0]), | ||
2703 | .modemuxs = ssp1_17_20_modemux, | ||
2704 | .nmodemuxs = ARRAY_SIZE(ssp1_17_20_modemux), | ||
2705 | }, { | ||
2706 | .name = "ssp1_36_39_grp", | ||
2707 | .pins = ssp1_pins[1], | ||
2708 | .npins = ARRAY_SIZE(ssp1_pins[1]), | ||
2709 | .modemuxs = ssp1_36_39_modemux, | ||
2710 | .nmodemuxs = ARRAY_SIZE(ssp1_36_39_modemux), | ||
2711 | }, { | ||
2712 | .name = "ssp1_48_51_grp", | ||
2713 | .pins = ssp1_pins[2], | ||
2714 | .npins = ARRAY_SIZE(ssp1_pins[2]), | ||
2715 | .modemuxs = ssp1_48_51_modemux, | ||
2716 | .nmodemuxs = ARRAY_SIZE(ssp1_48_51_modemux), | ||
2717 | }, { | ||
2718 | .name = "ssp1_65_68_grp", | ||
2719 | .pins = ssp1_pins[3], | ||
2720 | .npins = ARRAY_SIZE(ssp1_pins[3]), | ||
2721 | .modemuxs = ssp1_65_68_modemux, | ||
2722 | .nmodemuxs = ARRAY_SIZE(ssp1_65_68_modemux), | ||
2723 | }, { | ||
2724 | .name = "ssp1_94_97_grp", | ||
2725 | .pins = ssp1_pins[4], | ||
2726 | .npins = ARRAY_SIZE(ssp1_pins[4]), | ||
2727 | .modemuxs = ssp1_94_97_modemux, | ||
2728 | .nmodemuxs = ARRAY_SIZE(ssp1_94_97_modemux), | ||
2729 | }, | ||
2730 | }; | ||
2731 | |||
2732 | static const char *const ssp1_grps[] = { "ssp1_17_20_grp", "ssp1_36_39_grp", | ||
2733 | "ssp1_48_51_grp", "ssp1_65_68_grp", "ssp1_94_97_grp" | ||
2734 | }; | ||
2735 | static struct spear_function ssp1_function = { | ||
2736 | .name = "ssp1", | ||
2737 | .groups = ssp1_grps, | ||
2738 | .ngroups = ARRAY_SIZE(ssp1_grps), | ||
2739 | }; | ||
2740 | |||
2741 | /* Pad multiplexing for SSP2 device */ | ||
2742 | static const unsigned ssp2_pins[][2] = { { 13, 16 }, { 32, 35 }, { 44, 47 }, | ||
2743 | { 61, 64 }, { 90, 93 } }; | ||
2744 | static struct spear_muxreg ssp2_muxreg[] = { | ||
2745 | { | ||
2746 | .reg = PMX_CONFIG_REG, | ||
2747 | .mask = PMX_MII_MASK, | ||
2748 | .val = 0, | ||
2749 | }, | ||
2750 | }; | ||
2751 | |||
2752 | static struct spear_muxreg ssp2_ext_13_16_muxreg[] = { | ||
2753 | { | ||
2754 | .reg = IP_SEL_PAD_10_19_REG, | ||
2755 | .mask = PMX_PL_13_14_MASK | PMX_PL_15_16_MASK, | ||
2756 | .val = PMX_SSP2_PL_13_14_15_16_VAL, | ||
2757 | }, { | ||
2758 | .reg = IP_SEL_MIX_PAD_REG, | ||
2759 | .mask = PMX_SSP2_PORT_SEL_MASK, | ||
2760 | .val = PMX_SSP2_PORT_13_TO_16_VAL, | ||
2761 | }, | ||
2762 | }; | ||
2763 | |||
2764 | static struct spear_muxreg ssp2_ext_32_35_muxreg[] = { | ||
2765 | { | ||
2766 | .reg = PMX_CONFIG_REG, | ||
2767 | .mask = PMX_SSP_CS_MASK | PMX_GPIO_PIN4_MASK | | ||
2768 | PMX_GPIO_PIN5_MASK, | ||
2769 | .val = 0, | ||
2770 | }, { | ||
2771 | .reg = IP_SEL_PAD_30_39_REG, | ||
2772 | .mask = PMX_PL_32_33_MASK | PMX_PL_34_MASK | PMX_PL_35_MASK, | ||
2773 | .val = PMX_SSP2_PL_32_33_VAL | PMX_SSP2_PL_34_VAL | | ||
2774 | PMX_SSP2_PL_35_VAL, | ||
2775 | }, { | ||
2776 | .reg = IP_SEL_MIX_PAD_REG, | ||
2777 | .mask = PMX_SSP2_PORT_SEL_MASK, | ||
2778 | .val = PMX_SSP2_PORT_32_TO_35_VAL, | ||
2779 | }, | ||
2780 | }; | ||
2781 | |||
2782 | static struct spear_muxreg ssp2_ext_44_47_muxreg[] = { | ||
2783 | { | ||
2784 | .reg = PMX_CONFIG_REG, | ||
2785 | .mask = PMX_TIMER_0_1_MASK | PMX_TIMER_2_3_MASK, | ||
2786 | .val = 0, | ||
2787 | }, { | ||
2788 | .reg = IP_SEL_PAD_40_49_REG, | ||
2789 | .mask = PMX_PL_44_45_MASK | PMX_PL_46_47_MASK, | ||
2790 | .val = PMX_SSP2_PL_44_45_VAL | PMX_SSP2_PL_46_47_VAL, | ||
2791 | }, { | ||
2792 | .reg = IP_SEL_MIX_PAD_REG, | ||
2793 | .mask = PMX_SSP2_PORT_SEL_MASK, | ||
2794 | .val = PMX_SSP2_PORT_44_TO_47_VAL, | ||
2795 | }, | ||
2796 | }; | ||
2797 | |||
2798 | static struct spear_muxreg ssp2_ext_61_64_muxreg[] = { | ||
2799 | { | ||
2800 | .reg = IP_SEL_PAD_60_69_REG, | ||
2801 | .mask = PMX_PL_61_TO_64_MASK, | ||
2802 | .val = PMX_SSP2_PL_61_TO_64_VAL, | ||
2803 | }, { | ||
2804 | .reg = IP_SEL_MIX_PAD_REG, | ||
2805 | .mask = PMX_SSP2_PORT_SEL_MASK, | ||
2806 | .val = PMX_SSP2_PORT_61_TO_64_VAL, | ||
2807 | }, | ||
2808 | }; | ||
2809 | |||
2810 | static struct spear_muxreg ssp2_ext_90_93_muxreg[] = { | ||
2811 | { | ||
2812 | .reg = IP_SEL_PAD_90_99_REG, | ||
2813 | .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK, | ||
2814 | .val = PMX_SSP2_PL_90_91_VAL | PMX_SSP2_PL_92_93_VAL, | ||
2815 | }, { | ||
2816 | .reg = IP_SEL_MIX_PAD_REG, | ||
2817 | .mask = PMX_SSP2_PORT_SEL_MASK, | ||
2818 | .val = PMX_SSP2_PORT_90_TO_93_VAL, | ||
2819 | }, | ||
2820 | }; | ||
2821 | |||
2822 | static struct spear_modemux ssp2_13_16_modemux[] = { | ||
2823 | { | ||
2824 | .modes = AUTO_NET_SMII_MODE | EXTENDED_MODE, | ||
2825 | .muxregs = ssp2_muxreg, | ||
2826 | .nmuxregs = ARRAY_SIZE(ssp2_muxreg), | ||
2827 | }, { | ||
2828 | .modes = EXTENDED_MODE, | ||
2829 | .muxregs = ssp2_ext_13_16_muxreg, | ||
2830 | .nmuxregs = ARRAY_SIZE(ssp2_ext_13_16_muxreg), | ||
2831 | }, | ||
2832 | }; | ||
2833 | |||
2834 | static struct spear_modemux ssp2_32_35_modemux[] = { | ||
2835 | { | ||
2836 | .modes = EXTENDED_MODE, | ||
2837 | .muxregs = ssp2_ext_32_35_muxreg, | ||
2838 | .nmuxregs = ARRAY_SIZE(ssp2_ext_32_35_muxreg), | ||
2839 | }, | ||
2840 | }; | ||
2841 | |||
2842 | static struct spear_modemux ssp2_44_47_modemux[] = { | ||
2843 | { | ||
2844 | .modes = EXTENDED_MODE, | ||
2845 | .muxregs = ssp2_ext_44_47_muxreg, | ||
2846 | .nmuxregs = ARRAY_SIZE(ssp2_ext_44_47_muxreg), | ||
2847 | }, | ||
2848 | }; | ||
2849 | |||
2850 | static struct spear_modemux ssp2_61_64_modemux[] = { | ||
2851 | { | ||
2852 | .modes = EXTENDED_MODE, | ||
2853 | .muxregs = ssp2_ext_61_64_muxreg, | ||
2854 | .nmuxregs = ARRAY_SIZE(ssp2_ext_61_64_muxreg), | ||
2855 | }, | ||
2856 | }; | ||
2857 | |||
2858 | static struct spear_modemux ssp2_90_93_modemux[] = { | ||
2859 | { | ||
2860 | .modes = EXTENDED_MODE, | ||
2861 | .muxregs = ssp2_ext_90_93_muxreg, | ||
2862 | .nmuxregs = ARRAY_SIZE(ssp2_ext_90_93_muxreg), | ||
2863 | }, | ||
2864 | }; | ||
2865 | |||
2866 | static struct spear_pingroup ssp2_pingroup[] = { | ||
2867 | { | ||
2868 | .name = "ssp2_13_16_grp", | ||
2869 | .pins = ssp2_pins[0], | ||
2870 | .npins = ARRAY_SIZE(ssp2_pins[0]), | ||
2871 | .modemuxs = ssp2_13_16_modemux, | ||
2872 | .nmodemuxs = ARRAY_SIZE(ssp2_13_16_modemux), | ||
2873 | }, { | ||
2874 | .name = "ssp2_32_35_grp", | ||
2875 | .pins = ssp2_pins[1], | ||
2876 | .npins = ARRAY_SIZE(ssp2_pins[1]), | ||
2877 | .modemuxs = ssp2_32_35_modemux, | ||
2878 | .nmodemuxs = ARRAY_SIZE(ssp2_32_35_modemux), | ||
2879 | }, { | ||
2880 | .name = "ssp2_44_47_grp", | ||
2881 | .pins = ssp2_pins[2], | ||
2882 | .npins = ARRAY_SIZE(ssp2_pins[2]), | ||
2883 | .modemuxs = ssp2_44_47_modemux, | ||
2884 | .nmodemuxs = ARRAY_SIZE(ssp2_44_47_modemux), | ||
2885 | }, { | ||
2886 | .name = "ssp2_61_64_grp", | ||
2887 | .pins = ssp2_pins[3], | ||
2888 | .npins = ARRAY_SIZE(ssp2_pins[3]), | ||
2889 | .modemuxs = ssp2_61_64_modemux, | ||
2890 | .nmodemuxs = ARRAY_SIZE(ssp2_61_64_modemux), | ||
2891 | }, { | ||
2892 | .name = "ssp2_90_93_grp", | ||
2893 | .pins = ssp2_pins[4], | ||
2894 | .npins = ARRAY_SIZE(ssp2_pins[4]), | ||
2895 | .modemuxs = ssp2_90_93_modemux, | ||
2896 | .nmodemuxs = ARRAY_SIZE(ssp2_90_93_modemux), | ||
2897 | }, | ||
2898 | }; | ||
2899 | |||
2900 | static const char *const ssp2_grps[] = { "ssp2_13_16_grp", "ssp2_32_35_grp", | ||
2901 | "ssp2_44_47_grp", "ssp2_61_64_grp", "ssp2_90_93_grp" }; | ||
2902 | static struct spear_function ssp2_function = { | ||
2903 | .name = "ssp2", | ||
2904 | .groups = ssp2_grps, | ||
2905 | .ngroups = ARRAY_SIZE(ssp2_grps), | ||
2906 | }; | ||
2907 | |||
2908 | /* Pad multiplexing for cadence mii2 as mii device */ | ||
2909 | static const unsigned mii2_pins[] = { 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, | ||
2910 | 90, 91, 92, 93, 94, 95, 96, 97 }; | ||
2911 | static struct spear_muxreg mii2_muxreg[] = { | ||
2912 | { | ||
2913 | .reg = IP_SEL_PAD_80_89_REG, | ||
2914 | .mask = PMX_PL_80_TO_85_MASK | PMX_PL_86_87_MASK | | ||
2915 | PMX_PL_88_89_MASK, | ||
2916 | .val = PMX_MII2_PL_80_TO_85_VAL | PMX_MII2_PL_86_87_VAL | | ||
2917 | PMX_MII2_PL_88_89_VAL, | ||
2918 | }, { | ||
2919 | .reg = IP_SEL_PAD_90_99_REG, | ||
2920 | .mask = PMX_PL_90_91_MASK | PMX_PL_92_93_MASK | | ||
2921 | PMX_PL_94_95_MASK | PMX_PL_96_97_MASK, | ||
2922 | .val = PMX_MII2_PL_90_91_VAL | PMX_MII2_PL_92_93_VAL | | ||
2923 | PMX_MII2_PL_94_95_VAL | PMX_MII2_PL_96_97_VAL, | ||
2924 | }, { | ||
2925 | .reg = EXT_CTRL_REG, | ||
2926 | .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | | ||
2927 | (MAC_MODE_MASK << MAC1_MODE_SHIFT) | | ||
2928 | MII_MDIO_MASK, | ||
2929 | .val = (MAC_MODE_MII << MAC2_MODE_SHIFT) | | ||
2930 | (MAC_MODE_MII << MAC1_MODE_SHIFT) | | ||
2931 | MII_MDIO_81_VAL, | ||
2932 | }, | ||
2933 | }; | ||
2934 | |||
2935 | static struct spear_modemux mii2_modemux[] = { | ||
2936 | { | ||
2937 | .modes = EXTENDED_MODE, | ||
2938 | .muxregs = mii2_muxreg, | ||
2939 | .nmuxregs = ARRAY_SIZE(mii2_muxreg), | ||
2940 | }, | ||
2941 | }; | ||
2942 | |||
2943 | static struct spear_pingroup mii2_pingroup = { | ||
2944 | .name = "mii2_grp", | ||
2945 | .pins = mii2_pins, | ||
2946 | .npins = ARRAY_SIZE(mii2_pins), | ||
2947 | .modemuxs = mii2_modemux, | ||
2948 | .nmodemuxs = ARRAY_SIZE(mii2_modemux), | ||
2949 | }; | ||
2950 | |||
2951 | static const char *const mii2_grps[] = { "mii2_grp" }; | ||
2952 | static struct spear_function mii2_function = { | ||
2953 | .name = "mii2", | ||
2954 | .groups = mii2_grps, | ||
2955 | .ngroups = ARRAY_SIZE(mii2_grps), | ||
2956 | }; | ||
2957 | |||
2958 | /* Pad multiplexing for cadence mii 1_2 as smii or rmii device */ | ||
2959 | static const unsigned smii0_1_pins[] = { 10, 11, 13, 14, 15, 16, 17, 18, 19, 20, | ||
2960 | 21, 22, 23, 24, 25, 26, 27 }; | ||
2961 | static const unsigned rmii0_1_pins[] = { 10, 11, 21, 22, 23, 24, 25, 26, 27 }; | ||
2962 | static struct spear_muxreg mii0_1_muxreg[] = { | ||
2963 | { | ||
2964 | .reg = PMX_CONFIG_REG, | ||
2965 | .mask = PMX_MII_MASK, | ||
2966 | .val = 0, | ||
2967 | }, | ||
2968 | }; | ||
2969 | |||
2970 | static struct spear_muxreg smii0_1_ext_muxreg[] = { | ||
2971 | { | ||
2972 | .reg = IP_SEL_PAD_10_19_REG, | ||
2973 | .mask = PMX_PL_10_11_MASK, | ||
2974 | .val = PMX_SMII_PL_10_11_VAL, | ||
2975 | }, { | ||
2976 | .reg = IP_SEL_PAD_20_29_REG, | ||
2977 | .mask = PMX_PL_21_TO_27_MASK, | ||
2978 | .val = PMX_SMII_PL_21_TO_27_VAL, | ||
2979 | }, { | ||
2980 | .reg = EXT_CTRL_REG, | ||
2981 | .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | | ||
2982 | (MAC_MODE_MASK << MAC1_MODE_SHIFT) | | ||
2983 | MII_MDIO_MASK, | ||
2984 | .val = (MAC_MODE_SMII << MAC2_MODE_SHIFT) | ||
2985 | | (MAC_MODE_SMII << MAC1_MODE_SHIFT) | ||
2986 | | MII_MDIO_10_11_VAL, | ||
2987 | }, | ||
2988 | }; | ||
2989 | |||
2990 | static struct spear_muxreg rmii0_1_ext_muxreg[] = { | ||
2991 | { | ||
2992 | .reg = IP_SEL_PAD_10_19_REG, | ||
2993 | .mask = PMX_PL_10_11_MASK | PMX_PL_13_14_MASK | | ||
2994 | PMX_PL_15_16_MASK | PMX_PL_17_18_MASK | PMX_PL_19_MASK, | ||
2995 | .val = PMX_RMII_PL_10_11_VAL | PMX_RMII_PL_13_14_VAL | | ||
2996 | PMX_RMII_PL_15_16_VAL | PMX_RMII_PL_17_18_VAL | | ||
2997 | PMX_RMII_PL_19_VAL, | ||
2998 | }, { | ||
2999 | .reg = IP_SEL_PAD_20_29_REG, | ||
3000 | .mask = PMX_PL_20_MASK | PMX_PL_21_TO_27_MASK, | ||
3001 | .val = PMX_RMII_PL_20_VAL | PMX_RMII_PL_21_TO_27_VAL, | ||
3002 | }, { | ||
3003 | .reg = EXT_CTRL_REG, | ||
3004 | .mask = (MAC_MODE_MASK << MAC2_MODE_SHIFT) | | ||
3005 | (MAC_MODE_MASK << MAC1_MODE_SHIFT) | | ||
3006 | MII_MDIO_MASK, | ||
3007 | .val = (MAC_MODE_RMII << MAC2_MODE_SHIFT) | ||
3008 | | (MAC_MODE_RMII << MAC1_MODE_SHIFT) | ||
3009 | | MII_MDIO_10_11_VAL, | ||
3010 | }, | ||
3011 | }; | ||
3012 | |||
3013 | static struct spear_modemux mii0_1_modemux[][2] = { | ||
3014 | { | ||
3015 | /* configure as smii */ | ||
3016 | { | ||
3017 | .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | | ||
3018 | SMALL_PRINTERS_MODE | EXTENDED_MODE, | ||
3019 | .muxregs = mii0_1_muxreg, | ||
3020 | .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), | ||
3021 | }, { | ||
3022 | .modes = EXTENDED_MODE, | ||
3023 | .muxregs = smii0_1_ext_muxreg, | ||
3024 | .nmuxregs = ARRAY_SIZE(smii0_1_ext_muxreg), | ||
3025 | }, | ||
3026 | }, { | ||
3027 | /* configure as rmii */ | ||
3028 | { | ||
3029 | .modes = AUTO_NET_SMII_MODE | AUTO_EXP_MODE | | ||
3030 | SMALL_PRINTERS_MODE | EXTENDED_MODE, | ||
3031 | .muxregs = mii0_1_muxreg, | ||
3032 | .nmuxregs = ARRAY_SIZE(mii0_1_muxreg), | ||
3033 | }, { | ||
3034 | .modes = EXTENDED_MODE, | ||
3035 | .muxregs = rmii0_1_ext_muxreg, | ||
3036 | .nmuxregs = ARRAY_SIZE(rmii0_1_ext_muxreg), | ||
3037 | }, | ||
3038 | }, | ||
3039 | }; | ||
3040 | |||
3041 | static struct spear_pingroup mii0_1_pingroup[] = { | ||
3042 | { | ||
3043 | .name = "smii0_1_grp", | ||
3044 | .pins = smii0_1_pins, | ||
3045 | .npins = ARRAY_SIZE(smii0_1_pins), | ||
3046 | .modemuxs = mii0_1_modemux[0], | ||
3047 | .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[0]), | ||
3048 | }, { | ||
3049 | .name = "rmii0_1_grp", | ||
3050 | .pins = rmii0_1_pins, | ||
3051 | .npins = ARRAY_SIZE(rmii0_1_pins), | ||
3052 | .modemuxs = mii0_1_modemux[1], | ||
3053 | .nmodemuxs = ARRAY_SIZE(mii0_1_modemux[1]), | ||
3054 | }, | ||
3055 | }; | ||
3056 | |||
3057 | static const char *const mii0_1_grps[] = { "smii0_1_grp", "rmii0_1_grp" }; | ||
3058 | static struct spear_function mii0_1_function = { | ||
3059 | .name = "mii0_1", | ||
3060 | .groups = mii0_1_grps, | ||
3061 | .ngroups = ARRAY_SIZE(mii0_1_grps), | ||
3062 | }; | ||
3063 | |||
3064 | /* Pad multiplexing for i2c1 device */ | ||
3065 | static const unsigned i2c1_pins[][2] = { { 8, 9 }, { 98, 99 } }; | ||
3066 | static struct spear_muxreg i2c1_ext_8_9_muxreg[] = { | ||
3067 | { | ||
3068 | .reg = PMX_CONFIG_REG, | ||
3069 | .mask = PMX_SSP_CS_MASK, | ||
3070 | .val = 0, | ||
3071 | }, { | ||
3072 | .reg = IP_SEL_PAD_0_9_REG, | ||
3073 | .mask = PMX_PL_8_9_MASK, | ||
3074 | .val = PMX_I2C1_PL_8_9_VAL, | ||
3075 | }, { | ||
3076 | .reg = IP_SEL_MIX_PAD_REG, | ||
3077 | .mask = PMX_I2C1_PORT_SEL_MASK, | ||
3078 | .val = PMX_I2C1_PORT_8_9_VAL, | ||
3079 | }, | ||
3080 | }; | ||
3081 | |||
3082 | static struct spear_muxreg i2c1_ext_98_99_muxreg[] = { | ||
3083 | { | ||
3084 | .reg = IP_SEL_PAD_90_99_REG, | ||
3085 | .mask = PMX_PL_98_MASK | PMX_PL_99_MASK, | ||
3086 | .val = PMX_I2C1_PL_98_VAL | PMX_I2C1_PL_99_VAL, | ||
3087 | }, { | ||
3088 | .reg = IP_SEL_MIX_PAD_REG, | ||
3089 | .mask = PMX_I2C1_PORT_SEL_MASK, | ||
3090 | .val = PMX_I2C1_PORT_98_99_VAL, | ||
3091 | }, | ||
3092 | }; | ||
3093 | |||
3094 | static struct spear_modemux i2c1_modemux[][1] = { | ||
3095 | { | ||
3096 | /* Select signals on pins 8-9 */ | ||
3097 | { | ||
3098 | .modes = EXTENDED_MODE, | ||
3099 | .muxregs = i2c1_ext_8_9_muxreg, | ||
3100 | .nmuxregs = ARRAY_SIZE(i2c1_ext_8_9_muxreg), | ||
3101 | }, | ||
3102 | }, { | ||
3103 | /* Select signals on pins 98-99 */ | ||
3104 | { | ||
3105 | .modes = EXTENDED_MODE, | ||
3106 | .muxregs = i2c1_ext_98_99_muxreg, | ||
3107 | .nmuxregs = ARRAY_SIZE(i2c1_ext_98_99_muxreg), | ||
3108 | }, | ||
3109 | }, | ||
3110 | }; | ||
3111 | |||
3112 | static struct spear_pingroup i2c1_pingroup[] = { | ||
3113 | { | ||
3114 | .name = "i2c1_8_9_grp", | ||
3115 | .pins = i2c1_pins[0], | ||
3116 | .npins = ARRAY_SIZE(i2c1_pins[0]), | ||
3117 | .modemuxs = i2c1_modemux[0], | ||
3118 | .nmodemuxs = ARRAY_SIZE(i2c1_modemux[0]), | ||
3119 | }, { | ||
3120 | .name = "i2c1_98_99_grp", | ||
3121 | .pins = i2c1_pins[1], | ||
3122 | .npins = ARRAY_SIZE(i2c1_pins[1]), | ||
3123 | .modemuxs = i2c1_modemux[1], | ||
3124 | .nmodemuxs = ARRAY_SIZE(i2c1_modemux[1]), | ||
3125 | }, | ||
3126 | }; | ||
3127 | |||
3128 | static const char *const i2c1_grps[] = { "i2c1_8_9_grp", "i2c1_98_99_grp" }; | ||
3129 | static struct spear_function i2c1_function = { | ||
3130 | .name = "i2c1", | ||
3131 | .groups = i2c1_grps, | ||
3132 | .ngroups = ARRAY_SIZE(i2c1_grps), | ||
3133 | }; | ||
3134 | |||
3135 | /* Pad multiplexing for i2c2 device */ | ||
3136 | static const unsigned i2c2_pins[][2] = { { 0, 1 }, { 2, 3 }, { 19, 20 }, | ||
3137 | { 75, 76 }, { 96, 97 } }; | ||
3138 | static struct spear_muxreg i2c2_ext_0_1_muxreg[] = { | ||
3139 | { | ||
3140 | .reg = PMX_CONFIG_REG, | ||
3141 | .mask = PMX_FIRDA_MASK, | ||
3142 | .val = 0, | ||
3143 | }, { | ||
3144 | .reg = IP_SEL_PAD_0_9_REG, | ||
3145 | .mask = PMX_PL_0_1_MASK, | ||
3146 | .val = PMX_I2C2_PL_0_1_VAL, | ||
3147 | }, { | ||
3148 | .reg = IP_SEL_MIX_PAD_REG, | ||
3149 | .mask = PMX_I2C2_PORT_SEL_MASK, | ||
3150 | .val = PMX_I2C2_PORT_0_1_VAL, | ||
3151 | }, | ||
3152 | }; | ||
3153 | |||
3154 | static struct spear_muxreg i2c2_ext_2_3_muxreg[] = { | ||
3155 | { | ||
3156 | .reg = PMX_CONFIG_REG, | ||
3157 | .mask = PMX_UART0_MASK, | ||
3158 | .val = 0, | ||
3159 | }, { | ||
3160 | .reg = IP_SEL_PAD_0_9_REG, | ||
3161 | .mask = PMX_PL_2_3_MASK, | ||
3162 | .val = PMX_I2C2_PL_2_3_VAL, | ||
3163 | }, { | ||
3164 | .reg = IP_SEL_MIX_PAD_REG, | ||
3165 | .mask = PMX_I2C2_PORT_SEL_MASK, | ||
3166 | .val = PMX_I2C2_PORT_2_3_VAL, | ||
3167 | }, | ||
3168 | }; | ||
3169 | |||
3170 | static struct spear_muxreg i2c2_ext_19_20_muxreg[] = { | ||
3171 | { | ||
3172 | .reg = PMX_CONFIG_REG, | ||
3173 | .mask = PMX_MII_MASK, | ||
3174 | .val = 0, | ||
3175 | }, { | ||
3176 | .reg = IP_SEL_PAD_10_19_REG, | ||
3177 | .mask = PMX_PL_19_MASK, | ||
3178 | .val = PMX_I2C2_PL_19_VAL, | ||
3179 | }, { | ||
3180 | .reg = IP_SEL_PAD_20_29_REG, | ||
3181 | .mask = PMX_PL_20_MASK, | ||
3182 | .val = PMX_I2C2_PL_20_VAL, | ||
3183 | }, { | ||
3184 | .reg = IP_SEL_MIX_PAD_REG, | ||
3185 | .mask = PMX_I2C2_PORT_SEL_MASK, | ||
3186 | .val = PMX_I2C2_PORT_19_20_VAL, | ||
3187 | }, | ||
3188 | }; | ||
3189 | |||
3190 | static struct spear_muxreg i2c2_ext_75_76_muxreg[] = { | ||
3191 | { | ||
3192 | .reg = IP_SEL_PAD_70_79_REG, | ||
3193 | .mask = PMX_PL_75_76_MASK, | ||
3194 | .val = PMX_I2C2_PL_75_76_VAL, | ||
3195 | }, { | ||
3196 | .reg = IP_SEL_MIX_PAD_REG, | ||
3197 | .mask = PMX_I2C2_PORT_SEL_MASK, | ||
3198 | .val = PMX_I2C2_PORT_75_76_VAL, | ||
3199 | }, | ||
3200 | }; | ||
3201 | |||
3202 | static struct spear_muxreg i2c2_ext_96_97_muxreg[] = { | ||
3203 | { | ||
3204 | .reg = IP_SEL_PAD_90_99_REG, | ||
3205 | .mask = PMX_PL_96_97_MASK, | ||
3206 | .val = PMX_I2C2_PL_96_97_VAL, | ||
3207 | }, { | ||
3208 | .reg = IP_SEL_MIX_PAD_REG, | ||
3209 | .mask = PMX_I2C2_PORT_SEL_MASK, | ||
3210 | .val = PMX_I2C2_PORT_96_97_VAL, | ||
3211 | }, | ||
3212 | }; | ||
3213 | |||
3214 | static struct spear_modemux i2c2_modemux[][1] = { | ||
3215 | { | ||
3216 | /* Select signals on pins 0_1 */ | ||
3217 | { | ||
3218 | .modes = EXTENDED_MODE, | ||
3219 | .muxregs = i2c2_ext_0_1_muxreg, | ||
3220 | .nmuxregs = ARRAY_SIZE(i2c2_ext_0_1_muxreg), | ||
3221 | }, | ||
3222 | }, { | ||
3223 | /* Select signals on pins 2_3 */ | ||
3224 | { | ||
3225 | .modes = EXTENDED_MODE, | ||
3226 | .muxregs = i2c2_ext_2_3_muxreg, | ||
3227 | .nmuxregs = ARRAY_SIZE(i2c2_ext_2_3_muxreg), | ||
3228 | }, | ||
3229 | }, { | ||
3230 | /* Select signals on pins 19_20 */ | ||
3231 | { | ||
3232 | .modes = EXTENDED_MODE, | ||
3233 | .muxregs = i2c2_ext_19_20_muxreg, | ||
3234 | .nmuxregs = ARRAY_SIZE(i2c2_ext_19_20_muxreg), | ||
3235 | }, | ||
3236 | }, { | ||
3237 | /* Select signals on pins 75_76 */ | ||
3238 | { | ||
3239 | .modes = EXTENDED_MODE, | ||
3240 | .muxregs = i2c2_ext_75_76_muxreg, | ||
3241 | .nmuxregs = ARRAY_SIZE(i2c2_ext_75_76_muxreg), | ||
3242 | }, | ||
3243 | }, { | ||
3244 | /* Select signals on pins 96_97 */ | ||
3245 | { | ||
3246 | .modes = EXTENDED_MODE, | ||
3247 | .muxregs = i2c2_ext_96_97_muxreg, | ||
3248 | .nmuxregs = ARRAY_SIZE(i2c2_ext_96_97_muxreg), | ||
3249 | }, | ||
3250 | }, | ||
3251 | }; | ||
3252 | |||
3253 | static struct spear_pingroup i2c2_pingroup[] = { | ||
3254 | { | ||
3255 | .name = "i2c2_0_1_grp", | ||
3256 | .pins = i2c2_pins[0], | ||
3257 | .npins = ARRAY_SIZE(i2c2_pins[0]), | ||
3258 | .modemuxs = i2c2_modemux[0], | ||
3259 | .nmodemuxs = ARRAY_SIZE(i2c2_modemux[0]), | ||
3260 | }, { | ||
3261 | .name = "i2c2_2_3_grp", | ||
3262 | .pins = i2c2_pins[1], | ||
3263 | .npins = ARRAY_SIZE(i2c2_pins[1]), | ||
3264 | .modemuxs = i2c2_modemux[1], | ||
3265 | .nmodemuxs = ARRAY_SIZE(i2c2_modemux[1]), | ||
3266 | }, { | ||
3267 | .name = "i2c2_19_20_grp", | ||
3268 | .pins = i2c2_pins[2], | ||
3269 | .npins = ARRAY_SIZE(i2c2_pins[2]), | ||
3270 | .modemuxs = i2c2_modemux[2], | ||
3271 | .nmodemuxs = ARRAY_SIZE(i2c2_modemux[2]), | ||
3272 | }, { | ||
3273 | .name = "i2c2_75_76_grp", | ||
3274 | .pins = i2c2_pins[3], | ||
3275 | .npins = ARRAY_SIZE(i2c2_pins[3]), | ||
3276 | .modemuxs = i2c2_modemux[3], | ||
3277 | .nmodemuxs = ARRAY_SIZE(i2c2_modemux[3]), | ||
3278 | }, { | ||
3279 | .name = "i2c2_96_97_grp", | ||
3280 | .pins = i2c2_pins[4], | ||
3281 | .npins = ARRAY_SIZE(i2c2_pins[4]), | ||
3282 | .modemuxs = i2c2_modemux[4], | ||
3283 | .nmodemuxs = ARRAY_SIZE(i2c2_modemux[4]), | ||
3284 | }, | ||
3285 | }; | ||
3286 | |||
3287 | static const char *const i2c2_grps[] = { "i2c2_0_1_grp", "i2c2_2_3_grp", | ||
3288 | "i2c2_19_20_grp", "i2c2_75_76_grp", "i2c2_96_97_grp" }; | ||
3289 | static struct spear_function i2c2_function = { | ||
3290 | .name = "i2c2", | ||
3291 | .groups = i2c2_grps, | ||
3292 | .ngroups = ARRAY_SIZE(i2c2_grps), | ||
3293 | }; | ||
3294 | |||
3295 | /* pingroups */ | ||
3296 | static struct spear_pingroup *spear320_pingroups[] = { | ||
3297 | SPEAR3XX_COMMON_PINGROUPS, | ||
3298 | &clcd_pingroup, | ||
3299 | &emi_pingroup, | ||
3300 | &fsmc_8bit_pingroup, | ||
3301 | &fsmc_16bit_pingroup, | ||
3302 | &spp_pingroup, | ||
3303 | &sdhci_led_pingroup, | ||
3304 | &sdhci_pingroup[0], | ||
3305 | &sdhci_pingroup[1], | ||
3306 | &i2s_pingroup, | ||
3307 | &uart1_pingroup, | ||
3308 | &uart1_modem_pingroup[0], | ||
3309 | &uart1_modem_pingroup[1], | ||
3310 | &uart1_modem_pingroup[2], | ||
3311 | &uart1_modem_pingroup[3], | ||
3312 | &uart2_pingroup, | ||
3313 | &uart3_pingroup[0], | ||
3314 | &uart3_pingroup[1], | ||
3315 | &uart3_pingroup[2], | ||
3316 | &uart3_pingroup[3], | ||
3317 | &uart3_pingroup[4], | ||
3318 | &uart3_pingroup[5], | ||
3319 | &uart3_pingroup[6], | ||
3320 | &uart4_pingroup[0], | ||
3321 | &uart4_pingroup[1], | ||
3322 | &uart4_pingroup[2], | ||
3323 | &uart4_pingroup[3], | ||
3324 | &uart4_pingroup[4], | ||
3325 | &uart4_pingroup[5], | ||
3326 | &uart5_pingroup[0], | ||
3327 | &uart5_pingroup[1], | ||
3328 | &uart5_pingroup[2], | ||
3329 | &uart5_pingroup[3], | ||
3330 | &uart6_pingroup[0], | ||
3331 | &uart6_pingroup[1], | ||
3332 | &rs485_pingroup, | ||
3333 | &touchscreen_pingroup, | ||
3334 | &can0_pingroup, | ||
3335 | &can1_pingroup, | ||
3336 | &pwm0_1_pingroup[0], | ||
3337 | &pwm0_1_pingroup[1], | ||
3338 | &pwm0_1_pingroup[2], | ||
3339 | &pwm0_1_pingroup[3], | ||
3340 | &pwm0_1_pingroup[4], | ||
3341 | &pwm0_1_pingroup[5], | ||
3342 | &pwm0_1_pingroup[6], | ||
3343 | &pwm2_pingroup[0], | ||
3344 | &pwm2_pingroup[1], | ||
3345 | &pwm2_pingroup[2], | ||
3346 | &pwm2_pingroup[3], | ||
3347 | &pwm2_pingroup[4], | ||
3348 | &pwm2_pingroup[5], | ||
3349 | &pwm2_pingroup[6], | ||
3350 | &pwm3_pingroup[0], | ||
3351 | &pwm3_pingroup[1], | ||
3352 | &pwm3_pingroup[2], | ||
3353 | &pwm3_pingroup[3], | ||
3354 | &pwm3_pingroup[4], | ||
3355 | &pwm3_pingroup[5], | ||
3356 | &ssp1_pingroup[0], | ||
3357 | &ssp1_pingroup[1], | ||
3358 | &ssp1_pingroup[2], | ||
3359 | &ssp1_pingroup[3], | ||
3360 | &ssp1_pingroup[4], | ||
3361 | &ssp2_pingroup[0], | ||
3362 | &ssp2_pingroup[1], | ||
3363 | &ssp2_pingroup[2], | ||
3364 | &ssp2_pingroup[3], | ||
3365 | &ssp2_pingroup[4], | ||
3366 | &mii2_pingroup, | ||
3367 | &mii0_1_pingroup[0], | ||
3368 | &mii0_1_pingroup[1], | ||
3369 | &i2c1_pingroup[0], | ||
3370 | &i2c1_pingroup[1], | ||
3371 | &i2c2_pingroup[0], | ||
3372 | &i2c2_pingroup[1], | ||
3373 | &i2c2_pingroup[2], | ||
3374 | &i2c2_pingroup[3], | ||
3375 | &i2c2_pingroup[4], | ||
3376 | }; | ||
3377 | |||
3378 | /* functions */ | ||
3379 | static struct spear_function *spear320_functions[] = { | ||
3380 | SPEAR3XX_COMMON_FUNCTIONS, | ||
3381 | &clcd_function, | ||
3382 | &emi_function, | ||
3383 | &fsmc_function, | ||
3384 | &spp_function, | ||
3385 | &sdhci_function, | ||
3386 | &i2s_function, | ||
3387 | &uart1_function, | ||
3388 | &uart1_modem_function, | ||
3389 | &uart2_function, | ||
3390 | &uart3_function, | ||
3391 | &uart4_function, | ||
3392 | &uart5_function, | ||
3393 | &uart6_function, | ||
3394 | &rs485_function, | ||
3395 | &touchscreen_function, | ||
3396 | &can0_function, | ||
3397 | &can1_function, | ||
3398 | &pwm0_1_function, | ||
3399 | &pwm2_function, | ||
3400 | &pwm3_function, | ||
3401 | &ssp1_function, | ||
3402 | &ssp2_function, | ||
3403 | &mii2_function, | ||
3404 | &mii0_1_function, | ||
3405 | &i2c1_function, | ||
3406 | &i2c2_function, | ||
3407 | }; | ||
3408 | |||
3409 | static struct of_device_id spear320_pinctrl_of_match[] __devinitdata = { | ||
3410 | { | ||
3411 | .compatible = "st,spear320-pinmux", | ||
3412 | }, | ||
3413 | {}, | ||
3414 | }; | ||
3415 | |||
3416 | static int __devinit spear320_pinctrl_probe(struct platform_device *pdev) | ||
3417 | { | ||
3418 | int ret; | ||
3419 | |||
3420 | spear3xx_machdata.groups = spear320_pingroups; | ||
3421 | spear3xx_machdata.ngroups = ARRAY_SIZE(spear320_pingroups); | ||
3422 | spear3xx_machdata.functions = spear320_functions; | ||
3423 | spear3xx_machdata.nfunctions = ARRAY_SIZE(spear320_functions); | ||
3424 | |||
3425 | spear3xx_machdata.modes_supported = true; | ||
3426 | spear3xx_machdata.pmx_modes = spear320_pmx_modes; | ||
3427 | spear3xx_machdata.npmx_modes = ARRAY_SIZE(spear320_pmx_modes); | ||
3428 | |||
3429 | pmx_init_addr(&spear3xx_machdata, PMX_CONFIG_REG); | ||
3430 | |||
3431 | ret = spear_pinctrl_probe(pdev, &spear3xx_machdata); | ||
3432 | if (ret) | ||
3433 | return ret; | ||
3434 | |||
3435 | return 0; | ||
3436 | } | ||
3437 | |||
3438 | static int __devexit spear320_pinctrl_remove(struct platform_device *pdev) | ||
3439 | { | ||
3440 | return spear_pinctrl_remove(pdev); | ||
3441 | } | ||
3442 | |||
3443 | static struct platform_driver spear320_pinctrl_driver = { | ||
3444 | .driver = { | ||
3445 | .name = DRIVER_NAME, | ||
3446 | .owner = THIS_MODULE, | ||
3447 | .of_match_table = spear320_pinctrl_of_match, | ||
3448 | }, | ||
3449 | .probe = spear320_pinctrl_probe, | ||
3450 | .remove = __devexit_p(spear320_pinctrl_remove), | ||
3451 | }; | ||
3452 | |||
3453 | static int __init spear320_pinctrl_init(void) | ||
3454 | { | ||
3455 | return platform_driver_register(&spear320_pinctrl_driver); | ||
3456 | } | ||
3457 | arch_initcall(spear320_pinctrl_init); | ||
3458 | |||
3459 | static void __exit spear320_pinctrl_exit(void) | ||
3460 | { | ||
3461 | platform_driver_unregister(&spear320_pinctrl_driver); | ||
3462 | } | ||
3463 | module_exit(spear320_pinctrl_exit); | ||
3464 | |||
3465 | MODULE_AUTHOR("Viresh Kumar <viresh.kumar@st.com>"); | ||
3466 | MODULE_DESCRIPTION("ST Microelectronics SPEAr320 pinctrl driver"); | ||
3467 | MODULE_LICENSE("GPL v2"); | ||
3468 | MODULE_DEVICE_TABLE(of, spear320_pinctrl_of_match); | ||
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.c b/drivers/pinctrl/spear/pinctrl-spear3xx.c new file mode 100644 index 000000000000..832049a8b1c9 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear3xx.c | |||
@@ -0,0 +1,588 @@ | |||
1 | /* | ||
2 | * Driver for the ST Microelectronics SPEAr3xx pinmux | ||
3 | * | ||
4 | * Copyright (C) 2012 ST Microelectronics | ||
5 | * Viresh Kumar <viresh.kumar@st.com> | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public | ||
8 | * License version 2. This program is licensed "as is" without any | ||
9 | * warranty of any kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | #include <linux/pinctrl/pinctrl.h> | ||
13 | |||
14 | #include "pinctrl-spear3xx.h" | ||
15 | |||
16 | /* pins */ | ||
17 | static const struct pinctrl_pin_desc spear3xx_pins[] = { | ||
18 | PINCTRL_PIN(0, "PLGPIO0"), | ||
19 | PINCTRL_PIN(1, "PLGPIO1"), | ||
20 | PINCTRL_PIN(2, "PLGPIO2"), | ||
21 | PINCTRL_PIN(3, "PLGPIO3"), | ||
22 | PINCTRL_PIN(4, "PLGPIO4"), | ||
23 | PINCTRL_PIN(5, "PLGPIO5"), | ||
24 | PINCTRL_PIN(6, "PLGPIO6"), | ||
25 | PINCTRL_PIN(7, "PLGPIO7"), | ||
26 | PINCTRL_PIN(8, "PLGPIO8"), | ||
27 | PINCTRL_PIN(9, "PLGPIO9"), | ||
28 | PINCTRL_PIN(10, "PLGPIO10"), | ||
29 | PINCTRL_PIN(11, "PLGPIO11"), | ||
30 | PINCTRL_PIN(12, "PLGPIO12"), | ||
31 | PINCTRL_PIN(13, "PLGPIO13"), | ||
32 | PINCTRL_PIN(14, "PLGPIO14"), | ||
33 | PINCTRL_PIN(15, "PLGPIO15"), | ||
34 | PINCTRL_PIN(16, "PLGPIO16"), | ||
35 | PINCTRL_PIN(17, "PLGPIO17"), | ||
36 | PINCTRL_PIN(18, "PLGPIO18"), | ||
37 | PINCTRL_PIN(19, "PLGPIO19"), | ||
38 | PINCTRL_PIN(20, "PLGPIO20"), | ||
39 | PINCTRL_PIN(21, "PLGPIO21"), | ||
40 | PINCTRL_PIN(22, "PLGPIO22"), | ||
41 | PINCTRL_PIN(23, "PLGPIO23"), | ||
42 | PINCTRL_PIN(24, "PLGPIO24"), | ||
43 | PINCTRL_PIN(25, "PLGPIO25"), | ||
44 | PINCTRL_PIN(26, "PLGPIO26"), | ||
45 | PINCTRL_PIN(27, "PLGPIO27"), | ||
46 | PINCTRL_PIN(28, "PLGPIO28"), | ||
47 | PINCTRL_PIN(29, "PLGPIO29"), | ||
48 | PINCTRL_PIN(30, "PLGPIO30"), | ||
49 | PINCTRL_PIN(31, "PLGPIO31"), | ||
50 | PINCTRL_PIN(32, "PLGPIO32"), | ||
51 | PINCTRL_PIN(33, "PLGPIO33"), | ||
52 | PINCTRL_PIN(34, "PLGPIO34"), | ||
53 | PINCTRL_PIN(35, "PLGPIO35"), | ||
54 | PINCTRL_PIN(36, "PLGPIO36"), | ||
55 | PINCTRL_PIN(37, "PLGPIO37"), | ||
56 | PINCTRL_PIN(38, "PLGPIO38"), | ||
57 | PINCTRL_PIN(39, "PLGPIO39"), | ||
58 | PINCTRL_PIN(40, "PLGPIO40"), | ||
59 | PINCTRL_PIN(41, "PLGPIO41"), | ||
60 | PINCTRL_PIN(42, "PLGPIO42"), | ||
61 | PINCTRL_PIN(43, "PLGPIO43"), | ||
62 | PINCTRL_PIN(44, "PLGPIO44"), | ||
63 | PINCTRL_PIN(45, "PLGPIO45"), | ||
64 | PINCTRL_PIN(46, "PLGPIO46"), | ||
65 | PINCTRL_PIN(47, "PLGPIO47"), | ||
66 | PINCTRL_PIN(48, "PLGPIO48"), | ||
67 | PINCTRL_PIN(49, "PLGPIO49"), | ||
68 | PINCTRL_PIN(50, "PLGPIO50"), | ||
69 | PINCTRL_PIN(51, "PLGPIO51"), | ||
70 | PINCTRL_PIN(52, "PLGPIO52"), | ||
71 | PINCTRL_PIN(53, "PLGPIO53"), | ||
72 | PINCTRL_PIN(54, "PLGPIO54"), | ||
73 | PINCTRL_PIN(55, "PLGPIO55"), | ||
74 | PINCTRL_PIN(56, "PLGPIO56"), | ||
75 | PINCTRL_PIN(57, "PLGPIO57"), | ||
76 | PINCTRL_PIN(58, "PLGPIO58"), | ||
77 | PINCTRL_PIN(59, "PLGPIO59"), | ||
78 | PINCTRL_PIN(60, "PLGPIO60"), | ||
79 | PINCTRL_PIN(61, "PLGPIO61"), | ||
80 | PINCTRL_PIN(62, "PLGPIO62"), | ||
81 | PINCTRL_PIN(63, "PLGPIO63"), | ||
82 | PINCTRL_PIN(64, "PLGPIO64"), | ||
83 | PINCTRL_PIN(65, "PLGPIO65"), | ||
84 | PINCTRL_PIN(66, "PLGPIO66"), | ||
85 | PINCTRL_PIN(67, "PLGPIO67"), | ||
86 | PINCTRL_PIN(68, "PLGPIO68"), | ||
87 | PINCTRL_PIN(69, "PLGPIO69"), | ||
88 | PINCTRL_PIN(70, "PLGPIO70"), | ||
89 | PINCTRL_PIN(71, "PLGPIO71"), | ||
90 | PINCTRL_PIN(72, "PLGPIO72"), | ||
91 | PINCTRL_PIN(73, "PLGPIO73"), | ||
92 | PINCTRL_PIN(74, "PLGPIO74"), | ||
93 | PINCTRL_PIN(75, "PLGPIO75"), | ||
94 | PINCTRL_PIN(76, "PLGPIO76"), | ||
95 | PINCTRL_PIN(77, "PLGPIO77"), | ||
96 | PINCTRL_PIN(78, "PLGPIO78"), | ||
97 | PINCTRL_PIN(79, "PLGPIO79"), | ||
98 | PINCTRL_PIN(80, "PLGPIO80"), | ||
99 | PINCTRL_PIN(81, "PLGPIO81"), | ||
100 | PINCTRL_PIN(82, "PLGPIO82"), | ||
101 | PINCTRL_PIN(83, "PLGPIO83"), | ||
102 | PINCTRL_PIN(84, "PLGPIO84"), | ||
103 | PINCTRL_PIN(85, "PLGPIO85"), | ||
104 | PINCTRL_PIN(86, "PLGPIO86"), | ||
105 | PINCTRL_PIN(87, "PLGPIO87"), | ||
106 | PINCTRL_PIN(88, "PLGPIO88"), | ||
107 | PINCTRL_PIN(89, "PLGPIO89"), | ||
108 | PINCTRL_PIN(90, "PLGPIO90"), | ||
109 | PINCTRL_PIN(91, "PLGPIO91"), | ||
110 | PINCTRL_PIN(92, "PLGPIO92"), | ||
111 | PINCTRL_PIN(93, "PLGPIO93"), | ||
112 | PINCTRL_PIN(94, "PLGPIO94"), | ||
113 | PINCTRL_PIN(95, "PLGPIO95"), | ||
114 | PINCTRL_PIN(96, "PLGPIO96"), | ||
115 | PINCTRL_PIN(97, "PLGPIO97"), | ||
116 | PINCTRL_PIN(98, "PLGPIO98"), | ||
117 | PINCTRL_PIN(99, "PLGPIO99"), | ||
118 | PINCTRL_PIN(100, "PLGPIO100"), | ||
119 | PINCTRL_PIN(101, "PLGPIO101"), | ||
120 | }; | ||
121 | |||
122 | /* firda_pins */ | ||
123 | static const unsigned firda_pins[] = { 0, 1 }; | ||
124 | static struct spear_muxreg firda_muxreg[] = { | ||
125 | { | ||
126 | .reg = -1, | ||
127 | .mask = PMX_FIRDA_MASK, | ||
128 | .val = PMX_FIRDA_MASK, | ||
129 | }, | ||
130 | }; | ||
131 | |||
132 | static struct spear_modemux firda_modemux[] = { | ||
133 | { | ||
134 | .modes = ~0, | ||
135 | .muxregs = firda_muxreg, | ||
136 | .nmuxregs = ARRAY_SIZE(firda_muxreg), | ||
137 | }, | ||
138 | }; | ||
139 | |||
140 | struct spear_pingroup spear3xx_firda_pingroup = { | ||
141 | .name = "firda_grp", | ||
142 | .pins = firda_pins, | ||
143 | .npins = ARRAY_SIZE(firda_pins), | ||
144 | .modemuxs = firda_modemux, | ||
145 | .nmodemuxs = ARRAY_SIZE(firda_modemux), | ||
146 | }; | ||
147 | |||
148 | static const char *const firda_grps[] = { "firda_grp" }; | ||
149 | struct spear_function spear3xx_firda_function = { | ||
150 | .name = "firda", | ||
151 | .groups = firda_grps, | ||
152 | .ngroups = ARRAY_SIZE(firda_grps), | ||
153 | }; | ||
154 | |||
155 | /* i2c_pins */ | ||
156 | static const unsigned i2c_pins[] = { 4, 5 }; | ||
157 | static struct spear_muxreg i2c_muxreg[] = { | ||
158 | { | ||
159 | .reg = -1, | ||
160 | .mask = PMX_I2C_MASK, | ||
161 | .val = PMX_I2C_MASK, | ||
162 | }, | ||
163 | }; | ||
164 | |||
165 | static struct spear_modemux i2c_modemux[] = { | ||
166 | { | ||
167 | .modes = ~0, | ||
168 | .muxregs = i2c_muxreg, | ||
169 | .nmuxregs = ARRAY_SIZE(i2c_muxreg), | ||
170 | }, | ||
171 | }; | ||
172 | |||
173 | struct spear_pingroup spear3xx_i2c_pingroup = { | ||
174 | .name = "i2c0_grp", | ||
175 | .pins = i2c_pins, | ||
176 | .npins = ARRAY_SIZE(i2c_pins), | ||
177 | .modemuxs = i2c_modemux, | ||
178 | .nmodemuxs = ARRAY_SIZE(i2c_modemux), | ||
179 | }; | ||
180 | |||
181 | static const char *const i2c_grps[] = { "i2c0_grp" }; | ||
182 | struct spear_function spear3xx_i2c_function = { | ||
183 | .name = "i2c0", | ||
184 | .groups = i2c_grps, | ||
185 | .ngroups = ARRAY_SIZE(i2c_grps), | ||
186 | }; | ||
187 | |||
188 | /* ssp_cs_pins */ | ||
189 | static const unsigned ssp_cs_pins[] = { 34, 35, 36 }; | ||
190 | static struct spear_muxreg ssp_cs_muxreg[] = { | ||
191 | { | ||
192 | .reg = -1, | ||
193 | .mask = PMX_SSP_CS_MASK, | ||
194 | .val = PMX_SSP_CS_MASK, | ||
195 | }, | ||
196 | }; | ||
197 | |||
198 | static struct spear_modemux ssp_cs_modemux[] = { | ||
199 | { | ||
200 | .modes = ~0, | ||
201 | .muxregs = ssp_cs_muxreg, | ||
202 | .nmuxregs = ARRAY_SIZE(ssp_cs_muxreg), | ||
203 | }, | ||
204 | }; | ||
205 | |||
206 | struct spear_pingroup spear3xx_ssp_cs_pingroup = { | ||
207 | .name = "ssp_cs_grp", | ||
208 | .pins = ssp_cs_pins, | ||
209 | .npins = ARRAY_SIZE(ssp_cs_pins), | ||
210 | .modemuxs = ssp_cs_modemux, | ||
211 | .nmodemuxs = ARRAY_SIZE(ssp_cs_modemux), | ||
212 | }; | ||
213 | |||
214 | static const char *const ssp_cs_grps[] = { "ssp_cs_grp" }; | ||
215 | struct spear_function spear3xx_ssp_cs_function = { | ||
216 | .name = "ssp_cs", | ||
217 | .groups = ssp_cs_grps, | ||
218 | .ngroups = ARRAY_SIZE(ssp_cs_grps), | ||
219 | }; | ||
220 | |||
221 | /* ssp_pins */ | ||
222 | static const unsigned ssp_pins[] = { 6, 7, 8, 9 }; | ||
223 | static struct spear_muxreg ssp_muxreg[] = { | ||
224 | { | ||
225 | .reg = -1, | ||
226 | .mask = PMX_SSP_MASK, | ||
227 | .val = PMX_SSP_MASK, | ||
228 | }, | ||
229 | }; | ||
230 | |||
231 | static struct spear_modemux ssp_modemux[] = { | ||
232 | { | ||
233 | .modes = ~0, | ||
234 | .muxregs = ssp_muxreg, | ||
235 | .nmuxregs = ARRAY_SIZE(ssp_muxreg), | ||
236 | }, | ||
237 | }; | ||
238 | |||
239 | struct spear_pingroup spear3xx_ssp_pingroup = { | ||
240 | .name = "ssp0_grp", | ||
241 | .pins = ssp_pins, | ||
242 | .npins = ARRAY_SIZE(ssp_pins), | ||
243 | .modemuxs = ssp_modemux, | ||
244 | .nmodemuxs = ARRAY_SIZE(ssp_modemux), | ||
245 | }; | ||
246 | |||
247 | static const char *const ssp_grps[] = { "ssp0_grp" }; | ||
248 | struct spear_function spear3xx_ssp_function = { | ||
249 | .name = "ssp0", | ||
250 | .groups = ssp_grps, | ||
251 | .ngroups = ARRAY_SIZE(ssp_grps), | ||
252 | }; | ||
253 | |||
254 | /* mii_pins */ | ||
255 | static const unsigned mii_pins[] = { 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, | ||
256 | 21, 22, 23, 24, 25, 26, 27 }; | ||
257 | static struct spear_muxreg mii_muxreg[] = { | ||
258 | { | ||
259 | .reg = -1, | ||
260 | .mask = PMX_MII_MASK, | ||
261 | .val = PMX_MII_MASK, | ||
262 | }, | ||
263 | }; | ||
264 | |||
265 | static struct spear_modemux mii_modemux[] = { | ||
266 | { | ||
267 | .modes = ~0, | ||
268 | .muxregs = mii_muxreg, | ||
269 | .nmuxregs = ARRAY_SIZE(mii_muxreg), | ||
270 | }, | ||
271 | }; | ||
272 | |||
273 | struct spear_pingroup spear3xx_mii_pingroup = { | ||
274 | .name = "mii0_grp", | ||
275 | .pins = mii_pins, | ||
276 | .npins = ARRAY_SIZE(mii_pins), | ||
277 | .modemuxs = mii_modemux, | ||
278 | .nmodemuxs = ARRAY_SIZE(mii_modemux), | ||
279 | }; | ||
280 | |||
281 | static const char *const mii_grps[] = { "mii0_grp" }; | ||
282 | struct spear_function spear3xx_mii_function = { | ||
283 | .name = "mii0", | ||
284 | .groups = mii_grps, | ||
285 | .ngroups = ARRAY_SIZE(mii_grps), | ||
286 | }; | ||
287 | |||
288 | /* gpio0_pin0_pins */ | ||
289 | static const unsigned gpio0_pin0_pins[] = { 28 }; | ||
290 | static struct spear_muxreg gpio0_pin0_muxreg[] = { | ||
291 | { | ||
292 | .reg = -1, | ||
293 | .mask = PMX_GPIO_PIN0_MASK, | ||
294 | .val = PMX_GPIO_PIN0_MASK, | ||
295 | }, | ||
296 | }; | ||
297 | |||
298 | static struct spear_modemux gpio0_pin0_modemux[] = { | ||
299 | { | ||
300 | .modes = ~0, | ||
301 | .muxregs = gpio0_pin0_muxreg, | ||
302 | .nmuxregs = ARRAY_SIZE(gpio0_pin0_muxreg), | ||
303 | }, | ||
304 | }; | ||
305 | |||
306 | struct spear_pingroup spear3xx_gpio0_pin0_pingroup = { | ||
307 | .name = "gpio0_pin0_grp", | ||
308 | .pins = gpio0_pin0_pins, | ||
309 | .npins = ARRAY_SIZE(gpio0_pin0_pins), | ||
310 | .modemuxs = gpio0_pin0_modemux, | ||
311 | .nmodemuxs = ARRAY_SIZE(gpio0_pin0_modemux), | ||
312 | }; | ||
313 | |||
314 | /* gpio0_pin1_pins */ | ||
315 | static const unsigned gpio0_pin1_pins[] = { 29 }; | ||
316 | static struct spear_muxreg gpio0_pin1_muxreg[] = { | ||
317 | { | ||
318 | .reg = -1, | ||
319 | .mask = PMX_GPIO_PIN1_MASK, | ||
320 | .val = PMX_GPIO_PIN1_MASK, | ||
321 | }, | ||
322 | }; | ||
323 | |||
324 | static struct spear_modemux gpio0_pin1_modemux[] = { | ||
325 | { | ||
326 | .modes = ~0, | ||
327 | .muxregs = gpio0_pin1_muxreg, | ||
328 | .nmuxregs = ARRAY_SIZE(gpio0_pin1_muxreg), | ||
329 | }, | ||
330 | }; | ||
331 | |||
332 | struct spear_pingroup spear3xx_gpio0_pin1_pingroup = { | ||
333 | .name = "gpio0_pin1_grp", | ||
334 | .pins = gpio0_pin1_pins, | ||
335 | .npins = ARRAY_SIZE(gpio0_pin1_pins), | ||
336 | .modemuxs = gpio0_pin1_modemux, | ||
337 | .nmodemuxs = ARRAY_SIZE(gpio0_pin1_modemux), | ||
338 | }; | ||
339 | |||
340 | /* gpio0_pin2_pins */ | ||
341 | static const unsigned gpio0_pin2_pins[] = { 30 }; | ||
342 | static struct spear_muxreg gpio0_pin2_muxreg[] = { | ||
343 | { | ||
344 | .reg = -1, | ||
345 | .mask = PMX_GPIO_PIN2_MASK, | ||
346 | .val = PMX_GPIO_PIN2_MASK, | ||
347 | }, | ||
348 | }; | ||
349 | |||
350 | static struct spear_modemux gpio0_pin2_modemux[] = { | ||
351 | { | ||
352 | .modes = ~0, | ||
353 | .muxregs = gpio0_pin2_muxreg, | ||
354 | .nmuxregs = ARRAY_SIZE(gpio0_pin2_muxreg), | ||
355 | }, | ||
356 | }; | ||
357 | |||
358 | struct spear_pingroup spear3xx_gpio0_pin2_pingroup = { | ||
359 | .name = "gpio0_pin2_grp", | ||
360 | .pins = gpio0_pin2_pins, | ||
361 | .npins = ARRAY_SIZE(gpio0_pin2_pins), | ||
362 | .modemuxs = gpio0_pin2_modemux, | ||
363 | .nmodemuxs = ARRAY_SIZE(gpio0_pin2_modemux), | ||
364 | }; | ||
365 | |||
366 | /* gpio0_pin3_pins */ | ||
367 | static const unsigned gpio0_pin3_pins[] = { 31 }; | ||
368 | static struct spear_muxreg gpio0_pin3_muxreg[] = { | ||
369 | { | ||
370 | .reg = -1, | ||
371 | .mask = PMX_GPIO_PIN3_MASK, | ||
372 | .val = PMX_GPIO_PIN3_MASK, | ||
373 | }, | ||
374 | }; | ||
375 | |||
376 | static struct spear_modemux gpio0_pin3_modemux[] = { | ||
377 | { | ||
378 | .modes = ~0, | ||
379 | .muxregs = gpio0_pin3_muxreg, | ||
380 | .nmuxregs = ARRAY_SIZE(gpio0_pin3_muxreg), | ||
381 | }, | ||
382 | }; | ||
383 | |||
384 | struct spear_pingroup spear3xx_gpio0_pin3_pingroup = { | ||
385 | .name = "gpio0_pin3_grp", | ||
386 | .pins = gpio0_pin3_pins, | ||
387 | .npins = ARRAY_SIZE(gpio0_pin3_pins), | ||
388 | .modemuxs = gpio0_pin3_modemux, | ||
389 | .nmodemuxs = ARRAY_SIZE(gpio0_pin3_modemux), | ||
390 | }; | ||
391 | |||
392 | /* gpio0_pin4_pins */ | ||
393 | static const unsigned gpio0_pin4_pins[] = { 32 }; | ||
394 | static struct spear_muxreg gpio0_pin4_muxreg[] = { | ||
395 | { | ||
396 | .reg = -1, | ||
397 | .mask = PMX_GPIO_PIN4_MASK, | ||
398 | .val = PMX_GPIO_PIN4_MASK, | ||
399 | }, | ||
400 | }; | ||
401 | |||
402 | static struct spear_modemux gpio0_pin4_modemux[] = { | ||
403 | { | ||
404 | .modes = ~0, | ||
405 | .muxregs = gpio0_pin4_muxreg, | ||
406 | .nmuxregs = ARRAY_SIZE(gpio0_pin4_muxreg), | ||
407 | }, | ||
408 | }; | ||
409 | |||
410 | struct spear_pingroup spear3xx_gpio0_pin4_pingroup = { | ||
411 | .name = "gpio0_pin4_grp", | ||
412 | .pins = gpio0_pin4_pins, | ||
413 | .npins = ARRAY_SIZE(gpio0_pin4_pins), | ||
414 | .modemuxs = gpio0_pin4_modemux, | ||
415 | .nmodemuxs = ARRAY_SIZE(gpio0_pin4_modemux), | ||
416 | }; | ||
417 | |||
418 | /* gpio0_pin5_pins */ | ||
419 | static const unsigned gpio0_pin5_pins[] = { 33 }; | ||
420 | static struct spear_muxreg gpio0_pin5_muxreg[] = { | ||
421 | { | ||
422 | .reg = -1, | ||
423 | .mask = PMX_GPIO_PIN5_MASK, | ||
424 | .val = PMX_GPIO_PIN5_MASK, | ||
425 | }, | ||
426 | }; | ||
427 | |||
428 | static struct spear_modemux gpio0_pin5_modemux[] = { | ||
429 | { | ||
430 | .modes = ~0, | ||
431 | .muxregs = gpio0_pin5_muxreg, | ||
432 | .nmuxregs = ARRAY_SIZE(gpio0_pin5_muxreg), | ||
433 | }, | ||
434 | }; | ||
435 | |||
436 | struct spear_pingroup spear3xx_gpio0_pin5_pingroup = { | ||
437 | .name = "gpio0_pin5_grp", | ||
438 | .pins = gpio0_pin5_pins, | ||
439 | .npins = ARRAY_SIZE(gpio0_pin5_pins), | ||
440 | .modemuxs = gpio0_pin5_modemux, | ||
441 | .nmodemuxs = ARRAY_SIZE(gpio0_pin5_modemux), | ||
442 | }; | ||
443 | |||
444 | static const char *const gpio0_grps[] = { "gpio0_pin0_grp", "gpio0_pin1_grp", | ||
445 | "gpio0_pin2_grp", "gpio0_pin3_grp", "gpio0_pin4_grp", "gpio0_pin5_grp", | ||
446 | }; | ||
447 | struct spear_function spear3xx_gpio0_function = { | ||
448 | .name = "gpio0", | ||
449 | .groups = gpio0_grps, | ||
450 | .ngroups = ARRAY_SIZE(gpio0_grps), | ||
451 | }; | ||
452 | |||
453 | /* uart0_ext_pins */ | ||
454 | static const unsigned uart0_ext_pins[] = { 37, 38, 39, 40, 41, 42 }; | ||
455 | static struct spear_muxreg uart0_ext_muxreg[] = { | ||
456 | { | ||
457 | .reg = -1, | ||
458 | .mask = PMX_UART0_MODEM_MASK, | ||
459 | .val = PMX_UART0_MODEM_MASK, | ||
460 | }, | ||
461 | }; | ||
462 | |||
463 | static struct spear_modemux uart0_ext_modemux[] = { | ||
464 | { | ||
465 | .modes = ~0, | ||
466 | .muxregs = uart0_ext_muxreg, | ||
467 | .nmuxregs = ARRAY_SIZE(uart0_ext_muxreg), | ||
468 | }, | ||
469 | }; | ||
470 | |||
471 | struct spear_pingroup spear3xx_uart0_ext_pingroup = { | ||
472 | .name = "uart0_ext_grp", | ||
473 | .pins = uart0_ext_pins, | ||
474 | .npins = ARRAY_SIZE(uart0_ext_pins), | ||
475 | .modemuxs = uart0_ext_modemux, | ||
476 | .nmodemuxs = ARRAY_SIZE(uart0_ext_modemux), | ||
477 | }; | ||
478 | |||
479 | static const char *const uart0_ext_grps[] = { "uart0_ext_grp" }; | ||
480 | struct spear_function spear3xx_uart0_ext_function = { | ||
481 | .name = "uart0_ext", | ||
482 | .groups = uart0_ext_grps, | ||
483 | .ngroups = ARRAY_SIZE(uart0_ext_grps), | ||
484 | }; | ||
485 | |||
486 | /* uart0_pins */ | ||
487 | static const unsigned uart0_pins[] = { 2, 3 }; | ||
488 | static struct spear_muxreg uart0_muxreg[] = { | ||
489 | { | ||
490 | .reg = -1, | ||
491 | .mask = PMX_UART0_MASK, | ||
492 | .val = PMX_UART0_MASK, | ||
493 | }, | ||
494 | }; | ||
495 | |||
496 | static struct spear_modemux uart0_modemux[] = { | ||
497 | { | ||
498 | .modes = ~0, | ||
499 | .muxregs = uart0_muxreg, | ||
500 | .nmuxregs = ARRAY_SIZE(uart0_muxreg), | ||
501 | }, | ||
502 | }; | ||
503 | |||
504 | struct spear_pingroup spear3xx_uart0_pingroup = { | ||
505 | .name = "uart0_grp", | ||
506 | .pins = uart0_pins, | ||
507 | .npins = ARRAY_SIZE(uart0_pins), | ||
508 | .modemuxs = uart0_modemux, | ||
509 | .nmodemuxs = ARRAY_SIZE(uart0_modemux), | ||
510 | }; | ||
511 | |||
512 | static const char *const uart0_grps[] = { "uart0_grp" }; | ||
513 | struct spear_function spear3xx_uart0_function = { | ||
514 | .name = "uart0", | ||
515 | .groups = uart0_grps, | ||
516 | .ngroups = ARRAY_SIZE(uart0_grps), | ||
517 | }; | ||
518 | |||
519 | /* timer_0_1_pins */ | ||
520 | static const unsigned timer_0_1_pins[] = { 43, 44, 47, 48 }; | ||
521 | static struct spear_muxreg timer_0_1_muxreg[] = { | ||
522 | { | ||
523 | .reg = -1, | ||
524 | .mask = PMX_TIMER_0_1_MASK, | ||
525 | .val = PMX_TIMER_0_1_MASK, | ||
526 | }, | ||
527 | }; | ||
528 | |||
529 | static struct spear_modemux timer_0_1_modemux[] = { | ||
530 | { | ||
531 | .modes = ~0, | ||
532 | .muxregs = timer_0_1_muxreg, | ||
533 | .nmuxregs = ARRAY_SIZE(timer_0_1_muxreg), | ||
534 | }, | ||
535 | }; | ||
536 | |||
537 | struct spear_pingroup spear3xx_timer_0_1_pingroup = { | ||
538 | .name = "timer_0_1_grp", | ||
539 | .pins = timer_0_1_pins, | ||
540 | .npins = ARRAY_SIZE(timer_0_1_pins), | ||
541 | .modemuxs = timer_0_1_modemux, | ||
542 | .nmodemuxs = ARRAY_SIZE(timer_0_1_modemux), | ||
543 | }; | ||
544 | |||
545 | static const char *const timer_0_1_grps[] = { "timer_0_1_grp" }; | ||
546 | struct spear_function spear3xx_timer_0_1_function = { | ||
547 | .name = "timer_0_1", | ||
548 | .groups = timer_0_1_grps, | ||
549 | .ngroups = ARRAY_SIZE(timer_0_1_grps), | ||
550 | }; | ||
551 | |||
552 | /* timer_2_3_pins */ | ||
553 | static const unsigned timer_2_3_pins[] = { 45, 46, 49, 50 }; | ||
554 | static struct spear_muxreg timer_2_3_muxreg[] = { | ||
555 | { | ||
556 | .reg = -1, | ||
557 | .mask = PMX_TIMER_2_3_MASK, | ||
558 | .val = PMX_TIMER_2_3_MASK, | ||
559 | }, | ||
560 | }; | ||
561 | |||
562 | static struct spear_modemux timer_2_3_modemux[] = { | ||
563 | { | ||
564 | .modes = ~0, | ||
565 | .muxregs = timer_2_3_muxreg, | ||
566 | .nmuxregs = ARRAY_SIZE(timer_2_3_muxreg), | ||
567 | }, | ||
568 | }; | ||
569 | |||
570 | struct spear_pingroup spear3xx_timer_2_3_pingroup = { | ||
571 | .name = "timer_2_3_grp", | ||
572 | .pins = timer_2_3_pins, | ||
573 | .npins = ARRAY_SIZE(timer_2_3_pins), | ||
574 | .modemuxs = timer_2_3_modemux, | ||
575 | .nmodemuxs = ARRAY_SIZE(timer_2_3_modemux), | ||
576 | }; | ||
577 | |||
578 | static const char *const timer_2_3_grps[] = { "timer_2_3_grp" }; | ||
579 | struct spear_function spear3xx_timer_2_3_function = { | ||
580 | .name = "timer_2_3", | ||
581 | .groups = timer_2_3_grps, | ||
582 | .ngroups = ARRAY_SIZE(timer_2_3_grps), | ||
583 | }; | ||
584 | |||
585 | struct spear_pinctrl_machdata spear3xx_machdata = { | ||
586 | .pins = spear3xx_pins, | ||
587 | .npins = ARRAY_SIZE(spear3xx_pins), | ||
588 | }; | ||
diff --git a/drivers/pinctrl/spear/pinctrl-spear3xx.h b/drivers/pinctrl/spear/pinctrl-spear3xx.h new file mode 100644 index 000000000000..5d5fdd8df7b8 --- /dev/null +++ b/drivers/pinctrl/spear/pinctrl-spear3xx.h | |||
@@ -0,0 +1,92 @@ | |||
1 | /* | ||
2 | * Header file for the ST Microelectronics SPEAr3xx pinmux | ||
3 | * | ||
4 | * Copyright (C) 2012 ST Microelectronics | ||
5 | * Viresh Kumar <viresh.kumar@st.com> | ||
6 | * | ||
7 | * This file is licensed under the terms of the GNU General Public | ||
8 | * License version 2. This program is licensed "as is" without any | ||
9 | * warranty of any kind, whether express or implied. | ||
10 | */ | ||
11 | |||
12 | #ifndef __PINMUX_SPEAR3XX_H__ | ||
13 | #define __PINMUX_SPEAR3XX_H__ | ||
14 | |||
15 | #include "pinctrl-spear.h" | ||
16 | |||
17 | /* pad mux declarations */ | ||
18 | #define PMX_FIRDA_MASK (1 << 14) | ||
19 | #define PMX_I2C_MASK (1 << 13) | ||
20 | #define PMX_SSP_CS_MASK (1 << 12) | ||
21 | #define PMX_SSP_MASK (1 << 11) | ||
22 | #define PMX_MII_MASK (1 << 10) | ||
23 | #define PMX_GPIO_PIN0_MASK (1 << 9) | ||
24 | #define PMX_GPIO_PIN1_MASK (1 << 8) | ||
25 | #define PMX_GPIO_PIN2_MASK (1 << 7) | ||
26 | #define PMX_GPIO_PIN3_MASK (1 << 6) | ||
27 | #define PMX_GPIO_PIN4_MASK (1 << 5) | ||
28 | #define PMX_GPIO_PIN5_MASK (1 << 4) | ||
29 | #define PMX_UART0_MODEM_MASK (1 << 3) | ||
30 | #define PMX_UART0_MASK (1 << 2) | ||
31 | #define PMX_TIMER_2_3_MASK (1 << 1) | ||
32 | #define PMX_TIMER_0_1_MASK (1 << 0) | ||
33 | |||
34 | extern struct spear_pingroup spear3xx_firda_pingroup; | ||
35 | extern struct spear_pingroup spear3xx_gpio0_pin0_pingroup; | ||
36 | extern struct spear_pingroup spear3xx_gpio0_pin1_pingroup; | ||
37 | extern struct spear_pingroup spear3xx_gpio0_pin2_pingroup; | ||
38 | extern struct spear_pingroup spear3xx_gpio0_pin3_pingroup; | ||
39 | extern struct spear_pingroup spear3xx_gpio0_pin4_pingroup; | ||
40 | extern struct spear_pingroup spear3xx_gpio0_pin5_pingroup; | ||
41 | extern struct spear_pingroup spear3xx_i2c_pingroup; | ||
42 | extern struct spear_pingroup spear3xx_mii_pingroup; | ||
43 | extern struct spear_pingroup spear3xx_ssp_cs_pingroup; | ||
44 | extern struct spear_pingroup spear3xx_ssp_pingroup; | ||
45 | extern struct spear_pingroup spear3xx_timer_0_1_pingroup; | ||
46 | extern struct spear_pingroup spear3xx_timer_2_3_pingroup; | ||
47 | extern struct spear_pingroup spear3xx_uart0_ext_pingroup; | ||
48 | extern struct spear_pingroup spear3xx_uart0_pingroup; | ||
49 | |||
50 | #define SPEAR3XX_COMMON_PINGROUPS \ | ||
51 | &spear3xx_firda_pingroup, \ | ||
52 | &spear3xx_gpio0_pin0_pingroup, \ | ||
53 | &spear3xx_gpio0_pin1_pingroup, \ | ||
54 | &spear3xx_gpio0_pin2_pingroup, \ | ||
55 | &spear3xx_gpio0_pin3_pingroup, \ | ||
56 | &spear3xx_gpio0_pin4_pingroup, \ | ||
57 | &spear3xx_gpio0_pin5_pingroup, \ | ||
58 | &spear3xx_i2c_pingroup, \ | ||
59 | &spear3xx_mii_pingroup, \ | ||
60 | &spear3xx_ssp_cs_pingroup, \ | ||
61 | &spear3xx_ssp_pingroup, \ | ||
62 | &spear3xx_timer_0_1_pingroup, \ | ||
63 | &spear3xx_timer_2_3_pingroup, \ | ||
64 | &spear3xx_uart0_ext_pingroup, \ | ||
65 | &spear3xx_uart0_pingroup | ||
66 | |||
67 | extern struct spear_function spear3xx_firda_function; | ||
68 | extern struct spear_function spear3xx_gpio0_function; | ||
69 | extern struct spear_function spear3xx_i2c_function; | ||
70 | extern struct spear_function spear3xx_mii_function; | ||
71 | extern struct spear_function spear3xx_ssp_cs_function; | ||
72 | extern struct spear_function spear3xx_ssp_function; | ||
73 | extern struct spear_function spear3xx_timer_0_1_function; | ||
74 | extern struct spear_function spear3xx_timer_2_3_function; | ||
75 | extern struct spear_function spear3xx_uart0_ext_function; | ||
76 | extern struct spear_function spear3xx_uart0_function; | ||
77 | |||
78 | #define SPEAR3XX_COMMON_FUNCTIONS \ | ||
79 | &spear3xx_firda_function, \ | ||
80 | &spear3xx_gpio0_function, \ | ||
81 | &spear3xx_i2c_function, \ | ||
82 | &spear3xx_mii_function, \ | ||
83 | &spear3xx_ssp_cs_function, \ | ||
84 | &spear3xx_ssp_function, \ | ||
85 | &spear3xx_timer_0_1_function, \ | ||
86 | &spear3xx_timer_2_3_function, \ | ||
87 | &spear3xx_uart0_ext_function, \ | ||
88 | &spear3xx_uart0_function | ||
89 | |||
90 | extern struct spear_pinctrl_machdata spear3xx_machdata; | ||
91 | |||
92 | #endif /* __PINMUX_SPEAR3XX_H__ */ | ||
diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c index 570f22053be8..69c9a6601f45 100644 --- a/drivers/spi/spi-imx.c +++ b/drivers/spi/spi-imx.c | |||
@@ -37,6 +37,7 @@ | |||
37 | #include <linux/of.h> | 37 | #include <linux/of.h> |
38 | #include <linux/of_device.h> | 38 | #include <linux/of_device.h> |
39 | #include <linux/of_gpio.h> | 39 | #include <linux/of_gpio.h> |
40 | #include <linux/pinctrl/consumer.h> | ||
40 | 41 | ||
41 | #include <mach/spi.h> | 42 | #include <mach/spi.h> |
42 | 43 | ||
@@ -758,6 +759,7 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) | |||
758 | struct spi_master *master; | 759 | struct spi_master *master; |
759 | struct spi_imx_data *spi_imx; | 760 | struct spi_imx_data *spi_imx; |
760 | struct resource *res; | 761 | struct resource *res; |
762 | struct pinctrl *pinctrl; | ||
761 | int i, ret, num_cs; | 763 | int i, ret, num_cs; |
762 | 764 | ||
763 | if (!np && !mxc_platform_info) { | 765 | if (!np && !mxc_platform_info) { |
@@ -845,6 +847,12 @@ static int __devinit spi_imx_probe(struct platform_device *pdev) | |||
845 | goto out_iounmap; | 847 | goto out_iounmap; |
846 | } | 848 | } |
847 | 849 | ||
850 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
851 | if (IS_ERR(pinctrl)) { | ||
852 | ret = PTR_ERR(pinctrl); | ||
853 | goto out_free_irq; | ||
854 | } | ||
855 | |||
848 | spi_imx->clk = clk_get(&pdev->dev, NULL); | 856 | spi_imx->clk = clk_get(&pdev->dev, NULL); |
849 | if (IS_ERR(spi_imx->clk)) { | 857 | if (IS_ERR(spi_imx->clk)) { |
850 | dev_err(&pdev->dev, "unable to get clock\n"); | 858 | dev_err(&pdev->dev, "unable to get clock\n"); |
diff --git a/drivers/tty/serial/amba-pl011.c b/drivers/tty/serial/amba-pl011.c index 3d569cd68f58..062ef8c2b3cb 100644 --- a/drivers/tty/serial/amba-pl011.c +++ b/drivers/tty/serial/amba-pl011.c | |||
@@ -52,6 +52,7 @@ | |||
52 | #include <linux/scatterlist.h> | 52 | #include <linux/scatterlist.h> |
53 | #include <linux/delay.h> | 53 | #include <linux/delay.h> |
54 | #include <linux/types.h> | 54 | #include <linux/types.h> |
55 | #include <linux/pinctrl/consumer.h> | ||
55 | 56 | ||
56 | #include <asm/io.h> | 57 | #include <asm/io.h> |
57 | #include <asm/sizes.h> | 58 | #include <asm/sizes.h> |
@@ -1916,6 +1917,7 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) | |||
1916 | { | 1917 | { |
1917 | struct uart_amba_port *uap; | 1918 | struct uart_amba_port *uap; |
1918 | struct vendor_data *vendor = id->data; | 1919 | struct vendor_data *vendor = id->data; |
1920 | struct pinctrl *pinctrl; | ||
1919 | void __iomem *base; | 1921 | void __iomem *base; |
1920 | int i, ret; | 1922 | int i, ret; |
1921 | 1923 | ||
@@ -1940,6 +1942,12 @@ static int pl011_probe(struct amba_device *dev, const struct amba_id *id) | |||
1940 | goto free; | 1942 | goto free; |
1941 | } | 1943 | } |
1942 | 1944 | ||
1945 | pinctrl = devm_pinctrl_get_select_default(&dev->dev); | ||
1946 | if (IS_ERR(pinctrl)) { | ||
1947 | ret = PTR_ERR(pinctrl); | ||
1948 | goto unmap; | ||
1949 | } | ||
1950 | |||
1943 | uap->clk = clk_get(&dev->dev, NULL); | 1951 | uap->clk = clk_get(&dev->dev, NULL); |
1944 | if (IS_ERR(uap->clk)) { | 1952 | if (IS_ERR(uap->clk)) { |
1945 | ret = PTR_ERR(uap->clk); | 1953 | ret = PTR_ERR(uap->clk); |
diff --git a/drivers/tty/serial/imx.c b/drivers/tty/serial/imx.c index e7feceeebc2f..ec206732f68c 100644 --- a/drivers/tty/serial/imx.c +++ b/drivers/tty/serial/imx.c | |||
@@ -47,6 +47,7 @@ | |||
47 | #include <linux/slab.h> | 47 | #include <linux/slab.h> |
48 | #include <linux/of.h> | 48 | #include <linux/of.h> |
49 | #include <linux/of_device.h> | 49 | #include <linux/of_device.h> |
50 | #include <linux/pinctrl/consumer.h> | ||
50 | 51 | ||
51 | #include <asm/io.h> | 52 | #include <asm/io.h> |
52 | #include <asm/irq.h> | 53 | #include <asm/irq.h> |
@@ -1464,6 +1465,7 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
1464 | void __iomem *base; | 1465 | void __iomem *base; |
1465 | int ret = 0; | 1466 | int ret = 0; |
1466 | struct resource *res; | 1467 | struct resource *res; |
1468 | struct pinctrl *pinctrl; | ||
1467 | 1469 | ||
1468 | sport = kzalloc(sizeof(*sport), GFP_KERNEL); | 1470 | sport = kzalloc(sizeof(*sport), GFP_KERNEL); |
1469 | if (!sport) | 1471 | if (!sport) |
@@ -1503,6 +1505,12 @@ static int serial_imx_probe(struct platform_device *pdev) | |||
1503 | sport->timer.function = imx_timeout; | 1505 | sport->timer.function = imx_timeout; |
1504 | sport->timer.data = (unsigned long)sport; | 1506 | sport->timer.data = (unsigned long)sport; |
1505 | 1507 | ||
1508 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
1509 | if (IS_ERR(pinctrl)) { | ||
1510 | ret = PTR_ERR(pinctrl); | ||
1511 | goto unmap; | ||
1512 | } | ||
1513 | |||
1506 | sport->clk = clk_get(&pdev->dev, "uart"); | 1514 | sport->clk = clk_get(&pdev->dev, "uart"); |
1507 | if (IS_ERR(sport->clk)) { | 1515 | if (IS_ERR(sport->clk)) { |
1508 | ret = PTR_ERR(sport->clk); | 1516 | ret = PTR_ERR(sport->clk); |
diff --git a/drivers/tty/serial/mxs-auart.c b/drivers/tty/serial/mxs-auart.c index 55fd362b9879..7081600bede4 100644 --- a/drivers/tty/serial/mxs-auart.c +++ b/drivers/tty/serial/mxs-auart.c | |||
@@ -32,6 +32,7 @@ | |||
32 | #include <linux/clk.h> | 32 | #include <linux/clk.h> |
33 | #include <linux/delay.h> | 33 | #include <linux/delay.h> |
34 | #include <linux/io.h> | 34 | #include <linux/io.h> |
35 | #include <linux/pinctrl/consumer.h> | ||
35 | 36 | ||
36 | #include <asm/cacheflush.h> | 37 | #include <asm/cacheflush.h> |
37 | 38 | ||
@@ -678,6 +679,7 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev) | |||
678 | u32 version; | 679 | u32 version; |
679 | int ret = 0; | 680 | int ret = 0; |
680 | struct resource *r; | 681 | struct resource *r; |
682 | struct pinctrl *pinctrl; | ||
681 | 683 | ||
682 | s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); | 684 | s = kzalloc(sizeof(struct mxs_auart_port), GFP_KERNEL); |
683 | if (!s) { | 685 | if (!s) { |
@@ -685,6 +687,12 @@ static int __devinit mxs_auart_probe(struct platform_device *pdev) | |||
685 | goto out; | 687 | goto out; |
686 | } | 688 | } |
687 | 689 | ||
690 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
691 | if (IS_ERR(pinctrl)) { | ||
692 | ret = PTR_ERR(pinctrl); | ||
693 | goto out_free; | ||
694 | } | ||
695 | |||
688 | s->clk = clk_get(&pdev->dev, NULL); | 696 | s->clk = clk_get(&pdev->dev, NULL); |
689 | if (IS_ERR(s->clk)) { | 697 | if (IS_ERR(s->clk)) { |
690 | ret = PTR_ERR(s->clk); | 698 | ret = PTR_ERR(s->clk); |
diff --git a/drivers/usb/host/ehci-tegra.c b/drivers/usb/host/ehci-tegra.c index f214a80cdee2..87e271b9c157 100644 --- a/drivers/usb/host/ehci-tegra.c +++ b/drivers/usb/host/ehci-tegra.c | |||
@@ -436,15 +436,16 @@ static const struct hc_driver tegra_ehci_hc_driver = { | |||
436 | .port_handed_over = ehci_port_handed_over, | 436 | .port_handed_over = ehci_port_handed_over, |
437 | }; | 437 | }; |
438 | 438 | ||
439 | static int setup_vbus_gpio(struct platform_device *pdev) | 439 | static int setup_vbus_gpio(struct platform_device *pdev, |
440 | struct tegra_ehci_platform_data *pdata) | ||
440 | { | 441 | { |
441 | int err = 0; | 442 | int err = 0; |
442 | int gpio; | 443 | int gpio; |
443 | 444 | ||
444 | if (!pdev->dev.of_node) | 445 | gpio = pdata->vbus_gpio; |
445 | return 0; | 446 | if (!gpio_is_valid(gpio)) |
446 | 447 | gpio = of_get_named_gpio(pdev->dev.of_node, | |
447 | gpio = of_get_named_gpio(pdev->dev.of_node, "nvidia,vbus-gpio", 0); | 448 | "nvidia,vbus-gpio", 0); |
448 | if (!gpio_is_valid(gpio)) | 449 | if (!gpio_is_valid(gpio)) |
449 | return 0; | 450 | return 0; |
450 | 451 | ||
@@ -664,7 +665,7 @@ static int tegra_ehci_probe(struct platform_device *pdev) | |||
664 | if (!pdev->dev.dma_mask) | 665 | if (!pdev->dev.dma_mask) |
665 | pdev->dev.dma_mask = &tegra_ehci_dma_mask; | 666 | pdev->dev.dma_mask = &tegra_ehci_dma_mask; |
666 | 667 | ||
667 | setup_vbus_gpio(pdev); | 668 | setup_vbus_gpio(pdev, pdata); |
668 | 669 | ||
669 | tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); | 670 | tegra = kzalloc(sizeof(struct tegra_ehci_hcd), GFP_KERNEL); |
670 | if (!tegra) | 671 | if (!tegra) |
diff --git a/drivers/video/mxsfb.c b/drivers/video/mxsfb.c index 4a89f889852d..6c6bc578d0fc 100644 --- a/drivers/video/mxsfb.c +++ b/drivers/video/mxsfb.c | |||
@@ -45,6 +45,7 @@ | |||
45 | #include <linux/clk.h> | 45 | #include <linux/clk.h> |
46 | #include <linux/dma-mapping.h> | 46 | #include <linux/dma-mapping.h> |
47 | #include <linux/io.h> | 47 | #include <linux/io.h> |
48 | #include <linux/pinctrl/consumer.h> | ||
48 | #include <mach/mxsfb.h> | 49 | #include <mach/mxsfb.h> |
49 | 50 | ||
50 | #define REG_SET 4 | 51 | #define REG_SET 4 |
@@ -756,6 +757,7 @@ static int __devinit mxsfb_probe(struct platform_device *pdev) | |||
756 | struct mxsfb_info *host; | 757 | struct mxsfb_info *host; |
757 | struct fb_info *fb_info; | 758 | struct fb_info *fb_info; |
758 | struct fb_modelist *modelist; | 759 | struct fb_modelist *modelist; |
760 | struct pinctrl *pinctrl; | ||
759 | int i, ret; | 761 | int i, ret; |
760 | 762 | ||
761 | if (!pdata) { | 763 | if (!pdata) { |
@@ -793,6 +795,12 @@ static int __devinit mxsfb_probe(struct platform_device *pdev) | |||
793 | 795 | ||
794 | host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; | 796 | host->devdata = &mxsfb_devdata[pdev->id_entry->driver_data]; |
795 | 797 | ||
798 | pinctrl = devm_pinctrl_get_select_default(&pdev->dev); | ||
799 | if (IS_ERR(pinctrl)) { | ||
800 | ret = PTR_ERR(pinctrl); | ||
801 | goto error_getpin; | ||
802 | } | ||
803 | |||
796 | host->clk = clk_get(&host->pdev->dev, NULL); | 804 | host->clk = clk_get(&host->pdev->dev, NULL); |
797 | if (IS_ERR(host->clk)) { | 805 | if (IS_ERR(host->clk)) { |
798 | ret = PTR_ERR(host->clk); | 806 | ret = PTR_ERR(host->clk); |
@@ -848,6 +856,7 @@ error_init_fb: | |||
848 | error_pseudo_pallette: | 856 | error_pseudo_pallette: |
849 | clk_put(host->clk); | 857 | clk_put(host->clk); |
850 | error_getclock: | 858 | error_getclock: |
859 | error_getpin: | ||
851 | iounmap(host->base); | 860 | iounmap(host->base); |
852 | error_ioremap: | 861 | error_ioremap: |
853 | framebuffer_release(fb_info); | 862 | framebuffer_release(fb_info); |