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-rw-r--r--drivers/Makefile2
-rw-r--r--drivers/clk/Makefile1
-rw-r--r--drivers/clk/at91/Makefile12
-rw-r--r--drivers/clk/at91/clk-main.c187
-rw-r--r--drivers/clk/at91/clk-master.c270
-rw-r--r--drivers/clk/at91/clk-peripheral.c410
-rw-r--r--drivers/clk/at91/clk-pll.c531
-rw-r--r--drivers/clk/at91/clk-plldiv.c135
-rw-r--r--drivers/clk/at91/clk-programmable.c366
-rw-r--r--drivers/clk/at91/clk-smd.c171
-rw-r--r--drivers/clk/at91/clk-system.c135
-rw-r--r--drivers/clk/at91/clk-usb.c398
-rw-r--r--drivers/clk/at91/clk-utmi.c159
-rw-r--r--drivers/clk/at91/pmc.c397
-rw-r--r--drivers/clk/at91/pmc.h116
-rw-r--r--drivers/clk/samsung/clk-exynos4.c3
-rw-r--r--drivers/clocksource/exynos_mct.c4
-rw-r--r--drivers/clocksource/nomadik-mtu.c23
-rw-r--r--drivers/dma/ste_dma40.c4
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c296
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.h14
-rw-r--r--drivers/usb/gadget/atmel_usba_udc.c2
22 files changed, 3554 insertions, 82 deletions
diff --git a/drivers/Makefile b/drivers/Makefile
index 3cc8214f9b26..8e3b8b06c0b2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -118,7 +118,7 @@ obj-$(CONFIG_SGI_SN) += sn/
118obj-y += firmware/ 118obj-y += firmware/
119obj-$(CONFIG_CRYPTO) += crypto/ 119obj-$(CONFIG_CRYPTO) += crypto/
120obj-$(CONFIG_SUPERH) += sh/ 120obj-$(CONFIG_SUPERH) += sh/
121obj-$(CONFIG_ARCH_SHMOBILE) += sh/ 121obj-$(CONFIG_ARCH_SHMOBILE_LEGACY) += sh/
122ifndef CONFIG_ARCH_USES_GETTIMEOFFSET 122ifndef CONFIG_ARCH_USES_GETTIMEOFFSET
123obj-y += clocksource/ 123obj-y += clocksource/
124endif 124endif
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 7a10bc9a23e7..ace7309c4369 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -35,6 +35,7 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
35obj-$(CONFIG_PLAT_SAMSUNG) += samsung/ 35obj-$(CONFIG_PLAT_SAMSUNG) += samsung/
36obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o 36obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
37obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/ 37obj-$(CONFIG_COMMON_CLK_KEYSTONE) += keystone/
38obj-$(CONFIG_COMMON_CLK_AT91) += at91/
38 39
39obj-$(CONFIG_X86) += x86/ 40obj-$(CONFIG_X86) += x86/
40 41
diff --git a/drivers/clk/at91/Makefile b/drivers/clk/at91/Makefile
new file mode 100644
index 000000000000..0e92b716f934
--- /dev/null
+++ b/drivers/clk/at91/Makefile
@@ -0,0 +1,12 @@
1#
2# Makefile for at91 specific clk
3#
4
5obj-y += pmc.o
6obj-y += clk-main.o clk-pll.o clk-plldiv.o clk-master.o
7obj-y += clk-system.o clk-peripheral.o
8
9obj-$(CONFIG_AT91_PROGRAMMABLE_CLOCKS) += clk-programmable.o
10obj-$(CONFIG_HAVE_AT91_UTMI) += clk-utmi.o
11obj-$(CONFIG_HAVE_AT91_USB_CLK) += clk-usb.o
12obj-$(CONFIG_HAVE_AT91_SMD) += clk-smd.o
diff --git a/drivers/clk/at91/clk-main.c b/drivers/clk/at91/clk-main.c
new file mode 100644
index 000000000000..8e9e8cc0412d
--- /dev/null
+++ b/drivers/clk/at91/clk-main.c
@@ -0,0 +1,187 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/delay.h>
15#include <linux/of.h>
16#include <linux/of_address.h>
17#include <linux/of_irq.h>
18#include <linux/io.h>
19#include <linux/interrupt.h>
20#include <linux/irq.h>
21#include <linux/sched.h>
22#include <linux/wait.h>
23
24#include "pmc.h"
25
26#define SLOW_CLOCK_FREQ 32768
27#define MAINF_DIV 16
28#define MAINFRDY_TIMEOUT (((MAINF_DIV + 1) * USEC_PER_SEC) / \
29 SLOW_CLOCK_FREQ)
30#define MAINF_LOOP_MIN_WAIT (USEC_PER_SEC / SLOW_CLOCK_FREQ)
31#define MAINF_LOOP_MAX_WAIT MAINFRDY_TIMEOUT
32
33struct clk_main {
34 struct clk_hw hw;
35 struct at91_pmc *pmc;
36 unsigned long rate;
37 unsigned int irq;
38 wait_queue_head_t wait;
39};
40
41#define to_clk_main(hw) container_of(hw, struct clk_main, hw)
42
43static irqreturn_t clk_main_irq_handler(int irq, void *dev_id)
44{
45 struct clk_main *clkmain = (struct clk_main *)dev_id;
46
47 wake_up(&clkmain->wait);
48 disable_irq_nosync(clkmain->irq);
49
50 return IRQ_HANDLED;
51}
52
53static int clk_main_prepare(struct clk_hw *hw)
54{
55 struct clk_main *clkmain = to_clk_main(hw);
56 struct at91_pmc *pmc = clkmain->pmc;
57 unsigned long halt_time, timeout;
58 u32 tmp;
59
60 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS)) {
61 enable_irq(clkmain->irq);
62 wait_event(clkmain->wait,
63 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
64 }
65
66 if (clkmain->rate)
67 return 0;
68
69 timeout = jiffies + usecs_to_jiffies(MAINFRDY_TIMEOUT);
70 do {
71 halt_time = jiffies;
72 tmp = pmc_read(pmc, AT91_CKGR_MCFR);
73 if (tmp & AT91_PMC_MAINRDY)
74 return 0;
75 usleep_range(MAINF_LOOP_MIN_WAIT, MAINF_LOOP_MAX_WAIT);
76 } while (time_before(halt_time, timeout));
77
78 return 0;
79}
80
81static int clk_main_is_prepared(struct clk_hw *hw)
82{
83 struct clk_main *clkmain = to_clk_main(hw);
84
85 return !!(pmc_read(clkmain->pmc, AT91_PMC_SR) & AT91_PMC_MOSCS);
86}
87
88static unsigned long clk_main_recalc_rate(struct clk_hw *hw,
89 unsigned long parent_rate)
90{
91 u32 tmp;
92 struct clk_main *clkmain = to_clk_main(hw);
93 struct at91_pmc *pmc = clkmain->pmc;
94
95 if (clkmain->rate)
96 return clkmain->rate;
97
98 tmp = pmc_read(pmc, AT91_CKGR_MCFR) & AT91_PMC_MAINF;
99 clkmain->rate = (tmp * parent_rate) / MAINF_DIV;
100
101 return clkmain->rate;
102}
103
104static const struct clk_ops main_ops = {
105 .prepare = clk_main_prepare,
106 .is_prepared = clk_main_is_prepared,
107 .recalc_rate = clk_main_recalc_rate,
108};
109
110static struct clk * __init
111at91_clk_register_main(struct at91_pmc *pmc,
112 unsigned int irq,
113 const char *name,
114 const char *parent_name,
115 unsigned long rate)
116{
117 int ret;
118 struct clk_main *clkmain;
119 struct clk *clk = NULL;
120 struct clk_init_data init;
121
122 if (!pmc || !irq || !name)
123 return ERR_PTR(-EINVAL);
124
125 if (!rate && !parent_name)
126 return ERR_PTR(-EINVAL);
127
128 clkmain = kzalloc(sizeof(*clkmain), GFP_KERNEL);
129 if (!clkmain)
130 return ERR_PTR(-ENOMEM);
131
132 init.name = name;
133 init.ops = &main_ops;
134 init.parent_names = parent_name ? &parent_name : NULL;
135 init.num_parents = parent_name ? 1 : 0;
136 init.flags = parent_name ? 0 : CLK_IS_ROOT;
137
138 clkmain->hw.init = &init;
139 clkmain->rate = rate;
140 clkmain->pmc = pmc;
141 clkmain->irq = irq;
142 init_waitqueue_head(&clkmain->wait);
143 irq_set_status_flags(clkmain->irq, IRQ_NOAUTOEN);
144 ret = request_irq(clkmain->irq, clk_main_irq_handler,
145 IRQF_TRIGGER_HIGH, "clk-main", clkmain);
146 if (ret)
147 return ERR_PTR(ret);
148
149 clk = clk_register(NULL, &clkmain->hw);
150 if (IS_ERR(clk)) {
151 free_irq(clkmain->irq, clkmain);
152 kfree(clkmain);
153 }
154
155 return clk;
156}
157
158
159
160static void __init
161of_at91_clk_main_setup(struct device_node *np, struct at91_pmc *pmc)
162{
163 struct clk *clk;
164 unsigned int irq;
165 const char *parent_name;
166 const char *name = np->name;
167 u32 rate = 0;
168
169 parent_name = of_clk_get_parent_name(np, 0);
170 of_property_read_string(np, "clock-output-names", &name);
171 of_property_read_u32(np, "clock-frequency", &rate);
172 irq = irq_of_parse_and_map(np, 0);
173 if (!irq)
174 return;
175
176 clk = at91_clk_register_main(pmc, irq, name, parent_name, rate);
177 if (IS_ERR(clk))
178 return;
179
180 of_clk_add_provider(np, of_clk_src_simple_get, clk);
181}
182
183void __init of_at91rm9200_clk_main_setup(struct device_node *np,
184 struct at91_pmc *pmc)
185{
186 of_at91_clk_main_setup(np, pmc);
187}
diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
new file mode 100644
index 000000000000..bd313f7816a8
--- /dev/null
+++ b/drivers/clk/at91/clk-master.c
@@ -0,0 +1,270 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define MASTER_SOURCE_MAX 4
26
27#define MASTER_PRES_MASK 0x7
28#define MASTER_PRES_MAX MASTER_PRES_MASK
29#define MASTER_DIV_SHIFT 8
30#define MASTER_DIV_MASK 0x3
31
32struct clk_master_characteristics {
33 struct clk_range output;
34 u32 divisors[4];
35 u8 have_div3_pres;
36};
37
38struct clk_master_layout {
39 u32 mask;
40 u8 pres_shift;
41};
42
43#define to_clk_master(hw) container_of(hw, struct clk_master, hw)
44
45struct clk_master {
46 struct clk_hw hw;
47 struct at91_pmc *pmc;
48 unsigned int irq;
49 wait_queue_head_t wait;
50 const struct clk_master_layout *layout;
51 const struct clk_master_characteristics *characteristics;
52};
53
54static irqreturn_t clk_master_irq_handler(int irq, void *dev_id)
55{
56 struct clk_master *master = (struct clk_master *)dev_id;
57
58 wake_up(&master->wait);
59 disable_irq_nosync(master->irq);
60
61 return IRQ_HANDLED;
62}
63static int clk_master_prepare(struct clk_hw *hw)
64{
65 struct clk_master *master = to_clk_master(hw);
66 struct at91_pmc *pmc = master->pmc;
67
68 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY)) {
69 enable_irq(master->irq);
70 wait_event(master->wait,
71 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
72 }
73
74 return 0;
75}
76
77static int clk_master_is_prepared(struct clk_hw *hw)
78{
79 struct clk_master *master = to_clk_master(hw);
80
81 return !!(pmc_read(master->pmc, AT91_PMC_SR) & AT91_PMC_MCKRDY);
82}
83
84static unsigned long clk_master_recalc_rate(struct clk_hw *hw,
85 unsigned long parent_rate)
86{
87 u8 pres;
88 u8 div;
89 unsigned long rate = parent_rate;
90 struct clk_master *master = to_clk_master(hw);
91 struct at91_pmc *pmc = master->pmc;
92 const struct clk_master_layout *layout = master->layout;
93 const struct clk_master_characteristics *characteristics =
94 master->characteristics;
95 u32 tmp;
96
97 pmc_lock(pmc);
98 tmp = pmc_read(pmc, AT91_PMC_MCKR) & layout->mask;
99 pmc_unlock(pmc);
100
101 pres = (tmp >> layout->pres_shift) & MASTER_PRES_MASK;
102 div = (tmp >> MASTER_DIV_SHIFT) & MASTER_DIV_MASK;
103
104 if (characteristics->have_div3_pres && pres == MASTER_PRES_MAX)
105 rate /= 3;
106 else
107 rate >>= pres;
108
109 rate /= characteristics->divisors[div];
110
111 if (rate < characteristics->output.min)
112 pr_warn("master clk is underclocked");
113 else if (rate > characteristics->output.max)
114 pr_warn("master clk is overclocked");
115
116 return rate;
117}
118
119static u8 clk_master_get_parent(struct clk_hw *hw)
120{
121 struct clk_master *master = to_clk_master(hw);
122 struct at91_pmc *pmc = master->pmc;
123
124 return pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_CSS;
125}
126
127static const struct clk_ops master_ops = {
128 .prepare = clk_master_prepare,
129 .is_prepared = clk_master_is_prepared,
130 .recalc_rate = clk_master_recalc_rate,
131 .get_parent = clk_master_get_parent,
132};
133
134static struct clk * __init
135at91_clk_register_master(struct at91_pmc *pmc, unsigned int irq,
136 const char *name, int num_parents,
137 const char **parent_names,
138 const struct clk_master_layout *layout,
139 const struct clk_master_characteristics *characteristics)
140{
141 int ret;
142 struct clk_master *master;
143 struct clk *clk = NULL;
144 struct clk_init_data init;
145
146 if (!pmc || !irq || !name || !num_parents || !parent_names)
147 return ERR_PTR(-EINVAL);
148
149 master = kzalloc(sizeof(*master), GFP_KERNEL);
150 if (!master)
151 return ERR_PTR(-ENOMEM);
152
153 init.name = name;
154 init.ops = &master_ops;
155 init.parent_names = parent_names;
156 init.num_parents = num_parents;
157 init.flags = 0;
158
159 master->hw.init = &init;
160 master->layout = layout;
161 master->characteristics = characteristics;
162 master->pmc = pmc;
163 master->irq = irq;
164 init_waitqueue_head(&master->wait);
165 irq_set_status_flags(master->irq, IRQ_NOAUTOEN);
166 ret = request_irq(master->irq, clk_master_irq_handler,
167 IRQF_TRIGGER_HIGH, "clk-master", master);
168 if (ret)
169 return ERR_PTR(ret);
170
171 clk = clk_register(NULL, &master->hw);
172 if (IS_ERR(clk))
173 kfree(master);
174
175 return clk;
176}
177
178
179static const struct clk_master_layout at91rm9200_master_layout = {
180 .mask = 0x31F,
181 .pres_shift = 2,
182};
183
184static const struct clk_master_layout at91sam9x5_master_layout = {
185 .mask = 0x373,
186 .pres_shift = 4,
187};
188
189
190static struct clk_master_characteristics * __init
191of_at91_clk_master_get_characteristics(struct device_node *np)
192{
193 struct clk_master_characteristics *characteristics;
194
195 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
196 if (!characteristics)
197 return NULL;
198
199 if (of_at91_get_clk_range(np, "atmel,clk-output-range", &characteristics->output))
200 goto out_free_characteristics;
201
202 of_property_read_u32_array(np, "atmel,clk-divisors",
203 characteristics->divisors, 4);
204
205 characteristics->have_div3_pres =
206 of_property_read_bool(np, "atmel,master-clk-have-div3-pres");
207
208 return characteristics;
209
210out_free_characteristics:
211 kfree(characteristics);
212 return NULL;
213}
214
215static void __init
216of_at91_clk_master_setup(struct device_node *np, struct at91_pmc *pmc,
217 const struct clk_master_layout *layout)
218{
219 struct clk *clk;
220 int num_parents;
221 int i;
222 unsigned int irq;
223 const char *parent_names[MASTER_SOURCE_MAX];
224 const char *name = np->name;
225 struct clk_master_characteristics *characteristics;
226
227 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
228 if (num_parents <= 0 || num_parents > MASTER_SOURCE_MAX)
229 return;
230
231 for (i = 0; i < num_parents; ++i) {
232 parent_names[i] = of_clk_get_parent_name(np, i);
233 if (!parent_names[i])
234 return;
235 }
236
237 of_property_read_string(np, "clock-output-names", &name);
238
239 characteristics = of_at91_clk_master_get_characteristics(np);
240 if (!characteristics)
241 return;
242
243 irq = irq_of_parse_and_map(np, 0);
244 if (!irq)
245 return;
246
247 clk = at91_clk_register_master(pmc, irq, name, num_parents,
248 parent_names, layout,
249 characteristics);
250 if (IS_ERR(clk))
251 goto out_free_characteristics;
252
253 of_clk_add_provider(np, of_clk_src_simple_get, clk);
254 return;
255
256out_free_characteristics:
257 kfree(characteristics);
258}
259
260void __init of_at91rm9200_clk_master_setup(struct device_node *np,
261 struct at91_pmc *pmc)
262{
263 of_at91_clk_master_setup(np, pmc, &at91rm9200_master_layout);
264}
265
266void __init of_at91sam9x5_clk_master_setup(struct device_node *np,
267 struct at91_pmc *pmc)
268{
269 of_at91_clk_master_setup(np, pmc, &at91sam9x5_master_layout);
270}
diff --git a/drivers/clk/at91/clk-peripheral.c b/drivers/clk/at91/clk-peripheral.c
new file mode 100644
index 000000000000..597fed423d7d
--- /dev/null
+++ b/drivers/clk/at91/clk-peripheral.c
@@ -0,0 +1,410 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define PERIPHERAL_MAX 64
21
22#define PERIPHERAL_AT91RM9200 0
23#define PERIPHERAL_AT91SAM9X5 1
24
25#define PERIPHERAL_ID_MIN 2
26#define PERIPHERAL_ID_MAX 31
27#define PERIPHERAL_MASK(id) (1 << ((id) & PERIPHERAL_ID_MAX))
28
29#define PERIPHERAL_RSHIFT_MASK 0x3
30#define PERIPHERAL_RSHIFT(val) (((val) >> 16) & PERIPHERAL_RSHIFT_MASK)
31
32#define PERIPHERAL_MAX_SHIFT 4
33
34struct clk_peripheral {
35 struct clk_hw hw;
36 struct at91_pmc *pmc;
37 u32 id;
38};
39
40#define to_clk_peripheral(hw) container_of(hw, struct clk_peripheral, hw)
41
42struct clk_sam9x5_peripheral {
43 struct clk_hw hw;
44 struct at91_pmc *pmc;
45 struct clk_range range;
46 u32 id;
47 u32 div;
48 bool auto_div;
49};
50
51#define to_clk_sam9x5_peripheral(hw) \
52 container_of(hw, struct clk_sam9x5_peripheral, hw)
53
54static int clk_peripheral_enable(struct clk_hw *hw)
55{
56 struct clk_peripheral *periph = to_clk_peripheral(hw);
57 struct at91_pmc *pmc = periph->pmc;
58 int offset = AT91_PMC_PCER;
59 u32 id = periph->id;
60
61 if (id < PERIPHERAL_ID_MIN)
62 return 0;
63 if (id > PERIPHERAL_ID_MAX)
64 offset = AT91_PMC_PCER1;
65 pmc_write(pmc, offset, PERIPHERAL_MASK(id));
66 return 0;
67}
68
69static void clk_peripheral_disable(struct clk_hw *hw)
70{
71 struct clk_peripheral *periph = to_clk_peripheral(hw);
72 struct at91_pmc *pmc = periph->pmc;
73 int offset = AT91_PMC_PCDR;
74 u32 id = periph->id;
75
76 if (id < PERIPHERAL_ID_MIN)
77 return;
78 if (id > PERIPHERAL_ID_MAX)
79 offset = AT91_PMC_PCDR1;
80 pmc_write(pmc, offset, PERIPHERAL_MASK(id));
81}
82
83static int clk_peripheral_is_enabled(struct clk_hw *hw)
84{
85 struct clk_peripheral *periph = to_clk_peripheral(hw);
86 struct at91_pmc *pmc = periph->pmc;
87 int offset = AT91_PMC_PCSR;
88 u32 id = periph->id;
89
90 if (id < PERIPHERAL_ID_MIN)
91 return 1;
92 if (id > PERIPHERAL_ID_MAX)
93 offset = AT91_PMC_PCSR1;
94 return !!(pmc_read(pmc, offset) & PERIPHERAL_MASK(id));
95}
96
97static const struct clk_ops peripheral_ops = {
98 .enable = clk_peripheral_enable,
99 .disable = clk_peripheral_disable,
100 .is_enabled = clk_peripheral_is_enabled,
101};
102
103static struct clk * __init
104at91_clk_register_peripheral(struct at91_pmc *pmc, const char *name,
105 const char *parent_name, u32 id)
106{
107 struct clk_peripheral *periph;
108 struct clk *clk = NULL;
109 struct clk_init_data init;
110
111 if (!pmc || !name || !parent_name || id > PERIPHERAL_ID_MAX)
112 return ERR_PTR(-EINVAL);
113
114 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
115 if (!periph)
116 return ERR_PTR(-ENOMEM);
117
118 init.name = name;
119 init.ops = &peripheral_ops;
120 init.parent_names = (parent_name ? &parent_name : NULL);
121 init.num_parents = (parent_name ? 1 : 0);
122 init.flags = 0;
123
124 periph->id = id;
125 periph->hw.init = &init;
126 periph->pmc = pmc;
127
128 clk = clk_register(NULL, &periph->hw);
129 if (IS_ERR(clk))
130 kfree(periph);
131
132 return clk;
133}
134
135static void clk_sam9x5_peripheral_autodiv(struct clk_sam9x5_peripheral *periph)
136{
137 struct clk *parent;
138 unsigned long parent_rate;
139 int shift = 0;
140
141 if (!periph->auto_div)
142 return;
143
144 if (periph->range.max) {
145 parent = clk_get_parent_by_index(periph->hw.clk, 0);
146 parent_rate = __clk_get_rate(parent);
147 if (!parent_rate)
148 return;
149
150 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
151 if (parent_rate >> shift <= periph->range.max)
152 break;
153 }
154 }
155
156 periph->auto_div = false;
157 periph->div = shift;
158}
159
160static int clk_sam9x5_peripheral_enable(struct clk_hw *hw)
161{
162 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
163 struct at91_pmc *pmc = periph->pmc;
164
165 if (periph->id < PERIPHERAL_ID_MIN)
166 return 0;
167
168 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) |
169 AT91_PMC_PCR_CMD |
170 AT91_PMC_PCR_DIV(periph->div) |
171 AT91_PMC_PCR_EN);
172 return 0;
173}
174
175static void clk_sam9x5_peripheral_disable(struct clk_hw *hw)
176{
177 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
178 struct at91_pmc *pmc = periph->pmc;
179
180 if (periph->id < PERIPHERAL_ID_MIN)
181 return;
182
183 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID) |
184 AT91_PMC_PCR_CMD);
185}
186
187static int clk_sam9x5_peripheral_is_enabled(struct clk_hw *hw)
188{
189 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
190 struct at91_pmc *pmc = periph->pmc;
191 int ret;
192
193 if (periph->id < PERIPHERAL_ID_MIN)
194 return 1;
195
196 pmc_lock(pmc);
197 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID));
198 ret = !!(pmc_read(pmc, AT91_PMC_PCR) & AT91_PMC_PCR_EN);
199 pmc_unlock(pmc);
200
201 return ret;
202}
203
204static unsigned long
205clk_sam9x5_peripheral_recalc_rate(struct clk_hw *hw,
206 unsigned long parent_rate)
207{
208 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
209 struct at91_pmc *pmc = periph->pmc;
210 u32 tmp;
211
212 if (periph->id < PERIPHERAL_ID_MIN)
213 return parent_rate;
214
215 pmc_lock(pmc);
216 pmc_write(pmc, AT91_PMC_PCR, (periph->id & AT91_PMC_PCR_PID));
217 tmp = pmc_read(pmc, AT91_PMC_PCR);
218 pmc_unlock(pmc);
219
220 if (tmp & AT91_PMC_PCR_EN) {
221 periph->div = PERIPHERAL_RSHIFT(tmp);
222 periph->auto_div = false;
223 } else {
224 clk_sam9x5_peripheral_autodiv(periph);
225 }
226
227 return parent_rate >> periph->div;
228}
229
230static long clk_sam9x5_peripheral_round_rate(struct clk_hw *hw,
231 unsigned long rate,
232 unsigned long *parent_rate)
233{
234 int shift = 0;
235 unsigned long best_rate;
236 unsigned long best_diff;
237 unsigned long cur_rate = *parent_rate;
238 unsigned long cur_diff;
239 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
240
241 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max)
242 return *parent_rate;
243
244 if (periph->range.max) {
245 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
246 cur_rate = *parent_rate >> shift;
247 if (cur_rate <= periph->range.max)
248 break;
249 }
250 }
251
252 if (rate >= cur_rate)
253 return cur_rate;
254
255 best_diff = cur_rate - rate;
256 best_rate = cur_rate;
257 for (; shift < PERIPHERAL_MAX_SHIFT; shift++) {
258 cur_rate = *parent_rate >> shift;
259 if (cur_rate < rate)
260 cur_diff = rate - cur_rate;
261 else
262 cur_diff = cur_rate - rate;
263
264 if (cur_diff < best_diff) {
265 best_diff = cur_diff;
266 best_rate = cur_rate;
267 }
268
269 if (!best_diff || cur_rate < rate)
270 break;
271 }
272
273 return best_rate;
274}
275
276static int clk_sam9x5_peripheral_set_rate(struct clk_hw *hw,
277 unsigned long rate,
278 unsigned long parent_rate)
279{
280 int shift;
281 struct clk_sam9x5_peripheral *periph = to_clk_sam9x5_peripheral(hw);
282 if (periph->id < PERIPHERAL_ID_MIN || !periph->range.max) {
283 if (parent_rate == rate)
284 return 0;
285 else
286 return -EINVAL;
287 }
288
289 if (periph->range.max && rate > periph->range.max)
290 return -EINVAL;
291
292 for (shift = 0; shift < PERIPHERAL_MAX_SHIFT; shift++) {
293 if (parent_rate >> shift == rate) {
294 periph->auto_div = false;
295 periph->div = shift;
296 return 0;
297 }
298 }
299
300 return -EINVAL;
301}
302
303static const struct clk_ops sam9x5_peripheral_ops = {
304 .enable = clk_sam9x5_peripheral_enable,
305 .disable = clk_sam9x5_peripheral_disable,
306 .is_enabled = clk_sam9x5_peripheral_is_enabled,
307 .recalc_rate = clk_sam9x5_peripheral_recalc_rate,
308 .round_rate = clk_sam9x5_peripheral_round_rate,
309 .set_rate = clk_sam9x5_peripheral_set_rate,
310};
311
312static struct clk * __init
313at91_clk_register_sam9x5_peripheral(struct at91_pmc *pmc, const char *name,
314 const char *parent_name, u32 id,
315 const struct clk_range *range)
316{
317 struct clk_sam9x5_peripheral *periph;
318 struct clk *clk = NULL;
319 struct clk_init_data init;
320
321 if (!pmc || !name || !parent_name)
322 return ERR_PTR(-EINVAL);
323
324 periph = kzalloc(sizeof(*periph), GFP_KERNEL);
325 if (!periph)
326 return ERR_PTR(-ENOMEM);
327
328 init.name = name;
329 init.ops = &sam9x5_peripheral_ops;
330 init.parent_names = (parent_name ? &parent_name : NULL);
331 init.num_parents = (parent_name ? 1 : 0);
332 init.flags = 0;
333
334 periph->id = id;
335 periph->hw.init = &init;
336 periph->div = 0;
337 periph->pmc = pmc;
338 periph->auto_div = true;
339 periph->range = *range;
340
341 clk = clk_register(NULL, &periph->hw);
342 if (IS_ERR(clk))
343 kfree(periph);
344 else
345 clk_sam9x5_peripheral_autodiv(periph);
346
347 return clk;
348}
349
350static void __init
351of_at91_clk_periph_setup(struct device_node *np, struct at91_pmc *pmc, u8 type)
352{
353 int num;
354 u32 id;
355 struct clk *clk;
356 const char *parent_name;
357 const char *name;
358 struct device_node *periphclknp;
359
360 parent_name = of_clk_get_parent_name(np, 0);
361 if (!parent_name)
362 return;
363
364 num = of_get_child_count(np);
365 if (!num || num > PERIPHERAL_MAX)
366 return;
367
368 for_each_child_of_node(np, periphclknp) {
369 if (of_property_read_u32(periphclknp, "reg", &id))
370 continue;
371
372 if (id >= PERIPHERAL_MAX)
373 continue;
374
375 if (of_property_read_string(np, "clock-output-names", &name))
376 name = periphclknp->name;
377
378 if (type == PERIPHERAL_AT91RM9200) {
379 clk = at91_clk_register_peripheral(pmc, name,
380 parent_name, id);
381 } else {
382 struct clk_range range = CLK_RANGE(0, 0);
383
384 of_at91_get_clk_range(periphclknp,
385 "atmel,clk-output-range",
386 &range);
387
388 clk = at91_clk_register_sam9x5_peripheral(pmc, name,
389 parent_name,
390 id, &range);
391 }
392
393 if (IS_ERR(clk))
394 continue;
395
396 of_clk_add_provider(periphclknp, of_clk_src_simple_get, clk);
397 }
398}
399
400void __init of_at91rm9200_clk_periph_setup(struct device_node *np,
401 struct at91_pmc *pmc)
402{
403 of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91RM9200);
404}
405
406void __init of_at91sam9x5_clk_periph_setup(struct device_node *np,
407 struct at91_pmc *pmc)
408{
409 of_at91_clk_periph_setup(np, pmc, PERIPHERAL_AT91SAM9X5);
410}
diff --git a/drivers/clk/at91/clk-pll.c b/drivers/clk/at91/clk-pll.c
new file mode 100644
index 000000000000..cf6ed023504c
--- /dev/null
+++ b/drivers/clk/at91/clk-pll.c
@@ -0,0 +1,531 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define PLL_STATUS_MASK(id) (1 << (1 + (id)))
26#define PLL_REG(id) (AT91_CKGR_PLLAR + ((id) * 4))
27#define PLL_DIV_MASK 0xff
28#define PLL_DIV_MAX PLL_DIV_MASK
29#define PLL_DIV(reg) ((reg) & PLL_DIV_MASK)
30#define PLL_MUL(reg, layout) (((reg) >> (layout)->mul_shift) & \
31 (layout)->mul_mask)
32#define PLL_ICPR_SHIFT(id) ((id) * 16)
33#define PLL_ICPR_MASK(id) (0xffff << PLL_ICPR_SHIFT(id))
34#define PLL_MAX_COUNT 0x3ff
35#define PLL_COUNT_SHIFT 8
36#define PLL_OUT_SHIFT 14
37#define PLL_MAX_ID 1
38
39struct clk_pll_characteristics {
40 struct clk_range input;
41 int num_output;
42 struct clk_range *output;
43 u16 *icpll;
44 u8 *out;
45};
46
47struct clk_pll_layout {
48 u32 pllr_mask;
49 u16 mul_mask;
50 u8 mul_shift;
51};
52
53#define to_clk_pll(hw) container_of(hw, struct clk_pll, hw)
54
55struct clk_pll {
56 struct clk_hw hw;
57 struct at91_pmc *pmc;
58 unsigned int irq;
59 wait_queue_head_t wait;
60 u8 id;
61 u8 div;
62 u8 range;
63 u16 mul;
64 const struct clk_pll_layout *layout;
65 const struct clk_pll_characteristics *characteristics;
66};
67
68static irqreturn_t clk_pll_irq_handler(int irq, void *dev_id)
69{
70 struct clk_pll *pll = (struct clk_pll *)dev_id;
71
72 wake_up(&pll->wait);
73 disable_irq_nosync(pll->irq);
74
75 return IRQ_HANDLED;
76}
77
78static int clk_pll_prepare(struct clk_hw *hw)
79{
80 struct clk_pll *pll = to_clk_pll(hw);
81 struct at91_pmc *pmc = pll->pmc;
82 const struct clk_pll_layout *layout = pll->layout;
83 const struct clk_pll_characteristics *characteristics =
84 pll->characteristics;
85 u8 id = pll->id;
86 u32 mask = PLL_STATUS_MASK(id);
87 int offset = PLL_REG(id);
88 u8 out = 0;
89 u32 pllr, icpr;
90 u8 div;
91 u16 mul;
92
93 pllr = pmc_read(pmc, offset);
94 div = PLL_DIV(pllr);
95 mul = PLL_MUL(pllr, layout);
96
97 if ((pmc_read(pmc, AT91_PMC_SR) & mask) &&
98 (div == pll->div && mul == pll->mul))
99 return 0;
100
101 if (characteristics->out)
102 out = characteristics->out[pll->range];
103 if (characteristics->icpll) {
104 icpr = pmc_read(pmc, AT91_PMC_PLLICPR) & ~PLL_ICPR_MASK(id);
105 icpr |= (characteristics->icpll[pll->range] <<
106 PLL_ICPR_SHIFT(id));
107 pmc_write(pmc, AT91_PMC_PLLICPR, icpr);
108 }
109
110 pllr &= ~layout->pllr_mask;
111 pllr |= layout->pllr_mask &
112 (pll->div | (PLL_MAX_COUNT << PLL_COUNT_SHIFT) |
113 (out << PLL_OUT_SHIFT) |
114 ((pll->mul & layout->mul_mask) << layout->mul_shift));
115 pmc_write(pmc, offset, pllr);
116
117 while (!(pmc_read(pmc, AT91_PMC_SR) & mask)) {
118 enable_irq(pll->irq);
119 wait_event(pll->wait,
120 pmc_read(pmc, AT91_PMC_SR) & mask);
121 }
122
123 return 0;
124}
125
126static int clk_pll_is_prepared(struct clk_hw *hw)
127{
128 struct clk_pll *pll = to_clk_pll(hw);
129 struct at91_pmc *pmc = pll->pmc;
130
131 return !!(pmc_read(pmc, AT91_PMC_SR) &
132 PLL_STATUS_MASK(pll->id));
133}
134
135static void clk_pll_unprepare(struct clk_hw *hw)
136{
137 struct clk_pll *pll = to_clk_pll(hw);
138 struct at91_pmc *pmc = pll->pmc;
139 const struct clk_pll_layout *layout = pll->layout;
140 int offset = PLL_REG(pll->id);
141 u32 tmp = pmc_read(pmc, offset) & ~(layout->pllr_mask);
142
143 pmc_write(pmc, offset, tmp);
144}
145
146static unsigned long clk_pll_recalc_rate(struct clk_hw *hw,
147 unsigned long parent_rate)
148{
149 struct clk_pll *pll = to_clk_pll(hw);
150 const struct clk_pll_layout *layout = pll->layout;
151 struct at91_pmc *pmc = pll->pmc;
152 int offset = PLL_REG(pll->id);
153 u32 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
154 u8 div = PLL_DIV(tmp);
155 u16 mul = PLL_MUL(tmp, layout);
156 if (!div || !mul)
157 return 0;
158
159 return (parent_rate * (mul + 1)) / div;
160}
161
162static long clk_pll_get_best_div_mul(struct clk_pll *pll, unsigned long rate,
163 unsigned long parent_rate,
164 u32 *div, u32 *mul,
165 u32 *index) {
166 unsigned long maxrate;
167 unsigned long minrate;
168 unsigned long divrate;
169 unsigned long bestdiv = 1;
170 unsigned long bestmul;
171 unsigned long tmpdiv;
172 unsigned long roundup;
173 unsigned long rounddown;
174 unsigned long remainder;
175 unsigned long bestremainder;
176 unsigned long maxmul;
177 unsigned long maxdiv;
178 unsigned long mindiv;
179 int i = 0;
180 const struct clk_pll_layout *layout = pll->layout;
181 const struct clk_pll_characteristics *characteristics =
182 pll->characteristics;
183
184 /* Minimum divider = 1 */
185 /* Maximum multiplier = max_mul */
186 maxmul = layout->mul_mask + 1;
187 maxrate = (parent_rate * maxmul) / 1;
188
189 /* Maximum divider = max_div */
190 /* Minimum multiplier = 2 */
191 maxdiv = PLL_DIV_MAX;
192 minrate = (parent_rate * 2) / maxdiv;
193
194 if (parent_rate < characteristics->input.min ||
195 parent_rate < characteristics->input.max)
196 return -ERANGE;
197
198 if (parent_rate < minrate || parent_rate > maxrate)
199 return -ERANGE;
200
201 for (i = 0; i < characteristics->num_output; i++) {
202 if (parent_rate >= characteristics->output[i].min &&
203 parent_rate <= characteristics->output[i].max)
204 break;
205 }
206
207 if (i >= characteristics->num_output)
208 return -ERANGE;
209
210 bestmul = rate / parent_rate;
211 rounddown = parent_rate % rate;
212 roundup = rate - rounddown;
213 bestremainder = roundup < rounddown ? roundup : rounddown;
214
215 if (!bestremainder) {
216 if (div)
217 *div = bestdiv;
218 if (mul)
219 *mul = bestmul;
220 if (index)
221 *index = i;
222 return rate;
223 }
224
225 maxdiv = 255 / (bestmul + 1);
226 if (parent_rate / maxdiv < characteristics->input.min)
227 maxdiv = parent_rate / characteristics->input.min;
228 mindiv = parent_rate / characteristics->input.max;
229 if (parent_rate % characteristics->input.max)
230 mindiv++;
231
232 for (tmpdiv = mindiv; tmpdiv < maxdiv; tmpdiv++) {
233 divrate = parent_rate / tmpdiv;
234
235 rounddown = rate % divrate;
236 roundup = divrate - rounddown;
237 remainder = roundup < rounddown ? roundup : rounddown;
238
239 if (remainder < bestremainder) {
240 bestremainder = remainder;
241 bestmul = rate / divrate;
242 bestdiv = tmpdiv;
243 }
244
245 if (!remainder)
246 break;
247 }
248
249 rate = (parent_rate / bestdiv) * bestmul;
250
251 if (div)
252 *div = bestdiv;
253 if (mul)
254 *mul = bestmul;
255 if (index)
256 *index = i;
257
258 return rate;
259}
260
261static long clk_pll_round_rate(struct clk_hw *hw, unsigned long rate,
262 unsigned long *parent_rate)
263{
264 struct clk_pll *pll = to_clk_pll(hw);
265
266 return clk_pll_get_best_div_mul(pll, rate, *parent_rate,
267 NULL, NULL, NULL);
268}
269
270static int clk_pll_set_rate(struct clk_hw *hw, unsigned long rate,
271 unsigned long parent_rate)
272{
273 struct clk_pll *pll = to_clk_pll(hw);
274 long ret;
275 u32 div;
276 u32 mul;
277 u32 index;
278
279 ret = clk_pll_get_best_div_mul(pll, rate, parent_rate,
280 &div, &mul, &index);
281 if (ret < 0)
282 return ret;
283
284 pll->range = index;
285 pll->div = div;
286 pll->mul = mul;
287
288 return 0;
289}
290
291static const struct clk_ops pll_ops = {
292 .prepare = clk_pll_prepare,
293 .unprepare = clk_pll_unprepare,
294 .is_prepared = clk_pll_is_prepared,
295 .recalc_rate = clk_pll_recalc_rate,
296 .round_rate = clk_pll_round_rate,
297 .set_rate = clk_pll_set_rate,
298};
299
300static struct clk * __init
301at91_clk_register_pll(struct at91_pmc *pmc, unsigned int irq, const char *name,
302 const char *parent_name, u8 id,
303 const struct clk_pll_layout *layout,
304 const struct clk_pll_characteristics *characteristics)
305{
306 struct clk_pll *pll;
307 struct clk *clk = NULL;
308 struct clk_init_data init;
309 int ret;
310 int offset = PLL_REG(id);
311 u32 tmp;
312
313 if (id > PLL_MAX_ID)
314 return ERR_PTR(-EINVAL);
315
316 pll = kzalloc(sizeof(*pll), GFP_KERNEL);
317 if (!pll)
318 return ERR_PTR(-ENOMEM);
319
320 init.name = name;
321 init.ops = &pll_ops;
322 init.parent_names = &parent_name;
323 init.num_parents = 1;
324 init.flags = CLK_SET_RATE_GATE;
325
326 pll->id = id;
327 pll->hw.init = &init;
328 pll->layout = layout;
329 pll->characteristics = characteristics;
330 pll->pmc = pmc;
331 pll->irq = irq;
332 tmp = pmc_read(pmc, offset) & layout->pllr_mask;
333 pll->div = PLL_DIV(tmp);
334 pll->mul = PLL_MUL(tmp, layout);
335 init_waitqueue_head(&pll->wait);
336 irq_set_status_flags(pll->irq, IRQ_NOAUTOEN);
337 ret = request_irq(pll->irq, clk_pll_irq_handler, IRQF_TRIGGER_HIGH,
338 id ? "clk-pllb" : "clk-plla", pll);
339 if (ret)
340 return ERR_PTR(ret);
341
342 clk = clk_register(NULL, &pll->hw);
343 if (IS_ERR(clk))
344 kfree(pll);
345
346 return clk;
347}
348
349
350static const struct clk_pll_layout at91rm9200_pll_layout = {
351 .pllr_mask = 0x7FFFFFF,
352 .mul_shift = 16,
353 .mul_mask = 0x7FF,
354};
355
356static const struct clk_pll_layout at91sam9g45_pll_layout = {
357 .pllr_mask = 0xFFFFFF,
358 .mul_shift = 16,
359 .mul_mask = 0xFF,
360};
361
362static const struct clk_pll_layout at91sam9g20_pllb_layout = {
363 .pllr_mask = 0x3FFFFF,
364 .mul_shift = 16,
365 .mul_mask = 0x3F,
366};
367
368static const struct clk_pll_layout sama5d3_pll_layout = {
369 .pllr_mask = 0x1FFFFFF,
370 .mul_shift = 18,
371 .mul_mask = 0x7F,
372};
373
374
375static struct clk_pll_characteristics * __init
376of_at91_clk_pll_get_characteristics(struct device_node *np)
377{
378 int i;
379 int offset;
380 u32 tmp;
381 int num_output;
382 u32 num_cells;
383 struct clk_range input;
384 struct clk_range *output;
385 u8 *out = NULL;
386 u16 *icpll = NULL;
387 struct clk_pll_characteristics *characteristics;
388
389 if (of_at91_get_clk_range(np, "atmel,clk-input-range", &input))
390 return NULL;
391
392 if (of_property_read_u32(np, "#atmel,pll-clk-output-range-cells",
393 &num_cells))
394 return NULL;
395
396 if (num_cells < 2 || num_cells > 4)
397 return NULL;
398
399 if (!of_get_property(np, "atmel,pll-clk-output-ranges", &tmp))
400 return NULL;
401 num_output = tmp / (sizeof(u32) * num_cells);
402
403 characteristics = kzalloc(sizeof(*characteristics), GFP_KERNEL);
404 if (!characteristics)
405 return NULL;
406
407 output = kzalloc(sizeof(*output) * num_output, GFP_KERNEL);
408 if (!output)
409 goto out_free_characteristics;
410
411 if (num_cells > 2) {
412 out = kzalloc(sizeof(*out) * num_output, GFP_KERNEL);
413 if (!out)
414 goto out_free_output;
415 }
416
417 if (num_cells > 3) {
418 icpll = kzalloc(sizeof(*icpll) * num_output, GFP_KERNEL);
419 if (!icpll)
420 goto out_free_output;
421 }
422
423 for (i = 0; i < num_output; i++) {
424 offset = i * num_cells;
425 if (of_property_read_u32_index(np,
426 "atmel,pll-clk-output-ranges",
427 offset, &tmp))
428 goto out_free_output;
429 output[i].min = tmp;
430 if (of_property_read_u32_index(np,
431 "atmel,pll-clk-output-ranges",
432 offset + 1, &tmp))
433 goto out_free_output;
434 output[i].max = tmp;
435
436 if (num_cells == 2)
437 continue;
438
439 if (of_property_read_u32_index(np,
440 "atmel,pll-clk-output-ranges",
441 offset + 2, &tmp))
442 goto out_free_output;
443 out[i] = tmp;
444
445 if (num_cells == 3)
446 continue;
447
448 if (of_property_read_u32_index(np,
449 "atmel,pll-clk-output-ranges",
450 offset + 3, &tmp))
451 goto out_free_output;
452 icpll[i] = tmp;
453 }
454
455 characteristics->input = input;
456 characteristics->num_output = num_output;
457 characteristics->output = output;
458 characteristics->out = out;
459 characteristics->icpll = icpll;
460 return characteristics;
461
462out_free_output:
463 kfree(icpll);
464 kfree(out);
465 kfree(output);
466out_free_characteristics:
467 kfree(characteristics);
468 return NULL;
469}
470
471static void __init
472of_at91_clk_pll_setup(struct device_node *np, struct at91_pmc *pmc,
473 const struct clk_pll_layout *layout)
474{
475 u32 id;
476 unsigned int irq;
477 struct clk *clk;
478 const char *parent_name;
479 const char *name = np->name;
480 struct clk_pll_characteristics *characteristics;
481
482 if (of_property_read_u32(np, "reg", &id))
483 return;
484
485 parent_name = of_clk_get_parent_name(np, 0);
486
487 of_property_read_string(np, "clock-output-names", &name);
488
489 characteristics = of_at91_clk_pll_get_characteristics(np);
490 if (!characteristics)
491 return;
492
493 irq = irq_of_parse_and_map(np, 0);
494 if (!irq)
495 return;
496
497 clk = at91_clk_register_pll(pmc, irq, name, parent_name, id, layout,
498 characteristics);
499 if (IS_ERR(clk))
500 goto out_free_characteristics;
501
502 of_clk_add_provider(np, of_clk_src_simple_get, clk);
503 return;
504
505out_free_characteristics:
506 kfree(characteristics);
507}
508
509void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
510 struct at91_pmc *pmc)
511{
512 of_at91_clk_pll_setup(np, pmc, &at91rm9200_pll_layout);
513}
514
515void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
516 struct at91_pmc *pmc)
517{
518 of_at91_clk_pll_setup(np, pmc, &at91sam9g45_pll_layout);
519}
520
521void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
522 struct at91_pmc *pmc)
523{
524 of_at91_clk_pll_setup(np, pmc, &at91sam9g20_pllb_layout);
525}
526
527void __init of_sama5d3_clk_pll_setup(struct device_node *np,
528 struct at91_pmc *pmc)
529{
530 of_at91_clk_pll_setup(np, pmc, &sama5d3_pll_layout);
531}
diff --git a/drivers/clk/at91/clk-plldiv.c b/drivers/clk/at91/clk-plldiv.c
new file mode 100644
index 000000000000..ea226562bb40
--- /dev/null
+++ b/drivers/clk/at91/clk-plldiv.c
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define to_clk_plldiv(hw) container_of(hw, struct clk_plldiv, hw)
21
22struct clk_plldiv {
23 struct clk_hw hw;
24 struct at91_pmc *pmc;
25};
26
27static unsigned long clk_plldiv_recalc_rate(struct clk_hw *hw,
28 unsigned long parent_rate)
29{
30 struct clk_plldiv *plldiv = to_clk_plldiv(hw);
31 struct at91_pmc *pmc = plldiv->pmc;
32
33 if (pmc_read(pmc, AT91_PMC_MCKR) & AT91_PMC_PLLADIV2)
34 return parent_rate / 2;
35
36 return parent_rate;
37}
38
39static long clk_plldiv_round_rate(struct clk_hw *hw, unsigned long rate,
40 unsigned long *parent_rate)
41{
42 unsigned long div;
43
44 if (rate > *parent_rate)
45 return *parent_rate;
46 div = *parent_rate / 2;
47 if (rate < div)
48 return div;
49
50 if (rate - div < *parent_rate - rate)
51 return div;
52
53 return *parent_rate;
54}
55
56static int clk_plldiv_set_rate(struct clk_hw *hw, unsigned long rate,
57 unsigned long parent_rate)
58{
59 struct clk_plldiv *plldiv = to_clk_plldiv(hw);
60 struct at91_pmc *pmc = plldiv->pmc;
61 u32 tmp;
62
63 if (parent_rate != rate && (parent_rate / 2) != rate)
64 return -EINVAL;
65
66 pmc_lock(pmc);
67 tmp = pmc_read(pmc, AT91_PMC_MCKR) & ~AT91_PMC_PLLADIV2;
68 if ((parent_rate / 2) == rate)
69 tmp |= AT91_PMC_PLLADIV2;
70 pmc_write(pmc, AT91_PMC_MCKR, tmp);
71 pmc_unlock(pmc);
72
73 return 0;
74}
75
76static const struct clk_ops plldiv_ops = {
77 .recalc_rate = clk_plldiv_recalc_rate,
78 .round_rate = clk_plldiv_round_rate,
79 .set_rate = clk_plldiv_set_rate,
80};
81
82static struct clk * __init
83at91_clk_register_plldiv(struct at91_pmc *pmc, const char *name,
84 const char *parent_name)
85{
86 struct clk_plldiv *plldiv;
87 struct clk *clk = NULL;
88 struct clk_init_data init;
89
90 plldiv = kzalloc(sizeof(*plldiv), GFP_KERNEL);
91 if (!plldiv)
92 return ERR_PTR(-ENOMEM);
93
94 init.name = name;
95 init.ops = &plldiv_ops;
96 init.parent_names = parent_name ? &parent_name : NULL;
97 init.num_parents = parent_name ? 1 : 0;
98 init.flags = CLK_SET_RATE_GATE;
99
100 plldiv->hw.init = &init;
101 plldiv->pmc = pmc;
102
103 clk = clk_register(NULL, &plldiv->hw);
104
105 if (IS_ERR(clk))
106 kfree(plldiv);
107
108 return clk;
109}
110
111static void __init
112of_at91_clk_plldiv_setup(struct device_node *np, struct at91_pmc *pmc)
113{
114 struct clk *clk;
115 const char *parent_name;
116 const char *name = np->name;
117
118 parent_name = of_clk_get_parent_name(np, 0);
119
120 of_property_read_string(np, "clock-output-names", &name);
121
122 clk = at91_clk_register_plldiv(pmc, name, parent_name);
123
124 if (IS_ERR(clk))
125 return;
126
127 of_clk_add_provider(np, of_clk_src_simple_get, clk);
128 return;
129}
130
131void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np,
132 struct at91_pmc *pmc)
133{
134 of_at91_clk_plldiv_setup(np, pmc);
135}
diff --git a/drivers/clk/at91/clk-programmable.c b/drivers/clk/at91/clk-programmable.c
new file mode 100644
index 000000000000..fd792b203eaf
--- /dev/null
+++ b/drivers/clk/at91/clk-programmable.c
@@ -0,0 +1,366 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17#include <linux/io.h>
18#include <linux/wait.h>
19#include <linux/sched.h>
20#include <linux/interrupt.h>
21#include <linux/irq.h>
22
23#include "pmc.h"
24
25#define PROG_SOURCE_MAX 5
26#define PROG_ID_MAX 7
27
28#define PROG_STATUS_MASK(id) (1 << ((id) + 8))
29#define PROG_PRES_MASK 0x7
30#define PROG_MAX_RM9200_CSS 3
31
32struct clk_programmable_layout {
33 u8 pres_shift;
34 u8 css_mask;
35 u8 have_slck_mck;
36};
37
38struct clk_programmable {
39 struct clk_hw hw;
40 struct at91_pmc *pmc;
41 unsigned int irq;
42 wait_queue_head_t wait;
43 u8 id;
44 u8 css;
45 u8 pres;
46 u8 slckmck;
47 const struct clk_programmable_layout *layout;
48};
49
50#define to_clk_programmable(hw) container_of(hw, struct clk_programmable, hw)
51
52
53static irqreturn_t clk_programmable_irq_handler(int irq, void *dev_id)
54{
55 struct clk_programmable *prog = (struct clk_programmable *)dev_id;
56
57 wake_up(&prog->wait);
58
59 return IRQ_HANDLED;
60}
61
62static int clk_programmable_prepare(struct clk_hw *hw)
63{
64 u32 tmp;
65 struct clk_programmable *prog = to_clk_programmable(hw);
66 struct at91_pmc *pmc = prog->pmc;
67 const struct clk_programmable_layout *layout = prog->layout;
68 u8 id = prog->id;
69 u32 mask = PROG_STATUS_MASK(id);
70
71 tmp = prog->css | (prog->pres << layout->pres_shift);
72 if (layout->have_slck_mck && prog->slckmck)
73 tmp |= AT91_PMC_CSSMCK_MCK;
74
75 pmc_write(pmc, AT91_PMC_PCKR(id), tmp);
76
77 while (!(pmc_read(pmc, AT91_PMC_SR) & mask))
78 wait_event(prog->wait, pmc_read(pmc, AT91_PMC_SR) & mask);
79
80 return 0;
81}
82
83static int clk_programmable_is_ready(struct clk_hw *hw)
84{
85 struct clk_programmable *prog = to_clk_programmable(hw);
86 struct at91_pmc *pmc = prog->pmc;
87
88 return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_PCKR(prog->id));
89}
90
91static unsigned long clk_programmable_recalc_rate(struct clk_hw *hw,
92 unsigned long parent_rate)
93{
94 u32 tmp;
95 struct clk_programmable *prog = to_clk_programmable(hw);
96 struct at91_pmc *pmc = prog->pmc;
97 const struct clk_programmable_layout *layout = prog->layout;
98
99 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id));
100 prog->pres = (tmp >> layout->pres_shift) & PROG_PRES_MASK;
101
102 return parent_rate >> prog->pres;
103}
104
105static long clk_programmable_round_rate(struct clk_hw *hw, unsigned long rate,
106 unsigned long *parent_rate)
107{
108 unsigned long best_rate = *parent_rate;
109 unsigned long best_diff;
110 unsigned long new_diff;
111 unsigned long cur_rate;
112 int shift = shift;
113
114 if (rate > *parent_rate)
115 return *parent_rate;
116 else
117 best_diff = *parent_rate - rate;
118
119 if (!best_diff)
120 return best_rate;
121
122 for (shift = 1; shift < PROG_PRES_MASK; shift++) {
123 cur_rate = *parent_rate >> shift;
124
125 if (cur_rate > rate)
126 new_diff = cur_rate - rate;
127 else
128 new_diff = rate - cur_rate;
129
130 if (!new_diff)
131 return cur_rate;
132
133 if (new_diff < best_diff) {
134 best_diff = new_diff;
135 best_rate = cur_rate;
136 }
137
138 if (rate > cur_rate)
139 break;
140 }
141
142 return best_rate;
143}
144
145static int clk_programmable_set_parent(struct clk_hw *hw, u8 index)
146{
147 struct clk_programmable *prog = to_clk_programmable(hw);
148 const struct clk_programmable_layout *layout = prog->layout;
149 if (index > layout->css_mask) {
150 if (index > PROG_MAX_RM9200_CSS && layout->have_slck_mck) {
151 prog->css = 0;
152 prog->slckmck = 1;
153 return 0;
154 } else {
155 return -EINVAL;
156 }
157 }
158
159 prog->css = index;
160 return 0;
161}
162
163static u8 clk_programmable_get_parent(struct clk_hw *hw)
164{
165 u32 tmp;
166 u8 ret;
167 struct clk_programmable *prog = to_clk_programmable(hw);
168 struct at91_pmc *pmc = prog->pmc;
169 const struct clk_programmable_layout *layout = prog->layout;
170
171 tmp = pmc_read(pmc, AT91_PMC_PCKR(prog->id));
172 prog->css = tmp & layout->css_mask;
173 ret = prog->css;
174 if (layout->have_slck_mck) {
175 prog->slckmck = !!(tmp & AT91_PMC_CSSMCK_MCK);
176 if (prog->slckmck && !ret)
177 ret = PROG_MAX_RM9200_CSS + 1;
178 }
179
180 return ret;
181}
182
183static int clk_programmable_set_rate(struct clk_hw *hw, unsigned long rate,
184 unsigned long parent_rate)
185{
186 struct clk_programmable *prog = to_clk_programmable(hw);
187 unsigned long best_rate = parent_rate;
188 unsigned long best_diff;
189 unsigned long new_diff;
190 unsigned long cur_rate;
191 int shift = 0;
192
193 if (rate > parent_rate)
194 return parent_rate;
195 else
196 best_diff = parent_rate - rate;
197
198 if (!best_diff) {
199 prog->pres = shift;
200 return 0;
201 }
202
203 for (shift = 1; shift < PROG_PRES_MASK; shift++) {
204 cur_rate = parent_rate >> shift;
205
206 if (cur_rate > rate)
207 new_diff = cur_rate - rate;
208 else
209 new_diff = rate - cur_rate;
210
211 if (!new_diff)
212 break;
213
214 if (new_diff < best_diff) {
215 best_diff = new_diff;
216 best_rate = cur_rate;
217 }
218
219 if (rate > cur_rate)
220 break;
221 }
222
223 prog->pres = shift;
224 return 0;
225}
226
227static const struct clk_ops programmable_ops = {
228 .prepare = clk_programmable_prepare,
229 .is_prepared = clk_programmable_is_ready,
230 .recalc_rate = clk_programmable_recalc_rate,
231 .round_rate = clk_programmable_round_rate,
232 .get_parent = clk_programmable_get_parent,
233 .set_parent = clk_programmable_set_parent,
234 .set_rate = clk_programmable_set_rate,
235};
236
237static struct clk * __init
238at91_clk_register_programmable(struct at91_pmc *pmc, unsigned int irq,
239 const char *name, const char **parent_names,
240 u8 num_parents, u8 id,
241 const struct clk_programmable_layout *layout)
242{
243 int ret;
244 struct clk_programmable *prog;
245 struct clk *clk = NULL;
246 struct clk_init_data init;
247 char irq_name[11];
248
249 if (id > PROG_ID_MAX)
250 return ERR_PTR(-EINVAL);
251
252 prog = kzalloc(sizeof(*prog), GFP_KERNEL);
253 if (!prog)
254 return ERR_PTR(-ENOMEM);
255
256 init.name = name;
257 init.ops = &programmable_ops;
258 init.parent_names = parent_names;
259 init.num_parents = num_parents;
260 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
261
262 prog->id = id;
263 prog->layout = layout;
264 prog->hw.init = &init;
265 prog->pmc = pmc;
266 prog->irq = irq;
267 init_waitqueue_head(&prog->wait);
268 irq_set_status_flags(prog->irq, IRQ_NOAUTOEN);
269 snprintf(irq_name, sizeof(irq_name), "clk-prog%d", id);
270 ret = request_irq(prog->irq, clk_programmable_irq_handler,
271 IRQF_TRIGGER_HIGH, irq_name, prog);
272 if (ret)
273 return ERR_PTR(ret);
274
275 clk = clk_register(NULL, &prog->hw);
276 if (IS_ERR(clk))
277 kfree(prog);
278
279 return clk;
280}
281
282static const struct clk_programmable_layout at91rm9200_programmable_layout = {
283 .pres_shift = 2,
284 .css_mask = 0x3,
285 .have_slck_mck = 0,
286};
287
288static const struct clk_programmable_layout at91sam9g45_programmable_layout = {
289 .pres_shift = 2,
290 .css_mask = 0x3,
291 .have_slck_mck = 1,
292};
293
294static const struct clk_programmable_layout at91sam9x5_programmable_layout = {
295 .pres_shift = 4,
296 .css_mask = 0x7,
297 .have_slck_mck = 0,
298};
299
300static void __init
301of_at91_clk_prog_setup(struct device_node *np, struct at91_pmc *pmc,
302 const struct clk_programmable_layout *layout)
303{
304 int num;
305 u32 id;
306 int i;
307 unsigned int irq;
308 struct clk *clk;
309 int num_parents;
310 const char *parent_names[PROG_SOURCE_MAX];
311 const char *name;
312 struct device_node *progclknp;
313
314 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
315 if (num_parents <= 0 || num_parents > PROG_SOURCE_MAX)
316 return;
317
318 for (i = 0; i < num_parents; ++i) {
319 parent_names[i] = of_clk_get_parent_name(np, i);
320 if (!parent_names[i])
321 return;
322 }
323
324 num = of_get_child_count(np);
325 if (!num || num > (PROG_ID_MAX + 1))
326 return;
327
328 for_each_child_of_node(np, progclknp) {
329 if (of_property_read_u32(progclknp, "reg", &id))
330 continue;
331
332 if (of_property_read_string(np, "clock-output-names", &name))
333 name = progclknp->name;
334
335 irq = irq_of_parse_and_map(progclknp, 0);
336 if (!irq)
337 continue;
338
339 clk = at91_clk_register_programmable(pmc, irq, name,
340 parent_names, num_parents,
341 id, layout);
342 if (IS_ERR(clk))
343 continue;
344
345 of_clk_add_provider(progclknp, of_clk_src_simple_get, clk);
346 }
347}
348
349
350void __init of_at91rm9200_clk_prog_setup(struct device_node *np,
351 struct at91_pmc *pmc)
352{
353 of_at91_clk_prog_setup(np, pmc, &at91rm9200_programmable_layout);
354}
355
356void __init of_at91sam9g45_clk_prog_setup(struct device_node *np,
357 struct at91_pmc *pmc)
358{
359 of_at91_clk_prog_setup(np, pmc, &at91sam9g45_programmable_layout);
360}
361
362void __init of_at91sam9x5_clk_prog_setup(struct device_node *np,
363 struct at91_pmc *pmc)
364{
365 of_at91_clk_prog_setup(np, pmc, &at91sam9x5_programmable_layout);
366}
diff --git a/drivers/clk/at91/clk-smd.c b/drivers/clk/at91/clk-smd.c
new file mode 100644
index 000000000000..144d47ecfe63
--- /dev/null
+++ b/drivers/clk/at91/clk-smd.c
@@ -0,0 +1,171 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define SMD_SOURCE_MAX 2
21
22#define SMD_DIV_SHIFT 8
23#define SMD_MAX_DIV 0xf
24
25struct at91sam9x5_clk_smd {
26 struct clk_hw hw;
27 struct at91_pmc *pmc;
28};
29
30#define to_at91sam9x5_clk_smd(hw) \
31 container_of(hw, struct at91sam9x5_clk_smd, hw)
32
33static unsigned long at91sam9x5_clk_smd_recalc_rate(struct clk_hw *hw,
34 unsigned long parent_rate)
35{
36 u32 tmp;
37 u8 smddiv;
38 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
39 struct at91_pmc *pmc = smd->pmc;
40
41 tmp = pmc_read(pmc, AT91_PMC_SMD);
42 smddiv = (tmp & AT91_PMC_SMD_DIV) >> SMD_DIV_SHIFT;
43 return parent_rate / (smddiv + 1);
44}
45
46static long at91sam9x5_clk_smd_round_rate(struct clk_hw *hw, unsigned long rate,
47 unsigned long *parent_rate)
48{
49 unsigned long div;
50 unsigned long bestrate;
51 unsigned long tmp;
52
53 if (rate >= *parent_rate)
54 return *parent_rate;
55
56 div = *parent_rate / rate;
57 if (div > SMD_MAX_DIV)
58 return *parent_rate / (SMD_MAX_DIV + 1);
59
60 bestrate = *parent_rate / div;
61 tmp = *parent_rate / (div + 1);
62 if (bestrate - rate > rate - tmp)
63 bestrate = tmp;
64
65 return bestrate;
66}
67
68static int at91sam9x5_clk_smd_set_parent(struct clk_hw *hw, u8 index)
69{
70 u32 tmp;
71 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
72 struct at91_pmc *pmc = smd->pmc;
73
74 if (index > 1)
75 return -EINVAL;
76 tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMDS;
77 if (index)
78 tmp |= AT91_PMC_SMDS;
79 pmc_write(pmc, AT91_PMC_SMD, tmp);
80 return 0;
81}
82
83static u8 at91sam9x5_clk_smd_get_parent(struct clk_hw *hw)
84{
85 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
86 struct at91_pmc *pmc = smd->pmc;
87
88 return pmc_read(pmc, AT91_PMC_SMD) & AT91_PMC_SMDS;
89}
90
91static int at91sam9x5_clk_smd_set_rate(struct clk_hw *hw, unsigned long rate,
92 unsigned long parent_rate)
93{
94 u32 tmp;
95 struct at91sam9x5_clk_smd *smd = to_at91sam9x5_clk_smd(hw);
96 struct at91_pmc *pmc = smd->pmc;
97 unsigned long div = parent_rate / rate;
98
99 if (parent_rate % rate || div < 1 || div > (SMD_MAX_DIV + 1))
100 return -EINVAL;
101 tmp = pmc_read(pmc, AT91_PMC_SMD) & ~AT91_PMC_SMD_DIV;
102 tmp |= (div - 1) << SMD_DIV_SHIFT;
103 pmc_write(pmc, AT91_PMC_SMD, tmp);
104
105 return 0;
106}
107
108static const struct clk_ops at91sam9x5_smd_ops = {
109 .recalc_rate = at91sam9x5_clk_smd_recalc_rate,
110 .round_rate = at91sam9x5_clk_smd_round_rate,
111 .get_parent = at91sam9x5_clk_smd_get_parent,
112 .set_parent = at91sam9x5_clk_smd_set_parent,
113 .set_rate = at91sam9x5_clk_smd_set_rate,
114};
115
116static struct clk * __init
117at91sam9x5_clk_register_smd(struct at91_pmc *pmc, const char *name,
118 const char **parent_names, u8 num_parents)
119{
120 struct at91sam9x5_clk_smd *smd;
121 struct clk *clk = NULL;
122 struct clk_init_data init;
123
124 smd = kzalloc(sizeof(*smd), GFP_KERNEL);
125 if (!smd)
126 return ERR_PTR(-ENOMEM);
127
128 init.name = name;
129 init.ops = &at91sam9x5_smd_ops;
130 init.parent_names = parent_names;
131 init.num_parents = num_parents;
132 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
133
134 smd->hw.init = &init;
135 smd->pmc = pmc;
136
137 clk = clk_register(NULL, &smd->hw);
138 if (IS_ERR(clk))
139 kfree(smd);
140
141 return clk;
142}
143
144void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
145 struct at91_pmc *pmc)
146{
147 struct clk *clk;
148 int i;
149 int num_parents;
150 const char *parent_names[SMD_SOURCE_MAX];
151 const char *name = np->name;
152
153 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
154 if (num_parents <= 0 || num_parents > SMD_SOURCE_MAX)
155 return;
156
157 for (i = 0; i < num_parents; i++) {
158 parent_names[i] = of_clk_get_parent_name(np, i);
159 if (!parent_names[i])
160 return;
161 }
162
163 of_property_read_string(np, "clock-output-names", &name);
164
165 clk = at91sam9x5_clk_register_smd(pmc, name, parent_names,
166 num_parents);
167 if (IS_ERR(clk))
168 return;
169
170 of_clk_add_provider(np, of_clk_src_simple_get, clk);
171}
diff --git a/drivers/clk/at91/clk-system.c b/drivers/clk/at91/clk-system.c
new file mode 100644
index 000000000000..8f7c0434a09f
--- /dev/null
+++ b/drivers/clk/at91/clk-system.c
@@ -0,0 +1,135 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define SYSTEM_MAX_ID 31
21
22#define SYSTEM_MAX_NAME_SZ 32
23
24#define to_clk_system(hw) container_of(hw, struct clk_system, hw)
25struct clk_system {
26 struct clk_hw hw;
27 struct at91_pmc *pmc;
28 u8 id;
29};
30
31static int clk_system_enable(struct clk_hw *hw)
32{
33 struct clk_system *sys = to_clk_system(hw);
34 struct at91_pmc *pmc = sys->pmc;
35
36 pmc_write(pmc, AT91_PMC_SCER, 1 << sys->id);
37 return 0;
38}
39
40static void clk_system_disable(struct clk_hw *hw)
41{
42 struct clk_system *sys = to_clk_system(hw);
43 struct at91_pmc *pmc = sys->pmc;
44
45 pmc_write(pmc, AT91_PMC_SCDR, 1 << sys->id);
46}
47
48static int clk_system_is_enabled(struct clk_hw *hw)
49{
50 struct clk_system *sys = to_clk_system(hw);
51 struct at91_pmc *pmc = sys->pmc;
52
53 return !!(pmc_read(pmc, AT91_PMC_SCSR) & (1 << sys->id));
54}
55
56static const struct clk_ops system_ops = {
57 .enable = clk_system_enable,
58 .disable = clk_system_disable,
59 .is_enabled = clk_system_is_enabled,
60};
61
62static struct clk * __init
63at91_clk_register_system(struct at91_pmc *pmc, const char *name,
64 const char *parent_name, u8 id)
65{
66 struct clk_system *sys;
67 struct clk *clk = NULL;
68 struct clk_init_data init;
69
70 if (!parent_name || id > SYSTEM_MAX_ID)
71 return ERR_PTR(-EINVAL);
72
73 sys = kzalloc(sizeof(*sys), GFP_KERNEL);
74 if (!sys)
75 return ERR_PTR(-ENOMEM);
76
77 init.name = name;
78 init.ops = &system_ops;
79 init.parent_names = &parent_name;
80 init.num_parents = 1;
81 /*
82 * CLK_IGNORE_UNUSED is used to avoid ddrck switch off.
83 * TODO : we should implement a driver supporting at91 ddr controller
84 * (see drivers/memory) which would request and enable the ddrck clock.
85 * When this is done we will be able to remove CLK_IGNORE_UNUSED flag.
86 */
87 init.flags = CLK_IGNORE_UNUSED;
88
89 sys->id = id;
90 sys->hw.init = &init;
91 sys->pmc = pmc;
92
93 clk = clk_register(NULL, &sys->hw);
94 if (IS_ERR(clk))
95 kfree(sys);
96
97 return clk;
98}
99
100static void __init
101of_at91_clk_sys_setup(struct device_node *np, struct at91_pmc *pmc)
102{
103 int num;
104 u32 id;
105 struct clk *clk;
106 const char *name;
107 struct device_node *sysclknp;
108 const char *parent_name;
109
110 num = of_get_child_count(np);
111 if (num > (SYSTEM_MAX_ID + 1))
112 return;
113
114 for_each_child_of_node(np, sysclknp) {
115 if (of_property_read_u32(sysclknp, "reg", &id))
116 continue;
117
118 if (of_property_read_string(np, "clock-output-names", &name))
119 name = sysclknp->name;
120
121 parent_name = of_clk_get_parent_name(sysclknp, 0);
122
123 clk = at91_clk_register_system(pmc, name, parent_name, id);
124 if (IS_ERR(clk))
125 continue;
126
127 of_clk_add_provider(sysclknp, of_clk_src_simple_get, clk);
128 }
129}
130
131void __init of_at91rm9200_clk_sys_setup(struct device_node *np,
132 struct at91_pmc *pmc)
133{
134 of_at91_clk_sys_setup(np, pmc);
135}
diff --git a/drivers/clk/at91/clk-usb.c b/drivers/clk/at91/clk-usb.c
new file mode 100644
index 000000000000..7d1d26a4bd04
--- /dev/null
+++ b/drivers/clk/at91/clk-usb.c
@@ -0,0 +1,398 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17
18#include "pmc.h"
19
20#define USB_SOURCE_MAX 2
21
22#define SAM9X5_USB_DIV_SHIFT 8
23#define SAM9X5_USB_MAX_DIV 0xf
24
25#define RM9200_USB_DIV_SHIFT 28
26#define RM9200_USB_DIV_TAB_SIZE 4
27
28struct at91sam9x5_clk_usb {
29 struct clk_hw hw;
30 struct at91_pmc *pmc;
31};
32
33#define to_at91sam9x5_clk_usb(hw) \
34 container_of(hw, struct at91sam9x5_clk_usb, hw)
35
36struct at91rm9200_clk_usb {
37 struct clk_hw hw;
38 struct at91_pmc *pmc;
39 u32 divisors[4];
40};
41
42#define to_at91rm9200_clk_usb(hw) \
43 container_of(hw, struct at91rm9200_clk_usb, hw)
44
45static unsigned long at91sam9x5_clk_usb_recalc_rate(struct clk_hw *hw,
46 unsigned long parent_rate)
47{
48 u32 tmp;
49 u8 usbdiv;
50 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
51 struct at91_pmc *pmc = usb->pmc;
52
53 tmp = pmc_read(pmc, AT91_PMC_USB);
54 usbdiv = (tmp & AT91_PMC_OHCIUSBDIV) >> SAM9X5_USB_DIV_SHIFT;
55 return parent_rate / (usbdiv + 1);
56}
57
58static long at91sam9x5_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
59 unsigned long *parent_rate)
60{
61 unsigned long div;
62 unsigned long bestrate;
63 unsigned long tmp;
64
65 if (rate >= *parent_rate)
66 return *parent_rate;
67
68 div = *parent_rate / rate;
69 if (div >= SAM9X5_USB_MAX_DIV)
70 return *parent_rate / (SAM9X5_USB_MAX_DIV + 1);
71
72 bestrate = *parent_rate / div;
73 tmp = *parent_rate / (div + 1);
74 if (bestrate - rate > rate - tmp)
75 bestrate = tmp;
76
77 return bestrate;
78}
79
80static int at91sam9x5_clk_usb_set_parent(struct clk_hw *hw, u8 index)
81{
82 u32 tmp;
83 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
84 struct at91_pmc *pmc = usb->pmc;
85
86 if (index > 1)
87 return -EINVAL;
88 tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS;
89 if (index)
90 tmp |= AT91_PMC_USBS;
91 pmc_write(pmc, AT91_PMC_USB, tmp);
92 return 0;
93}
94
95static u8 at91sam9x5_clk_usb_get_parent(struct clk_hw *hw)
96{
97 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
98 struct at91_pmc *pmc = usb->pmc;
99
100 return pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS;
101}
102
103static int at91sam9x5_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
104 unsigned long parent_rate)
105{
106 u32 tmp;
107 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
108 struct at91_pmc *pmc = usb->pmc;
109 unsigned long div = parent_rate / rate;
110
111 if (parent_rate % rate || div < 1 || div >= SAM9X5_USB_MAX_DIV)
112 return -EINVAL;
113
114 tmp = pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_OHCIUSBDIV;
115 tmp |= (div - 1) << SAM9X5_USB_DIV_SHIFT;
116 pmc_write(pmc, AT91_PMC_USB, tmp);
117
118 return 0;
119}
120
121static const struct clk_ops at91sam9x5_usb_ops = {
122 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
123 .round_rate = at91sam9x5_clk_usb_round_rate,
124 .get_parent = at91sam9x5_clk_usb_get_parent,
125 .set_parent = at91sam9x5_clk_usb_set_parent,
126 .set_rate = at91sam9x5_clk_usb_set_rate,
127};
128
129static int at91sam9n12_clk_usb_enable(struct clk_hw *hw)
130{
131 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
132 struct at91_pmc *pmc = usb->pmc;
133
134 pmc_write(pmc, AT91_PMC_USB,
135 pmc_read(pmc, AT91_PMC_USB) | AT91_PMC_USBS);
136 return 0;
137}
138
139static void at91sam9n12_clk_usb_disable(struct clk_hw *hw)
140{
141 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
142 struct at91_pmc *pmc = usb->pmc;
143
144 pmc_write(pmc, AT91_PMC_USB,
145 pmc_read(pmc, AT91_PMC_USB) & ~AT91_PMC_USBS);
146}
147
148static int at91sam9n12_clk_usb_is_enabled(struct clk_hw *hw)
149{
150 struct at91sam9x5_clk_usb *usb = to_at91sam9x5_clk_usb(hw);
151 struct at91_pmc *pmc = usb->pmc;
152
153 return !!(pmc_read(pmc, AT91_PMC_USB) & AT91_PMC_USBS);
154}
155
156static const struct clk_ops at91sam9n12_usb_ops = {
157 .enable = at91sam9n12_clk_usb_enable,
158 .disable = at91sam9n12_clk_usb_disable,
159 .is_enabled = at91sam9n12_clk_usb_is_enabled,
160 .recalc_rate = at91sam9x5_clk_usb_recalc_rate,
161 .round_rate = at91sam9x5_clk_usb_round_rate,
162 .set_rate = at91sam9x5_clk_usb_set_rate,
163};
164
165static struct clk * __init
166at91sam9x5_clk_register_usb(struct at91_pmc *pmc, const char *name,
167 const char **parent_names, u8 num_parents)
168{
169 struct at91sam9x5_clk_usb *usb;
170 struct clk *clk = NULL;
171 struct clk_init_data init;
172
173 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
174 if (!usb)
175 return ERR_PTR(-ENOMEM);
176
177 init.name = name;
178 init.ops = &at91sam9x5_usb_ops;
179 init.parent_names = parent_names;
180 init.num_parents = num_parents;
181 init.flags = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE;
182
183 usb->hw.init = &init;
184 usb->pmc = pmc;
185
186 clk = clk_register(NULL, &usb->hw);
187 if (IS_ERR(clk))
188 kfree(usb);
189
190 return clk;
191}
192
193static struct clk * __init
194at91sam9n12_clk_register_usb(struct at91_pmc *pmc, const char *name,
195 const char *parent_name)
196{
197 struct at91sam9x5_clk_usb *usb;
198 struct clk *clk = NULL;
199 struct clk_init_data init;
200
201 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
202 if (!usb)
203 return ERR_PTR(-ENOMEM);
204
205 init.name = name;
206 init.ops = &at91sam9n12_usb_ops;
207 init.parent_names = &parent_name;
208 init.num_parents = 1;
209 init.flags = CLK_SET_RATE_GATE;
210
211 usb->hw.init = &init;
212 usb->pmc = pmc;
213
214 clk = clk_register(NULL, &usb->hw);
215 if (IS_ERR(clk))
216 kfree(usb);
217
218 return clk;
219}
220
221static unsigned long at91rm9200_clk_usb_recalc_rate(struct clk_hw *hw,
222 unsigned long parent_rate)
223{
224 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
225 struct at91_pmc *pmc = usb->pmc;
226 u32 tmp;
227 u8 usbdiv;
228
229 tmp = pmc_read(pmc, AT91_CKGR_PLLBR);
230 usbdiv = (tmp & AT91_PMC_USBDIV) >> RM9200_USB_DIV_SHIFT;
231 if (usb->divisors[usbdiv])
232 return parent_rate / usb->divisors[usbdiv];
233
234 return 0;
235}
236
237static long at91rm9200_clk_usb_round_rate(struct clk_hw *hw, unsigned long rate,
238 unsigned long *parent_rate)
239{
240 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
241 unsigned long bestrate = 0;
242 int bestdiff = -1;
243 unsigned long tmprate;
244 int tmpdiff;
245 int i = 0;
246
247 for (i = 0; i < 4; i++) {
248 if (!usb->divisors[i])
249 continue;
250 tmprate = *parent_rate / usb->divisors[i];
251 if (tmprate < rate)
252 tmpdiff = rate - tmprate;
253 else
254 tmpdiff = tmprate - rate;
255
256 if (bestdiff < 0 || bestdiff > tmpdiff) {
257 bestrate = tmprate;
258 bestdiff = tmpdiff;
259 }
260
261 if (!bestdiff)
262 break;
263 }
264
265 return bestrate;
266}
267
268static int at91rm9200_clk_usb_set_rate(struct clk_hw *hw, unsigned long rate,
269 unsigned long parent_rate)
270{
271 u32 tmp;
272 int i;
273 struct at91rm9200_clk_usb *usb = to_at91rm9200_clk_usb(hw);
274 struct at91_pmc *pmc = usb->pmc;
275 unsigned long div = parent_rate / rate;
276
277 if (parent_rate % rate)
278 return -EINVAL;
279 for (i = 0; i < RM9200_USB_DIV_TAB_SIZE; i++) {
280 if (usb->divisors[i] == div) {
281 tmp = pmc_read(pmc, AT91_CKGR_PLLBR) &
282 ~AT91_PMC_USBDIV;
283 tmp |= i << RM9200_USB_DIV_SHIFT;
284 pmc_write(pmc, AT91_CKGR_PLLBR, tmp);
285 return 0;
286 }
287 }
288
289 return -EINVAL;
290}
291
292static const struct clk_ops at91rm9200_usb_ops = {
293 .recalc_rate = at91rm9200_clk_usb_recalc_rate,
294 .round_rate = at91rm9200_clk_usb_round_rate,
295 .set_rate = at91rm9200_clk_usb_set_rate,
296};
297
298static struct clk * __init
299at91rm9200_clk_register_usb(struct at91_pmc *pmc, const char *name,
300 const char *parent_name, const u32 *divisors)
301{
302 struct at91rm9200_clk_usb *usb;
303 struct clk *clk = NULL;
304 struct clk_init_data init;
305
306 usb = kzalloc(sizeof(*usb), GFP_KERNEL);
307 if (!usb)
308 return ERR_PTR(-ENOMEM);
309
310 init.name = name;
311 init.ops = &at91rm9200_usb_ops;
312 init.parent_names = &parent_name;
313 init.num_parents = 1;
314 init.flags = 0;
315
316 usb->hw.init = &init;
317 usb->pmc = pmc;
318 memcpy(usb->divisors, divisors, sizeof(usb->divisors));
319
320 clk = clk_register(NULL, &usb->hw);
321 if (IS_ERR(clk))
322 kfree(usb);
323
324 return clk;
325}
326
327void __init of_at91sam9x5_clk_usb_setup(struct device_node *np,
328 struct at91_pmc *pmc)
329{
330 struct clk *clk;
331 int i;
332 int num_parents;
333 const char *parent_names[USB_SOURCE_MAX];
334 const char *name = np->name;
335
336 num_parents = of_count_phandle_with_args(np, "clocks", "#clock-cells");
337 if (num_parents <= 0 || num_parents > USB_SOURCE_MAX)
338 return;
339
340 for (i = 0; i < num_parents; i++) {
341 parent_names[i] = of_clk_get_parent_name(np, i);
342 if (!parent_names[i])
343 return;
344 }
345
346 of_property_read_string(np, "clock-output-names", &name);
347
348 clk = at91sam9x5_clk_register_usb(pmc, name, parent_names, num_parents);
349 if (IS_ERR(clk))
350 return;
351
352 of_clk_add_provider(np, of_clk_src_simple_get, clk);
353}
354
355void __init of_at91sam9n12_clk_usb_setup(struct device_node *np,
356 struct at91_pmc *pmc)
357{
358 struct clk *clk;
359 const char *parent_name;
360 const char *name = np->name;
361
362 parent_name = of_clk_get_parent_name(np, 0);
363 if (!parent_name)
364 return;
365
366 of_property_read_string(np, "clock-output-names", &name);
367
368 clk = at91sam9n12_clk_register_usb(pmc, name, parent_name);
369 if (IS_ERR(clk))
370 return;
371
372 of_clk_add_provider(np, of_clk_src_simple_get, clk);
373}
374
375void __init of_at91rm9200_clk_usb_setup(struct device_node *np,
376 struct at91_pmc *pmc)
377{
378 struct clk *clk;
379 const char *parent_name;
380 const char *name = np->name;
381 u32 divisors[4] = {0, 0, 0, 0};
382
383 parent_name = of_clk_get_parent_name(np, 0);
384 if (!parent_name)
385 return;
386
387 of_property_read_u32_array(np, "atmel,clk-divisors", divisors, 4);
388 if (!divisors[0])
389 return;
390
391 of_property_read_string(np, "clock-output-names", &name);
392
393 clk = at91rm9200_clk_register_usb(pmc, name, parent_name, divisors);
394 if (IS_ERR(clk))
395 return;
396
397 of_clk_add_provider(np, of_clk_src_simple_get, clk);
398}
diff --git a/drivers/clk/at91/clk-utmi.c b/drivers/clk/at91/clk-utmi.c
new file mode 100644
index 000000000000..ae3263bc1476
--- /dev/null
+++ b/drivers/clk/at91/clk-utmi.c
@@ -0,0 +1,159 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/interrupt.h>
15#include <linux/irq.h>
16#include <linux/of.h>
17#include <linux/of_address.h>
18#include <linux/of_irq.h>
19#include <linux/io.h>
20#include <linux/sched.h>
21#include <linux/wait.h>
22
23#include "pmc.h"
24
25#define UTMI_FIXED_MUL 40
26
27struct clk_utmi {
28 struct clk_hw hw;
29 struct at91_pmc *pmc;
30 unsigned int irq;
31 wait_queue_head_t wait;
32};
33
34#define to_clk_utmi(hw) container_of(hw, struct clk_utmi, hw)
35
36static irqreturn_t clk_utmi_irq_handler(int irq, void *dev_id)
37{
38 struct clk_utmi *utmi = (struct clk_utmi *)dev_id;
39
40 wake_up(&utmi->wait);
41 disable_irq_nosync(utmi->irq);
42
43 return IRQ_HANDLED;
44}
45
46static int clk_utmi_prepare(struct clk_hw *hw)
47{
48 struct clk_utmi *utmi = to_clk_utmi(hw);
49 struct at91_pmc *pmc = utmi->pmc;
50 u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) | AT91_PMC_UPLLEN |
51 AT91_PMC_UPLLCOUNT | AT91_PMC_BIASEN;
52
53 pmc_write(pmc, AT91_CKGR_UCKR, tmp);
54
55 while (!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU)) {
56 enable_irq(utmi->irq);
57 wait_event(utmi->wait,
58 pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU);
59 }
60
61 return 0;
62}
63
64static int clk_utmi_is_prepared(struct clk_hw *hw)
65{
66 struct clk_utmi *utmi = to_clk_utmi(hw);
67 struct at91_pmc *pmc = utmi->pmc;
68
69 return !!(pmc_read(pmc, AT91_PMC_SR) & AT91_PMC_LOCKU);
70}
71
72static void clk_utmi_unprepare(struct clk_hw *hw)
73{
74 struct clk_utmi *utmi = to_clk_utmi(hw);
75 struct at91_pmc *pmc = utmi->pmc;
76 u32 tmp = at91_pmc_read(AT91_CKGR_UCKR) & ~AT91_PMC_UPLLEN;
77
78 pmc_write(pmc, AT91_CKGR_UCKR, tmp);
79}
80
81static unsigned long clk_utmi_recalc_rate(struct clk_hw *hw,
82 unsigned long parent_rate)
83{
84 /* UTMI clk is a fixed clk multiplier */
85 return parent_rate * UTMI_FIXED_MUL;
86}
87
88static const struct clk_ops utmi_ops = {
89 .prepare = clk_utmi_prepare,
90 .unprepare = clk_utmi_unprepare,
91 .is_prepared = clk_utmi_is_prepared,
92 .recalc_rate = clk_utmi_recalc_rate,
93};
94
95static struct clk * __init
96at91_clk_register_utmi(struct at91_pmc *pmc, unsigned int irq,
97 const char *name, const char *parent_name)
98{
99 int ret;
100 struct clk_utmi *utmi;
101 struct clk *clk = NULL;
102 struct clk_init_data init;
103
104 utmi = kzalloc(sizeof(*utmi), GFP_KERNEL);
105 if (!utmi)
106 return ERR_PTR(-ENOMEM);
107
108 init.name = name;
109 init.ops = &utmi_ops;
110 init.parent_names = parent_name ? &parent_name : NULL;
111 init.num_parents = parent_name ? 1 : 0;
112 init.flags = CLK_SET_RATE_GATE;
113
114 utmi->hw.init = &init;
115 utmi->pmc = pmc;
116 utmi->irq = irq;
117 init_waitqueue_head(&utmi->wait);
118 irq_set_status_flags(utmi->irq, IRQ_NOAUTOEN);
119 ret = request_irq(utmi->irq, clk_utmi_irq_handler,
120 IRQF_TRIGGER_HIGH, "clk-utmi", utmi);
121 if (ret)
122 return ERR_PTR(ret);
123
124 clk = clk_register(NULL, &utmi->hw);
125 if (IS_ERR(clk))
126 kfree(utmi);
127
128 return clk;
129}
130
131static void __init
132of_at91_clk_utmi_setup(struct device_node *np, struct at91_pmc *pmc)
133{
134 unsigned int irq;
135 struct clk *clk;
136 const char *parent_name;
137 const char *name = np->name;
138
139 parent_name = of_clk_get_parent_name(np, 0);
140
141 of_property_read_string(np, "clock-output-names", &name);
142
143 irq = irq_of_parse_and_map(np, 0);
144 if (!irq)
145 return;
146
147 clk = at91_clk_register_utmi(pmc, irq, name, parent_name);
148 if (IS_ERR(clk))
149 return;
150
151 of_clk_add_provider(np, of_clk_src_simple_get, clk);
152 return;
153}
154
155void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np,
156 struct at91_pmc *pmc)
157{
158 of_at91_clk_utmi_setup(np, pmc);
159}
diff --git a/drivers/clk/at91/pmc.c b/drivers/clk/at91/pmc.c
new file mode 100644
index 000000000000..7b9db603b936
--- /dev/null
+++ b/drivers/clk/at91/pmc.c
@@ -0,0 +1,397 @@
1/*
2 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 *
9 */
10
11#include <linux/clk-provider.h>
12#include <linux/clkdev.h>
13#include <linux/clk/at91_pmc.h>
14#include <linux/of.h>
15#include <linux/of_address.h>
16#include <linux/io.h>
17#include <linux/interrupt.h>
18#include <linux/irq.h>
19#include <linux/irqchip/chained_irq.h>
20#include <linux/irqdomain.h>
21#include <linux/of_irq.h>
22
23#include <asm/proc-fns.h>
24
25#include "pmc.h"
26
27void __iomem *at91_pmc_base;
28EXPORT_SYMBOL_GPL(at91_pmc_base);
29
30void at91sam9_idle(void)
31{
32 at91_pmc_write(AT91_PMC_SCDR, AT91_PMC_PCK);
33 cpu_do_idle();
34}
35
36int of_at91_get_clk_range(struct device_node *np, const char *propname,
37 struct clk_range *range)
38{
39 u32 min, max;
40 int ret;
41
42 ret = of_property_read_u32_index(np, propname, 0, &min);
43 if (ret)
44 return ret;
45
46 ret = of_property_read_u32_index(np, propname, 1, &max);
47 if (ret)
48 return ret;
49
50 if (range) {
51 range->min = min;
52 range->max = max;
53 }
54
55 return 0;
56}
57EXPORT_SYMBOL_GPL(of_at91_get_clk_range);
58
59static void pmc_irq_mask(struct irq_data *d)
60{
61 struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
62
63 pmc_write(pmc, AT91_PMC_IDR, 1 << d->hwirq);
64}
65
66static void pmc_irq_unmask(struct irq_data *d)
67{
68 struct at91_pmc *pmc = irq_data_get_irq_chip_data(d);
69
70 pmc_write(pmc, AT91_PMC_IER, 1 << d->hwirq);
71}
72
73static int pmc_irq_set_type(struct irq_data *d, unsigned type)
74{
75 if (type != IRQ_TYPE_LEVEL_HIGH) {
76 pr_warn("PMC: type not supported (support only IRQ_TYPE_LEVEL_HIGH type)\n");
77 return -EINVAL;
78 }
79
80 return 0;
81}
82
83static struct irq_chip pmc_irq = {
84 .name = "PMC",
85 .irq_disable = pmc_irq_mask,
86 .irq_mask = pmc_irq_mask,
87 .irq_unmask = pmc_irq_unmask,
88 .irq_set_type = pmc_irq_set_type,
89};
90
91static struct lock_class_key pmc_lock_class;
92
93static int pmc_irq_map(struct irq_domain *h, unsigned int virq,
94 irq_hw_number_t hw)
95{
96 struct at91_pmc *pmc = h->host_data;
97
98 irq_set_lockdep_class(virq, &pmc_lock_class);
99
100 irq_set_chip_and_handler(virq, &pmc_irq,
101 handle_level_irq);
102 set_irq_flags(virq, IRQF_VALID);
103 irq_set_chip_data(virq, pmc);
104
105 return 0;
106}
107
108static int pmc_irq_domain_xlate(struct irq_domain *d,
109 struct device_node *ctrlr,
110 const u32 *intspec, unsigned int intsize,
111 irq_hw_number_t *out_hwirq,
112 unsigned int *out_type)
113{
114 struct at91_pmc *pmc = d->host_data;
115 const struct at91_pmc_caps *caps = pmc->caps;
116
117 if (WARN_ON(intsize < 1))
118 return -EINVAL;
119
120 *out_hwirq = intspec[0];
121
122 if (!(caps->available_irqs & (1 << *out_hwirq)))
123 return -EINVAL;
124
125 *out_type = IRQ_TYPE_LEVEL_HIGH;
126
127 return 0;
128}
129
130static struct irq_domain_ops pmc_irq_ops = {
131 .map = pmc_irq_map,
132 .xlate = pmc_irq_domain_xlate,
133};
134
135static irqreturn_t pmc_irq_handler(int irq, void *data)
136{
137 struct at91_pmc *pmc = (struct at91_pmc *)data;
138 unsigned long sr;
139 int n;
140
141 sr = pmc_read(pmc, AT91_PMC_SR) & pmc_read(pmc, AT91_PMC_IMR);
142 if (!sr)
143 return IRQ_NONE;
144
145 for_each_set_bit(n, &sr, BITS_PER_LONG)
146 generic_handle_irq(irq_find_mapping(pmc->irqdomain, n));
147
148 return IRQ_HANDLED;
149}
150
151static const struct at91_pmc_caps at91rm9200_caps = {
152 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
153 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
154 AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
155 AT91_PMC_PCK3RDY,
156};
157
158static const struct at91_pmc_caps at91sam9260_caps = {
159 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
160 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
161 AT91_PMC_PCK1RDY,
162};
163
164static const struct at91_pmc_caps at91sam9g45_caps = {
165 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
166 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
167 AT91_PMC_PCK1RDY,
168};
169
170static const struct at91_pmc_caps at91sam9n12_caps = {
171 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_LOCKB |
172 AT91_PMC_MCKRDY | AT91_PMC_PCK0RDY |
173 AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
174 AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
175};
176
177static const struct at91_pmc_caps at91sam9x5_caps = {
178 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
179 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
180 AT91_PMC_PCK1RDY | AT91_PMC_MOSCSELS |
181 AT91_PMC_MOSCRCS | AT91_PMC_CFDEV,
182};
183
184static const struct at91_pmc_caps sama5d3_caps = {
185 .available_irqs = AT91_PMC_MOSCS | AT91_PMC_LOCKA | AT91_PMC_MCKRDY |
186 AT91_PMC_LOCKU | AT91_PMC_PCK0RDY |
187 AT91_PMC_PCK1RDY | AT91_PMC_PCK2RDY |
188 AT91_PMC_MOSCSELS | AT91_PMC_MOSCRCS |
189 AT91_PMC_CFDEV,
190};
191
192static struct at91_pmc *__init at91_pmc_init(struct device_node *np,
193 void __iomem *regbase, int virq,
194 const struct at91_pmc_caps *caps)
195{
196 struct at91_pmc *pmc;
197
198 if (!regbase || !virq || !caps)
199 return NULL;
200
201 at91_pmc_base = regbase;
202
203 pmc = kzalloc(sizeof(*pmc), GFP_KERNEL);
204 if (!pmc)
205 return NULL;
206
207 spin_lock_init(&pmc->lock);
208 pmc->regbase = regbase;
209 pmc->virq = virq;
210 pmc->caps = caps;
211
212 pmc->irqdomain = irq_domain_add_linear(np, 32, &pmc_irq_ops, pmc);
213
214 if (!pmc->irqdomain)
215 goto out_free_pmc;
216
217 pmc_write(pmc, AT91_PMC_IDR, 0xffffffff);
218 if (request_irq(pmc->virq, pmc_irq_handler, IRQF_SHARED, "pmc", pmc))
219 goto out_remove_irqdomain;
220
221 return pmc;
222
223out_remove_irqdomain:
224 irq_domain_remove(pmc->irqdomain);
225out_free_pmc:
226 kfree(pmc);
227
228 return NULL;
229}
230
231static const struct of_device_id pmc_clk_ids[] __initdata = {
232 /* Main clock */
233 {
234 .compatible = "atmel,at91rm9200-clk-main",
235 .data = of_at91rm9200_clk_main_setup,
236 },
237 /* PLL clocks */
238 {
239 .compatible = "atmel,at91rm9200-clk-pll",
240 .data = of_at91rm9200_clk_pll_setup,
241 },
242 {
243 .compatible = "atmel,at91sam9g45-clk-pll",
244 .data = of_at91sam9g45_clk_pll_setup,
245 },
246 {
247 .compatible = "atmel,at91sam9g20-clk-pllb",
248 .data = of_at91sam9g20_clk_pllb_setup,
249 },
250 {
251 .compatible = "atmel,sama5d3-clk-pll",
252 .data = of_sama5d3_clk_pll_setup,
253 },
254 {
255 .compatible = "atmel,at91sam9x5-clk-plldiv",
256 .data = of_at91sam9x5_clk_plldiv_setup,
257 },
258 /* Master clock */
259 {
260 .compatible = "atmel,at91rm9200-clk-master",
261 .data = of_at91rm9200_clk_master_setup,
262 },
263 {
264 .compatible = "atmel,at91sam9x5-clk-master",
265 .data = of_at91sam9x5_clk_master_setup,
266 },
267 /* System clocks */
268 {
269 .compatible = "atmel,at91rm9200-clk-system",
270 .data = of_at91rm9200_clk_sys_setup,
271 },
272 /* Peripheral clocks */
273 {
274 .compatible = "atmel,at91rm9200-clk-peripheral",
275 .data = of_at91rm9200_clk_periph_setup,
276 },
277 {
278 .compatible = "atmel,at91sam9x5-clk-peripheral",
279 .data = of_at91sam9x5_clk_periph_setup,
280 },
281 /* Programmable clocks */
282#if defined(CONFIG_AT91_PROGRAMMABLE_CLOCKS)
283 {
284 .compatible = "atmel,at91rm9200-clk-programmable",
285 .data = of_at91rm9200_clk_prog_setup,
286 },
287 {
288 .compatible = "atmel,at91sam9g45-clk-programmable",
289 .data = of_at91sam9g45_clk_prog_setup,
290 },
291 {
292 .compatible = "atmel,at91sam9x5-clk-programmable",
293 .data = of_at91sam9x5_clk_prog_setup,
294 },
295#endif
296 /* UTMI clock */
297#if defined(CONFIG_HAVE_AT91_UTMI)
298 {
299 .compatible = "atmel,at91sam9x5-clk-utmi",
300 .data = of_at91sam9x5_clk_utmi_setup,
301 },
302#endif
303 /* USB clock */
304#if defined(CONFIG_HAVE_AT91_USB_CLK)
305 {
306 .compatible = "atmel,at91rm9200-clk-usb",
307 .data = of_at91rm9200_clk_usb_setup,
308 },
309 {
310 .compatible = "atmel,at91sam9x5-clk-usb",
311 .data = of_at91sam9x5_clk_usb_setup,
312 },
313 {
314 .compatible = "atmel,at91sam9n12-clk-usb",
315 .data = of_at91sam9n12_clk_usb_setup,
316 },
317#endif
318 /* SMD clock */
319#if defined(CONFIG_HAVE_AT91_SMD)
320 {
321 .compatible = "atmel,at91sam9x5-clk-smd",
322 .data = of_at91sam9x5_clk_smd_setup,
323 },
324#endif
325 { /*sentinel*/ }
326};
327
328static void __init of_at91_pmc_setup(struct device_node *np,
329 const struct at91_pmc_caps *caps)
330{
331 struct at91_pmc *pmc;
332 struct device_node *childnp;
333 void (*clk_setup)(struct device_node *, struct at91_pmc *);
334 const struct of_device_id *clk_id;
335 void __iomem *regbase = of_iomap(np, 0);
336 int virq;
337
338 if (!regbase)
339 return;
340
341 virq = irq_of_parse_and_map(np, 0);
342 if (!virq)
343 return;
344
345 pmc = at91_pmc_init(np, regbase, virq, caps);
346 if (!pmc)
347 return;
348 for_each_child_of_node(np, childnp) {
349 clk_id = of_match_node(pmc_clk_ids, childnp);
350 if (!clk_id)
351 continue;
352 clk_setup = clk_id->data;
353 clk_setup(childnp, pmc);
354 }
355}
356
357static void __init of_at91rm9200_pmc_setup(struct device_node *np)
358{
359 of_at91_pmc_setup(np, &at91rm9200_caps);
360}
361CLK_OF_DECLARE(at91rm9200_clk_pmc, "atmel,at91rm9200-pmc",
362 of_at91rm9200_pmc_setup);
363
364static void __init of_at91sam9260_pmc_setup(struct device_node *np)
365{
366 of_at91_pmc_setup(np, &at91sam9260_caps);
367}
368CLK_OF_DECLARE(at91sam9260_clk_pmc, "atmel,at91sam9260-pmc",
369 of_at91sam9260_pmc_setup);
370
371static void __init of_at91sam9g45_pmc_setup(struct device_node *np)
372{
373 of_at91_pmc_setup(np, &at91sam9g45_caps);
374}
375CLK_OF_DECLARE(at91sam9g45_clk_pmc, "atmel,at91sam9g45-pmc",
376 of_at91sam9g45_pmc_setup);
377
378static void __init of_at91sam9n12_pmc_setup(struct device_node *np)
379{
380 of_at91_pmc_setup(np, &at91sam9n12_caps);
381}
382CLK_OF_DECLARE(at91sam9n12_clk_pmc, "atmel,at91sam9n12-pmc",
383 of_at91sam9n12_pmc_setup);
384
385static void __init of_at91sam9x5_pmc_setup(struct device_node *np)
386{
387 of_at91_pmc_setup(np, &at91sam9x5_caps);
388}
389CLK_OF_DECLARE(at91sam9x5_clk_pmc, "atmel,at91sam9x5-pmc",
390 of_at91sam9x5_pmc_setup);
391
392static void __init of_sama5d3_pmc_setup(struct device_node *np)
393{
394 of_at91_pmc_setup(np, &sama5d3_caps);
395}
396CLK_OF_DECLARE(sama5d3_clk_pmc, "atmel,sama5d3-pmc",
397 of_sama5d3_pmc_setup);
diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
new file mode 100644
index 000000000000..ba8d14233f80
--- /dev/null
+++ b/drivers/clk/at91/pmc.h
@@ -0,0 +1,116 @@
1/*
2 * drivers/clk/at91/pmc.h
3 *
4 * Copyright (C) 2013 Boris BREZILLON <b.brezillon@overkiz.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12#ifndef __PMC_H_
13#define __PMC_H_
14
15#include <linux/io.h>
16#include <linux/irqdomain.h>
17#include <linux/spinlock.h>
18
19struct clk_range {
20 unsigned long min;
21 unsigned long max;
22};
23
24#define CLK_RANGE(MIN, MAX) {.min = MIN, .max = MAX,}
25
26struct at91_pmc_caps {
27 u32 available_irqs;
28};
29
30struct at91_pmc {
31 void __iomem *regbase;
32 int virq;
33 spinlock_t lock;
34 const struct at91_pmc_caps *caps;
35 struct irq_domain *irqdomain;
36};
37
38static inline void pmc_lock(struct at91_pmc *pmc)
39{
40 spin_lock(&pmc->lock);
41}
42
43static inline void pmc_unlock(struct at91_pmc *pmc)
44{
45 spin_unlock(&pmc->lock);
46}
47
48static inline u32 pmc_read(struct at91_pmc *pmc, int offset)
49{
50 return readl(pmc->regbase + offset);
51}
52
53static inline void pmc_write(struct at91_pmc *pmc, int offset, u32 value)
54{
55 writel(value, pmc->regbase + offset);
56}
57
58int of_at91_get_clk_range(struct device_node *np, const char *propname,
59 struct clk_range *range);
60
61extern void __init of_at91rm9200_clk_main_setup(struct device_node *np,
62 struct at91_pmc *pmc);
63
64extern void __init of_at91rm9200_clk_pll_setup(struct device_node *np,
65 struct at91_pmc *pmc);
66extern void __init of_at91sam9g45_clk_pll_setup(struct device_node *np,
67 struct at91_pmc *pmc);
68extern void __init of_at91sam9g20_clk_pllb_setup(struct device_node *np,
69 struct at91_pmc *pmc);
70extern void __init of_sama5d3_clk_pll_setup(struct device_node *np,
71 struct at91_pmc *pmc);
72extern void __init of_at91sam9x5_clk_plldiv_setup(struct device_node *np,
73 struct at91_pmc *pmc);
74
75extern void __init of_at91rm9200_clk_master_setup(struct device_node *np,
76 struct at91_pmc *pmc);
77extern void __init of_at91sam9x5_clk_master_setup(struct device_node *np,
78 struct at91_pmc *pmc);
79
80extern void __init of_at91rm9200_clk_sys_setup(struct device_node *np,
81 struct at91_pmc *pmc);
82
83extern void __init of_at91rm9200_clk_periph_setup(struct device_node *np,
84 struct at91_pmc *pmc);
85extern void __init of_at91sam9x5_clk_periph_setup(struct device_node *np,
86 struct at91_pmc *pmc);
87
88#if defined(CONFIG_AT91_PROGRAMMABLE_CLOCKS)
89extern void __init of_at91rm9200_clk_prog_setup(struct device_node *np,
90 struct at91_pmc *pmc);
91extern void __init of_at91sam9g45_clk_prog_setup(struct device_node *np,
92 struct at91_pmc *pmc);
93extern void __init of_at91sam9x5_clk_prog_setup(struct device_node *np,
94 struct at91_pmc *pmc);
95#endif
96
97#if defined(CONFIG_HAVE_AT91_UTMI)
98extern void __init of_at91sam9x5_clk_utmi_setup(struct device_node *np,
99 struct at91_pmc *pmc);
100#endif
101
102#if defined(CONFIG_HAVE_AT91_USB_CLK)
103extern void __init of_at91rm9200_clk_usb_setup(struct device_node *np,
104 struct at91_pmc *pmc);
105extern void __init of_at91sam9x5_clk_usb_setup(struct device_node *np,
106 struct at91_pmc *pmc);
107extern void __init of_at91sam9n12_clk_usb_setup(struct device_node *np,
108 struct at91_pmc *pmc);
109#endif
110
111#if defined(CONFIG_HAVE_AT91_SMD)
112extern void __init of_at91sam9x5_clk_smd_setup(struct device_node *np,
113 struct at91_pmc *pmc);
114#endif
115
116#endif /* __PMC_H_ */
diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index ad5ff50c5f28..d967571d305e 100644
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -530,7 +530,8 @@ static struct samsung_div_clock exynos4_div_clks[] __initdata = {
530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6), 530 DIV(sclk_i2s1, "sclk_i2s1", "sclk_audio1", DIV_PERIL5, 0, 6),
531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6), 531 DIV(sclk_i2s2, "sclk_i2s2", "sclk_audio2", DIV_PERIL5, 8, 6),
532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4), 532 DIV(none, "div_mmc4", "mout_mmc4", DIV_FSYS3, 0, 4),
533 DIV(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8), 533 DIV_F(none, "div_mmc_pre4", "div_mmc4", DIV_FSYS3, 8, 8,
534 CLK_SET_RATE_PARENT, 0),
534 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4), 535 DIV(none, "div_uart0", "mout_uart0", DIV_PERIL0, 0, 4),
535 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4), 536 DIV(none, "div_uart1", "mout_uart1", DIV_PERIL0, 4, 4),
536 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4), 537 DIV(none, "div_uart2", "mout_uart2", DIV_PERIL0, 8, 4),
diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c
index 62b0de6a1837..48f76bc05da0 100644
--- a/drivers/clocksource/exynos_mct.c
+++ b/drivers/clocksource/exynos_mct.c
@@ -71,6 +71,10 @@ enum {
71 MCT_L1_IRQ, 71 MCT_L1_IRQ,
72 MCT_L2_IRQ, 72 MCT_L2_IRQ,
73 MCT_L3_IRQ, 73 MCT_L3_IRQ,
74 MCT_L4_IRQ,
75 MCT_L5_IRQ,
76 MCT_L6_IRQ,
77 MCT_L7_IRQ,
74 MCT_NR_IRQS, 78 MCT_NR_IRQS,
75}; 79};
76 80
diff --git a/drivers/clocksource/nomadik-mtu.c b/drivers/clocksource/nomadik-mtu.c
index ed7b73b508e0..f00b5c9ce8b6 100644
--- a/drivers/clocksource/nomadik-mtu.c
+++ b/drivers/clocksource/nomadik-mtu.c
@@ -20,7 +20,6 @@
20#include <linux/jiffies.h> 20#include <linux/jiffies.h>
21#include <linux/delay.h> 21#include <linux/delay.h>
22#include <linux/err.h> 22#include <linux/err.h>
23#include <linux/platform_data/clocksource-nomadik-mtu.h>
24#include <linux/sched_clock.h> 23#include <linux/sched_clock.h>
25#include <asm/mach/time.h> 24#include <asm/mach/time.h>
26 25
@@ -103,7 +102,7 @@ static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
103 return 0; 102 return 0;
104} 103}
105 104
106void nmdk_clkevt_reset(void) 105static void nmdk_clkevt_reset(void)
107{ 106{
108 if (clkevt_periodic) { 107 if (clkevt_periodic) {
109 /* Timer: configure load and background-load, and fire it up */ 108 /* Timer: configure load and background-load, and fire it up */
@@ -144,7 +143,7 @@ static void nmdk_clkevt_mode(enum clock_event_mode mode,
144 } 143 }
145} 144}
146 145
147void nmdk_clksrc_reset(void) 146static void nmdk_clksrc_reset(void)
148{ 147{
149 /* Disable */ 148 /* Disable */
150 writel(0, mtu_base + MTU_CR(0)); 149 writel(0, mtu_base + MTU_CR(0));
@@ -192,8 +191,8 @@ static struct irqaction nmdk_timer_irq = {
192 .dev_id = &nmdk_clkevt, 191 .dev_id = &nmdk_clkevt,
193}; 192};
194 193
195static void __init __nmdk_timer_init(void __iomem *base, int irq, 194static void __init nmdk_timer_init(void __iomem *base, int irq,
196 struct clk *pclk, struct clk *clk) 195 struct clk *pclk, struct clk *clk)
197{ 196{
198 unsigned long rate; 197 unsigned long rate;
199 198
@@ -245,18 +244,6 @@ static void __init __nmdk_timer_init(void __iomem *base, int irq,
245 register_current_timer_delay(&mtu_delay_timer); 244 register_current_timer_delay(&mtu_delay_timer);
246} 245}
247 246
248void __init nmdk_timer_init(void __iomem *base, int irq)
249{
250 struct clk *clk0, *pclk0;
251
252 pclk0 = clk_get_sys("mtu0", "apb_pclk");
253 BUG_ON(IS_ERR(pclk0));
254 clk0 = clk_get_sys("mtu0", NULL);
255 BUG_ON(IS_ERR(clk0));
256
257 __nmdk_timer_init(base, irq, pclk0, clk0);
258}
259
260static void __init nmdk_timer_of_init(struct device_node *node) 247static void __init nmdk_timer_of_init(struct device_node *node)
261{ 248{
262 struct clk *pclk; 249 struct clk *pclk;
@@ -280,7 +267,7 @@ static void __init nmdk_timer_of_init(struct device_node *node)
280 if (irq <= 0) 267 if (irq <= 0)
281 panic("Can't parse IRQ"); 268 panic("Can't parse IRQ");
282 269
283 __nmdk_timer_init(base, irq, pclk, clk); 270 nmdk_timer_init(base, irq, pclk, clk);
284} 271}
285CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu", 272CLOCKSOURCE_OF_DECLARE(nomadik_mtu, "st,nomadik-mtu",
286 nmdk_timer_of_init); 273 nmdk_timer_of_init);
diff --git a/drivers/dma/ste_dma40.c b/drivers/dma/ste_dma40.c
index b8c031b7de4e..00a2de957b23 100644
--- a/drivers/dma/ste_dma40.c
+++ b/drivers/dma/ste_dma40.c
@@ -2409,6 +2409,7 @@ static void d40_set_prio_realtime(struct d40_chan *d40c)
2409#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1) 2409#define D40_DT_FLAGS_DIR(flags) ((flags >> 1) & 0x1)
2410#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1) 2410#define D40_DT_FLAGS_BIG_ENDIAN(flags) ((flags >> 2) & 0x1)
2411#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1) 2411#define D40_DT_FLAGS_FIXED_CHAN(flags) ((flags >> 3) & 0x1)
2412#define D40_DT_FLAGS_HIGH_PRIO(flags) ((flags >> 4) & 0x1)
2412 2413
2413static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec, 2414static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2414 struct of_dma *ofdma) 2415 struct of_dma *ofdma)
@@ -2446,6 +2447,9 @@ static struct dma_chan *d40_xlate(struct of_phandle_args *dma_spec,
2446 cfg.use_fixed_channel = true; 2447 cfg.use_fixed_channel = true;
2447 } 2448 }
2448 2449
2450 if (D40_DT_FLAGS_HIGH_PRIO(flags))
2451 cfg.high_priority = true;
2452
2449 return dma_request_channel(cap, stedma40_filter, &cfg); 2453 return dma_request_channel(cap, stedma40_filter, &cfg);
2450} 2454}
2451 2455
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index 7111c3b59130..983662e846a4 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -4,7 +4,7 @@
4 * Copyright (C) 2008,2009 STMicroelectronics 4 * Copyright (C) 2008,2009 STMicroelectronics
5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it> 5 * Copyright (C) 2009 Alessandro Rubini <rubini@unipv.it>
6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com> 6 * Rewritten based on work by Prafulla WADASKAR <prafulla.wadaskar@st.com>
7 * Copyright (C) 2011 Linus Walleij <linus.walleij@linaro.org> 7 * Copyright (C) 2011-2013 Linus Walleij <linus.walleij@linaro.org>
8 * 8 *
9 * This program is free software; you can redistribute it and/or modify 9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as 10 * it under the terms of the GNU General Public License version 2 as
@@ -33,7 +33,6 @@
33#include <linux/pinctrl/pinconf.h> 33#include <linux/pinctrl/pinconf.h>
34/* Since we request GPIOs from ourself */ 34/* Since we request GPIOs from ourself */
35#include <linux/pinctrl/consumer.h> 35#include <linux/pinctrl/consumer.h>
36#include <linux/platform_data/pinctrl-nomadik.h>
37#include "pinctrl-nomadik.h" 36#include "pinctrl-nomadik.h"
38#include "core.h" 37#include "core.h"
39 38
@@ -45,6 +44,221 @@
45 * Symbols in this file are called "nmk_gpio" for "nomadik gpio" 44 * Symbols in this file are called "nmk_gpio" for "nomadik gpio"
46 */ 45 */
47 46
47/*
48 * pin configurations are represented by 32-bit integers:
49 *
50 * bit 0.. 8 - Pin Number (512 Pins Maximum)
51 * bit 9..10 - Alternate Function Selection
52 * bit 11..12 - Pull up/down state
53 * bit 13 - Sleep mode behaviour
54 * bit 14 - Direction
55 * bit 15 - Value (if output)
56 * bit 16..18 - SLPM pull up/down state
57 * bit 19..20 - SLPM direction
58 * bit 21..22 - SLPM Value (if output)
59 * bit 23..25 - PDIS value (if input)
60 * bit 26 - Gpio mode
61 * bit 27 - Sleep mode
62 *
63 * to facilitate the definition, the following macros are provided
64 *
65 * PIN_CFG_DEFAULT - default config (0):
66 * pull up/down = disabled
67 * sleep mode = input/wakeup
68 * direction = input
69 * value = low
70 * SLPM direction = same as normal
71 * SLPM pull = same as normal
72 * SLPM value = same as normal
73 *
74 * PIN_CFG - default config with alternate function
75 */
76
77typedef unsigned long pin_cfg_t;
78
79#define PIN_NUM_MASK 0x1ff
80#define PIN_NUM(x) ((x) & PIN_NUM_MASK)
81
82#define PIN_ALT_SHIFT 9
83#define PIN_ALT_MASK (0x3 << PIN_ALT_SHIFT)
84#define PIN_ALT(x) (((x) & PIN_ALT_MASK) >> PIN_ALT_SHIFT)
85#define PIN_GPIO (NMK_GPIO_ALT_GPIO << PIN_ALT_SHIFT)
86#define PIN_ALT_A (NMK_GPIO_ALT_A << PIN_ALT_SHIFT)
87#define PIN_ALT_B (NMK_GPIO_ALT_B << PIN_ALT_SHIFT)
88#define PIN_ALT_C (NMK_GPIO_ALT_C << PIN_ALT_SHIFT)
89
90#define PIN_PULL_SHIFT 11
91#define PIN_PULL_MASK (0x3 << PIN_PULL_SHIFT)
92#define PIN_PULL(x) (((x) & PIN_PULL_MASK) >> PIN_PULL_SHIFT)
93#define PIN_PULL_NONE (NMK_GPIO_PULL_NONE << PIN_PULL_SHIFT)
94#define PIN_PULL_UP (NMK_GPIO_PULL_UP << PIN_PULL_SHIFT)
95#define PIN_PULL_DOWN (NMK_GPIO_PULL_DOWN << PIN_PULL_SHIFT)
96
97#define PIN_SLPM_SHIFT 13
98#define PIN_SLPM_MASK (0x1 << PIN_SLPM_SHIFT)
99#define PIN_SLPM(x) (((x) & PIN_SLPM_MASK) >> PIN_SLPM_SHIFT)
100#define PIN_SLPM_MAKE_INPUT (NMK_GPIO_SLPM_INPUT << PIN_SLPM_SHIFT)
101#define PIN_SLPM_NOCHANGE (NMK_GPIO_SLPM_NOCHANGE << PIN_SLPM_SHIFT)
102/* These two replace the above in DB8500v2+ */
103#define PIN_SLPM_WAKEUP_ENABLE (NMK_GPIO_SLPM_WAKEUP_ENABLE << PIN_SLPM_SHIFT)
104#define PIN_SLPM_WAKEUP_DISABLE (NMK_GPIO_SLPM_WAKEUP_DISABLE << PIN_SLPM_SHIFT)
105#define PIN_SLPM_USE_MUX_SETTINGS_IN_SLEEP PIN_SLPM_WAKEUP_DISABLE
106
107#define PIN_SLPM_GPIO PIN_SLPM_WAKEUP_ENABLE /* In SLPM, pin is a gpio */
108#define PIN_SLPM_ALTFUNC PIN_SLPM_WAKEUP_DISABLE /* In SLPM, pin is altfunc */
109
110#define PIN_DIR_SHIFT 14
111#define PIN_DIR_MASK (0x1 << PIN_DIR_SHIFT)
112#define PIN_DIR(x) (((x) & PIN_DIR_MASK) >> PIN_DIR_SHIFT)
113#define PIN_DIR_INPUT (0 << PIN_DIR_SHIFT)
114#define PIN_DIR_OUTPUT (1 << PIN_DIR_SHIFT)
115
116#define PIN_VAL_SHIFT 15
117#define PIN_VAL_MASK (0x1 << PIN_VAL_SHIFT)
118#define PIN_VAL(x) (((x) & PIN_VAL_MASK) >> PIN_VAL_SHIFT)
119#define PIN_VAL_LOW (0 << PIN_VAL_SHIFT)
120#define PIN_VAL_HIGH (1 << PIN_VAL_SHIFT)
121
122#define PIN_SLPM_PULL_SHIFT 16
123#define PIN_SLPM_PULL_MASK (0x7 << PIN_SLPM_PULL_SHIFT)
124#define PIN_SLPM_PULL(x) \
125 (((x) & PIN_SLPM_PULL_MASK) >> PIN_SLPM_PULL_SHIFT)
126#define PIN_SLPM_PULL_NONE \
127 ((1 + NMK_GPIO_PULL_NONE) << PIN_SLPM_PULL_SHIFT)
128#define PIN_SLPM_PULL_UP \
129 ((1 + NMK_GPIO_PULL_UP) << PIN_SLPM_PULL_SHIFT)
130#define PIN_SLPM_PULL_DOWN \
131 ((1 + NMK_GPIO_PULL_DOWN) << PIN_SLPM_PULL_SHIFT)
132
133#define PIN_SLPM_DIR_SHIFT 19
134#define PIN_SLPM_DIR_MASK (0x3 << PIN_SLPM_DIR_SHIFT)
135#define PIN_SLPM_DIR(x) \
136 (((x) & PIN_SLPM_DIR_MASK) >> PIN_SLPM_DIR_SHIFT)
137#define PIN_SLPM_DIR_INPUT ((1 + 0) << PIN_SLPM_DIR_SHIFT)
138#define PIN_SLPM_DIR_OUTPUT ((1 + 1) << PIN_SLPM_DIR_SHIFT)
139
140#define PIN_SLPM_VAL_SHIFT 21
141#define PIN_SLPM_VAL_MASK (0x3 << PIN_SLPM_VAL_SHIFT)
142#define PIN_SLPM_VAL(x) \
143 (((x) & PIN_SLPM_VAL_MASK) >> PIN_SLPM_VAL_SHIFT)
144#define PIN_SLPM_VAL_LOW ((1 + 0) << PIN_SLPM_VAL_SHIFT)
145#define PIN_SLPM_VAL_HIGH ((1 + 1) << PIN_SLPM_VAL_SHIFT)
146
147#define PIN_SLPM_PDIS_SHIFT 23
148#define PIN_SLPM_PDIS_MASK (0x3 << PIN_SLPM_PDIS_SHIFT)
149#define PIN_SLPM_PDIS(x) \
150 (((x) & PIN_SLPM_PDIS_MASK) >> PIN_SLPM_PDIS_SHIFT)
151#define PIN_SLPM_PDIS_NO_CHANGE (0 << PIN_SLPM_PDIS_SHIFT)
152#define PIN_SLPM_PDIS_DISABLED (1 << PIN_SLPM_PDIS_SHIFT)
153#define PIN_SLPM_PDIS_ENABLED (2 << PIN_SLPM_PDIS_SHIFT)
154
155#define PIN_LOWEMI_SHIFT 25
156#define PIN_LOWEMI_MASK (0x1 << PIN_LOWEMI_SHIFT)
157#define PIN_LOWEMI(x) (((x) & PIN_LOWEMI_MASK) >> PIN_LOWEMI_SHIFT)
158#define PIN_LOWEMI_DISABLED (0 << PIN_LOWEMI_SHIFT)
159#define PIN_LOWEMI_ENABLED (1 << PIN_LOWEMI_SHIFT)
160
161#define PIN_GPIOMODE_SHIFT 26
162#define PIN_GPIOMODE_MASK (0x1 << PIN_GPIOMODE_SHIFT)
163#define PIN_GPIOMODE(x) (((x) & PIN_GPIOMODE_MASK) >> PIN_GPIOMODE_SHIFT)
164#define PIN_GPIOMODE_DISABLED (0 << PIN_GPIOMODE_SHIFT)
165#define PIN_GPIOMODE_ENABLED (1 << PIN_GPIOMODE_SHIFT)
166
167#define PIN_SLEEPMODE_SHIFT 27
168#define PIN_SLEEPMODE_MASK (0x1 << PIN_SLEEPMODE_SHIFT)
169#define PIN_SLEEPMODE(x) (((x) & PIN_SLEEPMODE_MASK) >> PIN_SLEEPMODE_SHIFT)
170#define PIN_SLEEPMODE_DISABLED (0 << PIN_SLEEPMODE_SHIFT)
171#define PIN_SLEEPMODE_ENABLED (1 << PIN_SLEEPMODE_SHIFT)
172
173
174/* Shortcuts. Use these instead of separate DIR, PULL, and VAL. */
175#define PIN_INPUT_PULLDOWN (PIN_DIR_INPUT | PIN_PULL_DOWN)
176#define PIN_INPUT_PULLUP (PIN_DIR_INPUT | PIN_PULL_UP)
177#define PIN_INPUT_NOPULL (PIN_DIR_INPUT | PIN_PULL_NONE)
178#define PIN_OUTPUT_LOW (PIN_DIR_OUTPUT | PIN_VAL_LOW)
179#define PIN_OUTPUT_HIGH (PIN_DIR_OUTPUT | PIN_VAL_HIGH)
180
181#define PIN_SLPM_INPUT_PULLDOWN (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_DOWN)
182#define PIN_SLPM_INPUT_PULLUP (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_UP)
183#define PIN_SLPM_INPUT_NOPULL (PIN_SLPM_DIR_INPUT | PIN_SLPM_PULL_NONE)
184#define PIN_SLPM_OUTPUT_LOW (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_LOW)
185#define PIN_SLPM_OUTPUT_HIGH (PIN_SLPM_DIR_OUTPUT | PIN_SLPM_VAL_HIGH)
186
187#define PIN_CFG_DEFAULT (0)
188
189#define PIN_CFG(num, alt) \
190 (PIN_CFG_DEFAULT |\
191 (PIN_NUM(num) | PIN_##alt))
192
193#define PIN_CFG_INPUT(num, alt, pull) \
194 (PIN_CFG_DEFAULT |\
195 (PIN_NUM(num) | PIN_##alt | PIN_INPUT_##pull))
196
197#define PIN_CFG_OUTPUT(num, alt, val) \
198 (PIN_CFG_DEFAULT |\
199 (PIN_NUM(num) | PIN_##alt | PIN_OUTPUT_##val))
200
201/*
202 * "nmk_gpio" and "NMK_GPIO" stand for "Nomadik GPIO", leaving
203 * the "gpio" namespace for generic and cross-machine functions
204 */
205
206#define GPIO_BLOCK_SHIFT 5
207#define NMK_GPIO_PER_CHIP (1 << GPIO_BLOCK_SHIFT)
208
209/* Register in the logic block */
210#define NMK_GPIO_DAT 0x00
211#define NMK_GPIO_DATS 0x04
212#define NMK_GPIO_DATC 0x08
213#define NMK_GPIO_PDIS 0x0c
214#define NMK_GPIO_DIR 0x10
215#define NMK_GPIO_DIRS 0x14
216#define NMK_GPIO_DIRC 0x18
217#define NMK_GPIO_SLPC 0x1c
218#define NMK_GPIO_AFSLA 0x20
219#define NMK_GPIO_AFSLB 0x24
220#define NMK_GPIO_LOWEMI 0x28
221
222#define NMK_GPIO_RIMSC 0x40
223#define NMK_GPIO_FIMSC 0x44
224#define NMK_GPIO_IS 0x48
225#define NMK_GPIO_IC 0x4c
226#define NMK_GPIO_RWIMSC 0x50
227#define NMK_GPIO_FWIMSC 0x54
228#define NMK_GPIO_WKS 0x58
229/* These appear in DB8540 and later ASICs */
230#define NMK_GPIO_EDGELEVEL 0x5C
231#define NMK_GPIO_LEVEL 0x60
232
233
234/* Pull up/down values */
235enum nmk_gpio_pull {
236 NMK_GPIO_PULL_NONE,
237 NMK_GPIO_PULL_UP,
238 NMK_GPIO_PULL_DOWN,
239};
240
241/* Sleep mode */
242enum nmk_gpio_slpm {
243 NMK_GPIO_SLPM_INPUT,
244 NMK_GPIO_SLPM_WAKEUP_ENABLE = NMK_GPIO_SLPM_INPUT,
245 NMK_GPIO_SLPM_NOCHANGE,
246 NMK_GPIO_SLPM_WAKEUP_DISABLE = NMK_GPIO_SLPM_NOCHANGE,
247};
248
249/*
250 * Platform data to register a block: only the initial gpio/irq number.
251 */
252struct nmk_gpio_platform_data {
253 char *name;
254 int first_gpio;
255 int first_irq;
256 int num_gpio;
257 u32 (*get_secondary_status)(unsigned int bank);
258 void (*set_ioforce)(bool enable);
259 bool supports_sleepmode;
260};
261
48struct nmk_gpio_chip { 262struct nmk_gpio_chip {
49 struct gpio_chip chip; 263 struct gpio_chip chip;
50 struct irq_domain *domain; 264 struct irq_domain *domain;
@@ -1026,7 +1240,7 @@ static const struct irq_domain_ops nmk_gpio_irq_simple_ops = {
1026 1240
1027static int nmk_gpio_probe(struct platform_device *dev) 1241static int nmk_gpio_probe(struct platform_device *dev)
1028{ 1242{
1029 struct nmk_gpio_platform_data *pdata = dev->dev.platform_data; 1243 struct nmk_gpio_platform_data *pdata;
1030 struct device_node *np = dev->dev.of_node; 1244 struct device_node *np = dev->dev.of_node;
1031 struct nmk_gpio_chip *nmk_chip; 1245 struct nmk_gpio_chip *nmk_chip;
1032 struct gpio_chip *chip; 1246 struct gpio_chip *chip;
@@ -1034,32 +1248,24 @@ static int nmk_gpio_probe(struct platform_device *dev)
1034 struct clk *clk; 1248 struct clk *clk;
1035 int secondary_irq; 1249 int secondary_irq;
1036 void __iomem *base; 1250 void __iomem *base;
1037 int irq_start = 0;
1038 int irq; 1251 int irq;
1039 int ret; 1252 int ret;
1040 1253
1041 if (!pdata && !np) { 1254 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1042 dev_err(&dev->dev, "No platform data or device tree found\n"); 1255 if (!pdata)
1043 return -ENODEV; 1256 return -ENOMEM;
1044 }
1045
1046 if (np) {
1047 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL);
1048 if (!pdata)
1049 return -ENOMEM;
1050
1051 if (of_get_property(np, "st,supports-sleepmode", NULL))
1052 pdata->supports_sleepmode = true;
1053 1257
1054 if (of_property_read_u32(np, "gpio-bank", &dev->id)) { 1258 if (of_get_property(np, "st,supports-sleepmode", NULL))
1055 dev_err(&dev->dev, "gpio-bank property not found\n"); 1259 pdata->supports_sleepmode = true;
1056 return -EINVAL;
1057 }
1058 1260
1059 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP; 1261 if (of_property_read_u32(np, "gpio-bank", &dev->id)) {
1060 pdata->num_gpio = NMK_GPIO_PER_CHIP; 1262 dev_err(&dev->dev, "gpio-bank property not found\n");
1263 return -EINVAL;
1061 } 1264 }
1062 1265
1266 pdata->first_gpio = dev->id * NMK_GPIO_PER_CHIP;
1267 pdata->num_gpio = NMK_GPIO_PER_CHIP;
1268
1063 irq = platform_get_irq(dev, 0); 1269 irq = platform_get_irq(dev, 0);
1064 if (irq < 0) 1270 if (irq < 0)
1065 return irq; 1271 return irq;
@@ -1107,10 +1313,7 @@ static int nmk_gpio_probe(struct platform_device *dev)
1107 clk_enable(nmk_chip->clk); 1313 clk_enable(nmk_chip->clk);
1108 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI); 1314 nmk_chip->lowemi = readl_relaxed(nmk_chip->addr + NMK_GPIO_LOWEMI);
1109 clk_disable(nmk_chip->clk); 1315 clk_disable(nmk_chip->clk);
1110
1111#ifdef CONFIG_OF_GPIO
1112 chip->of_node = np; 1316 chip->of_node = np;
1113#endif
1114 1317
1115 ret = gpiochip_add(&nmk_chip->chip); 1318 ret = gpiochip_add(&nmk_chip->chip);
1116 if (ret) 1319 if (ret)
@@ -1122,10 +1325,8 @@ static int nmk_gpio_probe(struct platform_device *dev)
1122 1325
1123 platform_set_drvdata(dev, nmk_chip); 1326 platform_set_drvdata(dev, nmk_chip);
1124 1327
1125 if (!np)
1126 irq_start = pdata->first_irq;
1127 nmk_chip->domain = irq_domain_add_simple(np, 1328 nmk_chip->domain = irq_domain_add_simple(np,
1128 NMK_GPIO_PER_CHIP, irq_start, 1329 NMK_GPIO_PER_CHIP, 0,
1129 &nmk_gpio_irq_simple_ops, nmk_chip); 1330 &nmk_gpio_irq_simple_ops, nmk_chip);
1130 if (!nmk_chip->domain) { 1331 if (!nmk_chip->domain) {
1131 dev_err(&dev->dev, "failed to create irqdomain\n"); 1332 dev_err(&dev->dev, "failed to create irqdomain\n");
@@ -1858,11 +2059,10 @@ static int nmk_pinctrl_resume(struct platform_device *pdev)
1858 2059
1859static int nmk_pinctrl_probe(struct platform_device *pdev) 2060static int nmk_pinctrl_probe(struct platform_device *pdev)
1860{ 2061{
1861 const struct platform_device_id *platid = platform_get_device_id(pdev); 2062 const struct of_device_id *match;
1862 struct device_node *np = pdev->dev.of_node; 2063 struct device_node *np = pdev->dev.of_node;
1863 struct device_node *prcm_np; 2064 struct device_node *prcm_np;
1864 struct nmk_pinctrl *npct; 2065 struct nmk_pinctrl *npct;
1865 struct resource *res;
1866 unsigned int version = 0; 2066 unsigned int version = 0;
1867 int i; 2067 int i;
1868 2068
@@ -1870,16 +2070,10 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
1870 if (!npct) 2070 if (!npct)
1871 return -ENOMEM; 2071 return -ENOMEM;
1872 2072
1873 if (platid) 2073 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1874 version = platid->driver_data; 2074 if (!match)
1875 else if (np) { 2075 return -ENODEV;
1876 const struct of_device_id *match; 2076 version = (unsigned int) match->data;
1877
1878 match = of_match_device(nmk_pinctrl_match, &pdev->dev);
1879 if (!match)
1880 return -ENODEV;
1881 version = (unsigned int) match->data;
1882 }
1883 2077
1884 /* Poke in other ASIC variants here */ 2078 /* Poke in other ASIC variants here */
1885 if (version == PINCTRL_NMK_STN8815) 2079 if (version == PINCTRL_NMK_STN8815)
@@ -1889,17 +2083,9 @@ static int nmk_pinctrl_probe(struct platform_device *pdev)
1889 if (version == PINCTRL_NMK_DB8540) 2083 if (version == PINCTRL_NMK_DB8540)
1890 nmk_pinctrl_db8540_init(&npct->soc); 2084 nmk_pinctrl_db8540_init(&npct->soc);
1891 2085
1892 if (np) { 2086 prcm_np = of_parse_phandle(np, "prcm", 0);
1893 prcm_np = of_parse_phandle(np, "prcm", 0); 2087 if (prcm_np)
1894 if (prcm_np) 2088 npct->prcm_base = of_iomap(prcm_np, 0);
1895 npct->prcm_base = of_iomap(prcm_np, 0);
1896 }
1897
1898 /* Allow platform passed information to over-write DT. */
1899 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1900 if (res)
1901 npct->prcm_base = devm_ioremap(&pdev->dev, res->start,
1902 resource_size(res));
1903 if (!npct->prcm_base) { 2089 if (!npct->prcm_base) {
1904 if (version == PINCTRL_NMK_STN8815) { 2090 if (version == PINCTRL_NMK_STN8815) {
1905 dev_info(&pdev->dev, 2091 dev_info(&pdev->dev,
@@ -1958,13 +2144,6 @@ static struct platform_driver nmk_gpio_driver = {
1958 .probe = nmk_gpio_probe, 2144 .probe = nmk_gpio_probe,
1959}; 2145};
1960 2146
1961static const struct platform_device_id nmk_pinctrl_id[] = {
1962 { "pinctrl-stn8815", PINCTRL_NMK_STN8815 },
1963 { "pinctrl-db8500", PINCTRL_NMK_DB8500 },
1964 { "pinctrl-db8540", PINCTRL_NMK_DB8540 },
1965 { }
1966};
1967
1968static struct platform_driver nmk_pinctrl_driver = { 2147static struct platform_driver nmk_pinctrl_driver = {
1969 .driver = { 2148 .driver = {
1970 .owner = THIS_MODULE, 2149 .owner = THIS_MODULE,
@@ -1972,7 +2151,6 @@ static struct platform_driver nmk_pinctrl_driver = {
1972 .of_match_table = nmk_pinctrl_match, 2151 .of_match_table = nmk_pinctrl_match,
1973 }, 2152 },
1974 .probe = nmk_pinctrl_probe, 2153 .probe = nmk_pinctrl_probe,
1975 .id_table = nmk_pinctrl_id,
1976#ifdef CONFIG_PM 2154#ifdef CONFIG_PM
1977 .suspend = nmk_pinctrl_suspend, 2155 .suspend = nmk_pinctrl_suspend,
1978 .resume = nmk_pinctrl_resume, 2156 .resume = nmk_pinctrl_resume,
diff --git a/drivers/pinctrl/pinctrl-nomadik.h b/drivers/pinctrl/pinctrl-nomadik.h
index bcd4191e10ea..d8215f1e70c7 100644
--- a/drivers/pinctrl/pinctrl-nomadik.h
+++ b/drivers/pinctrl/pinctrl-nomadik.h
@@ -1,13 +1,23 @@
1#ifndef PINCTRL_PINCTRL_NOMADIK_H 1#ifndef PINCTRL_PINCTRL_NOMADIK_H
2#define PINCTRL_PINCTRL_NOMADIK_H 2#define PINCTRL_PINCTRL_NOMADIK_H
3 3
4#include <linux/platform_data/pinctrl-nomadik.h>
5
6/* Package definitions */ 4/* Package definitions */
7#define PINCTRL_NMK_STN8815 0 5#define PINCTRL_NMK_STN8815 0
8#define PINCTRL_NMK_DB8500 1 6#define PINCTRL_NMK_DB8500 1
9#define PINCTRL_NMK_DB8540 2 7#define PINCTRL_NMK_DB8540 2
10 8
9/* Alternate functions: function C is set in hw by setting both A and B */
10#define NMK_GPIO_ALT_GPIO 0
11#define NMK_GPIO_ALT_A 1
12#define NMK_GPIO_ALT_B 2
13#define NMK_GPIO_ALT_C (NMK_GPIO_ALT_A | NMK_GPIO_ALT_B)
14
15#define NMK_GPIO_ALT_CX_SHIFT 2
16#define NMK_GPIO_ALT_C1 ((1<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
17#define NMK_GPIO_ALT_C2 ((2<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
18#define NMK_GPIO_ALT_C3 ((3<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
19#define NMK_GPIO_ALT_C4 ((4<<NMK_GPIO_ALT_CX_SHIFT) | NMK_GPIO_ALT_C)
20
11#define PRCM_GPIOCR_ALTCX(pin_num,\ 21#define PRCM_GPIOCR_ALTCX(pin_num,\
12 altc1_used, altc1_ri, altc1_cb,\ 22 altc1_used, altc1_ri, altc1_cb,\
13 altc2_used, altc2_ri, altc2_cb,\ 23 altc2_used, altc2_ri, altc2_cb,\
diff --git a/drivers/usb/gadget/atmel_usba_udc.c b/drivers/usb/gadget/atmel_usba_udc.c
index 2cb52e0438df..9f71d9fdcc14 100644
--- a/drivers/usb/gadget/atmel_usba_udc.c
+++ b/drivers/usb/gadget/atmel_usba_udc.c
@@ -326,7 +326,7 @@ static int vbus_is_present(struct usba_udc *udc)
326 326
327#if defined(CONFIG_ARCH_AT91SAM9RL) 327#if defined(CONFIG_ARCH_AT91SAM9RL)
328 328
329#include <mach/at91_pmc.h> 329#include <linux/clk/at91_pmc.h>
330 330
331static void toggle_bias(int is_on) 331static void toggle_bias(int is_on)
332{ 332{
generated by cgit v1.2.2 (git 2.25.0) at 2024-09-21 00:21:28 -0400