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-rw-r--r--drivers/char/hw_random/Kconfig14
-rw-r--r--drivers/char/hw_random/Makefile1
-rw-r--r--drivers/char/hw_random/bcm63xx-rng.c175
-rw-r--r--drivers/i2c/busses/i2c-octeon.c92
-rw-r--r--drivers/mtd/nand/jz4740_nand.c228
-rw-r--r--drivers/net/ethernet/octeon/octeon_mgmt.c312
-rw-r--r--drivers/net/phy/mdio-octeon.c92
-rw-r--r--drivers/spi/Kconfig9
-rw-r--r--drivers/spi/Makefile1
-rw-r--r--drivers/spi/spi-falcon.c469
-rw-r--r--drivers/staging/octeon/ethernet-mdio.c28
-rw-r--r--drivers/staging/octeon/ethernet.c153
-rw-r--r--drivers/staging/octeon/octeon-ethernet.h3
13 files changed, 1292 insertions, 285 deletions
diff --git a/drivers/char/hw_random/Kconfig b/drivers/char/hw_random/Kconfig
index f45dad39a18b..6640311ff1c9 100644
--- a/drivers/char/hw_random/Kconfig
+++ b/drivers/char/hw_random/Kconfig
@@ -73,6 +73,20 @@ config HW_RANDOM_ATMEL
73 73
74 If unsure, say Y. 74 If unsure, say Y.
75 75
76config HW_RANDOM_BCM63XX
77 tristate "Broadcom BCM63xx Random Number Generator support"
78 depends on HW_RANDOM && BCM63XX
79 default HW_RANDOM
80 ---help---
81 This driver provides kernel-side support for the Random Number
82 Generator hardware found on the Broadcom BCM63xx SoCs.
83
84 To compile this driver as a module, choose M here: the
85 module will be called bcm63xx-rng
86
87 If unusure, say Y.
88
89
76config HW_RANDOM_GEODE 90config HW_RANDOM_GEODE
77 tristate "AMD Geode HW Random Number Generator support" 91 tristate "AMD Geode HW Random Number Generator support"
78 depends on HW_RANDOM && X86_32 && PCI 92 depends on HW_RANDOM && X86_32 && PCI
diff --git a/drivers/char/hw_random/Makefile b/drivers/char/hw_random/Makefile
index d901dfa30321..67f57bf239e4 100644
--- a/drivers/char/hw_random/Makefile
+++ b/drivers/char/hw_random/Makefile
@@ -8,6 +8,7 @@ obj-$(CONFIG_HW_RANDOM_TIMERIOMEM) += timeriomem-rng.o
8obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o 8obj-$(CONFIG_HW_RANDOM_INTEL) += intel-rng.o
9obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o 9obj-$(CONFIG_HW_RANDOM_AMD) += amd-rng.o
10obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o 10obj-$(CONFIG_HW_RANDOM_ATMEL) += atmel-rng.o
11obj-$(CONFIG_HW_RANDOM_BCM63XX) += bcm63xx-rng.o
11obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o 12obj-$(CONFIG_HW_RANDOM_GEODE) += geode-rng.o
12obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o 13obj-$(CONFIG_HW_RANDOM_N2RNG) += n2-rng.o
13n2-rng-y := n2-drv.o n2-asm.o 14n2-rng-y := n2-drv.o n2-asm.o
diff --git a/drivers/char/hw_random/bcm63xx-rng.c b/drivers/char/hw_random/bcm63xx-rng.c
new file mode 100644
index 000000000000..aec6a4277caa
--- /dev/null
+++ b/drivers/char/hw_random/bcm63xx-rng.c
@@ -0,0 +1,175 @@
1/*
2 * Broadcom BCM63xx Random Number Generator support
3 *
4 * Copyright (C) 2011, Florian Fainelli <florian@openwrt.org>
5 * Copyright (C) 2009, Broadcom Corporation
6 *
7 */
8#include <linux/module.h>
9#include <linux/slab.h>
10#include <linux/io.h>
11#include <linux/err.h>
12#include <linux/clk.h>
13#include <linux/platform_device.h>
14#include <linux/hw_random.h>
15
16#include <bcm63xx_io.h>
17#include <bcm63xx_regs.h>
18
19struct bcm63xx_rng_priv {
20 struct clk *clk;
21 void __iomem *regs;
22};
23
24#define to_rng_priv(rng) ((struct bcm63xx_rng_priv *)rng->priv)
25
26static int bcm63xx_rng_init(struct hwrng *rng)
27{
28 struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
29 u32 val;
30
31 val = bcm_readl(priv->regs + RNG_CTRL);
32 val |= RNG_EN;
33 bcm_writel(val, priv->regs + RNG_CTRL);
34
35 return 0;
36}
37
38static void bcm63xx_rng_cleanup(struct hwrng *rng)
39{
40 struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
41 u32 val;
42
43 val = bcm_readl(priv->regs + RNG_CTRL);
44 val &= ~RNG_EN;
45 bcm_writel(val, priv->regs + RNG_CTRL);
46}
47
48static int bcm63xx_rng_data_present(struct hwrng *rng, int wait)
49{
50 struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
51
52 return bcm_readl(priv->regs + RNG_STAT) & RNG_AVAIL_MASK;
53}
54
55static int bcm63xx_rng_data_read(struct hwrng *rng, u32 *data)
56{
57 struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
58
59 *data = bcm_readl(priv->regs + RNG_DATA);
60
61 return 4;
62}
63
64static int __devinit bcm63xx_rng_probe(struct platform_device *pdev)
65{
66 struct resource *r;
67 struct clk *clk;
68 int ret;
69 struct bcm63xx_rng_priv *priv;
70 struct hwrng *rng;
71
72 r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
73 if (!r) {
74 dev_err(&pdev->dev, "no iomem resource\n");
75 ret = -ENXIO;
76 goto out;
77 }
78
79 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
80 if (!priv) {
81 dev_err(&pdev->dev, "no memory for private structure\n");
82 ret = -ENOMEM;
83 goto out;
84 }
85
86 rng = kzalloc(sizeof(*rng), GFP_KERNEL);
87 if (!rng) {
88 dev_err(&pdev->dev, "no memory for rng structure\n");
89 ret = -ENOMEM;
90 goto out_free_priv;
91 }
92
93 platform_set_drvdata(pdev, rng);
94 rng->priv = (unsigned long)priv;
95 rng->name = pdev->name;
96 rng->init = bcm63xx_rng_init;
97 rng->cleanup = bcm63xx_rng_cleanup;
98 rng->data_present = bcm63xx_rng_data_present;
99 rng->data_read = bcm63xx_rng_data_read;
100
101 clk = clk_get(&pdev->dev, "ipsec");
102 if (IS_ERR(clk)) {
103 dev_err(&pdev->dev, "no clock for device\n");
104 ret = PTR_ERR(clk);
105 goto out_free_rng;
106 }
107
108 priv->clk = clk;
109
110 if (!devm_request_mem_region(&pdev->dev, r->start,
111 resource_size(r), pdev->name)) {
112 dev_err(&pdev->dev, "request mem failed");
113 ret = -ENOMEM;
114 goto out_free_rng;
115 }
116
117 priv->regs = devm_ioremap_nocache(&pdev->dev, r->start,
118 resource_size(r));
119 if (!priv->regs) {
120 dev_err(&pdev->dev, "ioremap failed");
121 ret = -ENOMEM;
122 goto out_free_rng;
123 }
124
125 clk_enable(clk);
126
127 ret = hwrng_register(rng);
128 if (ret) {
129 dev_err(&pdev->dev, "failed to register rng device\n");
130 goto out_clk_disable;
131 }
132
133 dev_info(&pdev->dev, "registered RNG driver\n");
134
135 return 0;
136
137out_clk_disable:
138 clk_disable(clk);
139out_free_rng:
140 platform_set_drvdata(pdev, NULL);
141 kfree(rng);
142out_free_priv:
143 kfree(priv);
144out:
145 return ret;
146}
147
148static int __devexit bcm63xx_rng_remove(struct platform_device *pdev)
149{
150 struct hwrng *rng = platform_get_drvdata(pdev);
151 struct bcm63xx_rng_priv *priv = to_rng_priv(rng);
152
153 hwrng_unregister(rng);
154 clk_disable(priv->clk);
155 kfree(priv);
156 kfree(rng);
157 platform_set_drvdata(pdev, NULL);
158
159 return 0;
160}
161
162static struct platform_driver bcm63xx_rng_driver = {
163 .probe = bcm63xx_rng_probe,
164 .remove = __devexit_p(bcm63xx_rng_remove),
165 .driver = {
166 .name = "bcm63xx-rng",
167 .owner = THIS_MODULE,
168 },
169};
170
171module_platform_driver(bcm63xx_rng_driver);
172
173MODULE_AUTHOR("Florian Fainelli <florian@openwrt.org>");
174MODULE_DESCRIPTION("Broadcom BCM63xx RNG driver");
175MODULE_LICENSE("GPL");
diff --git a/drivers/i2c/busses/i2c-octeon.c b/drivers/i2c/busses/i2c-octeon.c
index ee139a598814..f44c83549fe5 100644
--- a/drivers/i2c/busses/i2c-octeon.c
+++ b/drivers/i2c/busses/i2c-octeon.c
@@ -2,7 +2,7 @@
2 * (C) Copyright 2009-2010 2 * (C) Copyright 2009-2010
3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com 3 * Nokia Siemens Networks, michael.lawnick.ext@nsn.com
4 * 4 *
5 * Portions Copyright (C) 2010 Cavium Networks, Inc. 5 * Portions Copyright (C) 2010, 2011 Cavium Networks, Inc.
6 * 6 *
7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors. 7 * This is a driver for the i2c adapter in Cavium Networks' OCTEON processors.
8 * 8 *
@@ -11,17 +11,18 @@
11 * warranty of any kind, whether express or implied. 11 * warranty of any kind, whether express or implied.
12 */ 12 */
13 13
14#include <linux/platform_device.h>
15#include <linux/interrupt.h>
14#include <linux/kernel.h> 16#include <linux/kernel.h>
15#include <linux/module.h> 17#include <linux/module.h>
18#include <linux/of_i2c.h>
19#include <linux/delay.h>
16#include <linux/sched.h> 20#include <linux/sched.h>
17#include <linux/slab.h> 21#include <linux/slab.h>
18#include <linux/init.h> 22#include <linux/init.h>
19
20#include <linux/io.h>
21#include <linux/i2c.h> 23#include <linux/i2c.h>
22#include <linux/interrupt.h> 24#include <linux/io.h>
23#include <linux/delay.h> 25#include <linux/of.h>
24#include <linux/platform_device.h>
25 26
26#include <asm/octeon/octeon.h> 27#include <asm/octeon/octeon.h>
27 28
@@ -65,7 +66,7 @@ struct octeon_i2c {
65 wait_queue_head_t queue; 66 wait_queue_head_t queue;
66 struct i2c_adapter adap; 67 struct i2c_adapter adap;
67 int irq; 68 int irq;
68 int twsi_freq; 69 u32 twsi_freq;
69 int sys_freq; 70 int sys_freq;
70 resource_size_t twsi_phys; 71 resource_size_t twsi_phys;
71 void __iomem *twsi_base; 72 void __iomem *twsi_base;
@@ -121,10 +122,8 @@ static u8 octeon_i2c_read_sw(struct octeon_i2c *i2c, u64 eop_reg)
121 */ 122 */
122static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data) 123static void octeon_i2c_write_int(struct octeon_i2c *i2c, u64 data)
123{ 124{
124 u64 tmp;
125
126 __raw_writeq(data, i2c->twsi_base + TWSI_INT); 125 __raw_writeq(data, i2c->twsi_base + TWSI_INT);
127 tmp = __raw_readq(i2c->twsi_base + TWSI_INT); 126 __raw_readq(i2c->twsi_base + TWSI_INT);
128} 127}
129 128
130/** 129/**
@@ -515,7 +514,6 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev)
515{ 514{
516 int irq, result = 0; 515 int irq, result = 0;
517 struct octeon_i2c *i2c; 516 struct octeon_i2c *i2c;
518 struct octeon_i2c_data *i2c_data;
519 struct resource *res_mem; 517 struct resource *res_mem;
520 518
521 /* All adaptors have an irq. */ 519 /* All adaptors have an irq. */
@@ -523,86 +521,90 @@ static int __devinit octeon_i2c_probe(struct platform_device *pdev)
523 if (irq < 0) 521 if (irq < 0)
524 return irq; 522 return irq;
525 523
526 i2c = kzalloc(sizeof(*i2c), GFP_KERNEL); 524 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
527 if (!i2c) { 525 if (!i2c) {
528 dev_err(&pdev->dev, "kzalloc failed\n"); 526 dev_err(&pdev->dev, "kzalloc failed\n");
529 result = -ENOMEM; 527 result = -ENOMEM;
530 goto out; 528 goto out;
531 } 529 }
532 i2c->dev = &pdev->dev; 530 i2c->dev = &pdev->dev;
533 i2c_data = pdev->dev.platform_data;
534 531
535 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 532 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
536 533
537 if (res_mem == NULL) { 534 if (res_mem == NULL) {
538 dev_err(i2c->dev, "found no memory resource\n"); 535 dev_err(i2c->dev, "found no memory resource\n");
539 result = -ENXIO; 536 result = -ENXIO;
540 goto fail_region; 537 goto out;
541 } 538 }
539 i2c->twsi_phys = res_mem->start;
540 i2c->regsize = resource_size(res_mem);
542 541
543 if (i2c_data == NULL) { 542 /*
544 dev_err(i2c->dev, "no I2C frequency data\n"); 543 * "clock-rate" is a legacy binding, the official binding is
544 * "clock-frequency". Try the official one first and then
545 * fall back if it doesn't exist.
546 */
547 if (of_property_read_u32(pdev->dev.of_node,
548 "clock-frequency", &i2c->twsi_freq) &&
549 of_property_read_u32(pdev->dev.of_node,
550 "clock-rate", &i2c->twsi_freq)) {
551 dev_err(i2c->dev,
552 "no I2C 'clock-rate' or 'clock-frequency' property\n");
545 result = -ENXIO; 553 result = -ENXIO;
546 goto fail_region; 554 goto out;
547 } 555 }
548 556
549 i2c->twsi_phys = res_mem->start; 557 i2c->sys_freq = octeon_get_io_clock_rate();
550 i2c->regsize = resource_size(res_mem);
551 i2c->twsi_freq = i2c_data->i2c_freq;
552 i2c->sys_freq = i2c_data->sys_freq;
553 558
554 if (!request_mem_region(i2c->twsi_phys, i2c->regsize, res_mem->name)) { 559 if (!devm_request_mem_region(&pdev->dev, i2c->twsi_phys, i2c->regsize,
560 res_mem->name)) {
555 dev_err(i2c->dev, "request_mem_region failed\n"); 561 dev_err(i2c->dev, "request_mem_region failed\n");
556 goto fail_region; 562 goto out;
557 } 563 }
558 i2c->twsi_base = ioremap(i2c->twsi_phys, i2c->regsize); 564 i2c->twsi_base = devm_ioremap(&pdev->dev, i2c->twsi_phys, i2c->regsize);
559 565
560 init_waitqueue_head(&i2c->queue); 566 init_waitqueue_head(&i2c->queue);
561 567
562 i2c->irq = irq; 568 i2c->irq = irq;
563 569
564 result = request_irq(i2c->irq, octeon_i2c_isr, 0, DRV_NAME, i2c); 570 result = devm_request_irq(&pdev->dev, i2c->irq,
571 octeon_i2c_isr, 0, DRV_NAME, i2c);
565 if (result < 0) { 572 if (result < 0) {
566 dev_err(i2c->dev, "failed to attach interrupt\n"); 573 dev_err(i2c->dev, "failed to attach interrupt\n");
567 goto fail_irq; 574 goto out;
568 } 575 }
569 576
570 result = octeon_i2c_initlowlevel(i2c); 577 result = octeon_i2c_initlowlevel(i2c);
571 if (result) { 578 if (result) {
572 dev_err(i2c->dev, "init low level failed\n"); 579 dev_err(i2c->dev, "init low level failed\n");
573 goto fail_add; 580 goto out;
574 } 581 }
575 582
576 result = octeon_i2c_setclock(i2c); 583 result = octeon_i2c_setclock(i2c);
577 if (result) { 584 if (result) {
578 dev_err(i2c->dev, "clock init failed\n"); 585 dev_err(i2c->dev, "clock init failed\n");
579 goto fail_add; 586 goto out;
580 } 587 }
581 588
582 i2c->adap = octeon_i2c_ops; 589 i2c->adap = octeon_i2c_ops;
583 i2c->adap.dev.parent = &pdev->dev; 590 i2c->adap.dev.parent = &pdev->dev;
584 i2c->adap.nr = pdev->id >= 0 ? pdev->id : 0; 591 i2c->adap.dev.of_node = pdev->dev.of_node;
585 i2c_set_adapdata(&i2c->adap, i2c); 592 i2c_set_adapdata(&i2c->adap, i2c);
586 platform_set_drvdata(pdev, i2c); 593 platform_set_drvdata(pdev, i2c);
587 594
588 result = i2c_add_numbered_adapter(&i2c->adap); 595 result = i2c_add_adapter(&i2c->adap);
589 if (result < 0) { 596 if (result < 0) {
590 dev_err(i2c->dev, "failed to add adapter\n"); 597 dev_err(i2c->dev, "failed to add adapter\n");
591 goto fail_add; 598 goto fail_add;
592 } 599 }
593
594 dev_info(i2c->dev, "version %s\n", DRV_VERSION); 600 dev_info(i2c->dev, "version %s\n", DRV_VERSION);
595 601
596 return result; 602 of_i2c_register_devices(&i2c->adap);
603
604 return 0;
597 605
598fail_add: 606fail_add:
599 platform_set_drvdata(pdev, NULL); 607 platform_set_drvdata(pdev, NULL);
600 free_irq(i2c->irq, i2c);
601fail_irq:
602 iounmap(i2c->twsi_base);
603 release_mem_region(i2c->twsi_phys, i2c->regsize);
604fail_region:
605 kfree(i2c);
606out: 608out:
607 return result; 609 return result;
608}; 610};
@@ -613,19 +615,24 @@ static int __devexit octeon_i2c_remove(struct platform_device *pdev)
613 615
614 i2c_del_adapter(&i2c->adap); 616 i2c_del_adapter(&i2c->adap);
615 platform_set_drvdata(pdev, NULL); 617 platform_set_drvdata(pdev, NULL);
616 free_irq(i2c->irq, i2c);
617 iounmap(i2c->twsi_base);
618 release_mem_region(i2c->twsi_phys, i2c->regsize);
619 kfree(i2c);
620 return 0; 618 return 0;
621}; 619};
622 620
621static struct of_device_id octeon_i2c_match[] = {
622 {
623 .compatible = "cavium,octeon-3860-twsi",
624 },
625 {},
626};
627MODULE_DEVICE_TABLE(of, octeon_i2c_match);
628
623static struct platform_driver octeon_i2c_driver = { 629static struct platform_driver octeon_i2c_driver = {
624 .probe = octeon_i2c_probe, 630 .probe = octeon_i2c_probe,
625 .remove = __devexit_p(octeon_i2c_remove), 631 .remove = __devexit_p(octeon_i2c_remove),
626 .driver = { 632 .driver = {
627 .owner = THIS_MODULE, 633 .owner = THIS_MODULE,
628 .name = DRV_NAME, 634 .name = DRV_NAME,
635 .of_match_table = octeon_i2c_match,
629 }, 636 },
630}; 637};
631 638
@@ -635,4 +642,3 @@ MODULE_AUTHOR("Michael Lawnick <michael.lawnick.ext@nsn.com>");
635MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors"); 642MODULE_DESCRIPTION("I2C-Bus adapter for Cavium OCTEON processors");
636MODULE_LICENSE("GPL"); 643MODULE_LICENSE("GPL");
637MODULE_VERSION(DRV_VERSION); 644MODULE_VERSION(DRV_VERSION);
638MODULE_ALIAS("platform:" DRV_NAME);
diff --git a/drivers/mtd/nand/jz4740_nand.c b/drivers/mtd/nand/jz4740_nand.c
index a6fa884ae49b..100b6775e175 100644
--- a/drivers/mtd/nand/jz4740_nand.c
+++ b/drivers/mtd/nand/jz4740_nand.c
@@ -52,9 +52,10 @@
52 52
53#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1) 53#define JZ_NAND_CTRL_ENABLE_CHIP(x) BIT((x) << 1)
54#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1) 54#define JZ_NAND_CTRL_ASSERT_CHIP(x) BIT(((x) << 1) + 1)
55#define JZ_NAND_CTRL_ASSERT_CHIP_MASK 0xaa
55 56
56#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
57#define JZ_NAND_MEM_CMD_OFFSET 0x08000 57#define JZ_NAND_MEM_CMD_OFFSET 0x08000
58#define JZ_NAND_MEM_ADDR_OFFSET 0x10000
58 59
59struct jz_nand { 60struct jz_nand {
60 struct mtd_info mtd; 61 struct mtd_info mtd;
@@ -62,8 +63,11 @@ struct jz_nand {
62 void __iomem *base; 63 void __iomem *base;
63 struct resource *mem; 64 struct resource *mem;
64 65
65 void __iomem *bank_base; 66 unsigned char banks[JZ_NAND_NUM_BANKS];
66 struct resource *bank_mem; 67 void __iomem *bank_base[JZ_NAND_NUM_BANKS];
68 struct resource *bank_mem[JZ_NAND_NUM_BANKS];
69
70 int selected_bank;
67 71
68 struct jz_nand_platform_data *pdata; 72 struct jz_nand_platform_data *pdata;
69 bool is_reading; 73 bool is_reading;
@@ -74,26 +78,50 @@ static inline struct jz_nand *mtd_to_jz_nand(struct mtd_info *mtd)
74 return container_of(mtd, struct jz_nand, mtd); 78 return container_of(mtd, struct jz_nand, mtd);
75} 79}
76 80
81static void jz_nand_select_chip(struct mtd_info *mtd, int chipnr)
82{
83 struct jz_nand *nand = mtd_to_jz_nand(mtd);
84 struct nand_chip *chip = mtd->priv;
85 uint32_t ctrl;
86 int banknr;
87
88 ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
89 ctrl &= ~JZ_NAND_CTRL_ASSERT_CHIP_MASK;
90
91 if (chipnr == -1) {
92 banknr = -1;
93 } else {
94 banknr = nand->banks[chipnr] - 1;
95 chip->IO_ADDR_R = nand->bank_base[banknr];
96 chip->IO_ADDR_W = nand->bank_base[banknr];
97 }
98 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
99
100 nand->selected_bank = banknr;
101}
102
77static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl) 103static void jz_nand_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
78{ 104{
79 struct jz_nand *nand = mtd_to_jz_nand(mtd); 105 struct jz_nand *nand = mtd_to_jz_nand(mtd);
80 struct nand_chip *chip = mtd->priv; 106 struct nand_chip *chip = mtd->priv;
81 uint32_t reg; 107 uint32_t reg;
108 void __iomem *bank_base = nand->bank_base[nand->selected_bank];
109
110 BUG_ON(nand->selected_bank < 0);
82 111
83 if (ctrl & NAND_CTRL_CHANGE) { 112 if (ctrl & NAND_CTRL_CHANGE) {
84 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE)); 113 BUG_ON((ctrl & NAND_ALE) && (ctrl & NAND_CLE));
85 if (ctrl & NAND_ALE) 114 if (ctrl & NAND_ALE)
86 chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_ADDR_OFFSET; 115 bank_base += JZ_NAND_MEM_ADDR_OFFSET;
87 else if (ctrl & NAND_CLE) 116 else if (ctrl & NAND_CLE)
88 chip->IO_ADDR_W = nand->bank_base + JZ_NAND_MEM_CMD_OFFSET; 117 bank_base += JZ_NAND_MEM_CMD_OFFSET;
89 else 118 chip->IO_ADDR_W = bank_base;
90 chip->IO_ADDR_W = nand->bank_base;
91 119
92 reg = readl(nand->base + JZ_REG_NAND_CTRL); 120 reg = readl(nand->base + JZ_REG_NAND_CTRL);
93 if (ctrl & NAND_NCE) 121 if (ctrl & NAND_NCE)
94 reg |= JZ_NAND_CTRL_ASSERT_CHIP(0); 122 reg |= JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
95 else 123 else
96 reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(0); 124 reg &= ~JZ_NAND_CTRL_ASSERT_CHIP(nand->selected_bank);
97 writel(reg, nand->base + JZ_REG_NAND_CTRL); 125 writel(reg, nand->base + JZ_REG_NAND_CTRL);
98 } 126 }
99 if (dat != NAND_CMD_NONE) 127 if (dat != NAND_CMD_NONE)
@@ -252,7 +280,7 @@ static int jz_nand_correct_ecc_rs(struct mtd_info *mtd, uint8_t *dat,
252} 280}
253 281
254static int jz_nand_ioremap_resource(struct platform_device *pdev, 282static int jz_nand_ioremap_resource(struct platform_device *pdev,
255 const char *name, struct resource **res, void __iomem **base) 283 const char *name, struct resource **res, void *__iomem *base)
256{ 284{
257 int ret; 285 int ret;
258 286
@@ -288,6 +316,90 @@ err:
288 return ret; 316 return ret;
289} 317}
290 318
319static inline void jz_nand_iounmap_resource(struct resource *res, void __iomem *base)
320{
321 iounmap(base);
322 release_mem_region(res->start, resource_size(res));
323}
324
325static int __devinit jz_nand_detect_bank(struct platform_device *pdev, struct jz_nand *nand, unsigned char bank, size_t chipnr, uint8_t *nand_maf_id, uint8_t *nand_dev_id) {
326 int ret;
327 int gpio;
328 char gpio_name[9];
329 char res_name[6];
330 uint32_t ctrl;
331 struct mtd_info *mtd = &nand->mtd;
332 struct nand_chip *chip = &nand->chip;
333
334 /* Request GPIO port. */
335 gpio = JZ_GPIO_MEM_CS0 + bank - 1;
336 sprintf(gpio_name, "NAND CS%d", bank);
337 ret = gpio_request(gpio, gpio_name);
338 if (ret) {
339 dev_warn(&pdev->dev,
340 "Failed to request %s gpio %d: %d\n",
341 gpio_name, gpio, ret);
342 goto notfound_gpio;
343 }
344
345 /* Request I/O resource. */
346 sprintf(res_name, "bank%d", bank);
347 ret = jz_nand_ioremap_resource(pdev, res_name,
348 &nand->bank_mem[bank - 1],
349 &nand->bank_base[bank - 1]);
350 if (ret)
351 goto notfound_resource;
352
353 /* Enable chip in bank. */
354 jz_gpio_set_function(gpio, JZ_GPIO_FUNC_MEM_CS0);
355 ctrl = readl(nand->base + JZ_REG_NAND_CTRL);
356 ctrl |= JZ_NAND_CTRL_ENABLE_CHIP(bank - 1);
357 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
358
359 if (chipnr == 0) {
360 /* Detect first chip. */
361 ret = nand_scan_ident(mtd, 1, NULL);
362 if (ret)
363 goto notfound_id;
364
365 /* Retrieve the IDs from the first chip. */
366 chip->select_chip(mtd, 0);
367 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
368 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
369 *nand_maf_id = chip->read_byte(mtd);
370 *nand_dev_id = chip->read_byte(mtd);
371 } else {
372 /* Detect additional chip. */
373 chip->select_chip(mtd, chipnr);
374 chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
375 chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
376 if (*nand_maf_id != chip->read_byte(mtd)
377 || *nand_dev_id != chip->read_byte(mtd)) {
378 ret = -ENODEV;
379 goto notfound_id;
380 }
381
382 /* Update size of the MTD. */
383 chip->numchips++;
384 mtd->size += chip->chipsize;
385 }
386
387 dev_info(&pdev->dev, "Found chip %i on bank %i\n", chipnr, bank);
388 return 0;
389
390notfound_id:
391 dev_info(&pdev->dev, "No chip found on bank %i\n", bank);
392 ctrl &= ~(JZ_NAND_CTRL_ENABLE_CHIP(bank - 1));
393 writel(ctrl, nand->base + JZ_REG_NAND_CTRL);
394 jz_gpio_set_function(gpio, JZ_GPIO_FUNC_NONE);
395 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
396 nand->bank_base[bank - 1]);
397notfound_resource:
398 gpio_free(gpio);
399notfound_gpio:
400 return ret;
401}
402
291static int __devinit jz_nand_probe(struct platform_device *pdev) 403static int __devinit jz_nand_probe(struct platform_device *pdev)
292{ 404{
293 int ret; 405 int ret;
@@ -295,6 +407,8 @@ static int __devinit jz_nand_probe(struct platform_device *pdev)
295 struct nand_chip *chip; 407 struct nand_chip *chip;
296 struct mtd_info *mtd; 408 struct mtd_info *mtd;
297 struct jz_nand_platform_data *pdata = pdev->dev.platform_data; 409 struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
410 size_t chipnr, bank_idx;
411 uint8_t nand_maf_id = 0, nand_dev_id = 0;
298 412
299 nand = kzalloc(sizeof(*nand), GFP_KERNEL); 413 nand = kzalloc(sizeof(*nand), GFP_KERNEL);
300 if (!nand) { 414 if (!nand) {
@@ -305,10 +419,6 @@ static int __devinit jz_nand_probe(struct platform_device *pdev)
305 ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base); 419 ret = jz_nand_ioremap_resource(pdev, "mmio", &nand->mem, &nand->base);
306 if (ret) 420 if (ret)
307 goto err_free; 421 goto err_free;
308 ret = jz_nand_ioremap_resource(pdev, "bank", &nand->bank_mem,
309 &nand->bank_base);
310 if (ret)
311 goto err_iounmap_mmio;
312 422
313 if (pdata && gpio_is_valid(pdata->busy_gpio)) { 423 if (pdata && gpio_is_valid(pdata->busy_gpio)) {
314 ret = gpio_request(pdata->busy_gpio, "NAND busy pin"); 424 ret = gpio_request(pdata->busy_gpio, "NAND busy pin");
@@ -316,7 +426,7 @@ static int __devinit jz_nand_probe(struct platform_device *pdev)
316 dev_err(&pdev->dev, 426 dev_err(&pdev->dev,
317 "Failed to request busy gpio %d: %d\n", 427 "Failed to request busy gpio %d: %d\n",
318 pdata->busy_gpio, ret); 428 pdata->busy_gpio, ret);
319 goto err_iounmap_mem; 429 goto err_iounmap_mmio;
320 } 430 }
321 } 431 }
322 432
@@ -339,22 +449,51 @@ static int __devinit jz_nand_probe(struct platform_device *pdev)
339 449
340 chip->chip_delay = 50; 450 chip->chip_delay = 50;
341 chip->cmd_ctrl = jz_nand_cmd_ctrl; 451 chip->cmd_ctrl = jz_nand_cmd_ctrl;
452 chip->select_chip = jz_nand_select_chip;
342 453
343 if (pdata && gpio_is_valid(pdata->busy_gpio)) 454 if (pdata && gpio_is_valid(pdata->busy_gpio))
344 chip->dev_ready = jz_nand_dev_ready; 455 chip->dev_ready = jz_nand_dev_ready;
345 456
346 chip->IO_ADDR_R = nand->bank_base;
347 chip->IO_ADDR_W = nand->bank_base;
348
349 nand->pdata = pdata; 457 nand->pdata = pdata;
350 platform_set_drvdata(pdev, nand); 458 platform_set_drvdata(pdev, nand);
351 459
352 writel(JZ_NAND_CTRL_ENABLE_CHIP(0), nand->base + JZ_REG_NAND_CTRL); 460 /* We are going to autodetect NAND chips in the banks specified in the
353 461 * platform data. Although nand_scan_ident() can detect multiple chips,
354 ret = nand_scan_ident(mtd, 1, NULL); 462 * it requires those chips to be numbered consecuitively, which is not
355 if (ret) { 463 * always the case for external memory banks. And a fixed chip-to-bank
356 dev_err(&pdev->dev, "Failed to scan nand\n"); 464 * mapping is not practical either, since for example Dingoo units
357 goto err_gpio_free; 465 * produced at different times have NAND chips in different banks.
466 */
467 chipnr = 0;
468 for (bank_idx = 0; bank_idx < JZ_NAND_NUM_BANKS; bank_idx++) {
469 unsigned char bank;
470
471 /* If there is no platform data, look for NAND in bank 1,
472 * which is the most likely bank since it is the only one
473 * that can be booted from.
474 */
475 bank = pdata ? pdata->banks[bank_idx] : bank_idx ^ 1;
476 if (bank == 0)
477 break;
478 if (bank > JZ_NAND_NUM_BANKS) {
479 dev_warn(&pdev->dev,
480 "Skipping non-existing bank: %d\n", bank);
481 continue;
482 }
483 /* The detection routine will directly or indirectly call
484 * jz_nand_select_chip(), so nand->banks has to contain the
485 * bank we're checking.
486 */
487 nand->banks[chipnr] = bank;
488 if (jz_nand_detect_bank(pdev, nand, bank, chipnr,
489 &nand_maf_id, &nand_dev_id) == 0)
490 chipnr++;
491 else
492 nand->banks[chipnr] = 0;
493 }
494 if (chipnr == 0) {
495 dev_err(&pdev->dev, "No NAND chips found\n");
496 goto err_gpio_busy;
358 } 497 }
359 498
360 if (pdata && pdata->ident_callback) { 499 if (pdata && pdata->ident_callback) {
@@ -364,8 +503,8 @@ static int __devinit jz_nand_probe(struct platform_device *pdev)
364 503
365 ret = nand_scan_tail(mtd); 504 ret = nand_scan_tail(mtd);
366 if (ret) { 505 if (ret) {
367 dev_err(&pdev->dev, "Failed to scan nand\n"); 506 dev_err(&pdev->dev, "Failed to scan NAND\n");
368 goto err_gpio_free; 507 goto err_unclaim_banks;
369 } 508 }
370 509
371 ret = mtd_device_parse_register(mtd, NULL, NULL, 510 ret = mtd_device_parse_register(mtd, NULL, NULL,
@@ -382,14 +521,21 @@ static int __devinit jz_nand_probe(struct platform_device *pdev)
382 return 0; 521 return 0;
383 522
384err_nand_release: 523err_nand_release:
385 nand_release(&nand->mtd); 524 nand_release(mtd);
386err_gpio_free: 525err_unclaim_banks:
526 while (chipnr--) {
527 unsigned char bank = nand->banks[chipnr];
528 gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
529 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
530 nand->bank_base[bank - 1]);
531 }
532 writel(0, nand->base + JZ_REG_NAND_CTRL);
533err_gpio_busy:
534 if (pdata && gpio_is_valid(pdata->busy_gpio))
535 gpio_free(pdata->busy_gpio);
387 platform_set_drvdata(pdev, NULL); 536 platform_set_drvdata(pdev, NULL);
388 gpio_free(pdata->busy_gpio);
389err_iounmap_mem:
390 iounmap(nand->bank_base);
391err_iounmap_mmio: 537err_iounmap_mmio:
392 iounmap(nand->base); 538 jz_nand_iounmap_resource(nand->mem, nand->base);
393err_free: 539err_free:
394 kfree(nand); 540 kfree(nand);
395 return ret; 541 return ret;
@@ -398,16 +544,26 @@ err_free:
398static int __devexit jz_nand_remove(struct platform_device *pdev) 544static int __devexit jz_nand_remove(struct platform_device *pdev)
399{ 545{
400 struct jz_nand *nand = platform_get_drvdata(pdev); 546 struct jz_nand *nand = platform_get_drvdata(pdev);
547 struct jz_nand_platform_data *pdata = pdev->dev.platform_data;
548 size_t i;
401 549
402 nand_release(&nand->mtd); 550 nand_release(&nand->mtd);
403 551
404 /* Deassert and disable all chips */ 552 /* Deassert and disable all chips */
405 writel(0, nand->base + JZ_REG_NAND_CTRL); 553 writel(0, nand->base + JZ_REG_NAND_CTRL);
406 554
407 iounmap(nand->bank_base); 555 for (i = 0; i < JZ_NAND_NUM_BANKS; ++i) {
408 release_mem_region(nand->bank_mem->start, resource_size(nand->bank_mem)); 556 unsigned char bank = nand->banks[i];
409 iounmap(nand->base); 557 if (bank != 0) {
410 release_mem_region(nand->mem->start, resource_size(nand->mem)); 558 jz_nand_iounmap_resource(nand->bank_mem[bank - 1],
559 nand->bank_base[bank - 1]);
560 gpio_free(JZ_GPIO_MEM_CS0 + bank - 1);
561 }
562 }
563 if (pdata && gpio_is_valid(pdata->busy_gpio))
564 gpio_free(pdata->busy_gpio);
565
566 jz_nand_iounmap_resource(nand->mem, nand->base);
411 567
412 platform_set_drvdata(pdev, NULL); 568 platform_set_drvdata(pdev, NULL);
413 kfree(nand); 569 kfree(nand);
diff --git a/drivers/net/ethernet/octeon/octeon_mgmt.c b/drivers/net/ethernet/octeon/octeon_mgmt.c
index cd827ff4a021..c42bbb16cdae 100644
--- a/drivers/net/ethernet/octeon/octeon_mgmt.c
+++ b/drivers/net/ethernet/octeon/octeon_mgmt.c
@@ -6,19 +6,21 @@
6 * Copyright (C) 2009 Cavium Networks 6 * Copyright (C) 2009 Cavium Networks
7 */ 7 */
8 8
9#include <linux/capability.h> 9#include <linux/platform_device.h>
10#include <linux/dma-mapping.h> 10#include <linux/dma-mapping.h>
11#include <linux/init.h> 11#include <linux/etherdevice.h>
12#include <linux/module.h> 12#include <linux/capability.h>
13#include <linux/interrupt.h> 13#include <linux/interrupt.h>
14#include <linux/platform_device.h>
15#include <linux/netdevice.h> 14#include <linux/netdevice.h>
16#include <linux/etherdevice.h> 15#include <linux/spinlock.h>
17#include <linux/if.h>
18#include <linux/if_vlan.h> 16#include <linux/if_vlan.h>
17#include <linux/of_mdio.h>
18#include <linux/module.h>
19#include <linux/of_net.h>
20#include <linux/init.h>
19#include <linux/slab.h> 21#include <linux/slab.h>
20#include <linux/phy.h> 22#include <linux/phy.h>
21#include <linux/spinlock.h> 23#include <linux/io.h>
22 24
23#include <asm/octeon/octeon.h> 25#include <asm/octeon/octeon.h>
24#include <asm/octeon/cvmx-mixx-defs.h> 26#include <asm/octeon/cvmx-mixx-defs.h>
@@ -58,8 +60,56 @@ union mgmt_port_ring_entry {
58 } s; 60 } s;
59}; 61};
60 62
63#define MIX_ORING1 0x0
64#define MIX_ORING2 0x8
65#define MIX_IRING1 0x10
66#define MIX_IRING2 0x18
67#define MIX_CTL 0x20
68#define MIX_IRHWM 0x28
69#define MIX_IRCNT 0x30
70#define MIX_ORHWM 0x38
71#define MIX_ORCNT 0x40
72#define MIX_ISR 0x48
73#define MIX_INTENA 0x50
74#define MIX_REMCNT 0x58
75#define MIX_BIST 0x78
76
77#define AGL_GMX_PRT_CFG 0x10
78#define AGL_GMX_RX_FRM_CTL 0x18
79#define AGL_GMX_RX_FRM_MAX 0x30
80#define AGL_GMX_RX_JABBER 0x38
81#define AGL_GMX_RX_STATS_CTL 0x50
82
83#define AGL_GMX_RX_STATS_PKTS_DRP 0xb0
84#define AGL_GMX_RX_STATS_OCTS_DRP 0xb8
85#define AGL_GMX_RX_STATS_PKTS_BAD 0xc0
86
87#define AGL_GMX_RX_ADR_CTL 0x100
88#define AGL_GMX_RX_ADR_CAM_EN 0x108
89#define AGL_GMX_RX_ADR_CAM0 0x180
90#define AGL_GMX_RX_ADR_CAM1 0x188
91#define AGL_GMX_RX_ADR_CAM2 0x190
92#define AGL_GMX_RX_ADR_CAM3 0x198
93#define AGL_GMX_RX_ADR_CAM4 0x1a0
94#define AGL_GMX_RX_ADR_CAM5 0x1a8
95
96#define AGL_GMX_TX_STATS_CTL 0x268
97#define AGL_GMX_TX_CTL 0x270
98#define AGL_GMX_TX_STAT0 0x280
99#define AGL_GMX_TX_STAT1 0x288
100#define AGL_GMX_TX_STAT2 0x290
101#define AGL_GMX_TX_STAT3 0x298
102#define AGL_GMX_TX_STAT4 0x2a0
103#define AGL_GMX_TX_STAT5 0x2a8
104#define AGL_GMX_TX_STAT6 0x2b0
105#define AGL_GMX_TX_STAT7 0x2b8
106#define AGL_GMX_TX_STAT8 0x2c0
107#define AGL_GMX_TX_STAT9 0x2c8
108
61struct octeon_mgmt { 109struct octeon_mgmt {
62 struct net_device *netdev; 110 struct net_device *netdev;
111 u64 mix;
112 u64 agl;
63 int port; 113 int port;
64 int irq; 114 int irq;
65 u64 *tx_ring; 115 u64 *tx_ring;
@@ -85,31 +135,34 @@ struct octeon_mgmt {
85 struct napi_struct napi; 135 struct napi_struct napi;
86 struct tasklet_struct tx_clean_tasklet; 136 struct tasklet_struct tx_clean_tasklet;
87 struct phy_device *phydev; 137 struct phy_device *phydev;
138 struct device_node *phy_np;
139 resource_size_t mix_phys;
140 resource_size_t mix_size;
141 resource_size_t agl_phys;
142 resource_size_t agl_size;
88}; 143};
89 144
90static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable) 145static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
91{ 146{
92 int port = p->port;
93 union cvmx_mixx_intena mix_intena; 147 union cvmx_mixx_intena mix_intena;
94 unsigned long flags; 148 unsigned long flags;
95 149
96 spin_lock_irqsave(&p->lock, flags); 150 spin_lock_irqsave(&p->lock, flags);
97 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); 151 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);
98 mix_intena.s.ithena = enable ? 1 : 0; 152 mix_intena.s.ithena = enable ? 1 : 0;
99 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); 153 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
100 spin_unlock_irqrestore(&p->lock, flags); 154 spin_unlock_irqrestore(&p->lock, flags);
101} 155}
102 156
103static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable) 157static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable)
104{ 158{
105 int port = p->port;
106 union cvmx_mixx_intena mix_intena; 159 union cvmx_mixx_intena mix_intena;
107 unsigned long flags; 160 unsigned long flags;
108 161
109 spin_lock_irqsave(&p->lock, flags); 162 spin_lock_irqsave(&p->lock, flags);
110 mix_intena.u64 = cvmx_read_csr(CVMX_MIXX_INTENA(port)); 163 mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);
111 mix_intena.s.othena = enable ? 1 : 0; 164 mix_intena.s.othena = enable ? 1 : 0;
112 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); 165 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
113 spin_unlock_irqrestore(&p->lock, flags); 166 spin_unlock_irqrestore(&p->lock, flags);
114} 167}
115 168
@@ -146,7 +199,6 @@ static unsigned int ring_size_to_bytes(unsigned int ring_size)
146static void octeon_mgmt_rx_fill_ring(struct net_device *netdev) 199static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
147{ 200{
148 struct octeon_mgmt *p = netdev_priv(netdev); 201 struct octeon_mgmt *p = netdev_priv(netdev);
149 int port = p->port;
150 202
151 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) { 203 while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) {
152 unsigned int size; 204 unsigned int size;
@@ -177,24 +229,23 @@ static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
177 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE; 229 (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE;
178 p->rx_current_fill++; 230 p->rx_current_fill++;
179 /* Ring the bell. */ 231 /* Ring the bell. */
180 cvmx_write_csr(CVMX_MIXX_IRING2(port), 1); 232 cvmx_write_csr(p->mix + MIX_IRING2, 1);
181 } 233 }
182} 234}
183 235
184static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p) 236static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
185{ 237{
186 int port = p->port;
187 union cvmx_mixx_orcnt mix_orcnt; 238 union cvmx_mixx_orcnt mix_orcnt;
188 union mgmt_port_ring_entry re; 239 union mgmt_port_ring_entry re;
189 struct sk_buff *skb; 240 struct sk_buff *skb;
190 int cleaned = 0; 241 int cleaned = 0;
191 unsigned long flags; 242 unsigned long flags;
192 243
193 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); 244 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
194 while (mix_orcnt.s.orcnt) { 245 while (mix_orcnt.s.orcnt) {
195 spin_lock_irqsave(&p->tx_list.lock, flags); 246 spin_lock_irqsave(&p->tx_list.lock, flags);
196 247
197 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); 248 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
198 249
199 if (mix_orcnt.s.orcnt == 0) { 250 if (mix_orcnt.s.orcnt == 0) {
200 spin_unlock_irqrestore(&p->tx_list.lock, flags); 251 spin_unlock_irqrestore(&p->tx_list.lock, flags);
@@ -214,7 +265,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
214 mix_orcnt.s.orcnt = 1; 265 mix_orcnt.s.orcnt = 1;
215 266
216 /* Acknowledge to hardware that we have the buffer. */ 267 /* Acknowledge to hardware that we have the buffer. */
217 cvmx_write_csr(CVMX_MIXX_ORCNT(port), mix_orcnt.u64); 268 cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64);
218 p->tx_current_fill--; 269 p->tx_current_fill--;
219 270
220 spin_unlock_irqrestore(&p->tx_list.lock, flags); 271 spin_unlock_irqrestore(&p->tx_list.lock, flags);
@@ -224,7 +275,7 @@ static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
224 dev_kfree_skb_any(skb); 275 dev_kfree_skb_any(skb);
225 cleaned++; 276 cleaned++;
226 277
227 mix_orcnt.u64 = cvmx_read_csr(CVMX_MIXX_ORCNT(port)); 278 mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
228 } 279 }
229 280
230 if (cleaned && netif_queue_stopped(p->netdev)) 281 if (cleaned && netif_queue_stopped(p->netdev))
@@ -241,13 +292,12 @@ static void octeon_mgmt_clean_tx_tasklet(unsigned long arg)
241static void octeon_mgmt_update_rx_stats(struct net_device *netdev) 292static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
242{ 293{
243 struct octeon_mgmt *p = netdev_priv(netdev); 294 struct octeon_mgmt *p = netdev_priv(netdev);
244 int port = p->port;
245 unsigned long flags; 295 unsigned long flags;
246 u64 drop, bad; 296 u64 drop, bad;
247 297
248 /* These reads also clear the count registers. */ 298 /* These reads also clear the count registers. */
249 drop = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port)); 299 drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP);
250 bad = cvmx_read_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port)); 300 bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD);
251 301
252 if (drop || bad) { 302 if (drop || bad) {
253 /* Do an atomic update. */ 303 /* Do an atomic update. */
@@ -261,15 +311,14 @@ static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
261static void octeon_mgmt_update_tx_stats(struct net_device *netdev) 311static void octeon_mgmt_update_tx_stats(struct net_device *netdev)
262{ 312{
263 struct octeon_mgmt *p = netdev_priv(netdev); 313 struct octeon_mgmt *p = netdev_priv(netdev);
264 int port = p->port;
265 unsigned long flags; 314 unsigned long flags;
266 315
267 union cvmx_agl_gmx_txx_stat0 s0; 316 union cvmx_agl_gmx_txx_stat0 s0;
268 union cvmx_agl_gmx_txx_stat1 s1; 317 union cvmx_agl_gmx_txx_stat1 s1;
269 318
270 /* These reads also clear the count registers. */ 319 /* These reads also clear the count registers. */
271 s0.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT0(port)); 320 s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0);
272 s1.u64 = cvmx_read_csr(CVMX_AGL_GMX_TXX_STAT1(port)); 321 s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1);
273 322
274 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) { 323 if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) {
275 /* Do an atomic update. */ 324 /* Do an atomic update. */
@@ -308,7 +357,6 @@ static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,
308 357
309static int octeon_mgmt_receive_one(struct octeon_mgmt *p) 358static int octeon_mgmt_receive_one(struct octeon_mgmt *p)
310{ 359{
311 int port = p->port;
312 struct net_device *netdev = p->netdev; 360 struct net_device *netdev = p->netdev;
313 union cvmx_mixx_ircnt mix_ircnt; 361 union cvmx_mixx_ircnt mix_ircnt;
314 union mgmt_port_ring_entry re; 362 union mgmt_port_ring_entry re;
@@ -381,18 +429,17 @@ done:
381 /* Tell the hardware we processed a packet. */ 429 /* Tell the hardware we processed a packet. */
382 mix_ircnt.u64 = 0; 430 mix_ircnt.u64 = 0;
383 mix_ircnt.s.ircnt = 1; 431 mix_ircnt.s.ircnt = 1;
384 cvmx_write_csr(CVMX_MIXX_IRCNT(port), mix_ircnt.u64); 432 cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64);
385 return rc; 433 return rc;
386} 434}
387 435
388static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget) 436static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
389{ 437{
390 int port = p->port;
391 unsigned int work_done = 0; 438 unsigned int work_done = 0;
392 union cvmx_mixx_ircnt mix_ircnt; 439 union cvmx_mixx_ircnt mix_ircnt;
393 int rc; 440 int rc;
394 441
395 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); 442 mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);
396 while (work_done < budget && mix_ircnt.s.ircnt) { 443 while (work_done < budget && mix_ircnt.s.ircnt) {
397 444
398 rc = octeon_mgmt_receive_one(p); 445 rc = octeon_mgmt_receive_one(p);
@@ -400,7 +447,7 @@ static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
400 work_done++; 447 work_done++;
401 448
402 /* Check for more packets. */ 449 /* Check for more packets. */
403 mix_ircnt.u64 = cvmx_read_csr(CVMX_MIXX_IRCNT(port)); 450 mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);
404 } 451 }
405 452
406 octeon_mgmt_rx_fill_ring(p->netdev); 453 octeon_mgmt_rx_fill_ring(p->netdev);
@@ -434,16 +481,16 @@ static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
434 union cvmx_agl_gmx_bist agl_gmx_bist; 481 union cvmx_agl_gmx_bist agl_gmx_bist;
435 482
436 mix_ctl.u64 = 0; 483 mix_ctl.u64 = 0;
437 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); 484 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
438 do { 485 do {
439 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(p->port)); 486 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
440 } while (mix_ctl.s.busy); 487 } while (mix_ctl.s.busy);
441 mix_ctl.s.reset = 1; 488 mix_ctl.s.reset = 1;
442 cvmx_write_csr(CVMX_MIXX_CTL(p->port), mix_ctl.u64); 489 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
443 cvmx_read_csr(CVMX_MIXX_CTL(p->port)); 490 cvmx_read_csr(p->mix + MIX_CTL);
444 cvmx_wait(64); 491 cvmx_wait(64);
445 492
446 mix_bist.u64 = cvmx_read_csr(CVMX_MIXX_BIST(p->port)); 493 mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST);
447 if (mix_bist.u64) 494 if (mix_bist.u64)
448 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n", 495 dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n",
449 (unsigned long long)mix_bist.u64); 496 (unsigned long long)mix_bist.u64);
@@ -474,7 +521,6 @@ static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs,
474static void octeon_mgmt_set_rx_filtering(struct net_device *netdev) 521static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
475{ 522{
476 struct octeon_mgmt *p = netdev_priv(netdev); 523 struct octeon_mgmt *p = netdev_priv(netdev);
477 int port = p->port;
478 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl; 524 union cvmx_agl_gmx_rxx_adr_ctl adr_ctl;
479 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx; 525 union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx;
480 unsigned long flags; 526 unsigned long flags;
@@ -520,29 +566,29 @@ static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
520 spin_lock_irqsave(&p->lock, flags); 566 spin_lock_irqsave(&p->lock, flags);
521 567
522 /* Disable packet I/O. */ 568 /* Disable packet I/O. */
523 agl_gmx_prtx.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); 569 agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
524 prev_packet_enable = agl_gmx_prtx.s.en; 570 prev_packet_enable = agl_gmx_prtx.s.en;
525 agl_gmx_prtx.s.en = 0; 571 agl_gmx_prtx.s.en = 0;
526 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 572 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);
527 573
528 adr_ctl.u64 = 0; 574 adr_ctl.u64 = 0;
529 adr_ctl.s.cam_mode = cam_mode; 575 adr_ctl.s.cam_mode = cam_mode;
530 adr_ctl.s.mcst = multicast_mode; 576 adr_ctl.s.mcst = multicast_mode;
531 adr_ctl.s.bcst = 1; /* Allow broadcast */ 577 adr_ctl.s.bcst = 1; /* Allow broadcast */
532 578
533 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CTL(port), adr_ctl.u64); 579 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64);
534 580
535 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM0(port), cam_state.cam[0]); 581 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]);
536 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM1(port), cam_state.cam[1]); 582 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]);
537 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM2(port), cam_state.cam[2]); 583 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]);
538 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM3(port), cam_state.cam[3]); 584 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]);
539 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM4(port), cam_state.cam[4]); 585 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]);
540 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM5(port), cam_state.cam[5]); 586 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]);
541 cvmx_write_csr(CVMX_AGL_GMX_RXX_ADR_CAM_EN(port), cam_state.cam_mask); 587 cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask);
542 588
543 /* Restore packet I/O. */ 589 /* Restore packet I/O. */
544 agl_gmx_prtx.s.en = prev_packet_enable; 590 agl_gmx_prtx.s.en = prev_packet_enable;
545 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), agl_gmx_prtx.u64); 591 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);
546 592
547 spin_unlock_irqrestore(&p->lock, flags); 593 spin_unlock_irqrestore(&p->lock, flags);
548} 594}
@@ -564,7 +610,6 @@ static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr)
564static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu) 610static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
565{ 611{
566 struct octeon_mgmt *p = netdev_priv(netdev); 612 struct octeon_mgmt *p = netdev_priv(netdev);
567 int port = p->port;
568 int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM; 613 int size_without_fcs = new_mtu + OCTEON_MGMT_RX_HEADROOM;
569 614
570 /* 615 /*
@@ -580,8 +625,8 @@ static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
580 625
581 netdev->mtu = new_mtu; 626 netdev->mtu = new_mtu;
582 627
583 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_MAX(port), size_without_fcs); 628 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, size_without_fcs);
584 cvmx_write_csr(CVMX_AGL_GMX_RXX_JABBER(port), 629 cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER,
585 (size_without_fcs + 7) & 0xfff8); 630 (size_without_fcs + 7) & 0xfff8);
586 631
587 return 0; 632 return 0;
@@ -591,14 +636,13 @@ static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id)
591{ 636{
592 struct net_device *netdev = dev_id; 637 struct net_device *netdev = dev_id;
593 struct octeon_mgmt *p = netdev_priv(netdev); 638 struct octeon_mgmt *p = netdev_priv(netdev);
594 int port = p->port;
595 union cvmx_mixx_isr mixx_isr; 639 union cvmx_mixx_isr mixx_isr;
596 640
597 mixx_isr.u64 = cvmx_read_csr(CVMX_MIXX_ISR(port)); 641 mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR);
598 642
599 /* Clear any pending interrupts */ 643 /* Clear any pending interrupts */
600 cvmx_write_csr(CVMX_MIXX_ISR(port), mixx_isr.u64); 644 cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64);
601 cvmx_read_csr(CVMX_MIXX_ISR(port)); 645 cvmx_read_csr(p->mix + MIX_ISR);
602 646
603 if (mixx_isr.s.irthresh) { 647 if (mixx_isr.s.irthresh) {
604 octeon_mgmt_disable_rx_irq(p); 648 octeon_mgmt_disable_rx_irq(p);
@@ -629,7 +673,6 @@ static int octeon_mgmt_ioctl(struct net_device *netdev,
629static void octeon_mgmt_adjust_link(struct net_device *netdev) 673static void octeon_mgmt_adjust_link(struct net_device *netdev)
630{ 674{
631 struct octeon_mgmt *p = netdev_priv(netdev); 675 struct octeon_mgmt *p = netdev_priv(netdev);
632 int port = p->port;
633 union cvmx_agl_gmx_prtx_cfg prtx_cfg; 676 union cvmx_agl_gmx_prtx_cfg prtx_cfg;
634 unsigned long flags; 677 unsigned long flags;
635 int link_changed = 0; 678 int link_changed = 0;
@@ -640,11 +683,9 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev)
640 link_changed = 1; 683 link_changed = 1;
641 if (p->last_duplex != p->phydev->duplex) { 684 if (p->last_duplex != p->phydev->duplex) {
642 p->last_duplex = p->phydev->duplex; 685 p->last_duplex = p->phydev->duplex;
643 prtx_cfg.u64 = 686 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
644 cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port));
645 prtx_cfg.s.duplex = p->phydev->duplex; 687 prtx_cfg.s.duplex = p->phydev->duplex;
646 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), 688 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
647 prtx_cfg.u64);
648 } 689 }
649 } else { 690 } else {
650 if (p->last_link) 691 if (p->last_link)
@@ -670,18 +711,16 @@ static void octeon_mgmt_adjust_link(struct net_device *netdev)
670static int octeon_mgmt_init_phy(struct net_device *netdev) 711static int octeon_mgmt_init_phy(struct net_device *netdev)
671{ 712{
672 struct octeon_mgmt *p = netdev_priv(netdev); 713 struct octeon_mgmt *p = netdev_priv(netdev);
673 char phy_id[MII_BUS_ID_SIZE + 3];
674 714
675 if (octeon_is_simulation()) { 715 if (octeon_is_simulation() || p->phy_np == NULL) {
676 /* No PHYs in the simulator. */ 716 /* No PHYs in the simulator. */
677 netif_carrier_on(netdev); 717 netif_carrier_on(netdev);
678 return 0; 718 return 0;
679 } 719 }
680 720
681 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", p->port); 721 p->phydev = of_phy_connect(netdev, p->phy_np,
682 722 octeon_mgmt_adjust_link, 0,
683 p->phydev = phy_connect(netdev, phy_id, octeon_mgmt_adjust_link, 0, 723 PHY_INTERFACE_MODE_MII);
684 PHY_INTERFACE_MODE_MII);
685 724
686 if (IS_ERR(p->phydev)) { 725 if (IS_ERR(p->phydev)) {
687 p->phydev = NULL; 726 p->phydev = NULL;
@@ -737,14 +776,14 @@ static int octeon_mgmt_open(struct net_device *netdev)
737 776
738 octeon_mgmt_reset_hw(p); 777 octeon_mgmt_reset_hw(p);
739 778
740 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); 779 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
741 780
742 /* Bring it out of reset if needed. */ 781 /* Bring it out of reset if needed. */
743 if (mix_ctl.s.reset) { 782 if (mix_ctl.s.reset) {
744 mix_ctl.s.reset = 0; 783 mix_ctl.s.reset = 0;
745 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); 784 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
746 do { 785 do {
747 mix_ctl.u64 = cvmx_read_csr(CVMX_MIXX_CTL(port)); 786 mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
748 } while (mix_ctl.s.reset); 787 } while (mix_ctl.s.reset);
749 } 788 }
750 789
@@ -755,17 +794,17 @@ static int octeon_mgmt_open(struct net_device *netdev)
755 oring1.u64 = 0; 794 oring1.u64 = 0;
756 oring1.s.obase = p->tx_ring_handle >> 3; 795 oring1.s.obase = p->tx_ring_handle >> 3;
757 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE; 796 oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE;
758 cvmx_write_csr(CVMX_MIXX_ORING1(port), oring1.u64); 797 cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64);
759 798
760 iring1.u64 = 0; 799 iring1.u64 = 0;
761 iring1.s.ibase = p->rx_ring_handle >> 3; 800 iring1.s.ibase = p->rx_ring_handle >> 3;
762 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE; 801 iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
763 cvmx_write_csr(CVMX_MIXX_IRING1(port), iring1.u64); 802 cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64);
764 803
765 /* Disable packet I/O. */ 804 /* Disable packet I/O. */
766 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); 805 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
767 prtx_cfg.s.en = 0; 806 prtx_cfg.s.en = 0;
768 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); 807 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
769 808
770 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN); 809 memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
771 octeon_mgmt_set_mac_address(netdev, &sa); 810 octeon_mgmt_set_mac_address(netdev, &sa);
@@ -782,7 +821,7 @@ static int octeon_mgmt_open(struct net_device *netdev)
782 mix_ctl.s.nbtarb = 0; /* Arbitration mode */ 821 mix_ctl.s.nbtarb = 0; /* Arbitration mode */
783 /* MII CB-request FIFO programmable high watermark */ 822 /* MII CB-request FIFO programmable high watermark */
784 mix_ctl.s.mrq_hwm = 1; 823 mix_ctl.s.mrq_hwm = 1;
785 cvmx_write_csr(CVMX_MIXX_CTL(port), mix_ctl.u64); 824 cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
786 825
787 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X) 826 if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
788 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) { 827 || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
@@ -809,16 +848,16 @@ static int octeon_mgmt_open(struct net_device *netdev)
809 848
810 /* Clear statistics. */ 849 /* Clear statistics. */
811 /* Clear on read. */ 850 /* Clear on read. */
812 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_CTL(port), 1); 851 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1);
813 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_DRP(port), 0); 852 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0);
814 cvmx_write_csr(CVMX_AGL_GMX_RXX_STATS_PKTS_BAD(port), 0); 853 cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0);
815 854
816 cvmx_write_csr(CVMX_AGL_GMX_TXX_STATS_CTL(port), 1); 855 cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1);
817 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT0(port), 0); 856 cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0);
818 cvmx_write_csr(CVMX_AGL_GMX_TXX_STAT1(port), 0); 857 cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0);
819 858
820 /* Clear any pending interrupts */ 859 /* Clear any pending interrupts */
821 cvmx_write_csr(CVMX_MIXX_ISR(port), cvmx_read_csr(CVMX_MIXX_ISR(port))); 860 cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR));
822 861
823 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name, 862 if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name,
824 netdev)) { 863 netdev)) {
@@ -829,18 +868,18 @@ static int octeon_mgmt_open(struct net_device *netdev)
829 /* Interrupt every single RX packet */ 868 /* Interrupt every single RX packet */
830 mix_irhwm.u64 = 0; 869 mix_irhwm.u64 = 0;
831 mix_irhwm.s.irhwm = 0; 870 mix_irhwm.s.irhwm = 0;
832 cvmx_write_csr(CVMX_MIXX_IRHWM(port), mix_irhwm.u64); 871 cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64);
833 872
834 /* Interrupt when we have 1 or more packets to clean. */ 873 /* Interrupt when we have 1 or more packets to clean. */
835 mix_orhwm.u64 = 0; 874 mix_orhwm.u64 = 0;
836 mix_orhwm.s.orhwm = 1; 875 mix_orhwm.s.orhwm = 1;
837 cvmx_write_csr(CVMX_MIXX_ORHWM(port), mix_orhwm.u64); 876 cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64);
838 877
839 /* Enable receive and transmit interrupts */ 878 /* Enable receive and transmit interrupts */
840 mix_intena.u64 = 0; 879 mix_intena.u64 = 0;
841 mix_intena.s.ithena = 1; 880 mix_intena.s.ithena = 1;
842 mix_intena.s.othena = 1; 881 mix_intena.s.othena = 1;
843 cvmx_write_csr(CVMX_MIXX_INTENA(port), mix_intena.u64); 882 cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
844 883
845 884
846 /* Enable packet I/O. */ 885 /* Enable packet I/O. */
@@ -871,7 +910,7 @@ static int octeon_mgmt_open(struct net_device *netdev)
871 * frame. GMX checks that the PREAMBLE is sent correctly. 910 * frame. GMX checks that the PREAMBLE is sent correctly.
872 */ 911 */
873 rxx_frm_ctl.s.pre_chk = 1; 912 rxx_frm_ctl.s.pre_chk = 1;
874 cvmx_write_csr(CVMX_AGL_GMX_RXX_FRM_CTL(port), rxx_frm_ctl.u64); 913 cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);
875 914
876 /* Enable the AGL block */ 915 /* Enable the AGL block */
877 agl_gmx_inf_mode.u64 = 0; 916 agl_gmx_inf_mode.u64 = 0;
@@ -879,13 +918,13 @@ static int octeon_mgmt_open(struct net_device *netdev)
879 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64); 918 cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
880 919
881 /* Configure the port duplex and enables */ 920 /* Configure the port duplex and enables */
882 prtx_cfg.u64 = cvmx_read_csr(CVMX_AGL_GMX_PRTX_CFG(port)); 921 prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
883 prtx_cfg.s.tx_en = 1; 922 prtx_cfg.s.tx_en = 1;
884 prtx_cfg.s.rx_en = 1; 923 prtx_cfg.s.rx_en = 1;
885 prtx_cfg.s.en = 1; 924 prtx_cfg.s.en = 1;
886 p->last_duplex = 1; 925 p->last_duplex = 1;
887 prtx_cfg.s.duplex = p->last_duplex; 926 prtx_cfg.s.duplex = p->last_duplex;
888 cvmx_write_csr(CVMX_AGL_GMX_PRTX_CFG(port), prtx_cfg.u64); 927 cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
889 928
890 p->last_link = 0; 929 p->last_link = 0;
891 netif_carrier_off(netdev); 930 netif_carrier_off(netdev);
@@ -949,7 +988,6 @@ static int octeon_mgmt_stop(struct net_device *netdev)
949static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev) 988static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
950{ 989{
951 struct octeon_mgmt *p = netdev_priv(netdev); 990 struct octeon_mgmt *p = netdev_priv(netdev);
952 int port = p->port;
953 union mgmt_port_ring_entry re; 991 union mgmt_port_ring_entry re;
954 unsigned long flags; 992 unsigned long flags;
955 int rv = NETDEV_TX_BUSY; 993 int rv = NETDEV_TX_BUSY;
@@ -993,7 +1031,7 @@ static int octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
993 netdev->stats.tx_bytes += skb->len; 1031 netdev->stats.tx_bytes += skb->len;
994 1032
995 /* Ring the bell. */ 1033 /* Ring the bell. */
996 cvmx_write_csr(CVMX_MIXX_ORING2(port), 1); 1034 cvmx_write_csr(p->mix + MIX_ORING2, 1);
997 1035
998 rv = NETDEV_TX_OK; 1036 rv = NETDEV_TX_OK;
999out: 1037out:
@@ -1071,10 +1109,14 @@ static const struct net_device_ops octeon_mgmt_ops = {
1071 1109
1072static int __devinit octeon_mgmt_probe(struct platform_device *pdev) 1110static int __devinit octeon_mgmt_probe(struct platform_device *pdev)
1073{ 1111{
1074 struct resource *res_irq;
1075 struct net_device *netdev; 1112 struct net_device *netdev;
1076 struct octeon_mgmt *p; 1113 struct octeon_mgmt *p;
1077 int i; 1114 const __be32 *data;
1115 const u8 *mac;
1116 struct resource *res_mix;
1117 struct resource *res_agl;
1118 int len;
1119 int result;
1078 1120
1079 netdev = alloc_etherdev(sizeof(struct octeon_mgmt)); 1121 netdev = alloc_etherdev(sizeof(struct octeon_mgmt));
1080 if (netdev == NULL) 1122 if (netdev == NULL)
@@ -1088,14 +1130,63 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev)
1088 p->netdev = netdev; 1130 p->netdev = netdev;
1089 p->dev = &pdev->dev; 1131 p->dev = &pdev->dev;
1090 1132
1091 p->port = pdev->id; 1133 data = of_get_property(pdev->dev.of_node, "cell-index", &len);
1134 if (data && len == sizeof(*data)) {
1135 p->port = be32_to_cpup(data);
1136 } else {
1137 dev_err(&pdev->dev, "no 'cell-index' property\n");
1138 result = -ENXIO;
1139 goto err;
1140 }
1141
1092 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port); 1142 snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
1093 1143
1094 res_irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0); 1144 result = platform_get_irq(pdev, 0);
1095 if (!res_irq) 1145 if (result < 0)
1146 goto err;
1147
1148 p->irq = result;
1149
1150 res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1151 if (res_mix == NULL) {
1152 dev_err(&pdev->dev, "no 'reg' resource\n");
1153 result = -ENXIO;
1154 goto err;
1155 }
1156
1157 res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1158 if (res_agl == NULL) {
1159 dev_err(&pdev->dev, "no 'reg' resource\n");
1160 result = -ENXIO;
1161 goto err;
1162 }
1163
1164 p->mix_phys = res_mix->start;
1165 p->mix_size = resource_size(res_mix);
1166 p->agl_phys = res_agl->start;
1167 p->agl_size = resource_size(res_agl);
1168
1169
1170 if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size,
1171 res_mix->name)) {
1172 dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
1173 res_mix->name);
1174 result = -ENXIO;
1175 goto err;
1176 }
1177
1178 if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size,
1179 res_agl->name)) {
1180 result = -ENXIO;
1181 dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
1182 res_agl->name);
1096 goto err; 1183 goto err;
1184 }
1185
1186
1187 p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size);
1188 p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size);
1097 1189
1098 p->irq = res_irq->start;
1099 spin_lock_init(&p->lock); 1190 spin_lock_init(&p->lock);
1100 1191
1101 skb_queue_head_init(&p->tx_list); 1192 skb_queue_head_init(&p->tx_list);
@@ -1108,24 +1199,26 @@ static int __devinit octeon_mgmt_probe(struct platform_device *pdev)
1108 netdev->netdev_ops = &octeon_mgmt_ops; 1199 netdev->netdev_ops = &octeon_mgmt_ops;
1109 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops; 1200 netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;
1110 1201
1111 /* The mgmt ports get the first N MACs. */ 1202 mac = of_get_mac_address(pdev->dev.of_node);
1112 for (i = 0; i < 6; i++) 1203
1113 netdev->dev_addr[i] = octeon_bootinfo->mac_addr_base[i]; 1204 if (mac)
1114 netdev->dev_addr[5] += p->port; 1205 memcpy(netdev->dev_addr, mac, 6);
1115 1206
1116 if (p->port >= octeon_bootinfo->mac_addr_count) 1207 p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1117 dev_err(&pdev->dev,
1118 "Error %s: Using MAC outside of the assigned range: %pM\n",
1119 netdev->name, netdev->dev_addr);
1120 1208
1121 if (register_netdev(netdev)) 1209 pdev->dev.coherent_dma_mask = DMA_BIT_MASK(64);
1210 pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
1211
1212 result = register_netdev(netdev);
1213 if (result)
1122 goto err; 1214 goto err;
1123 1215
1124 dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); 1216 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
1125 return 0; 1217 return 0;
1218
1126err: 1219err:
1127 free_netdev(netdev); 1220 free_netdev(netdev);
1128 return -ENOENT; 1221 return result;
1129} 1222}
1130 1223
1131static int __devexit octeon_mgmt_remove(struct platform_device *pdev) 1224static int __devexit octeon_mgmt_remove(struct platform_device *pdev)
@@ -1137,10 +1230,19 @@ static int __devexit octeon_mgmt_remove(struct platform_device *pdev)
1137 return 0; 1230 return 0;
1138} 1231}
1139 1232
1233static struct of_device_id octeon_mgmt_match[] = {
1234 {
1235 .compatible = "cavium,octeon-5750-mix",
1236 },
1237 {},
1238};
1239MODULE_DEVICE_TABLE(of, octeon_mgmt_match);
1240
1140static struct platform_driver octeon_mgmt_driver = { 1241static struct platform_driver octeon_mgmt_driver = {
1141 .driver = { 1242 .driver = {
1142 .name = "octeon_mgmt", 1243 .name = "octeon_mgmt",
1143 .owner = THIS_MODULE, 1244 .owner = THIS_MODULE,
1245 .of_match_table = octeon_mgmt_match,
1144 }, 1246 },
1145 .probe = octeon_mgmt_probe, 1247 .probe = octeon_mgmt_probe,
1146 .remove = __devexit_p(octeon_mgmt_remove), 1248 .remove = __devexit_p(octeon_mgmt_remove),
diff --git a/drivers/net/phy/mdio-octeon.c b/drivers/net/phy/mdio-octeon.c
index 826d961f39f7..d4015aa663e6 100644
--- a/drivers/net/phy/mdio-octeon.c
+++ b/drivers/net/phy/mdio-octeon.c
@@ -3,14 +3,17 @@
3 * License. See the file "COPYING" in the main directory of this archive 3 * License. See the file "COPYING" in the main directory of this archive
4 * for more details. 4 * for more details.
5 * 5 *
6 * Copyright (C) 2009 Cavium Networks 6 * Copyright (C) 2009,2011 Cavium, Inc.
7 */ 7 */
8 8
9#include <linux/gfp.h>
10#include <linux/init.h>
11#include <linux/module.h>
12#include <linux/platform_device.h> 9#include <linux/platform_device.h>
10#include <linux/of_mdio.h>
11#include <linux/delay.h>
12#include <linux/module.h>
13#include <linux/init.h>
14#include <linux/gfp.h>
13#include <linux/phy.h> 15#include <linux/phy.h>
16#include <linux/io.h>
14 17
15#include <asm/octeon/octeon.h> 18#include <asm/octeon/octeon.h>
16#include <asm/octeon/cvmx-smix-defs.h> 19#include <asm/octeon/cvmx-smix-defs.h>
@@ -18,9 +21,17 @@
18#define DRV_VERSION "1.0" 21#define DRV_VERSION "1.0"
19#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver" 22#define DRV_DESCRIPTION "Cavium Networks Octeon SMI/MDIO driver"
20 23
24#define SMI_CMD 0x0
25#define SMI_WR_DAT 0x8
26#define SMI_RD_DAT 0x10
27#define SMI_CLK 0x18
28#define SMI_EN 0x20
29
21struct octeon_mdiobus { 30struct octeon_mdiobus {
22 struct mii_bus *mii_bus; 31 struct mii_bus *mii_bus;
23 int unit; 32 u64 register_base;
33 resource_size_t mdio_phys;
34 resource_size_t regsize;
24 int phy_irq[PHY_MAX_ADDR]; 35 int phy_irq[PHY_MAX_ADDR];
25}; 36};
26 37
@@ -35,15 +46,15 @@ static int octeon_mdiobus_read(struct mii_bus *bus, int phy_id, int regnum)
35 smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */ 46 smi_cmd.s.phy_op = 1; /* MDIO_CLAUSE_22_READ */
36 smi_cmd.s.phy_adr = phy_id; 47 smi_cmd.s.phy_adr = phy_id;
37 smi_cmd.s.reg_adr = regnum; 48 smi_cmd.s.reg_adr = regnum;
38 cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); 49 cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
39 50
40 do { 51 do {
41 /* 52 /*
42 * Wait 1000 clocks so we don't saturate the RSL bus 53 * Wait 1000 clocks so we don't saturate the RSL bus
43 * doing reads. 54 * doing reads.
44 */ 55 */
45 cvmx_wait(1000); 56 __delay(1000);
46 smi_rd.u64 = cvmx_read_csr(CVMX_SMIX_RD_DAT(p->unit)); 57 smi_rd.u64 = cvmx_read_csr(p->register_base + SMI_RD_DAT);
47 } while (smi_rd.s.pending && --timeout); 58 } while (smi_rd.s.pending && --timeout);
48 59
49 if (smi_rd.s.val) 60 if (smi_rd.s.val)
@@ -62,21 +73,21 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
62 73
63 smi_wr.u64 = 0; 74 smi_wr.u64 = 0;
64 smi_wr.s.dat = val; 75 smi_wr.s.dat = val;
65 cvmx_write_csr(CVMX_SMIX_WR_DAT(p->unit), smi_wr.u64); 76 cvmx_write_csr(p->register_base + SMI_WR_DAT, smi_wr.u64);
66 77
67 smi_cmd.u64 = 0; 78 smi_cmd.u64 = 0;
68 smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */ 79 smi_cmd.s.phy_op = 0; /* MDIO_CLAUSE_22_WRITE */
69 smi_cmd.s.phy_adr = phy_id; 80 smi_cmd.s.phy_adr = phy_id;
70 smi_cmd.s.reg_adr = regnum; 81 smi_cmd.s.reg_adr = regnum;
71 cvmx_write_csr(CVMX_SMIX_CMD(p->unit), smi_cmd.u64); 82 cvmx_write_csr(p->register_base + SMI_CMD, smi_cmd.u64);
72 83
73 do { 84 do {
74 /* 85 /*
75 * Wait 1000 clocks so we don't saturate the RSL bus 86 * Wait 1000 clocks so we don't saturate the RSL bus
76 * doing reads. 87 * doing reads.
77 */ 88 */
78 cvmx_wait(1000); 89 __delay(1000);
79 smi_wr.u64 = cvmx_read_csr(CVMX_SMIX_WR_DAT(p->unit)); 90 smi_wr.u64 = cvmx_read_csr(p->register_base + SMI_WR_DAT);
80 } while (smi_wr.s.pending && --timeout); 91 } while (smi_wr.s.pending && --timeout);
81 92
82 if (timeout <= 0) 93 if (timeout <= 0)
@@ -88,38 +99,44 @@ static int octeon_mdiobus_write(struct mii_bus *bus, int phy_id,
88static int __devinit octeon_mdiobus_probe(struct platform_device *pdev) 99static int __devinit octeon_mdiobus_probe(struct platform_device *pdev)
89{ 100{
90 struct octeon_mdiobus *bus; 101 struct octeon_mdiobus *bus;
102 struct resource *res_mem;
91 union cvmx_smix_en smi_en; 103 union cvmx_smix_en smi_en;
92 int i;
93 int err = -ENOENT; 104 int err = -ENOENT;
94 105
95 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL); 106 bus = devm_kzalloc(&pdev->dev, sizeof(*bus), GFP_KERNEL);
96 if (!bus) 107 if (!bus)
97 return -ENOMEM; 108 return -ENOMEM;
98 109
99 /* The platform_device id is our unit number. */ 110 res_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
100 bus->unit = pdev->id; 111
112 if (res_mem == NULL) {
113 dev_err(&pdev->dev, "found no memory resource\n");
114 err = -ENXIO;
115 goto fail;
116 }
117 bus->mdio_phys = res_mem->start;
118 bus->regsize = resource_size(res_mem);
119 if (!devm_request_mem_region(&pdev->dev, bus->mdio_phys, bus->regsize,
120 res_mem->name)) {
121 dev_err(&pdev->dev, "request_mem_region failed\n");
122 goto fail;
123 }
124 bus->register_base =
125 (u64)devm_ioremap(&pdev->dev, bus->mdio_phys, bus->regsize);
101 126
102 bus->mii_bus = mdiobus_alloc(); 127 bus->mii_bus = mdiobus_alloc();
103 128
104 if (!bus->mii_bus) 129 if (!bus->mii_bus)
105 goto err; 130 goto fail;
106 131
107 smi_en.u64 = 0; 132 smi_en.u64 = 0;
108 smi_en.s.en = 1; 133 smi_en.s.en = 1;
109 cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); 134 cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
110
111 /*
112 * Standard Octeon evaluation boards don't support phy
113 * interrupts, we need to poll.
114 */
115 for (i = 0; i < PHY_MAX_ADDR; i++)
116 bus->phy_irq[i] = PHY_POLL;
117 135
118 bus->mii_bus->priv = bus; 136 bus->mii_bus->priv = bus;
119 bus->mii_bus->irq = bus->phy_irq; 137 bus->mii_bus->irq = bus->phy_irq;
120 bus->mii_bus->name = "mdio-octeon"; 138 bus->mii_bus->name = "mdio-octeon";
121 snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", 139 snprintf(bus->mii_bus->id, MII_BUS_ID_SIZE, "%llx", bus->register_base);
122 bus->mii_bus->name, bus->unit);
123 bus->mii_bus->parent = &pdev->dev; 140 bus->mii_bus->parent = &pdev->dev;
124 141
125 bus->mii_bus->read = octeon_mdiobus_read; 142 bus->mii_bus->read = octeon_mdiobus_read;
@@ -127,20 +144,18 @@ static int __devinit octeon_mdiobus_probe(struct platform_device *pdev)
127 144
128 dev_set_drvdata(&pdev->dev, bus); 145 dev_set_drvdata(&pdev->dev, bus);
129 146
130 err = mdiobus_register(bus->mii_bus); 147 err = of_mdiobus_register(bus->mii_bus, pdev->dev.of_node);
131 if (err) 148 if (err)
132 goto err_register; 149 goto fail_register;
133 150
134 dev_info(&pdev->dev, "Version " DRV_VERSION "\n"); 151 dev_info(&pdev->dev, "Version " DRV_VERSION "\n");
135 152
136 return 0; 153 return 0;
137err_register: 154fail_register:
138 mdiobus_free(bus->mii_bus); 155 mdiobus_free(bus->mii_bus);
139 156fail:
140err:
141 devm_kfree(&pdev->dev, bus);
142 smi_en.u64 = 0; 157 smi_en.u64 = 0;
143 cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); 158 cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
144 return err; 159 return err;
145} 160}
146 161
@@ -154,14 +169,23 @@ static int __devexit octeon_mdiobus_remove(struct platform_device *pdev)
154 mdiobus_unregister(bus->mii_bus); 169 mdiobus_unregister(bus->mii_bus);
155 mdiobus_free(bus->mii_bus); 170 mdiobus_free(bus->mii_bus);
156 smi_en.u64 = 0; 171 smi_en.u64 = 0;
157 cvmx_write_csr(CVMX_SMIX_EN(bus->unit), smi_en.u64); 172 cvmx_write_csr(bus->register_base + SMI_EN, smi_en.u64);
158 return 0; 173 return 0;
159} 174}
160 175
176static struct of_device_id octeon_mdiobus_match[] = {
177 {
178 .compatible = "cavium,octeon-3860-mdio",
179 },
180 {},
181};
182MODULE_DEVICE_TABLE(of, octeon_mdiobus_match);
183
161static struct platform_driver octeon_mdiobus_driver = { 184static struct platform_driver octeon_mdiobus_driver = {
162 .driver = { 185 .driver = {
163 .name = "mdio-octeon", 186 .name = "mdio-octeon",
164 .owner = THIS_MODULE, 187 .owner = THIS_MODULE,
188 .of_match_table = octeon_mdiobus_match,
165 }, 189 },
166 .probe = octeon_mdiobus_probe, 190 .probe = octeon_mdiobus_probe,
167 .remove = __devexit_p(octeon_mdiobus_remove), 191 .remove = __devexit_p(octeon_mdiobus_remove),
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index cd2fe350e724..b18abf31fd08 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -144,6 +144,15 @@ config SPI_EP93XX
144 This enables using the Cirrus EP93xx SPI controller in master 144 This enables using the Cirrus EP93xx SPI controller in master
145 mode. 145 mode.
146 146
147config SPI_FALCON
148 tristate "Falcon SPI controller support"
149 depends on SOC_FALCON
150 help
151 The external bus unit (EBU) found on the FALC-ON SoC has SPI
152 emulation that is designed for serial flash access. This driver
153 has only been tested with m25p80 type chips. The hardware has no
154 support for other types of SPI peripherals.
155
147config SPI_GPIO 156config SPI_GPIO
148 tristate "GPIO-based bitbanging SPI Master" 157 tristate "GPIO-based bitbanging SPI Master"
149 depends on GENERIC_GPIO 158 depends on GENERIC_GPIO
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index 9d75d2198ff5..b5cbab2b5ab0 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -26,6 +26,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmio.o
26obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o 26obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o
27spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o 27spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o
28obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o 28obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o
29obj-$(CONFIG_SPI_FALCON) += spi-falcon.o
29obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o 30obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o
30obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o 31obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o
31obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o 32obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o
diff --git a/drivers/spi/spi-falcon.c b/drivers/spi/spi-falcon.c
new file mode 100644
index 000000000000..8f6aa735a24c
--- /dev/null
+++ b/drivers/spi/spi-falcon.c
@@ -0,0 +1,469 @@
1/*
2 * This program is free software; you can redistribute it and/or modify it
3 * under the terms of the GNU General Public License version 2 as published
4 * by the Free Software Foundation.
5 *
6 * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
7 */
8
9#include <linux/module.h>
10#include <linux/device.h>
11#include <linux/platform_device.h>
12#include <linux/spi/spi.h>
13#include <linux/delay.h>
14#include <linux/workqueue.h>
15#include <linux/of.h>
16#include <linux/of_platform.h>
17
18#include <lantiq_soc.h>
19
20#define DRV_NAME "sflash-falcon"
21
22#define FALCON_SPI_XFER_BEGIN (1 << 0)
23#define FALCON_SPI_XFER_END (1 << 1)
24
25/* Bus Read Configuration Register0 */
26#define BUSRCON0 0x00000010
27/* Bus Write Configuration Register0 */
28#define BUSWCON0 0x00000018
29/* Serial Flash Configuration Register */
30#define SFCON 0x00000080
31/* Serial Flash Time Register */
32#define SFTIME 0x00000084
33/* Serial Flash Status Register */
34#define SFSTAT 0x00000088
35/* Serial Flash Command Register */
36#define SFCMD 0x0000008C
37/* Serial Flash Address Register */
38#define SFADDR 0x00000090
39/* Serial Flash Data Register */
40#define SFDATA 0x00000094
41/* Serial Flash I/O Control Register */
42#define SFIO 0x00000098
43/* EBU Clock Control Register */
44#define EBUCC 0x000000C4
45
46/* Dummy Phase Length */
47#define SFCMD_DUMLEN_OFFSET 16
48#define SFCMD_DUMLEN_MASK 0x000F0000
49/* Chip Select */
50#define SFCMD_CS_OFFSET 24
51#define SFCMD_CS_MASK 0x07000000
52/* field offset */
53#define SFCMD_ALEN_OFFSET 20
54#define SFCMD_ALEN_MASK 0x00700000
55/* SCK Rise-edge Position */
56#define SFTIME_SCKR_POS_OFFSET 8
57#define SFTIME_SCKR_POS_MASK 0x00000F00
58/* SCK Period */
59#define SFTIME_SCK_PER_OFFSET 0
60#define SFTIME_SCK_PER_MASK 0x0000000F
61/* SCK Fall-edge Position */
62#define SFTIME_SCKF_POS_OFFSET 12
63#define SFTIME_SCKF_POS_MASK 0x0000F000
64/* Device Size */
65#define SFCON_DEV_SIZE_A23_0 0x03000000
66#define SFCON_DEV_SIZE_MASK 0x0F000000
67/* Read Data Position */
68#define SFTIME_RD_POS_MASK 0x000F0000
69/* Data Output */
70#define SFIO_UNUSED_WD_MASK 0x0000000F
71/* Command Opcode mask */
72#define SFCMD_OPC_MASK 0x000000FF
73/* dlen bytes of data to write */
74#define SFCMD_DIR_WRITE 0x00000100
75/* Data Length offset */
76#define SFCMD_DLEN_OFFSET 9
77/* Command Error */
78#define SFSTAT_CMD_ERR 0x20000000
79/* Access Command Pending */
80#define SFSTAT_CMD_PEND 0x00400000
81/* Frequency set to 100MHz. */
82#define EBUCC_EBUDIV_SELF100 0x00000001
83/* Serial Flash */
84#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000
85/* 8-bit multiplexed */
86#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000
87/* Serial Flash */
88#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000
89/* Chip Select after opcode */
90#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000
91
92#define CLOCK_100M 100000000
93#define CLOCK_50M 50000000
94
95struct falcon_sflash {
96 u32 sfcmd; /* for caching of opcode, direction, ... */
97 struct spi_master *master;
98};
99
100int falcon_sflash_xfer(struct spi_device *spi, struct spi_transfer *t,
101 unsigned long flags)
102{
103 struct device *dev = &spi->dev;
104 struct falcon_sflash *priv = spi_master_get_devdata(spi->master);
105 const u8 *txp = t->tx_buf;
106 u8 *rxp = t->rx_buf;
107 unsigned int bytelen = ((8 * t->len + 7) / 8);
108 unsigned int len, alen, dumlen;
109 u32 val;
110 enum {
111 state_init,
112 state_command_prepare,
113 state_write,
114 state_read,
115 state_disable_cs,
116 state_end
117 } state = state_init;
118
119 do {
120 switch (state) {
121 case state_init: /* detect phase of upper layer sequence */
122 {
123 /* initial write ? */
124 if (flags & FALCON_SPI_XFER_BEGIN) {
125 if (!txp) {
126 dev_err(dev,
127 "BEGIN without tx data!\n");
128 return -ENODATA;
129 }
130 /*
131 * Prepare the parts of the sfcmd register,
132 * which should not change during a sequence!
133 * Only exception are the length fields,
134 * especially alen and dumlen.
135 */
136
137 priv->sfcmd = ((spi->chip_select
138 << SFCMD_CS_OFFSET)
139 & SFCMD_CS_MASK);
140 priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED;
141 priv->sfcmd |= *txp;
142 txp++;
143 bytelen--;
144 if (bytelen) {
145 /*
146 * more data:
147 * maybe address and/or dummy
148 */
149 state = state_command_prepare;
150 break;
151 } else {
152 dev_dbg(dev, "write cmd %02X\n",
153 priv->sfcmd & SFCMD_OPC_MASK);
154 }
155 }
156 /* continued write ? */
157 if (txp && bytelen) {
158 state = state_write;
159 break;
160 }
161 /* read data? */
162 if (rxp && bytelen) {
163 state = state_read;
164 break;
165 }
166 /* end of sequence? */
167 if (flags & FALCON_SPI_XFER_END)
168 state = state_disable_cs;
169 else
170 state = state_end;
171 break;
172 }
173 /* collect tx data for address and dummy phase */
174 case state_command_prepare:
175 {
176 /* txp is valid, already checked */
177 val = 0;
178 alen = 0;
179 dumlen = 0;
180 while (bytelen > 0) {
181 if (alen < 3) {
182 val = (val << 8) | (*txp++);
183 alen++;
184 } else if ((dumlen < 15) && (*txp == 0)) {
185 /*
186 * assume dummy bytes are set to 0
187 * from upper layer
188 */
189 dumlen++;
190 txp++;
191 } else {
192 break;
193 }
194 bytelen--;
195 }
196 priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK);
197 priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) |
198 (dumlen << SFCMD_DUMLEN_OFFSET);
199 if (alen > 0)
200 ltq_ebu_w32(val, SFADDR);
201
202 dev_dbg(dev, "wr %02X, alen=%d (addr=%06X) dlen=%d\n",
203 priv->sfcmd & SFCMD_OPC_MASK,
204 alen, val, dumlen);
205
206 if (bytelen > 0) {
207 /* continue with write */
208 state = state_write;
209 } else if (flags & FALCON_SPI_XFER_END) {
210 /* end of sequence? */
211 state = state_disable_cs;
212 } else {
213 /*
214 * go to end and expect another
215 * call (read or write)
216 */
217 state = state_end;
218 }
219 break;
220 }
221 case state_write:
222 {
223 /* txp still valid */
224 priv->sfcmd |= SFCMD_DIR_WRITE;
225 len = 0;
226 val = 0;
227 do {
228 if (bytelen--)
229 val |= (*txp++) << (8 * len++);
230 if ((flags & FALCON_SPI_XFER_END)
231 && (bytelen == 0)) {
232 priv->sfcmd &=
233 ~SFCMD_KEEP_CS_KEEP_SELECTED;
234 }
235 if ((len == 4) || (bytelen == 0)) {
236 ltq_ebu_w32(val, SFDATA);
237 ltq_ebu_w32(priv->sfcmd
238 | (len<<SFCMD_DLEN_OFFSET),
239 SFCMD);
240 len = 0;
241 val = 0;
242 priv->sfcmd &= ~(SFCMD_ALEN_MASK
243 | SFCMD_DUMLEN_MASK);
244 }
245 } while (bytelen);
246 state = state_end;
247 break;
248 }
249 case state_read:
250 {
251 /* read data */
252 priv->sfcmd &= ~SFCMD_DIR_WRITE;
253 do {
254 if ((flags & FALCON_SPI_XFER_END)
255 && (bytelen <= 4)) {
256 priv->sfcmd &=
257 ~SFCMD_KEEP_CS_KEEP_SELECTED;
258 }
259 len = (bytelen > 4) ? 4 : bytelen;
260 bytelen -= len;
261 ltq_ebu_w32(priv->sfcmd
262 | (len << SFCMD_DLEN_OFFSET), SFCMD);
263 priv->sfcmd &= ~(SFCMD_ALEN_MASK
264 | SFCMD_DUMLEN_MASK);
265 do {
266 val = ltq_ebu_r32(SFSTAT);
267 if (val & SFSTAT_CMD_ERR) {
268 /* reset error status */
269 dev_err(dev, "SFSTAT: CMD_ERR");
270 dev_err(dev, " (%x)\n", val);
271 ltq_ebu_w32(SFSTAT_CMD_ERR,
272 SFSTAT);
273 return -EBADE;
274 }
275 } while (val & SFSTAT_CMD_PEND);
276 val = ltq_ebu_r32(SFDATA);
277 do {
278 *rxp = (val & 0xFF);
279 rxp++;
280 val >>= 8;
281 len--;
282 } while (len);
283 } while (bytelen);
284 state = state_end;
285 break;
286 }
287 case state_disable_cs:
288 {
289 priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED;
290 ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET),
291 SFCMD);
292 val = ltq_ebu_r32(SFSTAT);
293 if (val & SFSTAT_CMD_ERR) {
294 /* reset error status */
295 dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val);
296 ltq_ebu_w32(SFSTAT_CMD_ERR, SFSTAT);
297 return -EBADE;
298 }
299 state = state_end;
300 break;
301 }
302 case state_end:
303 break;
304 }
305 } while (state != state_end);
306
307 return 0;
308}
309
310static int falcon_sflash_setup(struct spi_device *spi)
311{
312 unsigned int i;
313 unsigned long flags;
314
315 if (spi->chip_select > 0)
316 return -ENODEV;
317
318 spin_lock_irqsave(&ebu_lock, flags);
319
320 if (spi->max_speed_hz >= CLOCK_100M) {
321 /* set EBU clock to 100 MHz */
322 ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, EBUCC);
323 i = 1; /* divider */
324 } else {
325 /* set EBU clock to 50 MHz */
326 ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, EBUCC);
327
328 /* search for suitable divider */
329 for (i = 1; i < 7; i++) {
330 if (CLOCK_50M / i <= spi->max_speed_hz)
331 break;
332 }
333 }
334
335 /* setup period of serial clock */
336 ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK
337 | SFTIME_SCKR_POS_MASK
338 | SFTIME_SCK_PER_MASK,
339 (i << SFTIME_SCKR_POS_OFFSET)
340 | (i << (SFTIME_SCK_PER_OFFSET + 1)),
341 SFTIME);
342
343 /*
344 * set some bits of unused_wd, to not trigger HOLD/WP
345 * signals on non QUAD flashes
346 */
347 ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), SFIO);
348
349 ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX,
350 BUSRCON0);
351 ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, BUSWCON0);
352 /* set address wrap around to maximum for 24-bit addresses */
353 ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, SFCON);
354
355 spin_unlock_irqrestore(&ebu_lock, flags);
356
357 return 0;
358}
359
360static int falcon_sflash_prepare_xfer(struct spi_master *master)
361{
362 return 0;
363}
364
365static int falcon_sflash_unprepare_xfer(struct spi_master *master)
366{
367 return 0;
368}
369
370static int falcon_sflash_xfer_one(struct spi_master *master,
371 struct spi_message *m)
372{
373 struct falcon_sflash *priv = spi_master_get_devdata(master);
374 struct spi_transfer *t;
375 unsigned long spi_flags;
376 unsigned long flags;
377 int ret = 0;
378
379 priv->sfcmd = 0;
380 m->actual_length = 0;
381
382 spi_flags = FALCON_SPI_XFER_BEGIN;
383 list_for_each_entry(t, &m->transfers, transfer_list) {
384 if (list_is_last(&t->transfer_list, &m->transfers))
385 spi_flags |= FALCON_SPI_XFER_END;
386
387 spin_lock_irqsave(&ebu_lock, flags);
388 ret = falcon_sflash_xfer(m->spi, t, spi_flags);
389 spin_unlock_irqrestore(&ebu_lock, flags);
390
391 if (ret)
392 break;
393
394 m->actual_length += t->len;
395
396 WARN_ON(t->delay_usecs || t->cs_change);
397 spi_flags = 0;
398 }
399
400 m->status = ret;
401 m->complete(m->context);
402
403 return 0;
404}
405
406static int __devinit falcon_sflash_probe(struct platform_device *pdev)
407{
408 struct falcon_sflash *priv;
409 struct spi_master *master;
410 int ret;
411
412 if (ltq_boot_select() != BS_SPI) {
413 dev_err(&pdev->dev, "invalid bootstrap options\n");
414 return -ENODEV;
415 }
416
417 master = spi_alloc_master(&pdev->dev, sizeof(*priv));
418 if (!master)
419 return -ENOMEM;
420
421 priv = spi_master_get_devdata(master);
422 priv->master = master;
423
424 master->mode_bits = SPI_MODE_3;
425 master->num_chipselect = 1;
426 master->bus_num = -1;
427 master->setup = falcon_sflash_setup;
428 master->prepare_transfer_hardware = falcon_sflash_prepare_xfer;
429 master->transfer_one_message = falcon_sflash_xfer_one;
430 master->unprepare_transfer_hardware = falcon_sflash_unprepare_xfer;
431 master->dev.of_node = pdev->dev.of_node;
432
433 platform_set_drvdata(pdev, priv);
434
435 ret = spi_register_master(master);
436 if (ret)
437 spi_master_put(master);
438 return ret;
439}
440
441static int __devexit falcon_sflash_remove(struct platform_device *pdev)
442{
443 struct falcon_sflash *priv = platform_get_drvdata(pdev);
444
445 spi_unregister_master(priv->master);
446
447 return 0;
448}
449
450static const struct of_device_id falcon_sflash_match[] = {
451 { .compatible = "lantiq,sflash-falcon" },
452 {},
453};
454MODULE_DEVICE_TABLE(of, falcon_sflash_match);
455
456static struct platform_driver falcon_sflash_driver = {
457 .probe = falcon_sflash_probe,
458 .remove = __devexit_p(falcon_sflash_remove),
459 .driver = {
460 .name = DRV_NAME,
461 .owner = THIS_MODULE,
462 .of_match_table = falcon_sflash_match,
463 }
464};
465
466module_platform_driver(falcon_sflash_driver);
467
468MODULE_LICENSE("GPL");
469MODULE_DESCRIPTION("Lantiq Falcon SPI/SFLASH controller driver");
diff --git a/drivers/staging/octeon/ethernet-mdio.c b/drivers/staging/octeon/ethernet-mdio.c
index e31949c9c87e..f15b31b37ca5 100644
--- a/drivers/staging/octeon/ethernet-mdio.c
+++ b/drivers/staging/octeon/ethernet-mdio.c
@@ -28,6 +28,7 @@
28#include <linux/ethtool.h> 28#include <linux/ethtool.h>
29#include <linux/phy.h> 29#include <linux/phy.h>
30#include <linux/ratelimit.h> 30#include <linux/ratelimit.h>
31#include <linux/of_mdio.h>
31 32
32#include <net/dst.h> 33#include <net/dst.h>
33 34
@@ -161,22 +162,23 @@ static void cvm_oct_adjust_link(struct net_device *dev)
161int cvm_oct_phy_setup_device(struct net_device *dev) 162int cvm_oct_phy_setup_device(struct net_device *dev)
162{ 163{
163 struct octeon_ethernet *priv = netdev_priv(dev); 164 struct octeon_ethernet *priv = netdev_priv(dev);
165 struct device_node *phy_node;
164 166
165 int phy_addr = cvmx_helper_board_get_mii_address(priv->port); 167 if (!priv->of_node)
166 if (phy_addr != -1) { 168 return 0;
167 char phy_id[MII_BUS_ID_SIZE + 3];
168 169
169 snprintf(phy_id, sizeof(phy_id), PHY_ID_FMT, "mdio-octeon-0", phy_addr); 170 phy_node = of_parse_phandle(priv->of_node, "phy-handle", 0);
171 if (!phy_node)
172 return 0;
170 173
171 priv->phydev = phy_connect(dev, phy_id, cvm_oct_adjust_link, 0, 174 priv->phydev = of_phy_connect(dev, phy_node, cvm_oct_adjust_link, 0,
172 PHY_INTERFACE_MODE_GMII); 175 PHY_INTERFACE_MODE_GMII);
176
177 if (priv->phydev == NULL)
178 return -ENODEV;
179
180 priv->last_link = 0;
181 phy_start_aneg(priv->phydev);
173 182
174 if (IS_ERR(priv->phydev)) {
175 priv->phydev = NULL;
176 return -1;
177 }
178 priv->last_link = 0;
179 phy_start_aneg(priv->phydev);
180 }
181 return 0; 183 return 0;
182} 184}
diff --git a/drivers/staging/octeon/ethernet.c b/drivers/staging/octeon/ethernet.c
index 18f7a790f73d..683bedc74dde 100644
--- a/drivers/staging/octeon/ethernet.c
+++ b/drivers/staging/octeon/ethernet.c
@@ -24,6 +24,7 @@
24 * This file may also be available under a different license from Cavium. 24 * This file may also be available under a different license from Cavium.
25 * Contact Cavium Networks for more information 25 * Contact Cavium Networks for more information
26**********************************************************************/ 26**********************************************************************/
27#include <linux/platform_device.h>
27#include <linux/kernel.h> 28#include <linux/kernel.h>
28#include <linux/init.h> 29#include <linux/init.h>
29#include <linux/module.h> 30#include <linux/module.h>
@@ -32,6 +33,7 @@
32#include <linux/phy.h> 33#include <linux/phy.h>
33#include <linux/slab.h> 34#include <linux/slab.h>
34#include <linux/interrupt.h> 35#include <linux/interrupt.h>
36#include <linux/of_net.h>
35 37
36#include <net/dst.h> 38#include <net/dst.h>
37 39
@@ -113,15 +115,6 @@ int rx_napi_weight = 32;
113module_param(rx_napi_weight, int, 0444); 115module_param(rx_napi_weight, int, 0444);
114MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter."); 116MODULE_PARM_DESC(rx_napi_weight, "The NAPI WEIGHT parameter.");
115 117
116/*
117 * The offset from mac_addr_base that should be used for the next port
118 * that is configured. By convention, if any mgmt ports exist on the
119 * chip, they get the first mac addresses, The ports controlled by
120 * this driver are numbered sequencially following any mgmt addresses
121 * that may exist.
122 */
123static unsigned int cvm_oct_mac_addr_offset;
124
125/** 118/**
126 * cvm_oct_poll_queue - Workqueue for polling operations. 119 * cvm_oct_poll_queue - Workqueue for polling operations.
127 */ 120 */
@@ -176,7 +169,7 @@ static void cvm_oct_periodic_worker(struct work_struct *work)
176 queue_delayed_work(cvm_oct_poll_queue, &priv->port_periodic_work, HZ); 169 queue_delayed_work(cvm_oct_poll_queue, &priv->port_periodic_work, HZ);
177 } 170 }
178 171
179static __init void cvm_oct_configure_common_hw(void) 172static __devinit void cvm_oct_configure_common_hw(void)
180{ 173{
181 /* Setup the FPA */ 174 /* Setup the FPA */
182 cvmx_fpa_enable(); 175 cvmx_fpa_enable();
@@ -396,23 +389,21 @@ static void cvm_oct_common_set_multicast_list(struct net_device *dev)
396 389
397 * Returns Zero on success 390 * Returns Zero on success
398 */ 391 */
399static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr) 392static int cvm_oct_set_mac_filter(struct net_device *dev)
400{ 393{
401 struct octeon_ethernet *priv = netdev_priv(dev); 394 struct octeon_ethernet *priv = netdev_priv(dev);
402 union cvmx_gmxx_prtx_cfg gmx_cfg; 395 union cvmx_gmxx_prtx_cfg gmx_cfg;
403 int interface = INTERFACE(priv->port); 396 int interface = INTERFACE(priv->port);
404 int index = INDEX(priv->port); 397 int index = INDEX(priv->port);
405 398
406 memcpy(dev->dev_addr, addr + 2, 6);
407
408 if ((interface < 2) 399 if ((interface < 2)
409 && (cvmx_helper_interface_get_mode(interface) != 400 && (cvmx_helper_interface_get_mode(interface) !=
410 CVMX_HELPER_INTERFACE_MODE_SPI)) { 401 CVMX_HELPER_INTERFACE_MODE_SPI)) {
411 int i; 402 int i;
412 uint8_t *ptr = addr; 403 uint8_t *ptr = dev->dev_addr;
413 uint64_t mac = 0; 404 uint64_t mac = 0;
414 for (i = 0; i < 6; i++) 405 for (i = 0; i < 6; i++)
415 mac = (mac << 8) | (uint64_t) (ptr[i + 2]); 406 mac = (mac << 8) | (uint64_t)ptr[i];
416 407
417 gmx_cfg.u64 = 408 gmx_cfg.u64 =
418 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface)); 409 cvmx_read_csr(CVMX_GMXX_PRTX_CFG(index, interface));
@@ -421,17 +412,17 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr)
421 412
422 cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac); 413 cvmx_write_csr(CVMX_GMXX_SMACX(index, interface), mac);
423 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface), 414 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM0(index, interface),
424 ptr[2]); 415 ptr[0]);
425 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface), 416 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM1(index, interface),
426 ptr[3]); 417 ptr[1]);
427 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface), 418 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM2(index, interface),
428 ptr[4]); 419 ptr[2]);
429 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface), 420 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM3(index, interface),
430 ptr[5]); 421 ptr[3]);
431 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface), 422 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM4(index, interface),
432 ptr[6]); 423 ptr[4]);
433 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface), 424 cvmx_write_csr(CVMX_GMXX_RXX_ADR_CAM5(index, interface),
434 ptr[7]); 425 ptr[5]);
435 cvm_oct_common_set_multicast_list(dev); 426 cvm_oct_common_set_multicast_list(dev);
436 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface), 427 cvmx_write_csr(CVMX_GMXX_PRTX_CFG(index, interface),
437 gmx_cfg.u64); 428 gmx_cfg.u64);
@@ -439,6 +430,15 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr)
439 return 0; 430 return 0;
440} 431}
441 432
433static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr)
434{
435 int r = eth_mac_addr(dev, addr);
436
437 if (r)
438 return r;
439 return cvm_oct_set_mac_filter(dev);
440}
441
442/** 442/**
443 * cvm_oct_common_init - per network device initialization 443 * cvm_oct_common_init - per network device initialization
444 * @dev: Device to initialize 444 * @dev: Device to initialize
@@ -448,26 +448,17 @@ static int cvm_oct_common_set_mac_address(struct net_device *dev, void *addr)
448int cvm_oct_common_init(struct net_device *dev) 448int cvm_oct_common_init(struct net_device *dev)
449{ 449{
450 struct octeon_ethernet *priv = netdev_priv(dev); 450 struct octeon_ethernet *priv = netdev_priv(dev);
451 struct sockaddr sa; 451 const u8 *mac = NULL;
452 u64 mac = ((u64)(octeon_bootinfo->mac_addr_base[0] & 0xff) << 40) | 452
453 ((u64)(octeon_bootinfo->mac_addr_base[1] & 0xff) << 32) | 453 if (priv->of_node)
454 ((u64)(octeon_bootinfo->mac_addr_base[2] & 0xff) << 24) | 454 mac = of_get_mac_address(priv->of_node);
455 ((u64)(octeon_bootinfo->mac_addr_base[3] & 0xff) << 16) | 455
456 ((u64)(octeon_bootinfo->mac_addr_base[4] & 0xff) << 8) | 456 if (mac && is_valid_ether_addr(mac)) {
457 (u64)(octeon_bootinfo->mac_addr_base[5] & 0xff); 457 memcpy(dev->dev_addr, mac, ETH_ALEN);
458 458 dev->addr_assign_type &= ~NET_ADDR_RANDOM;
459 mac += cvm_oct_mac_addr_offset; 459 } else {
460 sa.sa_data[0] = (mac >> 40) & 0xff; 460 eth_hw_addr_random(dev);
461 sa.sa_data[1] = (mac >> 32) & 0xff; 461 }
462 sa.sa_data[2] = (mac >> 24) & 0xff;
463 sa.sa_data[3] = (mac >> 16) & 0xff;
464 sa.sa_data[4] = (mac >> 8) & 0xff;
465 sa.sa_data[5] = mac & 0xff;
466
467 if (cvm_oct_mac_addr_offset >= octeon_bootinfo->mac_addr_count)
468 printk(KERN_DEBUG "%s: Using MAC outside of the assigned range:"
469 " %pM\n", dev->name, sa.sa_data);
470 cvm_oct_mac_addr_offset++;
471 462
472 /* 463 /*
473 * Force the interface to use the POW send if always_use_pow 464 * Force the interface to use the POW send if always_use_pow
@@ -488,7 +479,7 @@ int cvm_oct_common_init(struct net_device *dev)
488 SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops); 479 SET_ETHTOOL_OPS(dev, &cvm_oct_ethtool_ops);
489 480
490 cvm_oct_phy_setup_device(dev); 481 cvm_oct_phy_setup_device(dev);
491 dev->netdev_ops->ndo_set_mac_address(dev, &sa); 482 cvm_oct_set_mac_filter(dev);
492 dev->netdev_ops->ndo_change_mtu(dev, dev->mtu); 483 dev->netdev_ops->ndo_change_mtu(dev, dev->mtu);
493 484
494 /* 485 /*
@@ -595,22 +586,55 @@ static const struct net_device_ops cvm_oct_pow_netdev_ops = {
595 586
596extern void octeon_mdiobus_force_mod_depencency(void); 587extern void octeon_mdiobus_force_mod_depencency(void);
597 588
598static int __init cvm_oct_init_module(void) 589static struct device_node * __devinit cvm_oct_of_get_child(const struct device_node *parent,
590 int reg_val)
591{
592 struct device_node *node = NULL;
593 int size;
594 const __be32 *addr;
595
596 for (;;) {
597 node = of_get_next_child(parent, node);
598 if (!node)
599 break;
600 addr = of_get_property(node, "reg", &size);
601 if (addr && (be32_to_cpu(*addr) == reg_val))
602 break;
603 }
604 return node;
605}
606
607static struct device_node * __devinit cvm_oct_node_for_port(struct device_node *pip,
608 int interface, int port)
609{
610 struct device_node *ni, *np;
611
612 ni = cvm_oct_of_get_child(pip, interface);
613 if (!ni)
614 return NULL;
615
616 np = cvm_oct_of_get_child(ni, port);
617 of_node_put(ni);
618
619 return np;
620}
621
622static int __devinit cvm_oct_probe(struct platform_device *pdev)
599{ 623{
600 int num_interfaces; 624 int num_interfaces;
601 int interface; 625 int interface;
602 int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE; 626 int fau = FAU_NUM_PACKET_BUFFERS_TO_FREE;
603 int qos; 627 int qos;
628 struct device_node *pip;
604 629
605 octeon_mdiobus_force_mod_depencency(); 630 octeon_mdiobus_force_mod_depencency();
606 pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION); 631 pr_notice("cavium-ethernet %s\n", OCTEON_ETHERNET_VERSION);
607 632
608 if (OCTEON_IS_MODEL(OCTEON_CN52XX)) 633 pip = pdev->dev.of_node;
609 cvm_oct_mac_addr_offset = 2; /* First two are the mgmt ports. */ 634 if (!pip) {
610 else if (OCTEON_IS_MODEL(OCTEON_CN56XX)) 635 pr_err("Error: No 'pip' in /aliases\n");
611 cvm_oct_mac_addr_offset = 1; /* First one is the mgmt port. */ 636 return -EINVAL;
612 else 637 }
613 cvm_oct_mac_addr_offset = 0;
614 638
615 cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet"); 639 cvm_oct_poll_queue = create_singlethread_workqueue("octeon-ethernet");
616 if (cvm_oct_poll_queue == NULL) { 640 if (cvm_oct_poll_queue == NULL) {
@@ -689,10 +713,11 @@ static int __init cvm_oct_init_module(void)
689 cvmx_helper_interface_get_mode(interface); 713 cvmx_helper_interface_get_mode(interface);
690 int num_ports = cvmx_helper_ports_on_interface(interface); 714 int num_ports = cvmx_helper_ports_on_interface(interface);
691 int port; 715 int port;
716 int port_index;
692 717
693 for (port = cvmx_helper_get_ipd_port(interface, 0); 718 for (port_index = 0, port = cvmx_helper_get_ipd_port(interface, 0);
694 port < cvmx_helper_get_ipd_port(interface, num_ports); 719 port < cvmx_helper_get_ipd_port(interface, num_ports);
695 port++) { 720 port_index++, port++) {
696 struct octeon_ethernet *priv; 721 struct octeon_ethernet *priv;
697 struct net_device *dev = 722 struct net_device *dev =
698 alloc_etherdev(sizeof(struct octeon_ethernet)); 723 alloc_etherdev(sizeof(struct octeon_ethernet));
@@ -703,6 +728,7 @@ static int __init cvm_oct_init_module(void)
703 728
704 /* Initialize the device private structure. */ 729 /* Initialize the device private structure. */
705 priv = netdev_priv(dev); 730 priv = netdev_priv(dev);
731 priv->of_node = cvm_oct_node_for_port(pip, interface, port_index);
706 732
707 INIT_DELAYED_WORK(&priv->port_periodic_work, 733 INIT_DELAYED_WORK(&priv->port_periodic_work,
708 cvm_oct_periodic_worker); 734 cvm_oct_periodic_worker);
@@ -787,7 +813,7 @@ static int __init cvm_oct_init_module(void)
787 return 0; 813 return 0;
788} 814}
789 815
790static void __exit cvm_oct_cleanup_module(void) 816static int __devexit cvm_oct_remove(struct platform_device *pdev)
791{ 817{
792 int port; 818 int port;
793 819
@@ -835,10 +861,29 @@ static void __exit cvm_oct_cleanup_module(void)
835 if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL) 861 if (CVMX_FPA_OUTPUT_BUFFER_POOL != CVMX_FPA_PACKET_POOL)
836 cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL, 862 cvm_oct_mem_empty_fpa(CVMX_FPA_OUTPUT_BUFFER_POOL,
837 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128); 863 CVMX_FPA_OUTPUT_BUFFER_POOL_SIZE, 128);
864 return 0;
838} 865}
839 866
867static struct of_device_id cvm_oct_match[] = {
868 {
869 .compatible = "cavium,octeon-3860-pip",
870 },
871 {},
872};
873MODULE_DEVICE_TABLE(of, cvm_oct_match);
874
875static struct platform_driver cvm_oct_driver = {
876 .probe = cvm_oct_probe,
877 .remove = __devexit_p(cvm_oct_remove),
878 .driver = {
879 .owner = THIS_MODULE,
880 .name = KBUILD_MODNAME,
881 .of_match_table = cvm_oct_match,
882 },
883};
884
885module_platform_driver(cvm_oct_driver);
886
840MODULE_LICENSE("GPL"); 887MODULE_LICENSE("GPL");
841MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>"); 888MODULE_AUTHOR("Cavium Networks <support@caviumnetworks.com>");
842MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver."); 889MODULE_DESCRIPTION("Cavium Networks Octeon ethernet driver.");
843module_init(cvm_oct_init_module);
844module_exit(cvm_oct_cleanup_module);
diff --git a/drivers/staging/octeon/octeon-ethernet.h b/drivers/staging/octeon/octeon-ethernet.h
index d58192563552..9360e22e0739 100644
--- a/drivers/staging/octeon/octeon-ethernet.h
+++ b/drivers/staging/octeon/octeon-ethernet.h
@@ -31,6 +31,8 @@
31#ifndef OCTEON_ETHERNET_H 31#ifndef OCTEON_ETHERNET_H
32#define OCTEON_ETHERNET_H 32#define OCTEON_ETHERNET_H
33 33
34#include <linux/of.h>
35
34/** 36/**
35 * This is the definition of the Ethernet driver's private 37 * This is the definition of the Ethernet driver's private
36 * driver state stored in netdev_priv(dev). 38 * driver state stored in netdev_priv(dev).
@@ -59,6 +61,7 @@ struct octeon_ethernet {
59 void (*poll) (struct net_device *dev); 61 void (*poll) (struct net_device *dev);
60 struct delayed_work port_periodic_work; 62 struct delayed_work port_periodic_work;
61 struct work_struct port_work; /* may be unused. */ 63 struct work_struct port_work; /* may be unused. */
64 struct device_node *of_node;
62}; 65};
63 66
64int cvm_oct_free_work(void *work_queue_entry); 67int cvm_oct_free_work(void *work_queue_entry);
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-27 11:35:34 -0500