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-rw-r--r--drivers/mtd/nand/davinci_nand.c22
1 files changed, 0 insertions, 22 deletions
diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c
index a4989ec6292e..8eb6a36f125a 100644
--- a/drivers/mtd/nand/davinci_nand.c
+++ b/drivers/mtd/nand/davinci_nand.c
@@ -746,28 +746,6 @@ static int nand_davinci_probe(struct platform_device *pdev)
746 goto err_clk_enable; 746 goto err_clk_enable;
747 } 747 }
748 748
749 /*
750 * Setup Async configuration register in case we did not boot from
751 * NAND and so bootloader did not bother to set it up.
752 */
753 val = davinci_nand_readl(info, A1CR_OFFSET + info->core_chipsel * 4);
754
755 /* Extended Wait is not valid and Select Strobe mode is not used */
756 val &= ~(ACR_ASIZE_MASK | ACR_EW_MASK | ACR_SS_MASK);
757 if (info->chip.options & NAND_BUSWIDTH_16)
758 val |= 0x1;
759
760 davinci_nand_writel(info, A1CR_OFFSET + info->core_chipsel * 4, val);
761
762 ret = 0;
763 if (info->timing)
764 ret = davinci_aemif_setup_timing(info->timing, info->base,
765 info->core_chipsel);
766 if (ret < 0) {
767 dev_dbg(&pdev->dev, "NAND timing values setup fail\n");
768 goto err;
769 }
770
771 spin_lock_irq(&davinci_nand_lock); 749 spin_lock_irq(&davinci_nand_lock);
772 750
773 /* put CSxNAND into NAND mode */ 751 /* put CSxNAND into NAND mode */