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-rw-r--r--drivers/net/bonding/bond_3ad.c8
-rw-r--r--drivers/net/bonding/bond_alb.c16
-rw-r--r--drivers/net/bonding/bond_main.c96
-rw-r--r--drivers/net/bonding/bonding.h1
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x.h4
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c1
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h2
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c217
-rw-r--r--drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h3
-rw-r--r--drivers/net/ethernet/emulex/benet/be_cmds.c400
-rw-r--r--drivers/net/ethernet/emulex/benet/be_main.c28
-rw-r--r--drivers/net/ethernet/i825xx/Kconfig2
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic.h4
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c45
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h2
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c2
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c50
-rw-r--r--drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c48
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/common.h8
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/descs.h31
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/norm_desc.c38
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c8
-rw-r--r--drivers/net/ethernet/stmicro/stmmac/stmmac_main.c13
23 files changed, 539 insertions, 488 deletions
diff --git a/drivers/net/bonding/bond_3ad.c b/drivers/net/bonding/bond_3ad.c
index b33c099d65a4..0ae0d7c54ccf 100644
--- a/drivers/net/bonding/bond_3ad.c
+++ b/drivers/net/bonding/bond_3ad.c
@@ -2110,9 +2110,6 @@ void bond_3ad_state_machine_handler(struct work_struct *work)
2110 2110
2111 read_lock(&bond->lock); 2111 read_lock(&bond->lock);
2112 2112
2113 if (bond->kill_timers)
2114 goto out;
2115
2116 //check if there are any slaves 2113 //check if there are any slaves
2117 if (bond->slave_cnt == 0) 2114 if (bond->slave_cnt == 0)
2118 goto re_arm; 2115 goto re_arm;
@@ -2161,9 +2158,8 @@ void bond_3ad_state_machine_handler(struct work_struct *work)
2161 } 2158 }
2162 2159
2163re_arm: 2160re_arm:
2164 if (!bond->kill_timers) 2161 queue_delayed_work(bond->wq, &bond->ad_work, ad_delta_in_ticks);
2165 queue_delayed_work(bond->wq, &bond->ad_work, ad_delta_in_ticks); 2162
2166out:
2167 read_unlock(&bond->lock); 2163 read_unlock(&bond->lock);
2168} 2164}
2169 2165
diff --git a/drivers/net/bonding/bond_alb.c b/drivers/net/bonding/bond_alb.c
index d4fbd2e62616..106b88a04738 100644
--- a/drivers/net/bonding/bond_alb.c
+++ b/drivers/net/bonding/bond_alb.c
@@ -1343,10 +1343,6 @@ void bond_alb_monitor(struct work_struct *work)
1343 1343
1344 read_lock(&bond->lock); 1344 read_lock(&bond->lock);
1345 1345
1346 if (bond->kill_timers) {
1347 goto out;
1348 }
1349
1350 if (bond->slave_cnt == 0) { 1346 if (bond->slave_cnt == 0) {
1351 bond_info->tx_rebalance_counter = 0; 1347 bond_info->tx_rebalance_counter = 0;
1352 bond_info->lp_counter = 0; 1348 bond_info->lp_counter = 0;
@@ -1401,10 +1397,13 @@ void bond_alb_monitor(struct work_struct *work)
1401 1397
1402 /* 1398 /*
1403 * dev_set_promiscuity requires rtnl and 1399 * dev_set_promiscuity requires rtnl and
1404 * nothing else. 1400 * nothing else. Avoid race with bond_close.
1405 */ 1401 */
1406 read_unlock(&bond->lock); 1402 read_unlock(&bond->lock);
1407 rtnl_lock(); 1403 if (!rtnl_trylock()) {
1404 read_lock(&bond->lock);
1405 goto re_arm;
1406 }
1408 1407
1409 bond_info->rlb_promisc_timeout_counter = 0; 1408 bond_info->rlb_promisc_timeout_counter = 0;
1410 1409
@@ -1440,9 +1439,8 @@ void bond_alb_monitor(struct work_struct *work)
1440 } 1439 }
1441 1440
1442re_arm: 1441re_arm:
1443 if (!bond->kill_timers) 1442 queue_delayed_work(bond->wq, &bond->alb_work, alb_delta_in_ticks);
1444 queue_delayed_work(bond->wq, &bond->alb_work, alb_delta_in_ticks); 1443
1445out:
1446 read_unlock(&bond->lock); 1444 read_unlock(&bond->lock);
1447} 1445}
1448 1446
diff --git a/drivers/net/bonding/bond_main.c b/drivers/net/bonding/bond_main.c
index c5944f1a4f9d..c34cc1e7c6f6 100644
--- a/drivers/net/bonding/bond_main.c
+++ b/drivers/net/bonding/bond_main.c
@@ -773,9 +773,6 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
773 773
774 read_lock(&bond->lock); 774 read_lock(&bond->lock);
775 775
776 if (bond->kill_timers)
777 goto out;
778
779 /* rejoin all groups on bond device */ 776 /* rejoin all groups on bond device */
780 __bond_resend_igmp_join_requests(bond->dev); 777 __bond_resend_igmp_join_requests(bond->dev);
781 778
@@ -789,9 +786,9 @@ static void bond_resend_igmp_join_requests(struct bonding *bond)
789 __bond_resend_igmp_join_requests(vlan_dev); 786 __bond_resend_igmp_join_requests(vlan_dev);
790 } 787 }
791 788
792 if ((--bond->igmp_retrans > 0) && !bond->kill_timers) 789 if (--bond->igmp_retrans > 0)
793 queue_delayed_work(bond->wq, &bond->mcast_work, HZ/5); 790 queue_delayed_work(bond->wq, &bond->mcast_work, HZ/5);
794out: 791
795 read_unlock(&bond->lock); 792 read_unlock(&bond->lock);
796} 793}
797 794
@@ -2517,10 +2514,11 @@ void bond_mii_monitor(struct work_struct *work)
2517 struct bonding *bond = container_of(work, struct bonding, 2514 struct bonding *bond = container_of(work, struct bonding,
2518 mii_work.work); 2515 mii_work.work);
2519 bool should_notify_peers = false; 2516 bool should_notify_peers = false;
2517 unsigned long delay;
2520 2518
2521 read_lock(&bond->lock); 2519 read_lock(&bond->lock);
2522 if (bond->kill_timers) 2520
2523 goto out; 2521 delay = msecs_to_jiffies(bond->params.miimon);
2524 2522
2525 if (bond->slave_cnt == 0) 2523 if (bond->slave_cnt == 0)
2526 goto re_arm; 2524 goto re_arm;
@@ -2529,7 +2527,15 @@ void bond_mii_monitor(struct work_struct *work)
2529 2527
2530 if (bond_miimon_inspect(bond)) { 2528 if (bond_miimon_inspect(bond)) {
2531 read_unlock(&bond->lock); 2529 read_unlock(&bond->lock);
2532 rtnl_lock(); 2530
2531 /* Race avoidance with bond_close cancel of workqueue */
2532 if (!rtnl_trylock()) {
2533 read_lock(&bond->lock);
2534 delay = 1;
2535 should_notify_peers = false;
2536 goto re_arm;
2537 }
2538
2533 read_lock(&bond->lock); 2539 read_lock(&bond->lock);
2534 2540
2535 bond_miimon_commit(bond); 2541 bond_miimon_commit(bond);
@@ -2540,14 +2546,18 @@ void bond_mii_monitor(struct work_struct *work)
2540 } 2546 }
2541 2547
2542re_arm: 2548re_arm:
2543 if (bond->params.miimon && !bond->kill_timers) 2549 if (bond->params.miimon)
2544 queue_delayed_work(bond->wq, &bond->mii_work, 2550 queue_delayed_work(bond->wq, &bond->mii_work, delay);
2545 msecs_to_jiffies(bond->params.miimon)); 2551
2546out:
2547 read_unlock(&bond->lock); 2552 read_unlock(&bond->lock);
2548 2553
2549 if (should_notify_peers) { 2554 if (should_notify_peers) {
2550 rtnl_lock(); 2555 if (!rtnl_trylock()) {
2556 read_lock(&bond->lock);
2557 bond->send_peer_notif++;
2558 read_unlock(&bond->lock);
2559 return;
2560 }
2551 netdev_bonding_change(bond->dev, NETDEV_NOTIFY_PEERS); 2561 netdev_bonding_change(bond->dev, NETDEV_NOTIFY_PEERS);
2552 rtnl_unlock(); 2562 rtnl_unlock();
2553 } 2563 }
@@ -2789,9 +2799,6 @@ void bond_loadbalance_arp_mon(struct work_struct *work)
2789 2799
2790 delta_in_ticks = msecs_to_jiffies(bond->params.arp_interval); 2800 delta_in_ticks = msecs_to_jiffies(bond->params.arp_interval);
2791 2801
2792 if (bond->kill_timers)
2793 goto out;
2794
2795 if (bond->slave_cnt == 0) 2802 if (bond->slave_cnt == 0)
2796 goto re_arm; 2803 goto re_arm;
2797 2804
@@ -2888,9 +2895,9 @@ void bond_loadbalance_arp_mon(struct work_struct *work)
2888 } 2895 }
2889 2896
2890re_arm: 2897re_arm:
2891 if (bond->params.arp_interval && !bond->kill_timers) 2898 if (bond->params.arp_interval)
2892 queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks); 2899 queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks);
2893out: 2900
2894 read_unlock(&bond->lock); 2901 read_unlock(&bond->lock);
2895} 2902}
2896 2903
@@ -3131,9 +3138,6 @@ void bond_activebackup_arp_mon(struct work_struct *work)
3131 3138
3132 read_lock(&bond->lock); 3139 read_lock(&bond->lock);
3133 3140
3134 if (bond->kill_timers)
3135 goto out;
3136
3137 delta_in_ticks = msecs_to_jiffies(bond->params.arp_interval); 3141 delta_in_ticks = msecs_to_jiffies(bond->params.arp_interval);
3138 3142
3139 if (bond->slave_cnt == 0) 3143 if (bond->slave_cnt == 0)
@@ -3143,7 +3147,15 @@ void bond_activebackup_arp_mon(struct work_struct *work)
3143 3147
3144 if (bond_ab_arp_inspect(bond, delta_in_ticks)) { 3148 if (bond_ab_arp_inspect(bond, delta_in_ticks)) {
3145 read_unlock(&bond->lock); 3149 read_unlock(&bond->lock);
3146 rtnl_lock(); 3150
3151 /* Race avoidance with bond_close flush of workqueue */
3152 if (!rtnl_trylock()) {
3153 read_lock(&bond->lock);
3154 delta_in_ticks = 1;
3155 should_notify_peers = false;
3156 goto re_arm;
3157 }
3158
3147 read_lock(&bond->lock); 3159 read_lock(&bond->lock);
3148 3160
3149 bond_ab_arp_commit(bond, delta_in_ticks); 3161 bond_ab_arp_commit(bond, delta_in_ticks);
@@ -3156,13 +3168,18 @@ void bond_activebackup_arp_mon(struct work_struct *work)
3156 bond_ab_arp_probe(bond); 3168 bond_ab_arp_probe(bond);
3157 3169
3158re_arm: 3170re_arm:
3159 if (bond->params.arp_interval && !bond->kill_timers) 3171 if (bond->params.arp_interval)
3160 queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks); 3172 queue_delayed_work(bond->wq, &bond->arp_work, delta_in_ticks);
3161out: 3173
3162 read_unlock(&bond->lock); 3174 read_unlock(&bond->lock);
3163 3175
3164 if (should_notify_peers) { 3176 if (should_notify_peers) {
3165 rtnl_lock(); 3177 if (!rtnl_trylock()) {
3178 read_lock(&bond->lock);
3179 bond->send_peer_notif++;
3180 read_unlock(&bond->lock);
3181 return;
3182 }
3166 netdev_bonding_change(bond->dev, NETDEV_NOTIFY_PEERS); 3183 netdev_bonding_change(bond->dev, NETDEV_NOTIFY_PEERS);
3167 rtnl_unlock(); 3184 rtnl_unlock();
3168 } 3185 }
@@ -3424,8 +3441,6 @@ static int bond_open(struct net_device *bond_dev)
3424 struct slave *slave; 3441 struct slave *slave;
3425 int i; 3442 int i;
3426 3443
3427 bond->kill_timers = 0;
3428
3429 /* reset slave->backup and slave->inactive */ 3444 /* reset slave->backup and slave->inactive */
3430 read_lock(&bond->lock); 3445 read_lock(&bond->lock);
3431 if (bond->slave_cnt > 0) { 3446 if (bond->slave_cnt > 0) {
@@ -3494,33 +3509,30 @@ static int bond_close(struct net_device *bond_dev)
3494 3509
3495 bond->send_peer_notif = 0; 3510 bond->send_peer_notif = 0;
3496 3511
3497 /* signal timers not to re-arm */
3498 bond->kill_timers = 1;
3499
3500 write_unlock_bh(&bond->lock); 3512 write_unlock_bh(&bond->lock);
3501 3513
3502 if (bond->params.miimon) { /* link check interval, in milliseconds. */ 3514 if (bond->params.miimon) { /* link check interval, in milliseconds. */
3503 cancel_delayed_work(&bond->mii_work); 3515 cancel_delayed_work_sync(&bond->mii_work);
3504 } 3516 }
3505 3517
3506 if (bond->params.arp_interval) { /* arp interval, in milliseconds. */ 3518 if (bond->params.arp_interval) { /* arp interval, in milliseconds. */
3507 cancel_delayed_work(&bond->arp_work); 3519 cancel_delayed_work_sync(&bond->arp_work);
3508 } 3520 }
3509 3521
3510 switch (bond->params.mode) { 3522 switch (bond->params.mode) {
3511 case BOND_MODE_8023AD: 3523 case BOND_MODE_8023AD:
3512 cancel_delayed_work(&bond->ad_work); 3524 cancel_delayed_work_sync(&bond->ad_work);
3513 break; 3525 break;
3514 case BOND_MODE_TLB: 3526 case BOND_MODE_TLB:
3515 case BOND_MODE_ALB: 3527 case BOND_MODE_ALB:
3516 cancel_delayed_work(&bond->alb_work); 3528 cancel_delayed_work_sync(&bond->alb_work);
3517 break; 3529 break;
3518 default: 3530 default:
3519 break; 3531 break;
3520 } 3532 }
3521 3533
3522 if (delayed_work_pending(&bond->mcast_work)) 3534 if (delayed_work_pending(&bond->mcast_work))
3523 cancel_delayed_work(&bond->mcast_work); 3535 cancel_delayed_work_sync(&bond->mcast_work);
3524 3536
3525 if (bond_is_lb(bond)) { 3537 if (bond_is_lb(bond)) {
3526 /* Must be called only after all 3538 /* Must be called only after all
@@ -4367,26 +4379,22 @@ static void bond_setup(struct net_device *bond_dev)
4367 4379
4368static void bond_work_cancel_all(struct bonding *bond) 4380static void bond_work_cancel_all(struct bonding *bond)
4369{ 4381{
4370 write_lock_bh(&bond->lock);
4371 bond->kill_timers = 1;
4372 write_unlock_bh(&bond->lock);
4373
4374 if (bond->params.miimon && delayed_work_pending(&bond->mii_work)) 4382 if (bond->params.miimon && delayed_work_pending(&bond->mii_work))
4375 cancel_delayed_work(&bond->mii_work); 4383 cancel_delayed_work_sync(&bond->mii_work);
4376 4384
4377 if (bond->params.arp_interval && delayed_work_pending(&bond->arp_work)) 4385 if (bond->params.arp_interval && delayed_work_pending(&bond->arp_work))
4378 cancel_delayed_work(&bond->arp_work); 4386 cancel_delayed_work_sync(&bond->arp_work);
4379 4387
4380 if (bond->params.mode == BOND_MODE_ALB && 4388 if (bond->params.mode == BOND_MODE_ALB &&
4381 delayed_work_pending(&bond->alb_work)) 4389 delayed_work_pending(&bond->alb_work))
4382 cancel_delayed_work(&bond->alb_work); 4390 cancel_delayed_work_sync(&bond->alb_work);
4383 4391
4384 if (bond->params.mode == BOND_MODE_8023AD && 4392 if (bond->params.mode == BOND_MODE_8023AD &&
4385 delayed_work_pending(&bond->ad_work)) 4393 delayed_work_pending(&bond->ad_work))
4386 cancel_delayed_work(&bond->ad_work); 4394 cancel_delayed_work_sync(&bond->ad_work);
4387 4395
4388 if (delayed_work_pending(&bond->mcast_work)) 4396 if (delayed_work_pending(&bond->mcast_work))
4389 cancel_delayed_work(&bond->mcast_work); 4397 cancel_delayed_work_sync(&bond->mcast_work);
4390} 4398}
4391 4399
4392/* 4400/*
diff --git a/drivers/net/bonding/bonding.h b/drivers/net/bonding/bonding.h
index 82fec5fc75d7..1aecc37e5b4d 100644
--- a/drivers/net/bonding/bonding.h
+++ b/drivers/net/bonding/bonding.h
@@ -222,7 +222,6 @@ struct bonding {
222 struct slave *); 222 struct slave *);
223 rwlock_t lock; 223 rwlock_t lock;
224 rwlock_t curr_slave_lock; 224 rwlock_t curr_slave_lock;
225 s8 kill_timers;
226 u8 send_peer_notif; 225 u8 send_peer_notif;
227 s8 setup_by_slave; 226 s8 setup_by_slave;
228 s8 igmp_retrans; 227 s8 igmp_retrans;
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
index 627a5807836d..aec7212ac983 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x.h
@@ -23,8 +23,8 @@
23 * (you will need to reboot afterwards) */ 23 * (you will need to reboot afterwards) */
24/* #define BNX2X_STOP_ON_ERROR */ 24/* #define BNX2X_STOP_ON_ERROR */
25 25
26#define DRV_MODULE_VERSION "1.70.00-0" 26#define DRV_MODULE_VERSION "1.70.30-0"
27#define DRV_MODULE_RELDATE "2011/06/13" 27#define DRV_MODULE_RELDATE "2011/10/25"
28#define BNX2X_BC_VER 0x040200 28#define BNX2X_BC_VER 0x040200
29 29
30#if defined(CONFIG_DCB) 30#if defined(CONFIG_DCB)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
index 1a6e37ce730c..f0ca8b27a55e 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_ethtool.c
@@ -329,6 +329,7 @@ static int bnx2x_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
329 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 329 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
330 break; 330 break;
331 case PORT_FIBRE: 331 case PORT_FIBRE:
332 case PORT_DA:
332 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE) 333 if (bp->port.supported[cfg_idx] & SUPPORTED_FIBRE)
333 break; /* no port change */ 334 break; /* no port change */
334 335
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
index e44b858ff12f..fc754cb6cc0f 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_hsi.h
@@ -2550,7 +2550,7 @@ struct host_func_stats {
2550 2550
2551#define BCM_5710_FW_MAJOR_VERSION 7 2551#define BCM_5710_FW_MAJOR_VERSION 7
2552#define BCM_5710_FW_MINOR_VERSION 0 2552#define BCM_5710_FW_MINOR_VERSION 0
2553#define BCM_5710_FW_REVISION_VERSION 23 2553#define BCM_5710_FW_REVISION_VERSION 29
2554#define BCM_5710_FW_ENGINEERING_VERSION 0 2554#define BCM_5710_FW_ENGINEERING_VERSION 0
2555#define BCM_5710_FW_COMPILE_FLAGS 1 2555#define BCM_5710_FW_COMPILE_FLAGS 1
2556 2556
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
index 818723c9e678..bce203fa4b9e 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.c
@@ -45,6 +45,9 @@
45#define MCPR_IMC_COMMAND_READ_OP 1 45#define MCPR_IMC_COMMAND_READ_OP 1
46#define MCPR_IMC_COMMAND_WRITE_OP 2 46#define MCPR_IMC_COMMAND_WRITE_OP 2
47 47
48/* LED Blink rate that will achieve ~15.9Hz */
49#define LED_BLINK_RATE_VAL_E3 354
50#define LED_BLINK_RATE_VAL_E1X_E2 480
48/***********************************************************/ 51/***********************************************************/
49/* Shortcut definitions */ 52/* Shortcut definitions */
50/***********************************************************/ 53/***********************************************************/
@@ -258,6 +261,7 @@
258 261
259#define MAX_PACKET_SIZE (9700) 262#define MAX_PACKET_SIZE (9700)
260#define WC_UC_TIMEOUT 100 263#define WC_UC_TIMEOUT 100
264#define MAX_KR_LINK_RETRY 4
261 265
262/**********************************************************/ 266/**********************************************************/
263/* INTERFACE */ 267/* INTERFACE */
@@ -1490,6 +1494,18 @@ static void bnx2x_set_xumac_nig(struct link_params *params,
1490 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 1494 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
1491} 1495}
1492 1496
1497static void bnx2x_umac_disable(struct link_params *params)
1498{
1499 u32 umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
1500 struct bnx2x *bp = params->bp;
1501 if (!(REG_RD(bp, MISC_REG_RESET_REG_2) &
1502 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
1503 return;
1504
1505 /* Disable RX and TX */
1506 REG_WR(bp, umac_base + UMAC_REG_COMMAND_CONFIG, 0);
1507}
1508
1493static void bnx2x_umac_enable(struct link_params *params, 1509static void bnx2x_umac_enable(struct link_params *params,
1494 struct link_vars *vars, u8 lb) 1510 struct link_vars *vars, u8 lb)
1495{ 1511{
@@ -1599,8 +1615,9 @@ static u8 bnx2x_is_4_port_mode(struct bnx2x *bp)
1599} 1615}
1600 1616
1601/* Define the XMAC mode */ 1617/* Define the XMAC mode */
1602static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed) 1618static void bnx2x_xmac_init(struct link_params *params, u32 max_speed)
1603{ 1619{
1620 struct bnx2x *bp = params->bp;
1604 u32 is_port4mode = bnx2x_is_4_port_mode(bp); 1621 u32 is_port4mode = bnx2x_is_4_port_mode(bp);
1605 1622
1606 /** 1623 /**
@@ -1610,7 +1627,8 @@ static void bnx2x_xmac_init(struct bnx2x *bp, u32 max_speed)
1610 * ports of the path 1627 * ports of the path
1611 **/ 1628 **/
1612 1629
1613 if (is_port4mode && (REG_RD(bp, MISC_REG_RESET_REG_2) & 1630 if ((CHIP_NUM(bp) == CHIP_NUM_57840) &&
1631 (REG_RD(bp, MISC_REG_RESET_REG_2) &
1614 MISC_REGISTERS_RESET_REG_2_XMAC)) { 1632 MISC_REGISTERS_RESET_REG_2_XMAC)) {
1615 DP(NETIF_MSG_LINK, 1633 DP(NETIF_MSG_LINK,
1616 "XMAC already out of reset in 4-port mode\n"); 1634 "XMAC already out of reset in 4-port mode\n");
@@ -1677,10 +1695,6 @@ static void bnx2x_xmac_disable(struct link_params *params)
1677 (pfc_ctrl | (1<<1))); 1695 (pfc_ctrl | (1<<1)));
1678 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port); 1696 DP(NETIF_MSG_LINK, "Disable XMAC on port %x\n", port);
1679 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0); 1697 REG_WR(bp, xmac_base + XMAC_REG_CTRL, 0);
1680 usleep_range(1000, 1000);
1681 bnx2x_set_xumac_nig(params, 0, 0);
1682 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
1683 XMAC_CTRL_REG_SOFT_RESET);
1684 } 1698 }
1685} 1699}
1686 1700
@@ -1693,7 +1707,7 @@ static int bnx2x_xmac_enable(struct link_params *params,
1693 1707
1694 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 1708 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
1695 1709
1696 bnx2x_xmac_init(bp, vars->line_speed); 1710 bnx2x_xmac_init(params, vars->line_speed);
1697 1711
1698 /* 1712 /*
1699 * This register determines on which events the MAC will assert 1713 * This register determines on which events the MAC will assert
@@ -3575,6 +3589,11 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3575 u16 val16 = 0, lane, bam37 = 0; 3589 u16 val16 = 0, lane, bam37 = 0;
3576 struct bnx2x *bp = params->bp; 3590 struct bnx2x *bp = params->bp;
3577 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n"); 3591 DP(NETIF_MSG_LINK, "Enable Auto Negotiation for KR\n");
3592
3593 /* Disable Autoneg: re-enable it after adv is done. */
3594 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3595 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0);
3596
3578 /* Check adding advertisement for 1G KX */ 3597 /* Check adding advertisement for 1G KX */
3579 if (((vars->line_speed == SPEED_AUTO_NEG) && 3598 if (((vars->line_speed == SPEED_AUTO_NEG) &&
3580 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 3599 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
@@ -3616,9 +3635,6 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3616 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3635 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3617 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 3636 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
3618 0x03f0); 3637 0x03f0);
3619 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3620 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
3621 0x383f);
3622 3638
3623 /* Advertised speeds */ 3639 /* Advertised speeds */
3624 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD, 3640 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
@@ -3645,19 +3661,22 @@ static void bnx2x_warpcore_enable_AN_KR(struct bnx2x_phy *phy,
3645 /* Advertise pause */ 3661 /* Advertise pause */
3646 bnx2x_ext_phy_set_pause(params, phy, vars); 3662 bnx2x_ext_phy_set_pause(params, phy, vars);
3647 3663
3648 /* Enable Autoneg */ 3664 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
3649 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3650 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3651
3652 /* Over 1G - AN local device user page 1 */
3653 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3654 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3655 3665
3656 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 3666 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD,
3657 MDIO_WC_REG_DIGITAL5_MISC7, &val16); 3667 MDIO_WC_REG_DIGITAL5_MISC7, &val16);
3658 3668
3659 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD, 3669 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3660 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100); 3670 MDIO_WC_REG_DIGITAL5_MISC7, val16 | 0x100);
3671
3672 /* Over 1G - AN local device user page 1 */
3673 bnx2x_cl45_write(bp, phy, MDIO_WC_DEVAD,
3674 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
3675
3676 /* Enable Autoneg */
3677 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
3678 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1000);
3679
3661} 3680}
3662 3681
3663static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy, 3682static void bnx2x_warpcore_set_10G_KR(struct bnx2x_phy *phy,
@@ -4126,6 +4145,85 @@ static int bnx2x_is_sfp_module_plugged(struct bnx2x_phy *phy,
4126 else 4145 else
4127 return 0; 4146 return 0;
4128} 4147}
4148static int bnx2x_warpcore_get_sigdet(struct bnx2x_phy *phy,
4149 struct link_params *params)
4150{
4151 u16 gp2_status_reg0, lane;
4152 struct bnx2x *bp = params->bp;
4153
4154 lane = bnx2x_get_warpcore_lane(phy, params);
4155
4156 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
4157 &gp2_status_reg0);
4158
4159 return (gp2_status_reg0 >> (8+lane)) & 0x1;
4160}
4161
4162static void bnx2x_warpcore_config_runtime(struct bnx2x_phy *phy,
4163 struct link_params *params,
4164 struct link_vars *vars)
4165{
4166 struct bnx2x *bp = params->bp;
4167 u32 serdes_net_if;
4168 u16 gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
4169 u16 lane = bnx2x_get_warpcore_lane(phy, params);
4170
4171 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
4172
4173 if (!vars->turn_to_run_wc_rt)
4174 return;
4175
4176 /* return if there is no link partner */
4177 if (!(bnx2x_warpcore_get_sigdet(phy, params))) {
4178 DP(NETIF_MSG_LINK, "bnx2x_warpcore_get_sigdet false\n");
4179 return;
4180 }
4181
4182 if (vars->rx_tx_asic_rst) {
4183 serdes_net_if = (REG_RD(bp, params->shmem_base +
4184 offsetof(struct shmem_region, dev_info.
4185 port_hw_config[params->port].default_cfg)) &
4186 PORT_HW_CFG_NET_SERDES_IF_MASK);
4187
4188 switch (serdes_net_if) {
4189 case PORT_HW_CFG_NET_SERDES_IF_KR:
4190 /* Do we get link yet? */
4191 bnx2x_cl45_read(bp, phy, MDIO_WC_DEVAD, 0x81d1,
4192 &gp_status1);
4193 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
4194 /*10G KR*/
4195 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
4196
4197 DP(NETIF_MSG_LINK,
4198 "gp_status1 0x%x\n", gp_status1);
4199
4200 if (lnkup_kr || lnkup) {
4201 vars->rx_tx_asic_rst = 0;
4202 DP(NETIF_MSG_LINK,
4203 "link up, rx_tx_asic_rst 0x%x\n",
4204 vars->rx_tx_asic_rst);
4205 } else {
4206 /*reset the lane to see if link comes up.*/
4207 bnx2x_warpcore_reset_lane(bp, phy, 1);
4208 bnx2x_warpcore_reset_lane(bp, phy, 0);
4209
4210 /* restart Autoneg */
4211 bnx2x_cl45_write(bp, phy, MDIO_AN_DEVAD,
4212 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4213
4214 vars->rx_tx_asic_rst--;
4215 DP(NETIF_MSG_LINK, "0x%x retry left\n",
4216 vars->rx_tx_asic_rst);
4217 }
4218 break;
4219
4220 default:
4221 break;
4222 }
4223
4224 } /*params->rx_tx_asic_rst*/
4225
4226}
4129 4227
4130static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy, 4228static void bnx2x_warpcore_config_init(struct bnx2x_phy *phy,
4131 struct link_params *params, 4229 struct link_params *params,
@@ -5896,7 +5994,13 @@ int bnx2x_set_led(struct link_params *params,
5896 SHARED_HW_CFG_LED_MAC1); 5994 SHARED_HW_CFG_LED_MAC1);
5897 5995
5898 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 5996 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
5899 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp | EMAC_LED_OVERRIDE)); 5997 if (params->phy[EXT_PHY1].type ==
5998 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
5999 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp & 0xfff1);
6000 else {
6001 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6002 (tmp | EMAC_LED_OVERRIDE));
6003 }
5900 break; 6004 break;
5901 6005
5902 case LED_MODE_OPER: 6006 case LED_MODE_OPER:
@@ -5949,17 +6053,33 @@ int bnx2x_set_led(struct link_params *params,
5949 else 6053 else
5950 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 6054 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
5951 hw_led_mode); 6055 hw_led_mode);
6056 } else if ((params->phy[EXT_PHY1].type ==
6057 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6058 (mode != LED_MODE_OPER)) {
6059 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, 0);
6060 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6061 EMAC_WR(bp, EMAC_REG_EMAC_LED, tmp | 0x3);
5952 } else 6062 } else
5953 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4, hw_led_mode); 6063 REG_WR(bp, NIG_REG_LED_MODE_P0 + port*4,
6064 hw_led_mode);
5954 6065
5955 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 6066 REG_WR(bp, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
5956 /* Set blinking rate to ~15.9Hz */ 6067 /* Set blinking rate to ~15.9Hz */
5957 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 6068 if (CHIP_IS_E3(bp))
5958 LED_BLINK_RATE_VAL); 6069 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6070 LED_BLINK_RATE_VAL_E3);
6071 else
6072 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
6073 LED_BLINK_RATE_VAL_E1X_E2);
5959 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 6074 REG_WR(bp, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
5960 port*4, 1); 6075 port*4, 1);
5961 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED); 6076 if ((params->phy[EXT_PHY1].type !=
5962 EMAC_WR(bp, EMAC_REG_EMAC_LED, (tmp & (~EMAC_LED_OVERRIDE))); 6077 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
6078 (mode != LED_MODE_OPER)) {
6079 tmp = EMAC_RD(bp, EMAC_REG_EMAC_LED);
6080 EMAC_WR(bp, EMAC_REG_EMAC_LED,
6081 (tmp & (~EMAC_LED_OVERRIDE)));
6082 }
5963 6083
5964 if (CHIP_IS_E1(bp) && 6084 if (CHIP_IS_E1(bp) &&
5965 ((speed == SPEED_2500) || 6085 ((speed == SPEED_2500) ||
@@ -6218,8 +6338,10 @@ static int bnx2x_update_link_down(struct link_params *params,
6218 MISC_REGISTERS_RESET_REG_2_CLEAR, 6338 MISC_REGISTERS_RESET_REG_2_CLEAR,
6219 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 6339 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
6220 } 6340 }
6221 if (CHIP_IS_E3(bp)) 6341 if (CHIP_IS_E3(bp)) {
6222 bnx2x_xmac_disable(params); 6342 bnx2x_xmac_disable(params);
6343 bnx2x_umac_disable(params);
6344 }
6223 6345
6224 return 0; 6346 return 0;
6225} 6347}
@@ -10205,22 +10327,6 @@ static int bnx2x_54618se_config_init(struct bnx2x_phy *phy,
10205 return 0; 10327 return 0;
10206} 10328}
10207 10329
10208static void bnx2x_54618se_set_link_led(struct bnx2x_phy *phy,
10209 struct link_params *params, u8 mode)
10210{
10211 struct bnx2x *bp = params->bp;
10212 DP(NETIF_MSG_LINK, "54618SE set link led (mode=%x)\n", mode);
10213 switch (mode) {
10214 case LED_MODE_FRONT_PANEL_OFF:
10215 case LED_MODE_OFF:
10216 case LED_MODE_OPER:
10217 case LED_MODE_ON:
10218 default:
10219 break;
10220 }
10221 return;
10222}
10223
10224static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy, 10330static void bnx2x_54618se_link_reset(struct bnx2x_phy *phy,
10225 struct link_params *params) 10331 struct link_params *params)
10226{ 10332{
@@ -10997,7 +11103,7 @@ static struct bnx2x_phy phy_54618se = {
10997 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback, 11103 .config_loopback = (config_loopback_t)bnx2x_54618se_config_loopback,
10998 .format_fw_ver = (format_fw_ver_t)NULL, 11104 .format_fw_ver = (format_fw_ver_t)NULL,
10999 .hw_reset = (hw_reset_t)NULL, 11105 .hw_reset = (hw_reset_t)NULL,
11000 .set_link_led = (set_link_led_t)bnx2x_54618se_set_link_led, 11106 .set_link_led = (set_link_led_t)NULL,
11001 .phy_specific_func = (phy_specific_func_t)NULL 11107 .phy_specific_func = (phy_specific_func_t)NULL
11002}; 11108};
11003/*****************************************************************/ 11109/*****************************************************************/
@@ -11718,8 +11824,10 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11718 /* Stop BigMac rx */ 11824 /* Stop BigMac rx */
11719 if (!CHIP_IS_E3(bp)) 11825 if (!CHIP_IS_E3(bp))
11720 bnx2x_bmac_rx_disable(bp, port); 11826 bnx2x_bmac_rx_disable(bp, port);
11721 else 11827 else {
11722 bnx2x_xmac_disable(params); 11828 bnx2x_xmac_disable(params);
11829 bnx2x_umac_disable(params);
11830 }
11723 /* disable emac */ 11831 /* disable emac */
11724 if (!CHIP_IS_E3(bp)) 11832 if (!CHIP_IS_E3(bp))
11725 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0); 11833 REG_WR(bp, NIG_REG_NIG_EMAC0_EN + port*4, 0);
@@ -11757,14 +11865,21 @@ int bnx2x_link_reset(struct link_params *params, struct link_vars *vars,
11757 if (params->phy[INT_PHY].link_reset) 11865 if (params->phy[INT_PHY].link_reset)
11758 params->phy[INT_PHY].link_reset( 11866 params->phy[INT_PHY].link_reset(
11759 &params->phy[INT_PHY], params); 11867 &params->phy[INT_PHY], params);
11760 /* reset BigMac */
11761 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11762 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11763 11868
11764 /* disable nig ingress interface */ 11869 /* disable nig ingress interface */
11765 if (!CHIP_IS_E3(bp)) { 11870 if (!CHIP_IS_E3(bp)) {
11871 /* reset BigMac */
11872 REG_WR(bp, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
11873 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
11766 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0); 11874 REG_WR(bp, NIG_REG_BMAC0_IN_EN + port*4, 0);
11767 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0); 11875 REG_WR(bp, NIG_REG_EMAC0_IN_EN + port*4, 0);
11876 } else {
11877 u32 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
11878 bnx2x_set_xumac_nig(params, 0, 0);
11879 if (REG_RD(bp, MISC_REG_RESET_REG_2) &
11880 MISC_REGISTERS_RESET_REG_2_XMAC)
11881 REG_WR(bp, xmac_base + XMAC_REG_CTRL,
11882 XMAC_CTRL_REG_SOFT_RESET);
11768 } 11883 }
11769 vars->link_up = 0; 11884 vars->link_up = 0;
11770 vars->phy_flags = 0; 11885 vars->phy_flags = 0;
@@ -12332,11 +12447,6 @@ void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12332{ 12447{
12333 struct bnx2x *bp = params->bp; 12448 struct bnx2x *bp = params->bp;
12334 u16 phy_idx; 12449 u16 phy_idx;
12335 if (!params) {
12336 DP(NETIF_MSG_LINK, "Uninitialized params !\n");
12337 return;
12338 }
12339
12340 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) { 12450 for (phy_idx = INT_PHY; phy_idx < MAX_PHYS; phy_idx++) {
12341 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) { 12451 if (params->phy[phy_idx].flags & FLAGS_TX_ERROR_CHECK) {
12342 bnx2x_set_aer_mmd(params, &params->phy[phy_idx]); 12452 bnx2x_set_aer_mmd(params, &params->phy[phy_idx]);
@@ -12345,8 +12455,13 @@ void bnx2x_period_func(struct link_params *params, struct link_vars *vars)
12345 } 12455 }
12346 } 12456 }
12347 12457
12348 if (CHIP_IS_E3(bp)) 12458 if (CHIP_IS_E3(bp)) {
12459 struct bnx2x_phy *phy = &params->phy[INT_PHY];
12460 bnx2x_set_aer_mmd(params, phy);
12349 bnx2x_check_over_curr(params, vars); 12461 bnx2x_check_over_curr(params, vars);
12462 bnx2x_warpcore_config_runtime(phy, params, vars);
12463 }
12464
12350} 12465}
12351 12466
12352u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base) 12467u8 bnx2x_hw_lock_required(struct bnx2x *bp, u32 shmem_base, u32 shmem2_base)
diff --git a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h
index c12db6da213e..2a46e633abe9 100644
--- a/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h
+++ b/drivers/net/ethernet/broadcom/bnx2x/bnx2x_link.h
@@ -303,6 +303,9 @@ struct link_vars {
303#define PERIODIC_FLAGS_LINK_EVENT 0x0001 303#define PERIODIC_FLAGS_LINK_EVENT 0x0001
304 304
305 u32 aeu_int_mask; 305 u32 aeu_int_mask;
306 u8 rx_tx_asic_rst;
307 u8 turn_to_run_wc_rt;
308 u16 rsrv2;
306}; 309};
307 310
308/***********************************************************/ 311/***********************************************************/
diff --git a/drivers/net/ethernet/emulex/benet/be_cmds.c b/drivers/net/ethernet/emulex/benet/be_cmds.c
index e0ff96193c49..824b8e6021f6 100644
--- a/drivers/net/ethernet/emulex/benet/be_cmds.c
+++ b/drivers/net/ethernet/emulex/benet/be_cmds.c
@@ -428,28 +428,33 @@ static inline struct be_sge *nonembedded_sgl(struct be_mcc_wrb *wrb)
428 return &wrb->payload.sgl[0]; 428 return &wrb->payload.sgl[0];
429} 429}
430 430
431/* Don't touch the hdr after it's prepared */
432static void be_wrb_hdr_prepare(struct be_mcc_wrb *wrb, int payload_len,
433 bool embedded, u8 sge_cnt, u32 opcode)
434{
435 if (embedded)
436 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
437 else
438 wrb->embedded |= (sge_cnt & MCC_WRB_SGE_CNT_MASK) <<
439 MCC_WRB_SGE_CNT_SHIFT;
440 wrb->payload_length = payload_len;
441 wrb->tag0 = opcode;
442 be_dws_cpu_to_le(wrb, 8);
443}
444 431
445/* Don't touch the hdr after it's prepared */ 432/* Don't touch the hdr after it's prepared */
446static void be_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr, 433/* mem will be NULL for embedded commands */
447 u8 subsystem, u8 opcode, int cmd_len) 434static void be_wrb_cmd_hdr_prepare(struct be_cmd_req_hdr *req_hdr,
435 u8 subsystem, u8 opcode, int cmd_len,
436 struct be_mcc_wrb *wrb, struct be_dma_mem *mem)
448{ 437{
438 struct be_sge *sge;
439
449 req_hdr->opcode = opcode; 440 req_hdr->opcode = opcode;
450 req_hdr->subsystem = subsystem; 441 req_hdr->subsystem = subsystem;
451 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr)); 442 req_hdr->request_length = cpu_to_le32(cmd_len - sizeof(*req_hdr));
452 req_hdr->version = 0; 443 req_hdr->version = 0;
444
445 wrb->tag0 = opcode;
446 wrb->tag1 = subsystem;
447 wrb->payload_length = cmd_len;
448 if (mem) {
449 wrb->embedded |= (1 & MCC_WRB_SGE_CNT_MASK) <<
450 MCC_WRB_SGE_CNT_SHIFT;
451 sge = nonembedded_sgl(wrb);
452 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
453 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
454 sge->len = cpu_to_le32(mem->size);
455 } else
456 wrb->embedded |= MCC_WRB_EMBEDDED_MASK;
457 be_dws_cpu_to_le(wrb, 8);
453} 458}
454 459
455static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages, 460static void be_cmd_page_addrs_prepare(struct phys_addr *pages, u32 max_pages,
@@ -586,10 +591,8 @@ int be_cmd_eq_create(struct be_adapter *adapter,
586 wrb = wrb_from_mbox(adapter); 591 wrb = wrb_from_mbox(adapter);
587 req = embedded_payload(wrb); 592 req = embedded_payload(wrb);
588 593
589 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_COMMON_EQ_CREATE); 594 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
590 595 OPCODE_COMMON_EQ_CREATE, sizeof(*req), wrb, NULL);
591 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
592 OPCODE_COMMON_EQ_CREATE, sizeof(*req));
593 596
594 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 597 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
595 598
@@ -632,12 +635,8 @@ int be_cmd_mac_addr_query(struct be_adapter *adapter, u8 *mac_addr,
632 } 635 }
633 req = embedded_payload(wrb); 636 req = embedded_payload(wrb);
634 637
635 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 638 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
636 OPCODE_COMMON_NTWK_MAC_QUERY); 639 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req), wrb, NULL);
637
638 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
639 OPCODE_COMMON_NTWK_MAC_QUERY, sizeof(*req));
640
641 req->type = type; 640 req->type = type;
642 if (permanent) { 641 if (permanent) {
643 req->permanent = 1; 642 req->permanent = 1;
@@ -674,11 +673,8 @@ int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
674 } 673 }
675 req = embedded_payload(wrb); 674 req = embedded_payload(wrb);
676 675
677 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 676 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
678 OPCODE_COMMON_NTWK_PMAC_ADD); 677 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req), wrb, NULL);
679
680 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
681 OPCODE_COMMON_NTWK_PMAC_ADD, sizeof(*req));
682 678
683 req->hdr.domain = domain; 679 req->hdr.domain = domain;
684 req->if_id = cpu_to_le32(if_id); 680 req->if_id = cpu_to_le32(if_id);
@@ -692,6 +688,10 @@ int be_cmd_pmac_add(struct be_adapter *adapter, u8 *mac_addr,
692 688
693err: 689err:
694 spin_unlock_bh(&adapter->mcc_lock); 690 spin_unlock_bh(&adapter->mcc_lock);
691
692 if (status == MCC_STATUS_UNAUTHORIZED_REQUEST)
693 status = -EPERM;
694
695 return status; 695 return status;
696} 696}
697 697
@@ -711,11 +711,8 @@ int be_cmd_pmac_del(struct be_adapter *adapter, u32 if_id, u32 pmac_id, u32 dom)
711 } 711 }
712 req = embedded_payload(wrb); 712 req = embedded_payload(wrb);
713 713
714 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 714 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
715 OPCODE_COMMON_NTWK_PMAC_DEL); 715 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req), wrb, NULL);
716
717 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
718 OPCODE_COMMON_NTWK_PMAC_DEL, sizeof(*req));
719 716
720 req->hdr.domain = dom; 717 req->hdr.domain = dom;
721 req->if_id = cpu_to_le32(if_id); 718 req->if_id = cpu_to_le32(if_id);
@@ -746,11 +743,8 @@ int be_cmd_cq_create(struct be_adapter *adapter,
746 req = embedded_payload(wrb); 743 req = embedded_payload(wrb);
747 ctxt = &req->context; 744 ctxt = &req->context;
748 745
749 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 746 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
750 OPCODE_COMMON_CQ_CREATE); 747 OPCODE_COMMON_CQ_CREATE, sizeof(*req), wrb, NULL);
751
752 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
753 OPCODE_COMMON_CQ_CREATE, sizeof(*req));
754 748
755 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 749 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
756 if (lancer_chip(adapter)) { 750 if (lancer_chip(adapter)) {
@@ -822,11 +816,8 @@ int be_cmd_mccq_ext_create(struct be_adapter *adapter,
822 req = embedded_payload(wrb); 816 req = embedded_payload(wrb);
823 ctxt = &req->context; 817 ctxt = &req->context;
824 818
825 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 819 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
826 OPCODE_COMMON_MCC_CREATE_EXT); 820 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req), wrb, NULL);
827
828 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
829 OPCODE_COMMON_MCC_CREATE_EXT, sizeof(*req));
830 821
831 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 822 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
832 if (lancer_chip(adapter)) { 823 if (lancer_chip(adapter)) {
@@ -882,11 +873,8 @@ int be_cmd_mccq_org_create(struct be_adapter *adapter,
882 req = embedded_payload(wrb); 873 req = embedded_payload(wrb);
883 ctxt = &req->context; 874 ctxt = &req->context;
884 875
885 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 876 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
886 OPCODE_COMMON_MCC_CREATE); 877 OPCODE_COMMON_MCC_CREATE, sizeof(*req), wrb, NULL);
887
888 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
889 OPCODE_COMMON_MCC_CREATE, sizeof(*req));
890 878
891 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size)); 879 req->num_pages = cpu_to_le16(PAGES_4K_SPANNED(q_mem->va, q_mem->size));
892 880
@@ -943,11 +931,8 @@ int be_cmd_txq_create(struct be_adapter *adapter,
943 req = embedded_payload(wrb); 931 req = embedded_payload(wrb);
944 ctxt = &req->context; 932 ctxt = &req->context;
945 933
946 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 934 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
947 OPCODE_ETH_TX_CREATE); 935 OPCODE_ETH_TX_CREATE, sizeof(*req), wrb, NULL);
948
949 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_TX_CREATE,
950 sizeof(*req));
951 936
952 if (lancer_chip(adapter)) { 937 if (lancer_chip(adapter)) {
953 req->hdr.version = 1; 938 req->hdr.version = 1;
@@ -999,11 +984,8 @@ int be_cmd_rxq_create(struct be_adapter *adapter,
999 } 984 }
1000 req = embedded_payload(wrb); 985 req = embedded_payload(wrb);
1001 986
1002 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 987 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1003 OPCODE_ETH_RX_CREATE); 988 OPCODE_ETH_RX_CREATE, sizeof(*req), wrb, NULL);
1004
1005 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_CREATE,
1006 sizeof(*req));
1007 989
1008 req->cq_id = cpu_to_le16(cq_id); 990 req->cq_id = cpu_to_le16(cq_id);
1009 req->frag_size = fls(frag_size) - 1; 991 req->frag_size = fls(frag_size) - 1;
@@ -1071,9 +1053,8 @@ int be_cmd_q_destroy(struct be_adapter *adapter, struct be_queue_info *q,
1071 BUG(); 1053 BUG();
1072 } 1054 }
1073 1055
1074 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, opcode); 1056 be_wrb_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req), wrb,
1075 1057 NULL);
1076 be_cmd_hdr_prepare(&req->hdr, subsys, opcode, sizeof(*req));
1077 req->id = cpu_to_le16(q->id); 1058 req->id = cpu_to_le16(q->id);
1078 1059
1079 status = be_mbox_notify_wait(adapter); 1060 status = be_mbox_notify_wait(adapter);
@@ -1100,9 +1081,8 @@ int be_cmd_rxq_destroy(struct be_adapter *adapter, struct be_queue_info *q)
1100 } 1081 }
1101 req = embedded_payload(wrb); 1082 req = embedded_payload(wrb);
1102 1083
1103 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, OPCODE_ETH_RX_DESTROY); 1084 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1104 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH, OPCODE_ETH_RX_DESTROY, 1085 OPCODE_ETH_RX_DESTROY, sizeof(*req), wrb, NULL);
1105 sizeof(*req));
1106 req->id = cpu_to_le16(q->id); 1086 req->id = cpu_to_le16(q->id);
1107 1087
1108 status = be_mcc_notify_wait(adapter); 1088 status = be_mcc_notify_wait(adapter);
@@ -1133,12 +1113,8 @@ int be_cmd_if_create(struct be_adapter *adapter, u32 cap_flags, u32 en_flags,
1133 } 1113 }
1134 req = embedded_payload(wrb); 1114 req = embedded_payload(wrb);
1135 1115
1136 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1116 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1137 OPCODE_COMMON_NTWK_INTERFACE_CREATE); 1117 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req), wrb, NULL);
1138
1139 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1140 OPCODE_COMMON_NTWK_INTERFACE_CREATE, sizeof(*req));
1141
1142 req->hdr.domain = domain; 1118 req->hdr.domain = domain;
1143 req->capability_flags = cpu_to_le32(cap_flags); 1119 req->capability_flags = cpu_to_le32(cap_flags);
1144 req->enable_flags = cpu_to_le32(en_flags); 1120 req->enable_flags = cpu_to_le32(en_flags);
@@ -1182,12 +1158,8 @@ int be_cmd_if_destroy(struct be_adapter *adapter, u32 interface_id, u32 domain)
1182 } 1158 }
1183 req = embedded_payload(wrb); 1159 req = embedded_payload(wrb);
1184 1160
1185 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1161 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1186 OPCODE_COMMON_NTWK_INTERFACE_DESTROY); 1162 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req), wrb, NULL);
1187
1188 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1189 OPCODE_COMMON_NTWK_INTERFACE_DESTROY, sizeof(*req));
1190
1191 req->hdr.domain = domain; 1163 req->hdr.domain = domain;
1192 req->interface_id = cpu_to_le32(interface_id); 1164 req->interface_id = cpu_to_le32(interface_id);
1193 1165
@@ -1205,7 +1177,6 @@ int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1205{ 1177{
1206 struct be_mcc_wrb *wrb; 1178 struct be_mcc_wrb *wrb;
1207 struct be_cmd_req_hdr *hdr; 1179 struct be_cmd_req_hdr *hdr;
1208 struct be_sge *sge;
1209 int status = 0; 1180 int status = 0;
1210 1181
1211 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0) 1182 if (MODULO(adapter->work_counter, be_get_temp_freq) == 0)
@@ -1219,22 +1190,13 @@ int be_cmd_get_stats(struct be_adapter *adapter, struct be_dma_mem *nonemb_cmd)
1219 goto err; 1190 goto err;
1220 } 1191 }
1221 hdr = nonemb_cmd->va; 1192 hdr = nonemb_cmd->va;
1222 sge = nonembedded_sgl(wrb);
1223
1224 be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1225 OPCODE_ETH_GET_STATISTICS);
1226 1193
1227 be_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH, 1194 be_wrb_cmd_hdr_prepare(hdr, CMD_SUBSYSTEM_ETH,
1228 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size); 1195 OPCODE_ETH_GET_STATISTICS, nonemb_cmd->size, wrb, nonemb_cmd);
1229 1196
1230 if (adapter->generation == BE_GEN3) 1197 if (adapter->generation == BE_GEN3)
1231 hdr->version = 1; 1198 hdr->version = 1;
1232 1199
1233 wrb->tag1 = CMD_SUBSYSTEM_ETH;
1234 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1235 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1236 sge->len = cpu_to_le32(nonemb_cmd->size);
1237
1238 be_mcc_notify(adapter); 1200 be_mcc_notify(adapter);
1239 adapter->stats_cmd_sent = true; 1201 adapter->stats_cmd_sent = true;
1240 1202
@@ -1250,7 +1212,6 @@ int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1250 1212
1251 struct be_mcc_wrb *wrb; 1213 struct be_mcc_wrb *wrb;
1252 struct lancer_cmd_req_pport_stats *req; 1214 struct lancer_cmd_req_pport_stats *req;
1253 struct be_sge *sge;
1254 int status = 0; 1215 int status = 0;
1255 1216
1256 spin_lock_bh(&adapter->mcc_lock); 1217 spin_lock_bh(&adapter->mcc_lock);
@@ -1261,23 +1222,14 @@ int lancer_cmd_get_pport_stats(struct be_adapter *adapter,
1261 goto err; 1222 goto err;
1262 } 1223 }
1263 req = nonemb_cmd->va; 1224 req = nonemb_cmd->va;
1264 sge = nonembedded_sgl(wrb);
1265
1266 be_wrb_hdr_prepare(wrb, nonemb_cmd->size, false, 1,
1267 OPCODE_ETH_GET_PPORT_STATS);
1268
1269 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1270 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size);
1271 1225
1226 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1227 OPCODE_ETH_GET_PPORT_STATS, nonemb_cmd->size, wrb,
1228 nonemb_cmd);
1272 1229
1273 req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num); 1230 req->cmd_params.params.pport_num = cpu_to_le16(adapter->port_num);
1274 req->cmd_params.params.reset_stats = 0; 1231 req->cmd_params.params.reset_stats = 0;
1275 1232
1276 wrb->tag1 = CMD_SUBSYSTEM_ETH;
1277 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
1278 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
1279 sge->len = cpu_to_le32(nonemb_cmd->size);
1280
1281 be_mcc_notify(adapter); 1233 be_mcc_notify(adapter);
1282 adapter->stats_cmd_sent = true; 1234 adapter->stats_cmd_sent = true;
1283 1235
@@ -1303,11 +1255,8 @@ int be_cmd_link_status_query(struct be_adapter *adapter, u8 *mac_speed,
1303 } 1255 }
1304 req = embedded_payload(wrb); 1256 req = embedded_payload(wrb);
1305 1257
1306 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1258 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1307 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY); 1259 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req), wrb, NULL);
1308
1309 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1310 OPCODE_COMMON_NTWK_LINK_STATUS_QUERY, sizeof(*req));
1311 1260
1312 status = be_mcc_notify_wait(adapter); 1261 status = be_mcc_notify_wait(adapter);
1313 if (!status) { 1262 if (!status) {
@@ -1343,11 +1292,9 @@ int be_cmd_get_die_temperature(struct be_adapter *adapter)
1343 } 1292 }
1344 req = embedded_payload(wrb); 1293 req = embedded_payload(wrb);
1345 1294
1346 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1295 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1347 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES); 1296 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req),
1348 1297 wrb, NULL);
1349 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1350 OPCODE_COMMON_GET_CNTL_ADDITIONAL_ATTRIBUTES, sizeof(*req));
1351 1298
1352 wrb->tag1 = mccq_index; 1299 wrb->tag1 = mccq_index;
1353 1300
@@ -1374,11 +1321,8 @@ int be_cmd_get_reg_len(struct be_adapter *adapter, u32 *log_size)
1374 } 1321 }
1375 req = embedded_payload(wrb); 1322 req = embedded_payload(wrb);
1376 1323
1377 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1324 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1378 OPCODE_COMMON_MANAGE_FAT); 1325 OPCODE_COMMON_MANAGE_FAT, sizeof(*req), wrb, NULL);
1379
1380 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1381 OPCODE_COMMON_MANAGE_FAT, sizeof(*req));
1382 req->fat_operation = cpu_to_le32(QUERY_FAT); 1326 req->fat_operation = cpu_to_le32(QUERY_FAT);
1383 status = be_mcc_notify_wait(adapter); 1327 status = be_mcc_notify_wait(adapter);
1384 if (!status) { 1328 if (!status) {
@@ -1397,7 +1341,6 @@ void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1397 struct be_dma_mem get_fat_cmd; 1341 struct be_dma_mem get_fat_cmd;
1398 struct be_mcc_wrb *wrb; 1342 struct be_mcc_wrb *wrb;
1399 struct be_cmd_req_get_fat *req; 1343 struct be_cmd_req_get_fat *req;
1400 struct be_sge *sge;
1401 u32 offset = 0, total_size, buf_size, 1344 u32 offset = 0, total_size, buf_size,
1402 log_offset = sizeof(u32), payload_len; 1345 log_offset = sizeof(u32), payload_len;
1403 int status; 1346 int status;
@@ -1430,18 +1373,11 @@ void be_cmd_get_regs(struct be_adapter *adapter, u32 buf_len, void *buf)
1430 goto err; 1373 goto err;
1431 } 1374 }
1432 req = get_fat_cmd.va; 1375 req = get_fat_cmd.va;
1433 sge = nonembedded_sgl(wrb);
1434 1376
1435 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size; 1377 payload_len = sizeof(struct be_cmd_req_get_fat) + buf_size;
1436 be_wrb_hdr_prepare(wrb, payload_len, false, 1, 1378 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1437 OPCODE_COMMON_MANAGE_FAT); 1379 OPCODE_COMMON_MANAGE_FAT, payload_len, wrb,
1438 1380 &get_fat_cmd);
1439 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1440 OPCODE_COMMON_MANAGE_FAT, payload_len);
1441
1442 sge->pa_hi = cpu_to_le32(upper_32_bits(get_fat_cmd.dma));
1443 sge->pa_lo = cpu_to_le32(get_fat_cmd.dma & 0xFFFFFFFF);
1444 sge->len = cpu_to_le32(get_fat_cmd.size);
1445 1381
1446 req->fat_operation = cpu_to_le32(RETRIEVE_FAT); 1382 req->fat_operation = cpu_to_le32(RETRIEVE_FAT);
1447 req->read_log_offset = cpu_to_le32(log_offset); 1383 req->read_log_offset = cpu_to_le32(log_offset);
@@ -1485,11 +1421,9 @@ int be_cmd_get_fw_ver(struct be_adapter *adapter, char *fw_ver,
1485 } 1421 }
1486 1422
1487 req = embedded_payload(wrb); 1423 req = embedded_payload(wrb);
1488 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0,
1489 OPCODE_COMMON_GET_FW_VERSION);
1490 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1491 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req));
1492 1424
1425 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1426 OPCODE_COMMON_GET_FW_VERSION, sizeof(*req), wrb, NULL);
1493 status = be_mcc_notify_wait(adapter); 1427 status = be_mcc_notify_wait(adapter);
1494 if (!status) { 1428 if (!status) {
1495 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb); 1429 struct be_cmd_resp_get_fw_version *resp = embedded_payload(wrb);
@@ -1520,11 +1454,8 @@ int be_cmd_modify_eqd(struct be_adapter *adapter, u32 eq_id, u32 eqd)
1520 } 1454 }
1521 req = embedded_payload(wrb); 1455 req = embedded_payload(wrb);
1522 1456
1523 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1457 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1524 OPCODE_COMMON_MODIFY_EQ_DELAY); 1458 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req), wrb, NULL);
1525
1526 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1527 OPCODE_COMMON_MODIFY_EQ_DELAY, sizeof(*req));
1528 1459
1529 req->num_eq = cpu_to_le32(1); 1460 req->num_eq = cpu_to_le32(1);
1530 req->delay[0].eq_id = cpu_to_le32(eq_id); 1461 req->delay[0].eq_id = cpu_to_le32(eq_id);
@@ -1555,11 +1486,8 @@ int be_cmd_vlan_config(struct be_adapter *adapter, u32 if_id, u16 *vtag_array,
1555 } 1486 }
1556 req = embedded_payload(wrb); 1487 req = embedded_payload(wrb);
1557 1488
1558 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1489 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1559 OPCODE_COMMON_NTWK_VLAN_CONFIG); 1490 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req), wrb, NULL);
1560
1561 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1562 OPCODE_COMMON_NTWK_VLAN_CONFIG, sizeof(*req));
1563 1491
1564 req->interface_id = if_id; 1492 req->interface_id = if_id;
1565 req->promiscuous = promiscuous; 1493 req->promiscuous = promiscuous;
@@ -1582,7 +1510,6 @@ int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1582 struct be_mcc_wrb *wrb; 1510 struct be_mcc_wrb *wrb;
1583 struct be_dma_mem *mem = &adapter->rx_filter; 1511 struct be_dma_mem *mem = &adapter->rx_filter;
1584 struct be_cmd_req_rx_filter *req = mem->va; 1512 struct be_cmd_req_rx_filter *req = mem->va;
1585 struct be_sge *sge;
1586 int status; 1513 int status;
1587 1514
1588 spin_lock_bh(&adapter->mcc_lock); 1515 spin_lock_bh(&adapter->mcc_lock);
@@ -1592,16 +1519,10 @@ int be_cmd_rx_filter(struct be_adapter *adapter, u32 flags, u32 value)
1592 status = -EBUSY; 1519 status = -EBUSY;
1593 goto err; 1520 goto err;
1594 } 1521 }
1595 sge = nonembedded_sgl(wrb);
1596 sge->pa_hi = cpu_to_le32(upper_32_bits(mem->dma));
1597 sge->pa_lo = cpu_to_le32(mem->dma & 0xFFFFFFFF);
1598 sge->len = cpu_to_le32(mem->size);
1599 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
1600 OPCODE_COMMON_NTWK_RX_FILTER);
1601
1602 memset(req, 0, sizeof(*req)); 1522 memset(req, 0, sizeof(*req));
1603 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1523 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1604 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req)); 1524 OPCODE_COMMON_NTWK_RX_FILTER, sizeof(*req),
1525 wrb, mem);
1605 1526
1606 req->if_id = cpu_to_le32(adapter->if_handle); 1527 req->if_id = cpu_to_le32(adapter->if_handle);
1607 if (flags & IFF_PROMISC) { 1528 if (flags & IFF_PROMISC) {
@@ -1646,11 +1567,8 @@ int be_cmd_set_flow_control(struct be_adapter *adapter, u32 tx_fc, u32 rx_fc)
1646 } 1567 }
1647 req = embedded_payload(wrb); 1568 req = embedded_payload(wrb);
1648 1569
1649 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1570 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1650 OPCODE_COMMON_SET_FLOW_CONTROL); 1571 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1651
1652 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1653 OPCODE_COMMON_SET_FLOW_CONTROL, sizeof(*req));
1654 1572
1655 req->tx_flow_control = cpu_to_le16((u16)tx_fc); 1573 req->tx_flow_control = cpu_to_le16((u16)tx_fc);
1656 req->rx_flow_control = cpu_to_le16((u16)rx_fc); 1574 req->rx_flow_control = cpu_to_le16((u16)rx_fc);
@@ -1678,11 +1596,8 @@ int be_cmd_get_flow_control(struct be_adapter *adapter, u32 *tx_fc, u32 *rx_fc)
1678 } 1596 }
1679 req = embedded_payload(wrb); 1597 req = embedded_payload(wrb);
1680 1598
1681 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1599 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1682 OPCODE_COMMON_GET_FLOW_CONTROL); 1600 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req), wrb, NULL);
1683
1684 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1685 OPCODE_COMMON_GET_FLOW_CONTROL, sizeof(*req));
1686 1601
1687 status = be_mcc_notify_wait(adapter); 1602 status = be_mcc_notify_wait(adapter);
1688 if (!status) { 1603 if (!status) {
@@ -1711,11 +1626,8 @@ int be_cmd_query_fw_cfg(struct be_adapter *adapter, u32 *port_num,
1711 wrb = wrb_from_mbox(adapter); 1626 wrb = wrb_from_mbox(adapter);
1712 req = embedded_payload(wrb); 1627 req = embedded_payload(wrb);
1713 1628
1714 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1629 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1715 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG); 1630 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req), wrb, NULL);
1716
1717 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1718 OPCODE_COMMON_QUERY_FIRMWARE_CONFIG, sizeof(*req));
1719 1631
1720 status = be_mbox_notify_wait(adapter); 1632 status = be_mbox_notify_wait(adapter);
1721 if (!status) { 1633 if (!status) {
@@ -1742,11 +1654,8 @@ int be_cmd_reset_function(struct be_adapter *adapter)
1742 wrb = wrb_from_mbox(adapter); 1654 wrb = wrb_from_mbox(adapter);
1743 req = embedded_payload(wrb); 1655 req = embedded_payload(wrb);
1744 1656
1745 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1657 be_wrb_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1746 OPCODE_COMMON_FUNCTION_RESET); 1658 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req), wrb, NULL);
1747
1748 be_cmd_hdr_prepare(req, CMD_SUBSYSTEM_COMMON,
1749 OPCODE_COMMON_FUNCTION_RESET, sizeof(*req));
1750 1659
1751 status = be_mbox_notify_wait(adapter); 1660 status = be_mbox_notify_wait(adapter);
1752 1661
@@ -1768,11 +1677,8 @@ int be_cmd_rss_config(struct be_adapter *adapter, u8 *rsstable, u16 table_size)
1768 wrb = wrb_from_mbox(adapter); 1677 wrb = wrb_from_mbox(adapter);
1769 req = embedded_payload(wrb); 1678 req = embedded_payload(wrb);
1770 1679
1771 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1680 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1772 OPCODE_ETH_RSS_CONFIG); 1681 OPCODE_ETH_RSS_CONFIG, sizeof(*req), wrb, NULL);
1773
1774 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
1775 OPCODE_ETH_RSS_CONFIG, sizeof(*req));
1776 1682
1777 req->if_id = cpu_to_le32(adapter->if_handle); 1683 req->if_id = cpu_to_le32(adapter->if_handle);
1778 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4); 1684 req->enable_rss = cpu_to_le16(RSS_ENABLE_TCP_IPV4 | RSS_ENABLE_IPV4);
@@ -1804,11 +1710,8 @@ int be_cmd_set_beacon_state(struct be_adapter *adapter, u8 port_num,
1804 } 1710 }
1805 req = embedded_payload(wrb); 1711 req = embedded_payload(wrb);
1806 1712
1807 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1713 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1808 OPCODE_COMMON_ENABLE_DISABLE_BEACON); 1714 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req), wrb, NULL);
1809
1810 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1811 OPCODE_COMMON_ENABLE_DISABLE_BEACON, sizeof(*req));
1812 1715
1813 req->port_num = port_num; 1716 req->port_num = port_num;
1814 req->beacon_state = state; 1717 req->beacon_state = state;
@@ -1838,11 +1741,8 @@ int be_cmd_get_beacon_state(struct be_adapter *adapter, u8 port_num, u32 *state)
1838 } 1741 }
1839 req = embedded_payload(wrb); 1742 req = embedded_payload(wrb);
1840 1743
1841 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1744 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1842 OPCODE_COMMON_GET_BEACON_STATE); 1745 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req), wrb, NULL);
1843
1844 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1845 OPCODE_COMMON_GET_BEACON_STATE, sizeof(*req));
1846 1746
1847 req->port_num = port_num; 1747 req->port_num = port_num;
1848 1748
@@ -1879,13 +1779,10 @@ int lancer_cmd_write_object(struct be_adapter *adapter, struct be_dma_mem *cmd,
1879 1779
1880 req = embedded_payload(wrb); 1780 req = embedded_payload(wrb);
1881 1781
1882 be_wrb_hdr_prepare(wrb, sizeof(struct lancer_cmd_req_write_object), 1782 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1883 true, 1, OPCODE_COMMON_WRITE_OBJECT);
1884 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1885
1886 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1887 OPCODE_COMMON_WRITE_OBJECT, 1783 OPCODE_COMMON_WRITE_OBJECT,
1888 sizeof(struct lancer_cmd_req_write_object)); 1784 sizeof(struct lancer_cmd_req_write_object), wrb,
1785 NULL);
1889 1786
1890 ctxt = &req->context; 1787 ctxt = &req->context;
1891 AMAP_SET_BITS(struct amap_lancer_write_obj_context, 1788 AMAP_SET_BITS(struct amap_lancer_write_obj_context,
@@ -1938,7 +1835,6 @@ int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1938{ 1835{
1939 struct be_mcc_wrb *wrb; 1836 struct be_mcc_wrb *wrb;
1940 struct be_cmd_write_flashrom *req; 1837 struct be_cmd_write_flashrom *req;
1941 struct be_sge *sge;
1942 int status; 1838 int status;
1943 1839
1944 spin_lock_bh(&adapter->mcc_lock); 1840 spin_lock_bh(&adapter->mcc_lock);
@@ -1950,17 +1846,9 @@ int be_cmd_write_flashrom(struct be_adapter *adapter, struct be_dma_mem *cmd,
1950 goto err_unlock; 1846 goto err_unlock;
1951 } 1847 }
1952 req = cmd->va; 1848 req = cmd->va;
1953 sge = nonembedded_sgl(wrb);
1954
1955 be_wrb_hdr_prepare(wrb, cmd->size, false, 1,
1956 OPCODE_COMMON_WRITE_FLASHROM);
1957 wrb->tag1 = CMD_SUBSYSTEM_COMMON;
1958 1849
1959 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 1850 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
1960 OPCODE_COMMON_WRITE_FLASHROM, cmd->size); 1851 OPCODE_COMMON_WRITE_FLASHROM, cmd->size, wrb, cmd);
1961 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
1962 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
1963 sge->len = cpu_to_le32(cmd->size);
1964 1852
1965 req->params.op_type = cpu_to_le32(flash_type); 1853 req->params.op_type = cpu_to_le32(flash_type);
1966 req->params.op_code = cpu_to_le32(flash_opcode); 1854 req->params.op_code = cpu_to_le32(flash_opcode);
@@ -1998,11 +1886,8 @@ int be_cmd_get_flash_crc(struct be_adapter *adapter, u8 *flashed_crc,
1998 } 1886 }
1999 req = embedded_payload(wrb); 1887 req = embedded_payload(wrb);
2000 1888
2001 be_wrb_hdr_prepare(wrb, sizeof(*req)+4, true, 0, 1889 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2002 OPCODE_COMMON_READ_FLASHROM); 1890 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4, wrb, NULL);
2003
2004 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2005 OPCODE_COMMON_READ_FLASHROM, sizeof(*req)+4);
2006 1891
2007 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT); 1892 req->params.op_type = cpu_to_le32(IMG_TYPE_REDBOOT);
2008 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT); 1893 req->params.op_code = cpu_to_le32(FLASHROM_OPER_REPORT);
@@ -2023,7 +1908,6 @@ int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2023{ 1908{
2024 struct be_mcc_wrb *wrb; 1909 struct be_mcc_wrb *wrb;
2025 struct be_cmd_req_acpi_wol_magic_config *req; 1910 struct be_cmd_req_acpi_wol_magic_config *req;
2026 struct be_sge *sge;
2027 int status; 1911 int status;
2028 1912
2029 spin_lock_bh(&adapter->mcc_lock); 1913 spin_lock_bh(&adapter->mcc_lock);
@@ -2034,19 +1918,12 @@ int be_cmd_enable_magic_wol(struct be_adapter *adapter, u8 *mac,
2034 goto err; 1918 goto err;
2035 } 1919 }
2036 req = nonemb_cmd->va; 1920 req = nonemb_cmd->va;
2037 sge = nonembedded_sgl(wrb);
2038 1921
2039 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, 1922 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2040 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG); 1923 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req), wrb,
2041 1924 nonemb_cmd);
2042 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_ETH,
2043 OPCODE_ETH_ACPI_WOL_MAGIC_CONFIG, sizeof(*req));
2044 memcpy(req->magic_mac, mac, ETH_ALEN); 1925 memcpy(req->magic_mac, mac, ETH_ALEN);
2045 1926
2046 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2047 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2048 sge->len = cpu_to_le32(nonemb_cmd->size);
2049
2050 status = be_mcc_notify_wait(adapter); 1927 status = be_mcc_notify_wait(adapter);
2051 1928
2052err: 1929err:
@@ -2071,12 +1948,9 @@ int be_cmd_set_loopback(struct be_adapter *adapter, u8 port_num,
2071 1948
2072 req = embedded_payload(wrb); 1949 req = embedded_payload(wrb);
2073 1950
2074 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1951 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2075 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE); 1952 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE, sizeof(*req), wrb,
2076 1953 NULL);
2077 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2078 OPCODE_LOWLEVEL_SET_LOOPBACK_MODE,
2079 sizeof(*req));
2080 1954
2081 req->src_port = port_num; 1955 req->src_port = port_num;
2082 req->dest_port = port_num; 1956 req->dest_port = port_num;
@@ -2106,11 +1980,8 @@ int be_cmd_loopback_test(struct be_adapter *adapter, u32 port_num,
2106 1980
2107 req = embedded_payload(wrb); 1981 req = embedded_payload(wrb);
2108 1982
2109 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 1983 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2110 OPCODE_LOWLEVEL_LOOPBACK_TEST); 1984 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req), wrb, NULL);
2111
2112 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2113 OPCODE_LOWLEVEL_LOOPBACK_TEST, sizeof(*req));
2114 req->hdr.timeout = cpu_to_le32(4); 1985 req->hdr.timeout = cpu_to_le32(4);
2115 1986
2116 req->pattern = cpu_to_le64(pattern); 1987 req->pattern = cpu_to_le64(pattern);
@@ -2136,7 +2007,6 @@ int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2136{ 2007{
2137 struct be_mcc_wrb *wrb; 2008 struct be_mcc_wrb *wrb;
2138 struct be_cmd_req_ddrdma_test *req; 2009 struct be_cmd_req_ddrdma_test *req;
2139 struct be_sge *sge;
2140 int status; 2010 int status;
2141 int i, j = 0; 2011 int i, j = 0;
2142 2012
@@ -2148,15 +2018,8 @@ int be_cmd_ddr_dma_test(struct be_adapter *adapter, u64 pattern,
2148 goto err; 2018 goto err;
2149 } 2019 }
2150 req = cmd->va; 2020 req = cmd->va;
2151 sge = nonembedded_sgl(wrb); 2021 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2152 be_wrb_hdr_prepare(wrb, cmd->size, false, 1, 2022 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size, wrb, cmd);
2153 OPCODE_LOWLEVEL_HOST_DDR_DMA);
2154 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_LOWLEVEL,
2155 OPCODE_LOWLEVEL_HOST_DDR_DMA, cmd->size);
2156
2157 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd->dma));
2158 sge->pa_lo = cpu_to_le32(cmd->dma & 0xFFFFFFFF);
2159 sge->len = cpu_to_le32(cmd->size);
2160 2023
2161 req->pattern = cpu_to_le64(pattern); 2024 req->pattern = cpu_to_le64(pattern);
2162 req->byte_count = cpu_to_le32(byte_cnt); 2025 req->byte_count = cpu_to_le32(byte_cnt);
@@ -2201,15 +2064,9 @@ int be_cmd_get_seeprom_data(struct be_adapter *adapter,
2201 req = nonemb_cmd->va; 2064 req = nonemb_cmd->va;
2202 sge = nonembedded_sgl(wrb); 2065 sge = nonembedded_sgl(wrb);
2203 2066
2204 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1, 2067 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2205 OPCODE_COMMON_SEEPROM_READ); 2068 OPCODE_COMMON_SEEPROM_READ, sizeof(*req), wrb,
2206 2069 nonemb_cmd);
2207 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2208 OPCODE_COMMON_SEEPROM_READ, sizeof(*req));
2209
2210 sge->pa_hi = cpu_to_le32(upper_32_bits(nonemb_cmd->dma));
2211 sge->pa_lo = cpu_to_le32(nonemb_cmd->dma & 0xFFFFFFFF);
2212 sge->len = cpu_to_le32(nonemb_cmd->size);
2213 2070
2214 status = be_mcc_notify_wait(adapter); 2071 status = be_mcc_notify_wait(adapter);
2215 2072
@@ -2223,7 +2080,6 @@ int be_cmd_get_phy_info(struct be_adapter *adapter,
2223{ 2080{
2224 struct be_mcc_wrb *wrb; 2081 struct be_mcc_wrb *wrb;
2225 struct be_cmd_req_get_phy_info *req; 2082 struct be_cmd_req_get_phy_info *req;
2226 struct be_sge *sge;
2227 struct be_dma_mem cmd; 2083 struct be_dma_mem cmd;
2228 int status; 2084 int status;
2229 2085
@@ -2244,18 +2100,10 @@ int be_cmd_get_phy_info(struct be_adapter *adapter,
2244 } 2100 }
2245 2101
2246 req = cmd.va; 2102 req = cmd.va;
2247 sge = nonembedded_sgl(wrb);
2248
2249 be_wrb_hdr_prepare(wrb, sizeof(*req), false, 1,
2250 OPCODE_COMMON_GET_PHY_DETAILS);
2251 2103
2252 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2104 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2253 OPCODE_COMMON_GET_PHY_DETAILS, 2105 OPCODE_COMMON_GET_PHY_DETAILS, sizeof(*req),
2254 sizeof(*req)); 2106 wrb, &cmd);
2255
2256 sge->pa_hi = cpu_to_le32(upper_32_bits(cmd.dma));
2257 sge->pa_lo = cpu_to_le32(cmd.dma & 0xFFFFFFFF);
2258 sge->len = cpu_to_le32(cmd.size);
2259 2107
2260 status = be_mcc_notify_wait(adapter); 2108 status = be_mcc_notify_wait(adapter);
2261 if (!status) { 2109 if (!status) {
@@ -2288,11 +2136,8 @@ int be_cmd_set_qos(struct be_adapter *adapter, u32 bps, u32 domain)
2288 2136
2289 req = embedded_payload(wrb); 2137 req = embedded_payload(wrb);
2290 2138
2291 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 2139 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2292 OPCODE_COMMON_SET_QOS); 2140 OPCODE_COMMON_SET_QOS, sizeof(*req), wrb, NULL);
2293
2294 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2295 OPCODE_COMMON_SET_QOS, sizeof(*req));
2296 2141
2297 req->hdr.domain = domain; 2142 req->hdr.domain = domain;
2298 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC); 2143 req->valid_bits = cpu_to_le32(BE_QOS_BITS_NIC);
@@ -2310,7 +2155,6 @@ int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2310 struct be_mcc_wrb *wrb; 2155 struct be_mcc_wrb *wrb;
2311 struct be_cmd_req_cntl_attribs *req; 2156 struct be_cmd_req_cntl_attribs *req;
2312 struct be_cmd_resp_cntl_attribs *resp; 2157 struct be_cmd_resp_cntl_attribs *resp;
2313 struct be_sge *sge;
2314 int status; 2158 int status;
2315 int payload_len = max(sizeof(*req), sizeof(*resp)); 2159 int payload_len = max(sizeof(*req), sizeof(*resp));
2316 struct mgmt_controller_attrib *attribs; 2160 struct mgmt_controller_attrib *attribs;
@@ -2335,15 +2179,10 @@ int be_cmd_get_cntl_attributes(struct be_adapter *adapter)
2335 goto err; 2179 goto err;
2336 } 2180 }
2337 req = attribs_cmd.va; 2181 req = attribs_cmd.va;
2338 sge = nonembedded_sgl(wrb);
2339 2182
2340 be_wrb_hdr_prepare(wrb, payload_len, false, 1, 2183 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2341 OPCODE_COMMON_GET_CNTL_ATTRIBUTES); 2184 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len, wrb,
2342 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON, 2185 &attribs_cmd);
2343 OPCODE_COMMON_GET_CNTL_ATTRIBUTES, payload_len);
2344 sge->pa_hi = cpu_to_le32(upper_32_bits(attribs_cmd.dma));
2345 sge->pa_lo = cpu_to_le32(attribs_cmd.dma & 0xFFFFFFFF);
2346 sge->len = cpu_to_le32(attribs_cmd.size);
2347 2186
2348 status = be_mbox_notify_wait(adapter); 2187 status = be_mbox_notify_wait(adapter);
2349 if (!status) { 2188 if (!status) {
@@ -2376,11 +2215,8 @@ int be_cmd_req_native_mode(struct be_adapter *adapter)
2376 2215
2377 req = embedded_payload(wrb); 2216 req = embedded_payload(wrb);
2378 2217
2379 be_wrb_hdr_prepare(wrb, sizeof(*req), true, 0, 2218 be_wrb_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2380 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP); 2219 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req), wrb, NULL);
2381
2382 be_cmd_hdr_prepare(&req->hdr, CMD_SUBSYSTEM_COMMON,
2383 OPCODE_COMMON_SET_DRIVER_FUNCTION_CAP, sizeof(*req));
2384 2220
2385 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS | 2221 req->valid_cap_flags = cpu_to_le32(CAPABILITY_SW_TIMESTAMPS |
2386 CAPABILITY_BE3_NATIVE_ERX_API); 2222 CAPABILITY_BE3_NATIVE_ERX_API);
diff --git a/drivers/net/ethernet/emulex/benet/be_main.c b/drivers/net/ethernet/emulex/benet/be_main.c
index d6a232a300ad..21804972fa2f 100644
--- a/drivers/net/ethernet/emulex/benet/be_main.c
+++ b/drivers/net/ethernet/emulex/benet/be_main.c
@@ -229,27 +229,29 @@ static int be_mac_addr_set(struct net_device *netdev, void *p)
229 struct be_adapter *adapter = netdev_priv(netdev); 229 struct be_adapter *adapter = netdev_priv(netdev);
230 struct sockaddr *addr = p; 230 struct sockaddr *addr = p;
231 int status = 0; 231 int status = 0;
232 u8 current_mac[ETH_ALEN];
233 u32 pmac_id = adapter->pmac_id;
232 234
233 if (!is_valid_ether_addr(addr->sa_data)) 235 if (!is_valid_ether_addr(addr->sa_data))
234 return -EADDRNOTAVAIL; 236 return -EADDRNOTAVAIL;
235 237
236 /* MAC addr configuration will be done in hardware for VFs 238 status = be_cmd_mac_addr_query(adapter, current_mac,
237 * by their corresponding PFs. Just copy to netdev addr here 239 MAC_ADDRESS_TYPE_NETWORK, false, adapter->if_handle);
238 */
239 if (!be_physfn(adapter))
240 goto netdev_addr;
241
242 status = be_cmd_pmac_del(adapter, adapter->if_handle,
243 adapter->pmac_id, 0);
244 if (status) 240 if (status)
245 return status; 241 goto err;
246 242
247 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data, 243 if (memcmp(addr->sa_data, current_mac, ETH_ALEN)) {
244 status = be_cmd_pmac_add(adapter, (u8 *)addr->sa_data,
248 adapter->if_handle, &adapter->pmac_id, 0); 245 adapter->if_handle, &adapter->pmac_id, 0);
249netdev_addr: 246 if (status)
250 if (!status) 247 goto err;
251 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
252 248
249 be_cmd_pmac_del(adapter, adapter->if_handle, pmac_id, 0);
250 }
251 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
252 return 0;
253err:
254 dev_err(&adapter->pdev->dev, "MAC %pM set Failed\n", addr->sa_data);
253 return status; 255 return status;
254} 256}
255 257
diff --git a/drivers/net/ethernet/i825xx/Kconfig b/drivers/net/ethernet/i825xx/Kconfig
index 2be46986cbe2..ca1ae985c6df 100644
--- a/drivers/net/ethernet/i825xx/Kconfig
+++ b/drivers/net/ethernet/i825xx/Kconfig
@@ -85,7 +85,7 @@ config APRICOT
85 85
86config BVME6000_NET 86config BVME6000_NET
87 tristate "BVME6000 Ethernet support" 87 tristate "BVME6000 Ethernet support"
88 depends on BVME6000MVME16x 88 depends on BVME6000
89 ---help--- 89 ---help---
90 This is the driver for the Ethernet interface on BVME4000 and 90 This is the driver for the Ethernet interface on BVME4000 and
91 BVME6000 VME boards. Say Y here to include the driver for this chip 91 BVME6000 VME boards. Say Y here to include the driver for this chip
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
index 2fd1ba8fee4a..7ed53dbb8646 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic.h
@@ -36,8 +36,8 @@
36 36
37#define _QLCNIC_LINUX_MAJOR 5 37#define _QLCNIC_LINUX_MAJOR 5
38#define _QLCNIC_LINUX_MINOR 0 38#define _QLCNIC_LINUX_MINOR 0
39#define _QLCNIC_LINUX_SUBVERSION 24 39#define _QLCNIC_LINUX_SUBVERSION 25
40#define QLCNIC_LINUX_VERSIONID "5.0.24" 40#define QLCNIC_LINUX_VERSIONID "5.0.25"
41#define QLCNIC_DRV_IDC_VER 0x01 41#define QLCNIC_DRV_IDC_VER 0x01
42#define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\ 42#define QLCNIC_DRIVER_VERSION ((_QLCNIC_LINUX_MAJOR << 16) |\
43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION)) 43 (_QLCNIC_LINUX_MINOR << 8) | (_QLCNIC_LINUX_SUBVERSION))
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c
index 5d8bec283267..8aa1c6e8667b 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_ethtool.c
@@ -935,31 +935,49 @@ static int qlcnic_set_led(struct net_device *dev,
935{ 935{
936 struct qlcnic_adapter *adapter = netdev_priv(dev); 936 struct qlcnic_adapter *adapter = netdev_priv(dev);
937 int max_sds_rings = adapter->max_sds_rings; 937 int max_sds_rings = adapter->max_sds_rings;
938 int err = -EIO, active = 1;
939
940 if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC) {
941 netdev_warn(dev, "LED test not supported for non "
942 "privilege function\n");
943 return -EOPNOTSUPP;
944 }
938 945
939 switch (state) { 946 switch (state) {
940 case ETHTOOL_ID_ACTIVE: 947 case ETHTOOL_ID_ACTIVE:
941 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state)) 948 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state))
942 return -EBUSY; 949 return -EBUSY;
943 950
944 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) { 951 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
945 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state)) 952 break;
946 return -EIO;
947 953
948 if (qlcnic_diag_alloc_res(dev, QLCNIC_LED_TEST)) { 954 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
949 clear_bit(__QLCNIC_RESETTING, &adapter->state); 955 if (qlcnic_diag_alloc_res(dev, QLCNIC_LED_TEST))
950 return -EIO; 956 break;
951 }
952 set_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state); 957 set_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state);
953 } 958 }
954 959
955 if (adapter->nic_ops->config_led(adapter, 1, 0xf) == 0) 960 if (adapter->nic_ops->config_led(adapter, 1, 0xf) == 0) {
956 return 0; 961 err = 0;
962 break;
963 }
957 964
958 dev_err(&adapter->pdev->dev, 965 dev_err(&adapter->pdev->dev,
959 "Failed to set LED blink state.\n"); 966 "Failed to set LED blink state.\n");
960 break; 967 break;
961 968
962 case ETHTOOL_ID_INACTIVE: 969 case ETHTOOL_ID_INACTIVE:
970 active = 0;
971
972 if (test_bit(__QLCNIC_RESETTING, &adapter->state))
973 break;
974
975 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
976 if (qlcnic_diag_alloc_res(dev, QLCNIC_LED_TEST))
977 break;
978 set_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state);
979 }
980
963 if (adapter->nic_ops->config_led(adapter, 0, 0xf)) 981 if (adapter->nic_ops->config_led(adapter, 0, 0xf))
964 dev_err(&adapter->pdev->dev, 982 dev_err(&adapter->pdev->dev,
965 "Failed to reset LED blink state.\n"); 983 "Failed to reset LED blink state.\n");
@@ -970,14 +988,13 @@ static int qlcnic_set_led(struct net_device *dev,
970 return -EINVAL; 988 return -EINVAL;
971 } 989 }
972 990
973 if (test_and_clear_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state)) { 991 if (test_and_clear_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state))
974 qlcnic_diag_free_res(dev, max_sds_rings); 992 qlcnic_diag_free_res(dev, max_sds_rings);
975 clear_bit(__QLCNIC_RESETTING, &adapter->state);
976 }
977 993
978 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state); 994 if (!active || err)
995 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
979 996
980 return -EIO; 997 return err;
981} 998}
982 999
983static void 1000static void
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
index 92bc8ce9b287..a52819303d1b 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hdr.h
@@ -407,7 +407,9 @@ enum {
407#define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE) 407#define QLCNIC_CRB_SRE QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SRE)
408#define QLCNIC_CRB_ROMUSB \ 408#define QLCNIC_CRB_ROMUSB \
409 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB) 409 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_ROMUSB)
410#define QLCNIC_CRB_EPG QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_EG)
410#define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q) 411#define QLCNIC_CRB_I2Q QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2Q)
412#define QLCNIC_CRB_TIMER QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_TIMR)
411#define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0) 413#define QLCNIC_CRB_I2C0 QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_I2C0)
412#define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB) 414#define QLCNIC_CRB_SMB QLCNIC_PCI_CRB_WINDOW(QLCNIC_HW_PX_MAP_CRB_SMB)
413#define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64) 415#define QLCNIC_CRB_MAX QLCNIC_PCI_CRB_WINDOW(64)
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
index 74e9d7b94965..bcb81e47543a 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_hw.c
@@ -566,7 +566,7 @@ int qlcnic_set_lb_mode(struct qlcnic_adapter *adapter, u8 mode)
566 return -EIO; 566 return -EIO;
567 567
568 if (qlcnic_nic_set_promisc(adapter, VPORT_MISS_MODE_ACCEPT_ALL)) { 568 if (qlcnic_nic_set_promisc(adapter, VPORT_MISS_MODE_ACCEPT_ALL)) {
569 qlcnic_set_fw_loopback(adapter, mode); 569 qlcnic_set_fw_loopback(adapter, 0);
570 return -EIO; 570 return -EIO;
571 } 571 }
572 572
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
index 312c1c37889d..38669583840c 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_init.c
@@ -422,9 +422,53 @@ int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
422 QLCWR32(adapter, CRB_CMDPEG_STATE, 0); 422 QLCWR32(adapter, CRB_CMDPEG_STATE, 0);
423 QLCWR32(adapter, CRB_RCVPEG_STATE, 0); 423 QLCWR32(adapter, CRB_RCVPEG_STATE, 0);
424 424
425 qlcnic_rom_lock(adapter); 425 /* Halt all the indiviual PEGs and other blocks */
426 QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xfeffffff); 426 /* disable all I2Q */
427 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x10, 0x0);
428 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x14, 0x0);
429 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x18, 0x0);
430 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x1c, 0x0);
431 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x20, 0x0);
432 QLCWR32(adapter, QLCNIC_CRB_I2Q + 0x24, 0x0);
433
434 /* disable all niu interrupts */
435 QLCWR32(adapter, QLCNIC_CRB_NIU + 0x40, 0xff);
436 /* disable xge rx/tx */
437 QLCWR32(adapter, QLCNIC_CRB_NIU + 0x70000, 0x00);
438 /* disable xg1 rx/tx */
439 QLCWR32(adapter, QLCNIC_CRB_NIU + 0x80000, 0x00);
440 /* disable sideband mac */
441 QLCWR32(adapter, QLCNIC_CRB_NIU + 0x90000, 0x00);
442 /* disable ap0 mac */
443 QLCWR32(adapter, QLCNIC_CRB_NIU + 0xa0000, 0x00);
444 /* disable ap1 mac */
445 QLCWR32(adapter, QLCNIC_CRB_NIU + 0xb0000, 0x00);
446
447 /* halt sre */
448 val = QLCRD32(adapter, QLCNIC_CRB_SRE + 0x1000);
449 QLCWR32(adapter, QLCNIC_CRB_SRE + 0x1000, val & (~(0x1)));
450
451 /* halt epg */
452 QLCWR32(adapter, QLCNIC_CRB_EPG + 0x1300, 0x1);
453
454 /* halt timers */
455 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x0, 0x0);
456 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x8, 0x0);
457 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x10, 0x0);
458 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x18, 0x0);
459 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x100, 0x0);
460 QLCWR32(adapter, QLCNIC_CRB_TIMER + 0x200, 0x0);
461 /* halt pegs */
462 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_0 + 0x3c, 1);
463 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_1 + 0x3c, 1);
464 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_2 + 0x3c, 1);
465 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_3 + 0x3c, 1);
466 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x3c, 1);
467 msleep(20);
468
427 qlcnic_rom_unlock(adapter); 469 qlcnic_rom_unlock(adapter);
470 /* big hammer don't reset CAM block on reset */
471 QLCWR32(adapter, QLCNIC_ROMUSB_GLB_SW_RESET, 0xfeffffff);
428 472
429 /* Init HW CRB block */ 473 /* Init HW CRB block */
430 if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) || 474 if (qlcnic_rom_fast_read(adapter, 0, &n) != 0 || (n != 0xcafecafe) ||
@@ -522,8 +566,10 @@ int qlcnic_pinit_from_rom(struct qlcnic_adapter *adapter)
522 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x8, 0); 566 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0x8, 0);
523 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0xc, 0); 567 QLCWR32(adapter, QLCNIC_CRB_PEG_NET_4 + 0xc, 0);
524 msleep(1); 568 msleep(1);
569
525 QLCWR32(adapter, QLCNIC_PEG_HALT_STATUS1, 0); 570 QLCWR32(adapter, QLCNIC_PEG_HALT_STATUS1, 0);
526 QLCWR32(adapter, QLCNIC_PEG_HALT_STATUS2, 0); 571 QLCWR32(adapter, QLCNIC_PEG_HALT_STATUS2, 0);
572
527 return 0; 573 return 0;
528} 574}
529 575
diff --git a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
index 106503f118f6..0bd163828e33 100644
--- a/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
+++ b/drivers/net/ethernet/qlogic/qlcnic/qlcnic_main.c
@@ -2840,8 +2840,15 @@ qlcnic_fwinit_work(struct work_struct *work)
2840 goto wait_npar; 2840 goto wait_npar;
2841 } 2841 }
2842 2842
2843 if (dev_state == QLCNIC_DEV_INITIALIZING ||
2844 dev_state == QLCNIC_DEV_READY) {
2845 dev_info(&adapter->pdev->dev, "Detected state change from "
2846 "DEV_NEED_RESET, skipping ack check\n");
2847 goto skip_ack_check;
2848 }
2849
2843 if (adapter->fw_wait_cnt++ > adapter->reset_ack_timeo) { 2850 if (adapter->fw_wait_cnt++ > adapter->reset_ack_timeo) {
2844 dev_err(&adapter->pdev->dev, "Reset:Failed to get ack %d sec\n", 2851 dev_info(&adapter->pdev->dev, "Reset:Failed to get ack %d sec\n",
2845 adapter->reset_ack_timeo); 2852 adapter->reset_ack_timeo);
2846 goto skip_ack_check; 2853 goto skip_ack_check;
2847 } 2854 }
@@ -3497,11 +3504,16 @@ qlcnic_store_beacon(struct device *dev,
3497{ 3504{
3498 struct qlcnic_adapter *adapter = dev_get_drvdata(dev); 3505 struct qlcnic_adapter *adapter = dev_get_drvdata(dev);
3499 int max_sds_rings = adapter->max_sds_rings; 3506 int max_sds_rings = adapter->max_sds_rings;
3500 int dev_down = 0;
3501 u16 beacon; 3507 u16 beacon;
3502 u8 b_state, b_rate; 3508 u8 b_state, b_rate;
3503 int err; 3509 int err;
3504 3510
3511 if (adapter->op_mode == QLCNIC_NON_PRIV_FUNC) {
3512 dev_warn(dev, "LED test not supported for non "
3513 "privilege function\n");
3514 return -EOPNOTSUPP;
3515 }
3516
3505 if (len != sizeof(u16)) 3517 if (len != sizeof(u16))
3506 return QL_STATUS_INVALID_PARAM; 3518 return QL_STATUS_INVALID_PARAM;
3507 3519
@@ -3513,36 +3525,40 @@ qlcnic_store_beacon(struct device *dev,
3513 if (adapter->ahw->beacon_state == b_state) 3525 if (adapter->ahw->beacon_state == b_state)
3514 return len; 3526 return len;
3515 3527
3528 rtnl_lock();
3529
3516 if (!adapter->ahw->beacon_state) 3530 if (!adapter->ahw->beacon_state)
3517 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state)) 3531 if (test_and_set_bit(__QLCNIC_LED_ENABLE, &adapter->state)) {
3532 rtnl_unlock();
3518 return -EBUSY; 3533 return -EBUSY;
3534 }
3535
3536 if (test_bit(__QLCNIC_RESETTING, &adapter->state)) {
3537 err = -EIO;
3538 goto out;
3539 }
3519 3540
3520 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) { 3541 if (!test_bit(__QLCNIC_DEV_UP, &adapter->state)) {
3521 if (test_and_set_bit(__QLCNIC_RESETTING, &adapter->state))
3522 return -EIO;
3523 err = qlcnic_diag_alloc_res(adapter->netdev, QLCNIC_LED_TEST); 3542 err = qlcnic_diag_alloc_res(adapter->netdev, QLCNIC_LED_TEST);
3524 if (err) { 3543 if (err)
3525 clear_bit(__QLCNIC_RESETTING, &adapter->state); 3544 goto out;
3526 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state); 3545 set_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state);
3527 return err;
3528 }
3529 dev_down = 1;
3530 } 3546 }
3531 3547
3532 err = qlcnic_config_led(adapter, b_state, b_rate); 3548 err = qlcnic_config_led(adapter, b_state, b_rate);
3533 3549
3534 if (!err) { 3550 if (!err) {
3535 adapter->ahw->beacon_state = b_state;
3536 err = len; 3551 err = len;
3552 adapter->ahw->beacon_state = b_state;
3537 } 3553 }
3538 3554
3539 if (dev_down) { 3555 if (test_and_clear_bit(__QLCNIC_DIAG_RES_ALLOC, &adapter->state))
3540 qlcnic_diag_free_res(adapter->netdev, max_sds_rings); 3556 qlcnic_diag_free_res(adapter->netdev, max_sds_rings);
3541 clear_bit(__QLCNIC_RESETTING, &adapter->state);
3542 }
3543 3557
3544 if (!b_state) 3558 out:
3559 if (!adapter->ahw->beacon_state)
3545 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state); 3560 clear_bit(__QLCNIC_LED_ENABLE, &adapter->state);
3561 rtnl_unlock();
3546 3562
3547 return err; 3563 return err;
3548} 3564}
diff --git a/drivers/net/ethernet/stmicro/stmmac/common.h b/drivers/net/ethernet/stmicro/stmmac/common.h
index 9100c100d295..2cc119295821 100644
--- a/drivers/net/ethernet/stmicro/stmmac/common.h
+++ b/drivers/net/ethernet/stmicro/stmmac/common.h
@@ -49,7 +49,7 @@ struct stmmac_extra_stats {
49 unsigned long tx_underflow ____cacheline_aligned; 49 unsigned long tx_underflow ____cacheline_aligned;
50 unsigned long tx_carrier; 50 unsigned long tx_carrier;
51 unsigned long tx_losscarrier; 51 unsigned long tx_losscarrier;
52 unsigned long tx_heartbeat; 52 unsigned long vlan_tag;
53 unsigned long tx_deferred; 53 unsigned long tx_deferred;
54 unsigned long tx_vlan; 54 unsigned long tx_vlan;
55 unsigned long tx_jabber; 55 unsigned long tx_jabber;
@@ -58,9 +58,9 @@ struct stmmac_extra_stats {
58 unsigned long tx_ip_header_error; 58 unsigned long tx_ip_header_error;
59 /* Receive errors */ 59 /* Receive errors */
60 unsigned long rx_desc; 60 unsigned long rx_desc;
61 unsigned long rx_partial; 61 unsigned long sa_filter_fail;
62 unsigned long rx_runt; 62 unsigned long overflow_error;
63 unsigned long rx_toolong; 63 unsigned long ipc_csum_error;
64 unsigned long rx_collision; 64 unsigned long rx_collision;
65 unsigned long rx_crc; 65 unsigned long rx_crc;
66 unsigned long rx_length; 66 unsigned long rx_length;
diff --git a/drivers/net/ethernet/stmicro/stmmac/descs.h b/drivers/net/ethernet/stmicro/stmmac/descs.h
index 63a03e264694..9820ec842cc0 100644
--- a/drivers/net/ethernet/stmicro/stmmac/descs.h
+++ b/drivers/net/ethernet/stmicro/stmmac/descs.h
@@ -25,33 +25,34 @@ struct dma_desc {
25 union { 25 union {
26 struct { 26 struct {
27 /* RDES0 */ 27 /* RDES0 */
28 u32 reserved1:1; 28 u32 payload_csum_error:1;
29 u32 crc_error:1; 29 u32 crc_error:1;
30 u32 dribbling:1; 30 u32 dribbling:1;
31 u32 mii_error:1; 31 u32 mii_error:1;
32 u32 receive_watchdog:1; 32 u32 receive_watchdog:1;
33 u32 frame_type:1; 33 u32 frame_type:1;
34 u32 collision:1; 34 u32 collision:1;
35 u32 frame_too_long:1; 35 u32 ipc_csum_error:1;
36 u32 last_descriptor:1; 36 u32 last_descriptor:1;
37 u32 first_descriptor:1; 37 u32 first_descriptor:1;
38 u32 multicast_frame:1; 38 u32 vlan_tag:1;
39 u32 run_frame:1; 39 u32 overflow_error:1;
40 u32 length_error:1; 40 u32 length_error:1;
41 u32 partial_frame_error:1; 41 u32 sa_filter_fail:1;
42 u32 descriptor_error:1; 42 u32 descriptor_error:1;
43 u32 error_summary:1; 43 u32 error_summary:1;
44 u32 frame_length:14; 44 u32 frame_length:14;
45 u32 filtering_fail:1; 45 u32 da_filter_fail:1;
46 u32 own:1; 46 u32 own:1;
47 /* RDES1 */ 47 /* RDES1 */
48 u32 buffer1_size:11; 48 u32 buffer1_size:11;
49 u32 buffer2_size:11; 49 u32 buffer2_size:11;
50 u32 reserved2:2; 50 u32 reserved1:2;
51 u32 second_address_chained:1; 51 u32 second_address_chained:1;
52 u32 end_ring:1; 52 u32 end_ring:1;
53 u32 reserved3:5; 53 u32 reserved2:5;
54 u32 disable_ic:1; 54 u32 disable_ic:1;
55
55 } rx; 56 } rx;
56 struct { 57 struct {
57 /* RDES0 */ 58 /* RDES0 */
@@ -91,24 +92,28 @@ struct dma_desc {
91 u32 underflow_error:1; 92 u32 underflow_error:1;
92 u32 excessive_deferral:1; 93 u32 excessive_deferral:1;
93 u32 collision_count:4; 94 u32 collision_count:4;
94 u32 heartbeat_fail:1; 95 u32 vlan_frame:1;
95 u32 excessive_collisions:1; 96 u32 excessive_collisions:1;
96 u32 late_collision:1; 97 u32 late_collision:1;
97 u32 no_carrier:1; 98 u32 no_carrier:1;
98 u32 loss_carrier:1; 99 u32 loss_carrier:1;
99 u32 reserved1:3; 100 u32 payload_error:1;
101 u32 frame_flushed:1;
102 u32 jabber_timeout:1;
100 u32 error_summary:1; 103 u32 error_summary:1;
101 u32 reserved2:15; 104 u32 ip_header_error:1;
105 u32 time_stamp_status:1;
106 u32 reserved1:13;
102 u32 own:1; 107 u32 own:1;
103 /* TDES1 */ 108 /* TDES1 */
104 u32 buffer1_size:11; 109 u32 buffer1_size:11;
105 u32 buffer2_size:11; 110 u32 buffer2_size:11;
106 u32 reserved3:1; 111 u32 time_stamp_enable:1;
107 u32 disable_padding:1; 112 u32 disable_padding:1;
108 u32 second_address_chained:1; 113 u32 second_address_chained:1;
109 u32 end_ring:1; 114 u32 end_ring:1;
110 u32 crc_disable:1; 115 u32 crc_disable:1;
111 u32 reserved4:2; 116 u32 checksum_insertion:2;
112 u32 first_segment:1; 117 u32 first_segment:1;
113 u32 last_segment:1; 118 u32 last_segment:1;
114 u32 interrupt:1; 119 u32 interrupt:1;
diff --git a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
index f7e8ba7f501a..fda5d2b31d3a 100644
--- a/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
+++ b/drivers/net/ethernet/stmicro/stmmac/norm_desc.c
@@ -50,11 +50,12 @@ static int ndesc_get_tx_status(void *data, struct stmmac_extra_stats *x,
50 stats->collisions += p->des01.tx.collision_count; 50 stats->collisions += p->des01.tx.collision_count;
51 ret = -1; 51 ret = -1;
52 } 52 }
53 if (unlikely(p->des01.tx.heartbeat_fail)) { 53
54 x->tx_heartbeat++; 54 if (p->des01.etx.vlan_frame) {
55 stats->tx_heartbeat_errors++; 55 CHIP_DBG(KERN_INFO "GMAC TX status: VLAN frame\n");
56 ret = -1; 56 x->tx_vlan++;
57 } 57 }
58
58 if (unlikely(p->des01.tx.deferred)) 59 if (unlikely(p->des01.tx.deferred))
59 x->tx_deferred++; 60 x->tx_deferred++;
60 61
@@ -68,12 +69,12 @@ static int ndesc_get_tx_len(struct dma_desc *p)
68 69
69/* This function verifies if each incoming frame has some errors 70/* This function verifies if each incoming frame has some errors
70 * and, if required, updates the multicast statistics. 71 * and, if required, updates the multicast statistics.
71 * In case of success, it returns csum_none because the device 72 * In case of success, it returns good_frame because the GMAC device
72 * is not able to compute the csum in HW. */ 73 * is supposed to be able to compute the csum in HW. */
73static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x, 74static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
74 struct dma_desc *p) 75 struct dma_desc *p)
75{ 76{
76 int ret = csum_none; 77 int ret = good_frame;
77 struct net_device_stats *stats = (struct net_device_stats *)data; 78 struct net_device_stats *stats = (struct net_device_stats *)data;
78 79
79 if (unlikely(p->des01.rx.last_descriptor == 0)) { 80 if (unlikely(p->des01.rx.last_descriptor == 0)) {
@@ -86,12 +87,12 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
86 if (unlikely(p->des01.rx.error_summary)) { 87 if (unlikely(p->des01.rx.error_summary)) {
87 if (unlikely(p->des01.rx.descriptor_error)) 88 if (unlikely(p->des01.rx.descriptor_error))
88 x->rx_desc++; 89 x->rx_desc++;
89 if (unlikely(p->des01.rx.partial_frame_error)) 90 if (unlikely(p->des01.rx.sa_filter_fail))
90 x->rx_partial++; 91 x->sa_filter_fail++;
91 if (unlikely(p->des01.rx.run_frame)) 92 if (unlikely(p->des01.rx.overflow_error))
92 x->rx_runt++; 93 x->overflow_error++;
93 if (unlikely(p->des01.rx.frame_too_long)) 94 if (unlikely(p->des01.rx.ipc_csum_error))
94 x->rx_toolong++; 95 x->ipc_csum_error++;
95 if (unlikely(p->des01.rx.collision)) { 96 if (unlikely(p->des01.rx.collision)) {
96 x->rx_collision++; 97 x->rx_collision++;
97 stats->collisions++; 98 stats->collisions++;
@@ -113,10 +114,10 @@ static int ndesc_get_rx_status(void *data, struct stmmac_extra_stats *x,
113 x->rx_mii++; 114 x->rx_mii++;
114 ret = discard_frame; 115 ret = discard_frame;
115 } 116 }
116 if (p->des01.rx.multicast_frame) { 117#ifdef STMMAC_VLAN_TAG_USED
117 x->rx_multicast++; 118 if (p->des01.rx.vlan_tag)
118 stats->multicast++; 119 x->vlan_tag++;
119 } 120#endif
120 return ret; 121 return ret;
121} 122}
122 123
@@ -184,6 +185,9 @@ static void ndesc_prepare_tx_desc(struct dma_desc *p, int is_fs, int len,
184{ 185{
185 p->des01.tx.first_segment = is_fs; 186 p->des01.tx.first_segment = is_fs;
186 norm_set_tx_desc_len(p, len); 187 norm_set_tx_desc_len(p, len);
188
189 if (likely(csum_flag))
190 p->des01.tx.checksum_insertion = cic_full;
187} 191}
188 192
189static void ndesc_clear_tx_ic(struct dma_desc *p) 193static void ndesc_clear_tx_ic(struct dma_desc *p)
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
index 406404f6e321..e8eff09bbbd7 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_ethtool.c
@@ -50,7 +50,7 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
50 STMMAC_STAT(tx_underflow), 50 STMMAC_STAT(tx_underflow),
51 STMMAC_STAT(tx_carrier), 51 STMMAC_STAT(tx_carrier),
52 STMMAC_STAT(tx_losscarrier), 52 STMMAC_STAT(tx_losscarrier),
53 STMMAC_STAT(tx_heartbeat), 53 STMMAC_STAT(vlan_tag),
54 STMMAC_STAT(tx_deferred), 54 STMMAC_STAT(tx_deferred),
55 STMMAC_STAT(tx_vlan), 55 STMMAC_STAT(tx_vlan),
56 STMMAC_STAT(rx_vlan), 56 STMMAC_STAT(rx_vlan),
@@ -59,9 +59,9 @@ static const struct stmmac_stats stmmac_gstrings_stats[] = {
59 STMMAC_STAT(tx_payload_error), 59 STMMAC_STAT(tx_payload_error),
60 STMMAC_STAT(tx_ip_header_error), 60 STMMAC_STAT(tx_ip_header_error),
61 STMMAC_STAT(rx_desc), 61 STMMAC_STAT(rx_desc),
62 STMMAC_STAT(rx_partial), 62 STMMAC_STAT(sa_filter_fail),
63 STMMAC_STAT(rx_runt), 63 STMMAC_STAT(overflow_error),
64 STMMAC_STAT(rx_toolong), 64 STMMAC_STAT(ipc_csum_error),
65 STMMAC_STAT(rx_collision), 65 STMMAC_STAT(rx_collision),
66 STMMAC_STAT(rx_crc), 66 STMMAC_STAT(rx_crc),
67 STMMAC_STAT(rx_length), 67 STMMAC_STAT(rx_length),
diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index aeaa15b451de..20546bbbb8db 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -325,7 +325,7 @@ static int stmmac_init_phy(struct net_device *dev)
325 (interface == PHY_INTERFACE_MODE_RMII))) { 325 (interface == PHY_INTERFACE_MODE_RMII))) {
326 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause | 326 phydev->supported &= (PHY_BASIC_FEATURES | SUPPORTED_Pause |
327 SUPPORTED_Asym_Pause); 327 SUPPORTED_Asym_Pause);
328 priv->phydev->advertising = priv->phydev->supported; 328 phydev->advertising = phydev->supported;
329 } 329 }
330 330
331 /* 331 /*
@@ -812,9 +812,11 @@ static u32 stmmac_get_synopsys_id(struct stmmac_priv *priv)
812 */ 812 */
813static int stmmac_get_hw_features(struct stmmac_priv *priv) 813static int stmmac_get_hw_features(struct stmmac_priv *priv)
814{ 814{
815 u32 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr); 815 u32 hw_cap = 0;
816
817 if (priv->hw->dma->get_hw_feature) {
818 hw_cap = priv->hw->dma->get_hw_feature(priv->ioaddr);
816 819
817 if (likely(hw_cap)) {
818 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL); 820 priv->dma_cap.mbps_10_100 = (hw_cap & DMA_HW_FEAT_MIISEL);
819 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1; 821 priv->dma_cap.mbps_1000 = (hw_cap & DMA_HW_FEAT_GMIISEL) >> 1;
820 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2; 822 priv->dma_cap.half_duplex = (hw_cap & DMA_HW_FEAT_HDSEL) >> 2;
@@ -937,6 +939,7 @@ static int stmmac_open(struct net_device *dev)
937 939
938 stmmac_get_hw_features(priv); 940 stmmac_get_hw_features(priv);
939 941
942 priv->rx_coe = priv->hw->mac->rx_coe(priv->ioaddr);
940 if (priv->rx_coe) 943 if (priv->rx_coe)
941 pr_info("stmmac: Rx Checksum Offload Engine supported\n"); 944 pr_info("stmmac: Rx Checksum Offload Engine supported\n");
942 if (priv->plat->tx_coe) 945 if (priv->plat->tx_coe)
@@ -1274,8 +1277,8 @@ static int stmmac_rx(struct stmmac_priv *priv, int limit)
1274#endif 1277#endif
1275 skb->protocol = eth_type_trans(skb, priv->dev); 1278 skb->protocol = eth_type_trans(skb, priv->dev);
1276 1279
1277 if (unlikely(status == csum_none)) { 1280 if (unlikely(!priv->rx_coe)) {
1278 /* always for the old mac 10/100 */ 1281 /* No RX COE for old mac10/100 devices */
1279 skb_checksum_none_assert(skb); 1282 skb_checksum_none_assert(skb);
1280 netif_receive_skb(skb); 1283 netif_receive_skb(skb);
1281 } else { 1284 } else {
generated by cgit v1.2.2 (git 2.25.0) at 2025-12-26 22:42:00 -0500