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-rw-r--r--drivers/net/arm/at91_ether.c45
-rw-r--r--drivers/net/arm/at91_ether.h49
2 files changed, 73 insertions, 21 deletions
diff --git a/drivers/net/arm/at91_ether.c b/drivers/net/arm/at91_ether.c
index 152fa7a042b8..b9cb5cb4d97f 100644
--- a/drivers/net/arm/at91_ether.c
+++ b/drivers/net/arm/at91_ether.c
@@ -225,6 +225,16 @@ static irqreturn_t at91ether_phy_interrupt(int irq, void *dev_id)
225 if (!(phy & ((1 << 2) | 1))) 225 if (!(phy & ((1 << 2) | 1)))
226 goto done; 226 goto done;
227 } 227 }
228 else if (lp->phy_type == MII_T78Q21x3_ID) { /* ack interrupt in Teridian PHY */
229 read_phy(lp->phy_address, MII_T78Q21INT_REG, &phy);
230 if (!(phy & ((1 << 2) | 1)))
231 goto done;
232 }
233 else if (lp->phy_type == MII_DP83848_ID) {
234 read_phy(lp->phy_address, MII_DPPHYSTS_REG, &phy); /* ack interrupt in DP83848 PHY */
235 if (!(phy & (1 << 7)))
236 goto done;
237 }
228 238
229 update_linkspeed(dev, 0); 239 update_linkspeed(dev, 0);
230 240
@@ -280,6 +290,19 @@ static void enable_phyirq(struct net_device *dev)
280 dsintr = (1 << 10) | ( 1 << 8); 290 dsintr = (1 << 10) | ( 1 << 8);
281 write_phy(lp->phy_address, MII_TPISTATUS, dsintr); 291 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
282 } 292 }
293 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
294 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
295 dsintr = dsintr | 0x500; /* set bits 8, 10 */
296 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
297 }
298 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
299 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
300 dsintr = dsintr | 0x3c; /* set bits 2..5 */
301 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
302 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
303 dsintr = dsintr | 0x3; /* set bits 0,1 */
304 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
305 }
283 306
284 disable_mdi(); 307 disable_mdi();
285 spin_unlock_irq(&lp->lock); 308 spin_unlock_irq(&lp->lock);
@@ -323,6 +346,19 @@ static void disable_phyirq(struct net_device *dev)
323 dsintr = ~((1 << 10) | (1 << 8)); 346 dsintr = ~((1 << 10) | (1 << 8));
324 write_phy(lp->phy_address, MII_TPISTATUS, dsintr); 347 write_phy(lp->phy_address, MII_TPISTATUS, dsintr);
325 } 348 }
349 else if (lp->phy_type == MII_T78Q21x3_ID) { /* for Teridian PHY */
350 read_phy(lp->phy_address, MII_T78Q21INT_REG, &dsintr);
351 dsintr = dsintr & ~0x500; /* clear bits 8, 10 */
352 write_phy(lp->phy_address, MII_T78Q21INT_REG, dsintr);
353 }
354 else if (lp->phy_type == MII_DP83848_ID) { /* National Semiconductor DP83848 PHY */
355 read_phy(lp->phy_address, MII_DPMICR_REG, &dsintr);
356 dsintr = dsintr & ~0x3; /* clear bits 0, 1 */
357 write_phy(lp->phy_address, MII_DPMICR_REG, dsintr);
358 read_phy(lp->phy_address, MII_DPMISR_REG, &dsintr);
359 dsintr = dsintr & ~0x3c; /* clear bits 2..5 */
360 write_phy(lp->phy_address, MII_DPMISR_REG, dsintr);
361 }
326 362
327 disable_mdi(); 363 disable_mdi();
328 spin_unlock_irq(&lp->lock); 364 spin_unlock_irq(&lp->lock);
@@ -1062,10 +1098,16 @@ static int __init at91ether_setup(unsigned long phy_type, unsigned short phy_add
1062 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name); 1098 printk(KERN_INFO "%s: Broadcom BCM5221 PHY\n", dev->name);
1063 else if (phy_type == MII_DP83847_ID) 1099 else if (phy_type == MII_DP83847_ID)
1064 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name); 1100 printk(KERN_INFO "%s: National Semiconductor DP83847 PHY\n", dev->name);
1101 else if (phy_type == MII_DP83848_ID)
1102 printk(KERN_INFO "%s: National Semiconductor DP83848 PHY\n", dev->name);
1065 else if (phy_type == MII_AC101L_ID) 1103 else if (phy_type == MII_AC101L_ID)
1066 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name); 1104 printk(KERN_INFO "%s: Altima AC101L PHY\n", dev->name);
1067 else if (phy_type == MII_KS8721_ID) 1105 else if (phy_type == MII_KS8721_ID)
1068 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name); 1106 printk(KERN_INFO "%s: Micrel KS8721 PHY\n", dev->name);
1107 else if (phy_type == MII_T78Q21x3_ID)
1108 printk(KERN_INFO "%s: Teridian 78Q21x3 PHY\n", dev->name);
1109 else if (phy_type == MII_LAN83C185_ID)
1110 printk(KERN_INFO "%s: SMSC LAN83C185 PHY\n", dev->name);
1069 1111
1070 return 0; 1112 return 0;
1071} 1113}
@@ -1103,8 +1145,11 @@ static int __init at91ether_probe(struct platform_device *pdev)
1103 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */ 1145 case MII_RTL8201_ID: /* Realtek RTL8201: PHY_ID1 = 0, PHY_ID2 = 0x8201 */
1104 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */ 1146 case MII_BCM5221_ID: /* Broadcom BCM5221: PHY_ID1 = 0x40, PHY_ID2 = 0x61e0 */
1105 case MII_DP83847_ID: /* National Semiconductor DP83847: */ 1147 case MII_DP83847_ID: /* National Semiconductor DP83847: */
1148 case MII_DP83848_ID: /* National Semiconductor DP83848: */
1106 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */ 1149 case MII_AC101L_ID: /* Altima AC101L: PHY_ID1 = 0x22, PHY_ID2 = 0x5520 */
1107 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */ 1150 case MII_KS8721_ID: /* Micrel KS8721: PHY_ID1 = 0x22, PHY_ID2 = 0x1610 */
1151 case MII_T78Q21x3_ID: /* Teridian 78Q21x3: PHY_ID1 = 0x0E, PHY_ID2 = 7237 */
1152 case MII_LAN83C185_ID: /* SMSC LAN83C185: PHY_ID1 = 0x0007, PHY_ID2 = 0xC0A1 */
1108 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk); 1153 detected = at91ether_setup(phy_id, phy_address, pdev, ether_clk);
1109 break; 1154 break;
1110 } 1155 }
diff --git a/drivers/net/arm/at91_ether.h b/drivers/net/arm/at91_ether.h
index b6b665de2ea0..a38fd2d053a6 100644
--- a/drivers/net/arm/at91_ether.h
+++ b/drivers/net/arm/at91_ether.h
@@ -17,39 +17,46 @@
17 17
18 18
19/* Davicom 9161 PHY */ 19/* Davicom 9161 PHY */
20#define MII_DM9161_ID 0x0181b880 20#define MII_DM9161_ID 0x0181b880
21#define MII_DM9161A_ID 0x0181b8a0 21#define MII_DM9161A_ID 0x0181b8a0
22 22#define MII_DSCR_REG 16
23/* Davicom specific registers */ 23#define MII_DSCSR_REG 17
24#define MII_DSCR_REG 16 24#define MII_DSINTR_REG 21
25#define MII_DSCSR_REG 17
26#define MII_DSINTR_REG 21
27 25
28/* Intel LXT971A PHY */ 26/* Intel LXT971A PHY */
29#define MII_LXT971A_ID 0x001378E0 27#define MII_LXT971A_ID 0x001378E0
30 28#define MII_ISINTE_REG 18
31/* Intel specific registers */ 29#define MII_ISINTS_REG 19
32#define MII_ISINTE_REG 18 30#define MII_LEDCTRL_REG 20
33#define MII_ISINTS_REG 19
34#define MII_LEDCTRL_REG 20
35 31
36/* Realtek RTL8201 PHY */ 32/* Realtek RTL8201 PHY */
37#define MII_RTL8201_ID 0x00008200 33#define MII_RTL8201_ID 0x00008200
38 34
39/* Broadcom BCM5221 PHY */ 35/* Broadcom BCM5221 PHY */
40#define MII_BCM5221_ID 0x004061e0 36#define MII_BCM5221_ID 0x004061e0
41 37#define MII_BCMINTR_REG 26
42/* Broadcom specific registers */
43#define MII_BCMINTR_REG 26
44 38
45/* National Semiconductor DP83847 */ 39/* National Semiconductor DP83847 */
46#define MII_DP83847_ID 0x20005c30 40#define MII_DP83847_ID 0x20005c30
41
42/* National Semiconductor DP83848 */
43#define MII_DP83848_ID 0x20005c90
44#define MII_DPPHYSTS_REG 16
45#define MII_DPMICR_REG 17
46#define MII_DPMISR_REG 18
47 47
48/* Altima AC101L PHY */ 48/* Altima AC101L PHY */
49#define MII_AC101L_ID 0x00225520 49#define MII_AC101L_ID 0x00225520
50 50
51/* Micrel KS8721 PHY */ 51/* Micrel KS8721 PHY */
52#define MII_KS8721_ID 0x00221610 52#define MII_KS8721_ID 0x00221610
53
54/* Teridian 78Q2123/78Q2133 */
55#define MII_T78Q21x3_ID 0x000e7230
56#define MII_T78Q21INT_REG 17
57
58/* SMSC LAN83C185 */
59#define MII_LAN83C185_ID 0x0007C0A0
53 60
54/* ........................................................................ */ 61/* ........................................................................ */
55 62