diff options
Diffstat (limited to 'drivers')
-rw-r--r-- | drivers/usb/phy/phy-tegra-usb.c | 20 |
1 files changed, 14 insertions, 6 deletions
diff --git a/drivers/usb/phy/phy-tegra-usb.c b/drivers/usb/phy/phy-tegra-usb.c index 49fa2da56c4b..ebbf85fdfc7f 100644 --- a/drivers/usb/phy/phy-tegra-usb.c +++ b/drivers/usb/phy/phy-tegra-usb.c | |||
@@ -86,11 +86,13 @@ | |||
86 | 86 | ||
87 | #define UTMIP_XCVR_CFG0 0x808 | 87 | #define UTMIP_XCVR_CFG0 0x808 |
88 | #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) | 88 | #define UTMIP_XCVR_SETUP(x) (((x) & 0xf) << 0) |
89 | #define UTMIP_XCVR_SETUP_MSB(x) ((((x) & 0x70) >> 4) << 22) | ||
89 | #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) | 90 | #define UTMIP_XCVR_LSRSLEW(x) (((x) & 0x3) << 8) |
90 | #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) | 91 | #define UTMIP_XCVR_LSFSLEW(x) (((x) & 0x3) << 10) |
91 | #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) | 92 | #define UTMIP_FORCE_PD_POWERDOWN (1 << 14) |
92 | #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) | 93 | #define UTMIP_FORCE_PD2_POWERDOWN (1 << 16) |
93 | #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) | 94 | #define UTMIP_FORCE_PDZI_POWERDOWN (1 << 18) |
95 | #define UTMIP_XCVR_LSBIAS_SEL (1 << 21) | ||
94 | #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) | 96 | #define UTMIP_XCVR_HSSLEW_MSB(x) (((x) & 0x7f) << 25) |
95 | 97 | ||
96 | #define UTMIP_BIAS_CFG0 0x80c | 98 | #define UTMIP_BIAS_CFG0 0x80c |
@@ -342,7 +344,7 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) | |||
342 | } | 344 | } |
343 | 345 | ||
344 | val = readl(base + UTMIP_TX_CFG0); | 346 | val = readl(base + UTMIP_TX_CFG0); |
345 | val &= ~UTMIP_FS_PREABMLE_J; | 347 | val |= UTMIP_FS_PREABMLE_J; |
346 | writel(val, base + UTMIP_TX_CFG0); | 348 | writel(val, base + UTMIP_TX_CFG0); |
347 | 349 | ||
348 | val = readl(base + UTMIP_HSRX_CFG0); | 350 | val = readl(base + UTMIP_HSRX_CFG0); |
@@ -381,16 +383,26 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) | |||
381 | val = readl(base + USB_SUSP_CTRL); | 383 | val = readl(base + USB_SUSP_CTRL); |
382 | val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); | 384 | val &= ~(USB_WAKE_ON_CNNT_EN_DEV | USB_WAKE_ON_DISCON_EN_DEV); |
383 | writel(val, base + USB_SUSP_CTRL); | 385 | writel(val, base + USB_SUSP_CTRL); |
386 | |||
387 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | ||
388 | val &= ~UTMIP_PD_CHRG; | ||
389 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | ||
390 | } else { | ||
391 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | ||
392 | val |= UTMIP_PD_CHRG; | ||
393 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | ||
384 | } | 394 | } |
385 | 395 | ||
386 | utmip_pad_power_on(phy); | 396 | utmip_pad_power_on(phy); |
387 | 397 | ||
388 | val = readl(base + UTMIP_XCVR_CFG0); | 398 | val = readl(base + UTMIP_XCVR_CFG0); |
389 | val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | | 399 | val &= ~(UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | |
390 | UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_SETUP(~0) | | 400 | UTMIP_FORCE_PDZI_POWERDOWN | UTMIP_XCVR_LSBIAS_SEL | |
401 | UTMIP_XCVR_SETUP(~0) | UTMIP_XCVR_SETUP_MSB(~0) | | ||
391 | UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | | 402 | UTMIP_XCVR_LSFSLEW(~0) | UTMIP_XCVR_LSRSLEW(~0) | |
392 | UTMIP_XCVR_HSSLEW_MSB(~0)); | 403 | UTMIP_XCVR_HSSLEW_MSB(~0)); |
393 | val |= UTMIP_XCVR_SETUP(config->xcvr_setup); | 404 | val |= UTMIP_XCVR_SETUP(config->xcvr_setup); |
405 | val |= UTMIP_XCVR_SETUP_MSB(config->xcvr_setup); | ||
394 | val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); | 406 | val |= UTMIP_XCVR_LSFSLEW(config->xcvr_lsfslew); |
395 | val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); | 407 | val |= UTMIP_XCVR_LSRSLEW(config->xcvr_lsrslew); |
396 | writel(val, base + UTMIP_XCVR_CFG0); | 408 | writel(val, base + UTMIP_XCVR_CFG0); |
@@ -401,10 +413,6 @@ static int utmi_phy_power_on(struct tegra_usb_phy *phy) | |||
401 | val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); | 413 | val |= UTMIP_XCVR_TERM_RANGE_ADJ(config->term_range_adj); |
402 | writel(val, base + UTMIP_XCVR_CFG1); | 414 | writel(val, base + UTMIP_XCVR_CFG1); |
403 | 415 | ||
404 | val = readl(base + UTMIP_BAT_CHRG_CFG0); | ||
405 | val &= ~UTMIP_PD_CHRG; | ||
406 | writel(val, base + UTMIP_BAT_CHRG_CFG0); | ||
407 | |||
408 | val = readl(base + UTMIP_BIAS_CFG1); | 416 | val = readl(base + UTMIP_BIAS_CFG1); |
409 | val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); | 417 | val &= ~UTMIP_BIAS_PDTRK_COUNT(~0); |
410 | val |= UTMIP_BIAS_PDTRK_COUNT(0x5); | 418 | val |= UTMIP_BIAS_PDTRK_COUNT(0x5); |