10 files changed, 163 insertions, 153 deletions

diff --git a/drivers/acpi/processor_idle.c b/drivers/acpi/processor_idle.c
index 2e69e09ff03e..9b88f9828d8c 100644
--- a/drivers/acpi/processor_idle.c
+++ b/drivers/acpi/processor_idle.c
@@ -852,7 +852,7 @@ static int acpi_idle_enter_simple(struct cpuidle_device *dev,
 }
 
 static int c3_cpu_count;
-static DEFINE_SPINLOCK(c3_lock);
+static DEFINE_RAW_SPINLOCK(c3_lock);
 
 /**
  * acpi_idle_enter_bm - enters C3 with proper BM handling
@@ -930,12 +930,12 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
          * without doing anything.
          */
         if (pr->flags.bm_check && pr->flags.bm_control) {
-                spin_lock(&c3_lock);
+                raw_spin_lock(&c3_lock);
                 c3_cpu_count++;
                 /* Disable bus master arbitration when all CPUs are in C3 */
                 if (c3_cpu_count == num_online_cpus())
                         acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 1);
-                spin_unlock(&c3_lock);
+                raw_spin_unlock(&c3_lock);
         } else if (!pr->flags.bm_check) {
                 ACPI_FLUSH_CPU_CACHE();
         }
@@ -944,10 +944,10 @@ static int acpi_idle_enter_bm(struct cpuidle_device *dev,
 
         /* Re-enable bus master arbitration */
         if (pr->flags.bm_check && pr->flags.bm_control) {
-                spin_lock(&c3_lock);
+                raw_spin_lock(&c3_lock);
                 acpi_write_bit_register(ACPI_BITREG_ARB_DISABLE, 0);
                 c3_cpu_count--;
-                spin_unlock(&c3_lock);
+                raw_spin_unlock(&c3_lock);
         }
         kt2 = ktime_get_real();
         idle_time_ns = ktime_to_ns(ktime_sub(kt2, kt1));
diff --git a/drivers/dca/dca-core.c b/drivers/dca/dca-core.c
index 4abd089a094f..25ec0bb05198 100644
--- a/drivers/dca/dca-core.c
+++ b/drivers/dca/dca-core.c
@@ -35,7 +35,7 @@ MODULE_VERSION(DCA_VERSION);
 MODULE_LICENSE("GPL");
 MODULE_AUTHOR("Intel Corporation");
 
-static DEFINE_SPINLOCK(dca_lock);
+static DEFINE_RAW_SPINLOCK(dca_lock);
 
 static LIST_HEAD(dca_domains);
 
@@ -101,10 +101,10 @@ static void unregister_dca_providers(void)
 
         INIT_LIST_HEAD(&unregistered_providers);
 
-        spin_lock_irqsave(&dca_lock, flags);
+        raw_spin_lock_irqsave(&dca_lock, flags);
 
         if (list_empty(&dca_domains)) {
-                spin_unlock_irqrestore(&dca_lock, flags);
+                raw_spin_unlock_irqrestore(&dca_lock, flags);
                 return;
         }
 
@@ -116,7 +116,7 @@ static void unregister_dca_providers(void)
 
         dca_free_domain(domain);
 
-        spin_unlock_irqrestore(&dca_lock, flags);
+        raw_spin_unlock_irqrestore(&dca_lock, flags);
 
         list_for_each_entry_safe(dca, _dca, &unregistered_providers, node) {
                 dca_sysfs_remove_provider(dca);
@@ -144,13 +144,8 @@ static struct dca_domain *dca_get_domain(struct device *dev)
         domain = dca_find_domain(rc);
 
         if (!domain) {
-                if (dca_provider_ioat_ver_3_0(dev) && !list_empty(&dca_domains)) {
+                if (dca_provider_ioat_ver_3_0(dev) && !list_empty(&dca_domains))
                         dca_providers_blocked = 1;
-                } else {
-                        domain = dca_allocate_domain(rc);
-                        if (domain)
-                                list_add(&domain->node, &dca_domains);
-                }
         }
 
         return domain;
@@ -198,19 +193,19 @@ int dca_add_requester(struct device *dev)
         if (!dev)
                 return -EFAULT;
 
-        spin_lock_irqsave(&dca_lock, flags);
+        raw_spin_lock_irqsave(&dca_lock, flags);
 
         /* check if the requester has not been added already */
         dca = dca_find_provider_by_dev(dev);
         if (dca) {
-                spin_unlock_irqrestore(&dca_lock, flags);
+                raw_spin_unlock_irqrestore(&dca_lock, flags);
                 return -EEXIST;
         }
 
         pci_rc = dca_pci_rc_from_dev(dev);
         domain = dca_find_domain(pci_rc);
         if (!domain) {
-                spin_unlock_irqrestore(&dca_lock, flags);
+                raw_spin_unlock_irqrestore(&dca_lock, flags);
                 return -ENODEV;
         }
 
@@ -220,17 +215,17 @@ int dca_add_requester(struct device *dev)
                         break;
         }
 
-        spin_unlock_irqrestore(&dca_lock, flags);
+        raw_spin_unlock_irqrestore(&dca_lock, flags);
 
         if (slot < 0)
                 return slot;
 
         err = dca_sysfs_add_req(dca, dev, slot);
         if (err) {
-                spin_lock_irqsave(&dca_lock, flags);
+                raw_spin_lock_irqsave(&dca_lock, flags);
                 if (dca == dca_find_provider_by_dev(dev))
                         dca->ops->remove_requester(dca, dev);
-                spin_unlock_irqrestore(&dca_lock, flags);
+                raw_spin_unlock_irqrestore(&dca_lock, flags);
                 return err;
         }
 
@@ -251,14 +246,14 @@ int dca_remove_requester(struct device *dev)
         if (!dev)
                 return -EFAULT;
 
-        spin_lock_irqsave(&dca_lock, flags);
+        raw_spin_lock_irqsave(&dca_lock, flags);
         dca = dca_find_provider_by_dev(dev);
         if (!dca) {
-                spin_unlock_irqrestore(&dca_lock, flags);
+                raw_spin_unlock_irqrestore(&dca_lock, flags);
                 return -ENODEV;
         }
         slot = dca->ops->remove_requester(dca, dev);
-        spin_unlock_irqrestore(&dca_lock, flags);
+        raw_spin_unlock_irqrestore(&dca_lock, flags);
 
         if (slot < 0)
                 return slot;
@@ -280,16 +275,16 @@ u8 dca_common_get_tag(struct device *dev, int cpu)
         u8 tag;
         unsigned long flags;
 
-        spin_lock_irqsave(&dca_lock, flags);
+        raw_spin_lock_irqsave(&dca_lock, flags);
 
         dca = dca_find_provider_by_dev(dev);
         if (!dca) {
-                spin_unlock_irqrestore(&dca_lock, flags);
+                raw_spin_unlock_irqrestore(&dca_lock, flags);
                 return -ENODEV;
         }
         tag = dca->ops->get_tag(dca, dev, cpu);
 
-        spin_unlock_irqrestore(&dca_lock, flags);
+        raw_spin_unlock_irqrestore(&dca_lock, flags);
         return tag;
 }
 
@@ -360,36 +355,51 @@ int register_dca_provider(struct dca_provider *dca, struct device *dev)
 {
         int err;
         unsigned long flags;
-        struct dca_domain *domain;
+        struct dca_domain *domain, *newdomain = NULL;
 
-        spin_lock_irqsave(&dca_lock, flags);
+        raw_spin_lock_irqsave(&dca_lock, flags);
         if (dca_providers_blocked) {
-                spin_unlock_irqrestore(&dca_lock, flags);
+                raw_spin_unlock_irqrestore(&dca_lock, flags);
                 return -ENODEV;
         }
-        spin_unlock_irqrestore(&dca_lock, flags);
+        raw_spin_unlock_irqrestore(&dca_lock, flags);
 
         err = dca_sysfs_add_provider(dca, dev);
         if (err)
                 return err;
 
-        spin_lock_irqsave(&dca_lock, flags);
+        raw_spin_lock_irqsave(&dca_lock, flags);
         domain = dca_get_domain(dev);
         if (!domain) {
+                struct pci_bus *rc;
+
                 if (dca_providers_blocked) {
-                        spin_unlock_irqrestore(&dca_lock, flags);
+                        raw_spin_unlock_irqrestore(&dca_lock, flags);
                         dca_sysfs_remove_provider(dca);
                         unregister_dca_providers();
-                } else {
-                        spin_unlock_irqrestore(&dca_lock, flags);
+                        return -ENODEV;
+                }
+
+                raw_spin_unlock_irqrestore(&dca_lock, flags);
+                rc = dca_pci_rc_from_dev(dev);
+                newdomain = dca_allocate_domain(rc);
+                if (!newdomain)
+                        return -ENODEV;
+                raw_spin_lock_irqsave(&dca_lock, flags);
+                /* Recheck, we might have raced after dropping the lock */
+                domain = dca_get_domain(dev);
+                if (!domain) {
+                        domain = newdomain;
+                        newdomain = NULL;
+                        list_add(&domain->node, &dca_domains);
                 }
-                return -ENODEV;
         }
         list_add(&dca->node, &domain->dca_providers);
-        spin_unlock_irqrestore(&dca_lock, flags);
+        raw_spin_unlock_irqrestore(&dca_lock, flags);
 
         blocking_notifier_call_chain(&dca_provider_chain,
                                      DCA_PROVIDER_ADD, NULL);
+        kfree(newdomain);
         return 0;
 }
 EXPORT_SYMBOL_GPL(register_dca_provider);
@@ -407,7 +417,7 @@ void unregister_dca_provider(struct dca_provider *dca, struct device *dev)
         blocking_notifier_call_chain(&dca_provider_chain,
                                      DCA_PROVIDER_REMOVE, NULL);
 
-        spin_lock_irqsave(&dca_lock, flags);
+        raw_spin_lock_irqsave(&dca_lock, flags);
 
         list_del(&dca->node);
 
@@ -416,7 +426,7 @@ void unregister_dca_provider(struct dca_provider *dca, struct device *dev)
         if (list_empty(&domain->dca_providers))
                 dca_free_domain(domain);
 
-        spin_unlock_irqrestore(&dca_lock, flags);
+        raw_spin_unlock_irqrestore(&dca_lock, flags);
 
         dca_sysfs_remove_provider(dca);
 }
diff --git a/drivers/dma/ipu/ipu_irq.c b/drivers/dma/ipu/ipu_irq.c
index ab8a4eff072a..a71f55e72be9 100644
--- a/drivers/dma/ipu/ipu_irq.c
+++ b/drivers/dma/ipu/ipu_irq.c
@@ -81,7 +81,7 @@ static struct ipu_irq_map irq_map[CONFIG_MX3_IPU_IRQS];
 /* Protects allocations from the above array of maps */
 static DEFINE_MUTEX(map_lock);
 /* Protects register accesses and individual mappings */
-static DEFINE_SPINLOCK(bank_lock);
+static DEFINE_RAW_SPINLOCK(bank_lock);
 
 static struct ipu_irq_map *src2map(unsigned int src)
 {
@@ -101,11 +101,11 @@ static void ipu_irq_unmask(struct irq_data *d)
         uint32_t reg;
         unsigned long lock_flags;
 
-        spin_lock_irqsave(&bank_lock, lock_flags);
+        raw_spin_lock_irqsave(&bank_lock, lock_flags);
 
         bank = map->bank;
         if (!bank) {
-                spin_unlock_irqrestore(&bank_lock, lock_flags);
+                raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
                 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
                 return;
         }
@@ -114,7 +114,7 @@ static void ipu_irq_unmask(struct irq_data *d)
         reg |= (1UL << (map->source & 31));
         ipu_write_reg(bank->ipu, reg, bank->control);
 
-        spin_unlock_irqrestore(&bank_lock, lock_flags);
+        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
 }
 
 static void ipu_irq_mask(struct irq_data *d)
@@ -124,11 +124,11 @@ static void ipu_irq_mask(struct irq_data *d)
         uint32_t reg;
         unsigned long lock_flags;
 
-        spin_lock_irqsave(&bank_lock, lock_flags);
+        raw_spin_lock_irqsave(&bank_lock, lock_flags);
 
         bank = map->bank;
         if (!bank) {
-                spin_unlock_irqrestore(&bank_lock, lock_flags);
+                raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
                 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
                 return;
         }
@@ -137,7 +137,7 @@ static void ipu_irq_mask(struct irq_data *d)
         reg &= ~(1UL << (map->source & 31));
         ipu_write_reg(bank->ipu, reg, bank->control);
 
-        spin_unlock_irqrestore(&bank_lock, lock_flags);
+        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
 }
 
 static void ipu_irq_ack(struct irq_data *d)
@@ -146,17 +146,17 @@ static void ipu_irq_ack(struct irq_data *d)
         struct ipu_irq_bank *bank;
         unsigned long lock_flags;
 
-        spin_lock_irqsave(&bank_lock, lock_flags);
+        raw_spin_lock_irqsave(&bank_lock, lock_flags);
 
         bank = map->bank;
         if (!bank) {
-                spin_unlock_irqrestore(&bank_lock, lock_flags);
+                raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
                 pr_err("IPU: %s(%u) - unmapped!\n", __func__, d->irq);
                 return;
         }
 
         ipu_write_reg(bank->ipu, 1UL << (map->source & 31), bank->status);
-        spin_unlock_irqrestore(&bank_lock, lock_flags);
+        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
 }
 
 /**
@@ -172,11 +172,11 @@ bool ipu_irq_status(unsigned int irq)
         unsigned long lock_flags;
         bool ret;
 
-        spin_lock_irqsave(&bank_lock, lock_flags);
+        raw_spin_lock_irqsave(&bank_lock, lock_flags);
         bank = map->bank;
         ret = bank && ipu_read_reg(bank->ipu, bank->status) &
                 (1UL << (map->source & 31));
-        spin_unlock_irqrestore(&bank_lock, lock_flags);
+        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
 
         return ret;
 }
@@ -213,10 +213,10 @@ int ipu_irq_map(unsigned int source)
                 if (irq_map[i].source < 0) {
                         unsigned long lock_flags;
 
-                        spin_lock_irqsave(&bank_lock, lock_flags);
+                        raw_spin_lock_irqsave(&bank_lock, lock_flags);
                         irq_map[i].source = source;
                         irq_map[i].bank = irq_bank + source / 32;
-                        spin_unlock_irqrestore(&bank_lock, lock_flags);
+                        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
 
                         ret = irq_map[i].irq;
                         pr_debug("IPU: mapped source %u to IRQ %u\n",
@@ -252,10 +252,10 @@ int ipu_irq_unmap(unsigned int source)
                         pr_debug("IPU: unmapped source %u from IRQ %u\n",
                                  source, irq_map[i].irq);
 
-                        spin_lock_irqsave(&bank_lock, lock_flags);
+                        raw_spin_lock_irqsave(&bank_lock, lock_flags);
                         irq_map[i].source = -EINVAL;
                         irq_map[i].bank = NULL;
-                        spin_unlock_irqrestore(&bank_lock, lock_flags);
+                        raw_spin_unlock_irqrestore(&bank_lock, lock_flags);
 
                         ret = 0;
                         break;
@@ -276,7 +276,7 @@ static void ipu_irq_err(unsigned int irq, struct irq_desc *desc)
         for (i = IPU_IRQ_NR_FN_BANKS; i < IPU_IRQ_NR_BANKS; i++) {
                 struct ipu_irq_bank *bank = irq_bank + i;
 
-                spin_lock(&bank_lock);
+                raw_spin_lock(&bank_lock);
                 status = ipu_read_reg(ipu, bank->status);
                 /*
                  * Don't think we have to clear all interrupts here, they will
@@ -284,18 +284,18 @@ static void ipu_irq_err(unsigned int irq, struct irq_desc *desc)
                  * might want to clear unhandled interrupts after the loop...
                  */
                 status &= ipu_read_reg(ipu, bank->control);
-                spin_unlock(&bank_lock);
+                raw_spin_unlock(&bank_lock);
                 while ((line = ffs(status))) {
                         struct ipu_irq_map *map;
 
                         line--;
                         status &= ~(1UL << line);
 
-                        spin_lock(&bank_lock);
+                        raw_spin_lock(&bank_lock);
                         map = src2map(32 * i + line);
                         if (map)
                                 irq = map->irq;
-                        spin_unlock(&bank_lock);
+                        raw_spin_unlock(&bank_lock);
 
                         if (!map) {
                                 pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
@@ -317,22 +317,22 @@ static void ipu_irq_fn(unsigned int irq, struct irq_desc *desc)
         for (i = 0; i < IPU_IRQ_NR_FN_BANKS; i++) {
                 struct ipu_irq_bank *bank = irq_bank + i;
 
-                spin_lock(&bank_lock);
+                raw_spin_lock(&bank_lock);
                 status = ipu_read_reg(ipu, bank->status);
                 /* Not clearing all interrupts, see above */
                 status &= ipu_read_reg(ipu, bank->control);
-                spin_unlock(&bank_lock);
+                raw_spin_unlock(&bank_lock);
                 while ((line = ffs(status))) {
                         struct ipu_irq_map *map;
 
                         line--;
                         status &= ~(1UL << line);
 
-                        spin_lock(&bank_lock);
+                        raw_spin_lock(&bank_lock);
                         map = src2map(32 * i + line);
                         if (map)
                                 irq = map->irq;
-                        spin_unlock(&bank_lock);
+                        raw_spin_unlock(&bank_lock);
 
                         if (!map) {
                                 pr_err("IPU: Interrupt on unmapped source %u bank %d\n",
diff --git a/drivers/iommu/dmar.c b/drivers/iommu/dmar.c
index 587e8f2d38d8..35c1e17fce1d 100644
--- a/drivers/iommu/dmar.c
+++ b/drivers/iommu/dmar.c
@@ -652,7 +652,7 @@ int alloc_iommu(struct dmar_drhd_unit *drhd)
                 (unsigned long long)iommu->cap,
                 (unsigned long long)iommu->ecap);
 
-        spin_lock_init(&iommu->register_lock);
+        raw_spin_lock_init(&iommu->register_lock);
 
         drhd->iommu = iommu;
         return 0;
@@ -771,11 +771,11 @@ int qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu)
 restart:
         rc = 0;
 
-        spin_lock_irqsave(&qi->q_lock, flags);
+        raw_spin_lock_irqsave(&qi->q_lock, flags);
         while (qi->free_cnt < 3) {
-                spin_unlock_irqrestore(&qi->q_lock, flags);
+                raw_spin_unlock_irqrestore(&qi->q_lock, flags);
                 cpu_relax();
-                spin_lock_irqsave(&qi->q_lock, flags);
+                raw_spin_lock_irqsave(&qi->q_lock, flags);
         }
 
         index = qi->free_head;
@@ -815,15 +815,15 @@ restart:
                 if (rc)
                         break;
 
-                spin_unlock(&qi->q_lock);
+                raw_spin_unlock(&qi->q_lock);
                 cpu_relax();
-                spin_lock(&qi->q_lock);
+                raw_spin_lock(&qi->q_lock);
         }
 
         qi->desc_status[index] = QI_DONE;
 
         reclaim_free_desc(qi);
-        spin_unlock_irqrestore(&qi->q_lock, flags);
+        raw_spin_unlock_irqrestore(&qi->q_lock, flags);
 
         if (rc == -EAGAIN)
                 goto restart;
@@ -912,7 +912,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
         if (!ecap_qis(iommu->ecap))
                 return;
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         sts =  dmar_readq(iommu->reg + DMAR_GSTS_REG);
         if (!(sts & DMA_GSTS_QIES))
@@ -932,7 +932,7 @@ void dmar_disable_qi(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl,
                       !(sts & DMA_GSTS_QIES), sts);
 end:
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 /*
@@ -947,7 +947,7 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)
         qi->free_head = qi->free_tail = 0;
         qi->free_cnt = QI_LENGTH;
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         /* write zero to the tail reg */
         writel(0, iommu->reg + DMAR_IQT_REG);
@@ -960,7 +960,7 @@ static void __dmar_enable_qi(struct intel_iommu *iommu)
         /* Make sure hardware complete it */
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG, readl, (sts & DMA_GSTS_QIES), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 /*
@@ -1009,7 +1009,7 @@ int dmar_enable_qi(struct intel_iommu *iommu)
         qi->free_head = qi->free_tail = 0;
         qi->free_cnt = QI_LENGTH;
 
-        spin_lock_init(&qi->q_lock);
+        raw_spin_lock_init(&qi->q_lock);
 
         __dmar_enable_qi(iommu);
 
@@ -1075,11 +1075,11 @@ void dmar_msi_unmask(struct irq_data *data)
         unsigned long flag;
 
         /* unmask it */
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         writel(0, iommu->reg + DMAR_FECTL_REG);
         /* Read a reg to force flush the post write */
         readl(iommu->reg + DMAR_FECTL_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 void dmar_msi_mask(struct irq_data *data)
@@ -1088,11 +1088,11 @@ void dmar_msi_mask(struct irq_data *data)
         struct intel_iommu *iommu = irq_data_get_irq_handler_data(data);
 
         /* mask it */
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         writel(DMA_FECTL_IM, iommu->reg + DMAR_FECTL_REG);
         /* Read a reg to force flush the post write */
         readl(iommu->reg + DMAR_FECTL_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 void dmar_msi_write(int irq, struct msi_msg *msg)
@@ -1100,11 +1100,11 @@ void dmar_msi_write(int irq, struct msi_msg *msg)
         struct intel_iommu *iommu = irq_get_handler_data(irq);
         unsigned long flag;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         writel(msg->data, iommu->reg + DMAR_FEDATA_REG);
         writel(msg->address_lo, iommu->reg + DMAR_FEADDR_REG);
         writel(msg->address_hi, iommu->reg + DMAR_FEUADDR_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 void dmar_msi_read(int irq, struct msi_msg *msg)
@@ -1112,11 +1112,11 @@ void dmar_msi_read(int irq, struct msi_msg *msg)
         struct intel_iommu *iommu = irq_get_handler_data(irq);
         unsigned long flag;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         msg->data = readl(iommu->reg + DMAR_FEDATA_REG);
         msg->address_lo = readl(iommu->reg + DMAR_FEADDR_REG);
         msg->address_hi = readl(iommu->reg + DMAR_FEUADDR_REG);
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 static int dmar_fault_do_one(struct intel_iommu *iommu, int type,
@@ -1153,7 +1153,7 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
         u32 fault_status;
         unsigned long flag;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
         if (fault_status)
                 printk(KERN_ERR "DRHD: handling fault status reg %x\n",
@@ -1192,7 +1192,7 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
                 writel(DMA_FRCD_F, iommu->reg + reg +
                         fault_index * PRIMARY_FAULT_REG_LEN + 12);
 
-                spin_unlock_irqrestore(&iommu->register_lock, flag);
+                raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 
                 dmar_fault_do_one(iommu, type, fault_reason,
                                 source_id, guest_addr);
@@ -1200,14 +1200,14 @@ irqreturn_t dmar_fault(int irq, void *dev_id)
                 fault_index++;
                 if (fault_index >= cap_num_fault_regs(iommu->cap))
                         fault_index = 0;
-                spin_lock_irqsave(&iommu->register_lock, flag);
+                raw_spin_lock_irqsave(&iommu->register_lock, flag);
         }
 clear_rest:
         /* clear all the other faults */
         fault_status = readl(iommu->reg + DMAR_FSTS_REG);
         writel(fault_status, iommu->reg + DMAR_FSTS_REG);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
         return IRQ_HANDLED;
 }
 
diff --git a/drivers/iommu/intel-iommu.c b/drivers/iommu/intel-iommu.c
index f28d933c7927..be1953c239b0 100644
--- a/drivers/iommu/intel-iommu.c
+++ b/drivers/iommu/intel-iommu.c
@@ -939,7 +939,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
 
         addr = iommu->root_entry;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         dmar_writeq(iommu->reg + DMAR_RTADDR_REG, virt_to_phys(addr));
 
         writel(iommu->gcmd | DMA_GCMD_SRTP, iommu->reg + DMAR_GCMD_REG);
@@ -948,7 +948,7 @@ static void iommu_set_root_entry(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_RTPS), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 static void iommu_flush_write_buffer(struct intel_iommu *iommu)
@@ -959,14 +959,14 @@ static void iommu_flush_write_buffer(struct intel_iommu *iommu)
         if (!rwbf_quirk && !cap_rwbf(iommu->cap))
                 return;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         writel(iommu->gcmd | DMA_GCMD_WBF, iommu->reg + DMAR_GCMD_REG);
 
         /* Make sure hardware complete it */
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (!(val & DMA_GSTS_WBFS)), val);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 /* return value determine if we need a write buffer flush */
@@ -993,14 +993,14 @@ static void __iommu_flush_context(struct intel_iommu *iommu,
         }
         val |= DMA_CCMD_ICC;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         dmar_writeq(iommu->reg + DMAR_CCMD_REG, val);
 
         /* Make sure hardware complete it */
         IOMMU_WAIT_OP(iommu, DMAR_CCMD_REG,
                 dmar_readq, (!(val & DMA_CCMD_ICC)), val);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 }
 
 /* return value determine if we need a write buffer flush */
@@ -1039,7 +1039,7 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
         if (cap_write_drain(iommu->cap))
                 val |= DMA_TLB_WRITE_DRAIN;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         /* Note: Only uses first TLB reg currently */
         if (val_iva)
                 dmar_writeq(iommu->reg + tlb_offset, val_iva);
@@ -1049,7 +1049,7 @@ static void __iommu_flush_iotlb(struct intel_iommu *iommu, u16 did,
         IOMMU_WAIT_OP(iommu, tlb_offset + 8,
                 dmar_readq, (!(val & DMA_TLB_IVT)), val);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
 
         /* check IOTLB invalidation granularity */
         if (DMA_TLB_IAIG(val) == 0)
@@ -1165,7 +1165,7 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
         u32 pmen;
         unsigned long flags;
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
         pmen = readl(iommu->reg + DMAR_PMEN_REG);
         pmen &= ~DMA_PMEN_EPM;
         writel(pmen, iommu->reg + DMAR_PMEN_REG);
@@ -1174,7 +1174,7 @@ static void iommu_disable_protect_mem_regions(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_PMEN_REG,
                 readl, !(pmen & DMA_PMEN_PRS), pmen);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 static int iommu_enable_translation(struct intel_iommu *iommu)
@@ -1182,7 +1182,7 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
         u32 sts;
         unsigned long flags;
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
         iommu->gcmd |= DMA_GCMD_TE;
         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 
@@ -1190,7 +1190,7 @@ static int iommu_enable_translation(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_TES), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
         return 0;
 }
 
@@ -1199,7 +1199,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
         u32 sts;
         unsigned long flag;
 
-        spin_lock_irqsave(&iommu->register_lock, flag);
+        raw_spin_lock_irqsave(&iommu->register_lock, flag);
         iommu->gcmd &= ~DMA_GCMD_TE;
         writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG);
 
@@ -1207,7 +1207,7 @@ static int iommu_disable_translation(struct intel_iommu *iommu)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (!(sts & DMA_GSTS_TES)), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flag);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
         return 0;
 }
 
@@ -3329,7 +3329,7 @@ static int iommu_suspend(void)
         for_each_active_iommu(iommu, drhd) {
                 iommu_disable_translation(iommu);
 
-                spin_lock_irqsave(&iommu->register_lock, flag);
+                raw_spin_lock_irqsave(&iommu->register_lock, flag);
 
                 iommu->iommu_state[SR_DMAR_FECTL_REG] =
                         readl(iommu->reg + DMAR_FECTL_REG);
@@ -3340,7 +3340,7 @@ static int iommu_suspend(void)
                 iommu->iommu_state[SR_DMAR_FEUADDR_REG] =
                         readl(iommu->reg + DMAR_FEUADDR_REG);
 
-                spin_unlock_irqrestore(&iommu->register_lock, flag);
+                raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
         }
         return 0;
 
@@ -3367,7 +3367,7 @@ static void iommu_resume(void)
 
         for_each_active_iommu(iommu, drhd) {
 
-                spin_lock_irqsave(&iommu->register_lock, flag);
+                raw_spin_lock_irqsave(&iommu->register_lock, flag);
 
                 writel(iommu->iommu_state[SR_DMAR_FECTL_REG],
                         iommu->reg + DMAR_FECTL_REG);
@@ -3378,7 +3378,7 @@ static void iommu_resume(void)
                 writel(iommu->iommu_state[SR_DMAR_FEUADDR_REG],
                         iommu->reg + DMAR_FEUADDR_REG);
 
-                spin_unlock_irqrestore(&iommu->register_lock, flag);
+                raw_spin_unlock_irqrestore(&iommu->register_lock, flag);
         }
 
         for_each_active_iommu(iommu, drhd)
diff --git a/drivers/iommu/intr_remapping.c b/drivers/iommu/intr_remapping.c
index cfb0dd4bf0b6..07c9f189f314 100644
--- a/drivers/iommu/intr_remapping.c
+++ b/drivers/iommu/intr_remapping.c
@@ -54,7 +54,7 @@ static __init int setup_intremap(char *str)
 }
 early_param("intremap", setup_intremap);
 
-static DEFINE_SPINLOCK(irq_2_ir_lock);
+static DEFINE_RAW_SPINLOCK(irq_2_ir_lock);
 
 static struct irq_2_iommu *irq_2_iommu(unsigned int irq)
 {
@@ -71,12 +71,12 @@ int get_irte(int irq, struct irte *entry)
         if (!entry || !irq_iommu)
                 return -1;
 
-        spin_lock_irqsave(&irq_2_ir_lock, flags);
+        raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 
         index = irq_iommu->irte_index + irq_iommu->sub_handle;
         *entry = *(irq_iommu->iommu->ir_table->base + index);
 
-        spin_unlock_irqrestore(&irq_2_ir_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
         return 0;
 }
 
@@ -110,7 +110,7 @@ int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
                 return -1;
         }
 
-        spin_lock_irqsave(&irq_2_ir_lock, flags);
+        raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
         do {
                 for (i = index; i < index + count; i++)
                         if  (table->base[i].present)
@@ -122,7 +122,7 @@ int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
                 index = (index + count) % INTR_REMAP_TABLE_ENTRIES;
 
                 if (index == start_index) {
-                        spin_unlock_irqrestore(&irq_2_ir_lock, flags);
+                        raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
                         printk(KERN_ERR "can't allocate an IRTE\n");
                         return -1;
                 }
@@ -136,7 +136,7 @@ int alloc_irte(struct intel_iommu *iommu, int irq, u16 count)
         irq_iommu->sub_handle = 0;
         irq_iommu->irte_mask = mask;
 
-        spin_unlock_irqrestore(&irq_2_ir_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 
         return index;
 }
@@ -161,10 +161,10 @@ int map_irq_to_irte_handle(int irq, u16 *sub_handle)
         if (!irq_iommu)
                 return -1;
 
-        spin_lock_irqsave(&irq_2_ir_lock, flags);
+        raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
         *sub_handle = irq_iommu->sub_handle;
         index = irq_iommu->irte_index;
-        spin_unlock_irqrestore(&irq_2_ir_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
         return index;
 }
 
@@ -176,14 +176,14 @@ int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index, u16 subhandle)
         if (!irq_iommu)
                 return -1;
 
-        spin_lock_irqsave(&irq_2_ir_lock, flags);
+        raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 
         irq_iommu->iommu = iommu;
         irq_iommu->irte_index = index;
         irq_iommu->sub_handle = subhandle;
         irq_iommu->irte_mask = 0;
 
-        spin_unlock_irqrestore(&irq_2_ir_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 
         return 0;
 }
@@ -199,7 +199,7 @@ int modify_irte(int irq, struct irte *irte_modified)
         if (!irq_iommu)
                 return -1;
 
-        spin_lock_irqsave(&irq_2_ir_lock, flags);
+        raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 
         iommu = irq_iommu->iommu;
 
@@ -211,7 +211,7 @@ int modify_irte(int irq, struct irte *irte_modified)
         __iommu_flush_cache(iommu, irte, sizeof(*irte));
 
         rc = qi_flush_iec(iommu, index, 0);
-        spin_unlock_irqrestore(&irq_2_ir_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 
         return rc;
 }
@@ -279,7 +279,7 @@ int free_irte(int irq)
         if (!irq_iommu)
                 return -1;
 
-        spin_lock_irqsave(&irq_2_ir_lock, flags);
+        raw_spin_lock_irqsave(&irq_2_ir_lock, flags);
 
         rc = clear_entries(irq_iommu);
 
@@ -288,7 +288,7 @@ int free_irte(int irq)
         irq_iommu->sub_handle = 0;
         irq_iommu->irte_mask = 0;
 
-        spin_unlock_irqrestore(&irq_2_ir_lock, flags);
+        raw_spin_unlock_irqrestore(&irq_2_ir_lock, flags);
 
         return rc;
 }
@@ -418,7 +418,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 
         addr = virt_to_phys((void *)iommu->ir_table->base);
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         dmar_writeq(iommu->reg + DMAR_IRTA_REG,
                     (addr) | IR_X2APIC_MODE(mode) | INTR_REMAP_TABLE_REG_SIZE);
@@ -429,7 +429,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
 
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_IRTPS), sts);
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 
         /*
          * global invalidation of interrupt entry cache before enabling
@@ -437,7 +437,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
          */
         qi_global_iec(iommu);
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         /* Enable interrupt-remapping */
         iommu->gcmd |= DMA_GCMD_IRE;
@@ -446,7 +446,7 @@ static void iommu_set_intr_remapping(struct intel_iommu *iommu, int mode)
         IOMMU_WAIT_OP(iommu, DMAR_GSTS_REG,
                       readl, (sts & DMA_GSTS_IRES), sts);
 
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 
@@ -494,7 +494,7 @@ static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
          */
         qi_global_iec(iommu);
 
-        spin_lock_irqsave(&iommu->register_lock, flags);
+        raw_spin_lock_irqsave(&iommu->register_lock, flags);
 
         sts = dmar_readq(iommu->reg + DMAR_GSTS_REG);
         if (!(sts & DMA_GSTS_IRES))
@@ -507,7 +507,7 @@ static void iommu_disable_intr_remapping(struct intel_iommu *iommu)
                       readl, !(sts & DMA_GSTS_IRES), sts);
 
 end:
-        spin_unlock_irqrestore(&iommu->register_lock, flags);
+        raw_spin_unlock_irqrestore(&iommu->register_lock, flags);
 }
 
 static int __init dmar_x2apic_optout(void)
diff --git a/drivers/oprofile/event_buffer.c b/drivers/oprofile/event_buffer.c
index dd87e86048be..c0cc4e7ff023 100644
--- a/drivers/oprofile/event_buffer.c
+++ b/drivers/oprofile/event_buffer.c
@@ -82,10 +82,10 @@ int alloc_event_buffer(void)
 {
         unsigned long flags;
 
-        spin_lock_irqsave(&oprofilefs_lock, flags);
+        raw_spin_lock_irqsave(&oprofilefs_lock, flags);
         buffer_size = oprofile_buffer_size;
         buffer_watershed = oprofile_buffer_watershed;
-        spin_unlock_irqrestore(&oprofilefs_lock, flags);
+        raw_spin_unlock_irqrestore(&oprofilefs_lock, flags);
 
         if (buffer_watershed >= buffer_size)
                 return -EINVAL;
diff --git a/drivers/oprofile/oprofile_perf.c b/drivers/oprofile/oprofile_perf.c
index 94796f39bc47..da14432806c6 100644
--- a/drivers/oprofile/oprofile_perf.c
+++ b/drivers/oprofile/oprofile_perf.c
@@ -160,9 +160,9 @@ static int oprofile_perf_create_files(struct super_block *sb, struct dentry *roo
 
 static int oprofile_perf_setup(void)
 {
-        spin_lock(&oprofilefs_lock);
+        raw_spin_lock(&oprofilefs_lock);
         op_perf_setup();
-        spin_unlock(&oprofilefs_lock);
+        raw_spin_unlock(&oprofilefs_lock);
         return 0;
 }
 
diff --git a/drivers/oprofile/oprofilefs.c b/drivers/oprofile/oprofilefs.c
index e9ff6f7770be..d0de6cc2d7a5 100644
--- a/drivers/oprofile/oprofilefs.c
+++ b/drivers/oprofile/oprofilefs.c
@@ -21,7 +21,7 @@
 
 #define OPROFILEFS_MAGIC 0x6f70726f
 
-DEFINE_SPINLOCK(oprofilefs_lock);
+DEFINE_RAW_SPINLOCK(oprofilefs_lock);
 
 static struct inode *oprofilefs_get_inode(struct super_block *sb, int mode)
 {
@@ -76,9 +76,9 @@ int oprofilefs_ulong_from_user(unsigned long *val, char const __user *buf, size_
         if (copy_from_user(tmpbuf, buf, count))
                 return -EFAULT;
 
-        spin_lock_irqsave(&oprofilefs_lock, flags);
+        raw_spin_lock_irqsave(&oprofilefs_lock, flags);
         *val = simple_strtoul(tmpbuf, NULL, 0);
-        spin_unlock_irqrestore(&oprofilefs_lock, flags);
+        raw_spin_unlock_irqrestore(&oprofilefs_lock, flags);
         return 0;
 }
 
diff --git a/drivers/video/console/vgacon.c b/drivers/video/console/vgacon.c
index 915fd74da7a2..d449a74d4a31 100644
--- a/drivers/video/console/vgacon.c
+++ b/drivers/video/console/vgacon.c
@@ -50,7 +50,7 @@
 #include <video/vga.h>
 #include <asm/io.h>
 
-static DEFINE_SPINLOCK(vga_lock);
+static DEFINE_RAW_SPINLOCK(vga_lock);
 static int cursor_size_lastfrom;
 static int cursor_size_lastto;
 static u32 vgacon_xres;
@@ -157,7 +157,7 @@ static inline void write_vga(unsigned char reg, unsigned int val)
          * ddprintk might set the console position from interrupt
          * handlers, thus the write has to be IRQ-atomic.
          */
-        spin_lock_irqsave(&vga_lock, flags);
+        raw_spin_lock_irqsave(&vga_lock, flags);
 
 #ifndef SLOW_VGA
         v1 = reg + (val & 0xff00);
@@ -170,7 +170,7 @@ static inline void write_vga(unsigned char reg, unsigned int val)
         outb_p(reg + 1, vga_video_port_reg);
         outb_p(val & 0xff, vga_video_port_val);
 #endif
-        spin_unlock_irqrestore(&vga_lock, flags);
+        raw_spin_unlock_irqrestore(&vga_lock, flags);
 }
 
 static inline void vga_set_mem_top(struct vc_data *c)
@@ -664,7 +664,7 @@ static void vgacon_set_cursor_size(int xpos, int from, int to)
         cursor_size_lastfrom = from;
         cursor_size_lastto = to;
 
-        spin_lock_irqsave(&vga_lock, flags);
+        raw_spin_lock_irqsave(&vga_lock, flags);
         if (vga_video_type >= VIDEO_TYPE_VGAC) {
                 outb_p(VGA_CRTC_CURSOR_START, vga_video_port_reg);
                 curs = inb_p(vga_video_port_val);
@@ -682,7 +682,7 @@ static void vgacon_set_cursor_size(int xpos, int from, int to)
         outb_p(curs, vga_video_port_val);
         outb_p(VGA_CRTC_CURSOR_END, vga_video_port_reg);
         outb_p(cure, vga_video_port_val);
-        spin_unlock_irqrestore(&vga_lock, flags);
+        raw_spin_unlock_irqrestore(&vga_lock, flags);
 }
 
 static void vgacon_cursor(struct vc_data *c, int mode)
@@ -757,7 +757,7 @@ static int vgacon_doresize(struct vc_data *c,
         unsigned int scanlines = height * c->vc_font.height;
         u8 scanlines_lo = 0, r7 = 0, vsync_end = 0, mode, max_scan;
 
-        spin_lock_irqsave(&vga_lock, flags);
+        raw_spin_lock_irqsave(&vga_lock, flags);
 
         vgacon_xres = width * VGA_FONTWIDTH;
         vgacon_yres = height * c->vc_font.height;
@@ -808,7 +808,7 @@ static int vgacon_doresize(struct vc_data *c,
                 outb_p(vsync_end, vga_video_port_val);
         }
 
-        spin_unlock_irqrestore(&vga_lock, flags);
+        raw_spin_unlock_irqrestore(&vga_lock, flags);
         return 0;
 }
 
@@ -891,11 +891,11 @@ static void vga_vesa_blank(struct vgastate *state, int mode)
 {
         /* save original values of VGA controller registers */
         if (!vga_vesa_blanked) {
-                spin_lock_irq(&vga_lock);
+                raw_spin_lock_irq(&vga_lock);
                 vga_state.SeqCtrlIndex = vga_r(state->vgabase, VGA_SEQ_I);
                 vga_state.CrtCtrlIndex = inb_p(vga_video_port_reg);
                 vga_state.CrtMiscIO = vga_r(state->vgabase, VGA_MIS_R);
-                spin_unlock_irq(&vga_lock);
+                raw_spin_unlock_irq(&vga_lock);
 
                 outb_p(0x00, vga_video_port_reg);       /* HorizontalTotal */
                 vga_state.HorizontalTotal = inb_p(vga_video_port_val);
@@ -918,7 +918,7 @@ static void vga_vesa_blank(struct vgastate *state, int mode)
 
         /* assure that video is enabled */
         /* "0x20" is VIDEO_ENABLE_bit in register 01 of sequencer */
-        spin_lock_irq(&vga_lock);
+        raw_spin_lock_irq(&vga_lock);
         vga_wseq(state->vgabase, VGA_SEQ_CLOCK_MODE, vga_state.ClockingMode | 0x20);
 
         /* test for vertical retrace in process.... */
@@ -954,13 +954,13 @@ static void vga_vesa_blank(struct vgastate *state, int mode)
         /* restore both index registers */
         vga_w(state->vgabase, VGA_SEQ_I, vga_state.SeqCtrlIndex);
         outb_p(vga_state.CrtCtrlIndex, vga_video_port_reg);
-        spin_unlock_irq(&vga_lock);
+        raw_spin_unlock_irq(&vga_lock);
 }
 
 static void vga_vesa_unblank(struct vgastate *state)
 {
         /* restore original values of VGA controller registers */
-        spin_lock_irq(&vga_lock);
+        raw_spin_lock_irq(&vga_lock);
         vga_w(state->vgabase, VGA_MIS_W, vga_state.CrtMiscIO);
 
         outb_p(0x00, vga_video_port_reg);       /* HorizontalTotal */
@@ -985,7 +985,7 @@ static void vga_vesa_unblank(struct vgastate *state)
         /* restore index/control registers */
         vga_w(state->vgabase, VGA_SEQ_I, vga_state.SeqCtrlIndex);
         outb_p(vga_state.CrtCtrlIndex, vga_video_port_reg);
-        spin_unlock_irq(&vga_lock);
+        raw_spin_unlock_irq(&vga_lock);
 }
 
 static void vga_pal_blank(struct vgastate *state)
@@ -1104,7 +1104,7 @@ static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512)
                 charmap += 4 * cmapsz;
 #endif
 
-        spin_lock_irq(&vga_lock);
+        raw_spin_lock_irq(&vga_lock);
         /* First, the Sequencer */
         vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x1);
         /* CPU writes only to map 2 */
@@ -1120,7 +1120,7 @@ static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512)
         vga_wgfx(state->vgabase, VGA_GFX_MODE, 0x00);
         /* map start at A000:0000 */
         vga_wgfx(state->vgabase, VGA_GFX_MISC, 0x00);
-        spin_unlock_irq(&vga_lock);
+        raw_spin_unlock_irq(&vga_lock);
 
         if (arg) {
                 if (set)
@@ -1147,7 +1147,7 @@ static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512)
                 }
         }
 
-        spin_lock_irq(&vga_lock);
+        raw_spin_lock_irq(&vga_lock);
         /* First, the sequencer, Synchronous reset */
         vga_wseq(state->vgabase, VGA_SEQ_RESET, 0x01);  
         /* CPU writes to maps 0 and 1 */
@@ -1186,7 +1186,7 @@ static int vgacon_do_font_op(struct vgastate *state,char *arg,int set,int ch512)
                 inb_p(video_port_status);
                 vga_wattr(state->vgabase, VGA_AR_ENABLE_DISPLAY, 0);    
         }
-        spin_unlock_irq(&vga_lock);
+        raw_spin_unlock_irq(&vga_lock);
         return 0;
 }
 
@@ -1211,26 +1211,26 @@ static int vgacon_adjust_height(struct vc_data *vc, unsigned fontheight)
            registers; they are write-only on EGA, but it appears that they
            are all don't care bits on EGA, so I guess it doesn't matter. */
 
-        spin_lock_irq(&vga_lock);
+        raw_spin_lock_irq(&vga_lock);
         outb_p(0x07, vga_video_port_reg);       /* CRTC overflow register */
         ovr = inb_p(vga_video_port_val);
         outb_p(0x09, vga_video_port_reg);       /* Font size register */
         fsr = inb_p(vga_video_port_val);
-        spin_unlock_irq(&vga_lock);
+        raw_spin_unlock_irq(&vga_lock);
 
         vde = maxscan & 0xff;   /* Vertical display end reg */
         ovr = (ovr & 0xbd) +    /* Overflow register */
             ((maxscan & 0x100) >> 7) + ((maxscan & 0x200) >> 3);
         fsr = (fsr & 0xe0) + (fontheight - 1);  /*  Font size register */
 
-        spin_lock_irq(&vga_lock);
+        raw_spin_lock_irq(&vga_lock);
         outb_p(0x07, vga_video_port_reg);       /* CRTC overflow register */
         outb_p(ovr, vga_video_port_val);
         outb_p(0x09, vga_video_port_reg);       /* Font size */
         outb_p(fsr, vga_video_port_val);
         outb_p(0x12, vga_video_port_reg);       /* Vertical display limit */
         outb_p(vde, vga_video_port_val);
-        spin_unlock_irq(&vga_lock);
+        raw_spin_unlock_irq(&vga_lock);
         vga_video_font_height = fontheight;
 
         for (i = 0; i < MAX_NR_CONSOLES; i++) {