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-rw-r--r--drivers/pinctrl/Kconfig48
-rw-r--r--drivers/pinctrl/Makefile5
-rw-r--r--drivers/pinctrl/pinconf-generic.c4
-rw-r--r--drivers/pinctrl/pinconf.c22
-rw-r--r--drivers/pinctrl/pinctrl-as3722.c20
-rw-r--r--drivers/pinctrl/pinctrl-at91.c48
-rw-r--r--drivers/pinctrl/pinctrl-baytrail.c30
-rw-r--r--drivers/pinctrl/pinctrl-capri.c1454
-rw-r--r--drivers/pinctrl/pinctrl-imx1-core.c7
-rw-r--r--drivers/pinctrl/pinctrl-imx25.c351
-rw-r--r--drivers/pinctrl/pinctrl-msm.c990
-rw-r--r--drivers/pinctrl/pinctrl-msm.h122
-rw-r--r--drivers/pinctrl/pinctrl-msm8x74.c636
-rw-r--r--drivers/pinctrl/pinctrl-nomadik.c6
-rw-r--r--drivers/pinctrl/pinctrl-single.c18
-rw-r--r--drivers/pinctrl/pinctrl-st.c8
-rw-r--r--drivers/pinctrl/pinctrl-sunxi-pins.h2
-rw-r--r--drivers/pinctrl/pinctrl-sunxi.c13
-rw-r--r--drivers/pinctrl/pinctrl-tegra124.c3137
-rw-r--r--drivers/pinctrl/pinctrl-xway.c4
-rw-r--r--drivers/pinctrl/sh-pfc/core.c76
-rw-r--r--drivers/pinctrl/sh-pfc/core.h4
-rw-r--r--drivers/pinctrl/sh-pfc/gpio.c24
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c17
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c15
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c752
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c655
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7203.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7264.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7269.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c15
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c66
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7720.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7722.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7723.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7724.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7734.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7757.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7785.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7786.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-shx3.c2
-rw-r--r--drivers/pinctrl/sh-pfc/sh_pfc.h16
-rw-r--r--drivers/pinctrl/sirf/pinctrl-atlas6.c24
-rw-r--r--drivers/pinctrl/sirf/pinctrl-prima2.c48
-rw-r--r--drivers/pinctrl/sirf/pinctrl-sirf.c51
47 files changed, 8410 insertions, 308 deletions
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 33f9dc1f14fd..be361b7cd30f 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -104,6 +104,19 @@ config PINCTRL_BCM2835
104 select PINMUX 104 select PINMUX
105 select PINCONF 105 select PINCONF
106 106
107config PINCTRL_CAPRI
108 bool "Broadcom Capri pinctrl driver"
109 depends on OF
110 select PINMUX
111 select PINCONF
112 select GENERIC_PINCONF
113 select REGMAP_MMIO
114 help
115 Say Y here to support Broadcom Capri pinctrl driver, which is used for
116 the BCM281xx SoC family, including BCM11130, BCM11140, BCM11351,
117 BCM28145, and BCM28155 SoCs. This driver requires the pinctrl
118 framework. GPIO is provided by a separate GPIO driver.
119
107config PINCTRL_IMX 120config PINCTRL_IMX
108 bool 121 bool
109 select PINMUX 122 select PINMUX
@@ -116,15 +129,22 @@ config PINCTRL_IMX1_CORE
116 129
117config PINCTRL_IMX27 130config PINCTRL_IMX27
118 bool "IMX27 pinctrl driver" 131 bool "IMX27 pinctrl driver"
119 depends on OF
120 depends on SOC_IMX27 132 depends on SOC_IMX27
121 select PINCTRL_IMX1_CORE 133 select PINCTRL_IMX1_CORE
122 help 134 help
123 Say Y here to enable the imx27 pinctrl driver 135 Say Y here to enable the imx27 pinctrl driver
124 136
137
138config PINCTRL_IMX25
139 bool "IMX25 pinctrl driver"
140 depends on OF
141 depends on SOC_IMX25
142 select PINCTRL_IMX
143 help
144 Say Y here to enable the imx25 pinctrl driver
145
125config PINCTRL_IMX35 146config PINCTRL_IMX35
126 bool "IMX35 pinctrl driver" 147 bool "IMX35 pinctrl driver"
127 depends on OF
128 depends on SOC_IMX35 148 depends on SOC_IMX35
129 select PINCTRL_IMX 149 select PINCTRL_IMX
130 help 150 help
@@ -132,7 +152,6 @@ config PINCTRL_IMX35
132 152
133config PINCTRL_IMX50 153config PINCTRL_IMX50
134 bool "IMX50 pinctrl driver" 154 bool "IMX50 pinctrl driver"
135 depends on OF
136 depends on SOC_IMX50 155 depends on SOC_IMX50
137 select PINCTRL_IMX 156 select PINCTRL_IMX
138 help 157 help
@@ -140,7 +159,6 @@ config PINCTRL_IMX50
140 159
141config PINCTRL_IMX51 160config PINCTRL_IMX51
142 bool "IMX51 pinctrl driver" 161 bool "IMX51 pinctrl driver"
143 depends on OF
144 depends on SOC_IMX51 162 depends on SOC_IMX51
145 select PINCTRL_IMX 163 select PINCTRL_IMX
146 help 164 help
@@ -148,7 +166,6 @@ config PINCTRL_IMX51
148 166
149config PINCTRL_IMX53 167config PINCTRL_IMX53
150 bool "IMX53 pinctrl driver" 168 bool "IMX53 pinctrl driver"
151 depends on OF
152 depends on SOC_IMX53 169 depends on SOC_IMX53
153 select PINCTRL_IMX 170 select PINCTRL_IMX
154 help 171 help
@@ -156,7 +173,6 @@ config PINCTRL_IMX53
156 173
157config PINCTRL_IMX6Q 174config PINCTRL_IMX6Q
158 bool "IMX6Q/DL pinctrl driver" 175 bool "IMX6Q/DL pinctrl driver"
159 depends on OF
160 depends on SOC_IMX6Q 176 depends on SOC_IMX6Q
161 select PINCTRL_IMX 177 select PINCTRL_IMX
162 help 178 help
@@ -164,7 +180,6 @@ config PINCTRL_IMX6Q
164 180
165config PINCTRL_IMX6SL 181config PINCTRL_IMX6SL
166 bool "IMX6SL pinctrl driver" 182 bool "IMX6SL pinctrl driver"
167 depends on OF
168 depends on SOC_IMX6SL 183 depends on SOC_IMX6SL
169 select PINCTRL_IMX 184 select PINCTRL_IMX
170 help 185 help
@@ -172,7 +187,6 @@ config PINCTRL_IMX6SL
172 187
173config PINCTRL_VF610 188config PINCTRL_VF610
174 bool "Freescale Vybrid VF610 pinctrl driver" 189 bool "Freescale Vybrid VF610 pinctrl driver"
175 depends on OF
176 depends on SOC_VF610 190 depends on SOC_VF610
177 select PINCTRL_IMX 191 select PINCTRL_IMX
178 help 192 help
@@ -202,6 +216,20 @@ config PINCTRL_IMX28
202 bool 216 bool
203 select PINCTRL_MXS 217 select PINCTRL_MXS
204 218
219config PINCTRL_MSM
220 tristate
221 select PINMUX
222 select PINCONF
223 select GENERIC_PINCONF
224
225config PINCTRL_MSM8X74
226 tristate "Qualcomm 8x74 pin controller driver"
227 depends on GPIOLIB && OF && OF_IRQ
228 select PINCTRL_MSM
229 help
230 This is the pinctrl, pinmux, pinconf and gpiolib driver for the
231 Qualcomm TLMM block found in the Qualcomm 8974 platform.
232
205config PINCTRL_NOMADIK 233config PINCTRL_NOMADIK
206 bool "Nomadik pin controller driver" 234 bool "Nomadik pin controller driver"
207 depends on ARCH_U8500 || ARCH_NOMADIK 235 depends on ARCH_U8500 || ARCH_NOMADIK
@@ -268,6 +296,10 @@ config PINCTRL_TEGRA114
268 bool 296 bool
269 select PINCTRL_TEGRA 297 select PINCTRL_TEGRA
270 298
299config PINCTRL_TEGRA124
300 bool
301 select PINCTRL_TEGRA
302
271config PINCTRL_TZ1090 303config PINCTRL_TZ1090
272 bool "Toumaz Xenif TZ1090 pin control driver" 304 bool "Toumaz Xenif TZ1090 pin control driver"
273 depends on SOC_TZ1090 305 depends on SOC_TZ1090
diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
index 4f7be2921aa5..4b835880cf80 100644
--- a/drivers/pinctrl/Makefile
+++ b/drivers/pinctrl/Makefile
@@ -21,6 +21,7 @@ obj-$(CONFIG_PINCTRL_BF60x) += pinctrl-adi2-bf60x.o
21obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o 21obj-$(CONFIG_PINCTRL_AT91) += pinctrl-at91.o
22obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o 22obj-$(CONFIG_PINCTRL_BCM2835) += pinctrl-bcm2835.o
23obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o 23obj-$(CONFIG_PINCTRL_BAYTRAIL) += pinctrl-baytrail.o
24obj-$(CONFIG_PINCTRL_CAPRI) += pinctrl-capri.o
24obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o 25obj-$(CONFIG_PINCTRL_IMX) += pinctrl-imx.o
25obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o 26obj-$(CONFIG_PINCTRL_IMX1_CORE) += pinctrl-imx1-core.o
26obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o 27obj-$(CONFIG_PINCTRL_IMX27) += pinctrl-imx27.o
@@ -34,7 +35,10 @@ obj-$(CONFIG_PINCTRL_IMX6SL) += pinctrl-imx6sl.o
34obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o 35obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
35obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o 36obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
36obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o 37obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
38obj-$(CONFIG_PINCTRL_IMX25) += pinctrl-imx25.o
37obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o 39obj-$(CONFIG_PINCTRL_IMX28) += pinctrl-imx28.o
40obj-$(CONFIG_PINCTRL_MSM) += pinctrl-msm.o
41obj-$(CONFIG_PINCTRL_MSM8X74) += pinctrl-msm8x74.o
38obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o 42obj-$(CONFIG_PINCTRL_NOMADIK) += pinctrl-nomadik.o
39obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o 43obj-$(CONFIG_PINCTRL_STN8815) += pinctrl-nomadik-stn8815.o
40obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o 44obj-$(CONFIG_PINCTRL_DB8500) += pinctrl-nomadik-db8500.o
@@ -48,6 +52,7 @@ obj-$(CONFIG_PINCTRL_TEGRA) += pinctrl-tegra.o
48obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o 52obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
49obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o 53obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
50obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o 54obj-$(CONFIG_PINCTRL_TEGRA114) += pinctrl-tegra114.o
55obj-$(CONFIG_PINCTRL_TEGRA124) += pinctrl-tegra124.o
51obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o 56obj-$(CONFIG_PINCTRL_TZ1090) += pinctrl-tz1090.o
52obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o 57obj-$(CONFIG_PINCTRL_TZ1090_PDC) += pinctrl-tz1090-pdc.o
53obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o 58obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
diff --git a/drivers/pinctrl/pinconf-generic.c b/drivers/pinctrl/pinconf-generic.c
index 55a0ebe830ac..3d9a999fb699 100644
--- a/drivers/pinctrl/pinconf-generic.c
+++ b/drivers/pinctrl/pinconf-generic.c
@@ -48,6 +48,7 @@ static struct pin_config_item conf_items[] = {
48 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL), 48 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_DRAIN, "output drive open drain", NULL),
49 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL), 49 PCONFDUMP(PIN_CONFIG_DRIVE_OPEN_SOURCE, "output drive open source", NULL),
50 PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA"), 50 PCONFDUMP(PIN_CONFIG_DRIVE_STRENGTH, "output drive strength", "mA"),
51 PCONFDUMP(PIN_CONFIG_INPUT_ENABLE, "input enabled", NULL),
51 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL), 52 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT_ENABLE, "input schmitt enabled", NULL),
52 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL), 53 PCONFDUMP(PIN_CONFIG_INPUT_SCHMITT, "input schmitt trigger", NULL),
53 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec"), 54 PCONFDUMP(PIN_CONFIG_INPUT_DEBOUNCE, "input debounce", "usec"),
@@ -160,6 +161,8 @@ static struct pinconf_generic_dt_params dt_params[] = {
160 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, 161 { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 },
161 { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 }, 162 { "drive-open-source", PIN_CONFIG_DRIVE_OPEN_SOURCE, 0 },
162 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 }, 163 { "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
164 { "input-enable", PIN_CONFIG_INPUT_ENABLE, 1 },
165 { "input-disable", PIN_CONFIG_INPUT_ENABLE, 0 },
163 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, 166 { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 },
164 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, 167 { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 },
165 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, 168 { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 },
@@ -167,6 +170,7 @@ static struct pinconf_generic_dt_params dt_params[] = {
167 { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 }, 170 { "low-power-disable", PIN_CONFIG_LOW_POWER_MODE, 0 },
168 { "output-low", PIN_CONFIG_OUTPUT, 0, }, 171 { "output-low", PIN_CONFIG_OUTPUT, 0, },
169 { "output-high", PIN_CONFIG_OUTPUT, 1, }, 172 { "output-high", PIN_CONFIG_OUTPUT, 1, },
173 { "slew-rate", PIN_CONFIG_SLEW_RATE, 0},
170}; 174};
171 175
172/** 176/**
diff --git a/drivers/pinctrl/pinconf.c b/drivers/pinctrl/pinconf.c
index b8fcc38c0d11..8bfa0643e5dc 100644
--- a/drivers/pinctrl/pinconf.c
+++ b/drivers/pinctrl/pinconf.c
@@ -28,12 +28,6 @@ int pinconf_check_ops(struct pinctrl_dev *pctldev)
28{ 28{
29 const struct pinconf_ops *ops = pctldev->desc->confops; 29 const struct pinconf_ops *ops = pctldev->desc->confops;
30 30
31 /* We must be able to read out pin status */
32 if (!ops->pin_config_get && !ops->pin_config_group_get) {
33 dev_err(pctldev->dev,
34 "pinconf must be able to read out pin status\n");
35 return -EINVAL;
36 }
37 /* We have to be able to config the pins in SOME way */ 31 /* We have to be able to config the pins in SOME way */
38 if (!ops->pin_config_set && !ops->pin_config_group_set) { 32 if (!ops->pin_config_set && !ops->pin_config_group_set) {
39 dev_err(pctldev->dev, 33 dev_err(pctldev->dev,
@@ -67,9 +61,9 @@ int pin_config_get_for_pin(struct pinctrl_dev *pctldev, unsigned pin,
67 const struct pinconf_ops *ops = pctldev->desc->confops; 61 const struct pinconf_ops *ops = pctldev->desc->confops;
68 62
69 if (!ops || !ops->pin_config_get) { 63 if (!ops || !ops->pin_config_get) {
70 dev_err(pctldev->dev, "cannot get pin configuration, missing " 64 dev_dbg(pctldev->dev, "cannot get pin configuration, missing "
71 "pin_config_get() function in driver\n"); 65 "pin_config_get() function in driver\n");
72 return -EINVAL; 66 return -ENOTSUPP;
73 } 67 }
74 68
75 return ops->pin_config_get(pctldev, pin, config); 69 return ops->pin_config_get(pctldev, pin, config);
@@ -93,10 +87,10 @@ int pin_config_group_get(const char *dev_name, const char *pin_group,
93 ops = pctldev->desc->confops; 87 ops = pctldev->desc->confops;
94 88
95 if (!ops || !ops->pin_config_group_get) { 89 if (!ops || !ops->pin_config_group_get) {
96 dev_err(pctldev->dev, "cannot get configuration for pin " 90 dev_dbg(pctldev->dev, "cannot get configuration for pin "
97 "group, missing group config get function in " 91 "group, missing group config get function in "
98 "driver\n"); 92 "driver\n");
99 ret = -EINVAL; 93 ret = -ENOTSUPP;
100 goto unlock; 94 goto unlock;
101 } 95 }
102 96
@@ -302,12 +296,8 @@ static void pinconf_dump_pin(struct pinctrl_dev *pctldev,
302static int pinconf_pins_show(struct seq_file *s, void *what) 296static int pinconf_pins_show(struct seq_file *s, void *what)
303{ 297{
304 struct pinctrl_dev *pctldev = s->private; 298 struct pinctrl_dev *pctldev = s->private;
305 const struct pinconf_ops *ops = pctldev->desc->confops;
306 unsigned i, pin; 299 unsigned i, pin;
307 300
308 if (!ops || !ops->pin_config_get)
309 return 0;
310
311 seq_puts(s, "Pin config settings per pin\n"); 301 seq_puts(s, "Pin config settings per pin\n");
312 seq_puts(s, "Format: pin (name): configs\n"); 302 seq_puts(s, "Format: pin (name): configs\n");
313 303
@@ -352,13 +342,9 @@ static int pinconf_groups_show(struct seq_file *s, void *what)
352{ 342{
353 struct pinctrl_dev *pctldev = s->private; 343 struct pinctrl_dev *pctldev = s->private;
354 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops; 344 const struct pinctrl_ops *pctlops = pctldev->desc->pctlops;
355 const struct pinconf_ops *ops = pctldev->desc->confops;
356 unsigned ngroups = pctlops->get_groups_count(pctldev); 345 unsigned ngroups = pctlops->get_groups_count(pctldev);
357 unsigned selector = 0; 346 unsigned selector = 0;
358 347
359 if (!ops || !ops->pin_config_group_get)
360 return 0;
361
362 seq_puts(s, "Pin config settings per pin group\n"); 348 seq_puts(s, "Pin config settings per pin group\n");
363 seq_puts(s, "Format: group (name): configs\n"); 349 seq_puts(s, "Format: group (name): configs\n");
364 350
diff --git a/drivers/pinctrl/pinctrl-as3722.c b/drivers/pinctrl/pinctrl-as3722.c
index b80f1e150f53..92ed4b2e3c07 100644
--- a/drivers/pinctrl/pinctrl-as3722.c
+++ b/drivers/pinctrl/pinctrl-as3722.c
@@ -250,6 +250,26 @@ static int as3722_pinctrl_enable(struct pinctrl_dev *pctldev, unsigned function,
250 return ret; 250 return ret;
251 } 251 }
252 as_pci->gpio_control[group].io_function = function; 252 as_pci->gpio_control[group].io_function = function;
253
254 switch (val) {
255 case AS3722_GPIO_IOSF_SD0_OUT:
256 case AS3722_GPIO_IOSF_PWR_GOOD_OUT:
257 case AS3722_GPIO_IOSF_Q32K_OUT:
258 case AS3722_GPIO_IOSF_PWM_OUT:
259 case AS3722_GPIO_IOSF_SD6_LOW_VOLT_LOW:
260 ret = as3722_update_bits(as_pci->as3722, gpio_cntr_reg,
261 AS3722_GPIO_MODE_MASK, AS3722_GPIO_MODE_OUTPUT_VDDH);
262 if (ret < 0) {
263 dev_err(as_pci->dev, "GPIO%d_CTRL update failed %d\n",
264 group, ret);
265 return ret;
266 }
267 as_pci->gpio_control[group].mode_prop =
268 AS3722_GPIO_MODE_OUTPUT_VDDH;
269 break;
270 default:
271 break;
272 }
253 return ret; 273 return ret;
254} 274}
255 275
diff --git a/drivers/pinctrl/pinctrl-at91.c b/drivers/pinctrl/pinctrl-at91.c
index 943805185f3f..38c6f8b9790e 100644
--- a/drivers/pinctrl/pinctrl-at91.c
+++ b/drivers/pinctrl/pinctrl-at91.c
@@ -118,7 +118,7 @@ struct at91_pin_group {
118}; 118};
119 119
120/** 120/**
121 * struct at91_pinctrl_mux_ops - describes an At91 mux ops group 121 * struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
122 * on new IP with support for periph C and D the way to mux in 122 * on new IP with support for periph C and D the way to mux in
123 * periph A and B has changed 123 * periph A and B has changed
124 * So provide the right call back 124 * So provide the right call back
@@ -722,7 +722,8 @@ static int at91_pinconf_get(struct pinctrl_dev *pctldev,
722 unsigned pin; 722 unsigned pin;
723 int div; 723 int div;
724 724
725 dev_dbg(info->dev, "%s:%d, pin_id=%d, config=0x%lx", __func__, __LINE__, pin_id, *config); 725 *config = 0;
726 dev_dbg(info->dev, "%s:%d, pin_id=%d", __func__, __LINE__, pin_id);
726 pio = pin_to_controller(info, pin_to_bank(pin_id)); 727 pio = pin_to_controller(info, pin_to_bank(pin_id));
727 pin = pin_id % MAX_NB_GPIO_PER_BANK; 728 pin = pin_id % MAX_NB_GPIO_PER_BANK;
728 729
@@ -783,10 +784,35 @@ static int at91_pinconf_set(struct pinctrl_dev *pctldev,
783 return 0; 784 return 0;
784} 785}
785 786
787#define DBG_SHOW_FLAG(flag) do { \
788 if (config & flag) { \
789 if (num_conf) \
790 seq_puts(s, "|"); \
791 seq_puts(s, #flag); \
792 num_conf++; \
793 } \
794} while (0)
795
786static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev, 796static void at91_pinconf_dbg_show(struct pinctrl_dev *pctldev,
787 struct seq_file *s, unsigned pin_id) 797 struct seq_file *s, unsigned pin_id)
788{ 798{
799 unsigned long config;
800 int ret, val, num_conf = 0;
801
802 ret = at91_pinconf_get(pctldev, pin_id, &config);
803
804 DBG_SHOW_FLAG(MULTI_DRIVE);
805 DBG_SHOW_FLAG(PULL_UP);
806 DBG_SHOW_FLAG(PULL_DOWN);
807 DBG_SHOW_FLAG(DIS_SCHMIT);
808 DBG_SHOW_FLAG(DEGLITCH);
809 DBG_SHOW_FLAG(DEBOUNCE);
810 if (config & DEBOUNCE) {
811 val = config >> DEBOUNCE_VAL_SHIFT;
812 seq_printf(s, "(%d)", val);
813 }
789 814
815 return;
790} 816}
791 817
792static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev, 818static void at91_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
@@ -1339,13 +1365,11 @@ void at91_pinctrl_gpio_suspend(void)
1339 __raw_writel(backups[i], pio + PIO_IDR); 1365 __raw_writel(backups[i], pio + PIO_IDR);
1340 __raw_writel(wakeups[i], pio + PIO_IER); 1366 __raw_writel(wakeups[i], pio + PIO_IER);
1341 1367
1342 if (!wakeups[i]) { 1368 if (!wakeups[i])
1343 clk_unprepare(gpio_chips[i]->clock); 1369 clk_disable_unprepare(gpio_chips[i]->clock);
1344 clk_disable(gpio_chips[i]->clock); 1370 else
1345 } else {
1346 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n", 1371 printk(KERN_DEBUG "GPIO-%c may wake for %08x\n",
1347 'A'+i, wakeups[i]); 1372 'A'+i, wakeups[i]);
1348 }
1349 } 1373 }
1350} 1374}
1351 1375
@@ -1361,10 +1385,8 @@ void at91_pinctrl_gpio_resume(void)
1361 1385
1362 pio = gpio_chips[i]->regbase; 1386 pio = gpio_chips[i]->regbase;
1363 1387
1364 if (!wakeups[i]) { 1388 if (!wakeups[i])
1365 if (clk_prepare(gpio_chips[i]->clock) == 0) 1389 clk_prepare_enable(gpio_chips[i]->clock);
1366 clk_enable(gpio_chips[i]->clock);
1367 }
1368 1390
1369 __raw_writel(wakeups[i], pio + PIO_IDR); 1391 __raw_writel(wakeups[i], pio + PIO_IDR);
1370 __raw_writel(backups[i], pio + PIO_IER); 1392 __raw_writel(backups[i], pio + PIO_IER);
@@ -1396,7 +1418,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
1396 chained_irq_enter(chip, desc); 1418 chained_irq_enter(chip, desc);
1397 for (;;) { 1419 for (;;) {
1398 /* Reading ISR acks pending (edge triggered) GPIO interrupts. 1420 /* Reading ISR acks pending (edge triggered) GPIO interrupts.
1399 * When there none are pending, we're finished unless we need 1421 * When there are none pending, we're finished unless we need
1400 * to process multiple banks (like ID_PIOCDE on sam9263). 1422 * to process multiple banks (like ID_PIOCDE on sam9263).
1401 */ 1423 */
1402 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR); 1424 isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
@@ -1505,7 +1527,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
1505 prev = gpio_chips[at91_gpio->pioc_idx - 1]; 1527 prev = gpio_chips[at91_gpio->pioc_idx - 1];
1506 1528
1507 /* The top level handler handles one bank of GPIOs, except 1529 /* The top level handler handles one bank of GPIOs, except
1508 * on some SoC it can handles up to three... 1530 * on some SoC it can handle up to three...
1509 * We only set up the handler for the first of the list. 1531 * We only set up the handler for the first of the list.
1510 */ 1532 */
1511 if (prev && prev->next == at91_gpio) 1533 if (prev && prev->next == at91_gpio)
diff --git a/drivers/pinctrl/pinctrl-baytrail.c b/drivers/pinctrl/pinctrl-baytrail.c
index 72e6a298a1e9..665b96bc0c3a 100644
--- a/drivers/pinctrl/pinctrl-baytrail.c
+++ b/drivers/pinctrl/pinctrl-baytrail.c
@@ -285,13 +285,19 @@ static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
285 spin_lock_irqsave(&vg->lock, flags); 285 spin_lock_irqsave(&vg->lock, flags);
286 286
287 for (i = 0; i < vg->chip.ngpio; i++) { 287 for (i = 0; i < vg->chip.ngpio; i++) {
288 const char *label;
288 offs = vg->range->pins[i] * 16; 289 offs = vg->range->pins[i] * 16;
289 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG); 290 conf0 = readl(vg->reg_base + offs + BYT_CONF0_REG);
290 val = readl(vg->reg_base + offs + BYT_VAL_REG); 291 val = readl(vg->reg_base + offs + BYT_VAL_REG);
291 292
293 label = gpiochip_is_requested(chip, i);
294 if (!label)
295 label = "Unrequested";
296
292 seq_printf(s, 297 seq_printf(s,
293 " gpio-%-3d %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n", 298 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s\n",
294 i, 299 i,
300 label,
295 val & BYT_INPUT_EN ? " " : "in", 301 val & BYT_INPUT_EN ? " " : "in",
296 val & BYT_OUTPUT_EN ? " " : "out", 302 val & BYT_OUTPUT_EN ? " " : "out",
297 val & BYT_LEVEL ? "hi" : "lo", 303 val & BYT_LEVEL ? "hi" : "lo",
@@ -365,11 +371,33 @@ static void byt_irq_mask(struct irq_data *d)
365{ 371{
366} 372}
367 373
374static unsigned int byt_irq_startup(struct irq_data *d)
375{
376 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
377
378 if (gpio_lock_as_irq(&vg->chip, irqd_to_hwirq(d)))
379 dev_err(vg->chip.dev,
380 "unable to lock HW IRQ %lu for IRQ\n",
381 irqd_to_hwirq(d));
382 byt_irq_unmask(d);
383 return 0;
384}
385
386static void byt_irq_shutdown(struct irq_data *d)
387{
388 struct byt_gpio *vg = irq_data_get_irq_chip_data(d);
389
390 byt_irq_mask(d);
391 gpio_unlock_as_irq(&vg->chip, irqd_to_hwirq(d));
392}
393
368static struct irq_chip byt_irqchip = { 394static struct irq_chip byt_irqchip = {
369 .name = "BYT-GPIO", 395 .name = "BYT-GPIO",
370 .irq_mask = byt_irq_mask, 396 .irq_mask = byt_irq_mask,
371 .irq_unmask = byt_irq_unmask, 397 .irq_unmask = byt_irq_unmask,
372 .irq_set_type = byt_irq_type, 398 .irq_set_type = byt_irq_type,
399 .irq_startup = byt_irq_startup,
400 .irq_shutdown = byt_irq_shutdown,
373}; 401};
374 402
375static void byt_gpio_irq_init_hw(struct byt_gpio *vg) 403static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
diff --git a/drivers/pinctrl/pinctrl-capri.c b/drivers/pinctrl/pinctrl-capri.c
new file mode 100644
index 000000000000..4669c53f99b0
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-capri.c
@@ -0,0 +1,1454 @@
1/*
2 * Copyright (C) 2013 Broadcom Corporation
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
7 *
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#include <linux/err.h>
14#include <linux/io.h>
15#include <linux/module.h>
16#include <linux/of.h>
17#include <linux/platform_device.h>
18#include <linux/pinctrl/pinctrl.h>
19#include <linux/pinctrl/pinmux.h>
20#include <linux/pinctrl/pinconf.h>
21#include <linux/pinctrl/pinconf-generic.h>
22#include <linux/regmap.h>
23#include <linux/slab.h>
24#include "core.h"
25#include "pinctrl-utils.h"
26
27/* Capri Pin Control Registers Definitions */
28
29/* Function Select bits are the same for all pin control registers */
30#define CAPRI_PIN_REG_F_SEL_MASK 0x0700
31#define CAPRI_PIN_REG_F_SEL_SHIFT 8
32
33/* Standard pin register */
34#define CAPRI_STD_PIN_REG_DRV_STR_MASK 0x0007
35#define CAPRI_STD_PIN_REG_DRV_STR_SHIFT 0
36#define CAPRI_STD_PIN_REG_INPUT_DIS_MASK 0x0008
37#define CAPRI_STD_PIN_REG_INPUT_DIS_SHIFT 3
38#define CAPRI_STD_PIN_REG_SLEW_MASK 0x0010
39#define CAPRI_STD_PIN_REG_SLEW_SHIFT 4
40#define CAPRI_STD_PIN_REG_PULL_UP_MASK 0x0020
41#define CAPRI_STD_PIN_REG_PULL_UP_SHIFT 5
42#define CAPRI_STD_PIN_REG_PULL_DN_MASK 0x0040
43#define CAPRI_STD_PIN_REG_PULL_DN_SHIFT 6
44#define CAPRI_STD_PIN_REG_HYST_MASK 0x0080
45#define CAPRI_STD_PIN_REG_HYST_SHIFT 7
46
47/* I2C pin register */
48#define CAPRI_I2C_PIN_REG_INPUT_DIS_MASK 0x0004
49#define CAPRI_I2C_PIN_REG_INPUT_DIS_SHIFT 2
50#define CAPRI_I2C_PIN_REG_SLEW_MASK 0x0008
51#define CAPRI_I2C_PIN_REG_SLEW_SHIFT 3
52#define CAPRI_I2C_PIN_REG_PULL_UP_STR_MASK 0x0070
53#define CAPRI_I2C_PIN_REG_PULL_UP_STR_SHIFT 4
54
55/* HDMI pin register */
56#define CAPRI_HDMI_PIN_REG_INPUT_DIS_MASK 0x0008
57#define CAPRI_HDMI_PIN_REG_INPUT_DIS_SHIFT 3
58#define CAPRI_HDMI_PIN_REG_MODE_MASK 0x0010
59#define CAPRI_HDMI_PIN_REG_MODE_SHIFT 4
60
61/**
62 * capri_pin_type - types of pin register
63 */
64enum capri_pin_type {
65 CAPRI_PIN_TYPE_UNKNOWN = 0,
66 CAPRI_PIN_TYPE_STD,
67 CAPRI_PIN_TYPE_I2C,
68 CAPRI_PIN_TYPE_HDMI,
69};
70
71static enum capri_pin_type std_pin = CAPRI_PIN_TYPE_STD;
72static enum capri_pin_type i2c_pin = CAPRI_PIN_TYPE_I2C;
73static enum capri_pin_type hdmi_pin = CAPRI_PIN_TYPE_HDMI;
74
75/**
76 * capri_pin_function- define pin function
77 */
78struct capri_pin_function {
79 const char *name;
80 const char * const *groups;
81 const unsigned ngroups;
82};
83
84/**
85 * capri_pinctrl_data - Broadcom-specific pinctrl data
86 * @reg_base - base of pinctrl registers
87 */
88struct capri_pinctrl_data {
89 void __iomem *reg_base;
90
91 /* List of all pins */
92 const struct pinctrl_pin_desc *pins;
93 const unsigned npins;
94
95 const struct capri_pin_function *functions;
96 const unsigned nfunctions;
97
98 struct regmap *regmap;
99};
100
101/*
102 * Pin number definition. The order here must be the same as defined in the
103 * PADCTRLREG block in the RDB.
104 */
105#define CAPRI_PIN_ADCSYNC 0
106#define CAPRI_PIN_BAT_RM 1
107#define CAPRI_PIN_BSC1_SCL 2
108#define CAPRI_PIN_BSC1_SDA 3
109#define CAPRI_PIN_BSC2_SCL 4
110#define CAPRI_PIN_BSC2_SDA 5
111#define CAPRI_PIN_CLASSGPWR 6
112#define CAPRI_PIN_CLK_CX8 7
113#define CAPRI_PIN_CLKOUT_0 8
114#define CAPRI_PIN_CLKOUT_1 9
115#define CAPRI_PIN_CLKOUT_2 10
116#define CAPRI_PIN_CLKOUT_3 11
117#define CAPRI_PIN_CLKREQ_IN_0 12
118#define CAPRI_PIN_CLKREQ_IN_1 13
119#define CAPRI_PIN_CWS_SYS_REQ1 14
120#define CAPRI_PIN_CWS_SYS_REQ2 15
121#define CAPRI_PIN_CWS_SYS_REQ3 16
122#define CAPRI_PIN_DIGMIC1_CLK 17
123#define CAPRI_PIN_DIGMIC1_DQ 18
124#define CAPRI_PIN_DIGMIC2_CLK 19
125#define CAPRI_PIN_DIGMIC2_DQ 20
126#define CAPRI_PIN_GPEN13 21
127#define CAPRI_PIN_GPEN14 22
128#define CAPRI_PIN_GPEN15 23
129#define CAPRI_PIN_GPIO00 24
130#define CAPRI_PIN_GPIO01 25
131#define CAPRI_PIN_GPIO02 26
132#define CAPRI_PIN_GPIO03 27
133#define CAPRI_PIN_GPIO04 28
134#define CAPRI_PIN_GPIO05 29
135#define CAPRI_PIN_GPIO06 30
136#define CAPRI_PIN_GPIO07 31
137#define CAPRI_PIN_GPIO08 32
138#define CAPRI_PIN_GPIO09 33
139#define CAPRI_PIN_GPIO10 34
140#define CAPRI_PIN_GPIO11 35
141#define CAPRI_PIN_GPIO12 36
142#define CAPRI_PIN_GPIO13 37
143#define CAPRI_PIN_GPIO14 38
144#define CAPRI_PIN_GPS_PABLANK 39
145#define CAPRI_PIN_GPS_TMARK 40
146#define CAPRI_PIN_HDMI_SCL 41
147#define CAPRI_PIN_HDMI_SDA 42
148#define CAPRI_PIN_IC_DM 43
149#define CAPRI_PIN_IC_DP 44
150#define CAPRI_PIN_KP_COL_IP_0 45
151#define CAPRI_PIN_KP_COL_IP_1 46
152#define CAPRI_PIN_KP_COL_IP_2 47
153#define CAPRI_PIN_KP_COL_IP_3 48
154#define CAPRI_PIN_KP_ROW_OP_0 49
155#define CAPRI_PIN_KP_ROW_OP_1 50
156#define CAPRI_PIN_KP_ROW_OP_2 51
157#define CAPRI_PIN_KP_ROW_OP_3 52
158#define CAPRI_PIN_LCD_B_0 53
159#define CAPRI_PIN_LCD_B_1 54
160#define CAPRI_PIN_LCD_B_2 55
161#define CAPRI_PIN_LCD_B_3 56
162#define CAPRI_PIN_LCD_B_4 57
163#define CAPRI_PIN_LCD_B_5 58
164#define CAPRI_PIN_LCD_B_6 59
165#define CAPRI_PIN_LCD_B_7 60
166#define CAPRI_PIN_LCD_G_0 61
167#define CAPRI_PIN_LCD_G_1 62
168#define CAPRI_PIN_LCD_G_2 63
169#define CAPRI_PIN_LCD_G_3 64
170#define CAPRI_PIN_LCD_G_4 65
171#define CAPRI_PIN_LCD_G_5 66
172#define CAPRI_PIN_LCD_G_6 67
173#define CAPRI_PIN_LCD_G_7 68
174#define CAPRI_PIN_LCD_HSYNC 69
175#define CAPRI_PIN_LCD_OE 70
176#define CAPRI_PIN_LCD_PCLK 71
177#define CAPRI_PIN_LCD_R_0 72
178#define CAPRI_PIN_LCD_R_1 73
179#define CAPRI_PIN_LCD_R_2 74
180#define CAPRI_PIN_LCD_R_3 75
181#define CAPRI_PIN_LCD_R_4 76
182#define CAPRI_PIN_LCD_R_5 77
183#define CAPRI_PIN_LCD_R_6 78
184#define CAPRI_PIN_LCD_R_7 79
185#define CAPRI_PIN_LCD_VSYNC 80
186#define CAPRI_PIN_MDMGPIO0 81
187#define CAPRI_PIN_MDMGPIO1 82
188#define CAPRI_PIN_MDMGPIO2 83
189#define CAPRI_PIN_MDMGPIO3 84
190#define CAPRI_PIN_MDMGPIO4 85
191#define CAPRI_PIN_MDMGPIO5 86
192#define CAPRI_PIN_MDMGPIO6 87
193#define CAPRI_PIN_MDMGPIO7 88
194#define CAPRI_PIN_MDMGPIO8 89
195#define CAPRI_PIN_MPHI_DATA_0 90
196#define CAPRI_PIN_MPHI_DATA_1 91
197#define CAPRI_PIN_MPHI_DATA_2 92
198#define CAPRI_PIN_MPHI_DATA_3 93
199#define CAPRI_PIN_MPHI_DATA_4 94
200#define CAPRI_PIN_MPHI_DATA_5 95
201#define CAPRI_PIN_MPHI_DATA_6 96
202#define CAPRI_PIN_MPHI_DATA_7 97
203#define CAPRI_PIN_MPHI_DATA_8 98
204#define CAPRI_PIN_MPHI_DATA_9 99
205#define CAPRI_PIN_MPHI_DATA_10 100
206#define CAPRI_PIN_MPHI_DATA_11 101
207#define CAPRI_PIN_MPHI_DATA_12 102
208#define CAPRI_PIN_MPHI_DATA_13 103
209#define CAPRI_PIN_MPHI_DATA_14 104
210#define CAPRI_PIN_MPHI_DATA_15 105
211#define CAPRI_PIN_MPHI_HA0 106
212#define CAPRI_PIN_MPHI_HAT0 107
213#define CAPRI_PIN_MPHI_HAT1 108
214#define CAPRI_PIN_MPHI_HCE0_N 109
215#define CAPRI_PIN_MPHI_HCE1_N 110
216#define CAPRI_PIN_MPHI_HRD_N 111
217#define CAPRI_PIN_MPHI_HWR_N 112
218#define CAPRI_PIN_MPHI_RUN0 113
219#define CAPRI_PIN_MPHI_RUN1 114
220#define CAPRI_PIN_MTX_SCAN_CLK 115
221#define CAPRI_PIN_MTX_SCAN_DATA 116
222#define CAPRI_PIN_NAND_AD_0 117
223#define CAPRI_PIN_NAND_AD_1 118
224#define CAPRI_PIN_NAND_AD_2 119
225#define CAPRI_PIN_NAND_AD_3 120
226#define CAPRI_PIN_NAND_AD_4 121
227#define CAPRI_PIN_NAND_AD_5 122
228#define CAPRI_PIN_NAND_AD_6 123
229#define CAPRI_PIN_NAND_AD_7 124
230#define CAPRI_PIN_NAND_ALE 125
231#define CAPRI_PIN_NAND_CEN_0 126
232#define CAPRI_PIN_NAND_CEN_1 127
233#define CAPRI_PIN_NAND_CLE 128
234#define CAPRI_PIN_NAND_OEN 129
235#define CAPRI_PIN_NAND_RDY_0 130
236#define CAPRI_PIN_NAND_RDY_1 131
237#define CAPRI_PIN_NAND_WEN 132
238#define CAPRI_PIN_NAND_WP 133
239#define CAPRI_PIN_PC1 134
240#define CAPRI_PIN_PC2 135
241#define CAPRI_PIN_PMU_INT 136
242#define CAPRI_PIN_PMU_SCL 137
243#define CAPRI_PIN_PMU_SDA 138
244#define CAPRI_PIN_RFST2G_MTSLOTEN3G 139
245#define CAPRI_PIN_RGMII_0_RX_CTL 140
246#define CAPRI_PIN_RGMII_0_RXC 141
247#define CAPRI_PIN_RGMII_0_RXD_0 142
248#define CAPRI_PIN_RGMII_0_RXD_1 143
249#define CAPRI_PIN_RGMII_0_RXD_2 144
250#define CAPRI_PIN_RGMII_0_RXD_3 145
251#define CAPRI_PIN_RGMII_0_TX_CTL 146
252#define CAPRI_PIN_RGMII_0_TXC 147
253#define CAPRI_PIN_RGMII_0_TXD_0 148
254#define CAPRI_PIN_RGMII_0_TXD_1 149
255#define CAPRI_PIN_RGMII_0_TXD_2 150
256#define CAPRI_PIN_RGMII_0_TXD_3 151
257#define CAPRI_PIN_RGMII_1_RX_CTL 152
258#define CAPRI_PIN_RGMII_1_RXC 153
259#define CAPRI_PIN_RGMII_1_RXD_0 154
260#define CAPRI_PIN_RGMII_1_RXD_1 155
261#define CAPRI_PIN_RGMII_1_RXD_2 156
262#define CAPRI_PIN_RGMII_1_RXD_3 157
263#define CAPRI_PIN_RGMII_1_TX_CTL 158
264#define CAPRI_PIN_RGMII_1_TXC 159
265#define CAPRI_PIN_RGMII_1_TXD_0 160
266#define CAPRI_PIN_RGMII_1_TXD_1 161
267#define CAPRI_PIN_RGMII_1_TXD_2 162
268#define CAPRI_PIN_RGMII_1_TXD_3 163
269#define CAPRI_PIN_RGMII_GPIO_0 164
270#define CAPRI_PIN_RGMII_GPIO_1 165
271#define CAPRI_PIN_RGMII_GPIO_2 166
272#define CAPRI_PIN_RGMII_GPIO_3 167
273#define CAPRI_PIN_RTXDATA2G_TXDATA3G1 168
274#define CAPRI_PIN_RTXEN2G_TXDATA3G2 169
275#define CAPRI_PIN_RXDATA3G0 170
276#define CAPRI_PIN_RXDATA3G1 171
277#define CAPRI_PIN_RXDATA3G2 172
278#define CAPRI_PIN_SDIO1_CLK 173
279#define CAPRI_PIN_SDIO1_CMD 174
280#define CAPRI_PIN_SDIO1_DATA_0 175
281#define CAPRI_PIN_SDIO1_DATA_1 176
282#define CAPRI_PIN_SDIO1_DATA_2 177
283#define CAPRI_PIN_SDIO1_DATA_3 178
284#define CAPRI_PIN_SDIO4_CLK 179
285#define CAPRI_PIN_SDIO4_CMD 180
286#define CAPRI_PIN_SDIO4_DATA_0 181
287#define CAPRI_PIN_SDIO4_DATA_1 182
288#define CAPRI_PIN_SDIO4_DATA_2 183
289#define CAPRI_PIN_SDIO4_DATA_3 184
290#define CAPRI_PIN_SIM_CLK 185
291#define CAPRI_PIN_SIM_DATA 186
292#define CAPRI_PIN_SIM_DET 187
293#define CAPRI_PIN_SIM_RESETN 188
294#define CAPRI_PIN_SIM2_CLK 189
295#define CAPRI_PIN_SIM2_DATA 190
296#define CAPRI_PIN_SIM2_DET 191
297#define CAPRI_PIN_SIM2_RESETN 192
298#define CAPRI_PIN_SRI_C 193
299#define CAPRI_PIN_SRI_D 194
300#define CAPRI_PIN_SRI_E 195
301#define CAPRI_PIN_SSP_EXTCLK 196
302#define CAPRI_PIN_SSP0_CLK 197
303#define CAPRI_PIN_SSP0_FS 198
304#define CAPRI_PIN_SSP0_RXD 199
305#define CAPRI_PIN_SSP0_TXD 200
306#define CAPRI_PIN_SSP2_CLK 201
307#define CAPRI_PIN_SSP2_FS_0 202
308#define CAPRI_PIN_SSP2_FS_1 203
309#define CAPRI_PIN_SSP2_FS_2 204
310#define CAPRI_PIN_SSP2_FS_3 205
311#define CAPRI_PIN_SSP2_RXD_0 206
312#define CAPRI_PIN_SSP2_RXD_1 207
313#define CAPRI_PIN_SSP2_TXD_0 208
314#define CAPRI_PIN_SSP2_TXD_1 209
315#define CAPRI_PIN_SSP3_CLK 210
316#define CAPRI_PIN_SSP3_FS 211
317#define CAPRI_PIN_SSP3_RXD 212
318#define CAPRI_PIN_SSP3_TXD 213
319#define CAPRI_PIN_SSP4_CLK 214
320#define CAPRI_PIN_SSP4_FS 215
321#define CAPRI_PIN_SSP4_RXD 216
322#define CAPRI_PIN_SSP4_TXD 217
323#define CAPRI_PIN_SSP5_CLK 218
324#define CAPRI_PIN_SSP5_FS 219
325#define CAPRI_PIN_SSP5_RXD 220
326#define CAPRI_PIN_SSP5_TXD 221
327#define CAPRI_PIN_SSP6_CLK 222
328#define CAPRI_PIN_SSP6_FS 223
329#define CAPRI_PIN_SSP6_RXD 224
330#define CAPRI_PIN_SSP6_TXD 225
331#define CAPRI_PIN_STAT_1 226
332#define CAPRI_PIN_STAT_2 227
333#define CAPRI_PIN_SYSCLKEN 228
334#define CAPRI_PIN_TRACECLK 229
335#define CAPRI_PIN_TRACEDT00 230
336#define CAPRI_PIN_TRACEDT01 231
337#define CAPRI_PIN_TRACEDT02 232
338#define CAPRI_PIN_TRACEDT03 233
339#define CAPRI_PIN_TRACEDT04 234
340#define CAPRI_PIN_TRACEDT05 235
341#define CAPRI_PIN_TRACEDT06 236
342#define CAPRI_PIN_TRACEDT07 237
343#define CAPRI_PIN_TRACEDT08 238
344#define CAPRI_PIN_TRACEDT09 239
345#define CAPRI_PIN_TRACEDT10 240
346#define CAPRI_PIN_TRACEDT11 241
347#define CAPRI_PIN_TRACEDT12 242
348#define CAPRI_PIN_TRACEDT13 243
349#define CAPRI_PIN_TRACEDT14 244
350#define CAPRI_PIN_TRACEDT15 245
351#define CAPRI_PIN_TXDATA3G0 246
352#define CAPRI_PIN_TXPWRIND 247
353#define CAPRI_PIN_UARTB1_UCTS 248
354#define CAPRI_PIN_UARTB1_URTS 249
355#define CAPRI_PIN_UARTB1_URXD 250
356#define CAPRI_PIN_UARTB1_UTXD 251
357#define CAPRI_PIN_UARTB2_URXD 252
358#define CAPRI_PIN_UARTB2_UTXD 253
359#define CAPRI_PIN_UARTB3_UCTS 254
360#define CAPRI_PIN_UARTB3_URTS 255
361#define CAPRI_PIN_UARTB3_URXD 256
362#define CAPRI_PIN_UARTB3_UTXD 257
363#define CAPRI_PIN_UARTB4_UCTS 258
364#define CAPRI_PIN_UARTB4_URTS 259
365#define CAPRI_PIN_UARTB4_URXD 260
366#define CAPRI_PIN_UARTB4_UTXD 261
367#define CAPRI_PIN_VC_CAM1_SCL 262
368#define CAPRI_PIN_VC_CAM1_SDA 263
369#define CAPRI_PIN_VC_CAM2_SCL 264
370#define CAPRI_PIN_VC_CAM2_SDA 265
371#define CAPRI_PIN_VC_CAM3_SCL 266
372#define CAPRI_PIN_VC_CAM3_SDA 267
373
374#define CAPRI_PIN_DESC(a, b, c) \
375 { .number = a, .name = b, .drv_data = &c##_pin }
376
377/*
378 * Pin description definition. The order here must be the same as defined in
379 * the PADCTRLREG block in the RDB, since the pin number is used as an index
380 * into this array.
381 */
382static const struct pinctrl_pin_desc capri_pinctrl_pins[] = {
383 CAPRI_PIN_DESC(CAPRI_PIN_ADCSYNC, "adcsync", std),
384 CAPRI_PIN_DESC(CAPRI_PIN_BAT_RM, "bat_rm", std),
385 CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SCL, "bsc1_scl", i2c),
386 CAPRI_PIN_DESC(CAPRI_PIN_BSC1_SDA, "bsc1_sda", i2c),
387 CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SCL, "bsc2_scl", i2c),
388 CAPRI_PIN_DESC(CAPRI_PIN_BSC2_SDA, "bsc2_sda", i2c),
389 CAPRI_PIN_DESC(CAPRI_PIN_CLASSGPWR, "classgpwr", std),
390 CAPRI_PIN_DESC(CAPRI_PIN_CLK_CX8, "clk_cx8", std),
391 CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_0, "clkout_0", std),
392 CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_1, "clkout_1", std),
393 CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_2, "clkout_2", std),
394 CAPRI_PIN_DESC(CAPRI_PIN_CLKOUT_3, "clkout_3", std),
395 CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_0, "clkreq_in_0", std),
396 CAPRI_PIN_DESC(CAPRI_PIN_CLKREQ_IN_1, "clkreq_in_1", std),
397 CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ1, "cws_sys_req1", std),
398 CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ2, "cws_sys_req2", std),
399 CAPRI_PIN_DESC(CAPRI_PIN_CWS_SYS_REQ3, "cws_sys_req3", std),
400 CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_CLK, "digmic1_clk", std),
401 CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC1_DQ, "digmic1_dq", std),
402 CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_CLK, "digmic2_clk", std),
403 CAPRI_PIN_DESC(CAPRI_PIN_DIGMIC2_DQ, "digmic2_dq", std),
404 CAPRI_PIN_DESC(CAPRI_PIN_GPEN13, "gpen13", std),
405 CAPRI_PIN_DESC(CAPRI_PIN_GPEN14, "gpen14", std),
406 CAPRI_PIN_DESC(CAPRI_PIN_GPEN15, "gpen15", std),
407 CAPRI_PIN_DESC(CAPRI_PIN_GPIO00, "gpio00", std),
408 CAPRI_PIN_DESC(CAPRI_PIN_GPIO01, "gpio01", std),
409 CAPRI_PIN_DESC(CAPRI_PIN_GPIO02, "gpio02", std),
410 CAPRI_PIN_DESC(CAPRI_PIN_GPIO03, "gpio03", std),
411 CAPRI_PIN_DESC(CAPRI_PIN_GPIO04, "gpio04", std),
412 CAPRI_PIN_DESC(CAPRI_PIN_GPIO05, "gpio05", std),
413 CAPRI_PIN_DESC(CAPRI_PIN_GPIO06, "gpio06", std),
414 CAPRI_PIN_DESC(CAPRI_PIN_GPIO07, "gpio07", std),
415 CAPRI_PIN_DESC(CAPRI_PIN_GPIO08, "gpio08", std),
416 CAPRI_PIN_DESC(CAPRI_PIN_GPIO09, "gpio09", std),
417 CAPRI_PIN_DESC(CAPRI_PIN_GPIO10, "gpio10", std),
418 CAPRI_PIN_DESC(CAPRI_PIN_GPIO11, "gpio11", std),
419 CAPRI_PIN_DESC(CAPRI_PIN_GPIO12, "gpio12", std),
420 CAPRI_PIN_DESC(CAPRI_PIN_GPIO13, "gpio13", std),
421 CAPRI_PIN_DESC(CAPRI_PIN_GPIO14, "gpio14", std),
422 CAPRI_PIN_DESC(CAPRI_PIN_GPS_PABLANK, "gps_pablank", std),
423 CAPRI_PIN_DESC(CAPRI_PIN_GPS_TMARK, "gps_tmark", std),
424 CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SCL, "hdmi_scl", hdmi),
425 CAPRI_PIN_DESC(CAPRI_PIN_HDMI_SDA, "hdmi_sda", hdmi),
426 CAPRI_PIN_DESC(CAPRI_PIN_IC_DM, "ic_dm", std),
427 CAPRI_PIN_DESC(CAPRI_PIN_IC_DP, "ic_dp", std),
428 CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_0, "kp_col_ip_0", std),
429 CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_1, "kp_col_ip_1", std),
430 CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_2, "kp_col_ip_2", std),
431 CAPRI_PIN_DESC(CAPRI_PIN_KP_COL_IP_3, "kp_col_ip_3", std),
432 CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_0, "kp_row_op_0", std),
433 CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_1, "kp_row_op_1", std),
434 CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_2, "kp_row_op_2", std),
435 CAPRI_PIN_DESC(CAPRI_PIN_KP_ROW_OP_3, "kp_row_op_3", std),
436 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_0, "lcd_b_0", std),
437 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_1, "lcd_b_1", std),
438 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_2, "lcd_b_2", std),
439 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_3, "lcd_b_3", std),
440 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_4, "lcd_b_4", std),
441 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_5, "lcd_b_5", std),
442 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_6, "lcd_b_6", std),
443 CAPRI_PIN_DESC(CAPRI_PIN_LCD_B_7, "lcd_b_7", std),
444 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_0, "lcd_g_0", std),
445 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_1, "lcd_g_1", std),
446 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_2, "lcd_g_2", std),
447 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_3, "lcd_g_3", std),
448 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_4, "lcd_g_4", std),
449 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_5, "lcd_g_5", std),
450 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_6, "lcd_g_6", std),
451 CAPRI_PIN_DESC(CAPRI_PIN_LCD_G_7, "lcd_g_7", std),
452 CAPRI_PIN_DESC(CAPRI_PIN_LCD_HSYNC, "lcd_hsync", std),
453 CAPRI_PIN_DESC(CAPRI_PIN_LCD_OE, "lcd_oe", std),
454 CAPRI_PIN_DESC(CAPRI_PIN_LCD_PCLK, "lcd_pclk", std),
455 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_0, "lcd_r_0", std),
456 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_1, "lcd_r_1", std),
457 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_2, "lcd_r_2", std),
458 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_3, "lcd_r_3", std),
459 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_4, "lcd_r_4", std),
460 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_5, "lcd_r_5", std),
461 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_6, "lcd_r_6", std),
462 CAPRI_PIN_DESC(CAPRI_PIN_LCD_R_7, "lcd_r_7", std),
463 CAPRI_PIN_DESC(CAPRI_PIN_LCD_VSYNC, "lcd_vsync", std),
464 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO0, "mdmgpio0", std),
465 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO1, "mdmgpio1", std),
466 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO2, "mdmgpio2", std),
467 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO3, "mdmgpio3", std),
468 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO4, "mdmgpio4", std),
469 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO5, "mdmgpio5", std),
470 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO6, "mdmgpio6", std),
471 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO7, "mdmgpio7", std),
472 CAPRI_PIN_DESC(CAPRI_PIN_MDMGPIO8, "mdmgpio8", std),
473 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_0, "mphi_data_0", std),
474 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_1, "mphi_data_1", std),
475 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_2, "mphi_data_2", std),
476 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_3, "mphi_data_3", std),
477 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_4, "mphi_data_4", std),
478 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_5, "mphi_data_5", std),
479 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_6, "mphi_data_6", std),
480 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_7, "mphi_data_7", std),
481 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_8, "mphi_data_8", std),
482 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_9, "mphi_data_9", std),
483 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_10, "mphi_data_10", std),
484 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_11, "mphi_data_11", std),
485 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_12, "mphi_data_12", std),
486 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_13, "mphi_data_13", std),
487 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_14, "mphi_data_14", std),
488 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_DATA_15, "mphi_data_15", std),
489 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HA0, "mphi_ha0", std),
490 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT0, "mphi_hat0", std),
491 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HAT1, "mphi_hat1", std),
492 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE0_N, "mphi_hce0_n", std),
493 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HCE1_N, "mphi_hce1_n", std),
494 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HRD_N, "mphi_hrd_n", std),
495 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_HWR_N, "mphi_hwr_n", std),
496 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN0, "mphi_run0", std),
497 CAPRI_PIN_DESC(CAPRI_PIN_MPHI_RUN1, "mphi_run1", std),
498 CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_CLK, "mtx_scan_clk", std),
499 CAPRI_PIN_DESC(CAPRI_PIN_MTX_SCAN_DATA, "mtx_scan_data", std),
500 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_0, "nand_ad_0", std),
501 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_1, "nand_ad_1", std),
502 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_2, "nand_ad_2", std),
503 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_3, "nand_ad_3", std),
504 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_4, "nand_ad_4", std),
505 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_5, "nand_ad_5", std),
506 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_6, "nand_ad_6", std),
507 CAPRI_PIN_DESC(CAPRI_PIN_NAND_AD_7, "nand_ad_7", std),
508 CAPRI_PIN_DESC(CAPRI_PIN_NAND_ALE, "nand_ale", std),
509 CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_0, "nand_cen_0", std),
510 CAPRI_PIN_DESC(CAPRI_PIN_NAND_CEN_1, "nand_cen_1", std),
511 CAPRI_PIN_DESC(CAPRI_PIN_NAND_CLE, "nand_cle", std),
512 CAPRI_PIN_DESC(CAPRI_PIN_NAND_OEN, "nand_oen", std),
513 CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_0, "nand_rdy_0", std),
514 CAPRI_PIN_DESC(CAPRI_PIN_NAND_RDY_1, "nand_rdy_1", std),
515 CAPRI_PIN_DESC(CAPRI_PIN_NAND_WEN, "nand_wen", std),
516 CAPRI_PIN_DESC(CAPRI_PIN_NAND_WP, "nand_wp", std),
517 CAPRI_PIN_DESC(CAPRI_PIN_PC1, "pc1", std),
518 CAPRI_PIN_DESC(CAPRI_PIN_PC2, "pc2", std),
519 CAPRI_PIN_DESC(CAPRI_PIN_PMU_INT, "pmu_int", std),
520 CAPRI_PIN_DESC(CAPRI_PIN_PMU_SCL, "pmu_scl", i2c),
521 CAPRI_PIN_DESC(CAPRI_PIN_PMU_SDA, "pmu_sda", i2c),
522 CAPRI_PIN_DESC(CAPRI_PIN_RFST2G_MTSLOTEN3G, "rfst2g_mtsloten3g", std),
523 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RX_CTL, "rgmii_0_rx_ctl", std),
524 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXC, "rgmii_0_rxc", std),
525 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_0, "rgmii_0_rxd_0", std),
526 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_1, "rgmii_0_rxd_1", std),
527 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_2, "rgmii_0_rxd_2", std),
528 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_RXD_3, "rgmii_0_rxd_3", std),
529 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TX_CTL, "rgmii_0_tx_ctl", std),
530 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXC, "rgmii_0_txc", std),
531 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_0, "rgmii_0_txd_0", std),
532 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_1, "rgmii_0_txd_1", std),
533 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_2, "rgmii_0_txd_2", std),
534 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_0_TXD_3, "rgmii_0_txd_3", std),
535 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RX_CTL, "rgmii_1_rx_ctl", std),
536 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXC, "rgmii_1_rxc", std),
537 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_0, "rgmii_1_rxd_0", std),
538 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_1, "rgmii_1_rxd_1", std),
539 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_2, "rgmii_1_rxd_2", std),
540 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_RXD_3, "rgmii_1_rxd_3", std),
541 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TX_CTL, "rgmii_1_tx_ctl", std),
542 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXC, "rgmii_1_txc", std),
543 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_0, "rgmii_1_txd_0", std),
544 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_1, "rgmii_1_txd_1", std),
545 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_2, "rgmii_1_txd_2", std),
546 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_1_TXD_3, "rgmii_1_txd_3", std),
547 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_0, "rgmii_gpio_0", std),
548 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_1, "rgmii_gpio_1", std),
549 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_2, "rgmii_gpio_2", std),
550 CAPRI_PIN_DESC(CAPRI_PIN_RGMII_GPIO_3, "rgmii_gpio_3", std),
551 CAPRI_PIN_DESC(CAPRI_PIN_RTXDATA2G_TXDATA3G1, "rtxdata2g_txdata3g1",
552 std),
553 CAPRI_PIN_DESC(CAPRI_PIN_RTXEN2G_TXDATA3G2, "rtxen2g_txdata3g2", std),
554 CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G0, "rxdata3g0", std),
555 CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G1, "rxdata3g1", std),
556 CAPRI_PIN_DESC(CAPRI_PIN_RXDATA3G2, "rxdata3g2", std),
557 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CLK, "sdio1_clk", std),
558 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_CMD, "sdio1_cmd", std),
559 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_0, "sdio1_data_0", std),
560 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_1, "sdio1_data_1", std),
561 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_2, "sdio1_data_2", std),
562 CAPRI_PIN_DESC(CAPRI_PIN_SDIO1_DATA_3, "sdio1_data_3", std),
563 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CLK, "sdio4_clk", std),
564 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_CMD, "sdio4_cmd", std),
565 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_0, "sdio4_data_0", std),
566 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_1, "sdio4_data_1", std),
567 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_2, "sdio4_data_2", std),
568 CAPRI_PIN_DESC(CAPRI_PIN_SDIO4_DATA_3, "sdio4_data_3", std),
569 CAPRI_PIN_DESC(CAPRI_PIN_SIM_CLK, "sim_clk", std),
570 CAPRI_PIN_DESC(CAPRI_PIN_SIM_DATA, "sim_data", std),
571 CAPRI_PIN_DESC(CAPRI_PIN_SIM_DET, "sim_det", std),
572 CAPRI_PIN_DESC(CAPRI_PIN_SIM_RESETN, "sim_resetn", std),
573 CAPRI_PIN_DESC(CAPRI_PIN_SIM2_CLK, "sim2_clk", std),
574 CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DATA, "sim2_data", std),
575 CAPRI_PIN_DESC(CAPRI_PIN_SIM2_DET, "sim2_det", std),
576 CAPRI_PIN_DESC(CAPRI_PIN_SIM2_RESETN, "sim2_resetn", std),
577 CAPRI_PIN_DESC(CAPRI_PIN_SRI_C, "sri_c", std),
578 CAPRI_PIN_DESC(CAPRI_PIN_SRI_D, "sri_d", std),
579 CAPRI_PIN_DESC(CAPRI_PIN_SRI_E, "sri_e", std),
580 CAPRI_PIN_DESC(CAPRI_PIN_SSP_EXTCLK, "ssp_extclk", std),
581 CAPRI_PIN_DESC(CAPRI_PIN_SSP0_CLK, "ssp0_clk", std),
582 CAPRI_PIN_DESC(CAPRI_PIN_SSP0_FS, "ssp0_fs", std),
583 CAPRI_PIN_DESC(CAPRI_PIN_SSP0_RXD, "ssp0_rxd", std),
584 CAPRI_PIN_DESC(CAPRI_PIN_SSP0_TXD, "ssp0_txd", std),
585 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_CLK, "ssp2_clk", std),
586 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_0, "ssp2_fs_0", std),
587 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_1, "ssp2_fs_1", std),
588 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_2, "ssp2_fs_2", std),
589 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_FS_3, "ssp2_fs_3", std),
590 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_0, "ssp2_rxd_0", std),
591 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_RXD_1, "ssp2_rxd_1", std),
592 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_0, "ssp2_txd_0", std),
593 CAPRI_PIN_DESC(CAPRI_PIN_SSP2_TXD_1, "ssp2_txd_1", std),
594 CAPRI_PIN_DESC(CAPRI_PIN_SSP3_CLK, "ssp3_clk", std),
595 CAPRI_PIN_DESC(CAPRI_PIN_SSP3_FS, "ssp3_fs", std),
596 CAPRI_PIN_DESC(CAPRI_PIN_SSP3_RXD, "ssp3_rxd", std),
597 CAPRI_PIN_DESC(CAPRI_PIN_SSP3_TXD, "ssp3_txd", std),
598 CAPRI_PIN_DESC(CAPRI_PIN_SSP4_CLK, "ssp4_clk", std),
599 CAPRI_PIN_DESC(CAPRI_PIN_SSP4_FS, "ssp4_fs", std),
600 CAPRI_PIN_DESC(CAPRI_PIN_SSP4_RXD, "ssp4_rxd", std),
601 CAPRI_PIN_DESC(CAPRI_PIN_SSP4_TXD, "ssp4_txd", std),
602 CAPRI_PIN_DESC(CAPRI_PIN_SSP5_CLK, "ssp5_clk", std),
603 CAPRI_PIN_DESC(CAPRI_PIN_SSP5_FS, "ssp5_fs", std),
604 CAPRI_PIN_DESC(CAPRI_PIN_SSP5_RXD, "ssp5_rxd", std),
605 CAPRI_PIN_DESC(CAPRI_PIN_SSP5_TXD, "ssp5_txd", std),
606 CAPRI_PIN_DESC(CAPRI_PIN_SSP6_CLK, "ssp6_clk", std),
607 CAPRI_PIN_DESC(CAPRI_PIN_SSP6_FS, "ssp6_fs", std),
608 CAPRI_PIN_DESC(CAPRI_PIN_SSP6_RXD, "ssp6_rxd", std),
609 CAPRI_PIN_DESC(CAPRI_PIN_SSP6_TXD, "ssp6_txd", std),
610 CAPRI_PIN_DESC(CAPRI_PIN_STAT_1, "stat_1", std),
611 CAPRI_PIN_DESC(CAPRI_PIN_STAT_2, "stat_2", std),
612 CAPRI_PIN_DESC(CAPRI_PIN_SYSCLKEN, "sysclken", std),
613 CAPRI_PIN_DESC(CAPRI_PIN_TRACECLK, "traceclk", std),
614 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT00, "tracedt00", std),
615 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT01, "tracedt01", std),
616 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT02, "tracedt02", std),
617 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT03, "tracedt03", std),
618 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT04, "tracedt04", std),
619 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT05, "tracedt05", std),
620 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT06, "tracedt06", std),
621 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT07, "tracedt07", std),
622 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT08, "tracedt08", std),
623 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT09, "tracedt09", std),
624 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT10, "tracedt10", std),
625 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT11, "tracedt11", std),
626 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT12, "tracedt12", std),
627 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT13, "tracedt13", std),
628 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT14, "tracedt14", std),
629 CAPRI_PIN_DESC(CAPRI_PIN_TRACEDT15, "tracedt15", std),
630 CAPRI_PIN_DESC(CAPRI_PIN_TXDATA3G0, "txdata3g0", std),
631 CAPRI_PIN_DESC(CAPRI_PIN_TXPWRIND, "txpwrind", std),
632 CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UCTS, "uartb1_ucts", std),
633 CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URTS, "uartb1_urts", std),
634 CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_URXD, "uartb1_urxd", std),
635 CAPRI_PIN_DESC(CAPRI_PIN_UARTB1_UTXD, "uartb1_utxd", std),
636 CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_URXD, "uartb2_urxd", std),
637 CAPRI_PIN_DESC(CAPRI_PIN_UARTB2_UTXD, "uartb2_utxd", std),
638 CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UCTS, "uartb3_ucts", std),
639 CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URTS, "uartb3_urts", std),
640 CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_URXD, "uartb3_urxd", std),
641 CAPRI_PIN_DESC(CAPRI_PIN_UARTB3_UTXD, "uartb3_utxd", std),
642 CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UCTS, "uartb4_ucts", std),
643 CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URTS, "uartb4_urts", std),
644 CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_URXD, "uartb4_urxd", std),
645 CAPRI_PIN_DESC(CAPRI_PIN_UARTB4_UTXD, "uartb4_utxd", std),
646 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SCL, "vc_cam1_scl", i2c),
647 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM1_SDA, "vc_cam1_sda", i2c),
648 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SCL, "vc_cam2_scl", i2c),
649 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM2_SDA, "vc_cam2_sda", i2c),
650 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SCL, "vc_cam3_scl", i2c),
651 CAPRI_PIN_DESC(CAPRI_PIN_VC_CAM3_SDA, "vc_cam3_sda", i2c),
652};
653
654static const char * const capri_alt_groups[] = {
655 "adcsync",
656 "bat_rm",
657 "bsc1_scl",
658 "bsc1_sda",
659 "bsc2_scl",
660 "bsc2_sda",
661 "classgpwr",
662 "clk_cx8",
663 "clkout_0",
664 "clkout_1",
665 "clkout_2",
666 "clkout_3",
667 "clkreq_in_0",
668 "clkreq_in_1",
669 "cws_sys_req1",
670 "cws_sys_req2",
671 "cws_sys_req3",
672 "digmic1_clk",
673 "digmic1_dq",
674 "digmic2_clk",
675 "digmic2_dq",
676 "gpen13",
677 "gpen14",
678 "gpen15",
679 "gpio00",
680 "gpio01",
681 "gpio02",
682 "gpio03",
683 "gpio04",
684 "gpio05",
685 "gpio06",
686 "gpio07",
687 "gpio08",
688 "gpio09",
689 "gpio10",
690 "gpio11",
691 "gpio12",
692 "gpio13",
693 "gpio14",
694 "gps_pablank",
695 "gps_tmark",
696 "hdmi_scl",
697 "hdmi_sda",
698 "ic_dm",
699 "ic_dp",
700 "kp_col_ip_0",
701 "kp_col_ip_1",
702 "kp_col_ip_2",
703 "kp_col_ip_3",
704 "kp_row_op_0",
705 "kp_row_op_1",
706 "kp_row_op_2",
707 "kp_row_op_3",
708 "lcd_b_0",
709 "lcd_b_1",
710 "lcd_b_2",
711 "lcd_b_3",
712 "lcd_b_4",
713 "lcd_b_5",
714 "lcd_b_6",
715 "lcd_b_7",
716 "lcd_g_0",
717 "lcd_g_1",
718 "lcd_g_2",
719 "lcd_g_3",
720 "lcd_g_4",
721 "lcd_g_5",
722 "lcd_g_6",
723 "lcd_g_7",
724 "lcd_hsync",
725 "lcd_oe",
726 "lcd_pclk",
727 "lcd_r_0",
728 "lcd_r_1",
729 "lcd_r_2",
730 "lcd_r_3",
731 "lcd_r_4",
732 "lcd_r_5",
733 "lcd_r_6",
734 "lcd_r_7",
735 "lcd_vsync",
736 "mdmgpio0",
737 "mdmgpio1",
738 "mdmgpio2",
739 "mdmgpio3",
740 "mdmgpio4",
741 "mdmgpio5",
742 "mdmgpio6",
743 "mdmgpio7",
744 "mdmgpio8",
745 "mphi_data_0",
746 "mphi_data_1",
747 "mphi_data_2",
748 "mphi_data_3",
749 "mphi_data_4",
750 "mphi_data_5",
751 "mphi_data_6",
752 "mphi_data_7",
753 "mphi_data_8",
754 "mphi_data_9",
755 "mphi_data_10",
756 "mphi_data_11",
757 "mphi_data_12",
758 "mphi_data_13",
759 "mphi_data_14",
760 "mphi_data_15",
761 "mphi_ha0",
762 "mphi_hat0",
763 "mphi_hat1",
764 "mphi_hce0_n",
765 "mphi_hce1_n",
766 "mphi_hrd_n",
767 "mphi_hwr_n",
768 "mphi_run0",
769 "mphi_run1",
770 "mtx_scan_clk",
771 "mtx_scan_data",
772 "nand_ad_0",
773 "nand_ad_1",
774 "nand_ad_2",
775 "nand_ad_3",
776 "nand_ad_4",
777 "nand_ad_5",
778 "nand_ad_6",
779 "nand_ad_7",
780 "nand_ale",
781 "nand_cen_0",
782 "nand_cen_1",
783 "nand_cle",
784 "nand_oen",
785 "nand_rdy_0",
786 "nand_rdy_1",
787 "nand_wen",
788 "nand_wp",
789 "pc1",
790 "pc2",
791 "pmu_int",
792 "pmu_scl",
793 "pmu_sda",
794 "rfst2g_mtsloten3g",
795 "rgmii_0_rx_ctl",
796 "rgmii_0_rxc",
797 "rgmii_0_rxd_0",
798 "rgmii_0_rxd_1",
799 "rgmii_0_rxd_2",
800 "rgmii_0_rxd_3",
801 "rgmii_0_tx_ctl",
802 "rgmii_0_txc",
803 "rgmii_0_txd_0",
804 "rgmii_0_txd_1",
805 "rgmii_0_txd_2",
806 "rgmii_0_txd_3",
807 "rgmii_1_rx_ctl",
808 "rgmii_1_rxc",
809 "rgmii_1_rxd_0",
810 "rgmii_1_rxd_1",
811 "rgmii_1_rxd_2",
812 "rgmii_1_rxd_3",
813 "rgmii_1_tx_ctl",
814 "rgmii_1_txc",
815 "rgmii_1_txd_0",
816 "rgmii_1_txd_1",
817 "rgmii_1_txd_2",
818 "rgmii_1_txd_3",
819 "rgmii_gpio_0",
820 "rgmii_gpio_1",
821 "rgmii_gpio_2",
822 "rgmii_gpio_3",
823 "rtxdata2g_txdata3g1",
824 "rtxen2g_txdata3g2",
825 "rxdata3g0",
826 "rxdata3g1",
827 "rxdata3g2",
828 "sdio1_clk",
829 "sdio1_cmd",
830 "sdio1_data_0",
831 "sdio1_data_1",
832 "sdio1_data_2",
833 "sdio1_data_3",
834 "sdio4_clk",
835 "sdio4_cmd",
836 "sdio4_data_0",
837 "sdio4_data_1",
838 "sdio4_data_2",
839 "sdio4_data_3",
840 "sim_clk",
841 "sim_data",
842 "sim_det",
843 "sim_resetn",
844 "sim2_clk",
845 "sim2_data",
846 "sim2_det",
847 "sim2_resetn",
848 "sri_c",
849 "sri_d",
850 "sri_e",
851 "ssp_extclk",
852 "ssp0_clk",
853 "ssp0_fs",
854 "ssp0_rxd",
855 "ssp0_txd",
856 "ssp2_clk",
857 "ssp2_fs_0",
858 "ssp2_fs_1",
859 "ssp2_fs_2",
860 "ssp2_fs_3",
861 "ssp2_rxd_0",
862 "ssp2_rxd_1",
863 "ssp2_txd_0",
864 "ssp2_txd_1",
865 "ssp3_clk",
866 "ssp3_fs",
867 "ssp3_rxd",
868 "ssp3_txd",
869 "ssp4_clk",
870 "ssp4_fs",
871 "ssp4_rxd",
872 "ssp4_txd",
873 "ssp5_clk",
874 "ssp5_fs",
875 "ssp5_rxd",
876 "ssp5_txd",
877 "ssp6_clk",
878 "ssp6_fs",
879 "ssp6_rxd",
880 "ssp6_txd",
881 "stat_1",
882 "stat_2",
883 "sysclken",
884 "traceclk",
885 "tracedt00",
886 "tracedt01",
887 "tracedt02",
888 "tracedt03",
889 "tracedt04",
890 "tracedt05",
891 "tracedt06",
892 "tracedt07",
893 "tracedt08",
894 "tracedt09",
895 "tracedt10",
896 "tracedt11",
897 "tracedt12",
898 "tracedt13",
899 "tracedt14",
900 "tracedt15",
901 "txdata3g0",
902 "txpwrind",
903 "uartb1_ucts",
904 "uartb1_urts",
905 "uartb1_urxd",
906 "uartb1_utxd",
907 "uartb2_urxd",
908 "uartb2_utxd",
909 "uartb3_ucts",
910 "uartb3_urts",
911 "uartb3_urxd",
912 "uartb3_utxd",
913 "uartb4_ucts",
914 "uartb4_urts",
915 "uartb4_urxd",
916 "uartb4_utxd",
917 "vc_cam1_scl",
918 "vc_cam1_sda",
919 "vc_cam2_scl",
920 "vc_cam2_sda",
921 "vc_cam3_scl",
922 "vc_cam3_sda",
923};
924
925/* Every pin can implement all ALT1-ALT4 functions */
926#define CAPRI_PIN_FUNCTION(fcn_name) \
927{ \
928 .name = #fcn_name, \
929 .groups = capri_alt_groups, \
930 .ngroups = ARRAY_SIZE(capri_alt_groups), \
931}
932
933static const struct capri_pin_function capri_functions[] = {
934 CAPRI_PIN_FUNCTION(alt1),
935 CAPRI_PIN_FUNCTION(alt2),
936 CAPRI_PIN_FUNCTION(alt3),
937 CAPRI_PIN_FUNCTION(alt4),
938};
939
940static struct capri_pinctrl_data capri_pinctrl = {
941 .pins = capri_pinctrl_pins,
942 .npins = ARRAY_SIZE(capri_pinctrl_pins),
943 .functions = capri_functions,
944 .nfunctions = ARRAY_SIZE(capri_functions),
945};
946
947static inline enum capri_pin_type pin_type_get(struct pinctrl_dev *pctldev,
948 unsigned pin)
949{
950 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
951
952 if (pin >= pdata->npins)
953 return CAPRI_PIN_TYPE_UNKNOWN;
954
955 return *(enum capri_pin_type *)(pdata->pins[pin].drv_data);
956}
957
958#define CAPRI_PIN_SHIFT(type, param) \
959 (CAPRI_ ## type ## _PIN_REG_ ## param ## _SHIFT)
960
961#define CAPRI_PIN_MASK(type, param) \
962 (CAPRI_ ## type ## _PIN_REG_ ## param ## _MASK)
963
964/*
965 * This helper function is used to build up the value and mask used to write to
966 * a pin register, but does not actually write to the register.
967 */
968static inline void capri_pin_update(u32 *reg_val, u32 *reg_mask, u32 param_val,
969 u32 param_shift, u32 param_mask)
970{
971 *reg_val &= ~param_mask;
972 *reg_val |= (param_val << param_shift) & param_mask;
973 *reg_mask |= param_mask;
974}
975
976static struct regmap_config capri_pinctrl_regmap_config = {
977 .reg_bits = 32,
978 .reg_stride = 4,
979 .val_bits = 32,
980 .max_register = CAPRI_PIN_VC_CAM3_SDA,
981};
982
983static int capri_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
984{
985 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
986
987 return pdata->npins;
988}
989
990static const char *capri_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
991 unsigned group)
992{
993 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
994
995 return pdata->pins[group].name;
996}
997
998static int capri_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
999 unsigned group,
1000 const unsigned **pins,
1001 unsigned *num_pins)
1002{
1003 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1004
1005 *pins = &pdata->pins[group].number;
1006 *num_pins = 1;
1007
1008 return 0;
1009}
1010
1011static void capri_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
1012 struct seq_file *s,
1013 unsigned offset)
1014{
1015 seq_printf(s, " %s", dev_name(pctldev->dev));
1016}
1017
1018static struct pinctrl_ops capri_pinctrl_ops = {
1019 .get_groups_count = capri_pinctrl_get_groups_count,
1020 .get_group_name = capri_pinctrl_get_group_name,
1021 .get_group_pins = capri_pinctrl_get_group_pins,
1022 .pin_dbg_show = capri_pinctrl_pin_dbg_show,
1023 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
1024 .dt_free_map = pinctrl_utils_dt_free_map,
1025};
1026
1027static int capri_pinctrl_get_fcns_count(struct pinctrl_dev *pctldev)
1028{
1029 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1030
1031 return pdata->nfunctions;
1032}
1033
1034static const char *capri_pinctrl_get_fcn_name(struct pinctrl_dev *pctldev,
1035 unsigned function)
1036{
1037 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1038
1039 return pdata->functions[function].name;
1040}
1041
1042static int capri_pinctrl_get_fcn_groups(struct pinctrl_dev *pctldev,
1043 unsigned function,
1044 const char * const **groups,
1045 unsigned * const num_groups)
1046{
1047 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1048
1049 *groups = pdata->functions[function].groups;
1050 *num_groups = pdata->functions[function].ngroups;
1051
1052 return 0;
1053}
1054
1055static int capri_pinmux_enable(struct pinctrl_dev *pctldev,
1056 unsigned function,
1057 unsigned group)
1058{
1059 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1060 const struct capri_pin_function *f = &pdata->functions[function];
1061 u32 offset = 4 * pdata->pins[group].number;
1062 int rc = 0;
1063
1064 dev_dbg(pctldev->dev,
1065 "%s(): Enable function %s (%d) of pin %s (%d) @offset 0x%x.\n",
1066 __func__, f->name, function, pdata->pins[group].name,
1067 pdata->pins[group].number, offset);
1068
1069 rc = regmap_update_bits(pdata->regmap, offset, CAPRI_PIN_REG_F_SEL_MASK,
1070 function << CAPRI_PIN_REG_F_SEL_SHIFT);
1071 if (rc)
1072 dev_err(pctldev->dev,
1073 "Error updating register for pin %s (%d).\n",
1074 pdata->pins[group].name, pdata->pins[group].number);
1075
1076 return rc;
1077}
1078
1079static struct pinmux_ops capri_pinctrl_pinmux_ops = {
1080 .get_functions_count = capri_pinctrl_get_fcns_count,
1081 .get_function_name = capri_pinctrl_get_fcn_name,
1082 .get_function_groups = capri_pinctrl_get_fcn_groups,
1083 .enable = capri_pinmux_enable,
1084};
1085
1086static int capri_pinctrl_pin_config_get(struct pinctrl_dev *pctldev,
1087 unsigned pin,
1088 unsigned long *config)
1089{
1090 return -ENOTSUPP;
1091}
1092
1093
1094/* Goes through the configs and update register val/mask */
1095static int capri_std_pin_update(struct pinctrl_dev *pctldev,
1096 unsigned pin,
1097 unsigned long *configs,
1098 unsigned num_configs,
1099 u32 *val,
1100 u32 *mask)
1101{
1102 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1103 int i;
1104 enum pin_config_param param;
1105 u16 arg;
1106
1107 for (i = 0; i < num_configs; i++) {
1108 param = pinconf_to_config_param(configs[i]);
1109 arg = pinconf_to_config_argument(configs[i]);
1110
1111 switch (param) {
1112 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
1113 arg = (arg >= 1 ? 1 : 0);
1114 capri_pin_update(val, mask, arg,
1115 CAPRI_PIN_SHIFT(STD, HYST),
1116 CAPRI_PIN_MASK(STD, HYST));
1117 break;
1118 /*
1119 * The pin bias can only be one of pull-up, pull-down, or
1120 * disable. The user does not need to specify a value for the
1121 * property, and the default value from pinconf-generic is
1122 * ignored.
1123 */
1124 case PIN_CONFIG_BIAS_DISABLE:
1125 capri_pin_update(val, mask, 0,
1126 CAPRI_PIN_SHIFT(STD, PULL_UP),
1127 CAPRI_PIN_MASK(STD, PULL_UP));
1128 capri_pin_update(val, mask, 0,
1129 CAPRI_PIN_SHIFT(STD, PULL_DN),
1130 CAPRI_PIN_MASK(STD, PULL_DN));
1131 break;
1132
1133 case PIN_CONFIG_BIAS_PULL_UP:
1134 capri_pin_update(val, mask, 1,
1135 CAPRI_PIN_SHIFT(STD, PULL_UP),
1136 CAPRI_PIN_MASK(STD, PULL_UP));
1137 capri_pin_update(val, mask, 0,
1138 CAPRI_PIN_SHIFT(STD, PULL_DN),
1139 CAPRI_PIN_MASK(STD, PULL_DN));
1140 break;
1141
1142 case PIN_CONFIG_BIAS_PULL_DOWN:
1143 capri_pin_update(val, mask, 0,
1144 CAPRI_PIN_SHIFT(STD, PULL_UP),
1145 CAPRI_PIN_MASK(STD, PULL_UP));
1146 capri_pin_update(val, mask, 1,
1147 CAPRI_PIN_SHIFT(STD, PULL_DN),
1148 CAPRI_PIN_MASK(STD, PULL_DN));
1149 break;
1150
1151 case PIN_CONFIG_SLEW_RATE:
1152 arg = (arg >= 1 ? 1 : 0);
1153 capri_pin_update(val, mask, arg,
1154 CAPRI_PIN_SHIFT(STD, SLEW),
1155 CAPRI_PIN_MASK(STD, SLEW));
1156 break;
1157
1158 case PIN_CONFIG_INPUT_ENABLE:
1159 /* inversed since register is for input _disable_ */
1160 arg = (arg >= 1 ? 0 : 1);
1161 capri_pin_update(val, mask, arg,
1162 CAPRI_PIN_SHIFT(STD, INPUT_DIS),
1163 CAPRI_PIN_MASK(STD, INPUT_DIS));
1164 break;
1165
1166 case PIN_CONFIG_DRIVE_STRENGTH:
1167 /* Valid range is 2-16 mA, even numbers only */
1168 if ((arg < 2) || (arg > 16) || (arg % 2)) {
1169 dev_err(pctldev->dev,
1170 "Invalid Drive Strength value (%d) for "
1171 "pin %s (%d). Valid values are "
1172 "(2..16) mA, even numbers only.\n",
1173 arg, pdata->pins[pin].name, pin);
1174 return -EINVAL;
1175 }
1176 capri_pin_update(val, mask, (arg/2)-1,
1177 CAPRI_PIN_SHIFT(STD, DRV_STR),
1178 CAPRI_PIN_MASK(STD, DRV_STR));
1179 break;
1180
1181 default:
1182 dev_err(pctldev->dev,
1183 "Unrecognized pin config %d for pin %s (%d).\n",
1184 param, pdata->pins[pin].name, pin);
1185 return -EINVAL;
1186
1187 } /* switch config */
1188 } /* for each config */
1189
1190 return 0;
1191}
1192
1193/*
1194 * The pull-up strength for an I2C pin is represented by bits 4-6 in the
1195 * register with the following mapping:
1196 * 0b000: No pull-up
1197 * 0b001: 1200 Ohm
1198 * 0b010: 1800 Ohm
1199 * 0b011: 720 Ohm
1200 * 0b100: 2700 Ohm
1201 * 0b101: 831 Ohm
1202 * 0b110: 1080 Ohm
1203 * 0b111: 568 Ohm
1204 * This array maps pull-up strength in Ohms to register values (1+index).
1205 */
1206static const u16 capri_pullup_map[] = {1200, 1800, 720, 2700, 831, 1080, 568};
1207
1208/* Goes through the configs and update register val/mask */
1209static int capri_i2c_pin_update(struct pinctrl_dev *pctldev,
1210 unsigned pin,
1211 unsigned long *configs,
1212 unsigned num_configs,
1213 u32 *val,
1214 u32 *mask)
1215{
1216 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1217 int i, j;
1218 enum pin_config_param param;
1219 u16 arg;
1220
1221 for (i = 0; i < num_configs; i++) {
1222 param = pinconf_to_config_param(configs[i]);
1223 arg = pinconf_to_config_argument(configs[i]);
1224
1225 switch (param) {
1226 case PIN_CONFIG_BIAS_PULL_UP:
1227 for (j = 0; j < ARRAY_SIZE(capri_pullup_map); j++)
1228 if (capri_pullup_map[j] == arg)
1229 break;
1230
1231 if (j == ARRAY_SIZE(capri_pullup_map)) {
1232 dev_err(pctldev->dev,
1233 "Invalid pull-up value (%d) for pin %s "
1234 "(%d). Valid values are 568, 720, 831, "
1235 "1080, 1200, 1800, 2700 Ohms.\n",
1236 arg, pdata->pins[pin].name, pin);
1237 return -EINVAL;
1238 }
1239
1240 capri_pin_update(val, mask, j+1,
1241 CAPRI_PIN_SHIFT(I2C, PULL_UP_STR),
1242 CAPRI_PIN_MASK(I2C, PULL_UP_STR));
1243 break;
1244
1245 case PIN_CONFIG_BIAS_DISABLE:
1246 capri_pin_update(val, mask, 0,
1247 CAPRI_PIN_SHIFT(I2C, PULL_UP_STR),
1248 CAPRI_PIN_MASK(I2C, PULL_UP_STR));
1249 break;
1250
1251 case PIN_CONFIG_SLEW_RATE:
1252 arg = (arg >= 1 ? 1 : 0);
1253 capri_pin_update(val, mask, arg,
1254 CAPRI_PIN_SHIFT(I2C, SLEW),
1255 CAPRI_PIN_MASK(I2C, SLEW));
1256 break;
1257
1258 case PIN_CONFIG_INPUT_ENABLE:
1259 /* inversed since register is for input _disable_ */
1260 arg = (arg >= 1 ? 0 : 1);
1261 capri_pin_update(val, mask, arg,
1262 CAPRI_PIN_SHIFT(I2C, INPUT_DIS),
1263 CAPRI_PIN_MASK(I2C, INPUT_DIS));
1264 break;
1265
1266 default:
1267 dev_err(pctldev->dev,
1268 "Unrecognized pin config %d for pin %s (%d).\n",
1269 param, pdata->pins[pin].name, pin);
1270 return -EINVAL;
1271
1272 } /* switch config */
1273 } /* for each config */
1274
1275 return 0;
1276}
1277
1278/* Goes through the configs and update register val/mask */
1279static int capri_hdmi_pin_update(struct pinctrl_dev *pctldev,
1280 unsigned pin,
1281 unsigned long *configs,
1282 unsigned num_configs,
1283 u32 *val,
1284 u32 *mask)
1285{
1286 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1287 int i;
1288 enum pin_config_param param;
1289 u16 arg;
1290
1291 for (i = 0; i < num_configs; i++) {
1292 param = pinconf_to_config_param(configs[i]);
1293 arg = pinconf_to_config_argument(configs[i]);
1294
1295 switch (param) {
1296 case PIN_CONFIG_SLEW_RATE:
1297 arg = (arg >= 1 ? 1 : 0);
1298 capri_pin_update(val, mask, arg,
1299 CAPRI_PIN_SHIFT(HDMI, MODE),
1300 CAPRI_PIN_MASK(HDMI, MODE));
1301 break;
1302
1303 case PIN_CONFIG_INPUT_ENABLE:
1304 /* inversed since register is for input _disable_ */
1305 arg = (arg >= 1 ? 0 : 1);
1306 capri_pin_update(val, mask, arg,
1307 CAPRI_PIN_SHIFT(HDMI, INPUT_DIS),
1308 CAPRI_PIN_MASK(HDMI, INPUT_DIS));
1309 break;
1310
1311 default:
1312 dev_err(pctldev->dev,
1313 "Unrecognized pin config %d for pin %s (%d).\n",
1314 param, pdata->pins[pin].name, pin);
1315 return -EINVAL;
1316
1317 } /* switch config */
1318 } /* for each config */
1319
1320 return 0;
1321}
1322
1323static int capri_pinctrl_pin_config_set(struct pinctrl_dev *pctldev,
1324 unsigned pin,
1325 unsigned long *configs,
1326 unsigned num_configs)
1327{
1328 struct capri_pinctrl_data *pdata = pinctrl_dev_get_drvdata(pctldev);
1329 enum capri_pin_type pin_type;
1330 u32 offset = 4 * pin;
1331 u32 cfg_val, cfg_mask;
1332 int rc;
1333
1334 cfg_val = 0;
1335 cfg_mask = 0;
1336 pin_type = pin_type_get(pctldev, pin);
1337
1338 /* Different pins have different configuration options */
1339 switch (pin_type) {
1340 case CAPRI_PIN_TYPE_STD:
1341 rc = capri_std_pin_update(pctldev, pin, configs, num_configs,
1342 &cfg_val, &cfg_mask);
1343 break;
1344
1345 case CAPRI_PIN_TYPE_I2C:
1346 rc = capri_i2c_pin_update(pctldev, pin, configs, num_configs,
1347 &cfg_val, &cfg_mask);
1348 break;
1349
1350 case CAPRI_PIN_TYPE_HDMI:
1351 rc = capri_hdmi_pin_update(pctldev, pin, configs, num_configs,
1352 &cfg_val, &cfg_mask);
1353 break;
1354
1355 default:
1356 dev_err(pctldev->dev, "Unknown pin type for pin %s (%d).\n",
1357 pdata->pins[pin].name, pin);
1358 return -EINVAL;
1359
1360 } /* switch pin type */
1361
1362 if (rc)
1363 return rc;
1364
1365 dev_dbg(pctldev->dev,
1366 "%s(): Set pin %s (%d) with config 0x%x, mask 0x%x\n",
1367 __func__, pdata->pins[pin].name, pin, cfg_val, cfg_mask);
1368
1369 rc = regmap_update_bits(pdata->regmap, offset, cfg_mask, cfg_val);
1370 if (rc) {
1371 dev_err(pctldev->dev,
1372 "Error updating register for pin %s (%d).\n",
1373 pdata->pins[pin].name, pin);
1374 return rc;
1375 }
1376
1377 return 0;
1378}
1379
1380static struct pinconf_ops capri_pinctrl_pinconf_ops = {
1381 .pin_config_get = capri_pinctrl_pin_config_get,
1382 .pin_config_set = capri_pinctrl_pin_config_set,
1383};
1384
1385static struct pinctrl_desc capri_pinctrl_desc = {
1386 /* name, pins, npins members initialized in probe function */
1387 .pctlops = &capri_pinctrl_ops,
1388 .pmxops = &capri_pinctrl_pinmux_ops,
1389 .confops = &capri_pinctrl_pinconf_ops,
1390 .owner = THIS_MODULE,
1391};
1392
1393int __init capri_pinctrl_probe(struct platform_device *pdev)
1394{
1395 struct capri_pinctrl_data *pdata = &capri_pinctrl;
1396 struct resource *res;
1397 struct pinctrl_dev *pctl;
1398
1399 /* So far We can assume there is only 1 bank of registers */
1400 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1401 if (!res) {
1402 dev_err(&pdev->dev, "Missing MEM resource\n");
1403 return -ENODEV;
1404 }
1405
1406 pdata->reg_base = devm_ioremap_resource(&pdev->dev, res);
1407 if (IS_ERR(pdata->reg_base)) {
1408 dev_err(&pdev->dev, "Failed to ioremap MEM resource\n");
1409 return -ENODEV;
1410 }
1411
1412 /* Initialize the dynamic part of pinctrl_desc */
1413 pdata->regmap = devm_regmap_init_mmio(&pdev->dev, pdata->reg_base,
1414 &capri_pinctrl_regmap_config);
1415 if (IS_ERR(pdata->regmap)) {
1416 dev_err(&pdev->dev, "Regmap MMIO init failed.\n");
1417 return -ENODEV;
1418 }
1419
1420 capri_pinctrl_desc.name = dev_name(&pdev->dev);
1421 capri_pinctrl_desc.pins = capri_pinctrl.pins;
1422 capri_pinctrl_desc.npins = capri_pinctrl.npins;
1423
1424 pctl = pinctrl_register(&capri_pinctrl_desc,
1425 &pdev->dev,
1426 pdata);
1427 if (!pctl) {
1428 dev_err(&pdev->dev, "Failed to register pinctrl\n");
1429 return -ENODEV;
1430 }
1431
1432 platform_set_drvdata(pdev, pdata);
1433
1434 return 0;
1435}
1436
1437static struct of_device_id capri_pinctrl_of_match[] = {
1438 { .compatible = "brcm,capri-pinctrl", },
1439 { },
1440};
1441
1442static struct platform_driver capri_pinctrl_driver = {
1443 .driver = {
1444 .name = "bcm-capri-pinctrl",
1445 .owner = THIS_MODULE,
1446 .of_match_table = capri_pinctrl_of_match,
1447 },
1448};
1449
1450module_platform_driver_probe(capri_pinctrl_driver, capri_pinctrl_probe);
1451
1452MODULE_AUTHOR("Sherman Yin <syin@broadcom.com>");
1453MODULE_DESCRIPTION("Broadcom Capri pinctrl driver");
1454MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-imx1-core.c b/drivers/pinctrl/pinctrl-imx1-core.c
index f77914ac081a..17aecde1b51d 100644
--- a/drivers/pinctrl/pinctrl-imx1-core.c
+++ b/drivers/pinctrl/pinctrl-imx1-core.c
@@ -638,6 +638,13 @@ int imx1_pinctrl_core_probe(struct platform_device *pdev,
638 return -EINVAL; 638 return -EINVAL;
639 } 639 }
640 640
641 ret = of_platform_populate(pdev->dev.of_node, NULL, NULL, &pdev->dev);
642 if (ret) {
643 pinctrl_unregister(ipctl->pctl);
644 dev_err(&pdev->dev, "Failed to populate subdevices\n");
645 return ret;
646 }
647
641 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n"); 648 dev_info(&pdev->dev, "initialized IMX pinctrl driver\n");
642 649
643 return 0; 650 return 0;
diff --git a/drivers/pinctrl/pinctrl-imx25.c b/drivers/pinctrl/pinctrl-imx25.c
new file mode 100644
index 000000000000..1aae1b61c4dc
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-imx25.c
@@ -0,0 +1,351 @@
1/*
2 * imx25 pinctrl driver.
3 *
4 * Copyright 2013 Eukréa Electromatique <denis@eukrea.com>
5 *
6 * This driver was mostly copied from the imx51 pinctrl driver which has:
7 *
8 * Copyright (C) 2012 Freescale Semiconductor, Inc.
9 * Copyright (C) 2012 Linaro, Inc.
10 *
11 * Author: Denis Carikli <denis@eukrea.com>
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as published
15 * by the Free Software Foundation.
16 */
17
18#include <linux/err.h>
19#include <linux/init.h>
20#include <linux/io.h>
21#include <linux/module.h>
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/pinctrl/pinctrl.h>
25
26#include "pinctrl-imx.h"
27
28enum imx25_pads {
29 MX25_PAD_RESERVE0 = 1,
30 MX25_PAD_RESERVE1 = 2,
31 MX25_PAD_A10 = 3,
32 MX25_PAD_A13 = 4,
33 MX25_PAD_A14 = 5,
34 MX25_PAD_A15 = 6,
35 MX25_PAD_A16 = 7,
36 MX25_PAD_A17 = 8,
37 MX25_PAD_A18 = 9,
38 MX25_PAD_A19 = 10,
39 MX25_PAD_A20 = 11,
40 MX25_PAD_A21 = 12,
41 MX25_PAD_A22 = 13,
42 MX25_PAD_A23 = 14,
43 MX25_PAD_A24 = 15,
44 MX25_PAD_A25 = 16,
45 MX25_PAD_EB0 = 17,
46 MX25_PAD_EB1 = 18,
47 MX25_PAD_OE = 19,
48 MX25_PAD_CS0 = 20,
49 MX25_PAD_CS1 = 21,
50 MX25_PAD_CS4 = 22,
51 MX25_PAD_CS5 = 23,
52 MX25_PAD_NF_CE0 = 24,
53 MX25_PAD_ECB = 25,
54 MX25_PAD_LBA = 26,
55 MX25_PAD_BCLK = 27,
56 MX25_PAD_RW = 28,
57 MX25_PAD_NFWE_B = 29,
58 MX25_PAD_NFRE_B = 30,
59 MX25_PAD_NFALE = 31,
60 MX25_PAD_NFCLE = 32,
61 MX25_PAD_NFWP_B = 33,
62 MX25_PAD_NFRB = 34,
63 MX25_PAD_D15 = 35,
64 MX25_PAD_D14 = 36,
65 MX25_PAD_D13 = 37,
66 MX25_PAD_D12 = 38,
67 MX25_PAD_D11 = 39,
68 MX25_PAD_D10 = 40,
69 MX25_PAD_D9 = 41,
70 MX25_PAD_D8 = 42,
71 MX25_PAD_D7 = 43,
72 MX25_PAD_D6 = 44,
73 MX25_PAD_D5 = 45,
74 MX25_PAD_D4 = 46,
75 MX25_PAD_D3 = 47,
76 MX25_PAD_D2 = 48,
77 MX25_PAD_D1 = 49,
78 MX25_PAD_D0 = 50,
79 MX25_PAD_LD0 = 51,
80 MX25_PAD_LD1 = 52,
81 MX25_PAD_LD2 = 53,
82 MX25_PAD_LD3 = 54,
83 MX25_PAD_LD4 = 55,
84 MX25_PAD_LD5 = 56,
85 MX25_PAD_LD6 = 57,
86 MX25_PAD_LD7 = 58,
87 MX25_PAD_LD8 = 59,
88 MX25_PAD_LD9 = 60,
89 MX25_PAD_LD10 = 61,
90 MX25_PAD_LD11 = 62,
91 MX25_PAD_LD12 = 63,
92 MX25_PAD_LD13 = 64,
93 MX25_PAD_LD14 = 65,
94 MX25_PAD_LD15 = 66,
95 MX25_PAD_HSYNC = 67,
96 MX25_PAD_VSYNC = 68,
97 MX25_PAD_LSCLK = 69,
98 MX25_PAD_OE_ACD = 70,
99 MX25_PAD_CONTRAST = 71,
100 MX25_PAD_PWM = 72,
101 MX25_PAD_CSI_D2 = 73,
102 MX25_PAD_CSI_D3 = 74,
103 MX25_PAD_CSI_D4 = 75,
104 MX25_PAD_CSI_D5 = 76,
105 MX25_PAD_CSI_D6 = 77,
106 MX25_PAD_CSI_D7 = 78,
107 MX25_PAD_CSI_D8 = 79,
108 MX25_PAD_CSI_D9 = 80,
109 MX25_PAD_CSI_MCLK = 81,
110 MX25_PAD_CSI_VSYNC = 82,
111 MX25_PAD_CSI_HSYNC = 83,
112 MX25_PAD_CSI_PIXCLK = 84,
113 MX25_PAD_I2C1_CLK = 85,
114 MX25_PAD_I2C1_DAT = 86,
115 MX25_PAD_CSPI1_MOSI = 87,
116 MX25_PAD_CSPI1_MISO = 88,
117 MX25_PAD_CSPI1_SS0 = 89,
118 MX25_PAD_CSPI1_SS1 = 90,
119 MX25_PAD_CSPI1_SCLK = 91,
120 MX25_PAD_CSPI1_RDY = 92,
121 MX25_PAD_UART1_RXD = 93,
122 MX25_PAD_UART1_TXD = 94,
123 MX25_PAD_UART1_RTS = 95,
124 MX25_PAD_UART1_CTS = 96,
125 MX25_PAD_UART2_RXD = 97,
126 MX25_PAD_UART2_TXD = 98,
127 MX25_PAD_UART2_RTS = 99,
128 MX25_PAD_UART2_CTS = 100,
129 MX25_PAD_SD1_CMD = 101,
130 MX25_PAD_SD1_CLK = 102,
131 MX25_PAD_SD1_DATA0 = 103,
132 MX25_PAD_SD1_DATA1 = 104,
133 MX25_PAD_SD1_DATA2 = 105,
134 MX25_PAD_SD1_DATA3 = 106,
135 MX25_PAD_KPP_ROW0 = 107,
136 MX25_PAD_KPP_ROW1 = 108,
137 MX25_PAD_KPP_ROW2 = 109,
138 MX25_PAD_KPP_ROW3 = 110,
139 MX25_PAD_KPP_COL0 = 111,
140 MX25_PAD_KPP_COL1 = 112,
141 MX25_PAD_KPP_COL2 = 113,
142 MX25_PAD_KPP_COL3 = 114,
143 MX25_PAD_FEC_MDC = 115,
144 MX25_PAD_FEC_MDIO = 116,
145 MX25_PAD_FEC_TDATA0 = 117,
146 MX25_PAD_FEC_TDATA1 = 118,
147 MX25_PAD_FEC_TX_EN = 119,
148 MX25_PAD_FEC_RDATA0 = 120,
149 MX25_PAD_FEC_RDATA1 = 121,
150 MX25_PAD_FEC_RX_DV = 122,
151 MX25_PAD_FEC_TX_CLK = 123,
152 MX25_PAD_RTCK = 124,
153 MX25_PAD_DE_B = 125,
154 MX25_PAD_GPIO_A = 126,
155 MX25_PAD_GPIO_B = 127,
156 MX25_PAD_GPIO_C = 128,
157 MX25_PAD_GPIO_D = 129,
158 MX25_PAD_GPIO_E = 130,
159 MX25_PAD_GPIO_F = 131,
160 MX25_PAD_EXT_ARMCLK = 132,
161 MX25_PAD_UPLL_BYPCLK = 133,
162 MX25_PAD_VSTBY_REQ = 134,
163 MX25_PAD_VSTBY_ACK = 135,
164 MX25_PAD_POWER_FAIL = 136,
165 MX25_PAD_CLKO = 137,
166 MX25_PAD_BOOT_MODE0 = 138,
167 MX25_PAD_BOOT_MODE1 = 139,
168};
169
170/* Pad names for the pinmux subsystem */
171static const struct pinctrl_pin_desc imx25_pinctrl_pads[] = {
172 IMX_PINCTRL_PIN(MX25_PAD_RESERVE0),
173 IMX_PINCTRL_PIN(MX25_PAD_RESERVE1),
174 IMX_PINCTRL_PIN(MX25_PAD_A10),
175 IMX_PINCTRL_PIN(MX25_PAD_A13),
176 IMX_PINCTRL_PIN(MX25_PAD_A14),
177 IMX_PINCTRL_PIN(MX25_PAD_A15),
178 IMX_PINCTRL_PIN(MX25_PAD_A16),
179 IMX_PINCTRL_PIN(MX25_PAD_A17),
180 IMX_PINCTRL_PIN(MX25_PAD_A18),
181 IMX_PINCTRL_PIN(MX25_PAD_A19),
182 IMX_PINCTRL_PIN(MX25_PAD_A20),
183 IMX_PINCTRL_PIN(MX25_PAD_A21),
184 IMX_PINCTRL_PIN(MX25_PAD_A22),
185 IMX_PINCTRL_PIN(MX25_PAD_A23),
186 IMX_PINCTRL_PIN(MX25_PAD_A24),
187 IMX_PINCTRL_PIN(MX25_PAD_A25),
188 IMX_PINCTRL_PIN(MX25_PAD_EB0),
189 IMX_PINCTRL_PIN(MX25_PAD_EB1),
190 IMX_PINCTRL_PIN(MX25_PAD_OE),
191 IMX_PINCTRL_PIN(MX25_PAD_CS0),
192 IMX_PINCTRL_PIN(MX25_PAD_CS1),
193 IMX_PINCTRL_PIN(MX25_PAD_CS4),
194 IMX_PINCTRL_PIN(MX25_PAD_CS5),
195 IMX_PINCTRL_PIN(MX25_PAD_NF_CE0),
196 IMX_PINCTRL_PIN(MX25_PAD_ECB),
197 IMX_PINCTRL_PIN(MX25_PAD_LBA),
198 IMX_PINCTRL_PIN(MX25_PAD_BCLK),
199 IMX_PINCTRL_PIN(MX25_PAD_RW),
200 IMX_PINCTRL_PIN(MX25_PAD_NFWE_B),
201 IMX_PINCTRL_PIN(MX25_PAD_NFRE_B),
202 IMX_PINCTRL_PIN(MX25_PAD_NFALE),
203 IMX_PINCTRL_PIN(MX25_PAD_NFCLE),
204 IMX_PINCTRL_PIN(MX25_PAD_NFWP_B),
205 IMX_PINCTRL_PIN(MX25_PAD_NFRB),
206 IMX_PINCTRL_PIN(MX25_PAD_D15),
207 IMX_PINCTRL_PIN(MX25_PAD_D14),
208 IMX_PINCTRL_PIN(MX25_PAD_D13),
209 IMX_PINCTRL_PIN(MX25_PAD_D12),
210 IMX_PINCTRL_PIN(MX25_PAD_D11),
211 IMX_PINCTRL_PIN(MX25_PAD_D10),
212 IMX_PINCTRL_PIN(MX25_PAD_D9),
213 IMX_PINCTRL_PIN(MX25_PAD_D8),
214 IMX_PINCTRL_PIN(MX25_PAD_D7),
215 IMX_PINCTRL_PIN(MX25_PAD_D6),
216 IMX_PINCTRL_PIN(MX25_PAD_D5),
217 IMX_PINCTRL_PIN(MX25_PAD_D4),
218 IMX_PINCTRL_PIN(MX25_PAD_D3),
219 IMX_PINCTRL_PIN(MX25_PAD_D2),
220 IMX_PINCTRL_PIN(MX25_PAD_D1),
221 IMX_PINCTRL_PIN(MX25_PAD_D0),
222 IMX_PINCTRL_PIN(MX25_PAD_LD0),
223 IMX_PINCTRL_PIN(MX25_PAD_LD1),
224 IMX_PINCTRL_PIN(MX25_PAD_LD2),
225 IMX_PINCTRL_PIN(MX25_PAD_LD3),
226 IMX_PINCTRL_PIN(MX25_PAD_LD4),
227 IMX_PINCTRL_PIN(MX25_PAD_LD5),
228 IMX_PINCTRL_PIN(MX25_PAD_LD6),
229 IMX_PINCTRL_PIN(MX25_PAD_LD7),
230 IMX_PINCTRL_PIN(MX25_PAD_LD8),
231 IMX_PINCTRL_PIN(MX25_PAD_LD9),
232 IMX_PINCTRL_PIN(MX25_PAD_LD10),
233 IMX_PINCTRL_PIN(MX25_PAD_LD11),
234 IMX_PINCTRL_PIN(MX25_PAD_LD12),
235 IMX_PINCTRL_PIN(MX25_PAD_LD13),
236 IMX_PINCTRL_PIN(MX25_PAD_LD14),
237 IMX_PINCTRL_PIN(MX25_PAD_LD15),
238 IMX_PINCTRL_PIN(MX25_PAD_HSYNC),
239 IMX_PINCTRL_PIN(MX25_PAD_VSYNC),
240 IMX_PINCTRL_PIN(MX25_PAD_LSCLK),
241 IMX_PINCTRL_PIN(MX25_PAD_OE_ACD),
242 IMX_PINCTRL_PIN(MX25_PAD_CONTRAST),
243 IMX_PINCTRL_PIN(MX25_PAD_PWM),
244 IMX_PINCTRL_PIN(MX25_PAD_CSI_D2),
245 IMX_PINCTRL_PIN(MX25_PAD_CSI_D3),
246 IMX_PINCTRL_PIN(MX25_PAD_CSI_D4),
247 IMX_PINCTRL_PIN(MX25_PAD_CSI_D5),
248 IMX_PINCTRL_PIN(MX25_PAD_CSI_D6),
249 IMX_PINCTRL_PIN(MX25_PAD_CSI_D7),
250 IMX_PINCTRL_PIN(MX25_PAD_CSI_D8),
251 IMX_PINCTRL_PIN(MX25_PAD_CSI_D9),
252 IMX_PINCTRL_PIN(MX25_PAD_CSI_MCLK),
253 IMX_PINCTRL_PIN(MX25_PAD_CSI_VSYNC),
254 IMX_PINCTRL_PIN(MX25_PAD_CSI_HSYNC),
255 IMX_PINCTRL_PIN(MX25_PAD_CSI_PIXCLK),
256 IMX_PINCTRL_PIN(MX25_PAD_I2C1_CLK),
257 IMX_PINCTRL_PIN(MX25_PAD_I2C1_DAT),
258 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MOSI),
259 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_MISO),
260 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS0),
261 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SS1),
262 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_SCLK),
263 IMX_PINCTRL_PIN(MX25_PAD_CSPI1_RDY),
264 IMX_PINCTRL_PIN(MX25_PAD_UART1_RXD),
265 IMX_PINCTRL_PIN(MX25_PAD_UART1_TXD),
266 IMX_PINCTRL_PIN(MX25_PAD_UART1_RTS),
267 IMX_PINCTRL_PIN(MX25_PAD_UART1_CTS),
268 IMX_PINCTRL_PIN(MX25_PAD_UART2_RXD),
269 IMX_PINCTRL_PIN(MX25_PAD_UART2_TXD),
270 IMX_PINCTRL_PIN(MX25_PAD_UART2_RTS),
271 IMX_PINCTRL_PIN(MX25_PAD_UART2_CTS),
272 IMX_PINCTRL_PIN(MX25_PAD_SD1_CMD),
273 IMX_PINCTRL_PIN(MX25_PAD_SD1_CLK),
274 IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA0),
275 IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA1),
276 IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA2),
277 IMX_PINCTRL_PIN(MX25_PAD_SD1_DATA3),
278 IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW0),
279 IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW1),
280 IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW2),
281 IMX_PINCTRL_PIN(MX25_PAD_KPP_ROW3),
282 IMX_PINCTRL_PIN(MX25_PAD_KPP_COL0),
283 IMX_PINCTRL_PIN(MX25_PAD_KPP_COL1),
284 IMX_PINCTRL_PIN(MX25_PAD_KPP_COL2),
285 IMX_PINCTRL_PIN(MX25_PAD_KPP_COL3),
286 IMX_PINCTRL_PIN(MX25_PAD_FEC_MDC),
287 IMX_PINCTRL_PIN(MX25_PAD_FEC_MDIO),
288 IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA0),
289 IMX_PINCTRL_PIN(MX25_PAD_FEC_TDATA1),
290 IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_EN),
291 IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA0),
292 IMX_PINCTRL_PIN(MX25_PAD_FEC_RDATA1),
293 IMX_PINCTRL_PIN(MX25_PAD_FEC_RX_DV),
294 IMX_PINCTRL_PIN(MX25_PAD_FEC_TX_CLK),
295 IMX_PINCTRL_PIN(MX25_PAD_RTCK),
296 IMX_PINCTRL_PIN(MX25_PAD_DE_B),
297 IMX_PINCTRL_PIN(MX25_PAD_GPIO_A),
298 IMX_PINCTRL_PIN(MX25_PAD_GPIO_B),
299 IMX_PINCTRL_PIN(MX25_PAD_GPIO_C),
300 IMX_PINCTRL_PIN(MX25_PAD_GPIO_D),
301 IMX_PINCTRL_PIN(MX25_PAD_GPIO_E),
302 IMX_PINCTRL_PIN(MX25_PAD_GPIO_F),
303 IMX_PINCTRL_PIN(MX25_PAD_EXT_ARMCLK),
304 IMX_PINCTRL_PIN(MX25_PAD_UPLL_BYPCLK),
305 IMX_PINCTRL_PIN(MX25_PAD_VSTBY_REQ),
306 IMX_PINCTRL_PIN(MX25_PAD_VSTBY_ACK),
307 IMX_PINCTRL_PIN(MX25_PAD_POWER_FAIL),
308 IMX_PINCTRL_PIN(MX25_PAD_CLKO),
309 IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE0),
310 IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
311};
312
313static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
314 .pins = imx25_pinctrl_pads,
315 .npins = ARRAY_SIZE(imx25_pinctrl_pads),
316};
317
318static struct of_device_id imx25_pinctrl_of_match[] = {
319 { .compatible = "fsl,imx25-iomuxc", },
320 { /* sentinel */ }
321};
322
323static int imx25_pinctrl_probe(struct platform_device *pdev)
324{
325 return imx_pinctrl_probe(pdev, &imx25_pinctrl_info);
326}
327
328static struct platform_driver imx25_pinctrl_driver = {
329 .driver = {
330 .name = "imx25-pinctrl",
331 .owner = THIS_MODULE,
332 .of_match_table = of_match_ptr(imx25_pinctrl_of_match),
333 },
334 .probe = imx25_pinctrl_probe,
335 .remove = imx_pinctrl_remove,
336};
337
338static int __init imx25_pinctrl_init(void)
339{
340 return platform_driver_register(&imx25_pinctrl_driver);
341}
342arch_initcall(imx25_pinctrl_init);
343
344static void __exit imx25_pinctrl_exit(void)
345{
346 platform_driver_unregister(&imx25_pinctrl_driver);
347}
348module_exit(imx25_pinctrl_exit);
349MODULE_AUTHOR("Denis Carikli <denis@eukrea.com>");
350MODULE_DESCRIPTION("Freescale IMX25 pinctrl driver");
351MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-msm.c b/drivers/pinctrl/pinctrl-msm.c
new file mode 100644
index 000000000000..ef2bf3126da6
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-msm.c
@@ -0,0 +1,990 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 * Copyright (c) 2013, The Linux Foundation. All rights reserved.
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 and
7 * only version 2 as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 */
14
15#include <linux/err.h>
16#include <linux/irqdomain.h>
17#include <linux/io.h>
18#include <linux/module.h>
19#include <linux/of.h>
20#include <linux/platform_device.h>
21#include <linux/pinctrl/machine.h>
22#include <linux/pinctrl/pinctrl.h>
23#include <linux/pinctrl/pinmux.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/slab.h>
27#include <linux/gpio.h>
28#include <linux/interrupt.h>
29#include <linux/irq.h>
30#include <linux/irqchip/chained_irq.h>
31#include <linux/of_irq.h>
32#include <linux/spinlock.h>
33
34#include "core.h"
35#include "pinconf.h"
36#include "pinctrl-msm.h"
37#include "pinctrl-utils.h"
38
39#define MAX_NR_GPIO 300
40
41/**
42 * struct msm_pinctrl - state for a pinctrl-msm device
43 * @dev: device handle.
44 * @pctrl: pinctrl handle.
45 * @domain: irqdomain handle.
46 * @chip: gpiochip handle.
47 * @irq: parent irq for the TLMM irq_chip.
48 * @lock: Spinlock to protect register resources as well
49 * as msm_pinctrl data structures.
50 * @enabled_irqs: Bitmap of currently enabled irqs.
51 * @dual_edge_irqs: Bitmap of irqs that need sw emulated dual edge
52 * detection.
53 * @wake_irqs: Bitmap of irqs with requested as wakeup source.
54 * @soc; Reference to soc_data of platform specific data.
55 * @regs: Base address for the TLMM register map.
56 */
57struct msm_pinctrl {
58 struct device *dev;
59 struct pinctrl_dev *pctrl;
60 struct irq_domain *domain;
61 struct gpio_chip chip;
62 int irq;
63
64 spinlock_t lock;
65
66 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
67 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
68 DECLARE_BITMAP(wake_irqs, MAX_NR_GPIO);
69
70 const struct msm_pinctrl_soc_data *soc;
71 void __iomem *regs;
72};
73
74static int msm_get_groups_count(struct pinctrl_dev *pctldev)
75{
76 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
77
78 return pctrl->soc->ngroups;
79}
80
81static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
82 unsigned group)
83{
84 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
85
86 return pctrl->soc->groups[group].name;
87}
88
89static int msm_get_group_pins(struct pinctrl_dev *pctldev,
90 unsigned group,
91 const unsigned **pins,
92 unsigned *num_pins)
93{
94 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
95
96 *pins = pctrl->soc->groups[group].pins;
97 *num_pins = pctrl->soc->groups[group].npins;
98 return 0;
99}
100
101static const struct pinctrl_ops msm_pinctrl_ops = {
102 .get_groups_count = msm_get_groups_count,
103 .get_group_name = msm_get_group_name,
104 .get_group_pins = msm_get_group_pins,
105 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
106 .dt_free_map = pinctrl_utils_dt_free_map,
107};
108
109static int msm_get_functions_count(struct pinctrl_dev *pctldev)
110{
111 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
112
113 return pctrl->soc->nfunctions;
114}
115
116static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
117 unsigned function)
118{
119 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
120
121 return pctrl->soc->functions[function].name;
122}
123
124static int msm_get_function_groups(struct pinctrl_dev *pctldev,
125 unsigned function,
126 const char * const **groups,
127 unsigned * const num_groups)
128{
129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
130
131 *groups = pctrl->soc->functions[function].groups;
132 *num_groups = pctrl->soc->functions[function].ngroups;
133 return 0;
134}
135
136static int msm_pinmux_enable(struct pinctrl_dev *pctldev,
137 unsigned function,
138 unsigned group)
139{
140 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
141 const struct msm_pingroup *g;
142 unsigned long flags;
143 u32 val;
144 int i;
145
146 g = &pctrl->soc->groups[group];
147
148 if (WARN_ON(g->mux_bit < 0))
149 return -EINVAL;
150
151 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
152 if (g->funcs[i] == function)
153 break;
154 }
155
156 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
157 return -EINVAL;
158
159 spin_lock_irqsave(&pctrl->lock, flags);
160
161 val = readl(pctrl->regs + g->ctl_reg);
162 val &= ~(0x7 << g->mux_bit);
163 val |= i << g->mux_bit;
164 writel(val, pctrl->regs + g->ctl_reg);
165
166 spin_unlock_irqrestore(&pctrl->lock, flags);
167
168 return 0;
169}
170
171static void msm_pinmux_disable(struct pinctrl_dev *pctldev,
172 unsigned function,
173 unsigned group)
174{
175 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
176 const struct msm_pingroup *g;
177 unsigned long flags;
178 u32 val;
179
180 g = &pctrl->soc->groups[group];
181
182 if (WARN_ON(g->mux_bit < 0))
183 return;
184
185 spin_lock_irqsave(&pctrl->lock, flags);
186
187 /* Clear the mux bits to select gpio mode */
188 val = readl(pctrl->regs + g->ctl_reg);
189 val &= ~(0x7 << g->mux_bit);
190 writel(val, pctrl->regs + g->ctl_reg);
191
192 spin_unlock_irqrestore(&pctrl->lock, flags);
193}
194
195static const struct pinmux_ops msm_pinmux_ops = {
196 .get_functions_count = msm_get_functions_count,
197 .get_function_name = msm_get_function_name,
198 .get_function_groups = msm_get_function_groups,
199 .enable = msm_pinmux_enable,
200 .disable = msm_pinmux_disable,
201};
202
203static int msm_config_reg(struct msm_pinctrl *pctrl,
204 const struct msm_pingroup *g,
205 unsigned param,
206 s16 *reg,
207 unsigned *mask,
208 unsigned *bit)
209{
210 switch (param) {
211 case PIN_CONFIG_BIAS_DISABLE:
212 *reg = g->ctl_reg;
213 *bit = g->pull_bit;
214 *mask = 3;
215 break;
216 case PIN_CONFIG_BIAS_PULL_DOWN:
217 *reg = g->ctl_reg;
218 *bit = g->pull_bit;
219 *mask = 3;
220 break;
221 case PIN_CONFIG_BIAS_PULL_UP:
222 *reg = g->ctl_reg;
223 *bit = g->pull_bit;
224 *mask = 3;
225 break;
226 case PIN_CONFIG_DRIVE_STRENGTH:
227 *reg = g->ctl_reg;
228 *bit = g->drv_bit;
229 *mask = 7;
230 break;
231 default:
232 dev_err(pctrl->dev, "Invalid config param %04x\n", param);
233 return -ENOTSUPP;
234 }
235
236 if (*reg < 0) {
237 dev_err(pctrl->dev, "Config param %04x not supported on group %s\n",
238 param, g->name);
239 return -ENOTSUPP;
240 }
241
242 return 0;
243}
244
245static int msm_config_get(struct pinctrl_dev *pctldev,
246 unsigned int pin,
247 unsigned long *config)
248{
249 dev_err(pctldev->dev, "pin_config_set op not supported\n");
250 return -ENOTSUPP;
251}
252
253static int msm_config_set(struct pinctrl_dev *pctldev, unsigned int pin,
254 unsigned long *configs, unsigned num_configs)
255{
256 dev_err(pctldev->dev, "pin_config_set op not supported\n");
257 return -ENOTSUPP;
258}
259
260#define MSM_NO_PULL 0
261#define MSM_PULL_DOWN 1
262#define MSM_PULL_UP 3
263
264static const unsigned msm_regval_to_drive[] = { 2, 4, 6, 8, 10, 12, 14, 16 };
265static const unsigned msm_drive_to_regval[] = { -1, -1, 0, -1, 1, -1, 2, -1, 3, -1, 4, -1, 5, -1, 6, -1, 7 };
266
267static int msm_config_group_get(struct pinctrl_dev *pctldev,
268 unsigned int group,
269 unsigned long *config)
270{
271 const struct msm_pingroup *g;
272 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
273 unsigned param = pinconf_to_config_param(*config);
274 unsigned mask;
275 unsigned arg;
276 unsigned bit;
277 s16 reg;
278 int ret;
279 u32 val;
280
281 g = &pctrl->soc->groups[group];
282
283 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
284 if (ret < 0)
285 return ret;
286
287 val = readl(pctrl->regs + reg);
288 arg = (val >> bit) & mask;
289
290 /* Convert register value to pinconf value */
291 switch (param) {
292 case PIN_CONFIG_BIAS_DISABLE:
293 arg = arg == MSM_NO_PULL;
294 break;
295 case PIN_CONFIG_BIAS_PULL_DOWN:
296 arg = arg == MSM_PULL_DOWN;
297 break;
298 case PIN_CONFIG_BIAS_PULL_UP:
299 arg = arg == MSM_PULL_UP;
300 break;
301 case PIN_CONFIG_DRIVE_STRENGTH:
302 arg = msm_regval_to_drive[arg];
303 break;
304 default:
305 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
306 param);
307 return -EINVAL;
308 }
309
310 *config = pinconf_to_config_packed(param, arg);
311
312 return 0;
313}
314
315static int msm_config_group_set(struct pinctrl_dev *pctldev,
316 unsigned group,
317 unsigned long *configs,
318 unsigned num_configs)
319{
320 const struct msm_pingroup *g;
321 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
322 unsigned long flags;
323 unsigned param;
324 unsigned mask;
325 unsigned arg;
326 unsigned bit;
327 s16 reg;
328 int ret;
329 u32 val;
330 int i;
331
332 g = &pctrl->soc->groups[group];
333
334 for (i = 0; i < num_configs; i++) {
335 param = pinconf_to_config_param(configs[i]);
336 arg = pinconf_to_config_argument(configs[i]);
337
338 ret = msm_config_reg(pctrl, g, param, &reg, &mask, &bit);
339 if (ret < 0)
340 return ret;
341
342 /* Convert pinconf values to register values */
343 switch (param) {
344 case PIN_CONFIG_BIAS_DISABLE:
345 arg = MSM_NO_PULL;
346 break;
347 case PIN_CONFIG_BIAS_PULL_DOWN:
348 arg = MSM_PULL_DOWN;
349 break;
350 case PIN_CONFIG_BIAS_PULL_UP:
351 arg = MSM_PULL_UP;
352 break;
353 case PIN_CONFIG_DRIVE_STRENGTH:
354 /* Check for invalid values */
355 if (arg >= ARRAY_SIZE(msm_drive_to_regval))
356 arg = -1;
357 else
358 arg = msm_drive_to_regval[arg];
359 break;
360 default:
361 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
362 param);
363 return -EINVAL;
364 }
365
366 /* Range-check user-supplied value */
367 if (arg & ~mask) {
368 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
369 return -EINVAL;
370 }
371
372 spin_lock_irqsave(&pctrl->lock, flags);
373 val = readl(pctrl->regs + reg);
374 val &= ~(mask << bit);
375 val |= arg << bit;
376 writel(val, pctrl->regs + reg);
377 spin_unlock_irqrestore(&pctrl->lock, flags);
378 }
379
380 return 0;
381}
382
383static const struct pinconf_ops msm_pinconf_ops = {
384 .pin_config_get = msm_config_get,
385 .pin_config_set = msm_config_set,
386 .pin_config_group_get = msm_config_group_get,
387 .pin_config_group_set = msm_config_group_set,
388};
389
390static struct pinctrl_desc msm_pinctrl_desc = {
391 .pctlops = &msm_pinctrl_ops,
392 .pmxops = &msm_pinmux_ops,
393 .confops = &msm_pinconf_ops,
394 .owner = THIS_MODULE,
395};
396
397static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
398{
399 const struct msm_pingroup *g;
400 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
401 unsigned long flags;
402 u32 val;
403
404 g = &pctrl->soc->groups[offset];
405 if (WARN_ON(g->io_reg < 0))
406 return -EINVAL;
407
408 spin_lock_irqsave(&pctrl->lock, flags);
409
410 val = readl(pctrl->regs + g->ctl_reg);
411 val &= ~BIT(g->oe_bit);
412 writel(val, pctrl->regs + g->ctl_reg);
413
414 spin_unlock_irqrestore(&pctrl->lock, flags);
415
416 return 0;
417}
418
419static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
420{
421 const struct msm_pingroup *g;
422 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
423 unsigned long flags;
424 u32 val;
425
426 g = &pctrl->soc->groups[offset];
427 if (WARN_ON(g->io_reg < 0))
428 return -EINVAL;
429
430 spin_lock_irqsave(&pctrl->lock, flags);
431
432 val = readl(pctrl->regs + g->io_reg);
433 if (value)
434 val |= BIT(g->out_bit);
435 else
436 val &= ~BIT(g->out_bit);
437 writel(val, pctrl->regs + g->io_reg);
438
439 val = readl(pctrl->regs + g->ctl_reg);
440 val |= BIT(g->oe_bit);
441 writel(val, pctrl->regs + g->ctl_reg);
442
443 spin_unlock_irqrestore(&pctrl->lock, flags);
444
445 return 0;
446}
447
448static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
449{
450 const struct msm_pingroup *g;
451 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
452 u32 val;
453
454 g = &pctrl->soc->groups[offset];
455 if (WARN_ON(g->io_reg < 0))
456 return -EINVAL;
457
458 val = readl(pctrl->regs + g->io_reg);
459 return !!(val & BIT(g->in_bit));
460}
461
462static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
463{
464 const struct msm_pingroup *g;
465 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
466 unsigned long flags;
467 u32 val;
468
469 g = &pctrl->soc->groups[offset];
470 if (WARN_ON(g->io_reg < 0))
471 return;
472
473 spin_lock_irqsave(&pctrl->lock, flags);
474
475 val = readl(pctrl->regs + g->io_reg);
476 if (value)
477 val |= BIT(g->out_bit);
478 else
479 val &= ~BIT(g->out_bit);
480 writel(val, pctrl->regs + g->io_reg);
481
482 spin_unlock_irqrestore(&pctrl->lock, flags);
483}
484
485static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
486{
487 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
488
489 return irq_find_mapping(pctrl->domain, offset);
490}
491
492static int msm_gpio_request(struct gpio_chip *chip, unsigned offset)
493{
494 int gpio = chip->base + offset;
495 return pinctrl_request_gpio(gpio);
496}
497
498static void msm_gpio_free(struct gpio_chip *chip, unsigned offset)
499{
500 int gpio = chip->base + offset;
501 return pinctrl_free_gpio(gpio);
502}
503
504#ifdef CONFIG_DEBUG_FS
505#include <linux/seq_file.h>
506
507static void msm_gpio_dbg_show_one(struct seq_file *s,
508 struct pinctrl_dev *pctldev,
509 struct gpio_chip *chip,
510 unsigned offset,
511 unsigned gpio)
512{
513 const struct msm_pingroup *g;
514 struct msm_pinctrl *pctrl = container_of(chip, struct msm_pinctrl, chip);
515 unsigned func;
516 int is_out;
517 int drive;
518 int pull;
519 u32 ctl_reg;
520
521 static const char * const pulls[] = {
522 "no pull",
523 "pull down",
524 "keeper",
525 "pull up"
526 };
527
528 g = &pctrl->soc->groups[offset];
529 ctl_reg = readl(pctrl->regs + g->ctl_reg);
530
531 is_out = !!(ctl_reg & BIT(g->oe_bit));
532 func = (ctl_reg >> g->mux_bit) & 7;
533 drive = (ctl_reg >> g->drv_bit) & 7;
534 pull = (ctl_reg >> g->pull_bit) & 3;
535
536 seq_printf(s, " %-8s: %-3s %d", g->name, is_out ? "out" : "in", func);
537 seq_printf(s, " %dmA", msm_regval_to_drive[drive]);
538 seq_printf(s, " %s", pulls[pull]);
539}
540
541static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
542{
543 unsigned gpio = chip->base;
544 unsigned i;
545
546 for (i = 0; i < chip->ngpio; i++, gpio++) {
547 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
548 seq_puts(s, "\n");
549 }
550}
551
552#else
553#define msm_gpio_dbg_show NULL
554#endif
555
556static struct gpio_chip msm_gpio_template = {
557 .direction_input = msm_gpio_direction_input,
558 .direction_output = msm_gpio_direction_output,
559 .get = msm_gpio_get,
560 .set = msm_gpio_set,
561 .to_irq = msm_gpio_to_irq,
562 .request = msm_gpio_request,
563 .free = msm_gpio_free,
564 .dbg_show = msm_gpio_dbg_show,
565};
566
567/* For dual-edge interrupts in software, since some hardware has no
568 * such support:
569 *
570 * At appropriate moments, this function may be called to flip the polarity
571 * settings of both-edge irq lines to try and catch the next edge.
572 *
573 * The attempt is considered successful if:
574 * - the status bit goes high, indicating that an edge was caught, or
575 * - the input value of the gpio doesn't change during the attempt.
576 * If the value changes twice during the process, that would cause the first
577 * test to fail but would force the second, as two opposite
578 * transitions would cause a detection no matter the polarity setting.
579 *
580 * The do-loop tries to sledge-hammer closed the timing hole between
581 * the initial value-read and the polarity-write - if the line value changes
582 * during that window, an interrupt is lost, the new polarity setting is
583 * incorrect, and the first success test will fail, causing a retry.
584 *
585 * Algorithm comes from Google's msmgpio driver.
586 */
587static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
588 const struct msm_pingroup *g,
589 struct irq_data *d)
590{
591 int loop_limit = 100;
592 unsigned val, val2, intstat;
593 unsigned pol;
594
595 do {
596 val = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
597
598 pol = readl(pctrl->regs + g->intr_cfg_reg);
599 pol ^= BIT(g->intr_polarity_bit);
600 writel(pol, pctrl->regs + g->intr_cfg_reg);
601
602 val2 = readl(pctrl->regs + g->io_reg) & BIT(g->in_bit);
603 intstat = readl(pctrl->regs + g->intr_status_reg);
604 if (intstat || (val == val2))
605 return;
606 } while (loop_limit-- > 0);
607 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
608 val, val2);
609}
610
611static void msm_gpio_irq_mask(struct irq_data *d)
612{
613 const struct msm_pingroup *g;
614 struct msm_pinctrl *pctrl;
615 unsigned long flags;
616 u32 val;
617
618 pctrl = irq_data_get_irq_chip_data(d);
619 g = &pctrl->soc->groups[d->hwirq];
620 if (WARN_ON(g->intr_cfg_reg < 0))
621 return;
622
623 spin_lock_irqsave(&pctrl->lock, flags);
624
625 val = readl(pctrl->regs + g->intr_cfg_reg);
626 val &= ~BIT(g->intr_enable_bit);
627 writel(val, pctrl->regs + g->intr_cfg_reg);
628
629 clear_bit(d->hwirq, pctrl->enabled_irqs);
630
631 spin_unlock_irqrestore(&pctrl->lock, flags);
632}
633
634static void msm_gpio_irq_unmask(struct irq_data *d)
635{
636 const struct msm_pingroup *g;
637 struct msm_pinctrl *pctrl;
638 unsigned long flags;
639 u32 val;
640
641 pctrl = irq_data_get_irq_chip_data(d);
642 g = &pctrl->soc->groups[d->hwirq];
643 if (WARN_ON(g->intr_status_reg < 0))
644 return;
645
646 spin_lock_irqsave(&pctrl->lock, flags);
647
648 val = readl(pctrl->regs + g->intr_status_reg);
649 val &= ~BIT(g->intr_status_bit);
650 writel(val, pctrl->regs + g->intr_status_reg);
651
652 val = readl(pctrl->regs + g->intr_cfg_reg);
653 val |= BIT(g->intr_enable_bit);
654 writel(val, pctrl->regs + g->intr_cfg_reg);
655
656 set_bit(d->hwirq, pctrl->enabled_irqs);
657
658 spin_unlock_irqrestore(&pctrl->lock, flags);
659}
660
661static void msm_gpio_irq_ack(struct irq_data *d)
662{
663 const struct msm_pingroup *g;
664 struct msm_pinctrl *pctrl;
665 unsigned long flags;
666 u32 val;
667
668 pctrl = irq_data_get_irq_chip_data(d);
669 g = &pctrl->soc->groups[d->hwirq];
670 if (WARN_ON(g->intr_status_reg < 0))
671 return;
672
673 spin_lock_irqsave(&pctrl->lock, flags);
674
675 val = readl(pctrl->regs + g->intr_status_reg);
676 val &= ~BIT(g->intr_status_bit);
677 writel(val, pctrl->regs + g->intr_status_reg);
678
679 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
680 msm_gpio_update_dual_edge_pos(pctrl, g, d);
681
682 spin_unlock_irqrestore(&pctrl->lock, flags);
683}
684
685#define INTR_TARGET_PROC_APPS 4
686
687static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
688{
689 const struct msm_pingroup *g;
690 struct msm_pinctrl *pctrl;
691 unsigned long flags;
692 u32 val;
693
694 pctrl = irq_data_get_irq_chip_data(d);
695 g = &pctrl->soc->groups[d->hwirq];
696 if (WARN_ON(g->intr_cfg_reg < 0))
697 return -EINVAL;
698
699 spin_lock_irqsave(&pctrl->lock, flags);
700
701 /*
702 * For hw without possibility of detecting both edges
703 */
704 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
705 set_bit(d->hwirq, pctrl->dual_edge_irqs);
706 else
707 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
708
709 /* Route interrupts to application cpu */
710 val = readl(pctrl->regs + g->intr_target_reg);
711 val &= ~(7 << g->intr_target_bit);
712 val |= INTR_TARGET_PROC_APPS << g->intr_target_bit;
713 writel(val, pctrl->regs + g->intr_target_reg);
714
715 /* Update configuration for gpio.
716 * RAW_STATUS_EN is left on for all gpio irqs. Due to the
717 * internal circuitry of TLMM, toggling the RAW_STATUS
718 * could cause the INTR_STATUS to be set for EDGE interrupts.
719 */
720 val = readl(pctrl->regs + g->intr_cfg_reg);
721 val |= BIT(g->intr_raw_status_bit);
722 if (g->intr_detection_width == 2) {
723 val &= ~(3 << g->intr_detection_bit);
724 val &= ~(1 << g->intr_polarity_bit);
725 switch (type) {
726 case IRQ_TYPE_EDGE_RISING:
727 val |= 1 << g->intr_detection_bit;
728 val |= BIT(g->intr_polarity_bit);
729 break;
730 case IRQ_TYPE_EDGE_FALLING:
731 val |= 2 << g->intr_detection_bit;
732 val |= BIT(g->intr_polarity_bit);
733 break;
734 case IRQ_TYPE_EDGE_BOTH:
735 val |= 3 << g->intr_detection_bit;
736 val |= BIT(g->intr_polarity_bit);
737 break;
738 case IRQ_TYPE_LEVEL_LOW:
739 break;
740 case IRQ_TYPE_LEVEL_HIGH:
741 val |= BIT(g->intr_polarity_bit);
742 break;
743 }
744 } else if (g->intr_detection_width == 1) {
745 val &= ~(1 << g->intr_detection_bit);
746 val &= ~(1 << g->intr_polarity_bit);
747 switch (type) {
748 case IRQ_TYPE_EDGE_RISING:
749 val |= BIT(g->intr_detection_bit);
750 val |= BIT(g->intr_polarity_bit);
751 break;
752 case IRQ_TYPE_EDGE_FALLING:
753 val |= BIT(g->intr_detection_bit);
754 break;
755 case IRQ_TYPE_EDGE_BOTH:
756 val |= BIT(g->intr_detection_bit);
757 break;
758 case IRQ_TYPE_LEVEL_LOW:
759 break;
760 case IRQ_TYPE_LEVEL_HIGH:
761 val |= BIT(g->intr_polarity_bit);
762 break;
763 }
764 } else {
765 BUG();
766 }
767 writel(val, pctrl->regs + g->intr_cfg_reg);
768
769 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
770 msm_gpio_update_dual_edge_pos(pctrl, g, d);
771
772 spin_unlock_irqrestore(&pctrl->lock, flags);
773
774 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
775 __irq_set_handler_locked(d->irq, handle_level_irq);
776 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
777 __irq_set_handler_locked(d->irq, handle_edge_irq);
778
779 return 0;
780}
781
782static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
783{
784 struct msm_pinctrl *pctrl;
785 unsigned long flags;
786 unsigned ngpio;
787
788 pctrl = irq_data_get_irq_chip_data(d);
789 ngpio = pctrl->chip.ngpio;
790
791 spin_lock_irqsave(&pctrl->lock, flags);
792
793 if (on) {
794 if (bitmap_empty(pctrl->wake_irqs, ngpio))
795 enable_irq_wake(pctrl->irq);
796 set_bit(d->hwirq, pctrl->wake_irqs);
797 } else {
798 clear_bit(d->hwirq, pctrl->wake_irqs);
799 if (bitmap_empty(pctrl->wake_irqs, ngpio))
800 disable_irq_wake(pctrl->irq);
801 }
802
803 spin_unlock_irqrestore(&pctrl->lock, flags);
804
805 return 0;
806}
807
808static unsigned int msm_gpio_irq_startup(struct irq_data *d)
809{
810 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
811
812 if (gpio_lock_as_irq(&pctrl->chip, d->hwirq)) {
813 dev_err(pctrl->dev, "unable to lock HW IRQ %lu for IRQ\n",
814 d->hwirq);
815 }
816 msm_gpio_irq_unmask(d);
817 return 0;
818}
819
820static void msm_gpio_irq_shutdown(struct irq_data *d)
821{
822 struct msm_pinctrl *pctrl = irq_data_get_irq_chip_data(d);
823
824 msm_gpio_irq_mask(d);
825 gpio_unlock_as_irq(&pctrl->chip, d->hwirq);
826}
827
828static struct irq_chip msm_gpio_irq_chip = {
829 .name = "msmgpio",
830 .irq_mask = msm_gpio_irq_mask,
831 .irq_unmask = msm_gpio_irq_unmask,
832 .irq_ack = msm_gpio_irq_ack,
833 .irq_set_type = msm_gpio_irq_set_type,
834 .irq_set_wake = msm_gpio_irq_set_wake,
835 .irq_startup = msm_gpio_irq_startup,
836 .irq_shutdown = msm_gpio_irq_shutdown,
837};
838
839static void msm_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
840{
841 const struct msm_pingroup *g;
842 struct msm_pinctrl *pctrl = irq_desc_get_handler_data(desc);
843 struct irq_chip *chip = irq_get_chip(irq);
844 int irq_pin;
845 int handled = 0;
846 u32 val;
847 int i;
848
849 chained_irq_enter(chip, desc);
850
851 /*
852 * Each pin has it's own IRQ status register, so use
853 * enabled_irq bitmap to limit the number of reads.
854 */
855 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
856 g = &pctrl->soc->groups[i];
857 val = readl(pctrl->regs + g->intr_status_reg);
858 if (val & BIT(g->intr_status_bit)) {
859 irq_pin = irq_find_mapping(pctrl->domain, i);
860 generic_handle_irq(irq_pin);
861 handled++;
862 }
863 }
864
865 /* No interrupts were flagged */
866 if (handled == 0)
867 handle_bad_irq(irq, desc);
868
869 chained_irq_exit(chip, desc);
870}
871
872static int msm_gpio_init(struct msm_pinctrl *pctrl)
873{
874 struct gpio_chip *chip;
875 int irq;
876 int ret;
877 int i;
878 int r;
879
880 chip = &pctrl->chip;
881 chip->base = 0;
882 chip->ngpio = pctrl->soc->ngpios;
883 chip->label = dev_name(pctrl->dev);
884 chip->dev = pctrl->dev;
885 chip->owner = THIS_MODULE;
886 chip->of_node = pctrl->dev->of_node;
887
888 ret = gpiochip_add(&pctrl->chip);
889 if (ret) {
890 dev_err(pctrl->dev, "Failed register gpiochip\n");
891 return ret;
892 }
893
894 ret = gpiochip_add_pin_range(&pctrl->chip, dev_name(pctrl->dev), 0, 0, chip->ngpio);
895 if (ret) {
896 dev_err(pctrl->dev, "Failed to add pin range\n");
897 return ret;
898 }
899
900 pctrl->domain = irq_domain_add_linear(pctrl->dev->of_node, chip->ngpio,
901 &irq_domain_simple_ops, NULL);
902 if (!pctrl->domain) {
903 dev_err(pctrl->dev, "Failed to register irq domain\n");
904 r = gpiochip_remove(&pctrl->chip);
905 return -ENOSYS;
906 }
907
908 for (i = 0; i < chip->ngpio; i++) {
909 irq = irq_create_mapping(pctrl->domain, i);
910 irq_set_chip_and_handler(irq, &msm_gpio_irq_chip, handle_edge_irq);
911 irq_set_chip_data(irq, pctrl);
912 }
913
914 irq_set_handler_data(pctrl->irq, pctrl);
915 irq_set_chained_handler(pctrl->irq, msm_gpio_irq_handler);
916
917 return 0;
918}
919
920int msm_pinctrl_probe(struct platform_device *pdev,
921 const struct msm_pinctrl_soc_data *soc_data)
922{
923 struct msm_pinctrl *pctrl;
924 struct resource *res;
925 int ret;
926
927 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
928 if (!pctrl) {
929 dev_err(&pdev->dev, "Can't allocate msm_pinctrl\n");
930 return -ENOMEM;
931 }
932 pctrl->dev = &pdev->dev;
933 pctrl->soc = soc_data;
934 pctrl->chip = msm_gpio_template;
935
936 spin_lock_init(&pctrl->lock);
937
938 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
939 pctrl->regs = devm_ioremap_resource(&pdev->dev, res);
940 if (IS_ERR(pctrl->regs))
941 return PTR_ERR(pctrl->regs);
942
943 pctrl->irq = platform_get_irq(pdev, 0);
944 if (pctrl->irq < 0) {
945 dev_err(&pdev->dev, "No interrupt defined for msmgpio\n");
946 return pctrl->irq;
947 }
948
949 msm_pinctrl_desc.name = dev_name(&pdev->dev);
950 msm_pinctrl_desc.pins = pctrl->soc->pins;
951 msm_pinctrl_desc.npins = pctrl->soc->npins;
952 pctrl->pctrl = pinctrl_register(&msm_pinctrl_desc, &pdev->dev, pctrl);
953 if (!pctrl->pctrl) {
954 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
955 return -ENODEV;
956 }
957
958 ret = msm_gpio_init(pctrl);
959 if (ret) {
960 pinctrl_unregister(pctrl->pctrl);
961 return ret;
962 }
963
964 platform_set_drvdata(pdev, pctrl);
965
966 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
967
968 return 0;
969}
970EXPORT_SYMBOL(msm_pinctrl_probe);
971
972int msm_pinctrl_remove(struct platform_device *pdev)
973{
974 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
975 int ret;
976
977 ret = gpiochip_remove(&pctrl->chip);
978 if (ret) {
979 dev_err(&pdev->dev, "Failed to remove gpiochip\n");
980 return ret;
981 }
982
983 irq_set_chained_handler(pctrl->irq, NULL);
984 irq_domain_remove(pctrl->domain);
985 pinctrl_unregister(pctrl->pctrl);
986
987 return 0;
988}
989EXPORT_SYMBOL(msm_pinctrl_remove);
990
diff --git a/drivers/pinctrl/pinctrl-msm.h b/drivers/pinctrl/pinctrl-msm.h
new file mode 100644
index 000000000000..206e782e2daa
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-msm.h
@@ -0,0 +1,122 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13#ifndef __PINCTRL_MSM_H__
14#define __PINCTRL_MSM_H__
15
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinmux.h>
18#include <linux/pinctrl/pinconf.h>
19#include <linux/pinctrl/machine.h>
20
21/**
22 * struct msm_function - a pinmux function
23 * @name: Name of the pinmux function.
24 * @groups: List of pingroups for this function.
25 * @ngroups: Number of entries in @groups.
26 */
27struct msm_function {
28 const char *name;
29 const char * const *groups;
30 unsigned ngroups;
31};
32
33/**
34 * struct msm_pingroup - Qualcomm pingroup definition
35 * @name: Name of the pingroup.
36 * @pins: A list of pins assigned to this pingroup.
37 * @npins: Number of entries in @pins.
38 * @funcs: A list of pinmux functions that can be selected for
39 * this group. The index of the selected function is used
40 * for programming the function selector.
41 * Entries should be indices into the groups list of the
42 * struct msm_pinctrl_soc_data.
43 * @ctl_reg: Offset of the register holding control bits for this group.
44 * @io_reg: Offset of the register holding input/output bits for this group.
45 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
46 * @intr_status_reg: Offset of the register holding the status bits for this group.
47 * @intr_target_reg: Offset of the register specifying routing of the interrupts
48 * from this group.
49 * @mux_bit: Offset in @ctl_reg for the pinmux function selection.
50 * @pull_bit: Offset in @ctl_reg for the bias configuration.
51 * @drv_bit: Offset in @ctl_reg for the drive strength configuration.
52 * @oe_bit: Offset in @ctl_reg for controlling output enable.
53 * @in_bit: Offset in @io_reg for the input bit value.
54 * @out_bit: Offset in @io_reg for the output bit value.
55 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
56 * @intr_status_bit: Offset in @intr_status_reg for reading and acking the interrupt
57 * status.
58 * @intr_target_bit: Offset in @intr_target_reg for configuring the interrupt routing.
59 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
60 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
61 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
62 * @intr_detection_width: Number of bits used for specifying interrupt type,
63 * Should be 2 for SoCs that can detect both edges in hardware,
64 * otherwise 1.
65 */
66struct msm_pingroup {
67 const char *name;
68 const unsigned *pins;
69 unsigned npins;
70
71 unsigned funcs[8];
72
73 s16 ctl_reg;
74 s16 io_reg;
75 s16 intr_cfg_reg;
76 s16 intr_status_reg;
77 s16 intr_target_reg;
78
79 unsigned mux_bit:5;
80
81 unsigned pull_bit:5;
82 unsigned drv_bit:5;
83
84 unsigned oe_bit:5;
85 unsigned in_bit:5;
86 unsigned out_bit:5;
87
88 unsigned intr_enable_bit:5;
89 unsigned intr_status_bit:5;
90
91 unsigned intr_target_bit:5;
92 unsigned intr_raw_status_bit:5;
93 unsigned intr_polarity_bit:5;
94 unsigned intr_detection_bit:5;
95 unsigned intr_detection_width:5;
96};
97
98/**
99 * struct msm_pinctrl_soc_data - Qualcomm pin controller driver configuration
100 * @pins: An array describing all pins the pin controller affects.
101 * @npins: The number of entries in @pins.
102 * @functions: An array describing all mux functions the SoC supports.
103 * @nfunctions: The number of entries in @functions.
104 * @groups: An array describing all pin groups the pin SoC supports.
105 * @ngroups: The numbmer of entries in @groups.
106 * @ngpio: The number of pingroups the driver should expose as GPIOs.
107 */
108struct msm_pinctrl_soc_data {
109 const struct pinctrl_pin_desc *pins;
110 unsigned npins;
111 const struct msm_function *functions;
112 unsigned nfunctions;
113 const struct msm_pingroup *groups;
114 unsigned ngroups;
115 unsigned ngpios;
116};
117
118int msm_pinctrl_probe(struct platform_device *pdev,
119 const struct msm_pinctrl_soc_data *soc_data);
120int msm_pinctrl_remove(struct platform_device *pdev);
121
122#endif
diff --git a/drivers/pinctrl/pinctrl-msm8x74.c b/drivers/pinctrl/pinctrl-msm8x74.c
new file mode 100644
index 000000000000..f944bf2172ef
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-msm8x74.c
@@ -0,0 +1,636 @@
1/*
2 * Copyright (c) 2013, Sony Mobile Communications AB.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 and
6 * only version 2 as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
12 */
13
14#include <linux/module.h>
15#include <linux/of.h>
16#include <linux/platform_device.h>
17#include <linux/pinctrl/pinctrl.h>
18#include <linux/pinctrl/pinmux.h>
19
20#include "pinctrl-msm.h"
21
22static const struct pinctrl_pin_desc msm8x74_pins[] = {
23 PINCTRL_PIN(0, "GPIO_0"),
24 PINCTRL_PIN(1, "GPIO_1"),
25 PINCTRL_PIN(2, "GPIO_2"),
26 PINCTRL_PIN(3, "GPIO_3"),
27 PINCTRL_PIN(4, "GPIO_4"),
28 PINCTRL_PIN(5, "GPIO_5"),
29 PINCTRL_PIN(6, "GPIO_6"),
30 PINCTRL_PIN(7, "GPIO_7"),
31 PINCTRL_PIN(8, "GPIO_8"),
32 PINCTRL_PIN(9, "GPIO_9"),
33 PINCTRL_PIN(10, "GPIO_10"),
34 PINCTRL_PIN(11, "GPIO_11"),
35 PINCTRL_PIN(12, "GPIO_12"),
36 PINCTRL_PIN(13, "GPIO_13"),
37 PINCTRL_PIN(14, "GPIO_14"),
38 PINCTRL_PIN(15, "GPIO_15"),
39 PINCTRL_PIN(16, "GPIO_16"),
40 PINCTRL_PIN(17, "GPIO_17"),
41 PINCTRL_PIN(18, "GPIO_18"),
42 PINCTRL_PIN(19, "GPIO_19"),
43 PINCTRL_PIN(20, "GPIO_20"),
44 PINCTRL_PIN(21, "GPIO_21"),
45 PINCTRL_PIN(22, "GPIO_22"),
46 PINCTRL_PIN(23, "GPIO_23"),
47 PINCTRL_PIN(24, "GPIO_24"),
48 PINCTRL_PIN(25, "GPIO_25"),
49 PINCTRL_PIN(26, "GPIO_26"),
50 PINCTRL_PIN(27, "GPIO_27"),
51 PINCTRL_PIN(28, "GPIO_28"),
52 PINCTRL_PIN(29, "GPIO_29"),
53 PINCTRL_PIN(30, "GPIO_30"),
54 PINCTRL_PIN(31, "GPIO_31"),
55 PINCTRL_PIN(32, "GPIO_32"),
56 PINCTRL_PIN(33, "GPIO_33"),
57 PINCTRL_PIN(34, "GPIO_34"),
58 PINCTRL_PIN(35, "GPIO_35"),
59 PINCTRL_PIN(36, "GPIO_36"),
60 PINCTRL_PIN(37, "GPIO_37"),
61 PINCTRL_PIN(38, "GPIO_38"),
62 PINCTRL_PIN(39, "GPIO_39"),
63 PINCTRL_PIN(40, "GPIO_40"),
64 PINCTRL_PIN(41, "GPIO_41"),
65 PINCTRL_PIN(42, "GPIO_42"),
66 PINCTRL_PIN(43, "GPIO_43"),
67 PINCTRL_PIN(44, "GPIO_44"),
68 PINCTRL_PIN(45, "GPIO_45"),
69 PINCTRL_PIN(46, "GPIO_46"),
70 PINCTRL_PIN(47, "GPIO_47"),
71 PINCTRL_PIN(48, "GPIO_48"),
72 PINCTRL_PIN(49, "GPIO_49"),
73 PINCTRL_PIN(50, "GPIO_50"),
74 PINCTRL_PIN(51, "GPIO_51"),
75 PINCTRL_PIN(52, "GPIO_52"),
76 PINCTRL_PIN(53, "GPIO_53"),
77 PINCTRL_PIN(54, "GPIO_54"),
78 PINCTRL_PIN(55, "GPIO_55"),
79 PINCTRL_PIN(56, "GPIO_56"),
80 PINCTRL_PIN(57, "GPIO_57"),
81 PINCTRL_PIN(58, "GPIO_58"),
82 PINCTRL_PIN(59, "GPIO_59"),
83 PINCTRL_PIN(60, "GPIO_60"),
84 PINCTRL_PIN(61, "GPIO_61"),
85 PINCTRL_PIN(62, "GPIO_62"),
86 PINCTRL_PIN(63, "GPIO_63"),
87 PINCTRL_PIN(64, "GPIO_64"),
88 PINCTRL_PIN(65, "GPIO_65"),
89 PINCTRL_PIN(66, "GPIO_66"),
90 PINCTRL_PIN(67, "GPIO_67"),
91 PINCTRL_PIN(68, "GPIO_68"),
92 PINCTRL_PIN(69, "GPIO_69"),
93 PINCTRL_PIN(70, "GPIO_70"),
94 PINCTRL_PIN(71, "GPIO_71"),
95 PINCTRL_PIN(72, "GPIO_72"),
96 PINCTRL_PIN(73, "GPIO_73"),
97 PINCTRL_PIN(74, "GPIO_74"),
98 PINCTRL_PIN(75, "GPIO_75"),
99 PINCTRL_PIN(76, "GPIO_76"),
100 PINCTRL_PIN(77, "GPIO_77"),
101 PINCTRL_PIN(78, "GPIO_78"),
102 PINCTRL_PIN(79, "GPIO_79"),
103 PINCTRL_PIN(80, "GPIO_80"),
104 PINCTRL_PIN(81, "GPIO_81"),
105 PINCTRL_PIN(82, "GPIO_82"),
106 PINCTRL_PIN(83, "GPIO_83"),
107 PINCTRL_PIN(84, "GPIO_84"),
108 PINCTRL_PIN(85, "GPIO_85"),
109 PINCTRL_PIN(86, "GPIO_86"),
110 PINCTRL_PIN(87, "GPIO_87"),
111 PINCTRL_PIN(88, "GPIO_88"),
112 PINCTRL_PIN(89, "GPIO_89"),
113 PINCTRL_PIN(90, "GPIO_90"),
114 PINCTRL_PIN(91, "GPIO_91"),
115 PINCTRL_PIN(92, "GPIO_92"),
116 PINCTRL_PIN(93, "GPIO_93"),
117 PINCTRL_PIN(94, "GPIO_94"),
118 PINCTRL_PIN(95, "GPIO_95"),
119 PINCTRL_PIN(96, "GPIO_96"),
120 PINCTRL_PIN(97, "GPIO_97"),
121 PINCTRL_PIN(98, "GPIO_98"),
122 PINCTRL_PIN(99, "GPIO_99"),
123 PINCTRL_PIN(100, "GPIO_100"),
124 PINCTRL_PIN(101, "GPIO_101"),
125 PINCTRL_PIN(102, "GPIO_102"),
126 PINCTRL_PIN(103, "GPIO_103"),
127 PINCTRL_PIN(104, "GPIO_104"),
128 PINCTRL_PIN(105, "GPIO_105"),
129 PINCTRL_PIN(106, "GPIO_106"),
130 PINCTRL_PIN(107, "GPIO_107"),
131 PINCTRL_PIN(108, "GPIO_108"),
132 PINCTRL_PIN(109, "GPIO_109"),
133 PINCTRL_PIN(110, "GPIO_110"),
134 PINCTRL_PIN(111, "GPIO_111"),
135 PINCTRL_PIN(112, "GPIO_112"),
136 PINCTRL_PIN(113, "GPIO_113"),
137 PINCTRL_PIN(114, "GPIO_114"),
138 PINCTRL_PIN(115, "GPIO_115"),
139 PINCTRL_PIN(116, "GPIO_116"),
140 PINCTRL_PIN(117, "GPIO_117"),
141 PINCTRL_PIN(118, "GPIO_118"),
142 PINCTRL_PIN(119, "GPIO_119"),
143 PINCTRL_PIN(120, "GPIO_120"),
144 PINCTRL_PIN(121, "GPIO_121"),
145 PINCTRL_PIN(122, "GPIO_122"),
146 PINCTRL_PIN(123, "GPIO_123"),
147 PINCTRL_PIN(124, "GPIO_124"),
148 PINCTRL_PIN(125, "GPIO_125"),
149 PINCTRL_PIN(126, "GPIO_126"),
150 PINCTRL_PIN(127, "GPIO_127"),
151 PINCTRL_PIN(128, "GPIO_128"),
152 PINCTRL_PIN(129, "GPIO_129"),
153 PINCTRL_PIN(130, "GPIO_130"),
154 PINCTRL_PIN(131, "GPIO_131"),
155 PINCTRL_PIN(132, "GPIO_132"),
156 PINCTRL_PIN(133, "GPIO_133"),
157 PINCTRL_PIN(134, "GPIO_134"),
158 PINCTRL_PIN(135, "GPIO_135"),
159 PINCTRL_PIN(136, "GPIO_136"),
160 PINCTRL_PIN(137, "GPIO_137"),
161 PINCTRL_PIN(138, "GPIO_138"),
162 PINCTRL_PIN(139, "GPIO_139"),
163 PINCTRL_PIN(140, "GPIO_140"),
164 PINCTRL_PIN(141, "GPIO_141"),
165 PINCTRL_PIN(142, "GPIO_142"),
166 PINCTRL_PIN(143, "GPIO_143"),
167 PINCTRL_PIN(144, "GPIO_144"),
168 PINCTRL_PIN(145, "GPIO_145"),
169
170 PINCTRL_PIN(146, "SDC1_CLK"),
171 PINCTRL_PIN(147, "SDC1_CMD"),
172 PINCTRL_PIN(148, "SDC1_DATA"),
173 PINCTRL_PIN(149, "SDC2_CLK"),
174 PINCTRL_PIN(150, "SDC2_CMD"),
175 PINCTRL_PIN(151, "SDC2_DATA"),
176};
177
178#define DECLARE_MSM_GPIO_PINS(pin) static const unsigned int gpio##pin##_pins[] = { pin }
179DECLARE_MSM_GPIO_PINS(0);
180DECLARE_MSM_GPIO_PINS(1);
181DECLARE_MSM_GPIO_PINS(2);
182DECLARE_MSM_GPIO_PINS(3);
183DECLARE_MSM_GPIO_PINS(4);
184DECLARE_MSM_GPIO_PINS(5);
185DECLARE_MSM_GPIO_PINS(6);
186DECLARE_MSM_GPIO_PINS(7);
187DECLARE_MSM_GPIO_PINS(8);
188DECLARE_MSM_GPIO_PINS(9);
189DECLARE_MSM_GPIO_PINS(10);
190DECLARE_MSM_GPIO_PINS(11);
191DECLARE_MSM_GPIO_PINS(12);
192DECLARE_MSM_GPIO_PINS(13);
193DECLARE_MSM_GPIO_PINS(14);
194DECLARE_MSM_GPIO_PINS(15);
195DECLARE_MSM_GPIO_PINS(16);
196DECLARE_MSM_GPIO_PINS(17);
197DECLARE_MSM_GPIO_PINS(18);
198DECLARE_MSM_GPIO_PINS(19);
199DECLARE_MSM_GPIO_PINS(20);
200DECLARE_MSM_GPIO_PINS(21);
201DECLARE_MSM_GPIO_PINS(22);
202DECLARE_MSM_GPIO_PINS(23);
203DECLARE_MSM_GPIO_PINS(24);
204DECLARE_MSM_GPIO_PINS(25);
205DECLARE_MSM_GPIO_PINS(26);
206DECLARE_MSM_GPIO_PINS(27);
207DECLARE_MSM_GPIO_PINS(28);
208DECLARE_MSM_GPIO_PINS(29);
209DECLARE_MSM_GPIO_PINS(30);
210DECLARE_MSM_GPIO_PINS(31);
211DECLARE_MSM_GPIO_PINS(32);
212DECLARE_MSM_GPIO_PINS(33);
213DECLARE_MSM_GPIO_PINS(34);
214DECLARE_MSM_GPIO_PINS(35);
215DECLARE_MSM_GPIO_PINS(36);
216DECLARE_MSM_GPIO_PINS(37);
217DECLARE_MSM_GPIO_PINS(38);
218DECLARE_MSM_GPIO_PINS(39);
219DECLARE_MSM_GPIO_PINS(40);
220DECLARE_MSM_GPIO_PINS(41);
221DECLARE_MSM_GPIO_PINS(42);
222DECLARE_MSM_GPIO_PINS(43);
223DECLARE_MSM_GPIO_PINS(44);
224DECLARE_MSM_GPIO_PINS(45);
225DECLARE_MSM_GPIO_PINS(46);
226DECLARE_MSM_GPIO_PINS(47);
227DECLARE_MSM_GPIO_PINS(48);
228DECLARE_MSM_GPIO_PINS(49);
229DECLARE_MSM_GPIO_PINS(50);
230DECLARE_MSM_GPIO_PINS(51);
231DECLARE_MSM_GPIO_PINS(52);
232DECLARE_MSM_GPIO_PINS(53);
233DECLARE_MSM_GPIO_PINS(54);
234DECLARE_MSM_GPIO_PINS(55);
235DECLARE_MSM_GPIO_PINS(56);
236DECLARE_MSM_GPIO_PINS(57);
237DECLARE_MSM_GPIO_PINS(58);
238DECLARE_MSM_GPIO_PINS(59);
239DECLARE_MSM_GPIO_PINS(60);
240DECLARE_MSM_GPIO_PINS(61);
241DECLARE_MSM_GPIO_PINS(62);
242DECLARE_MSM_GPIO_PINS(63);
243DECLARE_MSM_GPIO_PINS(64);
244DECLARE_MSM_GPIO_PINS(65);
245DECLARE_MSM_GPIO_PINS(66);
246DECLARE_MSM_GPIO_PINS(67);
247DECLARE_MSM_GPIO_PINS(68);
248DECLARE_MSM_GPIO_PINS(69);
249DECLARE_MSM_GPIO_PINS(70);
250DECLARE_MSM_GPIO_PINS(71);
251DECLARE_MSM_GPIO_PINS(72);
252DECLARE_MSM_GPIO_PINS(73);
253DECLARE_MSM_GPIO_PINS(74);
254DECLARE_MSM_GPIO_PINS(75);
255DECLARE_MSM_GPIO_PINS(76);
256DECLARE_MSM_GPIO_PINS(77);
257DECLARE_MSM_GPIO_PINS(78);
258DECLARE_MSM_GPIO_PINS(79);
259DECLARE_MSM_GPIO_PINS(80);
260DECLARE_MSM_GPIO_PINS(81);
261DECLARE_MSM_GPIO_PINS(82);
262DECLARE_MSM_GPIO_PINS(83);
263DECLARE_MSM_GPIO_PINS(84);
264DECLARE_MSM_GPIO_PINS(85);
265DECLARE_MSM_GPIO_PINS(86);
266DECLARE_MSM_GPIO_PINS(87);
267DECLARE_MSM_GPIO_PINS(88);
268DECLARE_MSM_GPIO_PINS(89);
269DECLARE_MSM_GPIO_PINS(90);
270DECLARE_MSM_GPIO_PINS(91);
271DECLARE_MSM_GPIO_PINS(92);
272DECLARE_MSM_GPIO_PINS(93);
273DECLARE_MSM_GPIO_PINS(94);
274DECLARE_MSM_GPIO_PINS(95);
275DECLARE_MSM_GPIO_PINS(96);
276DECLARE_MSM_GPIO_PINS(97);
277DECLARE_MSM_GPIO_PINS(98);
278DECLARE_MSM_GPIO_PINS(99);
279DECLARE_MSM_GPIO_PINS(100);
280DECLARE_MSM_GPIO_PINS(101);
281DECLARE_MSM_GPIO_PINS(102);
282DECLARE_MSM_GPIO_PINS(103);
283DECLARE_MSM_GPIO_PINS(104);
284DECLARE_MSM_GPIO_PINS(105);
285DECLARE_MSM_GPIO_PINS(106);
286DECLARE_MSM_GPIO_PINS(107);
287DECLARE_MSM_GPIO_PINS(108);
288DECLARE_MSM_GPIO_PINS(109);
289DECLARE_MSM_GPIO_PINS(110);
290DECLARE_MSM_GPIO_PINS(111);
291DECLARE_MSM_GPIO_PINS(112);
292DECLARE_MSM_GPIO_PINS(113);
293DECLARE_MSM_GPIO_PINS(114);
294DECLARE_MSM_GPIO_PINS(115);
295DECLARE_MSM_GPIO_PINS(116);
296DECLARE_MSM_GPIO_PINS(117);
297DECLARE_MSM_GPIO_PINS(118);
298DECLARE_MSM_GPIO_PINS(119);
299DECLARE_MSM_GPIO_PINS(120);
300DECLARE_MSM_GPIO_PINS(121);
301DECLARE_MSM_GPIO_PINS(122);
302DECLARE_MSM_GPIO_PINS(123);
303DECLARE_MSM_GPIO_PINS(124);
304DECLARE_MSM_GPIO_PINS(125);
305DECLARE_MSM_GPIO_PINS(126);
306DECLARE_MSM_GPIO_PINS(127);
307DECLARE_MSM_GPIO_PINS(128);
308DECLARE_MSM_GPIO_PINS(129);
309DECLARE_MSM_GPIO_PINS(130);
310DECLARE_MSM_GPIO_PINS(131);
311DECLARE_MSM_GPIO_PINS(132);
312DECLARE_MSM_GPIO_PINS(133);
313DECLARE_MSM_GPIO_PINS(134);
314DECLARE_MSM_GPIO_PINS(135);
315DECLARE_MSM_GPIO_PINS(136);
316DECLARE_MSM_GPIO_PINS(137);
317DECLARE_MSM_GPIO_PINS(138);
318DECLARE_MSM_GPIO_PINS(139);
319DECLARE_MSM_GPIO_PINS(140);
320DECLARE_MSM_GPIO_PINS(141);
321DECLARE_MSM_GPIO_PINS(142);
322DECLARE_MSM_GPIO_PINS(143);
323DECLARE_MSM_GPIO_PINS(144);
324DECLARE_MSM_GPIO_PINS(145);
325
326static const unsigned int sdc1_clk_pins[] = { 146 };
327static const unsigned int sdc1_cmd_pins[] = { 147 };
328static const unsigned int sdc1_data_pins[] = { 148 };
329static const unsigned int sdc2_clk_pins[] = { 149 };
330static const unsigned int sdc2_cmd_pins[] = { 150 };
331static const unsigned int sdc2_data_pins[] = { 151 };
332
333#define FUNCTION(fname) \
334 [MSM_MUX_##fname] = { \
335 .name = #fname, \
336 .groups = fname##_groups, \
337 .ngroups = ARRAY_SIZE(fname##_groups), \
338 }
339
340#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7) \
341 { \
342 .name = "gpio" #id, \
343 .pins = gpio##id##_pins, \
344 .npins = ARRAY_SIZE(gpio##id##_pins), \
345 .funcs = { \
346 MSM_MUX_NA, /* gpio mode */ \
347 MSM_MUX_##f1, \
348 MSM_MUX_##f2, \
349 MSM_MUX_##f3, \
350 MSM_MUX_##f4, \
351 MSM_MUX_##f5, \
352 MSM_MUX_##f6, \
353 MSM_MUX_##f7 \
354 }, \
355 .ctl_reg = 0x1000 + 0x10 * id, \
356 .io_reg = 0x1004 + 0x10 * id, \
357 .intr_cfg_reg = 0x1008 + 0x10 * id, \
358 .intr_status_reg = 0x100c + 0x10 * id, \
359 .intr_target_reg = 0x1008 + 0x10 * id, \
360 .mux_bit = 2, \
361 .pull_bit = 0, \
362 .drv_bit = 6, \
363 .oe_bit = 9, \
364 .in_bit = 0, \
365 .out_bit = 1, \
366 .intr_enable_bit = 0, \
367 .intr_status_bit = 0, \
368 .intr_target_bit = 5, \
369 .intr_raw_status_bit = 4, \
370 .intr_polarity_bit = 1, \
371 .intr_detection_bit = 2, \
372 .intr_detection_width = 2, \
373 }
374
375#define SDC_PINGROUP(pg_name, ctl, pull, drv) \
376 { \
377 .name = #pg_name, \
378 .pins = pg_name##_pins, \
379 .npins = ARRAY_SIZE(pg_name##_pins), \
380 .ctl_reg = ctl, \
381 .io_reg = 0, \
382 .intr_cfg_reg = 0, \
383 .intr_status_reg = 0, \
384 .intr_target_reg = 0, \
385 .mux_bit = -1, \
386 .pull_bit = pull, \
387 .drv_bit = drv, \
388 .oe_bit = -1, \
389 .in_bit = -1, \
390 .out_bit = -1, \
391 .intr_enable_bit = -1, \
392 .intr_status_bit = -1, \
393 .intr_target_bit = -1, \
394 .intr_raw_status_bit = -1, \
395 .intr_polarity_bit = -1, \
396 .intr_detection_bit = -1, \
397 .intr_detection_width = -1, \
398 }
399
400/*
401 * TODO: Add the rest of the possible functions and fill out
402 * the pingroup table below.
403 */
404enum msm8x74_functions {
405 MSM_MUX_blsp_i2c2,
406 MSM_MUX_blsp_i2c6,
407 MSM_MUX_blsp_i2c11,
408 MSM_MUX_blsp_spi1,
409 MSM_MUX_blsp_uart2,
410 MSM_MUX_blsp_uart8,
411 MSM_MUX_slimbus,
412 MSM_MUX_NA,
413};
414
415static const char * const blsp_i2c2_groups[] = { "gpio6", "gpio7" };
416static const char * const blsp_i2c6_groups[] = { "gpio29", "gpio30" };
417static const char * const blsp_i2c11_groups[] = { "gpio83", "gpio84" };
418static const char * const blsp_spi1_groups[] = { "gpio0", "gpio1", "gpio2", "gpio3" };
419static const char * const blsp_uart2_groups[] = { "gpio4", "gpio5" };
420static const char * const blsp_uart8_groups[] = { "gpio45", "gpio46" };
421static const char * const slimbus_groups[] = { "gpio70", "gpio71" };
422
423static const struct msm_function msm8x74_functions[] = {
424 FUNCTION(blsp_i2c2),
425 FUNCTION(blsp_i2c6),
426 FUNCTION(blsp_i2c11),
427 FUNCTION(blsp_spi1),
428 FUNCTION(blsp_uart2),
429 FUNCTION(blsp_uart8),
430 FUNCTION(slimbus),
431};
432
433static const struct msm_pingroup msm8x74_groups[] = {
434 PINGROUP(0, blsp_spi1, NA, NA, NA, NA, NA, NA),
435 PINGROUP(1, blsp_spi1, NA, NA, NA, NA, NA, NA),
436 PINGROUP(2, blsp_spi1, NA, NA, NA, NA, NA, NA),
437 PINGROUP(3, blsp_spi1, NA, NA, NA, NA, NA, NA),
438 PINGROUP(4, NA, blsp_uart2, NA, NA, NA, NA, NA),
439 PINGROUP(5, NA, blsp_uart2, NA, NA, NA, NA, NA),
440 PINGROUP(6, NA, NA, blsp_i2c2, NA, NA, NA, NA),
441 PINGROUP(7, NA, NA, blsp_i2c2, NA, NA, NA, NA),
442 PINGROUP(8, NA, NA, NA, NA, NA, NA, NA),
443 PINGROUP(9, NA, NA, NA, NA, NA, NA, NA),
444 PINGROUP(10, NA, NA, NA, NA, NA, NA, NA),
445 PINGROUP(11, NA, NA, NA, NA, NA, NA, NA),
446 PINGROUP(12, NA, NA, NA, NA, NA, NA, NA),
447 PINGROUP(13, NA, NA, NA, NA, NA, NA, NA),
448 PINGROUP(14, NA, NA, NA, NA, NA, NA, NA),
449 PINGROUP(15, NA, NA, NA, NA, NA, NA, NA),
450 PINGROUP(16, NA, NA, NA, NA, NA, NA, NA),
451 PINGROUP(17, NA, NA, NA, NA, NA, NA, NA),
452 PINGROUP(18, NA, NA, NA, NA, NA, NA, NA),
453 PINGROUP(19, NA, NA, NA, NA, NA, NA, NA),
454 PINGROUP(20, NA, NA, NA, NA, NA, NA, NA),
455 PINGROUP(21, NA, NA, NA, NA, NA, NA, NA),
456 PINGROUP(22, NA, NA, NA, NA, NA, NA, NA),
457 PINGROUP(23, NA, NA, NA, NA, NA, NA, NA),
458 PINGROUP(24, NA, NA, NA, NA, NA, NA, NA),
459 PINGROUP(25, NA, NA, NA, NA, NA, NA, NA),
460 PINGROUP(26, NA, NA, NA, NA, NA, NA, NA),
461 PINGROUP(27, NA, NA, NA, NA, NA, NA, NA),
462 PINGROUP(28, NA, NA, NA, NA, NA, NA, NA),
463 PINGROUP(29, NA, NA, blsp_i2c6, NA, NA, NA, NA),
464 PINGROUP(30, NA, NA, blsp_i2c6, NA, NA, NA, NA),
465 PINGROUP(31, NA, NA, NA, NA, NA, NA, NA),
466 PINGROUP(32, NA, NA, NA, NA, NA, NA, NA),
467 PINGROUP(33, NA, NA, NA, NA, NA, NA, NA),
468 PINGROUP(34, NA, NA, NA, NA, NA, NA, NA),
469 PINGROUP(35, NA, NA, NA, NA, NA, NA, NA),
470 PINGROUP(36, NA, NA, NA, NA, NA, NA, NA),
471 PINGROUP(37, NA, NA, NA, NA, NA, NA, NA),
472 PINGROUP(38, NA, NA, NA, NA, NA, NA, NA),
473 PINGROUP(39, NA, NA, NA, NA, NA, NA, NA),
474 PINGROUP(40, NA, NA, NA, NA, NA, NA, NA),
475 PINGROUP(41, NA, NA, NA, NA, NA, NA, NA),
476 PINGROUP(42, NA, NA, NA, NA, NA, NA, NA),
477 PINGROUP(43, NA, NA, NA, NA, NA, NA, NA),
478 PINGROUP(44, NA, NA, NA, NA, NA, NA, NA),
479 PINGROUP(45, NA, blsp_uart8, NA, NA, NA, NA, NA),
480 PINGROUP(46, NA, blsp_uart8, NA, NA, NA, NA, NA),
481 PINGROUP(47, NA, NA, NA, NA, NA, NA, NA),
482 PINGROUP(48, NA, NA, NA, NA, NA, NA, NA),
483 PINGROUP(49, NA, NA, NA, NA, NA, NA, NA),
484 PINGROUP(50, NA, NA, NA, NA, NA, NA, NA),
485 PINGROUP(51, NA, NA, NA, NA, NA, NA, NA),
486 PINGROUP(52, NA, NA, NA, NA, NA, NA, NA),
487 PINGROUP(53, NA, NA, NA, NA, NA, NA, NA),
488 PINGROUP(54, NA, NA, NA, NA, NA, NA, NA),
489 PINGROUP(55, NA, NA, NA, NA, NA, NA, NA),
490 PINGROUP(56, NA, NA, NA, NA, NA, NA, NA),
491 PINGROUP(57, NA, NA, NA, NA, NA, NA, NA),
492 PINGROUP(58, NA, NA, NA, NA, NA, NA, NA),
493 PINGROUP(59, NA, NA, NA, NA, NA, NA, NA),
494 PINGROUP(60, NA, NA, NA, NA, NA, NA, NA),
495 PINGROUP(61, NA, NA, NA, NA, NA, NA, NA),
496 PINGROUP(62, NA, NA, NA, NA, NA, NA, NA),
497 PINGROUP(63, NA, NA, NA, NA, NA, NA, NA),
498 PINGROUP(64, NA, NA, NA, NA, NA, NA, NA),
499 PINGROUP(65, NA, NA, NA, NA, NA, NA, NA),
500 PINGROUP(66, NA, NA, NA, NA, NA, NA, NA),
501 PINGROUP(67, NA, NA, NA, NA, NA, NA, NA),
502 PINGROUP(68, NA, NA, NA, NA, NA, NA, NA),
503 PINGROUP(69, NA, NA, NA, NA, NA, NA, NA),
504 PINGROUP(70, slimbus, NA, NA, NA, NA, NA, NA),
505 PINGROUP(71, slimbus, NA, NA, NA, NA, NA, NA),
506 PINGROUP(72, NA, NA, NA, NA, NA, NA, NA),
507 PINGROUP(73, NA, NA, NA, NA, NA, NA, NA),
508 PINGROUP(74, NA, NA, NA, NA, NA, NA, NA),
509 PINGROUP(75, NA, NA, NA, NA, NA, NA, NA),
510 PINGROUP(76, NA, NA, NA, NA, NA, NA, NA),
511 PINGROUP(77, NA, NA, NA, NA, NA, NA, NA),
512 PINGROUP(78, NA, NA, NA, NA, NA, NA, NA),
513 PINGROUP(79, NA, NA, NA, NA, NA, NA, NA),
514 PINGROUP(80, NA, NA, NA, NA, NA, NA, NA),
515 PINGROUP(81, NA, NA, NA, NA, NA, NA, NA),
516 PINGROUP(82, NA, NA, NA, NA, NA, NA, NA),
517 PINGROUP(83, NA, NA, blsp_i2c11, NA, NA, NA, NA),
518 PINGROUP(84, NA, NA, blsp_i2c11, NA, NA, NA, NA),
519 PINGROUP(85, NA, NA, NA, NA, NA, NA, NA),
520 PINGROUP(86, NA, NA, NA, NA, NA, NA, NA),
521 PINGROUP(87, NA, NA, NA, NA, NA, NA, NA),
522 PINGROUP(88, NA, NA, NA, NA, NA, NA, NA),
523 PINGROUP(89, NA, NA, NA, NA, NA, NA, NA),
524 PINGROUP(90, NA, NA, NA, NA, NA, NA, NA),
525 PINGROUP(91, NA, NA, NA, NA, NA, NA, NA),
526 PINGROUP(92, NA, NA, NA, NA, NA, NA, NA),
527 PINGROUP(93, NA, NA, NA, NA, NA, NA, NA),
528 PINGROUP(94, NA, NA, NA, NA, NA, NA, NA),
529 PINGROUP(95, NA, NA, NA, NA, NA, NA, NA),
530 PINGROUP(96, NA, NA, NA, NA, NA, NA, NA),
531 PINGROUP(97, NA, NA, NA, NA, NA, NA, NA),
532 PINGROUP(98, NA, NA, NA, NA, NA, NA, NA),
533 PINGROUP(99, NA, NA, NA, NA, NA, NA, NA),
534 PINGROUP(100, NA, NA, NA, NA, NA, NA, NA),
535 PINGROUP(101, NA, NA, NA, NA, NA, NA, NA),
536 PINGROUP(102, NA, NA, NA, NA, NA, NA, NA),
537 PINGROUP(103, NA, NA, NA, NA, NA, NA, NA),
538 PINGROUP(104, NA, NA, NA, NA, NA, NA, NA),
539 PINGROUP(105, NA, NA, NA, NA, NA, NA, NA),
540 PINGROUP(106, NA, NA, NA, NA, NA, NA, NA),
541 PINGROUP(107, NA, NA, NA, NA, NA, NA, NA),
542 PINGROUP(108, NA, NA, NA, NA, NA, NA, NA),
543 PINGROUP(109, NA, NA, NA, NA, NA, NA, NA),
544 PINGROUP(110, NA, NA, NA, NA, NA, NA, NA),
545 PINGROUP(111, NA, NA, NA, NA, NA, NA, NA),
546 PINGROUP(112, NA, NA, NA, NA, NA, NA, NA),
547 PINGROUP(113, NA, NA, NA, NA, NA, NA, NA),
548 PINGROUP(114, NA, NA, NA, NA, NA, NA, NA),
549 PINGROUP(115, NA, NA, NA, NA, NA, NA, NA),
550 PINGROUP(116, NA, NA, NA, NA, NA, NA, NA),
551 PINGROUP(117, NA, NA, NA, NA, NA, NA, NA),
552 PINGROUP(118, NA, NA, NA, NA, NA, NA, NA),
553 PINGROUP(119, NA, NA, NA, NA, NA, NA, NA),
554 PINGROUP(120, NA, NA, NA, NA, NA, NA, NA),
555 PINGROUP(121, NA, NA, NA, NA, NA, NA, NA),
556 PINGROUP(122, NA, NA, NA, NA, NA, NA, NA),
557 PINGROUP(123, NA, NA, NA, NA, NA, NA, NA),
558 PINGROUP(124, NA, NA, NA, NA, NA, NA, NA),
559 PINGROUP(125, NA, NA, NA, NA, NA, NA, NA),
560 PINGROUP(126, NA, NA, NA, NA, NA, NA, NA),
561 PINGROUP(127, NA, NA, NA, NA, NA, NA, NA),
562 PINGROUP(128, NA, NA, NA, NA, NA, NA, NA),
563 PINGROUP(129, NA, NA, NA, NA, NA, NA, NA),
564 PINGROUP(130, NA, NA, NA, NA, NA, NA, NA),
565 PINGROUP(131, NA, NA, NA, NA, NA, NA, NA),
566 PINGROUP(132, NA, NA, NA, NA, NA, NA, NA),
567 PINGROUP(133, NA, NA, NA, NA, NA, NA, NA),
568 PINGROUP(134, NA, NA, NA, NA, NA, NA, NA),
569 PINGROUP(135, NA, NA, NA, NA, NA, NA, NA),
570 PINGROUP(136, NA, NA, NA, NA, NA, NA, NA),
571 PINGROUP(137, NA, NA, NA, NA, NA, NA, NA),
572 PINGROUP(138, NA, NA, NA, NA, NA, NA, NA),
573 PINGROUP(139, NA, NA, NA, NA, NA, NA, NA),
574 PINGROUP(140, NA, NA, NA, NA, NA, NA, NA),
575 PINGROUP(141, NA, NA, NA, NA, NA, NA, NA),
576 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
577 PINGROUP(143, NA, NA, NA, NA, NA, NA, NA),
578 PINGROUP(144, NA, NA, NA, NA, NA, NA, NA),
579 PINGROUP(145, NA, NA, NA, NA, NA, NA, NA),
580 SDC_PINGROUP(sdc1_clk, 0x2044, 13, 6),
581 SDC_PINGROUP(sdc1_cmd, 0x2044, 11, 3),
582 SDC_PINGROUP(sdc1_data, 0x2044, 9, 0),
583 SDC_PINGROUP(sdc2_clk, 0x2048, 14, 6),
584 SDC_PINGROUP(sdc2_cmd, 0x2048, 11, 3),
585 SDC_PINGROUP(sdc2_data, 0x2048, 9, 0),
586};
587
588#define NUM_GPIO_PINGROUPS 146
589
590static const struct msm_pinctrl_soc_data msm8x74_pinctrl = {
591 .pins = msm8x74_pins,
592 .npins = ARRAY_SIZE(msm8x74_pins),
593 .functions = msm8x74_functions,
594 .nfunctions = ARRAY_SIZE(msm8x74_functions),
595 .groups = msm8x74_groups,
596 .ngroups = ARRAY_SIZE(msm8x74_groups),
597 .ngpios = NUM_GPIO_PINGROUPS,
598};
599
600static int msm8x74_pinctrl_probe(struct platform_device *pdev)
601{
602 return msm_pinctrl_probe(pdev, &msm8x74_pinctrl);
603}
604
605static const struct of_device_id msm8x74_pinctrl_of_match[] = {
606 { .compatible = "qcom,msm8974-pinctrl", },
607 { },
608};
609
610static struct platform_driver msm8x74_pinctrl_driver = {
611 .driver = {
612 .name = "msm8x74-pinctrl",
613 .owner = THIS_MODULE,
614 .of_match_table = msm8x74_pinctrl_of_match,
615 },
616 .probe = msm8x74_pinctrl_probe,
617 .remove = msm_pinctrl_remove,
618};
619
620static int __init msm8x74_pinctrl_init(void)
621{
622 return platform_driver_register(&msm8x74_pinctrl_driver);
623}
624arch_initcall(msm8x74_pinctrl_init);
625
626static void __exit msm8x74_pinctrl_exit(void)
627{
628 platform_driver_unregister(&msm8x74_pinctrl_driver);
629}
630module_exit(msm8x74_pinctrl_exit);
631
632MODULE_AUTHOR("Bjorn Andersson <bjorn.andersson@sonymobile.com>");
633MODULE_DESCRIPTION("Qualcomm MSM8x74 pinctrl driver");
634MODULE_LICENSE("GPL v2");
635MODULE_DEVICE_TABLE(of, msm8x74_pinctrl_of_match);
636
diff --git a/drivers/pinctrl/pinctrl-nomadik.c b/drivers/pinctrl/pinctrl-nomadik.c
index a21820fc4b7c..cd2b1a1c9275 100644
--- a/drivers/pinctrl/pinctrl-nomadik.c
+++ b/drivers/pinctrl/pinctrl-nomadik.c
@@ -846,14 +846,14 @@ static void nmk_gpio_dbg_show_one(struct seq_file *s,
846 (mode < 0) ? "unknown" : modes[mode], 846 (mode < 0) ? "unknown" : modes[mode],
847 pull ? "pull" : "none"); 847 pull ? "pull" : "none");
848 848
849 if (label && !is_out) { 849 if (!is_out) {
850 int irq = gpio_to_irq(gpio); 850 int irq = gpio_to_irq(gpio);
851 struct irq_desc *desc = irq_to_desc(irq); 851 struct irq_desc *desc = irq_to_desc(irq);
852 852
853 /* This races with request_irq(), set_irq_type(), 853 /* This races with request_irq(), set_irq_type(),
854 * and set_irq_wake() ... but those are "rare". 854 * and set_irq_wake() ... but those are "rare".
855 */ 855 */
856 if (irq >= 0 && desc->action) { 856 if (irq > 0 && desc && desc->action) {
857 char *trigger; 857 char *trigger;
858 u32 bitmask = nmk_gpio_get_bitmask(gpio); 858 u32 bitmask = nmk_gpio_get_bitmask(gpio);
859 859
diff --git a/drivers/pinctrl/pinctrl-single.c b/drivers/pinctrl/pinctrl-single.c
index 829b98c5c66f..de6459628b4f 100644
--- a/drivers/pinctrl/pinctrl-single.c
+++ b/drivers/pinctrl/pinctrl-single.c
@@ -525,12 +525,18 @@ static void pcs_disable(struct pinctrl_dev *pctldev, unsigned fselector,
525 for (i = 0; i < func->nvals; i++) { 525 for (i = 0; i < func->nvals; i++) {
526 struct pcs_func_vals *vals; 526 struct pcs_func_vals *vals;
527 unsigned long flags; 527 unsigned long flags;
528 unsigned val; 528 unsigned val, mask;
529 529
530 vals = &func->vals[i]; 530 vals = &func->vals[i];
531 raw_spin_lock_irqsave(&pcs->lock, flags); 531 raw_spin_lock_irqsave(&pcs->lock, flags);
532 val = pcs->read(vals->reg); 532 val = pcs->read(vals->reg);
533 val &= ~pcs->fmask; 533
534 if (pcs->bits_per_mux)
535 mask = vals->mask;
536 else
537 mask = pcs->fmask;
538
539 val &= ~mask;
534 val |= pcs->foff << pcs->fshift; 540 val |= pcs->foff << pcs->fshift;
535 pcs->write(val, vals->reg); 541 pcs->write(val, vals->reg);
536 raw_spin_unlock_irqrestore(&pcs->lock, flags); 542 raw_spin_unlock_irqrestore(&pcs->lock, flags);
@@ -1312,6 +1318,14 @@ static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1312 mask_pos = ((pcs->fmask) << (bit_pos - 1)); 1318 mask_pos = ((pcs->fmask) << (bit_pos - 1));
1313 val_pos = val & mask_pos; 1319 val_pos = val & mask_pos;
1314 submask = mask & mask_pos; 1320 submask = mask & mask_pos;
1321
1322 if ((mask & mask_pos) == 0) {
1323 dev_err(pcs->dev,
1324 "Invalid mask for %s at 0x%x\n",
1325 np->name, offset);
1326 break;
1327 }
1328
1315 mask &= ~mask_pos; 1329 mask &= ~mask_pos;
1316 1330
1317 if (submask != mask_pos) { 1331 if (submask != mask_pos) {
diff --git a/drivers/pinctrl/pinctrl-st.c b/drivers/pinctrl/pinctrl-st.c
index 9cadc68ee572..320c27363cc8 100644
--- a/drivers/pinctrl/pinctrl-st.c
+++ b/drivers/pinctrl/pinctrl-st.c
@@ -1370,10 +1370,10 @@ static int st_pctl_probe(struct platform_device *pdev)
1370 if (ret) 1370 if (ret)
1371 return ret; 1371 return ret;
1372 1372
1373 pctl_desc->owner = THIS_MODULE, 1373 pctl_desc->owner = THIS_MODULE;
1374 pctl_desc->pctlops = &st_pctlops, 1374 pctl_desc->pctlops = &st_pctlops;
1375 pctl_desc->pmxops = &st_pmxops, 1375 pctl_desc->pmxops = &st_pmxops;
1376 pctl_desc->confops = &st_confops, 1376 pctl_desc->confops = &st_confops;
1377 pctl_desc->name = dev_name(&pdev->dev); 1377 pctl_desc->name = dev_name(&pdev->dev);
1378 1378
1379 info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info); 1379 info->pctl = pinctrl_register(pctl_desc, &pdev->dev, info);
diff --git a/drivers/pinctrl/pinctrl-sunxi-pins.h b/drivers/pinctrl/pinctrl-sunxi-pins.h
index 2c7446a1a199..6fd8d4d95140 100644
--- a/drivers/pinctrl/pinctrl-sunxi-pins.h
+++ b/drivers/pinctrl/pinctrl-sunxi-pins.h
@@ -3774,12 +3774,14 @@ static const struct sunxi_desc_pin sun7i_a20_pins[] = {
3774 SUNXI_FUNCTION(0x1, "gpio_out"), 3774 SUNXI_FUNCTION(0x1, "gpio_out"),
3775 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */ 3775 SUNXI_FUNCTION(0x2, "spi0"), /* MOSI */
3776 SUNXI_FUNCTION(0x3, "uart6"), /* TX */ 3776 SUNXI_FUNCTION(0x3, "uart6"), /* TX */
3777 SUNXI_FUNCTION(0x4, "clk_out_a"), /* CLK_OUT_A */
3777 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */ 3778 SUNXI_FUNCTION_IRQ(0x5, 24)), /* EINT24 */
3778 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13, 3779 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI13,
3779 SUNXI_FUNCTION(0x0, "gpio_in"), 3780 SUNXI_FUNCTION(0x0, "gpio_in"),
3780 SUNXI_FUNCTION(0x1, "gpio_out"), 3781 SUNXI_FUNCTION(0x1, "gpio_out"),
3781 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */ 3782 SUNXI_FUNCTION(0x2, "spi0"), /* MISO */
3782 SUNXI_FUNCTION(0x3, "uart6"), /* RX */ 3783 SUNXI_FUNCTION(0x3, "uart6"), /* RX */
3784 SUNXI_FUNCTION(0x4, "clk_out_b"), /* CLK_OUT_B */
3783 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */ 3785 SUNXI_FUNCTION_IRQ(0x5, 25)), /* EINT25 */
3784 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14, 3786 SUNXI_PIN(SUNXI_PINCTRL_PIN_PI14,
3785 SUNXI_FUNCTION(0x0, "gpio_in"), 3787 SUNXI_FUNCTION(0x0, "gpio_in"),
diff --git a/drivers/pinctrl/pinctrl-sunxi.c b/drivers/pinctrl/pinctrl-sunxi.c
index 6b181cb90d39..9ccf681dad2f 100644
--- a/drivers/pinctrl/pinctrl-sunxi.c
+++ b/drivers/pinctrl/pinctrl-sunxi.c
@@ -469,12 +469,6 @@ static int sunxi_pinctrl_gpio_get(struct gpio_chip *chip, unsigned offset)
469 return val; 469 return val;
470} 470}
471 471
472static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
473 unsigned offset, int value)
474{
475 return pinctrl_gpio_direction_output(chip->base + offset);
476}
477
478static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip, 472static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
479 unsigned offset, int value) 473 unsigned offset, int value)
480{ 474{
@@ -498,6 +492,13 @@ static void sunxi_pinctrl_gpio_set(struct gpio_chip *chip,
498 spin_unlock_irqrestore(&pctl->lock, flags); 492 spin_unlock_irqrestore(&pctl->lock, flags);
499} 493}
500 494
495static int sunxi_pinctrl_gpio_direction_output(struct gpio_chip *chip,
496 unsigned offset, int value)
497{
498 sunxi_pinctrl_gpio_set(chip, offset, value);
499 return pinctrl_gpio_direction_output(chip->base + offset);
500}
501
501static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc, 502static int sunxi_pinctrl_gpio_of_xlate(struct gpio_chip *gc,
502 const struct of_phandle_args *gpiospec, 503 const struct of_phandle_args *gpiospec,
503 u32 *flags) 504 u32 *flags)
diff --git a/drivers/pinctrl/pinctrl-tegra124.c b/drivers/pinctrl/pinctrl-tegra124.c
new file mode 100644
index 000000000000..c20e0e1dda83
--- /dev/null
+++ b/drivers/pinctrl/pinctrl-tegra124.c
@@ -0,0 +1,3137 @@
1/*
2 * Pinctrl data for the NVIDIA Tegra124 pinmux
3 *
4 * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 */
15
16#include <linux/module.h>
17#include <linux/of.h>
18#include <linux/platform_device.h>
19#include <linux/pinctrl/pinctrl.h>
20#include <linux/pinctrl/pinmux.h>
21
22#include "pinctrl-tegra.h"
23
24/*
25 * Most pins affected by the pinmux can also be GPIOs. Define these first.
26 * These must match how the GPIO driver names/numbers its pins.
27 */
28#define _GPIO(offset) (offset)
29
30#define TEGRA_PIN_CLK_32K_OUT_PA0 _GPIO(0)
31#define TEGRA_PIN_UART3_CTS_N_PA1 _GPIO(1)
32#define TEGRA_PIN_DAP2_FS_PA2 _GPIO(2)
33#define TEGRA_PIN_DAP2_SCLK_PA3 _GPIO(3)
34#define TEGRA_PIN_DAP2_DIN_PA4 _GPIO(4)
35#define TEGRA_PIN_DAP2_DOUT_PA5 _GPIO(5)
36#define TEGRA_PIN_SDMMC3_CLK_PA6 _GPIO(6)
37#define TEGRA_PIN_SDMMC3_CMD_PA7 _GPIO(7)
38#define TEGRA_PIN_PB0 _GPIO(8)
39#define TEGRA_PIN_PB1 _GPIO(9)
40#define TEGRA_PIN_SDMMC3_DAT3_PB4 _GPIO(12)
41#define TEGRA_PIN_SDMMC3_DAT2_PB5 _GPIO(13)
42#define TEGRA_PIN_SDMMC3_DAT1_PB6 _GPIO(14)
43#define TEGRA_PIN_SDMMC3_DAT0_PB7 _GPIO(15)
44#define TEGRA_PIN_UART3_RTS_N_PC0 _GPIO(16)
45#define TEGRA_PIN_UART2_TXD_PC2 _GPIO(18)
46#define TEGRA_PIN_UART2_RXD_PC3 _GPIO(19)
47#define TEGRA_PIN_GEN1_I2C_SCL_PC4 _GPIO(20)
48#define TEGRA_PIN_GEN1_I2C_SDA_PC5 _GPIO(21)
49#define TEGRA_PIN_PC7 _GPIO(23)
50#define TEGRA_PIN_PG0 _GPIO(48)
51#define TEGRA_PIN_PG1 _GPIO(49)
52#define TEGRA_PIN_PG2 _GPIO(50)
53#define TEGRA_PIN_PG3 _GPIO(51)
54#define TEGRA_PIN_PG4 _GPIO(52)
55#define TEGRA_PIN_PG5 _GPIO(53)
56#define TEGRA_PIN_PG6 _GPIO(54)
57#define TEGRA_PIN_PG7 _GPIO(55)
58#define TEGRA_PIN_PH0 _GPIO(56)
59#define TEGRA_PIN_PH1 _GPIO(57)
60#define TEGRA_PIN_PH2 _GPIO(58)
61#define TEGRA_PIN_PH3 _GPIO(59)
62#define TEGRA_PIN_PH4 _GPIO(60)
63#define TEGRA_PIN_PH5 _GPIO(61)
64#define TEGRA_PIN_PH6 _GPIO(62)
65#define TEGRA_PIN_PH7 _GPIO(63)
66#define TEGRA_PIN_PI0 _GPIO(64)
67#define TEGRA_PIN_PI1 _GPIO(65)
68#define TEGRA_PIN_PI2 _GPIO(66)
69#define TEGRA_PIN_PI3 _GPIO(67)
70#define TEGRA_PIN_PI4 _GPIO(68)
71#define TEGRA_PIN_PI5 _GPIO(69)
72#define TEGRA_PIN_PI6 _GPIO(70)
73#define TEGRA_PIN_PI7 _GPIO(71)
74#define TEGRA_PIN_PJ0 _GPIO(72)
75#define TEGRA_PIN_PJ2 _GPIO(74)
76#define TEGRA_PIN_UART2_CTS_N_PJ5 _GPIO(77)
77#define TEGRA_PIN_UART2_RTS_N_PJ6 _GPIO(78)
78#define TEGRA_PIN_PJ7 _GPIO(79)
79#define TEGRA_PIN_PK0 _GPIO(80)
80#define TEGRA_PIN_PK1 _GPIO(81)
81#define TEGRA_PIN_PK2 _GPIO(82)
82#define TEGRA_PIN_PK3 _GPIO(83)
83#define TEGRA_PIN_PK4 _GPIO(84)
84#define TEGRA_PIN_SPDIF_OUT_PK5 _GPIO(85)
85#define TEGRA_PIN_SPDIF_IN_PK6 _GPIO(86)
86#define TEGRA_PIN_PK7 _GPIO(87)
87#define TEGRA_PIN_DAP1_FS_PN0 _GPIO(104)
88#define TEGRA_PIN_DAP1_DIN_PN1 _GPIO(105)
89#define TEGRA_PIN_DAP1_DOUT_PN2 _GPIO(106)
90#define TEGRA_PIN_DAP1_SCLK_PN3 _GPIO(107)
91#define TEGRA_PIN_USB_VBUS_EN0_PN4 _GPIO(108)
92#define TEGRA_PIN_USB_VBUS_EN1_PN5 _GPIO(109)
93#define TEGRA_PIN_HDMI_INT_PN7 _GPIO(111)
94#define TEGRA_PIN_ULPI_DATA7_PO0 _GPIO(112)
95#define TEGRA_PIN_ULPI_DATA0_PO1 _GPIO(113)
96#define TEGRA_PIN_ULPI_DATA1_PO2 _GPIO(114)
97#define TEGRA_PIN_ULPI_DATA2_PO3 _GPIO(115)
98#define TEGRA_PIN_ULPI_DATA3_PO4 _GPIO(116)
99#define TEGRA_PIN_ULPI_DATA4_PO5 _GPIO(117)
100#define TEGRA_PIN_ULPI_DATA5_PO6 _GPIO(118)
101#define TEGRA_PIN_ULPI_DATA6_PO7 _GPIO(119)
102#define TEGRA_PIN_DAP3_FS_PP0 _GPIO(120)
103#define TEGRA_PIN_DAP3_DIN_PP1 _GPIO(121)
104#define TEGRA_PIN_DAP3_DOUT_PP2 _GPIO(122)
105#define TEGRA_PIN_DAP3_SCLK_PP3 _GPIO(123)
106#define TEGRA_PIN_DAP4_FS_PP4 _GPIO(124)
107#define TEGRA_PIN_DAP4_DIN_PP5 _GPIO(125)
108#define TEGRA_PIN_DAP4_DOUT_PP6 _GPIO(126)
109#define TEGRA_PIN_DAP4_SCLK_PP7 _GPIO(127)
110#define TEGRA_PIN_KB_COL0_PQ0 _GPIO(128)
111#define TEGRA_PIN_KB_COL1_PQ1 _GPIO(129)
112#define TEGRA_PIN_KB_COL2_PQ2 _GPIO(130)
113#define TEGRA_PIN_KB_COL3_PQ3 _GPIO(131)
114#define TEGRA_PIN_KB_COL4_PQ4 _GPIO(132)
115#define TEGRA_PIN_KB_COL5_PQ5 _GPIO(133)
116#define TEGRA_PIN_KB_COL6_PQ6 _GPIO(134)
117#define TEGRA_PIN_KB_COL7_PQ7 _GPIO(135)
118#define TEGRA_PIN_KB_ROW0_PR0 _GPIO(136)
119#define TEGRA_PIN_KB_ROW1_PR1 _GPIO(137)
120#define TEGRA_PIN_KB_ROW2_PR2 _GPIO(138)
121#define TEGRA_PIN_KB_ROW3_PR3 _GPIO(139)
122#define TEGRA_PIN_KB_ROW4_PR4 _GPIO(140)
123#define TEGRA_PIN_KB_ROW5_PR5 _GPIO(141)
124#define TEGRA_PIN_KB_ROW6_PR6 _GPIO(142)
125#define TEGRA_PIN_KB_ROW7_PR7 _GPIO(143)
126#define TEGRA_PIN_KB_ROW8_PS0 _GPIO(144)
127#define TEGRA_PIN_KB_ROW9_PS1 _GPIO(145)
128#define TEGRA_PIN_KB_ROW10_PS2 _GPIO(146)
129#define TEGRA_PIN_KB_ROW11_PS3 _GPIO(147)
130#define TEGRA_PIN_KB_ROW12_PS4 _GPIO(148)
131#define TEGRA_PIN_KB_ROW13_PS5 _GPIO(149)
132#define TEGRA_PIN_KB_ROW14_PS6 _GPIO(150)
133#define TEGRA_PIN_KB_ROW15_PS7 _GPIO(151)
134#define TEGRA_PIN_KB_ROW16_PT0 _GPIO(152)
135#define TEGRA_PIN_KB_ROW17_PT1 _GPIO(153)
136#define TEGRA_PIN_GEN2_I2C_SCL_PT5 _GPIO(157)
137#define TEGRA_PIN_GEN2_I2C_SDA_PT6 _GPIO(158)
138#define TEGRA_PIN_SDMMC4_CMD_PT7 _GPIO(159)
139#define TEGRA_PIN_PU0 _GPIO(160)
140#define TEGRA_PIN_PU1 _GPIO(161)
141#define TEGRA_PIN_PU2 _GPIO(162)
142#define TEGRA_PIN_PU3 _GPIO(163)
143#define TEGRA_PIN_PU4 _GPIO(164)
144#define TEGRA_PIN_PU5 _GPIO(165)
145#define TEGRA_PIN_PU6 _GPIO(166)
146#define TEGRA_PIN_PV0 _GPIO(168)
147#define TEGRA_PIN_PV1 _GPIO(169)
148#define TEGRA_PIN_SDMMC3_CD_N_PV2 _GPIO(170)
149#define TEGRA_PIN_SDMMC1_WP_N_PV3 _GPIO(171)
150#define TEGRA_PIN_DDC_SCL_PV4 _GPIO(172)
151#define TEGRA_PIN_DDC_SDA_PV5 _GPIO(173)
152#define TEGRA_PIN_GPIO_W2_AUD_PW2 _GPIO(178)
153#define TEGRA_PIN_GPIO_W3_AUD_PW3 _GPIO(179)
154#define TEGRA_PIN_DAP_MCLK1_PW4 _GPIO(180)
155#define TEGRA_PIN_CLK2_OUT_PW5 _GPIO(181)
156#define TEGRA_PIN_UART3_TXD_PW6 _GPIO(182)
157#define TEGRA_PIN_UART3_RXD_PW7 _GPIO(183)
158#define TEGRA_PIN_DVFS_PWM_PX0 _GPIO(184)
159#define TEGRA_PIN_GPIO_X1_AUD_PX1 _GPIO(185)
160#define TEGRA_PIN_DVFS_CLK_PX2 _GPIO(186)
161#define TEGRA_PIN_GPIO_X3_AUD_PX3 _GPIO(187)
162#define TEGRA_PIN_GPIO_X4_AUD_PX4 _GPIO(188)
163#define TEGRA_PIN_GPIO_X5_AUD_PX5 _GPIO(189)
164#define TEGRA_PIN_GPIO_X6_AUD_PX6 _GPIO(190)
165#define TEGRA_PIN_GPIO_X7_AUD_PX7 _GPIO(191)
166#define TEGRA_PIN_ULPI_CLK_PY0 _GPIO(192)
167#define TEGRA_PIN_ULPI_DIR_PY1 _GPIO(193)
168#define TEGRA_PIN_ULPI_NXT_PY2 _GPIO(194)
169#define TEGRA_PIN_ULPI_STP_PY3 _GPIO(195)
170#define TEGRA_PIN_SDMMC1_DAT3_PY4 _GPIO(196)
171#define TEGRA_PIN_SDMMC1_DAT2_PY5 _GPIO(197)
172#define TEGRA_PIN_SDMMC1_DAT1_PY6 _GPIO(198)
173#define TEGRA_PIN_SDMMC1_DAT0_PY7 _GPIO(199)
174#define TEGRA_PIN_SDMMC1_CLK_PZ0 _GPIO(200)
175#define TEGRA_PIN_SDMMC1_CMD_PZ1 _GPIO(201)
176#define TEGRA_PIN_PWR_I2C_SCL_PZ6 _GPIO(206)
177#define TEGRA_PIN_PWR_I2C_SDA_PZ7 _GPIO(207)
178#define TEGRA_PIN_SDMMC4_DAT0_PAA0 _GPIO(208)
179#define TEGRA_PIN_SDMMC4_DAT1_PAA1 _GPIO(209)
180#define TEGRA_PIN_SDMMC4_DAT2_PAA2 _GPIO(210)
181#define TEGRA_PIN_SDMMC4_DAT3_PAA3 _GPIO(211)
182#define TEGRA_PIN_SDMMC4_DAT4_PAA4 _GPIO(212)
183#define TEGRA_PIN_SDMMC4_DAT5_PAA5 _GPIO(213)
184#define TEGRA_PIN_SDMMC4_DAT6_PAA6 _GPIO(214)
185#define TEGRA_PIN_SDMMC4_DAT7_PAA7 _GPIO(215)
186#define TEGRA_PIN_PBB0 _GPIO(216)
187#define TEGRA_PIN_CAM_I2C_SCL_PBB1 _GPIO(217)
188#define TEGRA_PIN_CAM_I2C_SDA_PBB2 _GPIO(218)
189#define TEGRA_PIN_PBB3 _GPIO(219)
190#define TEGRA_PIN_PBB4 _GPIO(220)
191#define TEGRA_PIN_PBB5 _GPIO(221)
192#define TEGRA_PIN_PBB6 _GPIO(222)
193#define TEGRA_PIN_PBB7 _GPIO(223)
194#define TEGRA_PIN_CAM_MCLK_PCC0 _GPIO(224)
195#define TEGRA_PIN_PCC1 _GPIO(225)
196#define TEGRA_PIN_PCC2 _GPIO(226)
197#define TEGRA_PIN_SDMMC4_CLK_PCC4 _GPIO(228)
198#define TEGRA_PIN_CLK2_REQ_PCC5 _GPIO(229)
199#define TEGRA_PIN_PEX_L0_RST_N_PDD1 _GPIO(233)
200#define TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2 _GPIO(234)
201#define TEGRA_PIN_PEX_WAKE_N_PDD3 _GPIO(235)
202#define TEGRA_PIN_PEX_L1_RST_N_PDD5 _GPIO(237)
203#define TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6 _GPIO(238)
204#define TEGRA_PIN_CLK3_OUT_PEE0 _GPIO(240)
205#define TEGRA_PIN_CLK3_REQ_PEE1 _GPIO(241)
206#define TEGRA_PIN_DAP_MCLK1_REQ_PEE2 _GPIO(242)
207#define TEGRA_PIN_HDMI_CEC_PEE3 _GPIO(243)
208#define TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4 _GPIO(244)
209#define TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5 _GPIO(245)
210#define TEGRA_PIN_DP_HPD_PFF0 _GPIO(248)
211#define TEGRA_PIN_USB_VBUS_EN2_PFF1 _GPIO(249)
212#define TEGRA_PIN_PFF2 _GPIO(250)
213
214/* All non-GPIO pins follow */
215#define NUM_GPIOS (TEGRA_PIN_PFF2 + 1)
216#define _PIN(offset) (NUM_GPIOS + (offset))
217
218/* Non-GPIO pins */
219#define TEGRA_PIN_CORE_PWR_REQ _PIN(0)
220#define TEGRA_PIN_CPU_PWR_REQ _PIN(1)
221#define TEGRA_PIN_PWR_INT_N _PIN(2)
222#define TEGRA_PIN_GMI_CLK_LB _PIN(3)
223#define TEGRA_PIN_RESET_OUT_N _PIN(4)
224#define TEGRA_PIN_OWR _PIN(5)
225#define TEGRA_PIN_CLK_32K_IN _PIN(6)
226#define TEGRA_PIN_JTAG_RTCK _PIN(7)
227
228static const struct pinctrl_pin_desc tegra124_pins[] = {
229 PINCTRL_PIN(TEGRA_PIN_CLK_32K_OUT_PA0, "CLK_32K_OUT PA0"),
230 PINCTRL_PIN(TEGRA_PIN_UART3_CTS_N_PA1, "UART3_CTS_N PA1"),
231 PINCTRL_PIN(TEGRA_PIN_DAP2_FS_PA2, "DAP2_FS PA2"),
232 PINCTRL_PIN(TEGRA_PIN_DAP2_SCLK_PA3, "DAP2_SCLK PA3"),
233 PINCTRL_PIN(TEGRA_PIN_DAP2_DIN_PA4, "DAP2_DIN PA4"),
234 PINCTRL_PIN(TEGRA_PIN_DAP2_DOUT_PA5, "DAP2_DOUT PA5"),
235 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_PA6, "SDMMC3_CLK PA6"),
236 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CMD_PA7, "SDMMC3_CMD PA7"),
237 PINCTRL_PIN(TEGRA_PIN_PB0, "PB0"),
238 PINCTRL_PIN(TEGRA_PIN_PB1, "PB1"),
239 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT3_PB4, "SDMMC3_DAT3 PB4"),
240 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT2_PB5, "SDMMC3_DAT2 PB5"),
241 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT1_PB6, "SDMMC3_DAT1 PB6"),
242 PINCTRL_PIN(TEGRA_PIN_SDMMC3_DAT0_PB7, "SDMMC3_DAT0 PB7"),
243 PINCTRL_PIN(TEGRA_PIN_UART3_RTS_N_PC0, "UART3_RTS_N PC0"),
244 PINCTRL_PIN(TEGRA_PIN_UART2_TXD_PC2, "UART2_TXD PC2"),
245 PINCTRL_PIN(TEGRA_PIN_UART2_RXD_PC3, "UART2_RXD PC3"),
246 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SCL_PC4, "GEN1_I2C_SCL PC4"),
247 PINCTRL_PIN(TEGRA_PIN_GEN1_I2C_SDA_PC5, "GEN1_I2C_SDA PC5"),
248 PINCTRL_PIN(TEGRA_PIN_PC7, "PC7"),
249 PINCTRL_PIN(TEGRA_PIN_PG0, "PG0"),
250 PINCTRL_PIN(TEGRA_PIN_PG1, "PG1"),
251 PINCTRL_PIN(TEGRA_PIN_PG2, "PG2"),
252 PINCTRL_PIN(TEGRA_PIN_PG3, "PG3"),
253 PINCTRL_PIN(TEGRA_PIN_PG4, "PG4"),
254 PINCTRL_PIN(TEGRA_PIN_PG5, "PG5"),
255 PINCTRL_PIN(TEGRA_PIN_PG6, "PG6"),
256 PINCTRL_PIN(TEGRA_PIN_PG7, "PG7"),
257 PINCTRL_PIN(TEGRA_PIN_PH0, "PH0"),
258 PINCTRL_PIN(TEGRA_PIN_PH1, "PH1"),
259 PINCTRL_PIN(TEGRA_PIN_PH2, "PH2"),
260 PINCTRL_PIN(TEGRA_PIN_PH3, "PH3"),
261 PINCTRL_PIN(TEGRA_PIN_PH4, "PH4"),
262 PINCTRL_PIN(TEGRA_PIN_PH5, "PH5"),
263 PINCTRL_PIN(TEGRA_PIN_PH6, "PH6"),
264 PINCTRL_PIN(TEGRA_PIN_PH7, "PH7"),
265 PINCTRL_PIN(TEGRA_PIN_PI0, "PI0"),
266 PINCTRL_PIN(TEGRA_PIN_PI1, "PI1"),
267 PINCTRL_PIN(TEGRA_PIN_PI2, "PI2"),
268 PINCTRL_PIN(TEGRA_PIN_PI3, "PI3"),
269 PINCTRL_PIN(TEGRA_PIN_PI4, "PI4"),
270 PINCTRL_PIN(TEGRA_PIN_PI5, "PI5"),
271 PINCTRL_PIN(TEGRA_PIN_PI6, "PI6"),
272 PINCTRL_PIN(TEGRA_PIN_PI7, "PI7"),
273 PINCTRL_PIN(TEGRA_PIN_PJ0, "PJ0"),
274 PINCTRL_PIN(TEGRA_PIN_PJ2, "PJ2"),
275 PINCTRL_PIN(TEGRA_PIN_UART2_CTS_N_PJ5, "UART2_CTS_N PJ5"),
276 PINCTRL_PIN(TEGRA_PIN_UART2_RTS_N_PJ6, "UART2_RTS_N PJ6"),
277 PINCTRL_PIN(TEGRA_PIN_PJ7, "PJ7"),
278 PINCTRL_PIN(TEGRA_PIN_PK0, "PK0"),
279 PINCTRL_PIN(TEGRA_PIN_PK1, "PK1"),
280 PINCTRL_PIN(TEGRA_PIN_PK2, "PK2"),
281 PINCTRL_PIN(TEGRA_PIN_PK3, "PK3"),
282 PINCTRL_PIN(TEGRA_PIN_PK4, "PK4"),
283 PINCTRL_PIN(TEGRA_PIN_SPDIF_OUT_PK5, "SPDIF_OUT PK5"),
284 PINCTRL_PIN(TEGRA_PIN_SPDIF_IN_PK6, "SPDIF_IN PK6"),
285 PINCTRL_PIN(TEGRA_PIN_PK7, "PK7"),
286 PINCTRL_PIN(TEGRA_PIN_DAP1_FS_PN0, "DAP1_FS PN0"),
287 PINCTRL_PIN(TEGRA_PIN_DAP1_DIN_PN1, "DAP1_DIN PN1"),
288 PINCTRL_PIN(TEGRA_PIN_DAP1_DOUT_PN2, "DAP1_DOUT PN2"),
289 PINCTRL_PIN(TEGRA_PIN_DAP1_SCLK_PN3, "DAP1_SCLK PN3"),
290 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN0_PN4, "USB_VBUS_EN0 PN4"),
291 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN1_PN5, "USB_VBUS_EN1 PN5"),
292 PINCTRL_PIN(TEGRA_PIN_HDMI_INT_PN7, "HDMI_INT PN7"),
293 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA7_PO0, "ULPI_DATA7 PO0"),
294 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA0_PO1, "ULPI_DATA0 PO1"),
295 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA1_PO2, "ULPI_DATA1 PO2"),
296 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA2_PO3, "ULPI_DATA2 PO3"),
297 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA3_PO4, "ULPI_DATA3 PO4"),
298 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA4_PO5, "ULPI_DATA4 PO5"),
299 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA5_PO6, "ULPI_DATA5 PO6"),
300 PINCTRL_PIN(TEGRA_PIN_ULPI_DATA6_PO7, "ULPI_DATA6 PO7"),
301 PINCTRL_PIN(TEGRA_PIN_DAP3_FS_PP0, "DAP3_FS PP0"),
302 PINCTRL_PIN(TEGRA_PIN_DAP3_DIN_PP1, "DAP3_DIN PP1"),
303 PINCTRL_PIN(TEGRA_PIN_DAP3_DOUT_PP2, "DAP3_DOUT PP2"),
304 PINCTRL_PIN(TEGRA_PIN_DAP3_SCLK_PP3, "DAP3_SCLK PP3"),
305 PINCTRL_PIN(TEGRA_PIN_DAP4_FS_PP4, "DAP4_FS PP4"),
306 PINCTRL_PIN(TEGRA_PIN_DAP4_DIN_PP5, "DAP4_DIN PP5"),
307 PINCTRL_PIN(TEGRA_PIN_DAP4_DOUT_PP6, "DAP4_DOUT PP6"),
308 PINCTRL_PIN(TEGRA_PIN_DAP4_SCLK_PP7, "DAP4_SCLK PP7"),
309 PINCTRL_PIN(TEGRA_PIN_KB_COL0_PQ0, "KB_COL0 PQ0"),
310 PINCTRL_PIN(TEGRA_PIN_KB_COL1_PQ1, "KB_COL1 PQ1"),
311 PINCTRL_PIN(TEGRA_PIN_KB_COL2_PQ2, "KB_COL2 PQ2"),
312 PINCTRL_PIN(TEGRA_PIN_KB_COL3_PQ3, "KB_COL3 PQ3"),
313 PINCTRL_PIN(TEGRA_PIN_KB_COL4_PQ4, "KB_COL4 PQ4"),
314 PINCTRL_PIN(TEGRA_PIN_KB_COL5_PQ5, "KB_COL5 PQ5"),
315 PINCTRL_PIN(TEGRA_PIN_KB_COL6_PQ6, "KB_COL6 PQ6"),
316 PINCTRL_PIN(TEGRA_PIN_KB_COL7_PQ7, "KB_COL7 PQ7"),
317 PINCTRL_PIN(TEGRA_PIN_KB_ROW0_PR0, "KB_ROW0 PR0"),
318 PINCTRL_PIN(TEGRA_PIN_KB_ROW1_PR1, "KB_ROW1 PR1"),
319 PINCTRL_PIN(TEGRA_PIN_KB_ROW2_PR2, "KB_ROW2 PR2"),
320 PINCTRL_PIN(TEGRA_PIN_KB_ROW3_PR3, "KB_ROW3 PR3"),
321 PINCTRL_PIN(TEGRA_PIN_KB_ROW4_PR4, "KB_ROW4 PR4"),
322 PINCTRL_PIN(TEGRA_PIN_KB_ROW5_PR5, "KB_ROW5 PR5"),
323 PINCTRL_PIN(TEGRA_PIN_KB_ROW6_PR6, "KB_ROW6 PR6"),
324 PINCTRL_PIN(TEGRA_PIN_KB_ROW7_PR7, "KB_ROW7 PR7"),
325 PINCTRL_PIN(TEGRA_PIN_KB_ROW8_PS0, "KB_ROW8 PS0"),
326 PINCTRL_PIN(TEGRA_PIN_KB_ROW9_PS1, "KB_ROW9 PS1"),
327 PINCTRL_PIN(TEGRA_PIN_KB_ROW10_PS2, "KB_ROW10 PS2"),
328 PINCTRL_PIN(TEGRA_PIN_KB_ROW11_PS3, "KB_ROW10 PS3"),
329 PINCTRL_PIN(TEGRA_PIN_KB_ROW12_PS4, "KB_ROW10 PS4"),
330 PINCTRL_PIN(TEGRA_PIN_KB_ROW13_PS5, "KB_ROW10 PS5"),
331 PINCTRL_PIN(TEGRA_PIN_KB_ROW14_PS6, "KB_ROW10 PS6"),
332 PINCTRL_PIN(TEGRA_PIN_KB_ROW15_PS7, "KB_ROW10 PS7"),
333 PINCTRL_PIN(TEGRA_PIN_KB_ROW16_PT0, "KB_ROW10 PT0"),
334 PINCTRL_PIN(TEGRA_PIN_KB_ROW17_PT1, "KB_ROW10 PT1"),
335 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SCL_PT5, "GEN2_I2C_SCL PT5"),
336 PINCTRL_PIN(TEGRA_PIN_GEN2_I2C_SDA_PT6, "GEN2_I2C_SDA PT6"),
337 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CMD_PT7, "SDMMC4_CMD PT7"),
338 PINCTRL_PIN(TEGRA_PIN_PU0, "PU0"),
339 PINCTRL_PIN(TEGRA_PIN_PU1, "PU1"),
340 PINCTRL_PIN(TEGRA_PIN_PU2, "PU2"),
341 PINCTRL_PIN(TEGRA_PIN_PU3, "PU3"),
342 PINCTRL_PIN(TEGRA_PIN_PU4, "PU4"),
343 PINCTRL_PIN(TEGRA_PIN_PU5, "PU5"),
344 PINCTRL_PIN(TEGRA_PIN_PU6, "PU6"),
345 PINCTRL_PIN(TEGRA_PIN_PV0, "PV0"),
346 PINCTRL_PIN(TEGRA_PIN_PV1, "PV1"),
347 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CD_N_PV2, "SDMMC3_CD_N PV2"),
348 PINCTRL_PIN(TEGRA_PIN_SDMMC1_WP_N_PV3, "SDMMC1_WP_N PV3"),
349 PINCTRL_PIN(TEGRA_PIN_DDC_SCL_PV4, "DDC_SCL PV4"),
350 PINCTRL_PIN(TEGRA_PIN_DDC_SDA_PV5, "DDC_SDA PV5"),
351 PINCTRL_PIN(TEGRA_PIN_GPIO_W2_AUD_PW2, "GPIO_W2_AUD PW2"),
352 PINCTRL_PIN(TEGRA_PIN_GPIO_W3_AUD_PW3, "GPIO_W3_AUD PW3"),
353 PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_PW4, "DAP_MCLK1 PW4"),
354 PINCTRL_PIN(TEGRA_PIN_CLK2_OUT_PW5, "CLK2_OUT PW5"),
355 PINCTRL_PIN(TEGRA_PIN_UART3_TXD_PW6, "UART3_TXD PW6"),
356 PINCTRL_PIN(TEGRA_PIN_UART3_RXD_PW7, "UART3_RXD PW7"),
357 PINCTRL_PIN(TEGRA_PIN_DVFS_PWM_PX0, "DVFS_PWM PX0"),
358 PINCTRL_PIN(TEGRA_PIN_GPIO_X1_AUD_PX1, "GPIO_X1_AUD PX1"),
359 PINCTRL_PIN(TEGRA_PIN_DVFS_CLK_PX2, "DVFS_CLK PX2"),
360 PINCTRL_PIN(TEGRA_PIN_GPIO_X3_AUD_PX3, "GPIO_X3_AUD PX3"),
361 PINCTRL_PIN(TEGRA_PIN_GPIO_X4_AUD_PX4, "GPIO_X4_AUD PX4"),
362 PINCTRL_PIN(TEGRA_PIN_GPIO_X5_AUD_PX5, "GPIO_X5_AUD PX5"),
363 PINCTRL_PIN(TEGRA_PIN_GPIO_X6_AUD_PX6, "GPIO_X6_AUD PX6"),
364 PINCTRL_PIN(TEGRA_PIN_GPIO_X7_AUD_PX7, "GPIO_X7_AUD PX7"),
365 PINCTRL_PIN(TEGRA_PIN_ULPI_CLK_PY0, "ULPI_CLK PY0"),
366 PINCTRL_PIN(TEGRA_PIN_ULPI_DIR_PY1, "ULPI_DIR PY1"),
367 PINCTRL_PIN(TEGRA_PIN_ULPI_NXT_PY2, "ULPI_NXT PY2"),
368 PINCTRL_PIN(TEGRA_PIN_ULPI_STP_PY3, "ULPI_STP PY3"),
369 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT3_PY4, "SDMMC1_DAT3 PY4"),
370 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT2_PY5, "SDMMC1_DAT2 PY5"),
371 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT1_PY6, "SDMMC1_DAT1 PY6"),
372 PINCTRL_PIN(TEGRA_PIN_SDMMC1_DAT0_PY7, "SDMMC1_DAT0 PY7"),
373 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CLK_PZ0, "SDMMC1_CLK PZ0"),
374 PINCTRL_PIN(TEGRA_PIN_SDMMC1_CMD_PZ1, "SDMMC1_CMD PZ1"),
375 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SCL_PZ6, "PWR_I2C_SCL PZ6"),
376 PINCTRL_PIN(TEGRA_PIN_PWR_I2C_SDA_PZ7, "PWR_I2C_SDA PZ7"),
377 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT0_PAA0, "SDMMC4_DAT0 PAA0"),
378 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT1_PAA1, "SDMMC4_DAT1 PAA1"),
379 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT2_PAA2, "SDMMC4_DAT2 PAA2"),
380 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT3_PAA3, "SDMMC4_DAT3 PAA3"),
381 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT4_PAA4, "SDMMC4_DAT4 PAA4"),
382 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT5_PAA5, "SDMMC4_DAT5 PAA5"),
383 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT6_PAA6, "SDMMC4_DAT6 PAA6"),
384 PINCTRL_PIN(TEGRA_PIN_SDMMC4_DAT7_PAA7, "SDMMC4_DAT7 PAA7"),
385 PINCTRL_PIN(TEGRA_PIN_PBB0, "PBB0"),
386 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SCL_PBB1, "CAM_I2C_SCL PBB1"),
387 PINCTRL_PIN(TEGRA_PIN_CAM_I2C_SDA_PBB2, "CAM_I2C_SDA PBB2"),
388 PINCTRL_PIN(TEGRA_PIN_PBB3, "PBB3"),
389 PINCTRL_PIN(TEGRA_PIN_PBB4, "PBB4"),
390 PINCTRL_PIN(TEGRA_PIN_PBB5, "PBB5"),
391 PINCTRL_PIN(TEGRA_PIN_PBB6, "PBB6"),
392 PINCTRL_PIN(TEGRA_PIN_PBB7, "PBB7"),
393 PINCTRL_PIN(TEGRA_PIN_CAM_MCLK_PCC0, "CAM_MCLK PCC0"),
394 PINCTRL_PIN(TEGRA_PIN_PCC1, "PCC1"),
395 PINCTRL_PIN(TEGRA_PIN_PCC2, "PCC2"),
396 PINCTRL_PIN(TEGRA_PIN_SDMMC4_CLK_PCC4, "SDMMC4_CLK PCC4"),
397 PINCTRL_PIN(TEGRA_PIN_CLK2_REQ_PCC5, "CLK2_REQ PCC5"),
398 PINCTRL_PIN(TEGRA_PIN_PEX_L0_RST_N_PDD1, "PEX_L0_RST_N PDD1"),
399 PINCTRL_PIN(TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2, "PEX_L0_CLKREQ_N PDD2"),
400 PINCTRL_PIN(TEGRA_PIN_PEX_WAKE_N_PDD3, "PEX_WAKE_N PDD3"),
401 PINCTRL_PIN(TEGRA_PIN_PEX_L1_RST_N_PDD5, "PEX_L1_RST_N PDD5"),
402 PINCTRL_PIN(TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6, "PEX_L1_CLKREQ_N PDD6"),
403 PINCTRL_PIN(TEGRA_PIN_CLK3_OUT_PEE0, "CLK3_OUT PEE0"),
404 PINCTRL_PIN(TEGRA_PIN_CLK3_REQ_PEE1, "CLK3_REQ PEE1"),
405 PINCTRL_PIN(TEGRA_PIN_DAP_MCLK1_REQ_PEE2, "DAP_MCLK1_REQ PEE2"),
406 PINCTRL_PIN(TEGRA_PIN_HDMI_CEC_PEE3, "HDMI_CEC PEE3"),
407 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4, "SDMMC3_CLK_LB_OUT PEE4"),
408 PINCTRL_PIN(TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5, "SDMMC3_CLK_LB_IN PEE5"),
409 PINCTRL_PIN(TEGRA_PIN_CORE_PWR_REQ, "CORE_PWR_REQ"),
410 PINCTRL_PIN(TEGRA_PIN_CPU_PWR_REQ, "CPU_PWR_REQ"),
411 PINCTRL_PIN(TEGRA_PIN_OWR, "OWR"),
412 PINCTRL_PIN(TEGRA_PIN_PWR_INT_N, "PWR_INT_N"),
413 PINCTRL_PIN(TEGRA_PIN_RESET_OUT_N, "RESET_OUT_N"),
414 PINCTRL_PIN(TEGRA_PIN_DP_HPD_PFF0, "DP_HPD PFF0"),
415 PINCTRL_PIN(TEGRA_PIN_USB_VBUS_EN2_PFF1, "USB_VBUS_EN2 PFF1"),
416 PINCTRL_PIN(TEGRA_PIN_PFF2, "PFF2"),
417 PINCTRL_PIN(TEGRA_PIN_CLK_32K_IN, "CLK_32K_IN"),
418 PINCTRL_PIN(TEGRA_PIN_GMI_CLK_LB, "GMI_CLK_LB"),
419 PINCTRL_PIN(TEGRA_PIN_JTAG_RTCK, "JTAG_RTCK"),
420};
421
422static const unsigned clk_32k_out_pa0_pins[] = {
423 TEGRA_PIN_CLK_32K_OUT_PA0,
424};
425
426static const unsigned uart3_cts_n_pa1_pins[] = {
427 TEGRA_PIN_UART3_CTS_N_PA1,
428};
429
430static const unsigned dap2_fs_pa2_pins[] = {
431 TEGRA_PIN_DAP2_FS_PA2,
432};
433
434static const unsigned dap2_sclk_pa3_pins[] = {
435 TEGRA_PIN_DAP2_SCLK_PA3,
436};
437
438static const unsigned dap2_din_pa4_pins[] = {
439 TEGRA_PIN_DAP2_DIN_PA4,
440};
441
442static const unsigned dap2_dout_pa5_pins[] = {
443 TEGRA_PIN_DAP2_DOUT_PA5,
444};
445
446static const unsigned sdmmc3_clk_pa6_pins[] = {
447 TEGRA_PIN_SDMMC3_CLK_PA6,
448};
449
450static const unsigned sdmmc3_cmd_pa7_pins[] = {
451 TEGRA_PIN_SDMMC3_CMD_PA7,
452};
453
454static const unsigned pb0_pins[] = {
455 TEGRA_PIN_PB0,
456};
457
458static const unsigned pb1_pins[] = {
459 TEGRA_PIN_PB1,
460};
461
462static const unsigned sdmmc3_dat3_pb4_pins[] = {
463 TEGRA_PIN_SDMMC3_DAT3_PB4,
464};
465
466static const unsigned sdmmc3_dat2_pb5_pins[] = {
467 TEGRA_PIN_SDMMC3_DAT2_PB5,
468};
469
470static const unsigned sdmmc3_dat1_pb6_pins[] = {
471 TEGRA_PIN_SDMMC3_DAT1_PB6,
472};
473
474static const unsigned sdmmc3_dat0_pb7_pins[] = {
475 TEGRA_PIN_SDMMC3_DAT0_PB7,
476};
477
478static const unsigned uart3_rts_n_pc0_pins[] = {
479 TEGRA_PIN_UART3_RTS_N_PC0,
480};
481
482static const unsigned uart2_txd_pc2_pins[] = {
483 TEGRA_PIN_UART2_TXD_PC2,
484};
485
486static const unsigned uart2_rxd_pc3_pins[] = {
487 TEGRA_PIN_UART2_RXD_PC3,
488};
489
490static const unsigned gen1_i2c_scl_pc4_pins[] = {
491 TEGRA_PIN_GEN1_I2C_SCL_PC4,
492};
493
494static const unsigned gen1_i2c_sda_pc5_pins[] = {
495 TEGRA_PIN_GEN1_I2C_SDA_PC5,
496};
497
498static const unsigned pc7_pins[] = {
499 TEGRA_PIN_PC7,
500};
501
502static const unsigned pg0_pins[] = {
503 TEGRA_PIN_PG0,
504};
505
506static const unsigned pg1_pins[] = {
507 TEGRA_PIN_PG1,
508};
509
510static const unsigned pg2_pins[] = {
511 TEGRA_PIN_PG2,
512};
513
514static const unsigned pg3_pins[] = {
515 TEGRA_PIN_PG3,
516};
517
518static const unsigned pg4_pins[] = {
519 TEGRA_PIN_PG4,
520};
521
522static const unsigned pg5_pins[] = {
523 TEGRA_PIN_PG5,
524};
525
526static const unsigned pg6_pins[] = {
527 TEGRA_PIN_PG6,
528};
529
530static const unsigned pg7_pins[] = {
531 TEGRA_PIN_PG7,
532};
533
534static const unsigned ph0_pins[] = {
535 TEGRA_PIN_PH0,
536};
537
538static const unsigned ph1_pins[] = {
539 TEGRA_PIN_PH1,
540};
541
542static const unsigned ph2_pins[] = {
543 TEGRA_PIN_PH2,
544};
545
546static const unsigned ph3_pins[] = {
547 TEGRA_PIN_PH3,
548};
549
550static const unsigned ph4_pins[] = {
551 TEGRA_PIN_PH4,
552};
553
554static const unsigned ph5_pins[] = {
555 TEGRA_PIN_PH5,
556};
557
558static const unsigned ph6_pins[] = {
559 TEGRA_PIN_PH6,
560};
561
562static const unsigned ph7_pins[] = {
563 TEGRA_PIN_PH7,
564};
565
566static const unsigned pi0_pins[] = {
567 TEGRA_PIN_PI0,
568};
569
570static const unsigned pi1_pins[] = {
571 TEGRA_PIN_PI1,
572};
573
574static const unsigned pi2_pins[] = {
575 TEGRA_PIN_PI2,
576};
577
578static const unsigned pi3_pins[] = {
579 TEGRA_PIN_PI3,
580};
581
582static const unsigned pi4_pins[] = {
583 TEGRA_PIN_PI4,
584};
585
586static const unsigned pi5_pins[] = {
587 TEGRA_PIN_PI5,
588};
589
590static const unsigned pi6_pins[] = {
591 TEGRA_PIN_PI6,
592};
593
594static const unsigned pi7_pins[] = {
595 TEGRA_PIN_PI7,
596};
597
598static const unsigned pj0_pins[] = {
599 TEGRA_PIN_PJ0,
600};
601
602static const unsigned pj2_pins[] = {
603 TEGRA_PIN_PJ2,
604};
605
606static const unsigned uart2_cts_n_pj5_pins[] = {
607 TEGRA_PIN_UART2_CTS_N_PJ5,
608};
609
610static const unsigned uart2_rts_n_pj6_pins[] = {
611 TEGRA_PIN_UART2_RTS_N_PJ6,
612};
613
614static const unsigned pj7_pins[] = {
615 TEGRA_PIN_PJ7,
616};
617
618static const unsigned pk0_pins[] = {
619 TEGRA_PIN_PK0,
620};
621
622static const unsigned pk1_pins[] = {
623 TEGRA_PIN_PK1,
624};
625
626static const unsigned pk2_pins[] = {
627 TEGRA_PIN_PK2,
628};
629
630static const unsigned pk3_pins[] = {
631 TEGRA_PIN_PK3,
632};
633
634static const unsigned pk4_pins[] = {
635 TEGRA_PIN_PK4,
636};
637
638static const unsigned spdif_out_pk5_pins[] = {
639 TEGRA_PIN_SPDIF_OUT_PK5,
640};
641
642static const unsigned spdif_in_pk6_pins[] = {
643 TEGRA_PIN_SPDIF_IN_PK6,
644};
645
646static const unsigned pk7_pins[] = {
647 TEGRA_PIN_PK7,
648};
649
650static const unsigned dap1_fs_pn0_pins[] = {
651 TEGRA_PIN_DAP1_FS_PN0,
652};
653
654static const unsigned dap1_din_pn1_pins[] = {
655 TEGRA_PIN_DAP1_DIN_PN1,
656};
657
658static const unsigned dap1_dout_pn2_pins[] = {
659 TEGRA_PIN_DAP1_DOUT_PN2,
660};
661
662static const unsigned dap1_sclk_pn3_pins[] = {
663 TEGRA_PIN_DAP1_SCLK_PN3,
664};
665
666static const unsigned usb_vbus_en0_pn4_pins[] = {
667 TEGRA_PIN_USB_VBUS_EN0_PN4,
668};
669
670static const unsigned usb_vbus_en1_pn5_pins[] = {
671 TEGRA_PIN_USB_VBUS_EN1_PN5,
672};
673
674static const unsigned hdmi_int_pn7_pins[] = {
675 TEGRA_PIN_HDMI_INT_PN7,
676};
677
678static const unsigned ulpi_data7_po0_pins[] = {
679 TEGRA_PIN_ULPI_DATA7_PO0,
680};
681
682static const unsigned ulpi_data0_po1_pins[] = {
683 TEGRA_PIN_ULPI_DATA0_PO1,
684};
685
686static const unsigned ulpi_data1_po2_pins[] = {
687 TEGRA_PIN_ULPI_DATA1_PO2,
688};
689
690static const unsigned ulpi_data2_po3_pins[] = {
691 TEGRA_PIN_ULPI_DATA2_PO3,
692};
693
694static const unsigned ulpi_data3_po4_pins[] = {
695 TEGRA_PIN_ULPI_DATA3_PO4,
696};
697
698static const unsigned ulpi_data4_po5_pins[] = {
699 TEGRA_PIN_ULPI_DATA4_PO5,
700};
701
702static const unsigned ulpi_data5_po6_pins[] = {
703 TEGRA_PIN_ULPI_DATA5_PO6,
704};
705
706static const unsigned ulpi_data6_po7_pins[] = {
707 TEGRA_PIN_ULPI_DATA6_PO7,
708};
709
710static const unsigned dap3_fs_pp0_pins[] = {
711 TEGRA_PIN_DAP3_FS_PP0,
712};
713
714static const unsigned dap3_din_pp1_pins[] = {
715 TEGRA_PIN_DAP3_DIN_PP1,
716};
717
718static const unsigned dap3_dout_pp2_pins[] = {
719 TEGRA_PIN_DAP3_DOUT_PP2,
720};
721
722static const unsigned dap3_sclk_pp3_pins[] = {
723 TEGRA_PIN_DAP3_SCLK_PP3,
724};
725
726static const unsigned dap4_fs_pp4_pins[] = {
727 TEGRA_PIN_DAP4_FS_PP4,
728};
729
730static const unsigned dap4_din_pp5_pins[] = {
731 TEGRA_PIN_DAP4_DIN_PP5,
732};
733
734static const unsigned dap4_dout_pp6_pins[] = {
735 TEGRA_PIN_DAP4_DOUT_PP6,
736};
737
738static const unsigned dap4_sclk_pp7_pins[] = {
739 TEGRA_PIN_DAP4_SCLK_PP7,
740};
741
742static const unsigned kb_col0_pq0_pins[] = {
743 TEGRA_PIN_KB_COL0_PQ0,
744};
745
746static const unsigned kb_col1_pq1_pins[] = {
747 TEGRA_PIN_KB_COL1_PQ1,
748};
749
750static const unsigned kb_col2_pq2_pins[] = {
751 TEGRA_PIN_KB_COL2_PQ2,
752};
753
754static const unsigned kb_col3_pq3_pins[] = {
755 TEGRA_PIN_KB_COL3_PQ3,
756};
757
758static const unsigned kb_col4_pq4_pins[] = {
759 TEGRA_PIN_KB_COL4_PQ4,
760};
761
762static const unsigned kb_col5_pq5_pins[] = {
763 TEGRA_PIN_KB_COL5_PQ5,
764};
765
766static const unsigned kb_col6_pq6_pins[] = {
767 TEGRA_PIN_KB_COL6_PQ6,
768};
769
770static const unsigned kb_col7_pq7_pins[] = {
771 TEGRA_PIN_KB_COL7_PQ7,
772};
773
774static const unsigned kb_row0_pr0_pins[] = {
775 TEGRA_PIN_KB_ROW0_PR0,
776};
777
778static const unsigned kb_row1_pr1_pins[] = {
779 TEGRA_PIN_KB_ROW1_PR1,
780};
781
782static const unsigned kb_row2_pr2_pins[] = {
783 TEGRA_PIN_KB_ROW2_PR2,
784};
785
786static const unsigned kb_row3_pr3_pins[] = {
787 TEGRA_PIN_KB_ROW3_PR3,
788};
789
790static const unsigned kb_row4_pr4_pins[] = {
791 TEGRA_PIN_KB_ROW4_PR4,
792};
793
794static const unsigned kb_row5_pr5_pins[] = {
795 TEGRA_PIN_KB_ROW5_PR5,
796};
797
798static const unsigned kb_row6_pr6_pins[] = {
799 TEGRA_PIN_KB_ROW6_PR6,
800};
801
802static const unsigned kb_row7_pr7_pins[] = {
803 TEGRA_PIN_KB_ROW7_PR7,
804};
805
806static const unsigned kb_row8_ps0_pins[] = {
807 TEGRA_PIN_KB_ROW8_PS0,
808};
809
810static const unsigned kb_row9_ps1_pins[] = {
811 TEGRA_PIN_KB_ROW9_PS1,
812};
813
814static const unsigned kb_row10_ps2_pins[] = {
815 TEGRA_PIN_KB_ROW10_PS2,
816};
817
818static const unsigned kb_row11_ps3_pins[] = {
819 TEGRA_PIN_KB_ROW11_PS3,
820};
821
822static const unsigned kb_row12_ps4_pins[] = {
823 TEGRA_PIN_KB_ROW12_PS4,
824};
825
826static const unsigned kb_row13_ps5_pins[] = {
827 TEGRA_PIN_KB_ROW13_PS5,
828};
829
830static const unsigned kb_row14_ps6_pins[] = {
831 TEGRA_PIN_KB_ROW14_PS6,
832};
833
834static const unsigned kb_row15_ps7_pins[] = {
835 TEGRA_PIN_KB_ROW15_PS7,
836};
837
838static const unsigned kb_row16_pt0_pins[] = {
839 TEGRA_PIN_KB_ROW16_PT0,
840};
841
842static const unsigned kb_row17_pt1_pins[] = {
843 TEGRA_PIN_KB_ROW17_PT1,
844};
845
846static const unsigned gen2_i2c_scl_pt5_pins[] = {
847 TEGRA_PIN_GEN2_I2C_SCL_PT5,
848};
849
850static const unsigned gen2_i2c_sda_pt6_pins[] = {
851 TEGRA_PIN_GEN2_I2C_SDA_PT6,
852};
853
854static const unsigned sdmmc4_cmd_pt7_pins[] = {
855 TEGRA_PIN_SDMMC4_CMD_PT7,
856};
857
858static const unsigned pu0_pins[] = {
859 TEGRA_PIN_PU0,
860};
861
862static const unsigned pu1_pins[] = {
863 TEGRA_PIN_PU1,
864};
865
866static const unsigned pu2_pins[] = {
867 TEGRA_PIN_PU2,
868};
869
870static const unsigned pu3_pins[] = {
871 TEGRA_PIN_PU3,
872};
873
874static const unsigned pu4_pins[] = {
875 TEGRA_PIN_PU4,
876};
877
878static const unsigned pu5_pins[] = {
879 TEGRA_PIN_PU5,
880};
881
882static const unsigned pu6_pins[] = {
883 TEGRA_PIN_PU6,
884};
885
886static const unsigned pv0_pins[] = {
887 TEGRA_PIN_PV0,
888};
889
890static const unsigned pv1_pins[] = {
891 TEGRA_PIN_PV1,
892};
893
894static const unsigned sdmmc3_cd_n_pv2_pins[] = {
895 TEGRA_PIN_SDMMC3_CD_N_PV2,
896};
897
898static const unsigned sdmmc1_wp_n_pv3_pins[] = {
899 TEGRA_PIN_SDMMC1_WP_N_PV3,
900};
901
902static const unsigned ddc_scl_pv4_pins[] = {
903 TEGRA_PIN_DDC_SCL_PV4,
904};
905
906static const unsigned ddc_sda_pv5_pins[] = {
907 TEGRA_PIN_DDC_SDA_PV5,
908};
909
910static const unsigned gpio_w2_aud_pw2_pins[] = {
911 TEGRA_PIN_GPIO_W2_AUD_PW2,
912};
913
914static const unsigned gpio_w3_aud_pw3_pins[] = {
915 TEGRA_PIN_GPIO_W3_AUD_PW3,
916};
917
918static const unsigned dap_mclk1_pw4_pins[] = {
919 TEGRA_PIN_DAP_MCLK1_PW4,
920};
921
922static const unsigned clk2_out_pw5_pins[] = {
923 TEGRA_PIN_CLK2_OUT_PW5,
924};
925
926static const unsigned uart3_txd_pw6_pins[] = {
927 TEGRA_PIN_UART3_TXD_PW6,
928};
929
930static const unsigned uart3_rxd_pw7_pins[] = {
931 TEGRA_PIN_UART3_RXD_PW7,
932};
933
934static const unsigned dvfs_pwm_px0_pins[] = {
935 TEGRA_PIN_DVFS_PWM_PX0,
936};
937
938static const unsigned gpio_x1_aud_px1_pins[] = {
939 TEGRA_PIN_GPIO_X1_AUD_PX1,
940};
941
942static const unsigned dvfs_clk_px2_pins[] = {
943 TEGRA_PIN_DVFS_CLK_PX2,
944};
945
946static const unsigned gpio_x3_aud_px3_pins[] = {
947 TEGRA_PIN_GPIO_X3_AUD_PX3,
948};
949
950static const unsigned gpio_x4_aud_px4_pins[] = {
951 TEGRA_PIN_GPIO_X4_AUD_PX4,
952};
953
954static const unsigned gpio_x5_aud_px5_pins[] = {
955 TEGRA_PIN_GPIO_X5_AUD_PX5,
956};
957
958static const unsigned gpio_x6_aud_px6_pins[] = {
959 TEGRA_PIN_GPIO_X6_AUD_PX6,
960};
961
962static const unsigned gpio_x7_aud_px7_pins[] = {
963 TEGRA_PIN_GPIO_X7_AUD_PX7,
964};
965
966static const unsigned ulpi_clk_py0_pins[] = {
967 TEGRA_PIN_ULPI_CLK_PY0,
968};
969
970static const unsigned ulpi_dir_py1_pins[] = {
971 TEGRA_PIN_ULPI_DIR_PY1,
972};
973
974static const unsigned ulpi_nxt_py2_pins[] = {
975 TEGRA_PIN_ULPI_NXT_PY2,
976};
977
978static const unsigned ulpi_stp_py3_pins[] = {
979 TEGRA_PIN_ULPI_STP_PY3,
980};
981
982static const unsigned sdmmc1_dat3_py4_pins[] = {
983 TEGRA_PIN_SDMMC1_DAT3_PY4,
984};
985
986static const unsigned sdmmc1_dat2_py5_pins[] = {
987 TEGRA_PIN_SDMMC1_DAT2_PY5,
988};
989
990static const unsigned sdmmc1_dat1_py6_pins[] = {
991 TEGRA_PIN_SDMMC1_DAT1_PY6,
992};
993
994static const unsigned sdmmc1_dat0_py7_pins[] = {
995 TEGRA_PIN_SDMMC1_DAT0_PY7,
996};
997
998static const unsigned sdmmc1_clk_pz0_pins[] = {
999 TEGRA_PIN_SDMMC1_CLK_PZ0,
1000};
1001
1002static const unsigned sdmmc1_cmd_pz1_pins[] = {
1003 TEGRA_PIN_SDMMC1_CMD_PZ1,
1004};
1005
1006static const unsigned pwr_i2c_scl_pz6_pins[] = {
1007 TEGRA_PIN_PWR_I2C_SCL_PZ6,
1008};
1009
1010static const unsigned pwr_i2c_sda_pz7_pins[] = {
1011 TEGRA_PIN_PWR_I2C_SDA_PZ7,
1012};
1013
1014static const unsigned sdmmc4_dat0_paa0_pins[] = {
1015 TEGRA_PIN_SDMMC4_DAT0_PAA0,
1016};
1017
1018static const unsigned sdmmc4_dat1_paa1_pins[] = {
1019 TEGRA_PIN_SDMMC4_DAT1_PAA1,
1020};
1021
1022static const unsigned sdmmc4_dat2_paa2_pins[] = {
1023 TEGRA_PIN_SDMMC4_DAT2_PAA2,
1024};
1025
1026static const unsigned sdmmc4_dat3_paa3_pins[] = {
1027 TEGRA_PIN_SDMMC4_DAT3_PAA3,
1028};
1029
1030static const unsigned sdmmc4_dat4_paa4_pins[] = {
1031 TEGRA_PIN_SDMMC4_DAT4_PAA4,
1032};
1033
1034static const unsigned sdmmc4_dat5_paa5_pins[] = {
1035 TEGRA_PIN_SDMMC4_DAT5_PAA5,
1036};
1037
1038static const unsigned sdmmc4_dat6_paa6_pins[] = {
1039 TEGRA_PIN_SDMMC4_DAT6_PAA6,
1040};
1041
1042static const unsigned sdmmc4_dat7_paa7_pins[] = {
1043 TEGRA_PIN_SDMMC4_DAT7_PAA7,
1044};
1045
1046static const unsigned pbb0_pins[] = {
1047 TEGRA_PIN_PBB0,
1048};
1049
1050static const unsigned cam_i2c_scl_pbb1_pins[] = {
1051 TEGRA_PIN_CAM_I2C_SCL_PBB1,
1052};
1053
1054static const unsigned cam_i2c_sda_pbb2_pins[] = {
1055 TEGRA_PIN_CAM_I2C_SDA_PBB2,
1056};
1057
1058static const unsigned pbb3_pins[] = {
1059 TEGRA_PIN_PBB3,
1060};
1061
1062static const unsigned pbb4_pins[] = {
1063 TEGRA_PIN_PBB4,
1064};
1065
1066static const unsigned pbb5_pins[] = {
1067 TEGRA_PIN_PBB5,
1068};
1069
1070static const unsigned pbb6_pins[] = {
1071 TEGRA_PIN_PBB6,
1072};
1073
1074static const unsigned pbb7_pins[] = {
1075 TEGRA_PIN_PBB7,
1076};
1077
1078static const unsigned cam_mclk_pcc0_pins[] = {
1079 TEGRA_PIN_CAM_MCLK_PCC0,
1080};
1081
1082static const unsigned pcc1_pins[] = {
1083 TEGRA_PIN_PCC1,
1084};
1085
1086static const unsigned pcc2_pins[] = {
1087 TEGRA_PIN_PCC2,
1088};
1089
1090static const unsigned sdmmc4_clk_pcc4_pins[] = {
1091 TEGRA_PIN_SDMMC4_CLK_PCC4,
1092};
1093
1094static const unsigned clk2_req_pcc5_pins[] = {
1095 TEGRA_PIN_CLK2_REQ_PCC5,
1096};
1097
1098static const unsigned pex_l0_rst_n_pdd1_pins[] = {
1099 TEGRA_PIN_PEX_L0_RST_N_PDD1,
1100};
1101
1102static const unsigned pex_l0_clkreq_n_pdd2_pins[] = {
1103 TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1104};
1105
1106static const unsigned pex_wake_n_pdd3_pins[] = {
1107 TEGRA_PIN_PEX_WAKE_N_PDD3,
1108};
1109
1110static const unsigned pex_l1_rst_n_pdd5_pins[] = {
1111 TEGRA_PIN_PEX_L1_RST_N_PDD5,
1112};
1113
1114static const unsigned pex_l1_clkreq_n_pdd6_pins[] = {
1115 TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1116};
1117
1118static const unsigned clk3_out_pee0_pins[] = {
1119 TEGRA_PIN_CLK3_OUT_PEE0,
1120};
1121
1122static const unsigned clk3_req_pee1_pins[] = {
1123 TEGRA_PIN_CLK3_REQ_PEE1,
1124};
1125
1126static const unsigned dap_mclk1_req_pee2_pins[] = {
1127 TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1128};
1129
1130static const unsigned hdmi_cec_pee3_pins[] = {
1131 TEGRA_PIN_HDMI_CEC_PEE3,
1132};
1133
1134static const unsigned sdmmc3_clk_lb_out_pee4_pins[] = {
1135 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1136};
1137
1138static const unsigned sdmmc3_clk_lb_in_pee5_pins[] = {
1139 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1140};
1141static const unsigned dp_hpd_pff0_pins[] = {
1142 TEGRA_PIN_DP_HPD_PFF0,
1143};
1144
1145static const unsigned usb_vbus_en2_pff1_pins[] = {
1146 TEGRA_PIN_USB_VBUS_EN2_PFF1,
1147};
1148
1149static const unsigned pff2_pins[] = {
1150 TEGRA_PIN_PFF2,
1151};
1152
1153static const unsigned core_pwr_req_pins[] = {
1154 TEGRA_PIN_CORE_PWR_REQ,
1155};
1156
1157static const unsigned cpu_pwr_req_pins[] = {
1158 TEGRA_PIN_CPU_PWR_REQ,
1159};
1160
1161static const unsigned owr_pins[] = {
1162 TEGRA_PIN_OWR,
1163};
1164
1165static const unsigned pwr_int_n_pins[] = {
1166 TEGRA_PIN_PWR_INT_N,
1167};
1168
1169static const unsigned reset_out_n_pins[] = {
1170 TEGRA_PIN_RESET_OUT_N,
1171};
1172
1173static const unsigned clk_32k_in_pins[] = {
1174 TEGRA_PIN_CLK_32K_IN,
1175};
1176
1177static const unsigned gmi_clk_lb_pins[] = {
1178 TEGRA_PIN_GMI_CLK_LB,
1179};
1180
1181static const unsigned jtag_rtck_pins[] = {
1182 TEGRA_PIN_JTAG_RTCK,
1183};
1184
1185static const unsigned drive_ao1_pins[] = {
1186 TEGRA_PIN_KB_ROW0_PR0,
1187 TEGRA_PIN_KB_ROW1_PR1,
1188 TEGRA_PIN_KB_ROW2_PR2,
1189 TEGRA_PIN_KB_ROW3_PR3,
1190 TEGRA_PIN_KB_ROW4_PR4,
1191 TEGRA_PIN_KB_ROW5_PR5,
1192 TEGRA_PIN_KB_ROW6_PR6,
1193 TEGRA_PIN_KB_ROW7_PR7,
1194 TEGRA_PIN_PWR_I2C_SCL_PZ6,
1195 TEGRA_PIN_PWR_I2C_SDA_PZ7,
1196};
1197
1198static const unsigned drive_ao2_pins[] = {
1199 TEGRA_PIN_CLK_32K_OUT_PA0,
1200 TEGRA_PIN_CLK_32K_IN,
1201 TEGRA_PIN_KB_COL0_PQ0,
1202 TEGRA_PIN_KB_COL1_PQ1,
1203 TEGRA_PIN_KB_COL2_PQ2,
1204 TEGRA_PIN_KB_COL3_PQ3,
1205 TEGRA_PIN_KB_COL4_PQ4,
1206 TEGRA_PIN_KB_COL5_PQ5,
1207 TEGRA_PIN_KB_COL6_PQ6,
1208 TEGRA_PIN_KB_COL7_PQ7,
1209 TEGRA_PIN_KB_ROW8_PS0,
1210 TEGRA_PIN_KB_ROW9_PS1,
1211 TEGRA_PIN_KB_ROW10_PS2,
1212 TEGRA_PIN_KB_ROW11_PS3,
1213 TEGRA_PIN_KB_ROW12_PS4,
1214 TEGRA_PIN_KB_ROW13_PS5,
1215 TEGRA_PIN_KB_ROW14_PS6,
1216 TEGRA_PIN_KB_ROW15_PS7,
1217 TEGRA_PIN_KB_ROW16_PT0,
1218 TEGRA_PIN_KB_ROW17_PT1,
1219 TEGRA_PIN_SDMMC3_CD_N_PV2,
1220 TEGRA_PIN_CORE_PWR_REQ,
1221 TEGRA_PIN_CPU_PWR_REQ,
1222 TEGRA_PIN_PWR_INT_N,
1223};
1224
1225static const unsigned drive_at1_pins[] = {
1226 TEGRA_PIN_PH0,
1227 TEGRA_PIN_PH1,
1228 TEGRA_PIN_PH2,
1229 TEGRA_PIN_PH3,
1230};
1231
1232static const unsigned drive_at2_pins[] = {
1233 TEGRA_PIN_PG0,
1234 TEGRA_PIN_PG1,
1235 TEGRA_PIN_PG2,
1236 TEGRA_PIN_PG3,
1237 TEGRA_PIN_PG4,
1238 TEGRA_PIN_PG5,
1239 TEGRA_PIN_PG6,
1240 TEGRA_PIN_PG7,
1241 TEGRA_PIN_PI0,
1242 TEGRA_PIN_PI1,
1243 TEGRA_PIN_PI3,
1244 TEGRA_PIN_PI4,
1245 TEGRA_PIN_PI7,
1246 TEGRA_PIN_PK0,
1247 TEGRA_PIN_PK2,
1248};
1249
1250static const unsigned drive_at3_pins[] = {
1251 TEGRA_PIN_PC7,
1252 TEGRA_PIN_PJ0,
1253};
1254
1255static const unsigned drive_at4_pins[] = {
1256 TEGRA_PIN_PB0,
1257 TEGRA_PIN_PB1,
1258 TEGRA_PIN_PJ0,
1259 TEGRA_PIN_PJ7,
1260 TEGRA_PIN_PK7,
1261};
1262
1263static const unsigned drive_at5_pins[] = {
1264 TEGRA_PIN_GEN2_I2C_SCL_PT5,
1265 TEGRA_PIN_GEN2_I2C_SDA_PT6,
1266};
1267
1268static const unsigned drive_cdev1_pins[] = {
1269 TEGRA_PIN_DAP_MCLK1_PW4,
1270 TEGRA_PIN_DAP_MCLK1_REQ_PEE2,
1271};
1272
1273static const unsigned drive_cdev2_pins[] = {
1274 TEGRA_PIN_CLK2_OUT_PW5,
1275 TEGRA_PIN_CLK2_REQ_PCC5,
1276};
1277
1278static const unsigned drive_dap1_pins[] = {
1279 TEGRA_PIN_DAP1_FS_PN0,
1280 TEGRA_PIN_DAP1_DIN_PN1,
1281 TEGRA_PIN_DAP1_DOUT_PN2,
1282 TEGRA_PIN_DAP1_SCLK_PN3,
1283};
1284
1285static const unsigned drive_dap2_pins[] = {
1286 TEGRA_PIN_DAP2_FS_PA2,
1287 TEGRA_PIN_DAP2_SCLK_PA3,
1288 TEGRA_PIN_DAP2_DIN_PA4,
1289 TEGRA_PIN_DAP2_DOUT_PA5,
1290};
1291
1292static const unsigned drive_dap3_pins[] = {
1293 TEGRA_PIN_DAP3_FS_PP0,
1294 TEGRA_PIN_DAP3_DIN_PP1,
1295 TEGRA_PIN_DAP3_DOUT_PP2,
1296 TEGRA_PIN_DAP3_SCLK_PP3,
1297};
1298
1299static const unsigned drive_dap4_pins[] = {
1300 TEGRA_PIN_DAP4_FS_PP4,
1301 TEGRA_PIN_DAP4_DIN_PP5,
1302 TEGRA_PIN_DAP4_DOUT_PP6,
1303 TEGRA_PIN_DAP4_SCLK_PP7,
1304};
1305
1306static const unsigned drive_dbg_pins[] = {
1307 TEGRA_PIN_GEN1_I2C_SCL_PC4,
1308 TEGRA_PIN_GEN1_I2C_SDA_PC5,
1309 TEGRA_PIN_PU0,
1310 TEGRA_PIN_PU1,
1311 TEGRA_PIN_PU2,
1312 TEGRA_PIN_PU3,
1313 TEGRA_PIN_PU4,
1314 TEGRA_PIN_PU5,
1315 TEGRA_PIN_PU6,
1316};
1317
1318static const unsigned drive_sdio3_pins[] = {
1319 TEGRA_PIN_SDMMC3_CLK_PA6,
1320 TEGRA_PIN_SDMMC3_CMD_PA7,
1321 TEGRA_PIN_SDMMC3_DAT3_PB4,
1322 TEGRA_PIN_SDMMC3_DAT2_PB5,
1323 TEGRA_PIN_SDMMC3_DAT1_PB6,
1324 TEGRA_PIN_SDMMC3_DAT0_PB7,
1325 TEGRA_PIN_SDMMC3_CLK_LB_OUT_PEE4,
1326 TEGRA_PIN_SDMMC3_CLK_LB_IN_PEE5,
1327};
1328
1329static const unsigned drive_spi_pins[] = {
1330 TEGRA_PIN_DVFS_PWM_PX0,
1331 TEGRA_PIN_GPIO_X1_AUD_PX1,
1332 TEGRA_PIN_DVFS_CLK_PX2,
1333 TEGRA_PIN_GPIO_X3_AUD_PX3,
1334 TEGRA_PIN_GPIO_X4_AUD_PX4,
1335 TEGRA_PIN_GPIO_X5_AUD_PX5,
1336 TEGRA_PIN_GPIO_X6_AUD_PX6,
1337 TEGRA_PIN_GPIO_X7_AUD_PX7,
1338 TEGRA_PIN_GPIO_W2_AUD_PW2,
1339 TEGRA_PIN_GPIO_W3_AUD_PW3,
1340};
1341
1342static const unsigned drive_uaa_pins[] = {
1343 TEGRA_PIN_ULPI_DATA0_PO1,
1344 TEGRA_PIN_ULPI_DATA1_PO2,
1345 TEGRA_PIN_ULPI_DATA2_PO3,
1346 TEGRA_PIN_ULPI_DATA3_PO4,
1347};
1348
1349static const unsigned drive_uab_pins[] = {
1350 TEGRA_PIN_ULPI_DATA7_PO0,
1351 TEGRA_PIN_ULPI_DATA4_PO5,
1352 TEGRA_PIN_ULPI_DATA5_PO6,
1353 TEGRA_PIN_ULPI_DATA6_PO7,
1354 TEGRA_PIN_PV0,
1355 TEGRA_PIN_PV1,
1356};
1357
1358static const unsigned drive_uart2_pins[] = {
1359 TEGRA_PIN_UART2_TXD_PC2,
1360 TEGRA_PIN_UART2_RXD_PC3,
1361 TEGRA_PIN_UART2_CTS_N_PJ5,
1362 TEGRA_PIN_UART2_RTS_N_PJ6,
1363};
1364
1365static const unsigned drive_uart3_pins[] = {
1366 TEGRA_PIN_UART3_CTS_N_PA1,
1367 TEGRA_PIN_UART3_RTS_N_PC0,
1368 TEGRA_PIN_UART3_TXD_PW6,
1369 TEGRA_PIN_UART3_RXD_PW7,
1370};
1371
1372static const unsigned drive_sdio1_pins[] = {
1373 TEGRA_PIN_SDMMC1_DAT3_PY4,
1374 TEGRA_PIN_SDMMC1_DAT2_PY5,
1375 TEGRA_PIN_SDMMC1_DAT1_PY6,
1376 TEGRA_PIN_SDMMC1_DAT0_PY7,
1377 TEGRA_PIN_SDMMC1_CLK_PZ0,
1378 TEGRA_PIN_SDMMC1_CMD_PZ1,
1379};
1380
1381static const unsigned drive_ddc_pins[] = {
1382 TEGRA_PIN_DDC_SCL_PV4,
1383 TEGRA_PIN_DDC_SDA_PV5,
1384};
1385
1386static const unsigned drive_gma_pins[] = {
1387 TEGRA_PIN_SDMMC4_CLK_PCC4,
1388 TEGRA_PIN_SDMMC4_CMD_PT7,
1389 TEGRA_PIN_SDMMC4_DAT0_PAA0,
1390 TEGRA_PIN_SDMMC4_DAT1_PAA1,
1391 TEGRA_PIN_SDMMC4_DAT2_PAA2,
1392 TEGRA_PIN_SDMMC4_DAT3_PAA3,
1393 TEGRA_PIN_SDMMC4_DAT4_PAA4,
1394 TEGRA_PIN_SDMMC4_DAT5_PAA5,
1395 TEGRA_PIN_SDMMC4_DAT6_PAA6,
1396 TEGRA_PIN_SDMMC4_DAT7_PAA7,
1397};
1398
1399static const unsigned drive_gme_pins[] = {
1400 TEGRA_PIN_PBB0,
1401 TEGRA_PIN_CAM_I2C_SCL_PBB1,
1402 TEGRA_PIN_CAM_I2C_SDA_PBB2,
1403 TEGRA_PIN_PBB3,
1404 TEGRA_PIN_PCC2,
1405};
1406
1407static const unsigned drive_gmf_pins[] = {
1408 TEGRA_PIN_PBB4,
1409 TEGRA_PIN_PBB5,
1410 TEGRA_PIN_PBB6,
1411 TEGRA_PIN_PBB7,
1412};
1413
1414static const unsigned drive_gmg_pins[] = {
1415 TEGRA_PIN_CAM_MCLK_PCC0,
1416};
1417
1418static const unsigned drive_gmh_pins[] = {
1419 TEGRA_PIN_PCC1,
1420};
1421
1422static const unsigned drive_owr_pins[] = {
1423 TEGRA_PIN_SDMMC3_CD_N_PV2,
1424 TEGRA_PIN_OWR,
1425};
1426
1427static const unsigned drive_uda_pins[] = {
1428 TEGRA_PIN_ULPI_CLK_PY0,
1429 TEGRA_PIN_ULPI_DIR_PY1,
1430 TEGRA_PIN_ULPI_NXT_PY2,
1431 TEGRA_PIN_ULPI_STP_PY3,
1432};
1433
1434static const unsigned drive_gpv_pins[] = {
1435 TEGRA_PIN_PEX_L0_RST_N_PDD1,
1436 TEGRA_PIN_PEX_L0_CLKREQ_N_PDD2,
1437 TEGRA_PIN_PEX_WAKE_N_PDD3,
1438 TEGRA_PIN_PEX_L1_RST_N_PDD5,
1439 TEGRA_PIN_PEX_L1_CLKREQ_N_PDD6,
1440 TEGRA_PIN_USB_VBUS_EN2_PFF1,
1441 TEGRA_PIN_PFF2,
1442};
1443
1444static const unsigned drive_cec_pins[] = {
1445 TEGRA_PIN_HDMI_CEC_PEE3,
1446};
1447
1448static const unsigned drive_dev3_pins[] = {
1449 TEGRA_PIN_CLK3_OUT_PEE0,
1450 TEGRA_PIN_CLK3_REQ_PEE1,
1451};
1452
1453static const unsigned drive_at6_pins[] = {
1454 TEGRA_PIN_PK1,
1455 TEGRA_PIN_PK3,
1456 TEGRA_PIN_PK4,
1457 TEGRA_PIN_PI2,
1458 TEGRA_PIN_PI5,
1459 TEGRA_PIN_PI6,
1460 TEGRA_PIN_PH4,
1461 TEGRA_PIN_PH5,
1462 TEGRA_PIN_PH6,
1463 TEGRA_PIN_PH7,
1464};
1465
1466static const unsigned drive_dap5_pins[] = {
1467 TEGRA_PIN_SPDIF_IN_PK6,
1468 TEGRA_PIN_SPDIF_OUT_PK5,
1469 TEGRA_PIN_DP_HPD_PFF0,
1470};
1471
1472static const unsigned drive_usb_vbus_en_pins[] = {
1473 TEGRA_PIN_USB_VBUS_EN0_PN4,
1474 TEGRA_PIN_USB_VBUS_EN1_PN5,
1475};
1476
1477static const unsigned drive_ao3_pins[] = {
1478 TEGRA_PIN_RESET_OUT_N,
1479};
1480
1481static const unsigned drive_ao0_pins[] = {
1482 TEGRA_PIN_JTAG_RTCK,
1483};
1484
1485static const unsigned drive_hv0_pins[] = {
1486 TEGRA_PIN_HDMI_INT_PN7,
1487};
1488
1489static const unsigned drive_sdio4_pins[] = {
1490 TEGRA_PIN_SDMMC1_WP_N_PV3,
1491};
1492
1493static const unsigned drive_ao4_pins[] = {
1494 TEGRA_PIN_JTAG_RTCK,
1495};
1496
1497enum tegra_mux {
1498 TEGRA_MUX_BLINK,
1499 TEGRA_MUX_CEC,
1500 TEGRA_MUX_CLDVFS,
1501 TEGRA_MUX_CLK12,
1502 TEGRA_MUX_CPU,
1503 TEGRA_MUX_DAP,
1504 TEGRA_MUX_DAP1,
1505 TEGRA_MUX_DAP2,
1506 TEGRA_MUX_DEV3,
1507 TEGRA_MUX_DISPLAYA,
1508 TEGRA_MUX_DISPLAYA_ALT,
1509 TEGRA_MUX_DISPLAYB,
1510 TEGRA_MUX_DTV,
1511 TEGRA_MUX_EXTPERIPH1,
1512 TEGRA_MUX_EXTPERIPH2,
1513 TEGRA_MUX_EXTPERIPH3,
1514 TEGRA_MUX_GMI,
1515 TEGRA_MUX_GMI_ALT,
1516 TEGRA_MUX_HDA,
1517 TEGRA_MUX_HSI,
1518 TEGRA_MUX_I2C1,
1519 TEGRA_MUX_I2C2,
1520 TEGRA_MUX_I2C3,
1521 TEGRA_MUX_I2C4,
1522 TEGRA_MUX_I2CPWR,
1523 TEGRA_MUX_I2S0,
1524 TEGRA_MUX_I2S1,
1525 TEGRA_MUX_I2S2,
1526 TEGRA_MUX_I2S3,
1527 TEGRA_MUX_I2S4,
1528 TEGRA_MUX_IRDA,
1529 TEGRA_MUX_KBC,
1530 TEGRA_MUX_OWR,
1531 TEGRA_MUX_PMI,
1532 TEGRA_MUX_PWM0,
1533 TEGRA_MUX_PWM1,
1534 TEGRA_MUX_PWM2,
1535 TEGRA_MUX_PWM3,
1536 TEGRA_MUX_PWRON,
1537 TEGRA_MUX_RESET_OUT_N,
1538 TEGRA_MUX_RSVD1,
1539 TEGRA_MUX_RSVD2,
1540 TEGRA_MUX_RSVD3,
1541 TEGRA_MUX_RSVD4,
1542 TEGRA_MUX_SDMMC1,
1543 TEGRA_MUX_SDMMC2,
1544 TEGRA_MUX_SDMMC3,
1545 TEGRA_MUX_SDMMC4,
1546 TEGRA_MUX_SOC,
1547 TEGRA_MUX_SPDIF,
1548 TEGRA_MUX_SPI1,
1549 TEGRA_MUX_SPI2,
1550 TEGRA_MUX_SPI3,
1551 TEGRA_MUX_SPI4,
1552 TEGRA_MUX_SPI5,
1553 TEGRA_MUX_SPI6,
1554 TEGRA_MUX_TRACE,
1555 TEGRA_MUX_UARTA,
1556 TEGRA_MUX_UARTB,
1557 TEGRA_MUX_UARTC,
1558 TEGRA_MUX_UARTD,
1559 TEGRA_MUX_ULPI,
1560 TEGRA_MUX_USB,
1561 TEGRA_MUX_VGP1,
1562 TEGRA_MUX_VGP2,
1563 TEGRA_MUX_VGP3,
1564 TEGRA_MUX_VGP4,
1565 TEGRA_MUX_VGP5,
1566 TEGRA_MUX_VGP6,
1567 TEGRA_MUX_VI,
1568 TEGRA_MUX_VI_ALT1,
1569 TEGRA_MUX_VI_ALT3,
1570 TEGRA_MUX_VIMCLK2,
1571 TEGRA_MUX_VIMCLK2_ALT,
1572 TEGRA_MUX_SATA,
1573 TEGRA_MUX_CCLA,
1574 TEGRA_MUX_PE0,
1575 TEGRA_MUX_PE,
1576 TEGRA_MUX_PE1,
1577 TEGRA_MUX_DP,
1578 TEGRA_MUX_RTCK,
1579 TEGRA_MUX_SYS,
1580 TEGRA_MUX_CLK,
1581 TEGRA_MUX_TMDS,
1582};
1583
1584static const char * const blink_groups[] = {
1585 "clk_32k_out_pa0",
1586};
1587
1588static const char * const cec_groups[] = {
1589 "hdmi_cec_pee3",
1590};
1591
1592static const char * const cldvfs_groups[] = {
1593 "ph2",
1594 "ph3",
1595 "kb_row7_pr7",
1596 "kb_row8_ps0",
1597 "dvfs_pwm_px0",
1598 "dvfs_clk_px2",
1599};
1600
1601static const char * const clk12_groups[] = {
1602 "sdmmc1_wp_n_pv3",
1603 "sdmmc1_clk_pz0",
1604};
1605
1606static const char * const cpu_groups[] = {
1607 "cpu_pwr_req",
1608};
1609
1610static const char * const dap_groups[] = {
1611 "dap_mclk1_pee2",
1612 "clk2_req_pcc5",
1613};
1614
1615static const char * const dap1_groups[] = {
1616 "dap_mclk1_pee2",
1617};
1618
1619static const char * const dap2_groups[] = {
1620 "dap_mclk1_pw4",
1621 "gpio_x4_aud_px4",
1622};
1623
1624static const char * const dev3_groups[] = {
1625 "clk3_req_pee1",
1626};
1627
1628static const char * const displaya_groups[] = {
1629 "dap3_fs_pp0",
1630 "dap3_din_pp1",
1631 "dap3_dout_pp2",
1632 "ph1",
1633 "pi4",
1634 "pbb3",
1635 "pbb4",
1636 "pbb5",
1637 "kb_row3_pr3",
1638 "kb_row4_pr4",
1639 "kb_row5_pr5",
1640 "kb_row6_pr6",
1641 "kb_col3_pq3",
1642 "sdmmc3_dat2_pb5",
1643};
1644
1645static const char * const displaya_alt_groups[] = {
1646 "kb_row6_pr6",
1647};
1648
1649static const char * const displayb_groups[] = {
1650 "dap3_fs_pp0",
1651 "dap3_din_pp1",
1652 "dap3_sclk_pp3",
1653
1654 "pu3",
1655 "pu4",
1656 "pu5",
1657
1658 "pbb3",
1659 "pbb4",
1660 "pbb6",
1661
1662 "kb_row3_pr3",
1663 "kb_row4_pr4",
1664 "kb_row5_pr5",
1665 "kb_row6_pr6",
1666
1667 "sdmmc3_dat3_pb4",
1668};
1669
1670static const char * const dtv_groups[] = {
1671 "uart3_cts_n_pa1",
1672 "uart3_rts_n_pc0",
1673 "dap4_fs_pp4",
1674 "dap4_dout_pp6",
1675 "pi7",
1676 "ph0",
1677 "ph6",
1678 "ph7",
1679};
1680
1681static const char * const extperiph1_groups[] = {
1682 "dap_mclk1_pw4",
1683};
1684
1685static const char * const extperiph2_groups[] = {
1686 "clk2_out_pw5",
1687};
1688
1689static const char * const extperiph3_groups[] = {
1690 "clk3_out_pee0",
1691};
1692
1693static const char * const gmi_groups[] = {
1694 "uart2_cts_n_pj5",
1695 "uart2_rts_n_pj6",
1696 "uart3_txd_pw6",
1697 "uart3_rxd_pw7",
1698 "uart3_cts_n_pa1",
1699 "uart3_rts_n_pc0",
1700
1701 "pu0",
1702 "pu1",
1703 "pu2",
1704 "pu3",
1705 "pu4",
1706 "pu5",
1707 "pu6",
1708
1709 "dap4_fs_pp4",
1710 "dap4_din_pp5",
1711 "dap4_dout_pp6",
1712 "dap4_sclk_pp7",
1713
1714 "pc7",
1715
1716 "pg0",
1717 "pg1",
1718 "pg2",
1719 "pg3",
1720 "pg4",
1721 "pg5",
1722 "pg6",
1723 "pg7",
1724
1725 "ph0",
1726 "ph1",
1727 "ph2",
1728 "ph3",
1729 "ph4",
1730 "ph5",
1731 "ph6",
1732 "ph7",
1733
1734 "pi0",
1735 "pi1",
1736 "pi2",
1737 "pi3",
1738 "pi4",
1739 "pi5",
1740 "pi6",
1741 "pi7",
1742
1743 "pj0",
1744 "pj2",
1745
1746 "pk0",
1747 "pk1",
1748 "pk2",
1749 "pk3",
1750 "pk4",
1751
1752 "pj7",
1753 "pb0",
1754 "pb1",
1755 "pk7",
1756
1757 "gen2_i2c_scl_pt5",
1758 "gen2_i2c_sda_pt6",
1759
1760 "sdmmc4_dat0_paa0",
1761 "sdmmc4_dat1_paa1",
1762 "sdmmc4_dat2_paa2",
1763 "sdmmc4_dat3_paa3",
1764 "sdmmc4_dat4_paa4",
1765 "sdmmc4_dat6_paa6",
1766 "sdmmc4_dat7_paa7",
1767 "sdmmc4_clk_pcc4",
1768 "sdmmc4_cmd_pt7",
1769 "gmi_clk_lb",
1770
1771 "dap1_fs_pn0",
1772 "dap1_din_pn1",
1773 "dap1_dout_pn2",
1774 "dap1_sclk_pn3",
1775
1776 "dap2_fs_pa2",
1777 "dap2_din_pa4",
1778 "dap2_dout_pa5",
1779 "dap2_sclk_pa3",
1780
1781 "dvfs_pwm_px0",
1782 "dvfs_clk_px2",
1783 "gpio_x1_aud_px1",
1784 "gpio_x3_aud_px3",
1785 "gpio_x4_aud_px4",
1786 "gpio_x5_aud_px5",
1787 "gpio_x6_aud_px6",
1788};
1789
1790static const char * const gmi_alt_groups[] = {
1791 "pc7",
1792 "pk4",
1793 "pj7",
1794};
1795
1796static const char * const hda_groups[] = {
1797 "dap1_fs_pn0",
1798 "dap1_din_pn1",
1799 "dap1_dout_pn2",
1800 "dap1_sclk_pn3",
1801 "dap2_fs_pa2",
1802 "dap2_sclk_pa3",
1803 "dap2_din_pa4",
1804 "dap2_dout_pa5",
1805};
1806
1807static const char * const hsi_groups[] = {
1808 "ulpi_data0_po1",
1809 "ulpi_data1_po2",
1810 "ulpi_data2_po3",
1811 "ulpi_data3_po4",
1812 "ulpi_data4_po5",
1813 "ulpi_data5_po6",
1814 "ulpi_data6_po7",
1815 "ulpi_data7_po0",
1816};
1817
1818static const char * const i2c1_groups[] = {
1819 "gen1_i2c_scl_pc4",
1820 "gen1_i2c_sda_pc5",
1821 "gpio_w2_aud_pw2",
1822 "gpio_w3_aud_pw3",
1823};
1824
1825static const char * const i2c2_groups[] = {
1826 "gen2_i2c_scl_pt5",
1827 "gen2_i2c_sda_pt6",
1828};
1829
1830static const char * const i2c3_groups[] = {
1831 "spdif_in_pk6",
1832 "spdif_out_pk5",
1833 "cam_i2c_scl_pbb1",
1834 "cam_i2c_sda_pbb2",
1835};
1836
1837static const char * const i2c4_groups[] = {
1838 "ddc_scl_pv4",
1839 "ddc_sda_pv5",
1840};
1841
1842static const char * const i2cpwr_groups[] = {
1843 "pwr_i2c_scl_pz6",
1844 "pwr_i2c_sda_pz7",
1845};
1846
1847static const char * const i2s0_groups[] = {
1848 "dap1_fs_pn0",
1849 "dap1_din_pn1",
1850 "dap1_dout_pn2",
1851 "dap1_sclk_pn3",
1852};
1853
1854static const char * const i2s1_groups[] = {
1855 "dap2_fs_pa2",
1856 "dap2_sclk_pa3",
1857 "dap2_din_pa4",
1858 "dap2_dout_pa5",
1859};
1860
1861static const char * const i2s2_groups[] = {
1862 "dap3_fs_pp0",
1863 "dap3_din_pp1",
1864 "dap3_dout_pp2",
1865 "dap3_sclk_pp3",
1866};
1867
1868static const char * const i2s3_groups[] = {
1869 "dap4_fs_pp4",
1870 "dap4_din_pp5",
1871 "dap4_dout_pp6",
1872 "dap4_sclk_pp7",
1873};
1874
1875static const char * const i2s4_groups[] = {
1876 "pcc1",
1877 "pbb6",
1878 "pbb7",
1879 "pcc2",
1880};
1881
1882static const char * const irda_groups[] = {
1883 "uart2_rxd_pc3",
1884 "uart2_txd_pc2",
1885 "kb_row11_ps3",
1886 "kb_row12_ps4",
1887};
1888
1889static const char * const kbc_groups[] = {
1890 "kb_row0_pr0",
1891 "kb_row1_pr1",
1892 "kb_row2_pr2",
1893 "kb_row3_pr3",
1894 "kb_row4_pr4",
1895 "kb_row5_pr5",
1896 "kb_row6_pr6",
1897 "kb_row7_pr7",
1898 "kb_row8_ps0",
1899 "kb_row9_ps1",
1900 "kb_row10_ps2",
1901 "kb_row11_ps3",
1902 "kb_row12_ps4",
1903 "kb_row13_ps5",
1904 "kb_row14_ps6",
1905 "kb_row15_ps7",
1906 "kb_row16_pt0",
1907 "kb_row17_pt1",
1908
1909 "kb_col0_pq0",
1910 "kb_col1_pq1",
1911 "kb_col2_pq2",
1912 "kb_col3_pq3",
1913 "kb_col4_pq4",
1914 "kb_col5_pq5",
1915 "kb_col6_pq6",
1916 "kb_col7_pq7",
1917};
1918
1919static const char * const owr_groups[] = {
1920 "pu0",
1921 "kb_col4_pq4",
1922 "owr",
1923 "sdmmc3_cd_n_pv2",
1924};
1925
1926static const char * const pmi_groups[] = {
1927 "pwr_int_n",
1928};
1929
1930static const char * const pwm0_groups[] = {
1931 "sdmmc1_dat2_py5",
1932 "uart3_rts_n_pc0",
1933 "pu3",
1934 "ph0",
1935 "sdmmc3_dat3_pb4",
1936};
1937
1938static const char * const pwm1_groups[] = {
1939 "sdmmc1_dat1_py6",
1940 "pu4",
1941 "ph1",
1942 "sdmmc3_dat2_pb5",
1943};
1944
1945static const char * const pwm2_groups[] = {
1946 "pu5",
1947 "ph2",
1948 "kb_col3_pq3",
1949 "sdmmc3_dat1_pb6",
1950};
1951
1952static const char * const pwm3_groups[] = {
1953 "pu6",
1954 "ph3",
1955 "sdmmc3_cmd_pa7",
1956};
1957
1958static const char * const pwron_groups[] = {
1959 "core_pwr_req",
1960};
1961
1962static const char * const reset_out_n_groups[] = {
1963 "reset_out_n",
1964};
1965
1966static const char * const rsvd1_groups[] = {
1967 "pv0",
1968 "pv1",
1969
1970 "hdmi_int_pn7",
1971 "pu1",
1972 "pu2",
1973 "pc7",
1974 "pi7",
1975 "pk0",
1976 "pj0",
1977 "pj2",
1978 "pk2",
1979 "pi3",
1980 "pi6",
1981
1982 "pg0",
1983 "pg1",
1984 "pg2",
1985 "pg3",
1986 "pg4",
1987 "pg5",
1988 "pg6",
1989 "pg7",
1990
1991 "pi0",
1992 "pi1",
1993
1994 "gpio_x7_aud_px7",
1995
1996 "reset_out_n",
1997};
1998
1999static const char * const rsvd2_groups[] = {
2000 "pv0",
2001 "pv1",
2002
2003 "sdmmc1_dat0_py7",
2004 "clk2_out_pw5",
2005 "clk2_req_pcc5",
2006 "hdmi_int_pn7",
2007 "ddc_scl_pv4",
2008 "ddc_sda_pv5",
2009
2010 "uart3_txd_pw6",
2011 "uart3_rxd_pw7",
2012
2013 "gen1_i2c_scl_pc4",
2014 "gen1_i2c_sda_pc5",
2015
2016 "clk2_out_pee0",
2017 "clk2_req_pee1",
2018 "pc7",
2019 "pi5",
2020 "pj0",
2021 "pj2",
2022
2023 "pk4",
2024 "pk2",
2025 "pi3",
2026 "pi6",
2027 "pg0",
2028 "pg1",
2029 "pg5",
2030 "pg6",
2031 "pg7",
2032
2033 "ph4",
2034 "ph5",
2035 "pj7",
2036 "pb0",
2037 "pb1",
2038 "pk7",
2039 "pi0",
2040 "pi1",
2041
2042 "gen2_i2c_scl_pt5",
2043 "gen2_i2c_sda_pt6",
2044 "sdmmc4_clk_pcc4",
2045 "sdmmc4_cmd_pt7",
2046 "sdmmc4_dat7_paa7",
2047 "pcc1",
2048 "pbb6",
2049 "pbb7",
2050 "pcc2",
2051 "jtag_rtck",
2052
2053 "pwr_i2c_scl_pz6",
2054 "pwr_i2c_sda_pz7",
2055
2056 "kb_row0_pr0",
2057 "kb_row1_pr1",
2058 "kb_row2_pr2",
2059 "kb_row7_pr7",
2060 "kb_row8_ps0",
2061 "kb_row9_ps1",
2062 "kb_row10_ps2",
2063 "kb_row11_ps3",
2064 "kb_row12_ps4",
2065 "kb_row13_ps5",
2066 "kb_row14_ps6",
2067
2068 "kb_col0_pq0",
2069 "kb_col1_pq1",
2070 "kb_col2_pq2",
2071 "kb_col5_pq5",
2072 "kb_col6_pq6",
2073 "kb_col7_pq7",
2074
2075 "core_pwr_req",
2076 "cpu_pwr_req",
2077 "pwr_int_n",
2078 "clk_32k_in",
2079 "owr",
2080
2081 "spdif_in_pk6",
2082 "spdif_out_pk5",
2083 "gpio_x1_aud_px1",
2084
2085 "sdmmc3_clk_pa6",
2086 "sdmmc3_dat0_pb7",
2087
2088 "pex_l0_rst_n_pdd1",
2089 "pex_l0_clkreq_n_pdd2",
2090 "pex_wake_n_pdd3",
2091 "pex_l1_rst_n_pdd5",
2092 "pex_l1_clkreq_n_pdd6",
2093 "hdmi_cec_pee3",
2094
2095 "gpio_w2_aud_pw2",
2096 "usb_vbus_en0_pn4",
2097 "usb_vbus_en1_pn5",
2098 "sdmmc3_clk_lb_out_pee4",
2099 "sdmmc3_clk_lb_in_pee5",
2100 "gmi_clk_lb",
2101 "reset_out_n",
2102 "kb_row16_pt0",
2103 "kb_row17_pt1",
2104 "dp_hpd_pff0",
2105 "usb_vbus_en2_pff1",
2106 "pff2",
2107};
2108
2109static const char * const rsvd3_groups[] = {
2110 "dap3_sclk_pp3",
2111 "pv0",
2112 "pv1",
2113 "sdmmc1_clk_pz0",
2114 "clk2_out_pw5",
2115 "clk2_req_pcc5",
2116 "hdmi_int_pn7",
2117
2118 "ddc_scl_pv4",
2119 "ddc_sda_pv5",
2120
2121 "pu6",
2122
2123 "gen1_i2c_scl_pc4",
2124 "gen1_i2c_sda_pc5",
2125
2126 "dap4_din_pp5",
2127 "dap4_sclk_pp7",
2128
2129 "clk3_out_pee0",
2130 "clk3_req_pee1",
2131
2132 "sdmmc4_dat5_paa5",
2133 "gpio_pcc1",
2134 "cam_i2c_scl_pbb1",
2135 "cam_i2c_sda_pbb2",
2136 "pbb5",
2137 "pbb7",
2138 "jtag_rtck",
2139 "pwr_i2c_scl_pz6",
2140 "pwr_i2c_sda_pz7",
2141
2142 "kb_row0_pr0",
2143 "kb_row1_pr1",
2144 "kb_row2_pr2",
2145 "kb_row4_pr4",
2146 "kb_row5_pr5",
2147 "kb_row9_ps1",
2148 "kb_row10_ps2",
2149 "kb_row11_ps3",
2150 "kb_row12_ps4",
2151 "kb_row15_ps7",
2152
2153 "clk_32k_out_pa0",
2154 "core_pwr_req",
2155 "cpu_pwr_req",
2156 "pwr_int_n",
2157 "clk_32k_in",
2158 "owr",
2159
2160 "dap_mclk1_pw4",
2161 "spdif_in_pk6",
2162 "spdif_out_pk5",
2163 "sdmmc3_clk_pa6",
2164 "sdmmc3_dat0_pb7",
2165
2166 "pex_l0_rst_n_pdd1",
2167 "pex_l0_clkreq_n_pdd2",
2168 "pex_wake_n_pdd3",
2169 "pex_l1_rst_n_pdd5",
2170 "pex_l1_clkreq_n_pdd6",
2171 "hdmi_cec_pee3",
2172
2173 "sdmmc3_cd_n_pv2",
2174 "usb_vbus_en0_pn4",
2175 "usb_vbus_en1_pn5",
2176 "sdmmc3_clk_lb_out_pee4",
2177 "sdmmc3_clk_lb_in_pee5",
2178 "reset_out_n",
2179 "kb_row16_pt0",
2180 "kb_row17_pt1",
2181 "dp_hpd_pff0",
2182 "usb_vbus_en2_pff1",
2183 "pff2",
2184};
2185
2186static const char * const rsvd4_groups[] = {
2187 "dap3_dout_pp2",
2188 "pv0",
2189 "pv1",
2190 "sdmmc1_clk_pz0",
2191
2192 "clk2_out_pw5",
2193 "clk2_req_pcc5",
2194 "hdmi_int_pn7",
2195 "ddc_scl_pv4",
2196 "ddc_sda_pv5",
2197
2198 "uart2_rts_n_pj6",
2199 "uart2_cts_n_pj5",
2200 "uart3_txd_pw6",
2201 "uart3_rxd_pw7",
2202
2203 "pu0",
2204 "pu1",
2205 "pu2",
2206
2207 "gen1_i2c_scl_pc4",
2208 "gen1_i2c_sda_pc5",
2209
2210 "dap4_fs_pp4",
2211 "dap4_dout_pp6",
2212 "dap4_din_pp5",
2213 "dap4_sclk_pp7",
2214
2215 "clk3_out_pee0",
2216 "clk3_req_pee1",
2217
2218 "pi5",
2219 "pk1",
2220 "pk2",
2221 "pg0",
2222 "pg1",
2223 "pg2",
2224 "pg3",
2225 "ph4",
2226 "ph5",
2227 "pb0",
2228 "pb1",
2229 "pk7",
2230 "pi0",
2231 "pi1",
2232 "pi2",
2233
2234 "gen2_i2c_scl_pt5",
2235 "gen2_i2c_sda_pt6",
2236
2237 "sdmmc4_cmd_pt7",
2238 "sdmmc4_dat0_paa0",
2239 "sdmmc4_dat1_paa1",
2240 "sdmmc4_dat2_paa2",
2241 "sdmmc4_dat3_paa3",
2242 "sdmmc4_dat4_paa4",
2243 "sdmmc4_dat5_paa5",
2244 "sdmmc4_dat6_paa6",
2245 "sdmmc4_dat7_paa7",
2246
2247 "jtag_rtck",
2248 "pwr_i2c_scl_pz6",
2249 "pwr_i2c_sda_pz7",
2250
2251 "kb_row0_pr0",
2252 "kb_row1_pr1",
2253 "kb_row2_pr2",
2254 "kb_row13_ps5",
2255 "kb_row14_ps6",
2256 "kb_row15_ps7",
2257
2258 "kb_col0_pq0",
2259 "kb_col1_pq1",
2260 "kb_col2_pq2",
2261 "kb_col5_pq5",
2262
2263 "clk_32k_out_pa0",
2264 "core_pwr_req",
2265 "cpu_pwr_req",
2266 "pwr_int_n",
2267 "clk_32k_in",
2268 "owr",
2269
2270 "dap1_fs_pn0",
2271 "dap1_din_pn1",
2272 "dap1_sclk_pn3",
2273 "dap_mclk1_req_pee2",
2274 "dap_mclk1_pw5",
2275
2276 "dap2_fs_pa2",
2277 "dap2_din_pa4",
2278 "dap2_dout_pa5",
2279 "dap2_sclk_pa3",
2280
2281 "dvfs_pwm_px0",
2282 "dvfs_clk_px2",
2283 "gpio_x1_aud_px1",
2284 "gpio_x3_aud_px3",
2285
2286 "gpio_x5_aud_px5",
2287 "gpio_x7_aud_px7",
2288
2289 "pex_l0_rst_n_pdd1",
2290 "pex_l0_clkreq_n_pdd2",
2291 "pex_wake_n_pdd3",
2292 "pex_l1_rst_n_pdd5",
2293 "pex_l1_clkreq_n_pdd6",
2294 "hdmi_cec_pee3",
2295
2296 "sdmmc3_cd_n_pv2",
2297 "usb_vbus_en0_pn4",
2298 "usb_vbus_en1_pn5",
2299 "sdmmc3_clk_lb_out_pee4",
2300 "sdmmc3_clk_lb_in_pee5",
2301 "gmi_clk_lb",
2302
2303 "dp_hpd_pff0",
2304 "usb_vbus_en2_pff1",
2305 "pff2",
2306};
2307
2308static const char * const sdmmc1_groups[] = {
2309 "sdmmc1_clk_pz0",
2310 "sdmmc1_cmd_pz1",
2311 "sdmmc1_dat3_py4",
2312 "sdmmc1_dat2_py5",
2313 "sdmmc1_dat1_py6",
2314 "sdmmc1_dat0_py7",
2315 "clk2_out_pw5",
2316 "clk2_req_pcc",
2317 "uart3_cts_n_pa1",
2318 "sdmmc1_wp_n_pv3",
2319};
2320
2321static const char * const sdmmc2_groups[] = {
2322 "pi5",
2323 "pk1",
2324 "pk3",
2325 "pk4",
2326 "pi6",
2327 "ph4",
2328 "ph5",
2329 "ph6",
2330 "ph7",
2331 "pi2",
2332 "cam_mclk_pcc0",
2333 "pcc1",
2334 "pbb0",
2335 "cam_i2c_scl_pbb1",
2336 "cam_i2c_sda_pbb2",
2337 "pbb3",
2338 "pbb4",
2339 "pbb5",
2340 "pbb6",
2341 "pbb7",
2342 "pcc2",
2343 "gmi_clk_lb",
2344};
2345
2346static const char * const sdmmc3_groups[] = {
2347 "pk0",
2348 "pcc2",
2349
2350 "kb_col4_pq4",
2351 "kb_col5_pq5",
2352
2353 "sdmmc3_clk_pa6",
2354 "sdmmc3_cmd_pa7",
2355 "sdmmc3_dat0_pb7",
2356 "sdmmc3_dat1_pb6",
2357 "sdmmc3_dat2_pb5",
2358 "sdmmc3_dat3_pb4",
2359
2360 "sdmmc3_cd_n_pv2",
2361 "sdmmc3_clk_lb_in_pee5",
2362 "sdmmc3_clk_lb_out_pee4",
2363};
2364
2365static const char * const sdmmc4_groups[] = {
2366 "sdmmc4_clk_pcc4",
2367 "sdmmc4_cmd_pt7",
2368 "sdmmc4_dat0_paa0",
2369 "sdmmc4_dat1_paa1",
2370 "sdmmc4_dat2_paa2",
2371 "sdmmc4_dat3_paa3",
2372 "sdmmc4_dat4_paa4",
2373 "sdmmc4_dat5_paa5",
2374 "sdmmc4_dat6_paa6",
2375 "sdmmc4_dat7_paa7",
2376};
2377
2378static const char * const soc_groups[] = {
2379 "pk0",
2380 "pj2",
2381 "kb_row15_ps7",
2382 "clk_32k_out_pa0",
2383};
2384
2385static const char * const spdif_groups[] = {
2386 "sdmmc1_cmd_pz1",
2387 "sdmmc1_dat3_py4",
2388 "uart2_rxd_pc3",
2389 "uart2_txd_pc2",
2390 "spdif_in_pk6",
2391 "spdif_out_pk5",
2392};
2393
2394static const char * const spi1_groups[] = {
2395 "ulpi_clk_py0",
2396 "ulpi_dir_py1",
2397 "ulpi_nxt_py2",
2398 "ulpi_stp_py3",
2399 "gpio_x3_aud_px3",
2400 "gpio_x4_aud_px4",
2401 "gpio_x5_aud_px5",
2402 "gpio_x6_aud_px6",
2403 "gpio_x7_aud_px7",
2404 "gpio_w3_aud_pw3",
2405};
2406
2407static const char * const spi2_groups[] = {
2408 "ulpi_data4_po5",
2409 "ulpi_data5_po6",
2410 "ulpi_data6_po7",
2411 "ulpi_data7_po0",
2412
2413 "kb_row13_ps5",
2414 "kb_row14_ps6",
2415 "kb_row15_ps7",
2416 "kb_col0_pq0",
2417 "kb_col1_pq1",
2418 "kb_col2_pq2",
2419 "kb_col6_pq6",
2420 "kb_col7_pq7",
2421 "gpio_x4_aud_px4",
2422 "gpio_x5_aud_px5",
2423 "gpio_x6_aud_px6",
2424 "gpio_x7_aud_px7",
2425 "gpio_w2_aud_pw2",
2426 "gpio_w3_aud_pw3",
2427};
2428
2429static const char * const spi3_groups[] = {
2430 "ulpi_data0_po1",
2431 "ulpi_data1_po2",
2432 "ulpi_data2_po3",
2433 "ulpi_data3_po4",
2434 "sdmmc4_dat0_paa0",
2435 "sdmmc4_dat1_paa1",
2436 "sdmmc4_dat2_paa2",
2437 "sdmmc4_dat3_paa3",
2438 "sdmmc4_dat4_paa4",
2439 "sdmmc4_dat5_paa5",
2440 "sdmmc4_dat6_paa6",
2441 "sdmmc3_clk_pa6",
2442 "sdmmc3_cmd_pa7",
2443 "sdmmc3_dat0_pb7",
2444 "sdmmc3_dat1_pb6",
2445 "sdmmc3_dat2_pb5",
2446 "sdmmc3_dat3_pb4",
2447};
2448
2449static const char * const spi4_groups[] = {
2450 "sdmmc1_cmd_pz1",
2451 "sdmmc1_dat3_py4",
2452 "sdmmc1_dat2_py5",
2453 "sdmmc1_dat1_py6",
2454 "sdmmc1_dat0_py7",
2455
2456 "uart2_rxd_pc3",
2457 "uart2_txd_pc2",
2458 "uart2_rts_n_pj6",
2459 "uart2_cts_n_pj5",
2460 "uart3_txd_pw6",
2461 "uart3_rxd_pw7",
2462
2463 "pi3",
2464 "pg4",
2465 "pg5",
2466 "pg6",
2467 "pg7",
2468 "ph3",
2469 "pi4",
2470 "sdmmc1_wp_n_pv3",
2471};
2472
2473static const char * const spi5_groups[] = {
2474 "ulpi_clk_py0",
2475 "ulpi_dir_py1",
2476 "ulpi_nxt_py2",
2477 "ulpi_stp_py3",
2478 "dap3_fs_pp0",
2479 "dap3_din_pp1",
2480 "dap3_dout_pp2",
2481 "dap3_sclk_pp3",
2482};
2483
2484static const char * const spi6_groups[] = {
2485 "dvfs_pwm_px0",
2486 "gpio_x1_aud_px1",
2487 "gpio_x3_aud_px3",
2488 "dvfs_clk_px2",
2489 "gpio_x6_aud_px6",
2490 "gpio_w2_aud_pw2",
2491 "gpio_w3_aud_pw3",
2492};
2493
2494static const char * const trace_groups[] = {
2495 "pi2",
2496 "pi4",
2497 "pi7",
2498 "ph0",
2499 "ph6",
2500 "ph7",
2501 "pg2",
2502 "pg3",
2503 "pk1",
2504 "pk3",
2505};
2506
2507static const char * const uarta_groups[] = {
2508 "ulpi_data0_po1",
2509 "ulpi_data1_po2",
2510 "ulpi_data2_po3",
2511 "ulpi_data3_po4",
2512 "ulpi_data4_po5",
2513 "ulpi_data5_po6",
2514 "ulpi_data6_po7",
2515 "ulpi_data7_po0",
2516
2517 "sdmmc1_cmd_pz1",
2518 "sdmmc1_dat3_py4",
2519 "sdmmc1_dat2_py5",
2520 "sdmmc1_dat1_py6",
2521 "sdmmc1_dat0_py7",
2522
2523
2524 "uart2_rxd_pc3",
2525 "uart2_txd_pc2",
2526 "uart2_rts_n_pj6",
2527 "uart2_cts_n_pj5",
2528
2529 "pu0",
2530 "pu1",
2531 "pu2",
2532 "pu3",
2533 "pu4",
2534 "pu5",
2535 "pu6",
2536
2537 "kb_row7_pr7",
2538 "kb_row8_ps0",
2539 "kb_row9_ps1",
2540 "kb_row10_ps2",
2541 "kb_col3_pq3",
2542 "kb_col4_pq4",
2543
2544 "sdmmc3_cmd_pa7",
2545 "sdmmc3_dat1_pb6",
2546 "sdmmc1_wp_n_pv3",
2547
2548};
2549
2550static const char * const uartb_groups[] = {
2551 "uart2_rts_n_pj6",
2552 "uart2_cts_n_pj5",
2553};
2554
2555static const char * const uartc_groups[] = {
2556 "uart3_txd_pw6",
2557 "uart3_rxd_pw7",
2558 "uart3_cts_n_pa1",
2559 "uart3_rts_n_pc0",
2560 "kb_row16_pt0",
2561 "kn_row17_pt1",
2562};
2563
2564static const char * const uartd_groups[] = {
2565 "ulpi_clk_py0",
2566 "ulpi_dir_py1",
2567 "ulpi_nxt_py2",
2568 "ulpi_stp_py3",
2569 "pj7",
2570 "pb0",
2571 "pb1",
2572 "pk7",
2573 "kb_col6_pq6",
2574 "kb_col7_pq7",
2575};
2576
2577static const char * const ulpi_groups[] = {
2578 "ulpi_data0_po1",
2579 "ulpi_data1_po2",
2580 "ulpi_data2_po3",
2581 "ulpi_data3_po4",
2582 "ulpi_data4_po5",
2583 "ulpi_data5_po6",
2584 "ulpi_data6_po7",
2585 "ulpi_data7_po0",
2586 "ulpi_clk_py0",
2587 "ulpi_dir_py1",
2588 "ulpi_nxt_py2",
2589 "ulpi_stp_py3",
2590};
2591
2592static const char * const usb_groups[] = {
2593 "pj0",
2594 "usb_vbus_en0_pn4",
2595 "usb_vbus_en1_pn5",
2596 "usb_vbus_en2_pff1",
2597};
2598
2599static const char * const vgp1_groups[] = {
2600 "cam_i2c_scl_pbb1",
2601};
2602
2603static const char * const vgp2_groups[] = {
2604 "cam_i2c_sda_pbb2",
2605};
2606
2607static const char * const vgp3_groups[] = {
2608 "pbb3",
2609};
2610
2611static const char * const vgp4_groups[] = {
2612 "pbb4",
2613};
2614
2615static const char * const vgp5_groups[] = {
2616 "pbb5",
2617};
2618
2619static const char * const vgp6_groups[] = {
2620 "pbb0",
2621};
2622
2623static const char * const vi_groups[] = {
2624 "cam_mclk_pcc0",
2625};
2626
2627static const char * const vi_alt1_groups[] = {
2628 "cam_mclk_pcc0",
2629};
2630
2631static const char * const vi_alt3_groups[] = {
2632 "cam_mclk_pcc0",
2633};
2634
2635static const char * const vimclk2_groups[] = {
2636 "pbb0",
2637};
2638
2639static const char * const vimclk2_alt_groups[] = {
2640 "pbb0",
2641};
2642
2643static const char * const sata_groups[] = {
2644 "dap_mclk1_req_pee2",
2645 "dap1_dout_pn2",
2646 "pff2",
2647};
2648
2649static const char * const ccla_groups[] = {
2650 "pk3",
2651};
2652
2653static const char * const rtck_groups[] = {
2654 "jtag_rtck",
2655};
2656
2657static const char * const sys_groups[] = {
2658 "kb_row3_pr3",
2659};
2660
2661static const char * const pe0_groups[] = {
2662 "pex_l0_rst_n_pdd1",
2663 "pex_l0_clkreq_n_pdd2",
2664};
2665
2666static const char * const pe_groups[] = {
2667 "pex_wake_n_pdd3",
2668};
2669
2670static const char * const pe1_groups[] = {
2671 "pex_l1_rst_n_pdd5",
2672 "pex_l1_clkreq_n_pdd6",
2673};
2674
2675static const char * const dp_groups[] = {
2676 "dp_hpd_pff0",
2677};
2678
2679static const char * const clk_groups[] = {
2680 "clk_32k_in",
2681};
2682
2683static const char * const tmds_groups[] = {
2684 "pg4",
2685 "ph1",
2686 "ph2",
2687};
2688
2689#define FUNCTION(fname) \
2690 { \
2691 .name = #fname, \
2692 .groups = fname##_groups, \
2693 .ngroups = ARRAY_SIZE(fname##_groups), \
2694 }
2695
2696static const struct tegra_function tegra124_functions[] = {
2697 FUNCTION(blink),
2698 FUNCTION(cec),
2699 FUNCTION(cldvfs),
2700 FUNCTION(clk12),
2701 FUNCTION(cpu),
2702 FUNCTION(dap),
2703 FUNCTION(dap1),
2704 FUNCTION(dap2),
2705 FUNCTION(dev3),
2706 FUNCTION(displaya),
2707 FUNCTION(displaya_alt),
2708 FUNCTION(displayb),
2709 FUNCTION(dtv),
2710 FUNCTION(extperiph1),
2711 FUNCTION(extperiph2),
2712 FUNCTION(extperiph3),
2713 FUNCTION(gmi),
2714 FUNCTION(gmi_alt),
2715 FUNCTION(hda),
2716 FUNCTION(hsi),
2717 FUNCTION(i2c1),
2718 FUNCTION(i2c2),
2719 FUNCTION(i2c3),
2720 FUNCTION(i2c4),
2721 FUNCTION(i2cpwr),
2722 FUNCTION(i2s0),
2723 FUNCTION(i2s1),
2724 FUNCTION(i2s2),
2725 FUNCTION(i2s3),
2726 FUNCTION(i2s4),
2727 FUNCTION(irda),
2728 FUNCTION(kbc),
2729 FUNCTION(owr),
2730 FUNCTION(pmi),
2731 FUNCTION(pwm0),
2732 FUNCTION(pwm1),
2733 FUNCTION(pwm2),
2734 FUNCTION(pwm3),
2735 FUNCTION(pwron),
2736 FUNCTION(reset_out_n),
2737 FUNCTION(rsvd1),
2738 FUNCTION(rsvd2),
2739 FUNCTION(rsvd3),
2740 FUNCTION(rsvd4),
2741 FUNCTION(sdmmc1),
2742 FUNCTION(sdmmc2),
2743 FUNCTION(sdmmc3),
2744 FUNCTION(sdmmc4),
2745 FUNCTION(soc),
2746 FUNCTION(spdif),
2747 FUNCTION(spi1),
2748 FUNCTION(spi2),
2749 FUNCTION(spi3),
2750 FUNCTION(spi4),
2751 FUNCTION(spi5),
2752 FUNCTION(spi6),
2753 FUNCTION(trace),
2754 FUNCTION(uarta),
2755 FUNCTION(uartb),
2756 FUNCTION(uartc),
2757 FUNCTION(uartd),
2758 FUNCTION(ulpi),
2759 FUNCTION(usb),
2760 FUNCTION(vgp1),
2761 FUNCTION(vgp2),
2762 FUNCTION(vgp3),
2763 FUNCTION(vgp4),
2764 FUNCTION(vgp5),
2765 FUNCTION(vgp6),
2766 FUNCTION(vi),
2767 FUNCTION(vi_alt1),
2768 FUNCTION(vi_alt3),
2769 FUNCTION(vimclk2),
2770 FUNCTION(vimclk2_alt),
2771 FUNCTION(sata),
2772 FUNCTION(ccla),
2773 FUNCTION(pe0),
2774 FUNCTION(pe),
2775 FUNCTION(pe1),
2776 FUNCTION(dp),
2777 FUNCTION(rtck),
2778 FUNCTION(sys),
2779 FUNCTION(clk),
2780 FUNCTION(tmds),
2781};
2782
2783#define DRV_PINGROUP_REG_A 0x868 /* bank 0 */
2784#define PINGROUP_REG_A 0x3000 /* bank 1 */
2785
2786#define PINGROUP_REG_Y(r) ((r) - PINGROUP_REG_A)
2787#define PINGROUP_REG_N(r) -1
2788
2789#define PINGROUP(pg_name, f0, f1, f2, f3, f_safe, r, od, ior, rcv_sel) \
2790 { \
2791 .name = #pg_name, \
2792 .pins = pg_name##_pins, \
2793 .npins = ARRAY_SIZE(pg_name##_pins), \
2794 .funcs = { \
2795 TEGRA_MUX_ ## f0, \
2796 TEGRA_MUX_ ## f1, \
2797 TEGRA_MUX_ ## f2, \
2798 TEGRA_MUX_ ## f3, \
2799 }, \
2800 .func_safe = TEGRA_MUX_ ## f_safe, \
2801 .mux_reg = PINGROUP_REG_Y(r), \
2802 .mux_bank = 1, \
2803 .mux_bit = 0, \
2804 .pupd_reg = PINGROUP_REG_Y(r), \
2805 .pupd_bank = 1, \
2806 .pupd_bit = 2, \
2807 .tri_reg = PINGROUP_REG_Y(r), \
2808 .tri_bank = 1, \
2809 .tri_bit = 4, \
2810 .einput_reg = PINGROUP_REG_Y(r), \
2811 .einput_bank = 1, \
2812 .einput_bit = 5, \
2813 .odrain_reg = PINGROUP_REG_##od(r), \
2814 .odrain_bank = 1, \
2815 .odrain_bit = 6, \
2816 .lock_reg = PINGROUP_REG_Y(r), \
2817 .lock_bank = 1, \
2818 .lock_bit = 7, \
2819 .ioreset_reg = PINGROUP_REG_##ior(r), \
2820 .ioreset_bank = 1, \
2821 .ioreset_bit = 8, \
2822 .rcv_sel_reg = PINGROUP_REG_##rcv_sel(r), \
2823 .rcv_sel_bank = 1, \
2824 .rcv_sel_bit = 9, \
2825 .drv_reg = -1, \
2826 .drvtype_reg = -1, \
2827 }
2828
2829#define DRV_PINGROUP_DVRTYPE_Y(r) ((r) - DRV_PINGROUP_REG_A)
2830#define DRV_PINGROUP_DVRTYPE_N(r) -1
2831
2832#define DRV_PINGROUP(pg_name, r, hsm_b, schmitt_b, lpmd_b, \
2833 drvdn_b, drvdn_w, drvup_b, drvup_w, \
2834 slwr_b, slwr_w, slwf_b, slwf_w, \
2835 drvtype) \
2836 { \
2837 .name = "drive_" #pg_name, \
2838 .pins = drive_##pg_name##_pins, \
2839 .npins = ARRAY_SIZE(drive_##pg_name##_pins), \
2840 .mux_reg = -1, \
2841 .pupd_reg = -1, \
2842 .tri_reg = -1, \
2843 .einput_reg = -1, \
2844 .odrain_reg = -1, \
2845 .lock_reg = -1, \
2846 .ioreset_reg = -1, \
2847 .rcv_sel_reg = -1, \
2848 .drv_reg = DRV_PINGROUP_DVRTYPE_Y(r), \
2849 .drv_bank = 0, \
2850 .hsm_bit = hsm_b, \
2851 .schmitt_bit = schmitt_b, \
2852 .lpmd_bit = lpmd_b, \
2853 .drvdn_bit = drvdn_b, \
2854 .drvdn_width = drvdn_w, \
2855 .drvup_bit = drvup_b, \
2856 .drvup_width = drvup_w, \
2857 .slwr_bit = slwr_b, \
2858 .slwr_width = slwr_w, \
2859 .slwf_bit = slwf_b, \
2860 .slwf_width = slwf_w, \
2861 .drvtype_reg = DRV_PINGROUP_DVRTYPE_##drvtype(r), \
2862 .drvtype_bank = 0, \
2863 .drvtype_bit = 6, \
2864 }
2865
2866static const struct tegra_pingroup tegra124_groups[] = {
2867 /* pg_name, f0, f1, f2, f3, safe, r, od, ior, rcv_sel */
2868 PINGROUP(ulpi_data0_po1, SPI3, HSI, UARTA, ULPI, SPI3, 0x3000, N, N, N),
2869 PINGROUP(ulpi_data1_po2, SPI3, HSI, UARTA, ULPI, SPI3, 0x3004, N, N, N),
2870 PINGROUP(ulpi_data2_po3, SPI3, HSI, UARTA, ULPI, SPI3, 0x3008, N, N, N),
2871 PINGROUP(ulpi_data3_po4, SPI3, HSI, UARTA, ULPI, SPI3, 0x300c, N, N, N),
2872 PINGROUP(ulpi_data4_po5, SPI2, HSI, UARTA, ULPI, SPI2, 0x3010, N, N, N),
2873 PINGROUP(ulpi_data5_po6, SPI2, HSI, UARTA, ULPI, SPI2, 0x3014, N, N, N),
2874 PINGROUP(ulpi_data6_po7, SPI2, HSI, UARTA, ULPI, SPI2, 0x3018, N, N, N),
2875 PINGROUP(ulpi_data7_po0, SPI2, HSI, UARTA, ULPI, SPI2, 0x301c, N, N, N),
2876 PINGROUP(ulpi_clk_py0, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3020, N, N, N),
2877 PINGROUP(ulpi_dir_py1, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3024, N, N, N),
2878 PINGROUP(ulpi_nxt_py2, SPI1, SPI5, UARTD, ULPI, SPI1, 0x3028, N, N, N),
2879 PINGROUP(ulpi_stp_py3, SPI1, SPI5, UARTD, ULPI, SPI1, 0x302c, N, N, N),
2880 PINGROUP(dap3_fs_pp0, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3030, N, N, N),
2881 PINGROUP(dap3_din_pp1, I2S2, SPI5, DISPLAYA, DISPLAYB, I2S2, 0x3034, N, N, N),
2882 PINGROUP(dap3_dout_pp2, I2S2, SPI5, DISPLAYA, RSVD4, I2S2, 0x3038, N, N, N),
2883 PINGROUP(dap3_sclk_pp3, I2S2, SPI5, RSVD3, DISPLAYB, I2S2, 0x303c, N, N, N),
2884 PINGROUP(pv0, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3040, N, N, N),
2885 PINGROUP(pv1, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3044, N, N, N),
2886 PINGROUP(sdmmc1_clk_pz0, SDMMC1, CLK12, RSVD3, RSVD4, RSVD3, 0x3048, N, N, N),
2887 PINGROUP(sdmmc1_cmd_pz1, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x304c, N, N, N),
2888 PINGROUP(sdmmc1_dat3_py4, SDMMC1, SPDIF, SPI4, UARTA, SDMMC1, 0x3050, N, N, N),
2889 PINGROUP(sdmmc1_dat2_py5, SDMMC1, PWM0, SPI4, UARTA, SDMMC1, 0x3054, N, N, N),
2890 PINGROUP(sdmmc1_dat1_py6, SDMMC1, PWM1, SPI4, UARTA, SDMMC1, 0x3058, N, N, N),
2891 PINGROUP(sdmmc1_dat0_py7, SDMMC1, RSVD2, SPI4, UARTA, SDMMC1, 0x305c, N, N, N),
2892 PINGROUP(clk2_out_pw5, EXTPERIPH2, RSVD2, RSVD3, RSVD4, EXTPERIPH2, 0x3068, N, N, N),
2893 PINGROUP(clk2_req_pcc5, DAP, RSVD2, RSVD3, RSVD4, DAP, 0x306c, N, N, N),
2894 PINGROUP(hdmi_int_pn7, RSVD1, RSVD2, RSVD3, RSVD4, RSVD1, 0x3110, N, N, Y),
2895 PINGROUP(ddc_scl_pv4, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3114, N, N, Y),
2896 PINGROUP(ddc_sda_pv5, I2C4, RSVD2, RSVD3, RSVD4, I2C4, 0x3118, N, N, Y),
2897 PINGROUP(uart2_rxd_pc3, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3164, N, N, N),
2898 PINGROUP(uart2_txd_pc2, IRDA, SPDIF, UARTA, SPI4, IRDA, 0x3168, N, N, N),
2899 PINGROUP(uart2_rts_n_pj6, UARTA, UARTB, GMI, SPI4, UARTA, 0x316c, N, N, N),
2900 PINGROUP(uart2_cts_n_pj5, UARTA, UARTB, GMI, SPI4, UARTA, 0x3170, N, N, N),
2901 PINGROUP(uart3_txd_pw6, UARTC, RSVD2, GMI, SPI4, UARTC, 0x3174, N, N, N),
2902 PINGROUP(uart3_rxd_pw7, UARTC, RSVD2, GMI, SPI4, UARTC, 0x3178, N, N, N),
2903 PINGROUP(uart3_cts_n_pa1, UARTC, SDMMC1, DTV, GMI, UARTC, 0x317c, N, N, N),
2904 PINGROUP(uart3_rts_n_pc0, UARTC, PWM0, DTV, GMI, UARTC, 0x3180, N, N, N),
2905 PINGROUP(pu0, OWR, UARTA, GMI, RSVD4, RSVD4, 0x3184, N, N, N),
2906 PINGROUP(pu1, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x3188, N, N, N),
2907 PINGROUP(pu2, RSVD1, UARTA, GMI, RSVD4, RSVD4, 0x318c, N, N, N),
2908 PINGROUP(pu3, PWM0, UARTA, GMI, DISPLAYB, PWM0, 0x3190, N, N, N),
2909 PINGROUP(pu4, PWM1, UARTA, GMI, DISPLAYB, PWM1, 0x3194, N, N, N),
2910 PINGROUP(pu5, PWM2, UARTA, GMI, DISPLAYB, PWM2, 0x3198, N, N, N),
2911 PINGROUP(pu6, PWM3, UARTA, RSVD3, GMI, RSVD3, 0x319c, N, N, N),
2912 PINGROUP(gen1_i2c_scl_pc4, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a0, Y, N, N),
2913 PINGROUP(gen1_i2c_sda_pc5, I2C1, RSVD2, RSVD3, RSVD4, I2C1, 0x31a4, Y, N, N),
2914 PINGROUP(dap4_fs_pp4, I2S3, GMI, DTV, RSVD4, I2S3, 0x31a8, N, N, N),
2915 PINGROUP(dap4_din_pp5, I2S3, GMI, RSVD3, RSVD4, I2S3, 0x31ac, N, N, N),
2916 PINGROUP(dap4_dout_pp6, I2S3, GMI, DTV, RSVD4, I2S3, 0x31b0, N, N, N),
2917 PINGROUP(dap4_sclk_pp7, I2S3, GMI, RSVD3, RSVD4, I2S3, 0x31b4, N, N, N),
2918 PINGROUP(clk3_out_pee0, EXTPERIPH3, RSVD2, RSVD3, RSVD4, RSVD3, 0x31b8, N, N, N),
2919 PINGROUP(clk3_req_pee1, DEV3, RSVD2, RSVD3, RSVD4, RSVD4, 0x31bc, N, N, N),
2920 PINGROUP(pc7, RSVD1, RSVD2, GMI, GMI_ALT, RSVD1, 0x31c0, N, N, N),
2921 PINGROUP(pi5, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x31c4, N, N, N),
2922 PINGROUP(pi7, RSVD1, TRACE, GMI, DTV, RSVD1, 0x31c8, N, N, N),
2923 PINGROUP(pk0, RSVD1, SDMMC3, GMI, SOC, RSVD1, 0x31cc, N, N, N),
2924 PINGROUP(pk1, SDMMC2, TRACE, GMI, RSVD4, GMI, 0x31d0, N, N, N),
2925 PINGROUP(pj0, RSVD1, RSVD2, GMI, USB, RSVD1, 0x31d4, N, N, N),
2926 PINGROUP(pj2, RSVD1, RSVD2, GMI, SOC, RSVD1, 0x31d8, N, N, N),
2927 PINGROUP(pk3, SDMMC2, TRACE, GMI, CCLA, GMI, 0x31dc, N, N, N),
2928 PINGROUP(pk4, SDMMC2, RSVD2, GMI, GMI_ALT, GMI, 0x31e0, N, N, N),
2929 PINGROUP(pk2, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31e4, N, N, N),
2930 PINGROUP(pi3, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x31e8, N, N, N),
2931 PINGROUP(pi6, RSVD1, RSVD2, GMI, SDMMC2, RSVD1, 0x31ec, N, N, N),
2932 PINGROUP(pg0, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31f0, N, N, N),
2933 PINGROUP(pg1, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x31f4, N, N, N),
2934 PINGROUP(pg2, RSVD1, TRACE, GMI, RSVD4, RSVD4, 0x31f8, N, N, N),
2935 PINGROUP(pg3, RSVD1, TRACE, GMI, RSVD4, RSVD4, 0x31fc, N, N, N),
2936 PINGROUP(pg4, RSVD1, TMDS, GMI, SPI4, RSVD1, 0x3200, N, N, N),
2937 PINGROUP(pg5, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x3204, N, N, N),
2938 PINGROUP(pg6, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x3208, N, N, N),
2939 PINGROUP(pg7, RSVD1, RSVD2, GMI, SPI4, RSVD1, 0x320c, N, N, N),
2940 PINGROUP(ph0, PWM0, TRACE, GMI, DTV, GMI, 0x3210, N, N, N),
2941 PINGROUP(ph1, PWM1, TMDS, GMI, DISPLAYA, GMI, 0x3214, N, N, N),
2942 PINGROUP(ph2, PWM2, TMDS, GMI, CLDVFS, GMI, 0x3218, N, N, N),
2943 PINGROUP(ph3, PWM3, SPI4, GMI, CLDVFS, GMI, 0x321c, N, N, N),
2944 PINGROUP(ph4, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x3220, N, N, N),
2945 PINGROUP(ph5, SDMMC2, RSVD2, GMI, RSVD4, GMI, 0x3224, N, N, N),
2946 PINGROUP(ph6, SDMMC2, TRACE, GMI, DTV, GMI, 0x3228, N, N, N),
2947 PINGROUP(ph7, SDMMC2, TRACE, GMI, DTV, GMI, 0x322c, N, N, N),
2948 PINGROUP(pj7, UARTD, RSVD2, GMI, GMI_ALT, RSVD2, 0x3230, N, N, N),
2949 PINGROUP(pb0, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x3234, N, N, N),
2950 PINGROUP(pb1, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x3238, N, N, N),
2951 PINGROUP(pk7, UARTD, RSVD2, GMI, RSVD4, RSVD2, 0x323c, N, N, N),
2952 PINGROUP(pi0, RSVD1, RSVD2, GMI, RSVD4, RSVD4, 0x3240, N, N, N),
2953 PINGROUP(pi1, RSVD1, RSVD2, GMI, RSVD4, RSVD1, 0x3244, N, N, N),
2954 PINGROUP(pi2, SDMMC2, TRACE, GMI, RSVD4, GMI, 0x3248, N, N, N),
2955 PINGROUP(pi4, SPI4, TRACE, GMI, DISPLAYA, GMI, 0x324c, N, N, N),
2956 PINGROUP(gen2_i2c_scl_pt5, I2C2, RSVD2, GMI, RSVD4, RSVD2, 0x3250, Y, N, N),
2957 PINGROUP(gen2_i2c_sda_pt6, I2C2, RSVD2, GMI, RSVD4, RSVD2, 0x3254, Y, N, N),
2958 PINGROUP(sdmmc4_clk_pcc4, SDMMC4, RSVD2, GMI, RSVD4, RSVD2, 0x3258, N, Y, N),
2959 PINGROUP(sdmmc4_cmd_pt7, SDMMC4, RSVD2, GMI, RSVD4, RSVD2, 0x325c, N, Y, N),
2960 PINGROUP(sdmmc4_dat0_paa0, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3260, N, Y, N),
2961 PINGROUP(sdmmc4_dat1_paa1, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3264, N, Y, N),
2962 PINGROUP(sdmmc4_dat2_paa2, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3268, N, Y, N),
2963 PINGROUP(sdmmc4_dat3_paa3, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x326c, N, Y, N),
2964 PINGROUP(sdmmc4_dat4_paa4, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3270, N, Y, N),
2965 PINGROUP(sdmmc4_dat5_paa5, SDMMC4, SPI3, RSVD3, RSVD4, SDMMC4, 0x3274, N, Y, N),
2966 PINGROUP(sdmmc4_dat6_paa6, SDMMC4, SPI3, GMI, RSVD4, SDMMC4, 0x3278, N, Y, N),
2967 PINGROUP(sdmmc4_dat7_paa7, SDMMC4, RSVD1, GMI, RSVD4, SDMMC4, 0x327c, N, Y, N),
2968 PINGROUP(cam_mclk_pcc0, VI, VI_ALT1, VI_ALT3, SDMMC2, VI, 0x3284, N, N, N),
2969 PINGROUP(pcc1, I2S4, RSVD1, RSVD3, SDMMC2, I2S4, 0x3288, N, N, N),
2970 PINGROUP(pbb0, VGP6, VIMCLK2, SDMMC2, VIMCLK2_ALT, VGP6, 0x328c, N, N, N),
2971 PINGROUP(cam_i2c_scl_pbb1, VGP1, I2C3, RSVD3, SDMMC2, VGP1, 0x3290, Y, N, N),
2972 PINGROUP(cam_i2c_sda_pbb2, VGP2, I2C3, RSVD3, SDMMC2, VGP2, 0x3294, Y, N, N),
2973 PINGROUP(pbb3, VGP3, DISPLAYA, DISPLAYB, SDMMC2, VGP3, 0x3298, N, N, N),
2974 PINGROUP(pbb4, VGP4, DISPLAYA, DISPLAYB, SDMMC2, VGP4, 0x329c, N, N, N),
2975 PINGROUP(pbb5, VGP5, DISPLAYA, RSVD3, SDMMC2, VGP5, 0x32a0, N, N, N),
2976 PINGROUP(pbb6, I2S4, RSVD2, DISPLAYB, SDMMC2, I2S4, 0x32a4, N, N, N),
2977 PINGROUP(pbb7, I2S4, RSVD2, RSVD3, SDMMC2, I2S4, 0x32a8, N, N, N),
2978 PINGROUP(pcc2, I2S4, RSVD2, SDMMC3, SDMMC2, I2S4, 0x32ac, N, N, N),
2979 PINGROUP(jtag_rtck, RTCK, RSVD2, RSVD3, RSVD4, RTCK, 0x32b0, N, N, N),
2980 PINGROUP(pwr_i2c_scl_pz6, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x32b4, Y, N, N),
2981 PINGROUP(pwr_i2c_sda_pz7, I2CPWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x32b8, Y, N, N),
2982 PINGROUP(kb_row0_pr0, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32bc, N, N, N),
2983 PINGROUP(kb_row1_pr1, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c0, N, N, N),
2984 PINGROUP(kb_row2_pr2, KBC, RSVD2, RSVD3, RSVD4, RSVD4, 0x32c4, N, N, N),
2985 PINGROUP(kb_row3_pr3, KBC, DISPLAYA, SYS, DISPLAYB, KBC, 0x32c8, N, N, N),
2986 PINGROUP(kb_row4_pr4, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32cc, N, N, N),
2987 PINGROUP(kb_row5_pr5, KBC, DISPLAYA, RSVD3, DISPLAYB, RSVD3, 0x32d0, N, N, N),
2988 PINGROUP(kb_row6_pr6, KBC, DISPLAYA, DISPLAYA_ALT, DISPLAYB, KBC, 0x32d4, N, N, N),
2989 PINGROUP(kb_row7_pr7, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32d8, N, N, N),
2990 PINGROUP(kb_row8_ps0, KBC, RSVD2, CLDVFS, UARTA, RSVD2, 0x32dc, N, N, N),
2991 PINGROUP(kb_row9_ps1, KBC, RSVD2, RSVD3, UARTA, KBC, 0x32e0, N, N, N),
2992 PINGROUP(kb_row10_ps2, KBC, RSVD2, RSVD3, UARTA, KBC, 0x32e4, N, N, N),
2993 PINGROUP(kb_row11_ps3, KBC, RSVD2, RSVD3, IRDA, RSVD3, 0x32e8, N, N, N),
2994 PINGROUP(kb_row12_ps4, KBC, RSVD2, RSVD3, IRDA, RSVD3, 0x32ec, N, N, N),
2995 PINGROUP(kb_row13_ps5, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32f0, N, N, N),
2996 PINGROUP(kb_row14_ps6, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32f4, N, N, N),
2997 PINGROUP(kb_row15_ps7, KBC, SOC, RSVD3, RSVD4, KBC, 0x32f8, N, N, N),
2998 PINGROUP(kb_col0_pq0, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x32fc, N, N, N),
2999 PINGROUP(kb_col1_pq1, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3300, N, N, N),
3000 PINGROUP(kb_col2_pq2, KBC, RSVD2, SPI2, RSVD4, RSVD4, 0x3304, N, N, N),
3001 PINGROUP(kb_col3_pq3, KBC, DISPLAYA, PWM2, UARTA, KBC, 0x3308, N, N, N),
3002 PINGROUP(kb_col4_pq4, KBC, OWR, SDMMC3, UARTA, KBC, 0x330c, N, N, N),
3003 PINGROUP(kb_col5_pq5, KBC, RSVD2, SDMMC3, RSVD4, RSVD4, 0x3310, N, N, N),
3004 PINGROUP(kb_col6_pq6, KBC, RSVD2, SPI2, UARTD, RSVD2, 0x3314, N, N, N),
3005 PINGROUP(kb_col7_pq7, KBC, RSVD2, SPI2, UARTD, RSVD2, 0x3318, N, N, N),
3006 PINGROUP(clk_32k_out_pa0, BLINK, SOC, RSVD3, RSVD4, RSVD3, 0x331c, N, N, N),
3007 PINGROUP(core_pwr_req, PWRON, RSVD2, RSVD3, RSVD4, RSVD2, 0x3324, N, N, N),
3008 PINGROUP(cpu_pwr_req, CPU, RSVD2, RSVD3, RSVD4, RSVD2, 0x3328, N, N, N),
3009 PINGROUP(pwr_int_n, PMI, RSVD2, RSVD3, RSVD4, RSVD2, 0x332c, N, N, N),
3010 PINGROUP(clk_32k_in, CLK, RSVD2, RSVD3, RSVD4, RSVD2, 0x3330, N, N, N),
3011 PINGROUP(owr, OWR, RSVD2, RSVD3, RSVD4, RSVD2, 0x3334, N, N, Y),
3012 PINGROUP(dap1_fs_pn0, I2S0, HDA, GMI, RSVD4, RSVD4, 0x3338, N, N, N),
3013 PINGROUP(dap1_din_pn1, I2S0, HDA, GMI, RSVD4, RSVD4, 0x333c, N, N, N),
3014 PINGROUP(dap1_dout_pn2, I2S0, HDA, GMI, SATA, I2S0, 0x3340, N, N, N),
3015 PINGROUP(dap1_sclk_pn3, I2S0, HDA, GMI, RSVD4, I2S0, 0x3344, N, N, N),
3016 PINGROUP(dap_mclk1_req_pee2, DAP, DAP1, SATA, RSVD4, DAP, 0x3348, N, N, N),
3017 PINGROUP(dap_mclk1_pw4, EXTPERIPH1, DAP2, RSVD3, RSVD4, RSVD3, 0x334c, N, N, N),
3018 PINGROUP(spdif_in_pk6, SPDIF, RSVD2, RSVD3, I2C3, RSVD3, 0x3350, N, N, N),
3019 PINGROUP(spdif_out_pk5, SPDIF, RSVD2, RSVD3, I2C3, RSVD3, 0x3354, N, N, N),
3020 PINGROUP(dap2_fs_pa2, I2S1, HDA, GMI, RSVD4, I2S1, 0x3358, N, N, N),
3021 PINGROUP(dap2_din_pa4, I2S1, HDA, GMI, RSVD4, I2S1, 0x335c, N, N, N),
3022 PINGROUP(dap2_dout_pa5, I2S1, HDA, GMI, RSVD4, I2S1, 0x3360, N, N, N),
3023 PINGROUP(dap2_sclk_pa3, I2S1, HDA, GMI, RSVD4, I2S1, 0x3364, N, N, N),
3024 PINGROUP(dvfs_pwm_px0, SPI6, CLDVFS, GMI, RSVD4, SPI6, 0x3368, N, N, N),
3025 PINGROUP(gpio_x1_aud_px1, SPI6, RSVD2, GMI, RSVD4, SPI6, 0x336c, N, N, N),
3026 PINGROUP(gpio_x3_aud_px3, SPI6, SPI1, GMI, RSVD4, SPI6, 0x3370, N, N, N),
3027 PINGROUP(dvfs_clk_px2, SPI6, CLDVFS, GMI, RSVD4, SPI6, 0x3374, N, N, N),
3028 PINGROUP(gpio_x4_aud_px4, GMI, SPI1, SPI2, DAP2, SPI1, 0x3378, N, N, N),
3029 PINGROUP(gpio_x5_aud_px5, GMI, SPI1, SPI2, RSVD4, SPI1, 0x337c, N, N, N),
3030 PINGROUP(gpio_x6_aud_px6, SPI6, SPI1, SPI2, GMI, SPI1, 0x3380, N, N, N),
3031 PINGROUP(gpio_x7_aud_px7, RSVD1, SPI1, SPI2, RSVD4, SPI1, 0x3384, N, N, N),
3032 PINGROUP(sdmmc3_clk_pa6, SDMMC3, RSVD2, RSVD3, SPI3, SDMMC3, 0x3390, N, N, N),
3033 PINGROUP(sdmmc3_cmd_pa7, SDMMC3, PWM3, UARTA, SPI3, SDMMC3, 0x3394, N, N, N),
3034 PINGROUP(sdmmc3_dat0_pb7, SDMMC3, RSVD2, RSVD3, SPI3, SDMMC3, 0x3398, N, N, N),
3035 PINGROUP(sdmmc3_dat1_pb6, SDMMC3, PWM2, UARTA, SPI3, SDMMC3, 0x339c, N, N, N),
3036 PINGROUP(sdmmc3_dat2_pb5, SDMMC3, PWM1, DISPLAYA, SPI3, SDMMC3, 0x33a0, N, N, N),
3037 PINGROUP(sdmmc3_dat3_pb4, SDMMC3, PWM0, DISPLAYB, SPI3, SDMMC3, 0x33a4, N, N, N),
3038 PINGROUP(pex_l0_rst_n_pdd1, PE0, RSVD2, RSVD3, RSVD4, PE0, 0x33bc, N, N, N),
3039 PINGROUP(pex_l0_clkreq_n_pdd2, PE0, RSVD2, RSVD3, RSVD4, PE0, 0x33c0, N, N, N),
3040 PINGROUP(pex_wake_n_pdd3, PE, RSVD2, RSVD3, RSVD4, PE, 0x33c4, N, N, N),
3041 PINGROUP(pex_l1_rst_n_pdd5, PE1, RSVD2, RSVD3, RSVD4, PE1, 0x33cc, N, N, N),
3042 PINGROUP(pex_l1_clkreq_n_pdd6, PE1, RSVD2, RSVD3, RSVD4, PE1, 0x33d0, N, N, N),
3043 PINGROUP(hdmi_cec_pee3, CEC, RSVD2, RSVD3, RSVD4, CEC, 0x33e0, Y, N, N),
3044 PINGROUP(sdmmc1_wp_n_pv3, SDMMC1, CLK12, SPI4, UARTA, SDMMC1, 0x33e4, N, N, N),
3045 PINGROUP(sdmmc3_cd_n_pv2, SDMMC3, OWR, RSVD3, RSVD4, SDMMC3, 0x33e8, N, N, N),
3046 PINGROUP(gpio_w2_aud_pw2, SPI6, RSVD2, SPI2, I2C1, RSVD2, 0x33ec, N, N, N),
3047 PINGROUP(gpio_w3_aud_pw3, SPI6, SPI1, SPI2, I2C1, SPI1, 0x33f0, N, N, N),
3048 PINGROUP(usb_vbus_en0_pn4, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f4, Y, N, N),
3049 PINGROUP(usb_vbus_en1_pn5, USB, RSVD2, RSVD3, RSVD4, USB, 0x33f8, Y, N, N),
3050 PINGROUP(sdmmc3_clk_lb_out_pee4, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x33fc, N, N, N),
3051 PINGROUP(sdmmc3_clk_lb_in_pee5, SDMMC3, RSVD2, RSVD3, RSVD4, SDMMC3, 0x3400, N, N, N),
3052 PINGROUP(gmi_clk_lb, SDMMC2, RSVD2, GMI, RSVD4, SDMMC2, 0x3404, N, N, N),
3053 PINGROUP(reset_out_n, RSVD1, RSVD2, RSVD3, RESET_OUT_N, RSVD1, 0x3408, N, N, N),
3054 PINGROUP(kb_row16_pt0, KBC, RSVD2, RSVD3, UARTC, KBC, 0x340c, N, N, N),
3055 PINGROUP(kb_row17_pt1, KBC, RSVD2, RSVD3, UARTC, KBC, 0x3410, N, N, N),
3056 PINGROUP(usb_vbus_en2_pff1, USB, RSVD2, RSVD3, RSVD4, USB, 0x3414, Y, N, N),
3057 PINGROUP(pff2, SATA, RSVD2, RSVD3, RSVD4, RSVD2, 0x3418, Y, N, N),
3058 PINGROUP(dp_hpd_pff0, DP, RSVD2, RSVD3, RSVD4, DP, 0x3430, N, N, N),
3059
3060 /* pg_name, r, hsm_b, schmitt_b, lpmd_b, drvdn_b, drvdn_w, drvup_b, drvup_w, slwr_b, slwr_w, slwf_b, slwf_w, drvtype */
3061 DRV_PINGROUP(ao1, 0x868, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3062 DRV_PINGROUP(ao2, 0x86c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3063 DRV_PINGROUP(at1, 0x870, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3064 DRV_PINGROUP(at2, 0x874, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3065 DRV_PINGROUP(at3, 0x878, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3066 DRV_PINGROUP(at4, 0x87c, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3067 DRV_PINGROUP(at5, 0x880, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3068 DRV_PINGROUP(cdev1, 0x884, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3069 DRV_PINGROUP(cdev2, 0x888, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3070 DRV_PINGROUP(dap1, 0x890, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3071 DRV_PINGROUP(dap2, 0x894, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3072 DRV_PINGROUP(dap3, 0x898, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3073 DRV_PINGROUP(dap4, 0x89c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3074 DRV_PINGROUP(dbg, 0x8a0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3075 DRV_PINGROUP(sdio3, 0x8b0, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
3076 DRV_PINGROUP(spi, 0x8b4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3077 DRV_PINGROUP(uaa, 0x8b8, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3078 DRV_PINGROUP(uab, 0x8bc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3079 DRV_PINGROUP(uart2, 0x8c0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3080 DRV_PINGROUP(uart3, 0x8c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3081 DRV_PINGROUP(sdio1, 0x8ec, 2, 3, -1, 12, 7, 20, 7, 28, 2, 30, 2, N),
3082 DRV_PINGROUP(ddc, 0x8fc, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3083 DRV_PINGROUP(gma, 0x900, 2, 3, 4, 14, 5, 20, 5, 28, 2, 30, 2, Y),
3084 DRV_PINGROUP(gme, 0x910, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3085 DRV_PINGROUP(gmf, 0x914, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3086 DRV_PINGROUP(gmg, 0x918, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3087 DRV_PINGROUP(gmh, 0x91c, 2, 3, 4, 14, 5, 19, 5, 28, 2, 30, 2, N),
3088 DRV_PINGROUP(owr, 0x920, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3089 DRV_PINGROUP(uda, 0x924, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3090 DRV_PINGROUP(gpv, 0x928, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3091 DRV_PINGROUP(dev3, 0x92c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3092 DRV_PINGROUP(cec, 0x938, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3093 DRV_PINGROUP(at6, 0x994, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3094 DRV_PINGROUP(dap5, 0x998, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3095 DRV_PINGROUP(usb_vbus_en, 0x99c, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3096 DRV_PINGROUP(ao3, 0x9a8, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
3097 DRV_PINGROUP(ao0, 0x9b0, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3098 DRV_PINGROUP(hv0, 0x9b4, 2, 3, 4, 12, 5, -1, -1, 28, 2, -1, -1, N),
3099 DRV_PINGROUP(sdio4, 0x9c4, 2, 3, 4, 12, 5, 20, 5, 28, 2, 30, 2, N),
3100 DRV_PINGROUP(ao4, 0x9c8, 2, 3, 4, 12, 7, 20, 7, 28, 2, 30, 2, Y),
3101};
3102
3103static const struct tegra_pinctrl_soc_data tegra124_pinctrl = {
3104 .ngpios = NUM_GPIOS,
3105 .pins = tegra124_pins,
3106 .npins = ARRAY_SIZE(tegra124_pins),
3107 .functions = tegra124_functions,
3108 .nfunctions = ARRAY_SIZE(tegra124_functions),
3109 .groups = tegra124_groups,
3110 .ngroups = ARRAY_SIZE(tegra124_groups),
3111};
3112
3113static int tegra124_pinctrl_probe(struct platform_device *pdev)
3114{
3115 return tegra_pinctrl_probe(pdev, &tegra124_pinctrl);
3116}
3117
3118static struct of_device_id tegra124_pinctrl_of_match[] = {
3119 { .compatible = "nvidia,tegra124-pinmux", },
3120 { },
3121};
3122MODULE_DEVICE_TABLE(of, tegra124_pinctrl_of_match);
3123
3124static struct platform_driver tegra124_pinctrl_driver = {
3125 .driver = {
3126 .name = "tegra124-pinctrl",
3127 .owner = THIS_MODULE,
3128 .of_match_table = tegra124_pinctrl_of_match,
3129 },
3130 .probe = tegra124_pinctrl_probe,
3131 .remove = tegra_pinctrl_remove,
3132};
3133module_platform_driver(tegra124_pinctrl_driver);
3134
3135MODULE_AUTHOR("Ashwini Ghuge <aghuge@nvidia.com>");
3136MODULE_DESCRIPTION("NVIDIA Tegra124 pinctrl driver");
3137MODULE_LICENSE("GPL v2");
diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
index ed2d1ba69cef..e66f4cae7633 100644
--- a/drivers/pinctrl/pinctrl-xway.c
+++ b/drivers/pinctrl/pinctrl-xway.c
@@ -332,10 +332,10 @@ static const struct ltq_pin_group xway_grps[] = {
332 GRP_MUX("mdio", MDIO, pins_mdio), 332 GRP_MUX("mdio", MDIO, pins_mdio),
333 GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0), 333 GRP_MUX("gphy0 led0", GPHY, pins_gphy0_led0),
334 GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1), 334 GRP_MUX("gphy0 led1", GPHY, pins_gphy0_led1),
335 GRP_MUX("gphy0 lde2", GPHY, pins_gphy0_led2), 335 GRP_MUX("gphy0 led2", GPHY, pins_gphy0_led2),
336 GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0), 336 GRP_MUX("gphy1 led0", GPHY, pins_gphy1_led0),
337 GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1), 337 GRP_MUX("gphy1 led1", GPHY, pins_gphy1_led1),
338 GRP_MUX("gphy1 lde2", GPHY, pins_gphy1_led2), 338 GRP_MUX("gphy1 led2", GPHY, pins_gphy1_led2),
339}; 339};
340 340
341static const struct ltq_pin_group ase_grps[] = { 341static const struct ltq_pin_group ase_grps[] = {
diff --git a/drivers/pinctrl/sh-pfc/core.c b/drivers/pinctrl/sh-pfc/core.c
index d77ece5217f0..b9b464d0578c 100644
--- a/drivers/pinctrl/sh-pfc/core.c
+++ b/drivers/pinctrl/sh-pfc/core.c
@@ -26,29 +26,67 @@
26 26
27#include "core.h" 27#include "core.h"
28 28
29static int sh_pfc_ioremap(struct sh_pfc *pfc, struct platform_device *pdev) 29static int sh_pfc_map_resources(struct sh_pfc *pfc,
30 struct platform_device *pdev)
30{ 31{
32 unsigned int num_windows = 0;
33 unsigned int num_irqs = 0;
34 struct sh_pfc_window *windows;
35 unsigned int *irqs = NULL;
31 struct resource *res; 36 struct resource *res;
32 int k; 37 unsigned int i;
38
39 /* Count the MEM and IRQ resources. */
40 for (i = 0; i < pdev->num_resources; ++i) {
41 switch (resource_type(&pdev->resource[i])) {
42 case IORESOURCE_MEM:
43 num_windows++;
44 break;
45
46 case IORESOURCE_IRQ:
47 num_irqs++;
48 break;
49 }
50 }
33 51
34 if (pdev->num_resources == 0) 52 if (num_windows == 0)
35 return -EINVAL; 53 return -EINVAL;
36 54
37 pfc->window = devm_kzalloc(pfc->dev, pdev->num_resources * 55 /* Allocate memory windows and IRQs arrays. */
38 sizeof(*pfc->window), GFP_NOWAIT); 56 windows = devm_kzalloc(pfc->dev, num_windows * sizeof(*windows),
39 if (!pfc->window) 57 GFP_KERNEL);
58 if (windows == NULL)
40 return -ENOMEM; 59 return -ENOMEM;
41 60
42 pfc->num_windows = pdev->num_resources; 61 pfc->num_windows = num_windows;
62 pfc->windows = windows;
43 63
44 for (k = 0, res = pdev->resource; k < pdev->num_resources; k++, res++) { 64 if (num_irqs) {
45 WARN_ON(resource_type(res) != IORESOURCE_MEM); 65 irqs = devm_kzalloc(pfc->dev, num_irqs * sizeof(*irqs),
46 pfc->window[k].phys = res->start; 66 GFP_KERNEL);
47 pfc->window[k].size = resource_size(res); 67 if (irqs == NULL)
48 pfc->window[k].virt = devm_ioremap_nocache(pfc->dev, res->start,
49 resource_size(res));
50 if (!pfc->window[k].virt)
51 return -ENOMEM; 68 return -ENOMEM;
69
70 pfc->num_irqs = num_irqs;
71 pfc->irqs = irqs;
72 }
73
74 /* Fill them. */
75 for (i = 0, res = pdev->resource; i < pdev->num_resources; i++, res++) {
76 switch (resource_type(res)) {
77 case IORESOURCE_MEM:
78 windows->phys = res->start;
79 windows->size = resource_size(res);
80 windows->virt = devm_ioremap_resource(pfc->dev, res);
81 if (IS_ERR(windows->virt))
82 return -ENOMEM;
83 windows++;
84 break;
85
86 case IORESOURCE_IRQ:
87 *irqs++ = res->start;
88 break;
89 }
52 } 90 }
53 91
54 return 0; 92 return 0;
@@ -62,7 +100,7 @@ static void __iomem *sh_pfc_phys_to_virt(struct sh_pfc *pfc,
62 100
63 /* scan through physical windows and convert address */ 101 /* scan through physical windows and convert address */
64 for (i = 0; i < pfc->num_windows; i++) { 102 for (i = 0; i < pfc->num_windows; i++) {
65 window = pfc->window + i; 103 window = pfc->windows + i;
66 104
67 if (address < window->phys) 105 if (address < window->phys)
68 continue; 106 continue;
@@ -147,7 +185,7 @@ static void sh_pfc_config_reg_helper(struct sh_pfc *pfc,
147 unsigned long *maskp, 185 unsigned long *maskp,
148 unsigned long *posp) 186 unsigned long *posp)
149{ 187{
150 int k; 188 unsigned int k;
151 189
152 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg); 190 *mapped_regp = sh_pfc_phys_to_virt(pfc, crp->reg);
153 191
@@ -196,7 +234,7 @@ static int sh_pfc_get_config_reg(struct sh_pfc *pfc, u16 enum_id,
196{ 234{
197 const struct pinmux_cfg_reg *config_reg; 235 const struct pinmux_cfg_reg *config_reg;
198 unsigned long r_width, f_width, curr_width, ncomb; 236 unsigned long r_width, f_width, curr_width, ncomb;
199 int k, m, n, pos, bit_pos; 237 unsigned int k, m, n, pos, bit_pos;
200 238
201 k = 0; 239 k = 0;
202 while (1) { 240 while (1) {
@@ -238,7 +276,7 @@ static int sh_pfc_mark_to_enum(struct sh_pfc *pfc, u16 mark, int pos,
238 u16 *enum_idp) 276 u16 *enum_idp)
239{ 277{
240 const u16 *data = pfc->info->gpio_data; 278 const u16 *data = pfc->info->gpio_data;
241 int k; 279 unsigned int k;
242 280
243 if (pos) { 281 if (pos) {
244 *enum_idp = data[pos + 1]; 282 *enum_idp = data[pos + 1];
@@ -481,7 +519,7 @@ static int sh_pfc_probe(struct platform_device *pdev)
481 pfc->info = info; 519 pfc->info = info;
482 pfc->dev = &pdev->dev; 520 pfc->dev = &pdev->dev;
483 521
484 ret = sh_pfc_ioremap(pfc, pdev); 522 ret = sh_pfc_map_resources(pfc, pdev);
485 if (unlikely(ret < 0)) 523 if (unlikely(ret < 0))
486 return ret; 524 return ret;
487 525
diff --git a/drivers/pinctrl/sh-pfc/core.h b/drivers/pinctrl/sh-pfc/core.h
index 11ea87268658..b7b0e6ccf305 100644
--- a/drivers/pinctrl/sh-pfc/core.h
+++ b/drivers/pinctrl/sh-pfc/core.h
@@ -37,7 +37,9 @@ struct sh_pfc {
37 spinlock_t lock; 37 spinlock_t lock;
38 38
39 unsigned int num_windows; 39 unsigned int num_windows;
40 struct sh_pfc_window *window; 40 struct sh_pfc_window *windows;
41 unsigned int num_irqs;
42 unsigned int *irqs;
41 43
42 struct sh_pfc_pin_range *ranges; 44 struct sh_pfc_pin_range *ranges;
43 unsigned int nr_ranges; 45 unsigned int nr_ranges;
diff --git a/drivers/pinctrl/sh-pfc/gpio.c b/drivers/pinctrl/sh-pfc/gpio.c
index 04bf52b64fb3..a9288ab01f7b 100644
--- a/drivers/pinctrl/sh-pfc/gpio.c
+++ b/drivers/pinctrl/sh-pfc/gpio.c
@@ -204,18 +204,24 @@ static void gpio_pin_set(struct gpio_chip *gc, unsigned offset, int value)
204static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset) 204static int gpio_pin_to_irq(struct gpio_chip *gc, unsigned offset)
205{ 205{
206 struct sh_pfc *pfc = gpio_to_pfc(gc); 206 struct sh_pfc *pfc = gpio_to_pfc(gc);
207 int i, k; 207 unsigned int i, k;
208 208
209 for (i = 0; i < pfc->info->gpio_irq_size; i++) { 209 for (i = 0; i < pfc->info->gpio_irq_size; i++) {
210 unsigned short *gpios = pfc->info->gpio_irq[i].gpios; 210 const short *gpios = pfc->info->gpio_irq[i].gpios;
211 211
212 for (k = 0; gpios[k]; k++) { 212 for (k = 0; gpios[k] >= 0; k++) {
213 if (gpios[k] == offset) 213 if (gpios[k] == offset)
214 return pfc->info->gpio_irq[i].irq; 214 goto found;
215 } 215 }
216 } 216 }
217 217
218 return -ENOSYS; 218 return -ENOSYS;
219
220found:
221 if (pfc->num_irqs)
222 return pfc->irqs[i];
223 else
224 return pfc->info->gpio_irq[i].irq;
219} 225}
220 226
221static int gpio_pin_setup(struct sh_pfc_chip *chip) 227static int gpio_pin_setup(struct sh_pfc_chip *chip)
@@ -347,7 +353,7 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
347 * GPIOs. 353 * GPIOs.
348 */ 354 */
349 for (i = 0; i < pfc->num_windows; ++i) { 355 for (i = 0; i < pfc->num_windows; ++i) {
350 struct sh_pfc_window *window = &pfc->window[i]; 356 struct sh_pfc_window *window = &pfc->windows[i];
351 357
352 if (pfc->info->data_regs[0].reg >= window->phys && 358 if (pfc->info->data_regs[0].reg >= window->phys &&
353 pfc->info->data_regs[0].reg < window->phys + window->size) 359 pfc->info->data_regs[0].reg < window->phys + window->size)
@@ -357,8 +363,14 @@ int sh_pfc_register_gpiochip(struct sh_pfc *pfc)
357 if (i == pfc->num_windows) 363 if (i == pfc->num_windows)
358 return 0; 364 return 0;
359 365
366 /* If we have IRQ resources make sure their number is correct. */
367 if (pfc->num_irqs && pfc->num_irqs != pfc->info->gpio_irq_size) {
368 dev_err(pfc->dev, "invalid number of IRQ resources\n");
369 return -EINVAL;
370 }
371
360 /* Register the real GPIOs chip. */ 372 /* Register the real GPIOs chip. */
361 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->window[i]); 373 chip = sh_pfc_add_gpiochip(pfc, gpio_pin_setup, &pfc->windows[i]);
362 if (IS_ERR(chip)) 374 if (IS_ERR(chip))
363 return PTR_ERR(chip); 375 return PTR_ERR(chip);
364 376
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index d25fd4ea0a1d..d39ca87353e4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1272,7 +1272,7 @@ static const u16 pinmux_data[] = {
1272#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) 1272#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1273#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) 1273#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1274 1274
1275static struct sh_pfc_pin pinmux_pins[] = { 1275static const struct sh_pfc_pin pinmux_pins[] = {
1276 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1), 1276 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1277 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3), 1277 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1278 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5), 1278 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
@@ -2061,17 +2061,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
2061 SH_PFC_FUNCTION(sdhi2), 2061 SH_PFC_FUNCTION(sdhi2),
2062}; 2062};
2063 2063
2064#undef PORTCR
2065#define PORTCR(nr, reg) \
2066 { \
2067 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2068 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2069 PORT##nr##_FN0, PORT##nr##_FN1, \
2070 PORT##nr##_FN2, PORT##nr##_FN3, \
2071 PORT##nr##_FN4, PORT##nr##_FN5, \
2072 PORT##nr##_FN6, PORT##nr##_FN7 } \
2073 }
2074
2075static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2064static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2076 PORTCR(0, 0xe6050000), 2065 PORTCR(0, 0xe6050000),
2077 PORTCR(1, 0xe6050001), 2066 PORTCR(1, 0xe6050001),
@@ -2691,7 +2680,7 @@ static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2691{ 2680{
2692 void __iomem *addr; 2681 void __iomem *addr;
2693 2682
2694 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; 2683 addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2695 2684
2696 switch (ioread8(addr) & PORTCR_PULMD_MASK) { 2685 switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2697 case PORTCR_PULMD_UP: 2686 case PORTCR_PULMD_UP:
@@ -2710,7 +2699,7 @@ static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2710 void __iomem *addr; 2699 void __iomem *addr;
2711 u32 value; 2700 u32 value;
2712 2701
2713 addr = pfc->window->virt + r8a73a4_portcr_offsets[pin >> 5] + pin; 2702 addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2714 value = ioread8(addr) & ~PORTCR_PULMD_MASK; 2703 value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2715 2704
2716 switch (bias) { 2705 switch (bias) {
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index bc5eb453a45c..6c83ce43a940 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1543,7 +1543,7 @@ static const u16 pinmux_data[] = {
1543#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) 1543#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1544#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) 1544#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
1545 1545
1546static struct sh_pfc_pin pinmux_pins[] = { 1546static const struct sh_pfc_pin pinmux_pins[] = {
1547 /* Table 56-1 (I/O and Pull U/D) */ 1547 /* Table 56-1 (I/O and Pull U/D) */
1548 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1), 1548 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1549 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3), 1549 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
@@ -3234,17 +3234,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
3234 SH_PFC_FUNCTION(tpu0), 3234 SH_PFC_FUNCTION(tpu0),
3235}; 3235};
3236 3236
3237#undef PORTCR
3238#define PORTCR(nr, reg) \
3239 { \
3240 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3241 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3242 PORT##nr##_FN0, PORT##nr##_FN1, \
3243 PORT##nr##_FN2, PORT##nr##_FN3, \
3244 PORT##nr##_FN4, PORT##nr##_FN5, \
3245 PORT##nr##_FN6, PORT##nr##_FN7 } \
3246 }
3247
3248static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3237static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3249 PORTCR(0, 0xe6050000), /* PORT0CR */ 3238 PORTCR(0, 0xe6050000), /* PORT0CR */
3250 PORTCR(1, 0xe6050001), /* PORT1CR */ 3239 PORTCR(1, 0xe6050001), /* PORT1CR */
@@ -3721,7 +3710,7 @@ static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3721 &r8a7740_portcr_offsets[i]; 3710 &r8a7740_portcr_offsets[i];
3722 3711
3723 if (pin <= group->end_pin) 3712 if (pin <= group->end_pin)
3724 return pfc->window->virt + group->offset + pin; 3713 return pfc->windows->virt + group->offset + pin;
3725 } 3714 }
3726 3715
3727 return NULL; 3716 return NULL;
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 8b1881c20598..c7d610d1f3ef 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1260,7 +1260,7 @@ static const u16 pinmux_data[] = {
1260 */ 1260 */
1261#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) 1261#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
1262 1262
1263static struct sh_pfc_pin pinmux_pins[] = { 1263static const struct sh_pfc_pin pinmux_pins[] = {
1264 PINMUX_GPIO_GP_ALL(), 1264 PINMUX_GPIO_GP_ALL(),
1265 1265
1266 /* Pins not associated with a GPIO port */ 1266 /* Pins not associated with a GPIO port */
@@ -2104,7 +2104,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
2104 SH_PFC_FUNCTION(vin1), 2104 SH_PFC_FUNCTION(vin1),
2105}; 2105};
2106 2106
2107static struct pinmux_cfg_reg pinmux_config_regs[] = { 2107static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2108 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { 2108 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
2109 GP_0_31_FN, FN_IP1_14_11, 2109 GP_0_31_FN, FN_IP1_14_11,
2110 GP_0_30_FN, FN_IP1_10_8, 2110 GP_0_30_FN, FN_IP1_10_8,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index d3e94e307d7f..f5c01e1e2615 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1410,7 +1410,7 @@ static const u16 pinmux_data[] = {
1410 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), 1410 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1411}; 1411};
1412 1412
1413static struct sh_pfc_pin pinmux_pins[] = { 1413static const struct sh_pfc_pin pinmux_pins[] = {
1414 PINMUX_GPIO_GP_ALL(), 1414 PINMUX_GPIO_GP_ALL(),
1415}; 1415};
1416 1416
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 72786fc93958..c381ae63c508 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1731,7 +1731,7 @@ static const u16 pinmux_data[] = {
1731#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) 1731#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1732#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1732#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1733 1733
1734static struct sh_pfc_pin pinmux_pins[] = { 1734static const struct sh_pfc_pin pinmux_pins[] = {
1735 PINMUX_GPIO_GP_ALL(), 1735 PINMUX_GPIO_GP_ALL(),
1736 1736
1737 /* Pins not associated with a GPIO port */ 1737 /* Pins not associated with a GPIO port */
@@ -1739,6 +1739,56 @@ static struct sh_pfc_pin pinmux_pins[] = {
1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15), 1739 SH_PFC_PIN_NAMED(ROW_GROUP_A('H'), 15, AH15),
1740}; 1740};
1741 1741
1742/* - AUDIO CLOCK ------------------------------------------------------------ */
1743static const unsigned int audio_clk_a_pins[] = {
1744 /* CLK A */
1745 RCAR_GP_PIN(4, 25),
1746};
1747static const unsigned int audio_clk_a_mux[] = {
1748 AUDIO_CLKA_MARK,
1749};
1750static const unsigned int audio_clk_b_pins[] = {
1751 /* CLK B */
1752 RCAR_GP_PIN(4, 26),
1753};
1754static const unsigned int audio_clk_b_mux[] = {
1755 AUDIO_CLKB_MARK,
1756};
1757static const unsigned int audio_clk_c_pins[] = {
1758 /* CLK C */
1759 RCAR_GP_PIN(5, 27),
1760};
1761static const unsigned int audio_clk_c_mux[] = {
1762 AUDIO_CLKC_MARK,
1763};
1764static const unsigned int audio_clkout_pins[] = {
1765 /* CLK OUT */
1766 RCAR_GP_PIN(5, 16),
1767};
1768static const unsigned int audio_clkout_mux[] = {
1769 AUDIO_CLKOUT_MARK,
1770};
1771static const unsigned int audio_clkout_b_pins[] = {
1772 /* CLK OUT B */
1773 RCAR_GP_PIN(0, 23),
1774};
1775static const unsigned int audio_clkout_b_mux[] = {
1776 AUDIO_CLKOUT_B_MARK,
1777};
1778static const unsigned int audio_clkout_c_pins[] = {
1779 /* CLK OUT C */
1780 RCAR_GP_PIN(5, 27),
1781};
1782static const unsigned int audio_clkout_c_mux[] = {
1783 AUDIO_CLKOUT_C_MARK,
1784};
1785static const unsigned int audio_clkout_d_pins[] = {
1786 /* CLK OUT D */
1787 RCAR_GP_PIN(5, 20),
1788};
1789static const unsigned int audio_clkout_d_mux[] = {
1790 AUDIO_CLKOUT_D_MARK,
1791};
1742/* - DU RGB ----------------------------------------------------------------- */ 1792/* - DU RGB ----------------------------------------------------------------- */
1743static const unsigned int du_rgb666_pins[] = { 1793static const unsigned int du_rgb666_pins[] = {
1744 /* R[7:2], G[7:2], B[7:2] */ 1794 /* R[7:2], G[7:2], B[7:2] */
@@ -2961,6 +3011,189 @@ static const unsigned int sdhi3_wp_pins[] = {
2961static const unsigned int sdhi3_wp_mux[] = { 3011static const unsigned int sdhi3_wp_mux[] = {
2962 SD3_WP_MARK, 3012 SD3_WP_MARK,
2963}; 3013};
3014/* - SSI -------------------------------------------------------------------- */
3015static const unsigned int ssi0_data_pins[] = {
3016 /* SDATA0 */
3017 RCAR_GP_PIN(4, 5),
3018};
3019static const unsigned int ssi0_data_mux[] = {
3020 SSI_SDATA0_MARK,
3021};
3022static const unsigned int ssi0129_ctrl_pins[] = {
3023 /* SCK, WS */
3024 RCAR_GP_PIN(4, 3), RCAR_GP_PIN(4, 4),
3025};
3026static const unsigned int ssi0129_ctrl_mux[] = {
3027 SSI_SCK0129_MARK, SSI_WS0129_MARK,
3028};
3029static const unsigned int ssi1_data_pins[] = {
3030 /* SDATA1 */
3031 RCAR_GP_PIN(4, 6),
3032};
3033static const unsigned int ssi1_data_mux[] = {
3034 SSI_SDATA1_MARK,
3035};
3036static const unsigned int ssi1_ctrl_pins[] = {
3037 /* SCK, WS */
3038 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 24),
3039};
3040static const unsigned int ssi1_ctrl_mux[] = {
3041 SSI_SCK1_MARK, SSI_WS1_MARK,
3042};
3043static const unsigned int ssi2_data_pins[] = {
3044 /* SDATA2 */
3045 RCAR_GP_PIN(4, 7),
3046};
3047static const unsigned int ssi2_data_mux[] = {
3048 SSI_SDATA2_MARK,
3049};
3050static const unsigned int ssi2_ctrl_pins[] = {
3051 /* SCK, WS */
3052 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 17),
3053};
3054static const unsigned int ssi2_ctrl_mux[] = {
3055 SSI_SCK2_MARK, SSI_WS2_MARK,
3056};
3057static const unsigned int ssi3_data_pins[] = {
3058 /* SDATA3 */
3059 RCAR_GP_PIN(4, 10),
3060};
3061static const unsigned int ssi3_data_mux[] = {
3062 SSI_SDATA3_MARK
3063};
3064static const unsigned int ssi34_ctrl_pins[] = {
3065 /* SCK, WS */
3066 RCAR_GP_PIN(4, 8), RCAR_GP_PIN(4, 9),
3067};
3068static const unsigned int ssi34_ctrl_mux[] = {
3069 SSI_SCK34_MARK, SSI_WS34_MARK,
3070};
3071static const unsigned int ssi4_data_pins[] = {
3072 /* SDATA4 */
3073 RCAR_GP_PIN(4, 13),
3074};
3075static const unsigned int ssi4_data_mux[] = {
3076 SSI_SDATA4_MARK,
3077};
3078static const unsigned int ssi4_ctrl_pins[] = {
3079 /* SCK, WS */
3080 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3081};
3082static const unsigned int ssi4_ctrl_mux[] = {
3083 SSI_SCK4_MARK, SSI_WS4_MARK,
3084};
3085static const unsigned int ssi5_pins[] = {
3086 /* SDATA5, SCK, WS */
3087 RCAR_GP_PIN(4, 16), RCAR_GP_PIN(4, 14), RCAR_GP_PIN(4, 15),
3088};
3089static const unsigned int ssi5_mux[] = {
3090 SSI_SDATA5_MARK, SSI_SCK5_MARK, SSI_WS5_MARK,
3091};
3092static const unsigned int ssi5_b_pins[] = {
3093 /* SDATA5, SCK, WS */
3094 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3095};
3096static const unsigned int ssi5_b_mux[] = {
3097 SSI_SDATA5_B_MARK, SSI_SCK5_B_MARK, SSI_WS5_B_MARK
3098};
3099static const unsigned int ssi5_c_pins[] = {
3100 /* SDATA5, SCK, WS */
3101 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
3102};
3103static const unsigned int ssi5_c_mux[] = {
3104 SSI_SDATA5_C_MARK, SSI_SCK5_C_MARK, SSI_WS5_C_MARK,
3105};
3106static const unsigned int ssi6_pins[] = {
3107 /* SDATA6, SCK, WS */
3108 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
3109};
3110static const unsigned int ssi6_mux[] = {
3111 SSI_SDATA6_MARK, SSI_SCK6_MARK, SSI_WS6_MARK,
3112};
3113static const unsigned int ssi6_b_pins[] = {
3114 /* SDATA6, SCK, WS */
3115 RCAR_GP_PIN(1, 29), RCAR_GP_PIN(1, 25), RCAR_GP_PIN(1, 27),
3116};
3117static const unsigned int ssi6_b_mux[] = {
3118 SSI_SDATA6_B_MARK, SSI_SCK6_B_MARK, SSI_WS6_B_MARK,
3119};
3120static const unsigned int ssi7_data_pins[] = {
3121 /* SDATA7 */
3122 RCAR_GP_PIN(4, 22),
3123};
3124static const unsigned int ssi7_data_mux[] = {
3125 SSI_SDATA7_MARK,
3126};
3127static const unsigned int ssi7_b_data_pins[] = {
3128 /* SDATA7 */
3129 RCAR_GP_PIN(4, 22),
3130};
3131static const unsigned int ssi7_b_data_mux[] = {
3132 SSI_SDATA7_B_MARK,
3133};
3134static const unsigned int ssi7_c_data_pins[] = {
3135 /* SDATA7 */
3136 RCAR_GP_PIN(1, 26),
3137};
3138static const unsigned int ssi7_c_data_mux[] = {
3139 SSI_SDATA7_C_MARK,
3140};
3141static const unsigned int ssi78_ctrl_pins[] = {
3142 /* SCK, WS */
3143 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3144};
3145static const unsigned int ssi78_ctrl_mux[] = {
3146 SSI_SCK78_MARK, SSI_WS78_MARK,
3147};
3148static const unsigned int ssi78_b_ctrl_pins[] = {
3149 /* SCK, WS */
3150 RCAR_GP_PIN(1, 26), RCAR_GP_PIN(1, 24),
3151};
3152static const unsigned int ssi78_b_ctrl_mux[] = {
3153 SSI_SCK78_B_MARK, SSI_WS78_B_MARK,
3154};
3155static const unsigned int ssi78_c_ctrl_pins[] = {
3156 /* SCK, WS */
3157 RCAR_GP_PIN(1, 24), RCAR_GP_PIN(1, 25),
3158};
3159static const unsigned int ssi78_c_ctrl_mux[] = {
3160 SSI_SCK78_C_MARK, SSI_WS78_C_MARK,
3161};
3162static const unsigned int ssi8_data_pins[] = {
3163 /* SDATA8 */
3164 RCAR_GP_PIN(4, 23),
3165};
3166static const unsigned int ssi8_data_mux[] = {
3167 SSI_SDATA8_MARK,
3168};
3169static const unsigned int ssi8_b_data_pins[] = {
3170 /* SDATA8 */
3171 RCAR_GP_PIN(4, 23),
3172};
3173static const unsigned int ssi8_b_data_mux[] = {
3174 SSI_SDATA8_B_MARK,
3175};
3176static const unsigned int ssi8_c_data_pins[] = {
3177 /* SDATA8 */
3178 RCAR_GP_PIN(1, 27),
3179};
3180static const unsigned int ssi8_c_data_mux[] = {
3181 SSI_SDATA8_C_MARK,
3182};
3183static const unsigned int ssi9_data_pins[] = {
3184 /* SDATA9 */
3185 RCAR_GP_PIN(4, 24),
3186};
3187static const unsigned int ssi9_data_mux[] = {
3188 SSI_SDATA9_MARK,
3189};
3190static const unsigned int ssi9_ctrl_pins[] = {
3191 /* SCK, WS */
3192 RCAR_GP_PIN(5, 10), RCAR_GP_PIN(5, 11),
3193};
3194static const unsigned int ssi9_ctrl_mux[] = {
3195 SSI_SCK9_MARK, SSI_WS9_MARK,
3196};
2964/* - TPU0 ------------------------------------------------------------------- */ 3197/* - TPU0 ------------------------------------------------------------------- */
2965static const unsigned int tpu0_to0_pins[] = { 3198static const unsigned int tpu0_to0_pins[] = {
2966 /* TO */ 3199 /* TO */
@@ -3014,59 +3247,110 @@ static const unsigned int usb2_pins[] = {
3014static const unsigned int usb2_mux[] = { 3247static const unsigned int usb2_mux[] = {
3015 USB2_PWEN_MARK, USB2_OVC_MARK, 3248 USB2_PWEN_MARK, USB2_OVC_MARK,
3016}; 3249};
3017/* - VIN0 ------------------------------------------------------------------- */ 3250
3018static const unsigned int vin0_data_g_pins[] = { 3251union vin_data {
3019 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9), RCAR_GP_PIN(0, 10), 3252 unsigned int data24[24];
3020 RCAR_GP_PIN(0, 11), RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1), 3253 unsigned int data20[20];
3021 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3), 3254 unsigned int data16[16];
3022}; 3255 unsigned int data12[12];
3023static const unsigned int vin0_data_g_mux[] = { 3256 unsigned int data10[10];
3024 VI0_G0_MARK, VI0_G1_MARK, VI0_G2_MARK, 3257 unsigned int data8[8];
3025 VI0_G3_MARK, VI0_G4_MARK, VI0_G5_MARK, 3258 unsigned int data4[4];
3026 VI0_G6_MARK, VI0_G7_MARK,
3027}; 3259};
3028static const unsigned int vin0_data_r_pins[] = { 3260
3029 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5), RCAR_GP_PIN(0, 6), 3261#define VIN_DATA_PIN_GROUP(n, s) \
3030 RCAR_GP_PIN(0, 7), RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25), 3262 { \
3031 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11), 3263 .name = #n#s, \
3264 .pins = n##_pins.data##s, \
3265 .mux = n##_mux.data##s, \
3266 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
3267 }
3268
3269/* - VIN0 ------------------------------------------------------------------- */
3270static const union vin_data vin0_data_pins = {
3271 .data24 = {
3272 /* B */
3273 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2),
3274 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3275 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3276 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3277 /* G */
3278 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3279 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3280 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3281 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3282 /* R */
3283 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3284 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3285 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3286 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3287 },
3032}; 3288};
3033static const unsigned int vin0_data_r_mux[] = { 3289static const union vin_data vin0_data_mux = {
3034 VI0_R0_MARK, VI0_R1_MARK, VI0_R2_MARK, 3290 .data24 = {
3035 VI0_R3_MARK, VI0_R4_MARK, VI0_R5_MARK, 3291 /* B */
3036 VI0_R6_MARK, VI0_R7_MARK, 3292 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
3293 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3294 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3295 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3296 /* G */
3297 VI0_G0_MARK, VI0_G1_MARK,
3298 VI0_G2_MARK, VI0_G3_MARK,
3299 VI0_G4_MARK, VI0_G5_MARK,
3300 VI0_G6_MARK, VI0_G7_MARK,
3301 /* R */
3302 VI0_R0_MARK, VI0_R1_MARK,
3303 VI0_R2_MARK, VI0_R3_MARK,
3304 VI0_R4_MARK, VI0_R5_MARK,
3305 VI0_R6_MARK, VI0_R7_MARK,
3306 },
3037}; 3307};
3038static const unsigned int vin0_data_b_pins[] = { 3308static const unsigned int vin0_data18_pins[] = {
3039 RCAR_GP_PIN(2, 1), RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3), 3309 /* B */
3040 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6), 3310 RCAR_GP_PIN(2, 3), RCAR_GP_PIN(2, 4),
3311 RCAR_GP_PIN(2, 5), RCAR_GP_PIN(2, 6),
3041 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8), 3312 RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 8),
3313 /* G */
3314 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3315 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3316 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3317 /* R */
3318 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3319 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
3320 RCAR_GP_PIN(0, 26), RCAR_GP_PIN(1, 11),
3042}; 3321};
3043static const unsigned int vin0_data_b_mux[] = { 3322static const unsigned int vin0_data18_mux[] = {
3044 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK, VI0_DATA2_VI0_B2_MARK, 3323 /* B */
3045 VI0_DATA3_VI0_B3_MARK, VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK, 3324 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
3325 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
3046 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK, 3326 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
3327 /* G */
3328 VI0_G2_MARK, VI0_G3_MARK,
3329 VI0_G4_MARK, VI0_G5_MARK,
3330 VI0_G6_MARK, VI0_G7_MARK,
3331 /* R */
3332 VI0_R2_MARK, VI0_R3_MARK,
3333 VI0_R4_MARK, VI0_R5_MARK,
3334 VI0_R6_MARK, VI0_R7_MARK,
3047}; 3335};
3048static const unsigned int vin0_hsync_signal_pins[] = { 3336static const unsigned int vin0_sync_pins[] = {
3049 RCAR_GP_PIN(0, 12), 3337 RCAR_GP_PIN(0, 12), /* HSYNC */
3338 RCAR_GP_PIN(0, 13), /* VSYNC */
3050}; 3339};
3051static const unsigned int vin0_hsync_signal_mux[] = { 3340static const unsigned int vin0_sync_mux[] = {
3052 VI0_HSYNC_N_MARK, 3341 VI0_HSYNC_N_MARK,
3053};
3054static const unsigned int vin0_vsync_signal_pins[] = {
3055 RCAR_GP_PIN(0, 13),
3056};
3057static const unsigned int vin0_vsync_signal_mux[] = {
3058 VI0_VSYNC_N_MARK, 3342 VI0_VSYNC_N_MARK,
3059}; 3343};
3060static const unsigned int vin0_field_signal_pins[] = { 3344static const unsigned int vin0_field_pins[] = {
3061 RCAR_GP_PIN(0, 15), 3345 RCAR_GP_PIN(0, 15),
3062}; 3346};
3063static const unsigned int vin0_field_signal_mux[] = { 3347static const unsigned int vin0_field_mux[] = {
3064 VI0_FIELD_MARK, 3348 VI0_FIELD_MARK,
3065}; 3349};
3066static const unsigned int vin0_data_enable_pins[] = { 3350static const unsigned int vin0_clkenb_pins[] = {
3067 RCAR_GP_PIN(0, 14), 3351 RCAR_GP_PIN(0, 14),
3068}; 3352};
3069static const unsigned int vin0_data_enable_mux[] = { 3353static const unsigned int vin0_clkenb_mux[] = {
3070 VI0_CLKENB_MARK, 3354 VI0_CLKENB_MARK,
3071}; 3355};
3072static const unsigned int vin0_clk_pins[] = { 3356static const unsigned int vin0_clk_pins[] = {
@@ -3076,15 +3360,91 @@ static const unsigned int vin0_clk_mux[] = {
3076 VI0_CLK_MARK, 3360 VI0_CLK_MARK,
3077}; 3361};
3078/* - VIN1 ------------------------------------------------------------------- */ 3362/* - VIN1 ------------------------------------------------------------------- */
3079static const unsigned int vin1_data_pins[] = { 3363static const union vin_data vin1_data_pins = {
3080 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11), RCAR_GP_PIN(2, 12), 3364 .data24 = {
3081 RCAR_GP_PIN(2, 13), RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15), 3365 /* B */
3082 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17), 3366 RCAR_GP_PIN(2, 10), RCAR_GP_PIN(2, 11),
3367 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3368 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3369 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3370 /* G */
3371 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3372 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3373 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3374 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3375 /* R */
3376 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3377 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3378 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3379 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3380 },
3083}; 3381};
3084static const unsigned int vin1_data_mux[] = { 3382static const union vin_data vin1_data_mux = {
3085 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK, VI1_DATA2_VI1_B2_MARK, 3383 .data24 = {
3086 VI1_DATA3_VI1_B3_MARK, VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK, 3384 /* B */
3385 VI1_DATA0_VI1_B0_MARK, VI1_DATA1_VI1_B1_MARK,
3386 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3387 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3388 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3389 /* G */
3390 VI1_G0_MARK, VI1_G1_MARK,
3391 VI1_G2_MARK, VI1_G3_MARK,
3392 VI1_G4_MARK, VI1_G5_MARK,
3393 VI1_G6_MARK, VI1_G7_MARK,
3394 /* R */
3395 VI1_R0_MARK, VI1_R1_MARK,
3396 VI1_R2_MARK, VI1_R3_MARK,
3397 VI1_R4_MARK, VI1_R5_MARK,
3398 VI1_R6_MARK, VI1_R7_MARK,
3399 },
3400};
3401static const unsigned int vin1_data18_pins[] = {
3402 /* B */
3403 RCAR_GP_PIN(2, 12), RCAR_GP_PIN(2, 13),
3404 RCAR_GP_PIN(2, 14), RCAR_GP_PIN(2, 15),
3405 RCAR_GP_PIN(2, 16), RCAR_GP_PIN(2, 17),
3406 /* G */
3407 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3408 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 12),
3409 RCAR_GP_PIN(1, 9), RCAR_GP_PIN(1, 7),
3410 /* R */
3411 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 4),
3412 RCAR_GP_PIN(1, 5), RCAR_GP_PIN(1, 6),
3413 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 8),
3414};
3415static const unsigned int vin1_data18_mux[] = {
3416 /* B */
3417 VI1_DATA2_VI1_B2_MARK, VI1_DATA3_VI1_B3_MARK,
3418 VI1_DATA4_VI1_B4_MARK, VI1_DATA5_VI1_B5_MARK,
3087 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK, 3419 VI1_DATA6_VI1_B6_MARK, VI1_DATA7_VI1_B7_MARK,
3420 /* G */
3421 VI1_G2_MARK, VI1_G3_MARK,
3422 VI1_G4_MARK, VI1_G5_MARK,
3423 VI1_G6_MARK, VI1_G7_MARK,
3424 /* R */
3425 VI1_R2_MARK, VI1_R3_MARK,
3426 VI1_R4_MARK, VI1_R5_MARK,
3427 VI1_R6_MARK, VI1_R7_MARK,
3428};
3429static const unsigned int vin1_sync_pins[] = {
3430 RCAR_GP_PIN(1, 24), /* HSYNC */
3431 RCAR_GP_PIN(1, 25), /* VSYNC */
3432};
3433static const unsigned int vin1_sync_mux[] = {
3434 VI1_HSYNC_N_MARK,
3435 VI1_VSYNC_N_MARK,
3436};
3437static const unsigned int vin1_field_pins[] = {
3438 RCAR_GP_PIN(1, 13),
3439};
3440static const unsigned int vin1_field_mux[] = {
3441 VI1_FIELD_MARK,
3442};
3443static const unsigned int vin1_clkenb_pins[] = {
3444 RCAR_GP_PIN(1, 26),
3445};
3446static const unsigned int vin1_clkenb_mux[] = {
3447 VI1_CLKENB_MARK,
3088}; 3448};
3089static const unsigned int vin1_clk_pins[] = { 3449static const unsigned int vin1_clk_pins[] = {
3090 RCAR_GP_PIN(2, 9), 3450 RCAR_GP_PIN(2, 9),
@@ -3092,8 +3452,147 @@ static const unsigned int vin1_clk_pins[] = {
3092static const unsigned int vin1_clk_mux[] = { 3452static const unsigned int vin1_clk_mux[] = {
3093 VI1_CLK_MARK, 3453 VI1_CLK_MARK,
3094}; 3454};
3455/* - VIN2 ----------------------------------------------------------------- */
3456static const union vin_data vin2_data_pins = {
3457 .data24 = {
3458 /* B */
3459 RCAR_GP_PIN(0, 8), RCAR_GP_PIN(0, 9),
3460 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3461 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3462 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3463 /* G */
3464 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
3465 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3466 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3467 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3468 /* R */
3469 RCAR_GP_PIN(1, 12), RCAR_GP_PIN(1, 13),
3470 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3471 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3472 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3473 },
3474};
3475static const union vin_data vin2_data_mux = {
3476 .data24 = {
3477 /* B */
3478 VI2_DATA0_VI2_B0_MARK, VI2_DATA1_VI2_B1_MARK,
3479 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3480 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3481 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3482 /* G */
3483 VI2_G0_MARK, VI2_G1_MARK,
3484 VI2_G2_MARK, VI2_G3_MARK,
3485 VI2_G4_MARK, VI2_G5_MARK,
3486 VI2_G6_MARK, VI2_G7_MARK,
3487 /* R */
3488 VI2_R0_MARK, VI2_R1_MARK,
3489 VI2_R2_MARK, VI2_R3_MARK,
3490 VI2_R4_MARK, VI2_R5_MARK,
3491 VI2_R6_MARK, VI2_R7_MARK,
3492 },
3493};
3494static const unsigned int vin2_data18_pins[] = {
3495 /* B */
3496 RCAR_GP_PIN(0, 10), RCAR_GP_PIN(0, 11),
3497 RCAR_GP_PIN(0, 12), RCAR_GP_PIN(0, 13),
3498 RCAR_GP_PIN(0, 14), RCAR_GP_PIN(0, 15),
3499 /* G */
3500 RCAR_GP_PIN(0, 29), RCAR_GP_PIN(1, 10),
3501 RCAR_GP_PIN(1, 4), RCAR_GP_PIN(1, 5),
3502 RCAR_GP_PIN(1, 6), RCAR_GP_PIN(1, 7),
3503 /* R */
3504 RCAR_GP_PIN(1, 14), RCAR_GP_PIN(1, 15),
3505 RCAR_GP_PIN(1, 17), RCAR_GP_PIN(1, 20),
3506 RCAR_GP_PIN(1, 22), RCAR_GP_PIN(1, 24),
3507};
3508static const unsigned int vin2_data18_mux[] = {
3509 /* B */
3510 VI2_DATA2_VI2_B2_MARK, VI2_DATA3_VI2_B3_MARK,
3511 VI2_DATA4_VI2_B4_MARK, VI2_DATA5_VI2_B5_MARK,
3512 VI2_DATA6_VI2_B6_MARK, VI2_DATA7_VI2_B7_MARK,
3513 /* G */
3514 VI2_G2_MARK, VI2_G3_MARK,
3515 VI2_G4_MARK, VI2_G5_MARK,
3516 VI2_G6_MARK, VI2_G7_MARK,
3517 /* R */
3518 VI2_R2_MARK, VI2_R3_MARK,
3519 VI2_R4_MARK, VI2_R5_MARK,
3520 VI2_R6_MARK, VI2_R7_MARK,
3521};
3522static const unsigned int vin2_sync_pins[] = {
3523 RCAR_GP_PIN(1, 16), /* HSYNC */
3524 RCAR_GP_PIN(1, 21), /* VSYNC */
3525};
3526static const unsigned int vin2_sync_mux[] = {
3527 VI2_HSYNC_N_MARK,
3528 VI2_VSYNC_N_MARK,
3529};
3530static const unsigned int vin2_field_pins[] = {
3531 RCAR_GP_PIN(1, 9),
3532};
3533static const unsigned int vin2_field_mux[] = {
3534 VI2_FIELD_MARK,
3535};
3536static const unsigned int vin2_clkenb_pins[] = {
3537 RCAR_GP_PIN(1, 8),
3538};
3539static const unsigned int vin2_clkenb_mux[] = {
3540 VI2_CLKENB_MARK,
3541};
3542static const unsigned int vin2_clk_pins[] = {
3543 RCAR_GP_PIN(1, 11),
3544};
3545static const unsigned int vin2_clk_mux[] = {
3546 VI2_CLK_MARK,
3547};
3548/* - VIN3 ----------------------------------------------------------------- */
3549static const unsigned int vin3_data8_pins[] = {
3550 RCAR_GP_PIN(0, 0), RCAR_GP_PIN(0, 1),
3551 RCAR_GP_PIN(0, 2), RCAR_GP_PIN(0, 3),
3552 RCAR_GP_PIN(0, 4), RCAR_GP_PIN(0, 5),
3553 RCAR_GP_PIN(0, 6), RCAR_GP_PIN(0, 7),
3554};
3555static const unsigned int vin3_data8_mux[] = {
3556 VI3_DATA0_MARK, VI3_DATA1_MARK,
3557 VI3_DATA2_MARK, VI3_DATA3_MARK,
3558 VI3_DATA4_MARK, VI3_DATA5_MARK,
3559 VI3_DATA6_MARK, VI3_DATA7_MARK,
3560};
3561static const unsigned int vin3_sync_pins[] = {
3562 RCAR_GP_PIN(1, 16), /* HSYNC */
3563 RCAR_GP_PIN(1, 17), /* VSYNC */
3564};
3565static const unsigned int vin3_sync_mux[] = {
3566 VI3_HSYNC_N_MARK,
3567 VI3_VSYNC_N_MARK,
3568};
3569static const unsigned int vin3_field_pins[] = {
3570 RCAR_GP_PIN(1, 15),
3571};
3572static const unsigned int vin3_field_mux[] = {
3573 VI3_FIELD_MARK,
3574};
3575static const unsigned int vin3_clkenb_pins[] = {
3576 RCAR_GP_PIN(1, 14),
3577};
3578static const unsigned int vin3_clkenb_mux[] = {
3579 VI3_CLKENB_MARK,
3580};
3581static const unsigned int vin3_clk_pins[] = {
3582 RCAR_GP_PIN(1, 23),
3583};
3584static const unsigned int vin3_clk_mux[] = {
3585 VI3_CLK_MARK,
3586};
3095 3587
3096static const struct sh_pfc_pin_group pinmux_groups[] = { 3588static const struct sh_pfc_pin_group pinmux_groups[] = {
3589 SH_PFC_PIN_GROUP(audio_clk_a),
3590 SH_PFC_PIN_GROUP(audio_clk_b),
3591 SH_PFC_PIN_GROUP(audio_clk_c),
3592 SH_PFC_PIN_GROUP(audio_clkout),
3593 SH_PFC_PIN_GROUP(audio_clkout_b),
3594 SH_PFC_PIN_GROUP(audio_clkout_c),
3595 SH_PFC_PIN_GROUP(audio_clkout_d),
3097 SH_PFC_PIN_GROUP(du_rgb666), 3596 SH_PFC_PIN_GROUP(du_rgb666),
3098 SH_PFC_PIN_GROUP(du_rgb888), 3597 SH_PFC_PIN_GROUP(du_rgb888),
3099 SH_PFC_PIN_GROUP(du_clk_out_0), 3598 SH_PFC_PIN_GROUP(du_clk_out_0),
@@ -3259,6 +3758,32 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3259 SH_PFC_PIN_GROUP(sdhi3_ctrl), 3758 SH_PFC_PIN_GROUP(sdhi3_ctrl),
3260 SH_PFC_PIN_GROUP(sdhi3_cd), 3759 SH_PFC_PIN_GROUP(sdhi3_cd),
3261 SH_PFC_PIN_GROUP(sdhi3_wp), 3760 SH_PFC_PIN_GROUP(sdhi3_wp),
3761 SH_PFC_PIN_GROUP(ssi0_data),
3762 SH_PFC_PIN_GROUP(ssi0129_ctrl),
3763 SH_PFC_PIN_GROUP(ssi1_data),
3764 SH_PFC_PIN_GROUP(ssi1_ctrl),
3765 SH_PFC_PIN_GROUP(ssi2_data),
3766 SH_PFC_PIN_GROUP(ssi2_ctrl),
3767 SH_PFC_PIN_GROUP(ssi3_data),
3768 SH_PFC_PIN_GROUP(ssi34_ctrl),
3769 SH_PFC_PIN_GROUP(ssi4_data),
3770 SH_PFC_PIN_GROUP(ssi4_ctrl),
3771 SH_PFC_PIN_GROUP(ssi5),
3772 SH_PFC_PIN_GROUP(ssi5_b),
3773 SH_PFC_PIN_GROUP(ssi5_c),
3774 SH_PFC_PIN_GROUP(ssi6),
3775 SH_PFC_PIN_GROUP(ssi6_b),
3776 SH_PFC_PIN_GROUP(ssi7_data),
3777 SH_PFC_PIN_GROUP(ssi7_b_data),
3778 SH_PFC_PIN_GROUP(ssi7_c_data),
3779 SH_PFC_PIN_GROUP(ssi78_ctrl),
3780 SH_PFC_PIN_GROUP(ssi78_b_ctrl),
3781 SH_PFC_PIN_GROUP(ssi78_c_ctrl),
3782 SH_PFC_PIN_GROUP(ssi8_data),
3783 SH_PFC_PIN_GROUP(ssi8_b_data),
3784 SH_PFC_PIN_GROUP(ssi8_c_data),
3785 SH_PFC_PIN_GROUP(ssi9_data),
3786 SH_PFC_PIN_GROUP(ssi9_ctrl),
3262 SH_PFC_PIN_GROUP(tpu0_to0), 3787 SH_PFC_PIN_GROUP(tpu0_to0),
3263 SH_PFC_PIN_GROUP(tpu0_to1), 3788 SH_PFC_PIN_GROUP(tpu0_to1),
3264 SH_PFC_PIN_GROUP(tpu0_to2), 3789 SH_PFC_PIN_GROUP(tpu0_to2),
@@ -3266,16 +3791,54 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
3266 SH_PFC_PIN_GROUP(usb0), 3791 SH_PFC_PIN_GROUP(usb0),
3267 SH_PFC_PIN_GROUP(usb1), 3792 SH_PFC_PIN_GROUP(usb1),
3268 SH_PFC_PIN_GROUP(usb2), 3793 SH_PFC_PIN_GROUP(usb2),
3269 SH_PFC_PIN_GROUP(vin0_data_g), 3794 VIN_DATA_PIN_GROUP(vin0_data, 24),
3270 SH_PFC_PIN_GROUP(vin0_data_r), 3795 VIN_DATA_PIN_GROUP(vin0_data, 20),
3271 SH_PFC_PIN_GROUP(vin0_data_b), 3796 SH_PFC_PIN_GROUP(vin0_data18),
3272 SH_PFC_PIN_GROUP(vin0_hsync_signal), 3797 VIN_DATA_PIN_GROUP(vin0_data, 16),
3273 SH_PFC_PIN_GROUP(vin0_vsync_signal), 3798 VIN_DATA_PIN_GROUP(vin0_data, 12),
3274 SH_PFC_PIN_GROUP(vin0_field_signal), 3799 VIN_DATA_PIN_GROUP(vin0_data, 10),
3275 SH_PFC_PIN_GROUP(vin0_data_enable), 3800 VIN_DATA_PIN_GROUP(vin0_data, 8),
3801 VIN_DATA_PIN_GROUP(vin0_data, 4),
3802 SH_PFC_PIN_GROUP(vin0_sync),
3803 SH_PFC_PIN_GROUP(vin0_field),
3804 SH_PFC_PIN_GROUP(vin0_clkenb),
3276 SH_PFC_PIN_GROUP(vin0_clk), 3805 SH_PFC_PIN_GROUP(vin0_clk),
3277 SH_PFC_PIN_GROUP(vin1_data), 3806 VIN_DATA_PIN_GROUP(vin1_data, 24),
3807 VIN_DATA_PIN_GROUP(vin1_data, 20),
3808 SH_PFC_PIN_GROUP(vin1_data18),
3809 VIN_DATA_PIN_GROUP(vin1_data, 16),
3810 VIN_DATA_PIN_GROUP(vin1_data, 12),
3811 VIN_DATA_PIN_GROUP(vin1_data, 10),
3812 VIN_DATA_PIN_GROUP(vin1_data, 8),
3813 VIN_DATA_PIN_GROUP(vin1_data, 4),
3814 SH_PFC_PIN_GROUP(vin1_sync),
3815 SH_PFC_PIN_GROUP(vin1_field),
3816 SH_PFC_PIN_GROUP(vin1_clkenb),
3278 SH_PFC_PIN_GROUP(vin1_clk), 3817 SH_PFC_PIN_GROUP(vin1_clk),
3818 VIN_DATA_PIN_GROUP(vin2_data, 24),
3819 SH_PFC_PIN_GROUP(vin2_data18),
3820 VIN_DATA_PIN_GROUP(vin2_data, 16),
3821 VIN_DATA_PIN_GROUP(vin2_data, 8),
3822 VIN_DATA_PIN_GROUP(vin2_data, 4),
3823 SH_PFC_PIN_GROUP(vin2_sync),
3824 SH_PFC_PIN_GROUP(vin2_field),
3825 SH_PFC_PIN_GROUP(vin2_clkenb),
3826 SH_PFC_PIN_GROUP(vin2_clk),
3827 SH_PFC_PIN_GROUP(vin3_data8),
3828 SH_PFC_PIN_GROUP(vin3_sync),
3829 SH_PFC_PIN_GROUP(vin3_field),
3830 SH_PFC_PIN_GROUP(vin3_clkenb),
3831 SH_PFC_PIN_GROUP(vin3_clk),
3832};
3833
3834static const char * const audio_clk_groups[] = {
3835 "audio_clk_a",
3836 "audio_clk_b",
3837 "audio_clk_c",
3838 "audio_clkout",
3839 "audio_clkout_b",
3840 "audio_clkout_c",
3841 "audio_clkout_d",
3279}; 3842};
3280 3843
3281static const char * const du_groups[] = { 3844static const char * const du_groups[] = {
@@ -3533,6 +4096,35 @@ static const char * const sdhi3_groups[] = {
3533 "sdhi3_wp", 4096 "sdhi3_wp",
3534}; 4097};
3535 4098
4099static const char * const ssi_groups[] = {
4100 "ssi0_data",
4101 "ssi0129_ctrl",
4102 "ssi1_data",
4103 "ssi1_ctrl",
4104 "ssi2_data",
4105 "ssi2_ctrl",
4106 "ssi3_data",
4107 "ssi34_ctrl",
4108 "ssi4_data",
4109 "ssi4_ctrl",
4110 "ssi5",
4111 "ssi5_b",
4112 "ssi5_c",
4113 "ssi6",
4114 "ssi6_b",
4115 "ssi7_data",
4116 "ssi7_b_data",
4117 "ssi7_c_data",
4118 "ssi78_ctrl",
4119 "ssi78_b_ctrl",
4120 "ssi78_c_ctrl",
4121 "ssi8_data",
4122 "ssi8_b_data",
4123 "ssi8_c_data",
4124 "ssi9_data",
4125 "ssi9_ctrl",
4126};
4127
3536static const char * const tpu0_groups[] = { 4128static const char * const tpu0_groups[] = {
3537 "tpu0_to0", 4129 "tpu0_to0",
3538 "tpu0_to1", 4130 "tpu0_to1",
@@ -3553,22 +4145,57 @@ static const char * const usb2_groups[] = {
3553}; 4145};
3554 4146
3555static const char * const vin0_groups[] = { 4147static const char * const vin0_groups[] = {
3556 "vin0_data_g", 4148 "vin0_data24",
3557 "vin0_data_r", 4149 "vin0_data20",
3558 "vin0_data_b", 4150 "vin0_data18",
3559 "vin0_hsync_signal", 4151 "vin0_data16",
3560 "vin0_vsync_signal", 4152 "vin0_data12",
3561 "vin0_field_signal", 4153 "vin0_data10",
3562 "vin0_data_enable", 4154 "vin0_data8",
4155 "vin0_data4",
4156 "vin0_sync",
4157 "vin0_field",
4158 "vin0_clkenb",
3563 "vin0_clk", 4159 "vin0_clk",
3564}; 4160};
3565 4161
3566static const char * const vin1_groups[] = { 4162static const char * const vin1_groups[] = {
3567 "vin1_data", 4163 "vin1_data24",
4164 "vin1_data20",
4165 "vin1_data18",
4166 "vin1_data16",
4167 "vin1_data12",
4168 "vin1_data10",
4169 "vin1_data8",
4170 "vin1_data4",
4171 "vin1_sync",
4172 "vin1_field",
4173 "vin1_clkenb",
3568 "vin1_clk", 4174 "vin1_clk",
3569}; 4175};
3570 4176
4177static const char * const vin2_groups[] = {
4178 "vin2_data24",
4179 "vin2_data18",
4180 "vin2_data16",
4181 "vin2_data8",
4182 "vin2_data4",
4183 "vin2_sync",
4184 "vin2_field",
4185 "vin2_clkenb",
4186 "vin2_clk",
4187};
4188
4189static const char * const vin3_groups[] = {
4190 "vin3_data8",
4191 "vin3_sync",
4192 "vin3_field",
4193 "vin3_clkenb",
4194 "vin3_clk",
4195};
4196
3571static const struct sh_pfc_function pinmux_functions[] = { 4197static const struct sh_pfc_function pinmux_functions[] = {
4198 SH_PFC_FUNCTION(audio_clk),
3572 SH_PFC_FUNCTION(du), 4199 SH_PFC_FUNCTION(du),
3573 SH_PFC_FUNCTION(du0), 4200 SH_PFC_FUNCTION(du0),
3574 SH_PFC_FUNCTION(du1), 4201 SH_PFC_FUNCTION(du1),
@@ -3599,15 +4226,18 @@ static const struct sh_pfc_function pinmux_functions[] = {
3599 SH_PFC_FUNCTION(sdhi1), 4226 SH_PFC_FUNCTION(sdhi1),
3600 SH_PFC_FUNCTION(sdhi2), 4227 SH_PFC_FUNCTION(sdhi2),
3601 SH_PFC_FUNCTION(sdhi3), 4228 SH_PFC_FUNCTION(sdhi3),
4229 SH_PFC_FUNCTION(ssi),
3602 SH_PFC_FUNCTION(tpu0), 4230 SH_PFC_FUNCTION(tpu0),
3603 SH_PFC_FUNCTION(usb0), 4231 SH_PFC_FUNCTION(usb0),
3604 SH_PFC_FUNCTION(usb1), 4232 SH_PFC_FUNCTION(usb1),
3605 SH_PFC_FUNCTION(usb2), 4233 SH_PFC_FUNCTION(usb2),
3606 SH_PFC_FUNCTION(vin0), 4234 SH_PFC_FUNCTION(vin0),
3607 SH_PFC_FUNCTION(vin1), 4235 SH_PFC_FUNCTION(vin1),
4236 SH_PFC_FUNCTION(vin2),
4237 SH_PFC_FUNCTION(vin3),
3608}; 4238};
3609 4239
3610static struct pinmux_cfg_reg pinmux_config_regs[] = { 4240static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3611 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 4241 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3612 GP_0_31_FN, FN_IP3_17_15, 4242 GP_0_31_FN, FN_IP3_17_15,
3613 GP_0_30_FN, FN_IP3_14_12, 4243 GP_0_30_FN, FN_IP3_14_12,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index bf76a654c02f..77d103fe39d9 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1674,7 +1674,7 @@ static const u16 pinmux_data[] = {
1674 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), 1674 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1675}; 1675};
1676 1676
1677static struct sh_pfc_pin pinmux_pins[] = { 1677static const struct sh_pfc_pin pinmux_pins[] = {
1678 PINMUX_GPIO_GP_ALL(), 1678 PINMUX_GPIO_GP_ALL(),
1679}; 1679};
1680 1680
@@ -1730,11 +1730,11 @@ static const unsigned int du_clk_out_1_pins[] = {
1730static const unsigned int du_clk_out_1_mux[] = { 1730static const unsigned int du_clk_out_1_mux[] = {
1731 DU1_DOTCLKOUT1_MARK 1731 DU1_DOTCLKOUT1_MARK
1732}; 1732};
1733static const unsigned int du_sync_1_pins[] = { 1733static const unsigned int du_sync_pins[] = {
1734 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */ 1734 /* EXVSYNC/VSYNC, EXHSYNC/HSYNC, EXDISP/EXODDF/EXCDE */
1735 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27), 1735 RCAR_GP_PIN(3, 29), RCAR_GP_PIN(3, 28), RCAR_GP_PIN(3, 27),
1736}; 1736};
1737static const unsigned int du_sync_1_mux[] = { 1737static const unsigned int du_sync_mux[] = {
1738 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK, 1738 DU1_EXODDF_DU1_ODDF_DISP_CDE_MARK,
1739 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK 1739 DU1_EXVSYNC_DU1_VSYNC_MARK, DU1_EXHSYNC_DU1_HSYNC_MARK
1740}; 1740};
@@ -1742,6 +1742,9 @@ static const unsigned int du_cde_disp_pins[] = {
1742 /* CDE DISP */ 1742 /* CDE DISP */
1743 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30), 1743 RCAR_GP_PIN(3, 31), RCAR_GP_PIN(3, 30),
1744}; 1744};
1745static const unsigned int du_cde_disp_mux[] = {
1746 DU1_CDE_MARK, DU1_DISP_MARK
1747};
1745static const unsigned int du0_clk_in_pins[] = { 1748static const unsigned int du0_clk_in_pins[] = {
1746 /* CLKIN */ 1749 /* CLKIN */
1747 RCAR_GP_PIN(6, 31), 1750 RCAR_GP_PIN(6, 31),
@@ -1749,15 +1752,26 @@ static const unsigned int du0_clk_in_pins[] = {
1749static const unsigned int du0_clk_in_mux[] = { 1752static const unsigned int du0_clk_in_mux[] = {
1750 DU0_DOTCLKIN_MARK 1753 DU0_DOTCLKIN_MARK
1751}; 1754};
1752static const unsigned int du_cde_disp_mux[] = {
1753 DU1_CDE_MARK, DU1_DISP_MARK
1754};
1755static const unsigned int du1_clk_in_pins[] = { 1755static const unsigned int du1_clk_in_pins[] = {
1756 /* CLKIN */ 1756 /* CLKIN */
1757 RCAR_GP_PIN(7, 20), RCAR_GP_PIN(7, 19), RCAR_GP_PIN(3, 24), 1757 RCAR_GP_PIN(3, 24),
1758}; 1758};
1759static const unsigned int du1_clk_in_mux[] = { 1759static const unsigned int du1_clk_in_mux[] = {
1760 DU1_DOTCLKIN_C_MARK, DU1_DOTCLKIN_B_MARK, DU1_DOTCLKIN_MARK 1760 DU1_DOTCLKIN_MARK
1761};
1762static const unsigned int du1_clk_in_b_pins[] = {
1763 /* CLKIN */
1764 RCAR_GP_PIN(7, 19),
1765};
1766static const unsigned int du1_clk_in_b_mux[] = {
1767 DU1_DOTCLKIN_B_MARK,
1768};
1769static const unsigned int du1_clk_in_c_pins[] = {
1770 /* CLKIN */
1771 RCAR_GP_PIN(7, 20),
1772};
1773static const unsigned int du1_clk_in_c_mux[] = {
1774 DU1_DOTCLKIN_C_MARK,
1761}; 1775};
1762/* - ETH -------------------------------------------------------------------- */ 1776/* - ETH -------------------------------------------------------------------- */
1763static const unsigned int eth_link_pins[] = { 1777static const unsigned int eth_link_pins[] = {
@@ -1791,6 +1805,144 @@ static const unsigned int eth_rmii_mux[] = {
1791 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK, 1805 ETH_RXD0_MARK, ETH_RXD1_MARK, ETH_RX_ER_MARK, ETH_CRS_DV_MARK,
1792 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK, 1806 ETH_TXD0_MARK, ETH_TXD1_MARK, ETH_TX_EN_MARK, ETH_REFCLK_MARK,
1793}; 1807};
1808/* - I2C0 ------------------------------------------------------------------- */
1809static const unsigned int i2c0_pins[] = {
1810 /* SCL, SDA */
1811 RCAR_GP_PIN(0, 24), RCAR_GP_PIN(0, 25),
1812};
1813static const unsigned int i2c0_mux[] = {
1814 SCL0_MARK, SDA0_MARK,
1815};
1816static const unsigned int i2c0_b_pins[] = {
1817 /* SCL, SDA */
1818 RCAR_GP_PIN(2, 2), RCAR_GP_PIN(2, 3),
1819};
1820static const unsigned int i2c0_b_mux[] = {
1821 SCL0_B_MARK, SDA0_B_MARK,
1822};
1823static const unsigned int i2c0_c_pins[] = {
1824 /* SCL, SDA */
1825 RCAR_GP_PIN(0, 16), RCAR_GP_PIN(1, 1),
1826};
1827static const unsigned int i2c0_c_mux[] = {
1828 SCL0_C_MARK, SDA0_C_MARK,
1829};
1830/* - I2C1 ------------------------------------------------------------------- */
1831static const unsigned int i2c1_pins[] = {
1832 /* SCL, SDA */
1833 RCAR_GP_PIN(1, 10), RCAR_GP_PIN(1, 11),
1834};
1835static const unsigned int i2c1_mux[] = {
1836 SCL1_MARK, SDA1_MARK,
1837};
1838static const unsigned int i2c1_b_pins[] = {
1839 /* SCL, SDA */
1840 RCAR_GP_PIN(2, 4), RCAR_GP_PIN(2, 5),
1841};
1842static const unsigned int i2c1_b_mux[] = {
1843 SCL1_B_MARK, SDA1_B_MARK,
1844};
1845static const unsigned int i2c1_c_pins[] = {
1846 /* SCL, SDA */
1847 RCAR_GP_PIN(6, 14), RCAR_GP_PIN(6, 15),
1848};
1849static const unsigned int i2c1_c_mux[] = {
1850 SCL1_C_MARK, SDA1_C_MARK,
1851};
1852static const unsigned int i2c1_d_pins[] = {
1853 /* SCL, SDA */
1854 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
1855};
1856static const unsigned int i2c1_d_mux[] = {
1857 SCL1_D_MARK, SDA1_D_MARK,
1858};
1859static const unsigned int i2c1_e_pins[] = {
1860 /* SCL, SDA */
1861 RCAR_GP_PIN(7, 15), RCAR_GP_PIN(7, 16),
1862};
1863static const unsigned int i2c1_e_mux[] = {
1864 SCL1_E_MARK, SDA1_E_MARK,
1865};
1866/* - I2C2 ------------------------------------------------------------------- */
1867static const unsigned int i2c2_pins[] = {
1868 /* SCL, SDA */
1869 RCAR_GP_PIN(2, 6), RCAR_GP_PIN(2, 7),
1870};
1871static const unsigned int i2c2_mux[] = {
1872 SCL2_MARK, SDA2_MARK,
1873};
1874static const unsigned int i2c2_b_pins[] = {
1875 /* SCL, SDA */
1876 RCAR_GP_PIN(3, 26), RCAR_GP_PIN(3, 29),
1877};
1878static const unsigned int i2c2_b_mux[] = {
1879 SCL2_B_MARK, SDA2_B_MARK,
1880};
1881static const unsigned int i2c2_c_pins[] = {
1882 /* SCL, SDA */
1883 RCAR_GP_PIN(5, 13), RCAR_GP_PIN(5, 14),
1884};
1885static const unsigned int i2c2_c_mux[] = {
1886 SCL2_C_MARK, SDA2_C_MARK,
1887};
1888static const unsigned int i2c2_d_pins[] = {
1889 /* SCL, SDA */
1890 RCAR_GP_PIN(5, 17), RCAR_GP_PIN(5, 18),
1891};
1892static const unsigned int i2c2_d_mux[] = {
1893 SCL2_D_MARK, SDA2_D_MARK,
1894};
1895/* - I2C3 ------------------------------------------------------------------- */
1896static const unsigned int i2c3_pins[] = {
1897 /* SCL, SDA */
1898 RCAR_GP_PIN(5, 15), RCAR_GP_PIN(5, 16),
1899};
1900static const unsigned int i2c3_mux[] = {
1901 SCL3_MARK, SDA3_MARK,
1902};
1903static const unsigned int i2c3_b_pins[] = {
1904 /* SCL, SDA */
1905 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
1906};
1907static const unsigned int i2c3_b_mux[] = {
1908 SCL3_B_MARK, SDA3_B_MARK,
1909};
1910static const unsigned int i2c3_c_pins[] = {
1911 /* SCL, SDA */
1912 RCAR_GP_PIN(3, 22), RCAR_GP_PIN(3, 23),
1913};
1914static const unsigned int i2c3_c_mux[] = {
1915 SCL3_C_MARK, SDA3_C_MARK,
1916};
1917static const unsigned int i2c3_d_pins[] = {
1918 /* SCL, SDA */
1919 RCAR_GP_PIN(0, 27), RCAR_GP_PIN(0, 28),
1920};
1921static const unsigned int i2c3_d_mux[] = {
1922 SCL3_D_MARK, SDA3_D_MARK,
1923};
1924/* - I2C4 ------------------------------------------------------------------- */
1925static const unsigned int i2c4_pins[] = {
1926 /* SCL, SDA */
1927 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
1928};
1929static const unsigned int i2c4_mux[] = {
1930 SCL4_MARK, SDA4_MARK,
1931};
1932static const unsigned int i2c4_b_pins[] = {
1933 /* SCL, SDA */
1934 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
1935};
1936static const unsigned int i2c4_b_mux[] = {
1937 SCL4_B_MARK, SDA4_B_MARK,
1938};
1939static const unsigned int i2c4_c_pins[] = {
1940 /* SCL, SDA */
1941 RCAR_GP_PIN(7, 13), RCAR_GP_PIN(7, 14),
1942};
1943static const unsigned int i2c4_c_mux[] = {
1944 SCL4_C_MARK, SDA4_C_MARK,
1945};
1794/* - INTC ------------------------------------------------------------------- */ 1946/* - INTC ------------------------------------------------------------------- */
1795static const unsigned int intc_irq0_pins[] = { 1947static const unsigned int intc_irq0_pins[] = {
1796 /* IRQ */ 1948 /* IRQ */
@@ -2635,34 +2787,306 @@ static const unsigned int sdhi2_wp_mux[] = {
2635 SD2_WP_MARK, 2787 SD2_WP_MARK,
2636}; 2788};
2637/* - USB0 ------------------------------------------------------------------- */ 2789/* - USB0 ------------------------------------------------------------------- */
2638static const unsigned int usb0_pwen_pins[] = { 2790static const unsigned int usb0_pins[] = {
2639 /* PWEN */ 2791 RCAR_GP_PIN(7, 23), /* PWEN */
2640 RCAR_GP_PIN(7, 23), 2792 RCAR_GP_PIN(7, 24), /* OVC */
2641}; 2793};
2642static const unsigned int usb0_pwen_mux[] = { 2794static const unsigned int usb0_mux[] = {
2643 USB0_PWEN_MARK, 2795 USB0_PWEN_MARK,
2644};
2645static const unsigned int usb0_ovc_pins[] = {
2646 /* OVC */
2647 RCAR_GP_PIN(7, 24),
2648};
2649static const unsigned int usb0_ovc_mux[] = {
2650 USB0_OVC_MARK, 2796 USB0_OVC_MARK,
2651}; 2797};
2652/* - USB1 ------------------------------------------------------------------- */ 2798/* - USB1 ------------------------------------------------------------------- */
2653static const unsigned int usb1_pwen_pins[] = { 2799static const unsigned int usb1_pins[] = {
2654 /* PWEN */ 2800 RCAR_GP_PIN(7, 25), /* PWEN */
2655 RCAR_GP_PIN(7, 25), 2801 RCAR_GP_PIN(6, 30), /* OVC */
2656}; 2802};
2657static const unsigned int usb1_pwen_mux[] = { 2803static const unsigned int usb1_mux[] = {
2658 USB1_PWEN_MARK, 2804 USB1_PWEN_MARK,
2805 USB1_OVC_MARK,
2659}; 2806};
2660static const unsigned int usb1_ovc_pins[] = { 2807
2661 /* OVC */ 2808union vin_data {
2662 RCAR_GP_PIN(6, 30), 2809 unsigned int data24[24];
2810 unsigned int data20[20];
2811 unsigned int data16[16];
2812 unsigned int data12[12];
2813 unsigned int data10[10];
2814 unsigned int data8[8];
2663}; 2815};
2664static const unsigned int usb1_ovc_mux[] = { 2816
2665 USB1_OVC_MARK, 2817#define VIN_DATA_PIN_GROUP(n, s) \
2818 { \
2819 .name = #n#s, \
2820 .pins = n##_pins.data##s, \
2821 .mux = n##_mux.data##s, \
2822 .nr_pins = ARRAY_SIZE(n##_pins.data##s), \
2823 }
2824
2825/* - VIN0 ------------------------------------------------------------------- */
2826static const union vin_data vin0_data_pins = {
2827 .data24 = {
2828 /* B */
2829 RCAR_GP_PIN(4, 5), RCAR_GP_PIN(4, 6),
2830 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
2831 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2832 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2833 /* G */
2834 RCAR_GP_PIN(4, 13), RCAR_GP_PIN(4, 14),
2835 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2836 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
2837 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
2838 /* R */
2839 RCAR_GP_PIN(4, 21), RCAR_GP_PIN(4, 22),
2840 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
2841 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2842 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2843 },
2844};
2845static const union vin_data vin0_data_mux = {
2846 .data24 = {
2847 /* B */
2848 VI0_DATA0_VI0_B0_MARK, VI0_DATA1_VI0_B1_MARK,
2849 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2850 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2851 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2852 /* G */
2853 VI0_G0_MARK, VI0_G1_MARK,
2854 VI0_G2_MARK, VI0_G3_MARK,
2855 VI0_G4_MARK, VI0_G5_MARK,
2856 VI0_G6_MARK, VI0_G7_MARK,
2857 /* R */
2858 VI0_R0_MARK, VI0_R1_MARK,
2859 VI0_R2_MARK, VI0_R3_MARK,
2860 VI0_R4_MARK, VI0_R5_MARK,
2861 VI0_R6_MARK, VI0_R7_MARK,
2862 },
2863};
2864static const unsigned int vin0_data18_pins[] = {
2865 /* B */
2866 RCAR_GP_PIN(4, 7), RCAR_GP_PIN(4, 8),
2867 RCAR_GP_PIN(4, 9), RCAR_GP_PIN(4, 10),
2868 RCAR_GP_PIN(4, 11), RCAR_GP_PIN(4, 12),
2869 /* G */
2870 RCAR_GP_PIN(4, 15), RCAR_GP_PIN(4, 16),
2871 RCAR_GP_PIN(4, 17), RCAR_GP_PIN(4, 18),
2872 RCAR_GP_PIN(4, 19), RCAR_GP_PIN(4, 20),
2873 /* R */
2874 RCAR_GP_PIN(4, 23), RCAR_GP_PIN(4, 24),
2875 RCAR_GP_PIN(4, 25), RCAR_GP_PIN(4, 26),
2876 RCAR_GP_PIN(4, 27), RCAR_GP_PIN(4, 28),
2877};
2878static const unsigned int vin0_data18_mux[] = {
2879 /* B */
2880 VI0_DATA2_VI0_B2_MARK, VI0_DATA3_VI0_B3_MARK,
2881 VI0_DATA4_VI0_B4_MARK, VI0_DATA5_VI0_B5_MARK,
2882 VI0_DATA6_VI0_B6_MARK, VI0_DATA7_VI0_B7_MARK,
2883 /* G */
2884 VI0_G2_MARK, VI0_G3_MARK,
2885 VI0_G4_MARK, VI0_G5_MARK,
2886 VI0_G6_MARK, VI0_G7_MARK,
2887 /* R */
2888 VI0_R2_MARK, VI0_R3_MARK,
2889 VI0_R4_MARK, VI0_R5_MARK,
2890 VI0_R6_MARK, VI0_R7_MARK,
2891};
2892static const unsigned int vin0_sync_pins[] = {
2893 RCAR_GP_PIN(4, 3), /* HSYNC */
2894 RCAR_GP_PIN(4, 4), /* VSYNC */
2895};
2896static const unsigned int vin0_sync_mux[] = {
2897 VI0_HSYNC_N_MARK,
2898 VI0_VSYNC_N_MARK,
2899};
2900static const unsigned int vin0_field_pins[] = {
2901 RCAR_GP_PIN(4, 2),
2902};
2903static const unsigned int vin0_field_mux[] = {
2904 VI0_FIELD_MARK,
2905};
2906static const unsigned int vin0_clkenb_pins[] = {
2907 RCAR_GP_PIN(4, 1),
2908};
2909static const unsigned int vin0_clkenb_mux[] = {
2910 VI0_CLKENB_MARK,
2911};
2912static const unsigned int vin0_clk_pins[] = {
2913 RCAR_GP_PIN(4, 0),
2914};
2915static const unsigned int vin0_clk_mux[] = {
2916 VI0_CLK_MARK,
2917};
2918/* - VIN1 ----------------------------------------------------------------- */
2919static const unsigned int vin1_data8_pins[] = {
2920 RCAR_GP_PIN(5, 5), RCAR_GP_PIN(5, 6),
2921 RCAR_GP_PIN(5, 7), RCAR_GP_PIN(5, 8),
2922 RCAR_GP_PIN(5, 9), RCAR_GP_PIN(5, 10),
2923 RCAR_GP_PIN(5, 11), RCAR_GP_PIN(5, 12),
2924};
2925static const unsigned int vin1_data8_mux[] = {
2926 VI1_DATA0_MARK, VI1_DATA1_MARK,
2927 VI1_DATA2_MARK, VI1_DATA3_MARK,
2928 VI1_DATA4_MARK, VI1_DATA5_MARK,
2929 VI1_DATA6_MARK, VI1_DATA7_MARK,
2930};
2931static const unsigned int vin1_sync_pins[] = {
2932 RCAR_GP_PIN(5, 0), /* HSYNC */
2933 RCAR_GP_PIN(5, 1), /* VSYNC */
2934};
2935static const unsigned int vin1_sync_mux[] = {
2936 VI1_HSYNC_N_MARK,
2937 VI1_VSYNC_N_MARK,
2938};
2939static const unsigned int vin1_field_pins[] = {
2940 RCAR_GP_PIN(5, 3),
2941};
2942static const unsigned int vin1_field_mux[] = {
2943 VI1_FIELD_MARK,
2944};
2945static const unsigned int vin1_clkenb_pins[] = {
2946 RCAR_GP_PIN(5, 2),
2947};
2948static const unsigned int vin1_clkenb_mux[] = {
2949 VI1_CLKENB_MARK,
2950};
2951static const unsigned int vin1_clk_pins[] = {
2952 RCAR_GP_PIN(5, 4),
2953};
2954static const unsigned int vin1_clk_mux[] = {
2955 VI1_CLK_MARK,
2956};
2957static const union vin_data vin1_b_data_pins = {
2958 .data24 = {
2959 /* B */
2960 RCAR_GP_PIN(3, 0), RCAR_GP_PIN(3, 1),
2961 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2962 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2963 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
2964 /* G */
2965 RCAR_GP_PIN(6, 24), RCAR_GP_PIN(6, 25),
2966 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
2967 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
2968 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
2969 /* R */
2970 RCAR_GP_PIN(7, 5), RCAR_GP_PIN(7, 6),
2971 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
2972 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
2973 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
2974 },
2975};
2976static const union vin_data vin1_b_data_mux = {
2977 .data24 = {
2978 /* B */
2979 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
2980 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
2981 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
2982 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
2983 /* G */
2984 VI1_G0_B_MARK, VI1_G1_B_MARK,
2985 VI1_G2_B_MARK, VI1_G3_B_MARK,
2986 VI1_G4_B_MARK, VI1_G5_B_MARK,
2987 VI1_G6_B_MARK, VI1_G7_B_MARK,
2988 /* R */
2989 VI1_R0_B_MARK, VI1_R1_B_MARK,
2990 VI1_R2_B_MARK, VI1_R3_B_MARK,
2991 VI1_R4_B_MARK, VI1_R5_B_MARK,
2992 VI1_R6_B_MARK, VI1_R7_B_MARK,
2993 },
2994};
2995static const unsigned int vin1_b_data18_pins[] = {
2996 /* B */
2997 RCAR_GP_PIN(3, 8), RCAR_GP_PIN(3, 9),
2998 RCAR_GP_PIN(3, 10), RCAR_GP_PIN(3, 11),
2999 RCAR_GP_PIN(3, 12), RCAR_GP_PIN(3, 13),
3000 /* G */
3001 RCAR_GP_PIN(6, 26), RCAR_GP_PIN(6, 27),
3002 RCAR_GP_PIN(6, 28), RCAR_GP_PIN(6, 29),
3003 RCAR_GP_PIN(7, 21), RCAR_GP_PIN(7, 22),
3004 /* R */
3005 RCAR_GP_PIN(2, 15), RCAR_GP_PIN(2, 16),
3006 RCAR_GP_PIN(2, 17), RCAR_GP_PIN(2, 18),
3007 RCAR_GP_PIN(2, 19), RCAR_GP_PIN(2, 20),
3008};
3009static const unsigned int vin1_b_data18_mux[] = {
3010 /* B */
3011 VI1_DATA0_B_MARK, VI1_DATA1_B_MARK,
3012 VI1_DATA2_B_MARK, VI1_DATA3_B_MARK,
3013 VI1_DATA4_B_MARK, VI1_DATA5_B_MARK,
3014 VI1_DATA6_B_MARK, VI1_DATA7_B_MARK,
3015 /* G */
3016 VI1_G0_B_MARK, VI1_G1_B_MARK,
3017 VI1_G2_B_MARK, VI1_G3_B_MARK,
3018 VI1_G4_B_MARK, VI1_G5_B_MARK,
3019 VI1_G6_B_MARK, VI1_G7_B_MARK,
3020 /* R */
3021 VI1_R0_B_MARK, VI1_R1_B_MARK,
3022 VI1_R2_B_MARK, VI1_R3_B_MARK,
3023 VI1_R4_B_MARK, VI1_R5_B_MARK,
3024 VI1_R6_B_MARK, VI1_R7_B_MARK,
3025};
3026static const unsigned int vin1_b_sync_pins[] = {
3027 RCAR_GP_PIN(3, 17), /* HSYNC */
3028 RCAR_GP_PIN(3, 18), /* VSYNC */
3029};
3030static const unsigned int vin1_b_sync_mux[] = {
3031 VI1_HSYNC_N_B_MARK,
3032 VI1_VSYNC_N_B_MARK,
3033};
3034static const unsigned int vin1_b_field_pins[] = {
3035 RCAR_GP_PIN(3, 20),
3036};
3037static const unsigned int vin1_b_field_mux[] = {
3038 VI1_FIELD_B_MARK,
3039};
3040static const unsigned int vin1_b_clkenb_pins[] = {
3041 RCAR_GP_PIN(3, 19),
3042};
3043static const unsigned int vin1_b_clkenb_mux[] = {
3044 VI1_CLKENB_B_MARK,
3045};
3046static const unsigned int vin1_b_clk_pins[] = {
3047 RCAR_GP_PIN(3, 16),
3048};
3049static const unsigned int vin1_b_clk_mux[] = {
3050 VI1_CLK_B_MARK,
3051};
3052/* - VIN2 ----------------------------------------------------------------- */
3053static const unsigned int vin2_data8_pins[] = {
3054 RCAR_GP_PIN(4, 20), RCAR_GP_PIN(4, 21),
3055 RCAR_GP_PIN(4, 22), RCAR_GP_PIN(4, 23),
3056 RCAR_GP_PIN(4, 24), RCAR_GP_PIN(4, 25),
3057 RCAR_GP_PIN(4, 26), RCAR_GP_PIN(4, 27),
3058};
3059static const unsigned int vin2_data8_mux[] = {
3060 VI2_DATA0_MARK, VI2_DATA1_MARK,
3061 VI2_DATA2_MARK, VI2_DATA3_MARK,
3062 VI2_DATA4_MARK, VI2_DATA5_MARK,
3063 VI2_DATA6_MARK, VI2_DATA7_MARK,
3064};
3065static const unsigned int vin2_sync_pins[] = {
3066 RCAR_GP_PIN(4, 15), /* HSYNC */
3067 RCAR_GP_PIN(4, 16), /* VSYNC */
3068};
3069static const unsigned int vin2_sync_mux[] = {
3070 VI2_HSYNC_N_MARK,
3071 VI2_VSYNC_N_MARK,
3072};
3073static const unsigned int vin2_field_pins[] = {
3074 RCAR_GP_PIN(4, 18),
3075};
3076static const unsigned int vin2_field_mux[] = {
3077 VI2_FIELD_MARK,
3078};
3079static const unsigned int vin2_clkenb_pins[] = {
3080 RCAR_GP_PIN(4, 17),
3081};
3082static const unsigned int vin2_clkenb_mux[] = {
3083 VI2_CLKENB_MARK,
3084};
3085static const unsigned int vin2_clk_pins[] = {
3086 RCAR_GP_PIN(4, 19),
3087};
3088static const unsigned int vin2_clk_mux[] = {
3089 VI2_CLK_MARK,
2666}; 3090};
2667 3091
2668static const struct sh_pfc_pin_group pinmux_groups[] = { 3092static const struct sh_pfc_pin_group pinmux_groups[] = {
@@ -2670,14 +3094,35 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2670 SH_PFC_PIN_GROUP(du_rgb888), 3094 SH_PFC_PIN_GROUP(du_rgb888),
2671 SH_PFC_PIN_GROUP(du_clk_out_0), 3095 SH_PFC_PIN_GROUP(du_clk_out_0),
2672 SH_PFC_PIN_GROUP(du_clk_out_1), 3096 SH_PFC_PIN_GROUP(du_clk_out_1),
2673 SH_PFC_PIN_GROUP(du_sync_1), 3097 SH_PFC_PIN_GROUP(du_sync),
2674 SH_PFC_PIN_GROUP(du_cde_disp), 3098 SH_PFC_PIN_GROUP(du_cde_disp),
2675 SH_PFC_PIN_GROUP(du0_clk_in), 3099 SH_PFC_PIN_GROUP(du0_clk_in),
2676 SH_PFC_PIN_GROUP(du1_clk_in), 3100 SH_PFC_PIN_GROUP(du1_clk_in),
3101 SH_PFC_PIN_GROUP(du1_clk_in_b),
3102 SH_PFC_PIN_GROUP(du1_clk_in_c),
2677 SH_PFC_PIN_GROUP(eth_link), 3103 SH_PFC_PIN_GROUP(eth_link),
2678 SH_PFC_PIN_GROUP(eth_magic), 3104 SH_PFC_PIN_GROUP(eth_magic),
2679 SH_PFC_PIN_GROUP(eth_mdio), 3105 SH_PFC_PIN_GROUP(eth_mdio),
2680 SH_PFC_PIN_GROUP(eth_rmii), 3106 SH_PFC_PIN_GROUP(eth_rmii),
3107 SH_PFC_PIN_GROUP(i2c0),
3108 SH_PFC_PIN_GROUP(i2c0_b),
3109 SH_PFC_PIN_GROUP(i2c0_c),
3110 SH_PFC_PIN_GROUP(i2c1),
3111 SH_PFC_PIN_GROUP(i2c1_b),
3112 SH_PFC_PIN_GROUP(i2c1_c),
3113 SH_PFC_PIN_GROUP(i2c1_d),
3114 SH_PFC_PIN_GROUP(i2c1_e),
3115 SH_PFC_PIN_GROUP(i2c2),
3116 SH_PFC_PIN_GROUP(i2c2_b),
3117 SH_PFC_PIN_GROUP(i2c2_c),
3118 SH_PFC_PIN_GROUP(i2c2_d),
3119 SH_PFC_PIN_GROUP(i2c3),
3120 SH_PFC_PIN_GROUP(i2c3_b),
3121 SH_PFC_PIN_GROUP(i2c3_c),
3122 SH_PFC_PIN_GROUP(i2c3_d),
3123 SH_PFC_PIN_GROUP(i2c4),
3124 SH_PFC_PIN_GROUP(i2c4_b),
3125 SH_PFC_PIN_GROUP(i2c4_c),
2681 SH_PFC_PIN_GROUP(intc_irq0), 3126 SH_PFC_PIN_GROUP(intc_irq0),
2682 SH_PFC_PIN_GROUP(intc_irq1), 3127 SH_PFC_PIN_GROUP(intc_irq1),
2683 SH_PFC_PIN_GROUP(intc_irq2), 3128 SH_PFC_PIN_GROUP(intc_irq2),
@@ -2794,10 +3239,40 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
2794 SH_PFC_PIN_GROUP(sdhi2_ctrl), 3239 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2795 SH_PFC_PIN_GROUP(sdhi2_cd), 3240 SH_PFC_PIN_GROUP(sdhi2_cd),
2796 SH_PFC_PIN_GROUP(sdhi2_wp), 3241 SH_PFC_PIN_GROUP(sdhi2_wp),
2797 SH_PFC_PIN_GROUP(usb0_pwen), 3242 SH_PFC_PIN_GROUP(usb0),
2798 SH_PFC_PIN_GROUP(usb0_ovc), 3243 SH_PFC_PIN_GROUP(usb1),
2799 SH_PFC_PIN_GROUP(usb1_pwen), 3244 VIN_DATA_PIN_GROUP(vin0_data, 24),
2800 SH_PFC_PIN_GROUP(usb1_ovc), 3245 VIN_DATA_PIN_GROUP(vin0_data, 20),
3246 SH_PFC_PIN_GROUP(vin0_data18),
3247 VIN_DATA_PIN_GROUP(vin0_data, 16),
3248 VIN_DATA_PIN_GROUP(vin0_data, 12),
3249 VIN_DATA_PIN_GROUP(vin0_data, 10),
3250 VIN_DATA_PIN_GROUP(vin0_data, 8),
3251 SH_PFC_PIN_GROUP(vin0_sync),
3252 SH_PFC_PIN_GROUP(vin0_field),
3253 SH_PFC_PIN_GROUP(vin0_clkenb),
3254 SH_PFC_PIN_GROUP(vin0_clk),
3255 SH_PFC_PIN_GROUP(vin1_data8),
3256 SH_PFC_PIN_GROUP(vin1_sync),
3257 SH_PFC_PIN_GROUP(vin1_field),
3258 SH_PFC_PIN_GROUP(vin1_clkenb),
3259 SH_PFC_PIN_GROUP(vin1_clk),
3260 VIN_DATA_PIN_GROUP(vin1_b_data, 24),
3261 VIN_DATA_PIN_GROUP(vin1_b_data, 20),
3262 SH_PFC_PIN_GROUP(vin1_b_data18),
3263 VIN_DATA_PIN_GROUP(vin1_b_data, 16),
3264 VIN_DATA_PIN_GROUP(vin1_b_data, 12),
3265 VIN_DATA_PIN_GROUP(vin1_b_data, 10),
3266 VIN_DATA_PIN_GROUP(vin1_b_data, 8),
3267 SH_PFC_PIN_GROUP(vin1_b_sync),
3268 SH_PFC_PIN_GROUP(vin1_b_field),
3269 SH_PFC_PIN_GROUP(vin1_b_clkenb),
3270 SH_PFC_PIN_GROUP(vin1_b_clk),
3271 SH_PFC_PIN_GROUP(vin2_data8),
3272 SH_PFC_PIN_GROUP(vin2_sync),
3273 SH_PFC_PIN_GROUP(vin2_field),
3274 SH_PFC_PIN_GROUP(vin2_clkenb),
3275 SH_PFC_PIN_GROUP(vin2_clk),
2801}; 3276};
2802 3277
2803static const char * const du_groups[] = { 3278static const char * const du_groups[] = {
@@ -2805,7 +3280,7 @@ static const char * const du_groups[] = {
2805 "du_rgb888", 3280 "du_rgb888",
2806 "du_clk_out_0", 3281 "du_clk_out_0",
2807 "du_clk_out_1", 3282 "du_clk_out_1",
2808 "du_sync_1", 3283 "du_sync",
2809 "du_cde_disp", 3284 "du_cde_disp",
2810}; 3285};
2811 3286
@@ -2815,6 +3290,8 @@ static const char * const du0_groups[] = {
2815 3290
2816static const char * const du1_groups[] = { 3291static const char * const du1_groups[] = {
2817 "du1_clk_in", 3292 "du1_clk_in",
3293 "du1_clk_in_b",
3294 "du1_clk_in_c",
2818}; 3295};
2819 3296
2820static const char * const eth_groups[] = { 3297static const char * const eth_groups[] = {
@@ -2824,6 +3301,40 @@ static const char * const eth_groups[] = {
2824 "eth_rmii", 3301 "eth_rmii",
2825}; 3302};
2826 3303
3304static const char * const i2c0_groups[] = {
3305 "i2c0",
3306 "i2c0_b",
3307 "i2c0_c",
3308};
3309
3310static const char * const i2c1_groups[] = {
3311 "i2c1",
3312 "i2c1_b",
3313 "i2c1_c",
3314 "i2c1_d",
3315 "i2c1_e",
3316};
3317
3318static const char * const i2c2_groups[] = {
3319 "i2c2",
3320 "i2c2_b",
3321 "i2c2_c",
3322 "i2c2_d",
3323};
3324
3325static const char * const i2c3_groups[] = {
3326 "i2c3",
3327 "i2c3_b",
3328 "i2c3_c",
3329 "i2c3_d",
3330};
3331
3332static const char * const i2c4_groups[] = {
3333 "i2c4",
3334 "i2c4_b",
3335 "i2c4_c",
3336};
3337
2827static const char * const intc_groups[] = { 3338static const char * const intc_groups[] = {
2828 "intc_irq0", 3339 "intc_irq0",
2829 "intc_irq1", 3340 "intc_irq1",
@@ -2840,20 +3351,29 @@ static const char * const mmc_groups[] = {
2840 3351
2841static const char * const msiof0_groups[] = { 3352static const char * const msiof0_groups[] = {
2842 "msiof0_clk", 3353 "msiof0_clk",
2843 "msiof0_ctrl", 3354 "msiof0_sync",
2844 "msiof0_data", 3355 "msiof0_ss1",
3356 "msiof0_ss2",
3357 "msiof0_rx",
3358 "msiof0_tx",
2845}; 3359};
2846 3360
2847static const char * const msiof1_groups[] = { 3361static const char * const msiof1_groups[] = {
2848 "msiof1_clk", 3362 "msiof1_clk",
2849 "msiof1_ctrl", 3363 "msiof1_sync",
2850 "msiof1_data", 3364 "msiof1_ss1",
3365 "msiof1_ss2",
3366 "msiof1_rx",
3367 "msiof1_tx",
2851}; 3368};
2852 3369
2853static const char * const msiof2_groups[] = { 3370static const char * const msiof2_groups[] = {
2854 "msiof2_clk", 3371 "msiof2_clk",
2855 "msiof2_ctrl", 3372 "msiof2_sync",
2856 "msiof2_data", 3373 "msiof2_ss1",
3374 "msiof2_ss2",
3375 "msiof2_rx",
3376 "msiof2_tx",
2857}; 3377};
2858 3378
2859static const char * const scif0_groups[] = { 3379static const char * const scif0_groups[] = {
@@ -2989,12 +3509,51 @@ static const char * const sdhi2_groups[] = {
2989}; 3509};
2990 3510
2991static const char * const usb0_groups[] = { 3511static const char * const usb0_groups[] = {
2992 "usb0_pwen", 3512 "usb0",
2993 "usb0_ovc",
2994}; 3513};
2995static const char * const usb1_groups[] = { 3514static const char * const usb1_groups[] = {
2996 "usb1_pwen", 3515 "usb1",
2997 "usb1_ovc", 3516};
3517
3518static const char * const vin0_groups[] = {
3519 "vin0_data24",
3520 "vin0_data20",
3521 "vin0_data18",
3522 "vin0_data16",
3523 "vin0_data12",
3524 "vin0_data10",
3525 "vin0_data8",
3526 "vin0_sync",
3527 "vin0_field",
3528 "vin0_clkenb",
3529 "vin0_clk",
3530};
3531
3532static const char * const vin1_groups[] = {
3533 "vin1_data8",
3534 "vin1_sync",
3535 "vin1_field",
3536 "vin1_clkenb",
3537 "vin1_clk",
3538 "vin1_b_data24",
3539 "vin1_b_data20",
3540 "vin1_b_data18",
3541 "vin1_b_data16",
3542 "vin1_b_data12",
3543 "vin1_b_data10",
3544 "vin1_b_data8",
3545 "vin1_b_sync",
3546 "vin1_b_field",
3547 "vin1_b_clkenb",
3548 "vin1_b_clk",
3549};
3550
3551static const char * const vin2_groups[] = {
3552 "vin2_data8",
3553 "vin2_sync",
3554 "vin2_field",
3555 "vin2_clkenb",
3556 "vin2_clk",
2998}; 3557};
2999 3558
3000static const struct sh_pfc_function pinmux_functions[] = { 3559static const struct sh_pfc_function pinmux_functions[] = {
@@ -3002,6 +3561,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
3002 SH_PFC_FUNCTION(du0), 3561 SH_PFC_FUNCTION(du0),
3003 SH_PFC_FUNCTION(du1), 3562 SH_PFC_FUNCTION(du1),
3004 SH_PFC_FUNCTION(eth), 3563 SH_PFC_FUNCTION(eth),
3564 SH_PFC_FUNCTION(i2c0),
3565 SH_PFC_FUNCTION(i2c1),
3566 SH_PFC_FUNCTION(i2c2),
3567 SH_PFC_FUNCTION(i2c3),
3568 SH_PFC_FUNCTION(i2c4),
3005 SH_PFC_FUNCTION(intc), 3569 SH_PFC_FUNCTION(intc),
3006 SH_PFC_FUNCTION(mmc), 3570 SH_PFC_FUNCTION(mmc),
3007 SH_PFC_FUNCTION(msiof0), 3571 SH_PFC_FUNCTION(msiof0),
@@ -3027,9 +3591,12 @@ static const struct sh_pfc_function pinmux_functions[] = {
3027 SH_PFC_FUNCTION(sdhi2), 3591 SH_PFC_FUNCTION(sdhi2),
3028 SH_PFC_FUNCTION(usb0), 3592 SH_PFC_FUNCTION(usb0),
3029 SH_PFC_FUNCTION(usb1), 3593 SH_PFC_FUNCTION(usb1),
3594 SH_PFC_FUNCTION(vin0),
3595 SH_PFC_FUNCTION(vin1),
3596 SH_PFC_FUNCTION(vin2),
3030}; 3597};
3031 3598
3032static struct pinmux_cfg_reg pinmux_config_regs[] = { 3599static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3033 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 3600 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3034 GP_0_31_FN, FN_IP1_22_20, 3601 GP_0_31_FN, FN_IP1_22_20,
3035 GP_0_30_FN, FN_IP1_19_17, 3602 GP_0_30_FN, FN_IP1_19_17,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7203.c b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
index bf3d8f28768d..3bda7bafd0ab 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7203.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7203.c
@@ -702,7 +702,7 @@ static const u16 pinmux_data[] = {
702 PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11), 702 PINMUX_DATA(SSCK0_PF_MARK, PF0MD_11),
703}; 703};
704 704
705static struct sh_pfc_pin pinmux_pins[] = { 705static const struct sh_pfc_pin pinmux_pins[] = {
706 /* PA */ 706 /* PA */
707 PINMUX_GPIO(PA7), 707 PINMUX_GPIO(PA7),
708 PINMUX_GPIO(PA6), 708 PINMUX_GPIO(PA6),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7264.c b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
index 673a59503223..e1cb6dc05028 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7264.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7264.c
@@ -1071,7 +1071,7 @@ static const u16 pinmux_data[] = {
1071 PINMUX_DATA(SD_D2_MARK, PK0MD_10), 1071 PINMUX_DATA(SD_D2_MARK, PK0MD_10),
1072}; 1072};
1073 1073
1074static struct sh_pfc_pin pinmux_pins[] = { 1074static const struct sh_pfc_pin pinmux_pins[] = {
1075 /* Port A */ 1075 /* Port A */
1076 PINMUX_GPIO(PA3), 1076 PINMUX_GPIO(PA3),
1077 PINMUX_GPIO(PA2), 1077 PINMUX_GPIO(PA2),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7269.c b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
index a19b60f72b23..7a11320ad96d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7269.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7269.c
@@ -1451,7 +1451,7 @@ static const u16 pinmux_data[] = {
1451 PINMUX_DATA(PWM1A_MARK, PJ0MD_100), 1451 PINMUX_DATA(PWM1A_MARK, PJ0MD_100),
1452}; 1452};
1453 1453
1454static struct sh_pfc_pin pinmux_pins[] = { 1454static const struct sh_pfc_pin pinmux_pins[] = {
1455 /* Port A */ 1455 /* Port A */
1456 PINMUX_GPIO(PA1), 1456 PINMUX_GPIO(PA1),
1457 PINMUX_GPIO(PA0), 1457 PINMUX_GPIO(PA0),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index cc097b693820..d9158b3b2919 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -844,7 +844,7 @@ static const u16 pinmux_data[] = {
844#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) 844#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
845#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) 845#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
846 846
847static struct sh_pfc_pin pinmux_pins[] = { 847static const struct sh_pfc_pin pinmux_pins[] = {
848 /* Table 57-1 (I/O and Pull U/D) */ 848 /* Table 57-1 (I/O and Pull U/D) */
849 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1), 849 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1),
850 SH7372_PIN_O(2), SH7372_PIN_I_PD(3), 850 SH7372_PIN_O(2), SH7372_PIN_I_PD(3),
@@ -2118,17 +2118,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
2118 SH_PFC_FUNCTION(usb1), 2118 SH_PFC_FUNCTION(usb1),
2119}; 2119};
2120 2120
2121#undef PORTCR
2122#define PORTCR(nr, reg) \
2123 { \
2124 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
2125 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
2126 PORT##nr##_FN0, PORT##nr##_FN1, \
2127 PORT##nr##_FN2, PORT##nr##_FN3, \
2128 PORT##nr##_FN4, PORT##nr##_FN5, \
2129 PORT##nr##_FN6, PORT##nr##_FN7 } \
2130 }
2131
2132static const struct pinmux_cfg_reg pinmux_config_regs[] = { 2121static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2133 PORTCR(0, 0xE6051000), /* PORT0CR */ 2122 PORTCR(0, 0xE6051000), /* PORT0CR */
2134 PORTCR(1, 0xE6051001), /* PORT1CR */ 2123 PORTCR(1, 0xE6051001), /* PORT1CR */
@@ -2585,7 +2574,7 @@ static void __iomem *sh7372_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
2585 &sh7372_portcr_offsets[i]; 2574 &sh7372_portcr_offsets[i];
2586 2575
2587 if (pin <= group->end_pin) 2576 if (pin <= group->end_pin)
2588 return pfc->window->virt + group->offset + pin; 2577 return pfc->windows->virt + group->offset + pin;
2589 } 2578 }
2590 2579
2591 return NULL; 2580 return NULL;
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index 7e278a97e411..6f6ba100994d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1179,7 +1179,7 @@ static const u16 pinmux_data[] = {
1179 */ 1179 */
1180#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) 1180#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
1181 1181
1182static struct sh_pfc_pin pinmux_pins[] = { 1182static const struct sh_pfc_pin pinmux_pins[] = {
1183 /* Table 25-1 (I/O and Pull U/D) */ 1183 /* Table 25-1 (I/O and Pull U/D) */
1184 SH73A0_PIN_I_PD(0), 1184 SH73A0_PIN_I_PD(0),
1185 SH73A0_PIN_I_PU(1), 1185 SH73A0_PIN_I_PU(1),
@@ -3138,16 +3138,6 @@ static const struct sh_pfc_function pinmux_functions[] = {
3138 SH_PFC_FUNCTION(usb), 3138 SH_PFC_FUNCTION(usb),
3139}; 3139};
3140 3140
3141#undef PORTCR
3142#define PORTCR(nr, reg) \
3143 { \
3144 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
3145 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
3146 PORT##nr##_FN0, PORT##nr##_FN1, \
3147 PORT##nr##_FN2, PORT##nr##_FN3, \
3148 PORT##nr##_FN4, PORT##nr##_FN5, \
3149 PORT##nr##_FN6, PORT##nr##_FN7 } \
3150 }
3151static const struct pinmux_cfg_reg pinmux_config_regs[] = { 3141static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3152 PORTCR(0, 0xe6050000), /* PORT0CR */ 3142 PORTCR(0, 0xe6050000), /* PORT0CR */
3153 PORTCR(1, 0xe6050001), /* PORT1CR */ 3143 PORTCR(1, 0xe6050001), /* PORT1CR */
@@ -3661,38 +3651,38 @@ static const struct pinmux_data_reg pinmux_data_regs[] = {
3661}; 3651};
3662 3652
3663static const struct pinmux_irq pinmux_irqs[] = { 3653static const struct pinmux_irq pinmux_irqs[] = {
3664 PINMUX_IRQ(irq_pin(19), 9),
3665 PINMUX_IRQ(irq_pin(1), 10),
3666 PINMUX_IRQ(irq_pin(0), 11), 3654 PINMUX_IRQ(irq_pin(0), 11),
3655 PINMUX_IRQ(irq_pin(1), 10),
3656 PINMUX_IRQ(irq_pin(2), 149),
3657 PINMUX_IRQ(irq_pin(3), 224),
3658 PINMUX_IRQ(irq_pin(4), 159),
3659 PINMUX_IRQ(irq_pin(5), 227),
3660 PINMUX_IRQ(irq_pin(6), 147),
3661 PINMUX_IRQ(irq_pin(7), 150),
3662 PINMUX_IRQ(irq_pin(8), 223),
3663 PINMUX_IRQ(irq_pin(9), 56, 308),
3664 PINMUX_IRQ(irq_pin(10), 54),
3665 PINMUX_IRQ(irq_pin(11), 238),
3666 PINMUX_IRQ(irq_pin(12), 156),
3667 PINMUX_IRQ(irq_pin(13), 239),
3668 PINMUX_IRQ(irq_pin(14), 251),
3669 PINMUX_IRQ(irq_pin(15), 0),
3670 PINMUX_IRQ(irq_pin(16), 249),
3671 PINMUX_IRQ(irq_pin(17), 234),
3667 PINMUX_IRQ(irq_pin(18), 13), 3672 PINMUX_IRQ(irq_pin(18), 13),
3673 PINMUX_IRQ(irq_pin(19), 9),
3668 PINMUX_IRQ(irq_pin(20), 14), 3674 PINMUX_IRQ(irq_pin(20), 14),
3669 PINMUX_IRQ(irq_pin(21), 15), 3675 PINMUX_IRQ(irq_pin(21), 15),
3670 PINMUX_IRQ(irq_pin(31), 26),
3671 PINMUX_IRQ(irq_pin(30), 27),
3672 PINMUX_IRQ(irq_pin(29), 28),
3673 PINMUX_IRQ(irq_pin(22), 40), 3676 PINMUX_IRQ(irq_pin(22), 40),
3674 PINMUX_IRQ(irq_pin(23), 53), 3677 PINMUX_IRQ(irq_pin(23), 53),
3675 PINMUX_IRQ(irq_pin(10), 54), 3678 PINMUX_IRQ(irq_pin(24), 118),
3676 PINMUX_IRQ(irq_pin(9), 56), 3679 PINMUX_IRQ(irq_pin(25), 164),
3677 PINMUX_IRQ(irq_pin(26), 115), 3680 PINMUX_IRQ(irq_pin(26), 115),
3678 PINMUX_IRQ(irq_pin(27), 116), 3681 PINMUX_IRQ(irq_pin(27), 116),
3679 PINMUX_IRQ(irq_pin(28), 117), 3682 PINMUX_IRQ(irq_pin(28), 117),
3680 PINMUX_IRQ(irq_pin(24), 118), 3683 PINMUX_IRQ(irq_pin(29), 28),
3681 PINMUX_IRQ(irq_pin(6), 147), 3684 PINMUX_IRQ(irq_pin(30), 27),
3682 PINMUX_IRQ(irq_pin(2), 149), 3685 PINMUX_IRQ(irq_pin(31), 26),
3683 PINMUX_IRQ(irq_pin(7), 150),
3684 PINMUX_IRQ(irq_pin(12), 156),
3685 PINMUX_IRQ(irq_pin(4), 159),
3686 PINMUX_IRQ(irq_pin(25), 164),
3687 PINMUX_IRQ(irq_pin(8), 223),
3688 PINMUX_IRQ(irq_pin(3), 224),
3689 PINMUX_IRQ(irq_pin(5), 227),
3690 PINMUX_IRQ(irq_pin(17), 234),
3691 PINMUX_IRQ(irq_pin(11), 238),
3692 PINMUX_IRQ(irq_pin(13), 239),
3693 PINMUX_IRQ(irq_pin(16), 249),
3694 PINMUX_IRQ(irq_pin(14), 251),
3695 PINMUX_IRQ(irq_pin(9), 308),
3696}; 3686};
3697 3687
3698/* ----------------------------------------------------------------------------- 3688/* -----------------------------------------------------------------------------
@@ -3702,7 +3692,7 @@ static const struct pinmux_irq pinmux_irqs[] = {
3702static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable) 3692static void sh73a0_vccq_mc0_endisable(struct regulator_dev *reg, bool enable)
3703{ 3693{
3704 struct sh_pfc *pfc = reg->reg_data; 3694 struct sh_pfc *pfc = reg->reg_data;
3705 void __iomem *addr = pfc->window[1].virt + 4; 3695 void __iomem *addr = pfc->windows[1].virt + 4;
3706 unsigned long flags; 3696 unsigned long flags;
3707 u32 value; 3697 u32 value;
3708 3698
@@ -3735,7 +3725,7 @@ static int sh73a0_vccq_mc0_disable(struct regulator_dev *reg)
3735static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg) 3725static int sh73a0_vccq_mc0_is_enabled(struct regulator_dev *reg)
3736{ 3726{
3737 struct sh_pfc *pfc = reg->reg_data; 3727 struct sh_pfc *pfc = reg->reg_data;
3738 void __iomem *addr = pfc->window[1].virt + 4; 3728 void __iomem *addr = pfc->windows[1].virt + 4;
3739 unsigned long flags; 3729 unsigned long flags;
3740 u32 value; 3730 u32 value;
3741 3731
@@ -3794,7 +3784,7 @@ static const unsigned int sh73a0_portcr_offsets[] = {
3794 3784
3795static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin) 3785static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3796{ 3786{
3797 void __iomem *addr = pfc->window->virt 3787 void __iomem *addr = pfc->windows->virt
3798 + sh73a0_portcr_offsets[pin >> 5] + pin; 3788 + sh73a0_portcr_offsets[pin >> 5] + pin;
3799 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK; 3789 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3800 3790
@@ -3812,7 +3802,7 @@ static unsigned int sh73a0_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3812static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin, 3802static void sh73a0_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3813 unsigned int bias) 3803 unsigned int bias)
3814{ 3804{
3815 void __iomem *addr = pfc->window->virt 3805 void __iomem *addr = pfc->windows->virt
3816 + sh73a0_portcr_offsets[pin >> 5] + pin; 3806 + sh73a0_portcr_offsets[pin >> 5] + pin;
3817 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK; 3807 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3818 3808
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7720.c b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
index 7a26809eda15..13d05f88bc01 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7720.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7720.c
@@ -576,7 +576,7 @@ static const u16 pinmux_data[] = {
576 PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN), 576 PINMUX_DATA(SIM_CLK_MARK, PSELD_1_0_10, PTV0_FN),
577}; 577};
578 578
579static struct sh_pfc_pin pinmux_pins[] = { 579static const struct sh_pfc_pin pinmux_pins[] = {
580 /* PTA */ 580 /* PTA */
581 PINMUX_GPIO(PTA7), 581 PINMUX_GPIO(PTA7),
582 PINMUX_GPIO(PTA6), 582 PINMUX_GPIO(PTA6),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7722.c b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
index add309347b05..914d872c37a4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7722.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7722.c
@@ -754,7 +754,7 @@ static const u16 pinmux_data[] = {
754 PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5), 754 PINMUX_DATA(KEYOUT5_IN5_MARK, HIZA14_KEYSC, KEYOUT5_IN5),
755}; 755};
756 756
757static struct sh_pfc_pin pinmux_pins[] = { 757static const struct sh_pfc_pin pinmux_pins[] = {
758 /* PTA */ 758 /* PTA */
759 PINMUX_GPIO(PTA7), 759 PINMUX_GPIO(PTA7),
760 PINMUX_GPIO(PTA6), 760 PINMUX_GPIO(PTA6),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7723.c b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
index 1cecc9101a52..4eb7eae2e6d0 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7723.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7723.c
@@ -917,7 +917,7 @@ static const u16 pinmux_data[] = {
917 PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN), 917 PINMUX_DATA(SIUBISLD_MARK, PSD1_PSD0_FN2, PTZ0_FN),
918}; 918};
919 919
920static struct sh_pfc_pin pinmux_pins[] = { 920static const struct sh_pfc_pin pinmux_pins[] = {
921 /* PTA */ 921 /* PTA */
922 PINMUX_GPIO(PTA7), 922 PINMUX_GPIO(PTA7),
923 PINMUX_GPIO(PTA6), 923 PINMUX_GPIO(PTA6),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7724.c b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
index 1085ab556b8e..74a1a7f1317c 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7724.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7724.c
@@ -1146,7 +1146,7 @@ static const u16 pinmux_data[] = {
1146 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN), 1146 PINMUX_DATA(SCIF3_I_TXD_MARK, PSB14_1, PTZ3_FN),
1147}; 1147};
1148 1148
1149static struct sh_pfc_pin pinmux_pins[] = { 1149static const struct sh_pfc_pin pinmux_pins[] = {
1150 /* PTA */ 1150 /* PTA */
1151 PINMUX_GPIO(PTA7), 1151 PINMUX_GPIO(PTA7),
1152 PINMUX_GPIO(PTA6), 1152 PINMUX_GPIO(PTA6),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7734.c b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
index ec0c47c4f100..e53dd1cb1625 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7734.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7734.c
@@ -1357,7 +1357,7 @@ static const u16 pinmux_data[] = {
1357 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT), 1357 PINMUX_IPSR_DATA(IP11_28, ST_CLKOUT),
1358}; 1358};
1359 1359
1360static struct sh_pfc_pin pinmux_pins[] = { 1360static const struct sh_pfc_pin pinmux_pins[] = {
1361 PINMUX_GPIO_GP_ALL(), 1361 PINMUX_GPIO_GP_ALL(),
1362}; 1362};
1363 1363
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7757.c b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
index 33d75e510911..625661a88c52 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7757.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7757.c
@@ -1074,7 +1074,7 @@ static const u16 pinmux_data[] = {
1074 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN), 1074 PINMUX_DATA(ON_DQ0_MARK, PS8_8_FN2, PTZ0_FN),
1075}; 1075};
1076 1076
1077static struct sh_pfc_pin pinmux_pins[] = { 1077static const struct sh_pfc_pin pinmux_pins[] = {
1078 /* PTA */ 1078 /* PTA */
1079 PINMUX_GPIO(PTA7), 1079 PINMUX_GPIO(PTA7),
1080 PINMUX_GPIO(PTA6), 1080 PINMUX_GPIO(PTA6),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7785.c b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
index 517eb49d76bd..b38dd7e3e375 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7785.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7785.c
@@ -671,7 +671,7 @@ static const u16 pinmux_data[] = {
671 PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1), 671 PINMUX_DATA(IRQOUT_MARK, P2MSEL2_1),
672}; 672};
673 673
674static struct sh_pfc_pin pinmux_pins[] = { 674static const struct sh_pfc_pin pinmux_pins[] = {
675 /* PA */ 675 /* PA */
676 PINMUX_GPIO(PA7), 676 PINMUX_GPIO(PA7),
677 PINMUX_GPIO(PA6), 677 PINMUX_GPIO(PA6),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7786.c b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
index 623345fac936..6cb4e0aaf20b 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7786.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7786.c
@@ -407,7 +407,7 @@ static const u16 pinmux_data[] = {
407 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN), 407 PINMUX_DATA(SSI3_SCK_MARK, P2MSEL6_1, P2MSEL5_1, PJ1_FN),
408}; 408};
409 409
410static struct sh_pfc_pin pinmux_pins[] = { 410static const struct sh_pfc_pin pinmux_pins[] = {
411 /* PA */ 411 /* PA */
412 PINMUX_GPIO(PA7), 412 PINMUX_GPIO(PA7),
413 PINMUX_GPIO(PA6), 413 PINMUX_GPIO(PA6),
diff --git a/drivers/pinctrl/sh-pfc/pfc-shx3.c b/drivers/pinctrl/sh-pfc/pfc-shx3.c
index 55262bd869ed..a3fcb2284d91 100644
--- a/drivers/pinctrl/sh-pfc/pfc-shx3.c
+++ b/drivers/pinctrl/sh-pfc/pfc-shx3.c
@@ -285,7 +285,7 @@ static const u16 pinmux_data[] = {
285 PINMUX_DATA(IRQOUT_MARK, PH0_FN), 285 PINMUX_DATA(IRQOUT_MARK, PH0_FN),
286}; 286};
287 287
288static struct sh_pfc_pin pinmux_pins[] = { 288static const struct sh_pfc_pin pinmux_pins[] = {
289 /* PA */ 289 /* PA */
290 PINMUX_GPIO(PA7), 290 PINMUX_GPIO(PA7),
291 PINMUX_GPIO(PA6), 291 PINMUX_GPIO(PA6),
diff --git a/drivers/pinctrl/sh-pfc/sh_pfc.h b/drivers/pinctrl/sh-pfc/sh_pfc.h
index e2142956a8e5..ab8fd258d9ed 100644
--- a/drivers/pinctrl/sh-pfc/sh_pfc.h
+++ b/drivers/pinctrl/sh-pfc/sh_pfc.h
@@ -76,12 +76,13 @@ struct pinmux_cfg_reg {
76 76
77#define PINMUX_CFG_REG(name, r, r_width, f_width) \ 77#define PINMUX_CFG_REG(name, r, r_width, f_width) \
78 .reg = r, .reg_width = r_width, .field_width = f_width, \ 78 .reg = r, .reg_width = r_width, .field_width = f_width, \
79 .enum_ids = (u16 [(r_width / f_width) * (1 << f_width)]) 79 .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)])
80 80
81#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \ 81#define PINMUX_CFG_REG_VAR(name, r, r_width, var_fw0, var_fwn...) \
82 .reg = r, .reg_width = r_width, \ 82 .reg = r, .reg_width = r_width, \
83 .var_field_width = (unsigned long [r_width]) { var_fw0, var_fwn, 0 }, \ 83 .var_field_width = (const unsigned long [r_width]) \
84 .enum_ids = (u16 []) 84 { var_fw0, var_fwn, 0 }, \
85 .enum_ids = (const u16 [])
85 86
86struct pinmux_data_reg { 87struct pinmux_data_reg {
87 unsigned long reg, reg_width; 88 unsigned long reg, reg_width;
@@ -90,15 +91,15 @@ struct pinmux_data_reg {
90 91
91#define PINMUX_DATA_REG(name, r, r_width) \ 92#define PINMUX_DATA_REG(name, r, r_width) \
92 .reg = r, .reg_width = r_width, \ 93 .reg = r, .reg_width = r_width, \
93 .enum_ids = (u16 [r_width]) \ 94 .enum_ids = (const u16 [r_width]) \
94 95
95struct pinmux_irq { 96struct pinmux_irq {
96 int irq; 97 int irq;
97 unsigned short *gpios; 98 const short *gpios;
98}; 99};
99 100
100#define PINMUX_IRQ(irq_nr, ids...) \ 101#define PINMUX_IRQ(irq_nr, ids...) \
101 { .irq = irq_nr, .gpios = (unsigned short []) { ids, 0 } } \ 102 { .irq = irq_nr, .gpios = (const short []) { ids, -1 } }
102 103
103struct pinmux_range { 104struct pinmux_range {
104 u16 begin; 105 u16 begin;
@@ -304,8 +305,7 @@ struct sh_pfc_soc_info {
304#define PORTCR(nr, reg) \ 305#define PORTCR(nr, reg) \
305 { \ 306 { \
306 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \ 307 PINMUX_CFG_REG("PORT" nr "CR", reg, 8, 4) { \
307 _PCRH(PORT##nr##_IN, PORT##nr##_IN_PD, \ 308 _PCRH(PORT##nr##_IN, 0, 0, PORT##nr##_OUT), \
308 PORT##nr##_IN_PU, PORT##nr##_OUT), \
309 PORT##nr##_FN0, PORT##nr##_FN1, \ 309 PORT##nr##_FN0, PORT##nr##_FN1, \
310 PORT##nr##_FN2, PORT##nr##_FN3, \ 310 PORT##nr##_FN2, PORT##nr##_FN3, \
311 PORT##nr##_FN4, PORT##nr##_FN5, \ 311 PORT##nr##_FN4, PORT##nr##_FN5, \
diff --git a/drivers/pinctrl/sirf/pinctrl-atlas6.c b/drivers/pinctrl/sirf/pinctrl-atlas6.c
index 8ab7898d21be..2b9f32065920 100644
--- a/drivers/pinctrl/sirf/pinctrl-atlas6.c
+++ b/drivers/pinctrl/sirf/pinctrl-atlas6.c
@@ -562,6 +562,23 @@ static const struct sirfsoc_padmux usp1_padmux = {
562 562
563static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 }; 563static const unsigned usp1_pins[] = { 15, 43, 44, 45, 46 };
564 564
565static const struct sirfsoc_muxmask usp1_uart_nostreamctrl_muxmask[] = {
566 {
567 .group = 1,
568 .mask = BIT(12) | BIT(13),
569 },
570};
571
572static const struct sirfsoc_padmux usp1_uart_nostreamctrl_padmux = {
573 .muxmask_counts = ARRAY_SIZE(usp1_uart_nostreamctrl_muxmask),
574 .muxmask = usp1_uart_nostreamctrl_muxmask,
575 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
576 .funcmask = BIT(16),
577 .funcval = BIT(16),
578};
579
580static const unsigned usp1_uart_nostreamctrl_pins[] = { 44, 45 };
581
565static const struct sirfsoc_muxmask nand_muxmask[] = { 582static const struct sirfsoc_muxmask nand_muxmask[] = {
566 { 583 {
567 .group = 2, 584 .group = 2,
@@ -889,6 +906,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
889 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", 906 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
890 usp0_uart_nostreamctrl_pins), 907 usp0_uart_nostreamctrl_pins),
891 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), 908 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
909 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
910 usp1_uart_nostreamctrl_pins),
892 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins), 911 SIRFSOC_PIN_GROUP("i2c0grp", i2c0_pins),
893 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins), 912 SIRFSOC_PIN_GROUP("i2c1grp", i2c1_pins),
894 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins), 913 SIRFSOC_PIN_GROUP("pwm0grp", pwm0_pins),
@@ -935,6 +954,8 @@ static const char * const usp0_uart_nostreamctrl_grp[] = {
935 "usp0_uart_nostreamctrl_grp" }; 954 "usp0_uart_nostreamctrl_grp" };
936static const char * const usp0grp[] = { "usp0grp" }; 955static const char * const usp0grp[] = { "usp0grp" };
937static const char * const usp1grp[] = { "usp1grp" }; 956static const char * const usp1grp[] = { "usp1grp" };
957static const char * const usp1_uart_nostreamctrl_grp[] = {
958 "usp1_uart_nostreamctrl_grp" };
938static const char * const i2c0grp[] = { "i2c0grp" }; 959static const char * const i2c0grp[] = { "i2c0grp" };
939static const char * const i2c1grp[] = { "i2c1grp" }; 960static const char * const i2c1grp[] = { "i2c1grp" };
940static const char * const pwm0grp[] = { "pwm0grp" }; 961static const char * const pwm0grp[] = { "pwm0grp" };
@@ -983,6 +1004,9 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
983 usp0_uart_nostreamctrl_grp, 1004 usp0_uart_nostreamctrl_grp,
984 usp0_uart_nostreamctrl_padmux), 1005 usp0_uart_nostreamctrl_padmux),
985 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), 1006 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
1007 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
1008 usp1_uart_nostreamctrl_grp,
1009 usp1_uart_nostreamctrl_padmux),
986 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux), 1010 SIRFSOC_PMX_FUNCTION("i2c0", i2c0grp, i2c0_padmux),
987 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux), 1011 SIRFSOC_PMX_FUNCTION("i2c1", i2c1grp, i2c1_padmux),
988 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux), 1012 SIRFSOC_PMX_FUNCTION("pwm0", pwm0grp, pwm0_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-prima2.c b/drivers/pinctrl/sirf/pinctrl-prima2.c
index 050777be0f1e..37b42651d76a 100644
--- a/drivers/pinctrl/sirf/pinctrl-prima2.c
+++ b/drivers/pinctrl/sirf/pinctrl-prima2.c
@@ -467,12 +467,6 @@ static const struct sirfsoc_muxmask sdmmc5_muxmask[] = {
467 { 467 {
468 .group = 0, 468 .group = 0,
469 .mask = BIT(24) | BIT(25) | BIT(26), 469 .mask = BIT(24) | BIT(25) | BIT(26),
470 }, {
471 .group = 1,
472 .mask = BIT(29),
473 }, {
474 .group = 2,
475 .mask = BIT(0) | BIT(1),
476 }, 470 },
477}; 471};
478 472
@@ -484,7 +478,7 @@ static const struct sirfsoc_padmux sdmmc5_padmux = {
484 .funcval = BIT(13) | BIT(14), 478 .funcval = BIT(13) | BIT(14),
485}; 479};
486 480
487static const unsigned sdmmc5_pins[] = { 24, 25, 26, 61, 64, 65 }; 481static const unsigned sdmmc5_pins[] = { 24, 25, 26 };
488 482
489static const struct sirfsoc_muxmask usp0_muxmask[] = { 483static const struct sirfsoc_muxmask usp0_muxmask[] = {
490 { 484 {
@@ -503,6 +497,40 @@ static const struct sirfsoc_padmux usp0_padmux = {
503 497
504static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 }; 498static const unsigned usp0_pins[] = { 51, 52, 53, 54, 55 };
505 499
500static const struct sirfsoc_muxmask usp0_only_utfs_muxmask[] = {
501 {
502 .group = 1,
503 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(22),
504 },
505};
506
507static const struct sirfsoc_padmux usp0_only_utfs_padmux = {
508 .muxmask_counts = ARRAY_SIZE(usp0_only_utfs_muxmask),
509 .muxmask = usp0_only_utfs_muxmask,
510 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
511 .funcmask = BIT(1) | BIT(2) | BIT(6),
512 .funcval = 0,
513};
514
515static const unsigned usp0_only_utfs_pins[] = { 51, 52, 53, 54 };
516
517static const struct sirfsoc_muxmask usp0_only_urfs_muxmask[] = {
518 {
519 .group = 1,
520 .mask = BIT(19) | BIT(20) | BIT(21) | BIT(23),
521 },
522};
523
524static const struct sirfsoc_padmux usp0_only_urfs_padmux = {
525 .muxmask_counts = ARRAY_SIZE(usp0_only_urfs_muxmask),
526 .muxmask = usp0_only_urfs_muxmask,
527 .ctrlreg = SIRFSOC_RSC_PIN_MUX,
528 .funcmask = BIT(1) | BIT(2) | BIT(9),
529 .funcval = 0,
530};
531
532static const unsigned usp0_only_urfs_pins[] = { 51, 52, 53, 55 };
533
506static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = { 534static const struct sirfsoc_muxmask usp0_uart_nostreamctrl_muxmask[] = {
507 { 535 {
508 .group = 1, 536 .group = 1,
@@ -859,6 +887,8 @@ static const struct sirfsoc_pin_group sirfsoc_pin_groups[] = {
859 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins), 887 SIRFSOC_PIN_GROUP("usp0grp", usp0_pins),
860 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp", 888 SIRFSOC_PIN_GROUP("usp0_uart_nostreamctrl_grp",
861 usp0_uart_nostreamctrl_pins), 889 usp0_uart_nostreamctrl_pins),
890 SIRFSOC_PIN_GROUP("usp0_only_utfs_grp", usp0_only_utfs_pins),
891 SIRFSOC_PIN_GROUP("usp0_only_urfs_grp", usp0_only_urfs_pins),
862 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins), 892 SIRFSOC_PIN_GROUP("usp1grp", usp1_pins),
863 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp", 893 SIRFSOC_PIN_GROUP("usp1_uart_nostreamctrl_grp",
864 usp1_uart_nostreamctrl_pins), 894 usp1_uart_nostreamctrl_pins),
@@ -907,6 +937,8 @@ static const char * const uart2_nostreamctrlgrp[] = { "uart2_nostreamctrlgrp" };
907static const char * const usp0grp[] = { "usp0grp" }; 937static const char * const usp0grp[] = { "usp0grp" };
908static const char * const usp0_uart_nostreamctrl_grp[] = 938static const char * const usp0_uart_nostreamctrl_grp[] =
909 { "usp0_uart_nostreamctrl_grp" }; 939 { "usp0_uart_nostreamctrl_grp" };
940static const char * const usp0_only_utfs_grp[] = { "usp0_only_utfs_grp" };
941static const char * const usp0_only_urfs_grp[] = { "usp0_only_urfs_grp" };
910static const char * const usp1grp[] = { "usp1grp" }; 942static const char * const usp1grp[] = { "usp1grp" };
911static const char * const usp1_uart_nostreamctrl_grp[] = 943static const char * const usp1_uart_nostreamctrl_grp[] =
912 { "usp1_uart_nostreamctrl_grp" }; 944 { "usp1_uart_nostreamctrl_grp" };
@@ -955,6 +987,8 @@ static const struct sirfsoc_pmx_func sirfsoc_pmx_functions[] = {
955 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux), 987 SIRFSOC_PMX_FUNCTION("usp0", usp0grp, usp0_padmux),
956 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl", 988 SIRFSOC_PMX_FUNCTION("usp0_uart_nostreamctrl",
957 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux), 989 usp0_uart_nostreamctrl_grp, usp0_uart_nostreamctrl_padmux),
990 SIRFSOC_PMX_FUNCTION("usp0_only_utfs", usp0_only_utfs_grp, usp0_only_utfs_padmux),
991 SIRFSOC_PMX_FUNCTION("usp0_only_urfs", usp0_only_urfs_grp, usp0_only_urfs_padmux),
958 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux), 992 SIRFSOC_PMX_FUNCTION("usp1", usp1grp, usp1_padmux),
959 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl", 993 SIRFSOC_PMX_FUNCTION("usp1_uart_nostreamctrl",
960 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux), 994 usp1_uart_nostreamctrl_grp, usp1_uart_nostreamctrl_padmux),
diff --git a/drivers/pinctrl/sirf/pinctrl-sirf.c b/drivers/pinctrl/sirf/pinctrl-sirf.c
index b81e388c50de..a0d6152701cd 100644
--- a/drivers/pinctrl/sirf/pinctrl-sirf.c
+++ b/drivers/pinctrl/sirf/pinctrl-sirf.c
@@ -468,7 +468,8 @@ static inline int sirfsoc_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
468 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip), 468 struct sirfsoc_gpio_bank *bank = container_of(to_of_mm_gpio_chip(chip),
469 struct sirfsoc_gpio_bank, chip); 469 struct sirfsoc_gpio_bank, chip);
470 470
471 return irq_create_mapping(bank->domain, offset); 471 return irq_create_mapping(bank->domain, offset + bank->id *
472 SIRFSOC_GPIO_BANK_SIZE);
472} 473}
473 474
474static inline int sirfsoc_gpio_to_offset(unsigned int gpio) 475static inline int sirfsoc_gpio_to_offset(unsigned int gpio)
@@ -559,7 +560,7 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
559 spin_lock_irqsave(&sgpio_lock, flags); 560 spin_lock_irqsave(&sgpio_lock, flags);
560 561
561 val = readl(bank->chip.regs + offset); 562 val = readl(bank->chip.regs + offset);
562 val &= ~SIRFSOC_GPIO_CTL_INTR_STS_MASK; 563 val &= ~(SIRFSOC_GPIO_CTL_INTR_STS_MASK | SIRFSOC_GPIO_CTL_OUT_EN_MASK);
563 564
564 switch (type) { 565 switch (type) {
565 case IRQ_TYPE_NONE: 566 case IRQ_TYPE_NONE:
@@ -593,12 +594,34 @@ static int sirfsoc_gpio_irq_type(struct irq_data *d, unsigned type)
593 return 0; 594 return 0;
594} 595}
595 596
597static unsigned int sirfsoc_gpio_irq_startup(struct irq_data *d)
598{
599 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
600
601 if (gpio_lock_as_irq(&bank->chip.gc, d->hwirq))
602 dev_err(bank->chip.gc.dev,
603 "unable to lock HW IRQ %lu for IRQ\n",
604 d->hwirq);
605 sirfsoc_gpio_irq_unmask(d);
606 return 0;
607}
608
609static void sirfsoc_gpio_irq_shutdown(struct irq_data *d)
610{
611 struct sirfsoc_gpio_bank *bank = irq_data_get_irq_chip_data(d);
612
613 sirfsoc_gpio_irq_mask(d);
614 gpio_unlock_as_irq(&bank->chip.gc, d->hwirq);
615}
616
596static struct irq_chip sirfsoc_irq_chip = { 617static struct irq_chip sirfsoc_irq_chip = {
597 .name = "sirf-gpio-irq", 618 .name = "sirf-gpio-irq",
598 .irq_ack = sirfsoc_gpio_irq_ack, 619 .irq_ack = sirfsoc_gpio_irq_ack,
599 .irq_mask = sirfsoc_gpio_irq_mask, 620 .irq_mask = sirfsoc_gpio_irq_mask,
600 .irq_unmask = sirfsoc_gpio_irq_unmask, 621 .irq_unmask = sirfsoc_gpio_irq_unmask,
601 .irq_set_type = sirfsoc_gpio_irq_type, 622 .irq_set_type = sirfsoc_gpio_irq_type,
623 .irq_startup = sirfsoc_gpio_irq_startup,
624 .irq_shutdown = sirfsoc_gpio_irq_shutdown,
602}; 625};
603 626
604static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc) 627static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
@@ -629,7 +652,8 @@ static void sirfsoc_gpio_handle_irq(unsigned int irq, struct irq_desc *desc)
629 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) { 652 if ((status & 0x1) && (ctrl & SIRFSOC_GPIO_CTL_INTR_EN_MASK)) {
630 pr_debug("%s: gpio id %d idx %d happens\n", 653 pr_debug("%s: gpio id %d idx %d happens\n",
631 __func__, bank->id, idx); 654 __func__, bank->id, idx);
632 generic_handle_irq(irq_find_mapping(bank->domain, idx)); 655 generic_handle_irq(irq_find_mapping(bank->domain, idx +
656 bank->id * SIRFSOC_GPIO_BANK_SIZE));
633 } 657 }
634 658
635 idx++; 659 idx++;
@@ -786,7 +810,7 @@ static int sirfsoc_gpio_irq_map(struct irq_domain *d, unsigned int irq,
786 810
787 irq_set_chip(irq, &sirfsoc_irq_chip); 811 irq_set_chip(irq, &sirfsoc_irq_chip);
788 irq_set_handler(irq, handle_level_irq); 812 irq_set_handler(irq, handle_level_irq);
789 irq_set_chip_data(irq, bank); 813 irq_set_chip_data(irq, bank + hwirq / SIRFSOC_GPIO_BANK_SIZE);
790 set_irq_flags(irq, IRQF_VALID); 814 set_irq_flags(irq, IRQF_VALID);
791 815
792 return 0; 816 return 0;
@@ -835,6 +859,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
835 struct sirfsoc_gpio_bank *bank; 859 struct sirfsoc_gpio_bank *bank;
836 void __iomem *regs; 860 void __iomem *regs;
837 struct platform_device *pdev; 861 struct platform_device *pdev;
862 struct irq_domain *domain;
838 bool is_marco = false; 863 bool is_marco = false;
839 864
840 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS]; 865 u32 pullups[SIRFSOC_GPIO_NO_OF_BANKS], pulldowns[SIRFSOC_GPIO_NO_OF_BANKS];
@@ -850,6 +875,14 @@ static int sirfsoc_gpio_probe(struct device_node *np)
850 if (of_device_is_compatible(np, "sirf,marco-pinctrl")) 875 if (of_device_is_compatible(np, "sirf,marco-pinctrl"))
851 is_marco = 1; 876 is_marco = 1;
852 877
878 domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE * SIRFSOC_GPIO_NO_OF_BANKS,
879 &sirfsoc_gpio_irq_simple_ops, sgpio_bank);
880 if (!domain) {
881 pr_err("%s: Failed to create irqdomain\n", np->full_name);
882 err = -ENOSYS;
883 goto out;
884 }
885
853 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) { 886 for (i = 0; i < SIRFSOC_GPIO_NO_OF_BANKS; i++) {
854 bank = &sgpio_bank[i]; 887 bank = &sgpio_bank[i];
855 spin_lock_init(&bank->lock); 888 spin_lock_init(&bank->lock);
@@ -866,6 +899,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
866 bank->chip.gc.of_node = np; 899 bank->chip.gc.of_node = np;
867 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate; 900 bank->chip.gc.of_xlate = sirfsoc_gpio_of_xlate;
868 bank->chip.gc.of_gpio_n_cells = 2; 901 bank->chip.gc.of_gpio_n_cells = 2;
902 bank->chip.gc.dev = &pdev->dev;
869 bank->chip.regs = regs; 903 bank->chip.regs = regs;
870 bank->id = i; 904 bank->id = i;
871 bank->is_marco = is_marco; 905 bank->is_marco = is_marco;
@@ -882,14 +916,7 @@ static int sirfsoc_gpio_probe(struct device_node *np)
882 goto out; 916 goto out;
883 } 917 }
884 918
885 bank->domain = irq_domain_add_linear(np, SIRFSOC_GPIO_BANK_SIZE, 919 bank->domain = domain;
886 &sirfsoc_gpio_irq_simple_ops, bank);
887
888 if (!bank->domain) {
889 pr_err("%s: Failed to create irqdomain\n", np->full_name);
890 err = -ENOSYS;
891 goto out;
892 }
893 920
894 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq); 921 irq_set_chained_handler(bank->parent_irq, sirfsoc_gpio_handle_irq);
895 irq_set_handler_data(bank->parent_irq, bank); 922 irq_set_handler_data(bank->parent_irq, bank);
generated by cgit v1.2.2 (git 2.25.0) at 2025-02-02 17:47:40 -0500