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-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a73a4.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7740.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7778.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7779.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7790.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-r8a7791.c4
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh7372.c2
-rw-r--r--drivers/pinctrl/sh-pfc/pfc-sh73a0.c2
8 files changed, 11 insertions, 11 deletions
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
index 32dd478f28e3..d39ca87353e4 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a73a4.c
@@ -1272,7 +1272,7 @@ static const u16 pinmux_data[] = {
1272#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD) 1272#define R8A73A4_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1273#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) 1273#define R8A73A4_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1274 1274
1275static struct sh_pfc_pin pinmux_pins[] = { 1275static const struct sh_pfc_pin pinmux_pins[] = {
1276 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1), 1276 R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1277 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3), 1277 R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1278 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5), 1278 R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
index a189b962a1eb..f4d30246460f 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7740.c
@@ -1543,7 +1543,7 @@ static const u16 pinmux_data[] = {
1543#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) 1543#define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1544#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) 1544#define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
1545 1545
1546static struct sh_pfc_pin pinmux_pins[] = { 1546static const struct sh_pfc_pin pinmux_pins[] = {
1547 /* Table 56-1 (I/O and Pull U/D) */ 1547 /* Table 56-1 (I/O and Pull U/D) */
1548 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1), 1548 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1549 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3), 1549 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
index 8b1881c20598..c7d610d1f3ef 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7778.c
@@ -1260,7 +1260,7 @@ static const u16 pinmux_data[] = {
1260 */ 1260 */
1261#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1) 1261#define PIN_NUMBER(row, col) (1000+((row)-1)*25+(col)-1)
1262 1262
1263static struct sh_pfc_pin pinmux_pins[] = { 1263static const struct sh_pfc_pin pinmux_pins[] = {
1264 PINMUX_GPIO_GP_ALL(), 1264 PINMUX_GPIO_GP_ALL(),
1265 1265
1266 /* Pins not associated with a GPIO port */ 1266 /* Pins not associated with a GPIO port */
@@ -2104,7 +2104,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
2104 SH_PFC_FUNCTION(vin1), 2104 SH_PFC_FUNCTION(vin1),
2105}; 2105};
2106 2106
2107static struct pinmux_cfg_reg pinmux_config_regs[] = { 2107static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2108 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) { 2108 { PINMUX_CFG_REG("GPSR0", 0xfffc0004, 32, 1) {
2109 GP_0_31_FN, FN_IP1_14_11, 2109 GP_0_31_FN, FN_IP1_14_11,
2110 GP_0_30_FN, FN_IP1_10_8, 2110 GP_0_30_FN, FN_IP1_10_8,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
index d3e94e307d7f..f5c01e1e2615 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7779.c
@@ -1410,7 +1410,7 @@ static const u16 pinmux_data[] = {
1410 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1), 1410 PINMUX_IPSR_MODSEL_DATA(IP12_17_15, SCK4_B, SEL_SCIF4_1),
1411}; 1411};
1412 1412
1413static struct sh_pfc_pin pinmux_pins[] = { 1413static const struct sh_pfc_pin pinmux_pins[] = {
1414 PINMUX_GPIO_GP_ALL(), 1414 PINMUX_GPIO_GP_ALL(),
1415}; 1415};
1416 1416
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
index 293a51a7434e..a8ba2575a453 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7790.c
@@ -1731,7 +1731,7 @@ static const u16 pinmux_data[] = {
1731#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200) 1731#define PIN_NUMBER(r, c) (((r) - 'A') * 31 + (c) + 200)
1732#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c) 1732#define PIN_A_NUMBER(r, c) PIN_NUMBER(ROW_GROUP_A(r), c)
1733 1733
1734static struct sh_pfc_pin pinmux_pins[] = { 1734static const struct sh_pfc_pin pinmux_pins[] = {
1735 PINMUX_GPIO_GP_ALL(), 1735 PINMUX_GPIO_GP_ALL(),
1736 1736
1737 /* Pins not associated with a GPIO port */ 1737 /* Pins not associated with a GPIO port */
@@ -4237,7 +4237,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
4237 SH_PFC_FUNCTION(vin3), 4237 SH_PFC_FUNCTION(vin3),
4238}; 4238};
4239 4239
4240static struct pinmux_cfg_reg pinmux_config_regs[] = { 4240static const struct pinmux_cfg_reg pinmux_config_regs[] = {
4241 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 4241 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
4242 GP_0_31_FN, FN_IP3_17_15, 4242 GP_0_31_FN, FN_IP3_17_15,
4243 GP_0_30_FN, FN_IP3_14_12, 4243 GP_0_30_FN, FN_IP3_14_12,
diff --git a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
index ea02d37bab7c..d73a5f312777 100644
--- a/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
+++ b/drivers/pinctrl/sh-pfc/pfc-r8a7791.c
@@ -1674,7 +1674,7 @@ static const u16 pinmux_data[] = {
1674 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1), 1674 PINMUX_IPSR_MODSEL_DATA(IP16_11_10, CAN1_RX_B, SEL_CAN1_1),
1675}; 1675};
1676 1676
1677static struct sh_pfc_pin pinmux_pins[] = { 1677static const struct sh_pfc_pin pinmux_pins[] = {
1678 PINMUX_GPIO_GP_ALL(), 1678 PINMUX_GPIO_GP_ALL(),
1679}; 1679};
1680 1680
@@ -3056,7 +3056,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
3056 SH_PFC_FUNCTION(usb1), 3056 SH_PFC_FUNCTION(usb1),
3057}; 3057};
3058 3058
3059static struct pinmux_cfg_reg pinmux_config_regs[] = { 3059static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3060 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) { 3060 { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
3061 GP_0_31_FN, FN_IP1_22_20, 3061 GP_0_31_FN, FN_IP1_22_20,
3062 GP_0_30_FN, FN_IP1_19_17, 3062 GP_0_30_FN, FN_IP1_19_17,
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh7372.c b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
index bcdd5c3cdcf0..e9c522bfb3df 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh7372.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh7372.c
@@ -844,7 +844,7 @@ static const u16 pinmux_data[] = {
844#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O) 844#define SH7372_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
845#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD) 845#define SH7372_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
846 846
847static struct sh_pfc_pin pinmux_pins[] = { 847static const struct sh_pfc_pin pinmux_pins[] = {
848 /* Table 57-1 (I/O and Pull U/D) */ 848 /* Table 57-1 (I/O and Pull U/D) */
849 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1), 849 SH7372_PIN_IO_PD(0), SH7372_PIN_IO_PD(1),
850 SH7372_PIN_O(2), SH7372_PIN_I_PD(3), 850 SH7372_PIN_O(2), SH7372_PIN_I_PD(3),
diff --git a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
index dc7c7fb33805..6f6ba100994d 100644
--- a/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
+++ b/drivers/pinctrl/sh-pfc/pfc-sh73a0.c
@@ -1179,7 +1179,7 @@ static const u16 pinmux_data[] = {
1179 */ 1179 */
1180#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1) 1180#define PIN_NUMBER(row, col) (1000+((row)-1)*34+(col)-1)
1181 1181
1182static struct sh_pfc_pin pinmux_pins[] = { 1182static const struct sh_pfc_pin pinmux_pins[] = {
1183 /* Table 25-1 (I/O and Pull U/D) */ 1183 /* Table 25-1 (I/O and Pull U/D) */
1184 SH73A0_PIN_I_PD(0), 1184 SH73A0_PIN_I_PD(0),
1185 SH73A0_PIN_I_PU(1), 1185 SH73A0_PIN_I_PU(1),