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-rw-r--r--drivers/net/bnx2x/bnx2x.h15
-rw-r--r--drivers/net/bnx2x/bnx2x_main.c43
-rw-r--r--drivers/net/bnx2x/bnx2x_stats.c4
3 files changed, 36 insertions, 26 deletions
diff --git a/drivers/net/bnx2x/bnx2x.h b/drivers/net/bnx2x/bnx2x.h
index 85297326506c..2621a1c56358 100644
--- a/drivers/net/bnx2x/bnx2x.h
+++ b/drivers/net/bnx2x/bnx2x.h
@@ -1166,11 +1166,12 @@ struct bnx2x {
1166#define BP_PORT(bp) (bp->pfid & 1) 1166#define BP_PORT(bp) (bp->pfid & 1)
1167#define BP_FUNC(bp) (bp->pfid) 1167#define BP_FUNC(bp) (bp->pfid)
1168#define BP_ABS_FUNC(bp) (bp->pf_num) 1168#define BP_ABS_FUNC(bp) (bp->pf_num)
1169#define BP_E1HVN(bp) (bp->pfid >> 1) 1169#define BP_VN(bp) ((bp)->pfid >> 1)
1170#define BP_VN(bp) (BP_E1HVN(bp)) /*remove when approved*/ 1170#define BP_MAX_VN_NUM(bp) (CHIP_MODE_IS_4_PORT(bp) ? 2 : 4)
1171#define BP_L_ID(bp) (BP_E1HVN(bp) << 2) 1171#define BP_L_ID(bp) (BP_VN(bp) << 2)
1172#define BP_FW_MB_IDX(bp) (BP_PORT(bp) +\ 1172#define BP_FW_MB_IDX_VN(bp, vn) (BP_PORT(bp) +\
1173 BP_VN(bp) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1)) 1173 (vn) * ((CHIP_IS_E1x(bp) || (CHIP_MODE_IS_4_PORT(bp))) ? 2 : 1))
1174#define BP_FW_MB_IDX(bp) BP_FW_MB_IDX_VN(bp, BP_VN(bp))
1174 1175
1175 struct net_device *dev; 1176 struct net_device *dev;
1176 struct pci_dev *pdev; 1177 struct pci_dev *pdev;
@@ -1833,7 +1834,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1833 1834
1834#define MAX_DMAE_C_PER_PORT 8 1835#define MAX_DMAE_C_PER_PORT 8
1835#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1836#define INIT_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1836 BP_E1HVN(bp)) 1837 BP_VN(bp))
1837#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \ 1838#define PMF_DMAE_C(bp) (BP_PORT(bp) * MAX_DMAE_C_PER_PORT + \
1838 E1HVN_MAX) 1839 E1HVN_MAX)
1839 1840
@@ -1859,7 +1860,7 @@ static inline u32 reg_poll(struct bnx2x *bp, u32 reg, u32 expected, int ms,
1859 1860
1860/* must be used on a CID before placing it on a HW ring */ 1861/* must be used on a CID before placing it on a HW ring */
1861#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \ 1862#define HW_CID(bp, x) ((BP_PORT(bp) << 23) | \
1862 (BP_E1HVN(bp) << BNX2X_SWCID_SHIFT) | \ 1863 (BP_VN(bp) << BNX2X_SWCID_SHIFT) | \
1863 (x)) 1864 (x))
1864 1865
1865#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1866#define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
diff --git a/drivers/net/bnx2x/bnx2x_main.c b/drivers/net/bnx2x/bnx2x_main.c
index 3f93e8666104..9633e9b6853c 100644
--- a/drivers/net/bnx2x/bnx2x_main.c
+++ b/drivers/net/bnx2x/bnx2x_main.c
@@ -407,8 +407,8 @@ u32 bnx2x_dmae_opcode(struct bnx2x *bp, u8 src_type, u8 dst_type,
407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 407 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET);
408 408
409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 409 opcode |= (BP_PORT(bp) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
410 opcode |= ((BP_E1HVN(bp) << DMAE_CMD_E1HVN_SHIFT) | 410 opcode |= ((BP_VN(bp) << DMAE_CMD_E1HVN_SHIFT) |
411 (BP_E1HVN(bp) << DMAE_COMMAND_DST_VN_SHIFT)); 411 (BP_VN(bp) << DMAE_COMMAND_DST_VN_SHIFT));
412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 412 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT);
413 413
414#ifdef __BIG_ENDIAN 414#ifdef __BIG_ENDIAN
@@ -1419,7 +1419,7 @@ static void bnx2x_hc_int_enable(struct bnx2x *bp)
1419 if (!CHIP_IS_E1(bp)) { 1419 if (!CHIP_IS_E1(bp)) {
1420 /* init leading/trailing edge */ 1420 /* init leading/trailing edge */
1421 if (IS_MF(bp)) { 1421 if (IS_MF(bp)) {
1422 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); 1422 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1423 if (bp->port.pmf) 1423 if (bp->port.pmf)
1424 /* enable nig and gpio3 attention */ 1424 /* enable nig and gpio3 attention */
1425 val |= 0x1100; 1425 val |= 0x1100;
@@ -1471,7 +1471,7 @@ static void bnx2x_igu_int_enable(struct bnx2x *bp)
1471 1471
1472 /* init leading/trailing edge */ 1472 /* init leading/trailing edge */
1473 if (IS_MF(bp)) { 1473 if (IS_MF(bp)) {
1474 val = (0xee0f | (1 << (BP_E1HVN(bp) + 4))); 1474 val = (0xee0f | (1 << (BP_VN(bp) + 4)));
1475 if (bp->port.pmf) 1475 if (bp->port.pmf)
1476 /* enable nig and gpio3 attention */ 1476 /* enable nig and gpio3 attention */
1477 val |= 0x1100; 1477 val |= 0x1100;
@@ -2287,7 +2287,7 @@ static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2287 int vn; 2287 int vn;
2288 2288
2289 bp->vn_weight_sum = 0; 2289 bp->vn_weight_sum = 0;
2290 for (vn = VN_0; vn < E1HVN_MAX; vn++) { 2290 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2291 u32 vn_cfg = bp->mf_config[vn]; 2291 u32 vn_cfg = bp->mf_config[vn];
2292 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 2292 u32 vn_min_rate = ((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >>
2293 FUNC_MF_CFG_MIN_BW_SHIFT) * 100; 2293 FUNC_MF_CFG_MIN_BW_SHIFT) * 100;
@@ -2320,12 +2320,18 @@ static void bnx2x_calc_vn_weight_sum(struct bnx2x *bp)
2320 CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 2320 CMNG_FLAGS_PER_PORT_FAIRNESS_VN;
2321} 2321}
2322 2322
2323/* returns func by VN for current port */
2324static inline int func_by_vn(struct bnx2x *bp, int vn)
2325{
2326 return 2 * vn + BP_PORT(bp);
2327}
2328
2323static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn) 2329static void bnx2x_init_vn_minmax(struct bnx2x *bp, int vn)
2324{ 2330{
2325 struct rate_shaping_vars_per_vn m_rs_vn; 2331 struct rate_shaping_vars_per_vn m_rs_vn;
2326 struct fairness_vars_per_vn m_fair_vn; 2332 struct fairness_vars_per_vn m_fair_vn;
2327 u32 vn_cfg = bp->mf_config[vn]; 2333 u32 vn_cfg = bp->mf_config[vn];
2328 int func = 2*vn + BP_PORT(bp); 2334 int func = func_by_vn(bp, vn);
2329 u16 vn_min_rate, vn_max_rate; 2335 u16 vn_min_rate, vn_max_rate;
2330 int i; 2336 int i;
2331 2337
@@ -2422,7 +2428,7 @@ void bnx2x_read_mf_cfg(struct bnx2x *bp)
2422 * 2428 *
2423 * and there are 2 functions per port 2429 * and there are 2 functions per port
2424 */ 2430 */
2425 for (vn = VN_0; vn < E1HVN_MAX; vn++) { 2431 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2426 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp); 2432 int /*abs*/func = n * (2 * vn + BP_PORT(bp)) + BP_PATH(bp);
2427 2433
2428 if (func >= E1H_FUNC_MAX) 2434 if (func >= E1H_FUNC_MAX)
@@ -2454,7 +2460,7 @@ static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2454 2460
2455 /* calculate and set min-max rate for each vn */ 2461 /* calculate and set min-max rate for each vn */
2456 if (bp->port.pmf) 2462 if (bp->port.pmf)
2457 for (vn = VN_0; vn < E1HVN_MAX; vn++) 2463 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++)
2458 bnx2x_init_vn_minmax(bp, vn); 2464 bnx2x_init_vn_minmax(bp, vn);
2459 2465
2460 /* always enable rate shaping and fairness */ 2466 /* always enable rate shaping and fairness */
@@ -2473,16 +2479,15 @@ static void bnx2x_cmng_fns_init(struct bnx2x *bp, u8 read_cfg, u8 cmng_type)
2473 2479
2474static inline void bnx2x_link_sync_notify(struct bnx2x *bp) 2480static inline void bnx2x_link_sync_notify(struct bnx2x *bp)
2475{ 2481{
2476 int port = BP_PORT(bp);
2477 int func; 2482 int func;
2478 int vn; 2483 int vn;
2479 2484
2480 /* Set the attention towards other drivers on the same port */ 2485 /* Set the attention towards other drivers on the same port */
2481 for (vn = VN_0; vn < E1HVN_MAX; vn++) { 2486 for (vn = VN_0; vn < BP_MAX_VN_NUM(bp); vn++) {
2482 if (vn == BP_E1HVN(bp)) 2487 if (vn == BP_VN(bp))
2483 continue; 2488 continue;
2484 2489
2485 func = ((vn << 1) | port); 2490 func = func_by_vn(bp, vn);
2486 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 + 2491 REG_WR(bp, MISC_REG_AEU_GENERAL_ATTN_0 +
2487 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1); 2492 (LINK_SYNC_ATTENTION_BIT_FUNC_0 + func)*4, 1);
2488 } 2493 }
@@ -2577,7 +2582,7 @@ static void bnx2x_pmf_update(struct bnx2x *bp)
2577 bnx2x_dcbx_pmf_update(bp); 2582 bnx2x_dcbx_pmf_update(bp);
2578 2583
2579 /* enable nig attention */ 2584 /* enable nig attention */
2580 val = (0xff0f | (1 << (BP_E1HVN(bp) + 4))); 2585 val = (0xff0f | (1 << (BP_VN(bp) + 4)));
2581 if (bp->common.int_block == INT_BLOCK_HC) { 2586 if (bp->common.int_block == INT_BLOCK_HC) {
2582 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val); 2587 REG_WR(bp, HC_REG_TRAILING_EDGE_0 + port*8, val);
2583 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val); 2588 REG_WR(bp, HC_REG_LEADING_EDGE_0 + port*8, val);
@@ -6686,12 +6691,16 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
6686 if (CHIP_MODE_IS_4_PORT(bp)) 6691 if (CHIP_MODE_IS_4_PORT(bp))
6687 dsb_idx = BP_FUNC(bp); 6692 dsb_idx = BP_FUNC(bp);
6688 else 6693 else
6689 dsb_idx = BP_E1HVN(bp); 6694 dsb_idx = BP_VN(bp);
6690 6695
6691 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ? 6696 prod_offset = (CHIP_INT_MODE_IS_BC(bp) ?
6692 IGU_BC_BASE_DSB_PROD + dsb_idx : 6697 IGU_BC_BASE_DSB_PROD + dsb_idx :
6693 IGU_NORM_BASE_DSB_PROD + dsb_idx); 6698 IGU_NORM_BASE_DSB_PROD + dsb_idx);
6694 6699
6700 /*
6701 * igu prods come in chunks of E1HVN_MAX (4) -
6702 * does not matters what is the current chip mode
6703 */
6695 for (i = 0; i < (num_segs * E1HVN_MAX); 6704 for (i = 0; i < (num_segs * E1HVN_MAX);
6696 i += E1HVN_MAX) { 6705 i += E1HVN_MAX) {
6697 addr = IGU_REG_PROD_CONS_MEMORY + 6706 addr = IGU_REG_PROD_CONS_MEMORY +
@@ -7585,7 +7594,7 @@ u32 bnx2x_send_unload_req(struct bnx2x *bp, int unload_mode)
7585 u32 val; 7594 u32 val;
7586 /* The mac address is written to entries 1-4 to 7595 /* The mac address is written to entries 1-4 to
7587 preserve entry 0 which is used by the PMF */ 7596 preserve entry 0 which is used by the PMF */
7588 u8 entry = (BP_E1HVN(bp) + 1)*8; 7597 u8 entry = (BP_VN(bp) + 1)*8;
7589 7598
7590 val = (mac_addr[0] << 8) | mac_addr[1]; 7599 val = (mac_addr[0] << 8) | mac_addr[1];
7591 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val); 7600 EMAC_WR(bp, EMAC_REG_EMAC_MAC_MATCH + entry, val);
@@ -8792,13 +8801,13 @@ static void __devinit bnx2x_get_common_hwinfo(struct bnx2x *bp)
8792static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp) 8801static void __devinit bnx2x_get_igu_cam_info(struct bnx2x *bp)
8793{ 8802{
8794 int pfid = BP_FUNC(bp); 8803 int pfid = BP_FUNC(bp);
8795 int vn = BP_E1HVN(bp);
8796 int igu_sb_id; 8804 int igu_sb_id;
8797 u32 val; 8805 u32 val;
8798 u8 fid, igu_sb_cnt = 0; 8806 u8 fid, igu_sb_cnt = 0;
8799 8807
8800 bp->igu_base_sb = 0xff; 8808 bp->igu_base_sb = 0xff;
8801 if (CHIP_INT_MODE_IS_BC(bp)) { 8809 if (CHIP_INT_MODE_IS_BC(bp)) {
8810 int vn = BP_VN(bp);
8802 igu_sb_cnt = bp->igu_sb_cnt; 8811 igu_sb_cnt = bp->igu_sb_cnt;
8803 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) * 8812 bp->igu_base_sb = (CHIP_MODE_IS_4_PORT(bp) ? pfid : vn) *
8804 FP_SB_MAX_E1x; 8813 FP_SB_MAX_E1x;
@@ -9488,7 +9497,7 @@ static int __devinit bnx2x_get_hwinfo(struct bnx2x *bp)
9488 9497
9489 bp->mf_ov = 0; 9498 bp->mf_ov = 0;
9490 bp->mf_mode = 0; 9499 bp->mf_mode = 0;
9491 vn = BP_E1HVN(bp); 9500 vn = BP_VN(bp);
9492 9501
9493 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) { 9502 if (!CHIP_IS_E1(bp) && !BP_NOMCP(bp)) {
9494 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n", 9503 BNX2X_DEV_INFO("shmem2base 0x%x, size %d, mfcfg offset %d\n",
diff --git a/drivers/net/bnx2x/bnx2x_stats.c b/drivers/net/bnx2x/bnx2x_stats.c
index f5d9b4213cad..9908f2bbcf73 100644
--- a/drivers/net/bnx2x/bnx2x_stats.c
+++ b/drivers/net/bnx2x/bnx2x_stats.c
@@ -1392,7 +1392,7 @@ static void bnx2x_port_stats_base_init(struct bnx2x *bp)
1392 1392
1393static void bnx2x_func_stats_base_init(struct bnx2x *bp) 1393static void bnx2x_func_stats_base_init(struct bnx2x *bp)
1394{ 1394{
1395 int vn, vn_max = IS_MF(bp) ? E1HVN_MAX : E1VN_MAX; 1395 int vn, vn_max = IS_MF(bp) ? BP_MAX_VN_NUM(bp) : E1VN_MAX;
1396 u32 func_stx; 1396 u32 func_stx;
1397 1397
1398 /* sanity */ 1398 /* sanity */
@@ -1405,7 +1405,7 @@ static void bnx2x_func_stats_base_init(struct bnx2x *bp)
1405 func_stx = bp->func_stx; 1405 func_stx = bp->func_stx;
1406 1406
1407 for (vn = VN_0; vn < vn_max; vn++) { 1407 for (vn = VN_0; vn < vn_max; vn++) {
1408 int mb_idx = CHIP_IS_E1x(bp) ? 2*vn + BP_PORT(bp) : vn; 1408 int mb_idx = BP_FW_MB_IDX_VN(bp, vn);
1409 1409
1410 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param); 1410 bp->func_stx = SHMEM_RD(bp, func_mb[mb_idx].fw_mb_param);
1411 bnx2x_func_stats_init(bp); 1411 bnx2x_func_stats_init(bp);